HDAStream.cpp@ 88158

Last change on this file since 88158 was 88158, checked in by vboxsync, 4 years ago
DevHDA: Restructured the input DMA code, getting rid of the FIFO bounce buffering and adding a silence pre-buffering period at the start of the stream (till we get a bit of data from the host device). bugref:9890
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File size: 114.1 KB

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1	/* $Id: HDAStream.cpp 88158 2021-03-17 14:39:22Z vboxsync $ */
2	/** @file
3	* HDAStream.cpp - Stream functions for HD Audio.
4	*/
5
6	/*
7	* Copyright (C) 2017-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_HDA
23	#include <VBox/log.h>
24
25	#include <iprt/mem.h>
26	#include <iprt/semaphore.h>
27
28	#include <VBox/AssertGuest.h>
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/vmm/pdmaudioinline.h>
32
33	#include "DrvAudio.h"
34
35	#include "DevHDA.h"
36	#include "HDAStream.h"
37
38	#ifdef VBOX_WITH_DTRACE
39	# include "dtrace/VBoxDD.h"
40	#endif
41
42	#ifdef IN_RING3 /* whole file */
43
44
45	/*********************************************************************************************************************************
46	* Internal Functions *
47	*********************************************************************************************************************************/
48	static void hdaR3StreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
49
50	static int hdaR3StreamAsyncIODestroy(PHDASTREAMR3 pStreamR3);
51
52
53
54	/**
55	* Creates an HDA stream.
56	*
57	* @returns IPRT status code.
58	* @param pStreamShared The HDA stream to construct - shared bits.
59	* @param pStreamR3 The HDA stream to construct - ring-3 bits.
60	* @param pThis The shared HDA device instance.
61	* @param pThisCC The ring-3 HDA device instance.
62	* @param uSD Stream descriptor number to assign.
63	*/
64	int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
65	{
66	int rc;
67
68	pStreamR3->u8SD = uSD;
69	pStreamShared->u8SD = uSD;
70	pStreamR3->pMixSink = NULL;
71	pStreamR3->pHDAStateShared = pThis;
72	pStreamR3->pHDAStateR3 = pThisCC;
73	Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
74
75	pStreamShared->State.fInReset = false;
76	pStreamShared->State.fRunning = false;
77	#ifdef HDA_USE_DMA_ACCESS_HANDLER
78	RTListInit(&pStreamR3->State.lstDMAHandlers);
79	#endif
80
81	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
82	AssertPtr(pStreamR3->pHDAStateR3);
83	AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
84	rc = PDMDevHlpCritSectInit(pStreamR3->pHDAStateR3->pDevIns, &pStreamShared->CritSect,
85	RT_SRC_POS, "hda_sd#%RU8", pStreamShared->u8SD);
86	AssertRCReturn(rc, rc);
87	#endif
88
89	rc = hdaR3StreamPeriodCreate(&pStreamShared->State.Period);
90	AssertRCReturn(rc, rc);
91
92	#ifdef DEBUG
93	rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
94	AssertRCReturn(rc, rc);
95	#endif
96
97	const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
98
99	if (fIsInput)
100	{
101	pStreamShared->State.Cfg.u.enmSrc = PDMAUDIORECSRC_UNKNOWN;
102	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
103	}
104	else
105	{
106	pStreamShared->State.Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_UNKNOWN;
107	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
108	}
109
110	pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
111
112	if (pStreamR3->Dbg.Runtime.fEnabled)
113	{
114	char szFile[64];
115	char szPath[RTPATH_MAX];
116
117	/* pFileStream */
118	if (fIsInput)
119	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
120	else
121	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
122
123	int rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
124	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
125	AssertRC(rc2);
126
127	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
128	AssertRC(rc2);
129
130	/* pFileDMARaw */
131	if (fIsInput)
132	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
133	else
134	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
135
136	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
137	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
138	AssertRC(rc2);
139
140	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
141	AssertRC(rc2);
142
143	/* pFileDMAMapped */
144	if (fIsInput)
145	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
146	else
147	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
148
149	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
150	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
151	AssertRC(rc2);
152
153	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
154	AssertRC(rc2);
155
156	/* Delete stale debugging files from a former run. */
157	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
158	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
159	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
160	}
161
162	return rc;
163	}
164
165	/**
166	* Destroys an HDA stream.
167	*
168	* @param pStreamShared The HDA stream to destroy - shared bits.
169	* @param pStreamR3 The HDA stream to destroy - ring-3 bits.
170	*/
171	void hdaR3StreamDestroy(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
172	{
173	LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamShared->u8SD));
174
175	hdaR3StreamMapDestroy(&pStreamR3->State.Mapping);
176
177	int rc2;
178
179	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
180	rc2 = hdaR3StreamAsyncIODestroy(pStreamR3);
181	AssertRC(rc2);
182	#endif
183
184	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
185	if (PDMCritSectIsInitialized(&pStreamShared->CritSect))
186	{
187	rc2 = PDMR3CritSectDelete(&pStreamShared->CritSect);
188	AssertRC(rc2);
189	}
190	#endif
191
192	if (pStreamR3->State.pCircBuf)
193	{
194	RTCircBufDestroy(pStreamR3->State.pCircBuf);
195	pStreamR3->State.pCircBuf = NULL;
196	}
197
198	hdaR3StreamPeriodDestroy(&pStreamShared->State.Period);
199
200	#ifdef DEBUG
201	if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
202	{
203	rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
204	AssertRC(rc2);
205	}
206	#endif
207
208	if (pStreamR3->Dbg.Runtime.fEnabled)
209	{
210	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
211	pStreamR3->Dbg.Runtime.pFileStream = NULL;
212
213	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
214	pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
215
216	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
217	pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
218	}
219
220	LogFlowFuncLeave();
221	}
222
223
224	/**
225	* Appends a item to the scheduler.
226	*
227	* @returns VBox status code.
228	* @param pStreamShared The stream which scheduler should be modified.
229	* @param cbCur The period length in guest bytes.
230	* @param cbMaxPeriod The max period in guest bytes.
231	* @param idxLastBdle The last BDLE in the period.
232	* @param pHostProps The host PCM properties.
233	* @param pGuestProps The guest PCM properties.
234	* @param pcbBorrow Where to account for bytes borrowed across buffers
235	* to align scheduling items on frame boundraries.
236	*/
237	static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod, uint32_t idxLastBdle,
238	PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps, uint32_t *pcbBorrow)
239	{
240	/* Check that we've got room (shouldn't ever be a problem). */
241	size_t idx = pStreamShared->State.cSchedule;
242	AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
243
244	/* Figure out the BDLE range for this period. */
245	uint32_t const idxFirstBdle = idx == 0 ? 0
246	: pStreamShared->State.aSchedule[idx - 1].idxFirst
247	+ pStreamShared->State.aSchedule[idx - 1].cEntries;
248
249	pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
250	pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
251	? idxLastBdle - idxFirstBdle + 1
252	: pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
253
254	/* Deal with borrowing due to unaligned IOC buffers. */
255	uint32_t const cbBorrowed = *pcbBorrow;
256	if (cbBorrowed < cbCur)
257	cbCur -= cbBorrowed;
258	else
259	{
260	/* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
261	ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
262	pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
263	LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
264	pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
265	return VERR_OUT_OF_RANGE;
266	}
267
268	uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbCur);
269	*pcbBorrow = cbCurAligned - cbCur;
270
271	/* Do we need to split up the period? */
272	if (cbCurAligned <= cbMaxPeriod)
273	{
274	uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
275	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
276	pStreamShared->State.aSchedule[idx].cLoops = 1;
277	}
278	else
279	{
280	/* Reduce till we've below the threshold. */
281	uint32_t cbLoop = cbCurAligned;
282	do
283	cbLoop = cbCurAligned / 2;
284	while (cbLoop > cbMaxPeriod);
285	cbLoop = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbLoop);
286
287	/* Complete the scheduling item. */
288	uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbLoop));
289	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
290	pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
291
292	/* If there is a remainder, add it as a separate entry (this is
293	why the schedule must be more than twice the size of the BDL).*/
294	cbCurAligned %= cbLoop;
295	if (cbCurAligned)
296	{
297	pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
298	idx++;
299	cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
300	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
301	pStreamShared->State.aSchedule[idx].cLoops = 1;
302	}
303	}
304
305	/* Done. */
306	pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
307
308	return VINF_SUCCESS;
309	}
310
311	/**
312	* Creates the DMA timer schedule for the stream
313	*
314	* This is called from the stream setup code.
315	*
316	* @returns VBox status code.
317	* @param pStreamShared The stream to create a schedule for. The BDL
318	* must be loaded.
319	* @param cSegments Number of BDL segments.
320	* @param cBufferIrqs Number of the BDLEs with IOC=1.
321	* @param cbTotal The total BDL length in guest bytes.
322	* @param cbMaxPeriod Max period in guest bytes. This is in case the
323	* guest want to play the whole "Der Ring des
324	* Nibelungen" cycle in one go.
325	* @param cTimerTicksPerSec The DMA timer frequency.
326	* @param pHostProps The host PCM properties.
327	* @param pGuestProps The guest PCM properties.
328	*/
329	static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
330	uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec,
331	PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps)
332	{
333	int rc;
334
335	/*
336	* Reset scheduling state.
337	*/
338	RT_ZERO(pStreamShared->State.aSchedule);
339	pStreamShared->State.cSchedule = 0;
340	pStreamShared->State.cSchedulePrologue = 0;
341	pStreamShared->State.idxSchedule = 0;
342	pStreamShared->State.idxScheduleLoop = 0;
343
344	/*
345	* Do the basic schedule compilation.
346	*/
347	uint32_t cPotentialPrologue = 0;
348	uint32_t cbBorrow = 0;
349	uint32_t cbCur = 0;
350	pStreamShared->State.aSchedule[0].idxFirst = 0;
351	for (uint32_t i = 0; i < cSegments; i++)
352	{
353	cbCur += pStreamShared->State.aBdl[i].cb;
354	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
355	{
356	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
357	ASSERT_GUEST_RC_RETURN(rc, rc);
358
359	if (cPotentialPrologue == 0)
360	cPotentialPrologue = pStreamShared->State.cSchedule;
361	cbCur = 0;
362	}
363	}
364	AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
365	pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
366	VERR_INTERNAL_ERROR_3);
367
368	/*
369	* Deal with any loose ends.
370	*/
371	if (cbCur && cBufferIrqs == 0)
372	{
373	/* No IOC. Split the period in two. */
374	Assert(cbCur == cbTotal);
375	cbCur = PDMAudioPropsFloorBytesToFrame(pGuestProps, cbCur / 2);
376	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, cSegments, pHostProps, pGuestProps, &cbBorrow);
377	ASSERT_GUEST_RC_RETURN(rc, rc);
378
379	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbTotal - cbCur, cbMaxPeriod, cSegments,
380	pHostProps, pGuestProps, &cbBorrow);
381	ASSERT_GUEST_RC_RETURN(rc, rc);
382	Assert(cbBorrow == 0);
383	}
384	else if (cbCur)
385	{
386	/* The last BDLE didn't have IOC set, so we must continue processing
387	from the start till we hit one that has. */
388	uint32_t i;
389	for (i = 0; i < cSegments; i++)
390	{
391	cbCur += pStreamShared->State.aBdl[i].cb;
392	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
393	break;
394	}
395	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
396	ASSERT_GUEST_RC_RETURN(rc, rc);
397
398	/* The initial scheduling items covering the wrap around area are
399	considered a prologue and must not repeated later. */
400	Assert(cPotentialPrologue);
401	pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
402	}
403
404	/*
405	* If there is just one BDLE with IOC set, we have to make sure
406	* we've got at least two periods scheduled, otherwise there is
407	* a very good chance the guest will overwrite the start of the
408	* buffer before we ever get around to reading it.
409	*/
410	if (cBufferIrqs == 1)
411	{
412	uint32_t i = pStreamShared->State.cSchedulePrologue;
413	Assert(i < pStreamShared->State.cSchedule);
414	if ( i + 1 == pStreamShared->State.cSchedule
415	&& pStreamShared->State.aSchedule[i].cLoops == 1)
416	{
417	uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pHostProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
418	uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
419	pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
420	if (cbFirstHalf == cbOtherHalf)
421	pStreamShared->State.aSchedule[i].cLoops = 2;
422	else
423	{
424	pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
425	pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
426	pStreamShared->State.cSchedule++;
427	}
428	}
429	}
430
431	/*
432	* Go over the schduling entries and calculate the timer ticks for each period.
433	*/
434	LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
435	pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
436	uint64_t const cbHostPerSec = PDMAudioPropsFramesToBytes(pHostProps, pHostProps->uHz);
437	for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
438	{
439	uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod,
440	cbHostPerSec);
441	AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
442	pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
443	LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
444	pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
445	pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
446	}
447
448	return VINF_SUCCESS;
449	}
450
451
452	/**
453	* Sets up ((re-)iniitalizes) an HDA stream.
454	*
455	* @returns IPRT status code. VINF_NO_CHANGE if the stream does not need
456	* be set-up again because the stream's (hardware) parameters did
457	* not change.
458	* @param pDevIns The device instance.
459	* @param pThis The shared HDA device state (for HW register
460	* parameters).
461	* @param pStreamShared HDA stream to set up, shared portion.
462	* @param pStreamR3 HDA stream to set up, ring-3 portion.
463	* @param uSD Stream descriptor number to assign it.
464	*/
465	int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
466	{
467	/* This must be valid all times. */
468	AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
469
470	/* These member can only change on data corruption, despite what the code does further down (bird). */
471	AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
472	AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
473
474	const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
475	HDA_STREAM_REG(pThis, BDPU, uSD));
476	const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
477	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
478	const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
479	uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
480	const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
481
482	/* Is the bare minimum set of registers configured for the stream?
483	* If not, bail out early, as there's nothing to do here for us (yet). */
484	if ( !u64BDLBase
485	\|\| !u16LVI
486	\|\| !u32CBL
487	\|\| !u8FIFOS
488	\|\| !u8FIFOW
489	\|\| !u16FMT)
490	{
491	LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
492	return VINF_SUCCESS;
493	}
494
495	PDMAUDIOPCMPROPS HostProps;
496	int rc = hdaR3SDFMTToPCMProps(u16FMT, &HostProps);
497	if (RT_FAILURE(rc))
498	{
499	LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
500	return rc;
501	}
502
503	/*
504	* Initialize the stream mapping in any case, regardless if
505	* we support surround audio or not. This is needed to handle
506	* the supported channels within a single audio stream, e.g. mono/stereo.
507	*
508	* In other words, the stream mapping always knows the real
509	* number of channels in a single audio stream.
510	*/
511	/** @todo r=bird: this is not done at the wrong time. We don't have the host
512	* output side set up yet, so we cannot really do proper mapping setup.
513	* However, we really need this further down when we configure the internal DMA
514	* buffer size. For now we just assume it's all stereo on the host side.
515	* This is not compatible with microphone support. */
516	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
517	# error "Implement me!"
518	# endif
519	rc = hdaR3StreamMapInit(&pStreamR3->State.Mapping, 2 /cHostChannels/, &HostProps);
520	AssertRCReturn(rc, rc);
521
522	ASSERT_GUEST_LOGREL_MSG_RETURN( pStreamR3->State.Mapping.cbGuestFrame > 0
523	&& u32CBL % pStreamR3->State.Mapping.cbGuestFrame == 0,
524	("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
525	uSD, u32CBL, pStreamR3->State.Mapping.cbGuestFrame),
526	VERR_INVALID_PARAMETER);
527
528	/* Make sure the guest behaves regarding the stream's FIFO. */
529	ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
530	("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
531	u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
532
533	pStreamShared->u8SD = uSD;
534
535	/* Update all register copies so that we later know that something has changed. */
536	pStreamShared->u64BDLBase = u64BDLBase;
537	pStreamShared->u16LVI = u16LVI;
538	pStreamShared->u32CBL = u32CBL;
539	pStreamShared->u8FIFOS = u8FIFOS;
540	pStreamShared->u8FIFOW = u8FIFOW;
541	pStreamShared->u16FMT = u16FMT;
542
543	PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
544	pCfg->Props = HostProps;
545
546	/* Set the stream's direction. */
547	pCfg->enmDir = hdaGetDirFromSD(uSD);
548
549	/* The the stream's name, based on the direction. */
550	switch (pCfg->enmDir)
551	{
552	case PDMAUDIODIR_IN:
553	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
554	# error "Implement me!"
555	# else
556	pCfg->u.enmSrc = PDMAUDIORECSRC_LINE;
557	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
558	RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
559	# endif
560	break;
561
562	case PDMAUDIODIR_OUT:
563	/* Destination(s) will be set in hdaR3AddStreamOut(),
564	* based on the channels / stream layout. */
565	break;
566
567	default:
568	AssertFailedReturn(VERR_NOT_SUPPORTED);
569	break;
570	}
571
572	LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n",
573	uSD, pStreamShared->u64BDLBase, pStreamShared->u32CBL,
574	PDMAudioPropsBytesToMilli(&pStreamR3->State.Mapping.GuestProps, pStreamShared->u32CBL)));
575
576
577	/*
578	* Load the buffer descriptor list.
579	*
580	* Section 3.6.2 states that "the BDL should not be modified unless the RUN
581	* bit is 0", so it should be within the specs to read it once here and not
582	* re-read any BDLEs later.
583	*/
584	/* Reset BDL state. */
585	RT_ZERO(pStreamShared->State.aBdl);
586	pStreamShared->State.offCurBdle = 0;
587	pStreamShared->State.idxCurBdle = 0;
588
589	uint32_t /const/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
590	if (cTransferFragments <= 1)
591	LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
592	AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
593	pStreamShared->State.cBdles = cTransferFragments;
594
595	/* Load them. */
596	rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
597	sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
598	AssertRC(rc);
599
600	/* Check what we just loaded. Refuse overly large buffer lists. */
601	uint64_t cbTotal = 0;
602	uint32_t cBufferIrqs = 0;
603	for (uint32_t i = 0; i < cTransferFragments; i++)
604	{
605	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
606	cBufferIrqs++;
607	cbTotal += pStreamShared->State.aBdl[i].cb;
608	}
609	ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
610	LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
611	uSD, cbTotal, cbTotal)),
612	VERR_NOT_SUPPORTED);
613	ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
614	LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
615	uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
616	VERR_NOT_SUPPORTED);
617
618	/*
619	* Create a DMA timer schedule.
620	*/
621	rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
622	PDMAudioPropsMilliToBytes(&pStreamR3->State.Mapping.GuestProps, 100 /** @todo make configurable */),
623	PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer),
624	&HostProps, &pStreamR3->State.Mapping.GuestProps);
625	if (RT_FAILURE(rc))
626	return rc;
627
628	pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[0].cbPeriod;
629
630	/*
631	* Calculate the transfer Hz for use in the circular buffer calculation.
632	*/
633	uint32_t cbMaxPeriod = 0;
634	uint32_t cbMinPeriod = UINT32_MAX;
635	uint32_t cPeriods = 0;
636	for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
637	{
638	uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
639	cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
640	cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
641	cPeriods += pStreamShared->State.aSchedule[i].cLoops;
642	}
643	uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
644	4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
645	unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
646	LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
647	uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
648	uTransferHz /= 1000;
649
650	if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
651	LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
652	uSD, uTransferHz));
653
654	pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
655
656	/* For input streams we must determin a pre-buffering requirement.
657	We use the initial delay as a basis here, though we must have at
658	least two max periods worth of data queued up due to the way we
659	work the AIO thread. */
660	pStreamShared->State.fInputPreBuffered = false;
661	pStreamShared->State.cbInputPreBuffer = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay);
662	pStreamShared->State.cbInputPreBuffer = RT_MIN(cbMaxPeriod * 2, pStreamShared->State.cbInputPreBuffer);
663
664	/*
665	* Set up data transfer stuff.
666	*/
667
668	/* Assign the global device rate to the stream I/O timer as default. */
669	pStreamShared->State.uTimerIoHz = pThis->uTimerHz;
670	ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.uTimerIoHz,
671	("I/O timer Hz rate for stream #%RU8 is invalid\n", uSD),
672	pStreamShared->State.uTimerIoHz = HDA_TIMER_HZ_DEFAULT);
673
674	/* Set I/O scheduling hint for the backends. */
675	/** @todo r=bird: This is in the 'Device' portion, yet it's used by the
676	* audio driver. You would think stuff in the 'Device' part is
677	* private to the device. */
678	pCfg->Device.cMsSchedulingHint = RT_MS_1SEC / pStreamShared->State.uTimerIoHz;
679	LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
680
681
682	/* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
683	hdaR3StreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
684
685	#ifdef LOG_ENABLED
686	hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
687	#endif
688
689	/*
690	* Set up internal ring buffer.
691	*/
692
693	/* (Re-)Allocate the stream's internal DMA buffer,
694	* based on the timing and PCM properties we just got above. */
695	if (pStreamR3->State.pCircBuf)
696	{
697	RTCircBufDestroy(pStreamR3->State.pCircBuf);
698	pStreamR3->State.pCircBuf = NULL;
699	}
700	pStreamR3->State.offWrite = 0;
701	pStreamR3->State.offRead = 0;
702
703	/*
704	* The default internal ring buffer size must be:
705	*
706	* - Large enough for at least three periodic DMA transfers.
707	*
708	* It is critically important that we don't experience underruns
709	* in the DMA OUT code, because it will cause the buffer processing
710	* to get skewed and possibly overlap with what the guest is updating.
711	* At the time of writing (2021-03-05) there is no code for getting
712	* back into sync there.
713	*
714	* - Large enough for at least three I/O scheduling hints.
715	*
716	* We want to lag behind a DMA period or two, but there must be
717	* sufficent space for the AIO thread to get schedule and shuffle
718	* data thru the mixer and onto the host audio hardware.
719	*
720	* - Both above with plenty to spare.
721	*
722	* So, just take the longest of the two periods and multipling it by 6.
723	* We aren't not talking about very large base buffers heres, so size isn't
724	* an issue.
725	*
726	* Note: Use pCfg->Props as PCM properties here, as we only want to store the
727	* samples we actually need, in other words, skipping the interleaved
728	* channels we don't support / need to save space.
729	*/
730	uint32_t msCircBuf = RT_MS_1SEC * 6 / RT_MIN(uTransferHz, pStreamShared->State.uTimerIoHz);
731	msCircBuf = RT_MAX(msCircBuf, pThis->msInitialDelay + RT_MS_1SEC * 6 / uTransferHz);
732
733	uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBuf);
734	LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
735	uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
736
737	uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cbCircBufInMs : pThis->cbCircBufOutMs;
738	if (msCircBufCfg) /* Anything set via CFGM? */
739	{
740	cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
741	LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
742	uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
743	}
744
745	/* Serious paranoia: */
746	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % (pCfg->Props.cbSample * pCfg->Props.cChannels) == 0,
747	("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
748	cbCircBuf, uSD, pCfg->Props.cbSample * pCfg->Props.cChannels),
749	rc = VERR_INVALID_PARAMETER);
750	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
751	rc = VERR_INVALID_PARAMETER);
752	if (RT_SUCCESS(rc))
753	{
754	rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
755	if (RT_SUCCESS(rc))
756	{
757	/*
758	* Forward the timer frequency hint to TM as well for better accuracy on
759	* systems w/o preemption timers (also good for 'info timers').
760	*/
761	PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
762	}
763	}
764
765	if (RT_FAILURE(rc))
766	LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
767
768	#ifdef VBOX_WITH_DTRACE
769	VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
770	pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
771	pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
772	#endif
773	return rc;
774	}
775
776	/**
777	* Resets an HDA stream.
778	*
779	* @param pThis The shared HDA device state.
780	* @param pThisCC The ring-3 HDA device state.
781	* @param pStreamShared HDA stream to reset (shared).
782	* @param pStreamR3 HDA stream to reset (ring-3).
783	* @param uSD Stream descriptor (SD) number to use for this stream.
784	*/
785	void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
786	{
787	AssertPtr(pThis);
788	AssertPtr(pStreamShared);
789	AssertPtr(pStreamR3);
790	Assert(uSD < HDA_MAX_STREAMS);
791	AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
792
793	LogFunc(("[SD%RU8] Reset\n", uSD));
794
795	/*
796	* Set reset state.
797	*/
798	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
799	ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
800
801	/*
802	* Second, initialize the registers.
803	*/
804	/* See 6.2.33: Clear on reset. */
805	HDA_STREAM_REG(pThis, STS, uSD) = 0;
806	/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
807	* bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
808	HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 \| (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
809	/* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
810	HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
811	/* See 18.2.38: Always defaults to 0x4 (32 bytes). */
812	HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
813	HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
814	HDA_STREAM_REG(pThis, CBL, uSD) = 0;
815	HDA_STREAM_REG(pThis, LVI, uSD) = 0;
816	HDA_STREAM_REG(pThis, FMT, uSD) = 0;
817	HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
818	HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
819
820	#ifdef HDA_USE_DMA_ACCESS_HANDLER
821	hdaR3StreamUnregisterDMAHandlers(pThis, pStream);
822	#endif
823
824	/* Assign the default mixer sink to the stream. */
825	pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
826
827	/* Reset transfer stuff. */
828	pStreamShared->State.cTransferPendingInterrupts = 0;
829	pStreamShared->State.tsTransferLast = 0;
830	pStreamShared->State.tsTransferNext = 0;
831
832	/* Initialize timestamps. */
833	pStreamShared->State.tsLastTransferNs = 0;
834	pStreamShared->State.tsLastReadNs = 0;
835	pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
836	pStreamShared->State.tsStart = 0;
837
838	RT_ZERO(pStreamShared->State.aBdl);
839	RT_ZERO(pStreamShared->State.aSchedule);
840	pStreamShared->State.offCurBdle = 0;
841	pStreamShared->State.cBdles = 0;
842	pStreamShared->State.idxCurBdle = 0;
843	pStreamShared->State.cSchedulePrologue = 0;
844	pStreamShared->State.cSchedule = 0;
845	pStreamShared->State.idxSchedule = 0;
846	pStreamShared->State.idxScheduleLoop = 0;
847	pStreamShared->State.fInputPreBuffered = false;
848
849	if (pStreamR3->State.pCircBuf)
850	RTCircBufReset(pStreamR3->State.pCircBuf);
851	pStreamR3->State.offWrite = 0;
852	pStreamR3->State.offRead = 0;
853
854	/* Reset the stream's period. */
855	hdaR3StreamPeriodReset(&pStreamShared->State.Period);
856
857	#ifdef DEBUG
858	pStreamR3->Dbg.cReadsTotal = 0;
859	pStreamR3->Dbg.cbReadTotal = 0;
860	pStreamR3->Dbg.tsLastReadNs = 0;
861	pStreamR3->Dbg.cWritesTotal = 0;
862	pStreamR3->Dbg.cbWrittenTotal = 0;
863	pStreamR3->Dbg.cWritesHz = 0;
864	pStreamR3->Dbg.cbWrittenHz = 0;
865	pStreamR3->Dbg.tsWriteSlotBegin = 0;
866	#endif
867
868	/* Report that we're done resetting this stream. */
869	HDA_STREAM_REG(pThis, CTL, uSD) = 0;
870
871	#ifdef VBOX_WITH_DTRACE
872	VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
873	#endif
874	LogFunc(("[SD%RU8] Reset\n", uSD));
875
876	/* Exit reset mode. */
877	ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
878	}
879
880	/**
881	* Enables or disables an HDA audio stream.
882	*
883	* @returns IPRT status code.
884	* @param pStreamShared HDA stream to enable or disable - shared bits.
885	* @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
886	* @param fEnable Whether to enable or disble the stream.
887	*/
888	int hdaR3StreamEnable(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
889	{
890	AssertPtr(pStreamR3);
891	AssertPtr(pStreamShared);
892
893	LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
894
895	int rc = VINF_SUCCESS;
896
897	AUDMIXSINKCMD enmCmd = fEnable
898	? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
899
900	/* First, enable or disable the stream and the stream's sink, if any. */
901	if ( pStreamR3->pMixSink
902	&& pStreamR3->pMixSink->pMixSink)
903	rc = AudioMixerSinkCtl(pStreamR3->pMixSink->pMixSink, enmCmd);
904
905	if ( RT_SUCCESS(rc)
906	&& fEnable
907	&& pStreamR3->Dbg.Runtime.fEnabled)
908	{
909	Assert(DrvAudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
910
911	if (fEnable)
912	{
913	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
914	{
915	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
916	&pStreamShared->State.Cfg.Props);
917	AssertRC(rc2);
918	}
919
920	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
921	{
922	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
923	&pStreamShared->State.Cfg.Props);
924	AssertRC(rc2);
925	}
926
927	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
928	{
929	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
930	&pStreamShared->State.Cfg.Props);
931	AssertRC(rc2);
932	}
933	}
934	}
935
936	if (RT_SUCCESS(rc))
937	{
938	pStreamShared->State.fRunning = fEnable;
939	}
940
941	LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
942	return rc;
943	}
944
945	/**
946	* Marks the stream as started.
947	*
948	* Used after the stream has been enabled and the DMA timer has been armed.
949	*/
950	void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
951	{
952	pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
953	pStreamShared->State.tsStart = tsNow;
954	pStreamShared->State.tsAioDelayEnd = tsNow + PDMDevHlpTimerFromMilli(pDevIns, pStreamShared->hTimer, pThis->msInitialDelay);
955	Log3Func(("#%u: tsStart=%RU64 tsAioDelayEnd=%RU64 tsLastReadNs=%RU64\n", pStreamShared->u8SD,
956	pStreamShared->State.tsStart, pStreamShared->State.tsAioDelayEnd, pStreamShared->State.tsLastReadNs));
957
958	}
959
960	/**
961	* Marks the stream as stopped.
962	*/
963	void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
964	{
965	Log3Func(("#%u\n", pStreamShared->u8SD));
966	pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
967	}
968
969
970	#if 0 /* Not used atm. */
971	static uint32_t hdaR3StreamGetPosition(PHDASTATE pThis, PHDASTREAM pStreamShared)
972	{
973	return HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD);
974	}
975	#endif
976
977	/**
978	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
979	* setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
980	*
981	* @param pStreamShared HDA stream to update read / write position for (shared).
982	* @param pDevIns The device instance.
983	* @param pThis The shared HDA device state.
984	* @param uLPIB Absolute position (in bytes) to set current read / write position to.
985	*/
986	static void hdaR3StreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
987	{
988	AssertPtrReturnVoid(pStreamShared);
989	AssertReturnVoid (uLPIB <= pStreamShared->u32CBL); /* Make sure that we don't go out-of-bounds. */
990
991	Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
992
993	/* Update LPIB in any case. */
994	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
995
996	/* Do we need to tell the current DMA position? */
997	if (pThis->fDMAPosition)
998	{
999	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1000	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1001	(void *)&uLPIB, sizeof(uint32_t));
1002	AssertRC(rc2);
1003	}
1004	}
1005
1006	/**
1007	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1008	* adding a value to its associated LPIB register and DMA position buffer (if enabled).
1009	*
1010	* @note Handles automatic CBL wrap-around.
1011	*
1012	* @param pStreamShared HDA stream to update read / write position for (shared).
1013	* @param pDevIns The device instance.
1014	* @param pThis The shared HDA device state.
1015	* @param cbToAdd Position (in bytes) to add to the current read / write position.
1016	*/
1017	void hdaR3StreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1018	{
1019	if (cbToAdd) /* No need to update anything if 0. */
1020	{
1021	uint32_t const uCBL = pStreamShared->u32CBL;
1022	if (uCBL) /* paranoia */
1023	hdaR3StreamSetPositionAbs(pStreamShared, pDevIns, pThis,
1024	(HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd) % uCBL);
1025	}
1026	}
1027
1028	/**
1029	* Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1030	*
1031	* @returns Available data (in bytes).
1032	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
1033	*/
1034	static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1035	{
1036	AssertPtrReturn(pStreamR3, 0);
1037
1038	if (pStreamR3->State.pCircBuf)
1039	return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1040	return 0;
1041	}
1042
1043	/**
1044	* Retrieves the free size of audio data (in bytes) of a given HDA stream.
1045	*
1046	* @returns Free data (in bytes).
1047	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
1048	*/
1049	static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1050	{
1051	AssertPtrReturn(pStreamR3, 0);
1052
1053	if (pStreamR3->State.pCircBuf)
1054	return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1055	return 0;
1056	}
1057
1058	/**
1059	* Reads audio data from an HDA stream's DMA buffer and writes into a specified mixer sink.
1060	*
1061	* @returns IPRT status code.
1062	* @param pStreamR3 HDA stream to read audio data from (ring-3).
1063	* @param cbToRead Number of bytes to read.
1064	* @param pcbRead Number of bytes read. Optional.
1065	*/
1066	static int hdaR3StreamRead(PHDASTREAMR3 pStreamR3, uint32_t cbToRead, uint32_t *pcbRead)
1067	{
1068	Assert(cbToRead);
1069
1070	PHDAMIXERSINK pSink = pStreamR3->pMixSink;
1071	AssertMsgReturnStmt(pSink, ("[SD%RU8] Can't read from a stream with no sink attached\n", pStreamR3->u8SD),
1072	if (pcbRead) *pcbRead = 0,
1073	VINF_SUCCESS);
1074
1075	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1076	AssertPtr(pCircBuf);
1077
1078	int rc = VINF_SUCCESS;
1079
1080	uint32_t cbReadTotal = 0;
1081	uint32_t cbLeft = RT_MIN(cbToRead, (uint32_t)RTCircBufUsed(pCircBuf));
1082
1083	while (cbLeft)
1084	{
1085	void *pvSrc;
1086	size_t cbSrc;
1087
1088	uint32_t cbWritten = 0;
1089
1090	RTCircBufAcquireReadBlock(pCircBuf, cbLeft, &pvSrc, &cbSrc);
1091
1092	if (cbSrc)
1093	{
1094	if (pStreamR3->Dbg.Runtime.fEnabled)
1095	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileStream, pvSrc, cbSrc, 0 /* fFlags */);
1096
1097	rc = AudioMixerSinkWrite(pSink->pMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbWritten);
1098	AssertRC(rc);
1099	Assert(cbSrc >= cbWritten);
1100
1101	Log2Func(("[SD%RU8] %#RX32/%#zx bytes read @ %#RX64\n", pStreamR3->u8SD, cbWritten, cbSrc, pStreamR3->State.offRead));
1102	#ifdef VBOX_WITH_DTRACE
1103	VBOXDD_HDA_STREAM_AIO_OUT(pStreamR3->u8SD, (uint32_t)cbSrc, pStreamR3->State.offRead);
1104	#endif
1105	pStreamR3->State.offRead += cbSrc;
1106	}
1107
1108	RTCircBufReleaseReadBlock(pCircBuf, cbWritten);
1109
1110	if ( !cbWritten /* Nothing written? */
1111	\|\| RT_FAILURE(rc))
1112	break;
1113
1114	Assert(cbLeft >= cbWritten);
1115	cbLeft -= cbWritten;
1116
1117	cbReadTotal += cbWritten;
1118	}
1119
1120	if (pcbRead)
1121	*pcbRead = cbReadTotal;
1122
1123	return rc;
1124	}
1125
1126	/**
1127	* Get the current address and number of bytes left in the current BDLE.
1128	*
1129	* @returns The current physical address.
1130	* @param pStreamShared The stream to check.
1131	* @param pcbLeft The number of bytes left at the returned address.
1132	*/
1133	DECLINLINE(RTGCPHYS) hdaR3StreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1134	{
1135	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1136	AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1137
1138	uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1139	uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1140	AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1141
1142	*pcbLeft = cbCurBdl - offCurBdle;
1143	return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1144	}
1145
1146	/**
1147	* Get the size of the current BDLE.
1148	*
1149	* @returns The size (in bytes).
1150	* @param pStreamShared The stream to check.
1151	*/
1152	DECLINLINE(RTGCPHYS) hdaR3StreamDmaBufGetSize(PHDASTREAM pStreamShared)
1153	{
1154	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1155	AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1156	return pStreamShared->State.aBdl[idxBdle].cb;
1157	}
1158
1159	/**
1160	* Checks if the current BDLE is completed.
1161	*
1162	* @retval true if complete
1163	* @retval false if not.
1164	* @param pStreamShared The stream to check.
1165	*/
1166	DECLINLINE(bool) hdaR3StreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1167	{
1168	uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1169	AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1170
1171	uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1172	uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1173	Assert(offCurBdle <= cbCurBdl);
1174	return offCurBdle >= cbCurBdl;
1175	}
1176
1177	/**
1178	* Checks if the current BDLE needs a completion IRQ.
1179	*
1180	* @retval true if IRQ is needed.
1181	* @retval false if not.
1182	* @param pStreamShared The stream to check.
1183	*/
1184	DECLINLINE(bool) hdaR3StreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1185	{
1186	uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1187	AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1188	return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1189	}
1190
1191	/**
1192	* Advances the DMA engine to the next BDLE.
1193	*
1194	* @param pStreamShared The stream which DMA engine is to be updated.
1195	*/
1196	DECLINLINE(void) hdaR3StreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1197	{
1198	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1199	Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1200
1201	if (idxBdle < pStreamShared->State.cBdles - 1)
1202	idxBdle++;
1203	else
1204	idxBdle = 0;
1205	pStreamShared->State.idxCurBdle = idxBdle;
1206	pStreamShared->State.offCurBdle = 0;
1207	}
1208
1209	/**
1210	* Does DMA transfer for an HDA input stream.
1211	*
1212	* Reads audio data from the HDA stream's internal DMA buffer and writing to
1213	* guest memory.
1214	*
1215	* @returns IPRT status code.
1216	* @param pDevIns The device instance.
1217	* @param pThis The shared HDA device state.
1218	* @param pThisCC The ring-3 HDA device state.
1219	* @param pStreamShared HDA stream to update (shared).
1220	* @param pStreamR3 HDA stream to update (ring-3).
1221	* @param cbToConsume The max amount of data to consume from the
1222	* internal DMA buffer. The caller will make sure
1223	* this is always the transfer size fo the current
1224	* period (unless something is seriously wrong).
1225	* @param fWriteSilence Whether to feed the guest silence rather than
1226	* fetching bytes from the internal DMA buffer.
1227	* This is set initially while we pre-buffer a
1228	* little bit of input, so we can better handle
1229	* time catch-ups and other schduling fun.
1230	* @param tsNowNs The current RTTimeNano() value.
1231	*
1232	* @remarks Caller owns the stream lock.
1233	*/
1234	static int hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared,
1235	PHDASTREAMR3 pStreamR3, uint32_t cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1236	{
1237	uint8_t const uSD = pStreamShared->u8SD;
1238	LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1239
1240
1241	/*
1242	* Check if we should skip town...
1243	*/
1244
1245	/* Stream not running (anymore)? */
1246	if (pStreamShared->State.fRunning)
1247	{ /* likely */ }
1248	else
1249	{
1250	Log3Func(("[SD%RU8] Not running, skipping transfer\n", uSD));
1251	return VINF_SUCCESS;
1252	}
1253
1254	if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1255	{ /* likely */ }
1256	else
1257	{
1258	Log3Func(("[SD%RU8] BCIS bit set, skipping transfer\n", uSD));
1259	#ifdef HDA_STRICT
1260	/* Timing emulation bug or guest is misbehaving -- let me know. */
1261	AssertMsgFailed(("BCIS bit for stream #%RU8 still set when it shouldn't\n", uSD));
1262	#endif
1263	return VINF_SUCCESS;
1264	}
1265
1266	/*
1267	* Stream sanity checks.
1268	*/
1269	/* Register sanity checks. */
1270	Assert(uSD < HDA_MAX_STREAMS);
1271	Assert(pStreamShared->u64BDLBase);
1272	Assert(pStreamShared->u32CBL);
1273	Assert(pStreamShared->u8FIFOS);
1274
1275	/* State sanity checks. */
1276	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1277	Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1278
1279	/*
1280	* Some timestamp stuff for logging/debugging.
1281	*/
1282	/const uint64_t tsNowNs = RTTimeNanoTS();/
1283	Log3Func(("[SD%RU8] tsDeltaNs=%'RU64 ns\n", uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1284	pStreamShared->State.tsLastTransferNs = tsNowNs;
1285	pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1286
1287	/*
1288	* Set the FIFORDY bit on the stream while doing the transfer.
1289	*/
1290	/** @todo r=bird: I don't get the HDA_SDSTS_FIFORDY logic. Unless we're
1291	* assuming SMP guest and that it can get stream registers while we're
1292	* here. Only it cannot do the later because we're sitting on the big
1293	* HDA device lock, see assertions in hdaR3Timer(). So, this is an
1294	* pointless guesture given that we clear it again after the loop. */
1295	HDA_STREAM_REG(pThis, STS, uSD) \|= HDA_SDSTS_FIFORDY;
1296
1297	/*
1298	*
1299	* The DMA copy loop.
1300	*
1301	*/
1302	uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1303	uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1304	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1305	uint32_t cbLeft = cbToConsume;
1306	Assert(cbLeft == pStreamShared->State.cbTransferSize);
1307	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1308
1309	while (cbLeft > 0)
1310	{
1311	STAM_PROFILE_START(&pThis->StatIn, a);
1312
1313	/*
1314	* Figure out how much we can read & write in this iteration.
1315	*/
1316	uint32_t cbChunk = 0;
1317	RTGCPHYS GCPhys = hdaR3StreamDmaBufGet(pStreamShared, &cbChunk);
1318
1319	/* Need to diverge if the frame format differs or if we're writing silence. */
1320	if ( !pStreamR3->State.Mapping.fMappingNeeded
1321	&& !fWriteSilence)
1322	{
1323	if (cbChunk <= cbLeft)
1324	{ /* very likely */ }
1325	else
1326	cbChunk = cbLeft;
1327
1328	/*
1329	* Write the host data directly into the guest buffers.
1330	*/
1331	while (cbChunk > 0)
1332	{
1333	/* Grab internal DMA buffer space and read into it. */
1334	void /const/ *pvBufSrc;
1335	size_t cbBufSrc;
1336	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1337	AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1338
1339	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1340	AssertRC(rc2);
1341
1342	#ifdef HDA_DEBUG_SILENCE
1343	fix me if relevant;
1344	#endif
1345	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1346	{ /* likely */ }
1347	else
1348	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1349
1350	#ifdef VBOX_WITH_DTRACE
1351	VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamR3->State.offRead);
1352	#endif
1353	pStreamR3->State.offRead += cbBufSrc;
1354	RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1355	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufSrc);
1356
1357	/* advance */
1358	cbChunk -= (uint32_t)cbBufSrc;
1359	GCPhys += cbBufSrc;
1360	cbLeft -= (uint32_t)cbBufSrc;
1361	pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1362	}
1363	}
1364	/*
1365	* Either we've got some initial silence to write, or we need to do
1366	* channel mapping. Both produces guest output into the bounce buffer,
1367	* which is then copied into guest memory. The bounce buffer may keep
1368	* partial frames there for the next BDLE, if an BDLE isn't frame aligned.
1369	*
1370	* Note! cbLeft is relative to the input (host) frame size.
1371	* cbChunk OTOH is relative to output (guest) size.
1372	*/
1373	else
1374	{
1375	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1376	uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps,
1377	PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1378	cbLeft));
1379	if (cbChunk <= cbLeftGuest)
1380	{ /* very likely */ }
1381	else
1382	cbChunk = cbLeftGuest;
1383
1384	/*
1385	* Work till we've covered the chunk.
1386	*/
1387	Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1388	while (cbChunk > 0)
1389	{
1390	/* Figure out how much we need to convert into the bounce buffer: */
1391	uint32_t cbGuest = PDMAudioPropsRoundUpBytesToFrame(&pStreamR3->State.Mapping.GuestProps, cbChunk - cbBounce);
1392	uint32_t cFrames = PDMAudioPropsBytesToFrames(&pStreamR3->State.Mapping.GuestProps,
1393	RT_MIN(cbGuest, sizeof(abBounce) - cbBounce));
1394	size_t cbBufSrc;
1395	if (!fWriteSilence)
1396	{
1397	/** @todo we could loop here to optimize buffer wrap around. Not important now though. */
1398	void /const/ *pvBufSrc;
1399	RTCircBufAcquireReadBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1400	&pvBufSrc, &cbBufSrc);
1401
1402	uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1403	(uint32_t)cbBufSrc);
1404	Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufSrc);
1405	Assert(cFramesToConvert > 0);
1406	Assert(cFramesToConvert <= cFrames);
1407
1408	pStreamR3->State.Mapping.pfnHostToGuest(&abBounce[cbBounce], pvBufSrc, cFramesToConvert,
1409	&pStreamR3->State.Mapping);
1410	Log5Func((" loop1: cbBounce=%#05x cFramesToConvert=%#05x cbBufSrc=%#x%s\n",
1411	cbBounce, cFramesToConvert, cbBufSrc, ASMMemIsZero(pvBufSrc, cbBufSrc) ? " all zero" : ""));
1412	#ifdef HDA_DEBUG_SILENCE
1413	fix me if relevant;
1414	#endif
1415	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1416	{ /* likely */ }
1417	else
1418	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1419
1420	#ifdef VBOX_WITH_DTRACE
1421	VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamR3->State.offRead);
1422	#endif
1423
1424	pStreamR3->State.offRead += cbBufSrc;
1425	RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1426
1427	cFrames = cFramesToConvert;
1428	cbGuest = cbBounce + PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps, cFrames);
1429	}
1430	else
1431	{
1432	cbBufSrc = PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames);
1433	cbGuest = PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps, cFrames);
1434	PDMAudioPropsClearBuffer(&pStreamR3->State.Mapping.GuestProps,
1435	&abBounce[cbBounce], cbGuest, cFrames);
1436	cbGuest += cbBounce;
1437	}
1438
1439	/* Write it to the guest buffer. */
1440	uint32_t cbGuestActual = RT_MIN(cbGuest, cbChunk);
1441	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, abBounce, cbGuestActual);
1442	AssertRC(rc2);
1443	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbGuestActual);
1444
1445	/* advance */
1446	cbLeft -= (uint32_t)cbBufSrc;
1447	cbChunk -= cbGuestActual;
1448	GCPhys += cbGuestActual;
1449	pStreamShared->State.offCurBdle += cbGuestActual;
1450
1451	cbBounce = cbGuest - cbGuestActual;
1452	if (cbBounce)
1453	memmove(abBounce, &abBounce[cbGuestActual], cbBounce);
1454
1455	Log5Func((" loop1: GCPhys=%RGp cbGuestActual=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbGuestActual, cbBounce, cFrames));
1456	}
1457	Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1458	}
1459
1460	STAM_PROFILE_STOP(&pThis->StatIn, a);
1461
1462	/*
1463	* Is the buffer descriptor complete.
1464	*/
1465	if (hdaR3StreamDmaBufIsComplete(pStreamShared))
1466	{
1467	Log3Func(("[SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n",
1468	uSD, pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1469	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1470	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1471
1472	/* Make sure to also update the wall clock when a BDLE is complete.
1473	* Needed for Windows 10 guests. */
1474	/** @todo there is a rounding error here. */
1475	hdaR3WalClkSet(pThis, pThisCC,
1476	hdaWalClkGetCurrent(pThis)
1477	+ hdaR3StreamPeriodFramesToWalClk(&pStreamShared->State.Period,
1478	hdaR3StreamDmaBufGetSize(pStreamShared)
1479	/ pStreamR3->State.Mapping.cbGuestFrame),
1480	false /* fForce */);
1481
1482	/*
1483	* Update the stream's current position.
1484	*
1485	* Do this as accurate and close to the actual data transfer as possible.
1486	* All guetsts rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1487	*
1488	* Note for Windows 10: The OS' driver is very picky about when the (DMA) positions get updated!
1489	* Not doing this at the right time will result in ugly sound crackles!
1490	*/
1491	hdaR3StreamSetPositionAdd(pStreamShared, pDevIns, pThis, hdaR3StreamDmaBufGetSize(pStreamShared));
1492
1493	/* Does the current BDLE require an interrupt to be sent? */
1494	if (hdaR3StreamDmaBufNeedsIrq(pStreamShared))
1495	{
1496	/* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1497	register is set we need to generate an interrupt. */
1498	if (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_IOCE)
1499	{
1500	/* Assert the interrupt before actually fetching the next BDLE below. */
1501	pStreamShared->State.cTransferPendingInterrupts = 1;
1502	Log3Func(("[SD%RU8] Scheduling interrupt\n", uSD));
1503
1504	/* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1505	* ending / beginning of a period. */
1506	/** @todo r=bird: What does the above comment mean? */
1507	HDA_STREAM_REG(pThis, STS, uSD) \|= HDA_SDSTS_BCIS;
1508	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1509	}
1510	}
1511
1512	/*
1513	* Advance to the next BDLE.
1514	*/
1515	hdaR3StreamDmaBufAdvanceToNext(pStreamShared);
1516	}
1517	else
1518	Log3Func(("[SD%RU8] Not completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n",
1519	uSD, pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1520	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1521	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1522	}
1523
1524	Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1525	AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1526
1527	/*
1528	* Clear the (pointless) FIFORDY bit again.
1529	*/
1530	HDA_STREAM_REG(pThis, STS, uSD) &= ~HDA_SDSTS_FIFORDY;
1531
1532	/*
1533	* Try updating the wall clock.
1534	*
1535	* Note 1) Only certain guests (like Linux' snd_hda_intel) rely on the WALCLK register
1536	* in order to determine the correct timing of the sound device. Other guests
1537	* like Windows 7 + 10 (or even more exotic ones like Haiku) will completely
1538	* ignore this.
1539	*
1540	* Note 2) When updating the WALCLK register too often / early (or even in a non-monotonic
1541	* fashion) this will upset guest device drivers and will completely fuck up the
1542	* sound output. Running VLC on the guest will tell!
1543	*/
1544	uint32_t const cFramesProcessed = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, cbToConsume);
1545	/** @todo this needs to go, but we need it for hdaR3WalClkGetMax below. */
1546	hdaR3StreamPeriodInc(&pStreamShared->State.Period,
1547	RT_MIN(cFramesProcessed, hdaR3StreamPeriodGetRemainingFrames(&pStreamShared->State.Period)));
1548
1549	uint64_t const cWallTicks = hdaR3StreamPeriodFramesToWalClk(&pStreamShared->State.Period, cFramesProcessed);
1550	uint64_t const uWallNew = hdaWalClkGetCurrent(pThis) + cWallTicks;
1551	uint64_t const uWallMax = hdaR3WalClkGetMax(pThis, pThisCC);
1552	bool const fWalClkSet = hdaR3WalClkSet(pThis, pThisCC, RT_MIN(uWallNew, uWallMax), false /* fForce */);
1553	RT_NOREF(fWalClkSet);
1554
1555	/*
1556	* Log and leave.
1557	*/
1558	Log3Func(("[SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1559	uSD, cbToConsume, pStreamShared->State.cbTransferSize, pStreamR3->State.offRead - cbToConsume,
1560	pStreamShared->State.cTransferPendingInterrupts));
1561	return VINF_SUCCESS;
1562	}
1563
1564
1565	/**
1566	* Input streams: Pulls data from to the host device thru the mixer, putting it
1567	* in the internal DMA buffer.
1568	*
1569	* @param pStreamShared HDA stream to update (shared bits).
1570	* @param pStreamR3 HDA stream to update (ring-3 bits).
1571	* @param pSink The mixer sink to push to.
1572	*/
1573	static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1574	{
1575	int rc = AudioMixerSinkUpdate(pSink);
1576	AssertRC(rc);
1577
1578	/* Is the sink ready to be read (host input data) from? If so, by how much? */
1579	uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1580
1581	/* How much (guest input) data is available for writing at the moment for the HDA stream? */
1582	const uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1583
1584	Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStreamShared->u8SD, cbSinkReadable, cbStreamFree));
1585
1586	/* Do not read more than the HDA stream can hold at the moment.
1587	* The host sets the overall pace. */
1588	if (cbSinkReadable > cbStreamFree)
1589	cbSinkReadable = cbStreamFree;
1590
1591	/** @todo should we throttle (read less) this if we're far ahead? */
1592
1593	/*
1594	* Copy loop.
1595	*/
1596	while (cbSinkReadable)
1597	{
1598	/* Read a chunk of data. */
1599	uint8_t abBuf[4096];
1600	uint32_t cbRead = 0;
1601	rc = AudioMixerSinkRead(pSink, AUDMIXOP_COPY, abBuf, RT_MIN(cbSinkReadable, sizeof(abBuf)), &cbRead);
1602	AssertRCBreak(rc);
1603	AssertMsg(cbRead > 0, ("Nothing read from sink, even if %RU32 bytes were (still) announced\n", cbSinkReadable));
1604
1605	/* Write it to the internal DMA buffer. */
1606	uint32_t off = 0;
1607	while (off < cbRead)
1608	{
1609	void *pvDstBuf;
1610	size_t cbDstBuf;
1611	RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbRead - off, &pvDstBuf, &cbDstBuf);
1612
1613	memcpy(pvDstBuf, &abBuf[off], cbDstBuf);
1614
1615	#ifdef VBOX_WITH_DTRACE
1616	VBOXDD_HDA_STREAM_AIO_IN((uint32_t)pStreamR3->u8SD, (uint32_t)cbDstBuf, pStreamR3->State.offWrite);
1617	#endif
1618	pStreamR3->State.offWrite += cbDstBuf;
1619
1620	RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
1621
1622	off += cbDstBuf;
1623	}
1624	Assert(off == cbRead);
1625
1626	/* Write to debug file? */
1627	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1628	{ /* likely */ }
1629	else
1630	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileStream, abBuf, cbRead, 0 /* fFlags */);
1631
1632	/* Advance. */
1633	Assert(cbRead <= cbSinkReadable);
1634	cbSinkReadable -= cbRead;
1635	}
1636	}
1637
1638	/**
1639	* Does DMA transfer for an HDA output stream.
1640	*
1641	* This transfers one DMA timer period worth of data from the guest and into the
1642	* internal DMA buffer.
1643	*
1644	* @returns IPRT status code.
1645	* @param pDevIns The device instance.
1646	* @param pThis The shared HDA device state.
1647	* @param pThisCC The ring-3 HDA device state.
1648	* @param pStreamShared HDA stream to update (shared).
1649	* @param pStreamR3 HDA stream to update (ring-3).
1650	* @param cbToProduce The max amount of data to produce (i.e. put into
1651	* the circular buffer). Unless something is going
1652	* seriously wrong, this will always be transfer
1653	* size for the current period.
1654	* @param tsNowNs The current RTTimeNano() value.
1655	*
1656	* @remarks Caller owns the stream lock.
1657	*/
1658	static int hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared,
1659	PHDASTREAMR3 pStreamR3, uint32_t cbToProduce, uint64_t tsNowNs)
1660	{
1661	uint8_t const uSD = pStreamShared->u8SD;
1662	LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1663
1664
1665	/*
1666	* Check if we should skip town...
1667	*/
1668
1669	/* Stream not running (anymore)? */
1670	if (pStreamShared->State.fRunning)
1671	{ /* likely */ }
1672	else
1673	{
1674	Log3Func(("[SD%RU8] Not running, skipping transfer\n", uSD));
1675	return VINF_SUCCESS;
1676	}
1677
1678	if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1679	{ /* likely */ }
1680	else
1681	{
1682	Log3Func(("[SD%RU8] BCIS bit set, skipping transfer\n", uSD));
1683	#ifdef HDA_STRICT
1684	/* Timing emulation bug or guest is misbehaving -- let me know. */
1685	AssertMsgFailed(("BCIS bit for stream #%RU8 still set when it shouldn't\n", uSD));
1686	#endif
1687	return VINF_SUCCESS;
1688	}
1689
1690	/*
1691	* Stream sanity checks.
1692	*/
1693	/* Register sanity checks. */
1694	Assert(uSD < HDA_MAX_STREAMS);
1695	Assert(pStreamShared->u64BDLBase);
1696	Assert(pStreamShared->u32CBL);
1697	Assert(pStreamShared->u8FIFOS);
1698
1699	/* State sanity checks. */
1700	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1701	Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1702
1703	/*
1704	* Some timestamp stuff for logging/debugging.
1705	*/
1706	/const uint64_t tsNowNs = RTTimeNanoTS();/
1707	Log3Func(("[SD%RU8] tsDeltaNs=%'RU64 ns\n", uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1708	pStreamShared->State.tsLastTransferNs = tsNowNs;
1709	pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1710
1711	/*
1712	* Set the FIFORDY bit on the stream while doing the transfer.
1713	*/
1714	/** @todo r=bird: I don't get the HDA_SDSTS_FIFORDY logic. Unless we're
1715	* assuming SMP guest and that it can get stream registers while we're
1716	* here. Only it cannot do the later because we're sitting on the big
1717	* HDA device lock, see assertions in hdaR3Timer(). So, this is an
1718	* pointless guesture given that we clear it again after the loop. */
1719	HDA_STREAM_REG(pThis, STS, uSD) \|= HDA_SDSTS_FIFORDY;
1720
1721	/*
1722	*
1723	* The DMA copy loop.
1724	*
1725	*/
1726	uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1727	uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1728	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1729	uint32_t cbLeft = cbToProduce;
1730	Assert(cbLeft == pStreamShared->State.cbTransferSize);
1731	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1732
1733	while (cbLeft > 0)
1734	{
1735	STAM_PROFILE_START(&pThis->StatOut, a);
1736
1737	/*
1738	* Figure out how much we can read & write in this iteration.
1739	*/
1740	uint32_t cbChunk = 0;
1741	RTGCPHYS GCPhys = hdaR3StreamDmaBufGet(pStreamShared, &cbChunk);
1742
1743	/* Need to diverge if the frame format differs. */
1744	if ( !pStreamR3->State.Mapping.fMappingNeeded
1745	/** @todo && pStreamShared->State.fFrameAlignedBuffers */)
1746	{
1747	if (cbChunk <= cbLeft)
1748	{ /* very likely */ }
1749	else
1750	cbChunk = cbLeft;
1751
1752	/*
1753	* Read the guest data directly into the internal DMA buffer.
1754	*/
1755	while (cbChunk > 0)
1756	{
1757	/* Grab internal DMA buffer space and read into it. */
1758	void *pvBufDst;
1759	size_t cbBufDst;
1760	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1761	AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1762
1763	int rc2 = PDMDevHlpPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1764	AssertRC(rc2);
1765
1766	#ifdef HDA_DEBUG_SILENCE
1767	fix me if relevant;
1768	#endif
1769	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1770	{ /* likely */ }
1771	else
1772	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1773
1774	#ifdef VBOX_WITH_DTRACE
1775	VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamR3->State.offWrite);
1776	#endif
1777	pStreamR3->State.offWrite += cbBufDst;
1778	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1779	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1780
1781	/* advance */
1782	cbChunk -= (uint32_t)cbBufDst;
1783	GCPhys += cbBufDst;
1784	cbLeft -= (uint32_t)cbBufDst;
1785	pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1786	}
1787	}
1788	/*
1789	* Need to map the frame content, so we need to read the guest data
1790	* into a temporary buffer, though the output can be directly written
1791	* into the internal buffer as it is assumed to be frame aligned.
1792	*
1793	* Note! cbLeft is relative to the output frame size.
1794	* cbChunk OTOH is relative to input size.
1795	*/
1796	else
1797	{
1798	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1799	uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps,
1800	PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1801	cbLeft));
1802	if (cbChunk <= cbLeftGuest)
1803	{ /* very likely */ }
1804	else
1805	cbChunk = cbLeftGuest;
1806
1807	/*
1808	* Loop till we've covered the chunk.
1809	*/
1810	Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1811	while (cbChunk > 0)
1812	{
1813	/* Read into the bounce buffer. */
1814	uint32_t const cbToRead = RT_MIN(cbChunk, sizeof(abBounce) - cbBounce);
1815	int rc2 = PDMDevHlpPhysRead(pDevIns, GCPhys, &abBounce[cbBounce], cbToRead);
1816	AssertRC(rc2);
1817	cbBounce += cbToRead;
1818
1819	/* Convert the size to whole frames and a remainder. */
1820	uint32_t cFrames = PDMAudioPropsBytesToFrames(&pStreamR3->State.Mapping.GuestProps, cbBounce);
1821	uint32_t const cbRemainder = cbBounce - PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps, cFrames);
1822	Log5Func((" loop1: GCPhys=%RGp cbToRead=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbToRead, cbBounce, cFrames));
1823
1824	/*
1825	* Convert from the bounce buffer and into the internal DMA buffer.
1826	*/
1827	uint32_t offBounce = 0;
1828	while (cFrames > 0)
1829	{
1830	void *pvBufDst;
1831	size_t cbBufDst;
1832	RTCircBufAcquireWriteBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1833	&pvBufDst, &cbBufDst);
1834
1835	uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, (uint32_t)cbBufDst);
1836	Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufDst);
1837	Assert(cFramesToConvert > 0);
1838	Assert(cFramesToConvert <= cFrames);
1839
1840	pStreamR3->State.Mapping.pfnGuestToHost(pvBufDst, &abBounce[offBounce], cFramesToConvert,
1841	&pStreamR3->State.Mapping);
1842	Log5Func((" loop2: offBounce=%#05x cFramesToConvert=%#05x cbBufDst=%#x%s\n",
1843	offBounce, cFramesToConvert, cbBufDst, ASMMemIsZero(pvBufDst, cbBufDst) ? " all zero" : ""));
1844
1845	# ifdef HDA_DEBUG_SILENCE
1846	fix me if relevant;
1847	# endif
1848	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1849	{ /* likely */ }
1850	else
1851	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1852
1853	pStreamR3->State.offWrite += cbBufDst;
1854	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1855	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1856
1857	/* advance */
1858	cbLeft -= (uint32_t)cbBufDst;
1859	cFrames -= cFramesToConvert;
1860	offBounce += PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps, cFramesToConvert);
1861	}
1862
1863	/* advance */
1864	cbChunk -= cbToRead;
1865	GCPhys += cbToRead;
1866	pStreamShared->State.offCurBdle += cbToRead;
1867	if (cbRemainder)
1868	memmove(&abBounce[0], &abBounce[cbBounce - cbRemainder], cbRemainder);
1869	cbBounce = cbRemainder;
1870	}
1871	Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1872	}
1873
1874	STAM_PROFILE_STOP(&pThis->StatOut, a);
1875
1876	/*
1877	* Is the buffer descriptor complete.
1878	*/
1879	if (hdaR3StreamDmaBufIsComplete(pStreamShared))
1880	{
1881	Log3Func(("[SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", uSD, pStreamShared->State.idxCurBdle,
1882	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1883	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1884	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1885
1886	/* Make sure to also update the wall clock when a BDLE is complete.
1887	* Needed for Windows 10 guests. */
1888	/** @todo there is a rounding error here. */
1889	hdaR3WalClkSet(pThis, pThisCC,
1890	hdaWalClkGetCurrent(pThis)
1891	+ hdaR3StreamPeriodFramesToWalClk(&pStreamShared->State.Period,
1892	hdaR3StreamDmaBufGetSize(pStreamShared)
1893	/ pStreamR3->State.Mapping.cbGuestFrame),
1894	false /* fForce */);
1895
1896	/*
1897	* Update the stream's current position.
1898	*
1899	* Do this as accurate and close to the actual data transfer as possible.
1900	* All guetsts rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1901	*
1902	* Note for Windows 10: The OS' driver is very picky about when the (DMA) positions get updated!
1903	* Not doing this at the right time will result in ugly sound crackles!
1904	*/
1905	hdaR3StreamSetPositionAdd(pStreamShared, pDevIns, pThis, hdaR3StreamDmaBufGetSize(pStreamShared));
1906
1907	/* Does the current BDLE require an interrupt to be sent? */
1908	if (hdaR3StreamDmaBufNeedsIrq(pStreamShared))
1909	{
1910	/* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1911	register is set we need to generate an interrupt. */
1912	if (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_IOCE)
1913	{
1914	/* Assert the interrupt before actually fetching the next BDLE below. */
1915	pStreamShared->State.cTransferPendingInterrupts = 1;
1916	Log3Func(("[SD%RU8] Scheduling interrupt\n", uSD));
1917
1918	/* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1919	* ending / beginning of a period. */
1920	/** @todo r=bird: What does the above comment mean? */
1921	HDA_STREAM_REG(pThis, STS, uSD) \|= HDA_SDSTS_BCIS;
1922	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1923	}
1924	}
1925
1926	/*
1927	* Advance to the next BDLE.
1928	*/
1929	hdaR3StreamDmaBufAdvanceToNext(pStreamShared);
1930	}
1931	else
1932	Log3Func(("[SD%RU8] Not completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n",
1933	uSD, pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1934	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1935	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1936	}
1937
1938	Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1939	AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1940
1941	/*
1942	* Clear the (pointless) FIFORDY bit again.
1943	*/
1944	HDA_STREAM_REG(pThis, STS, uSD) &= ~HDA_SDSTS_FIFORDY;
1945
1946	/*
1947	* Try updating the wall clock.
1948	*
1949	* Note 1) Only certain guests (like Linux' snd_hda_intel) rely on the WALCLK register
1950	* in order to determine the correct timing of the sound device. Other guests
1951	* like Windows 7 + 10 (or even more exotic ones like Haiku) will completely
1952	* ignore this.
1953	*
1954	* Note 2) When updating the WALCLK register too often / early (or even in a non-monotonic
1955	* fashion) this will upset guest device drivers and will completely fuck up the
1956	* sound output. Running VLC on the guest will tell!
1957	*/
1958	uint32_t const cFramesProcessed = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, cbToProduce);
1959	/** @todo this needs to go, but we need it for hdaR3WalClkGetMax below. */
1960	hdaR3StreamPeriodInc(&pStreamShared->State.Period,
1961	RT_MIN(cFramesProcessed, hdaR3StreamPeriodGetRemainingFrames(&pStreamShared->State.Period)));
1962
1963	uint64_t const cWallTicks = hdaR3StreamPeriodFramesToWalClk(&pStreamShared->State.Period, cFramesProcessed);
1964	uint64_t const uWallNew = hdaWalClkGetCurrent(pThis) + cWallTicks;
1965	uint64_t const uWallMax = hdaR3WalClkGetMax(pThis, pThisCC);
1966	bool const fWalClkSet = hdaR3WalClkSet(pThis, pThisCC, RT_MIN(uWallNew, uWallMax), false /* fForce */);
1967	RT_NOREF(fWalClkSet);
1968
1969	/*
1970	* Log and leave.
1971	*/
1972	Log3Func(("[SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1973	uSD, cbToProduce, pStreamShared->State.cbTransferSize, pStreamR3->State.offWrite - cbToProduce,
1974	pStreamShared->State.cTransferPendingInterrupts));
1975
1976	LogFlowFuncLeave();
1977	return VINF_SUCCESS;
1978	}
1979
1980
1981	/**
1982	* Output streams: Pushes data from to the mixer and host device.
1983	*
1984	* @param pStreamShared HDA stream to update (shared bits).
1985	* @param pStreamR3 HDA stream to update (ring-3 bits).
1986	* @param pSink The mixer sink to push to.
1987	* @param nsNow The current RTTimeNanoTS() value.
1988	*/
1989	static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
1990	{
1991	uint32_t const cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1992	uint32_t const cbStreamReadable = hdaR3StreamGetUsed(pStreamR3);
1993	uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1994	/* Make sure that we always align the number of bytes when reading to the stream's PCM properties. */
1995	cbToReadFromStream = PDMAudioPropsFloorBytesToFrame(&pStreamShared->State.Cfg.Props, cbToReadFromStream);
1996
1997	Assert(nsNow >= pStreamShared->State.tsLastReadNs);
1998	Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 cbSinkWritable=%RU32 cbStreamReadable=%RU32 -> cbToReadFromStream=%RU32\n",
1999	pStreamShared->u8SD, nsNow - pStreamShared->State.tsLastReadNs, cbSinkWritable, cbStreamReadable, cbToReadFromStream));
2000	RT_NOREF(pStreamShared, nsNow);
2001
2002	if (cbToReadFromStream)
2003	{
2004	/* Read (guest output) data and write it to the stream's sink. */
2005	int rc2 = hdaR3StreamRead(pStreamR3, cbToReadFromStream, NULL /* pcbRead */);
2006	AssertRC(rc2);
2007	}
2008
2009	int rc2 = AudioMixerSinkUpdate(pSink);
2010	AssertRC(rc2);
2011	}
2012
2013	/**
2014	* The stream's main function when called by the timer.
2015	*
2016	* @note This function also will be called without timer invocation when
2017	* starting (enabling) the stream to minimize startup latency.
2018	*
2019	* @returns Current timer time if the timer is enabled, otherwise zero.
2020	* @param pDevIns The device instance.
2021	* @param pThis The shared HDA device state.
2022	* @param pThisCC The ring-3 HDA device state.
2023	* @param pStreamShared HDA stream to update (shared bits).
2024	* @param pStreamR3 HDA stream to update (ring-3 bits).
2025	*/
2026	uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2027	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2028	{
2029	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2030	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
2031
2032	/* Do the work: */
2033	hdaR3StreamUpdate(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, true /* fInTimer */);
2034
2035	/* Re-arm the timer if the sink is still active: */
2036	if ( pStreamShared->State.fRunning
2037	&& pStreamR3->pMixSink
2038	&& AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
2039	{
2040	/* Advance the schduling: */
2041	uint32_t idxSched = pStreamShared->State.idxSchedule;
2042	AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2043	uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
2044	if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
2045	{
2046	idxSched += 1;
2047	if ( idxSched > pStreamShared->State.cSchedule
2048	\|\| idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /paranoia^2/)
2049	{
2050	idxSched = pStreamShared->State.cSchedulePrologue;
2051	AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2052	}
2053	idxLoop = 0;
2054	}
2055	pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
2056
2057	/* Do the arcual timer arming. */
2058	uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2059	uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
2060	Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
2061	pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
2062	int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
2063	AssertRC(rc);
2064
2065	/* Some legacy stuff: */
2066	pStreamShared->State.tsTransferNext = tsTransferNext;
2067	pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2068
2069	return tsNow;
2070	}
2071
2072	Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
2073	return 0;
2074	}
2075
2076	/**
2077	* Updates a HDA stream by doing its required data transfers.
2078	*
2079	* The host sink(s) set the overall pace.
2080	*
2081	* This routine is called by both, the synchronous and the asynchronous
2082	* (VBOX_WITH_AUDIO_HDA_ASYNC_IO), implementations.
2083	*
2084	* When running synchronously, the device DMA transfers and the mixer sink
2085	* processing is within the device timer.
2086	*
2087	* When running asynchronously, only the device DMA transfers are done in the
2088	* device timer, whereas the mixer sink processing then is done in the stream's
2089	* own async I/O thread. This thread also will call this function
2090	* (with fInTimer set to @c false).
2091	*
2092	* @param pDevIns The device instance.
2093	* @param pThis The shared HDA device state.
2094	* @param pThisCC The ring-3 HDA device state.
2095	* @param pStreamShared HDA stream to update (shared bits).
2096	* @param pStreamR3 HDA stream to update (ring-3 bits).
2097	* @param fInTimer Whether to this function was called from the timer
2098	* context or an asynchronous I/O stream thread (if supported).
2099	*/
2100	void hdaR3StreamUpdate(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2101	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fInTimer)
2102	{
2103	int rc2;
2104
2105	/*
2106	* Make sure we're running and got an active mixer sink.
2107	*/
2108	if (RT_LIKELY(pStreamShared->State.fRunning))
2109	{ /* likely */ }
2110	else
2111	return;
2112
2113	PAUDMIXSINK pSink = NULL;
2114	if (pStreamR3->pMixSink)
2115	pSink = pStreamR3->pMixSink->pMixSink;
2116	if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2117	{ /* likely */ }
2118	else
2119	return;
2120
2121	/*
2122	* Get scheduling info common to both input and output streams.
2123	*/
2124	const uint64_t tsNowNs = RTTimeNanoTS();
2125	uint32_t idxSched = pStreamShared->State.idxSchedule;
2126	AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2127	uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2128
2129	/*
2130	* Output streams (SDO).
2131	*/
2132	if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2133	{
2134	bool fDoRead; /* Whether to push data down the driver stack or not. */
2135	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2136	if (fInTimer)
2137	# endif
2138	{
2139	/*
2140	* Check how much room we have in our DMA buffer. There should be at
2141	* least one period worth of space there or we're in an overflow situation.
2142	*/
2143	uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2144	if (cbStreamFree >= cbPeriod)
2145	{ /* likely */ }
2146	else
2147	{
2148	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2149	Log(("hdaR3StreamUpdate: Warning! Stream #%u has insufficient space free: %u bytes, need %u. Will try move data out of the buffer...\n",
2150	pStreamShared->u8SD, cbStreamFree, cbPeriod));
2151	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2152	int rc = RTCritSectTryEnter(&pStreamR3->State.AIO.CritSect);
2153	if (RT_SUCCESS(rc))
2154	{
2155	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, tsNowNs);
2156	RTCritSectLeave(&pStreamR3->State.AIO.CritSect);
2157	}
2158	else
2159	RTThreadYield();
2160	#else
2161	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, tsNowNs);
2162	#endif
2163	Log(("hdaR3StreamUpdate: Gained %u bytes.\n", hdaR3StreamGetFree(pStreamR3) - cbStreamFree));
2164
2165	cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2166	if (cbStreamFree < cbPeriod)
2167	{
2168	/* Unable to make sufficient space. Drop the whole buffer content.
2169	* This is needed in order to keep the device emulation running at a constant rate,
2170	* at the cost of losing valid (but too much) data. */
2171	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2172	LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data\n",
2173	pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3)));
2174	# ifdef HDA_STRICT
2175	AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
2176	# endif
2177	RTCircBufReset(pStreamR3->State.pCircBuf);
2178	pStreamR3->State.offWrite = 0;
2179	pStreamR3->State.offRead = 0;
2180	cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2181	}
2182	}
2183
2184	/*
2185	* Do the DMA transfer.
2186	*/
2187	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2188	rc2 = PDMDevHlpCritSectEnter(pDevIns, &pStreamShared->CritSect, VERR_IGNORED);
2189	AssertRC(rc2);
2190	# endif
2191
2192	uint64_t const offWriteBefore = pStreamR3->State.offWrite;
2193	rc2 = hdaR3StreamDoDmaOutput(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2194	AssertRC(rc2);
2195
2196	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2197	rc2 = PDMDevHlpCritSectLeave(pDevIns, &pStreamShared->CritSect);
2198	AssertRC(rc2);
2199	# endif
2200
2201	/*
2202	* Should we push data to down thru the mixer to and to the host drivers?
2203	*
2204	* We initially delay this by pThis->msInitialDelay, but after than we'll
2205	* kick the AIO thread every time we've put more data in the buffer (which is
2206	* every time) as the host audio device needs to get data in a timely manner.
2207	*
2208	* (We used to try only wake up the AIO thread according to pThis->uIoTimer
2209	* and host wall clock, but that meant we would miss a wakup after the DMA
2210	* timer was called a little late or if TM entered into catch-up mode.)
2211	*/
2212	if (!pStreamShared->State.tsAioDelayEnd)
2213	fDoRead = pStreamR3->State.offWrite > offWriteBefore
2214	\|\| hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2215	else if (PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer) >= pStreamShared->State.tsAioDelayEnd)
2216	{
2217	Log3Func(("Initial delay done: Passed tsAioDelayEnd.\n"));
2218	pStreamShared->State.tsAioDelayEnd = 0;
2219	fDoRead = true;
2220	}
2221	else if (hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2)
2222	{
2223	Log3Func(("Initial delay done: Passed running short on buffer.\n"));
2224	pStreamShared->State.tsAioDelayEnd = 0;
2225	fDoRead = true;
2226	}
2227	else
2228	{
2229	Log3Func(("Initial delay pending...\n"));
2230	fDoRead = false;
2231	}
2232
2233	Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fDoRead=%RTbool\n",
2234	(tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2235	pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2236	pStreamShared->State.cbAvgTransfer * 2, fDoRead));
2237
2238	if (fDoRead)
2239	{
2240	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2241	/* Notify the async I/O worker thread that there's work to do. */
2242	Log5Func(("Notifying AIO thread\n"));
2243	rc2 = hdaR3StreamAsyncIONotify(pStreamR3);
2244	AssertRC(rc2);
2245	# endif
2246	/* Update last read timestamp for logging/debugging. */
2247	pStreamShared->State.tsLastReadNs = tsNowNs;
2248	}
2249	}
2250
2251	/*
2252	* Move data out of the pStreamR3->State.pCircBuf buffer and to
2253	* the mixer and in direction of the host audio devices.
2254	*/
2255	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2256	else
2257	# else
2258	if (fDoRead)
2259	# endif
2260	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, tsNowNs);
2261	}
2262	/*
2263	* Input stream (SDI).
2264	*/
2265	else
2266	{
2267	Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2268
2269	/*
2270	* If we're the async I/O worker, or not using AIO, pull bytes
2271	* from the mixer and into our internal DMA buffer.
2272	*/
2273	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2274	if (!fInTimer)
2275	# endif
2276	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2277	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2278	else /* fInTimer */
2279	# endif
2280	{
2281	/*
2282	* See how much data we've got buffered...
2283	*/
2284	bool fWriteSilence = false;
2285	uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2286	if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2287	{ /likely/ }
2288	/* Because it may take a while for the input stream to get going (at
2289	least with pulseaudio), we feed the guest silence till we've
2290	pre-buffer a reasonable amount of audio. */
2291	else if (!pStreamShared->State.fInputPreBuffered)
2292	{
2293	if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2294	{
2295	Log3(("hdaR3StreamUpdate: Pre-buffering (got %#x out of %#x bytes)...\n",
2296	cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2297	fWriteSilence = true;
2298	}
2299	else
2300	{
2301	Log3(("hdaR3StreamUpdate: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2302	cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2303	pStreamShared->State.fInputPreBuffered = true;
2304	fWriteSilence = true; /* For now, just do the most conservative thing. */
2305	}
2306	cbStreamUsed = cbPeriod;
2307	}
2308	/*
2309	* When we're low on data, we must really try fetch some ourselves
2310	* as buffer underruns must not happen.
2311	*/
2312	else
2313	{
2314	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2315	Log(("hdaR3StreamUpdate: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2316	pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2317	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2318	int rc = RTCritSectTryEnter(&pStreamR3->State.AIO.CritSect);
2319	if (RT_SUCCESS(rc))
2320	{
2321	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2322	RTCritSectLeave(&pStreamR3->State.AIO.CritSect);
2323	}
2324	else
2325	RTThreadYield();
2326	#else
2327	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2328	#endif
2329	Log(("hdaR3StreamUpdate: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2330	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2331	if (cbStreamUsed < cbPeriod)
2332	{
2333	/* Unable to find sufficient input data by simple prodding.
2334	In order to keep a constant byte stream following thru the DMA
2335	engine into the guest, we will try again and then fall back on
2336	filling the gap with silence. */
2337	uint32_t cbSilence = 0;
2338	do
2339	{
2340	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2341	RTCritSectEnter(&pStreamR3->State.AIO.CritSect);
2342	#endif
2343	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2344	if (cbStreamUsed < cbPeriod)
2345	{
2346	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2347	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2348	while (cbStreamUsed < cbPeriod)
2349	{
2350	void *pvDstBuf;
2351	size_t cbDstBuf;
2352	RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2353	&pvDstBuf, &cbDstBuf);
2354	RT_BZERO(pvDstBuf, cbDstBuf);
2355	RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2356	cbSilence += cbDstBuf;
2357	cbStreamUsed += cbDstBuf;
2358	}
2359	}
2360
2361	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2362	RTCritSectLeave(&pStreamR3->State.AIO.CritSect);
2363	#endif
2364	} while (cbStreamUsed < cbPeriod);
2365	if (cbSilence > 0)
2366	{
2367	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2368	STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2369	LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2370	cbSilence, PDMAudioPropsBytesToMicro(&pStreamR3->State.Mapping.GuestProps, cbSilence)));
2371	}
2372	}
2373	}
2374
2375	/*
2376	* Do the DMA'ing.
2377	*/
2378	if (cbStreamUsed)
2379	{
2380	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2381	rc2 = PDMDevHlpCritSectEnter(pDevIns, &pStreamShared->CritSect, VERR_IGNORED);
2382	AssertRC(rc2);
2383	# endif
2384
2385	rc2 = hdaR3StreamDoDmaInput(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3,
2386	RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2387	AssertRC(rc2);
2388
2389	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2390	rc2 = PDMDevHlpCritSectLeave(pDevIns, &pStreamShared->CritSect);
2391	AssertRC(rc2);
2392	# endif
2393	}
2394
2395	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2396	/*
2397	* We should always kick the AIO thread.
2398	*/
2399	/** @todo This isn't entirely ideal. If we get into an underrun situation,
2400	* we ideally want the AIO thread to run right before the DMA timer
2401	* rather than right after it ran. */
2402	Log5Func(("Notifying AIO thread\n"));
2403	rc2 = hdaR3StreamAsyncIONotify(pStreamR3);
2404	AssertRC(rc2);
2405	pStreamShared->State.tsLastReadNs = tsNowNs;
2406	# endif
2407	}
2408	}
2409	}
2410
2411	#endif /* IN_RING3 */
2412
2413	/**
2414	* Locks an HDA stream for serialized access.
2415	*
2416	* @returns IPRT status code.
2417	* @param pStreamShared HDA stream to lock (shared bits).
2418	*/
2419	void hdaStreamLock(PHDASTREAM pStreamShared)
2420	{
2421	AssertPtrReturnVoid(pStreamShared);
2422	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2423	int rc2 = PDMCritSectEnter(&pStreamShared->CritSect, VINF_SUCCESS);
2424	AssertRC(rc2);
2425	#endif
2426	}
2427
2428	/**
2429	* Unlocks a formerly locked HDA stream.
2430	*
2431	* @returns IPRT status code.
2432	* @param pStreamShared HDA stream to unlock (shared bits).
2433	*/
2434	void hdaStreamUnlock(PHDASTREAM pStreamShared)
2435	{
2436	AssertPtrReturnVoid(pStreamShared);
2437	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2438	int rc2 = PDMCritSectLeave(&pStreamShared->CritSect);
2439	AssertRC(rc2);
2440	# endif
2441	}
2442
2443	#ifdef IN_RING3
2444
2445	#if 0 /* unused - no prototype even */
2446	/**
2447	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
2448	* updating its associated LPIB register and DMA position buffer (if enabled).
2449	*
2450	* @returns Set LPIB value.
2451	* @param pDevIns The device instance.
2452	* @param pStream HDA stream to update read / write position for.
2453	* @param u32LPIB New LPIB (position) value to set.
2454	*/
2455	uint32_t hdaR3StreamUpdateLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t u32LPIB)
2456	{
2457	AssertMsg(u32LPIB <= pStreamShared->u32CBL,
2458	("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStreamShared->u8SD, u32LPIB, pStreamShared->u32CBL));
2459
2460	u32LPIB = RT_MIN(u32LPIB, pStreamShared->u32CBL);
2461
2462	LogFlowFunc(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
2463	pStreamShared->u8SD, u32LPIB, pThis->fDMAPosition));
2464
2465	/* Update LPIB in any case. */
2466	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = u32LPIB;
2467
2468	/* Do we need to tell the current DMA position? */
2469	if (pThis->fDMAPosition)
2470	{
2471	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
2472	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
2473	(void *)&u32LPIB, sizeof(uint32_t));
2474	AssertRC(rc2);
2475	}
2476
2477	return u32LPIB;
2478	}
2479	#endif
2480
2481	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2482	/**
2483	* Registers access handlers for a stream's BDLE DMA accesses.
2484	*
2485	* @returns true if registration was successful, false if not.
2486	* @param pStream HDA stream to register BDLE access handlers for.
2487	*/
2488	bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream)
2489	{
2490	/* At least LVI and the BDL base must be set. */
2491	if ( !pStreamShared->u16LVI
2492	\|\| !pStreamShared->u64BDLBase)
2493	{
2494	return false;
2495	}
2496
2497	hdaR3StreamUnregisterDMAHandlers(pStream);
2498
2499	LogFunc(("Registering ...\n"));
2500
2501	int rc = VINF_SUCCESS;
2502
2503	/*
2504	* Create BDLE ranges.
2505	*/
2506
2507	struct BDLERANGE
2508	{
2509	RTGCPHYS uAddr;
2510	uint32_t uSize;
2511	} arrRanges[16]; /** @todo Use a define. */
2512
2513	size_t cRanges = 0;
2514
2515	for (uint16_t i = 0; i < pStreamShared->u16LVI + 1; i++)
2516	{
2517	HDABDLE BDLE;
2518	rc = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, i /* Index */);
2519	if (RT_FAILURE(rc))
2520	break;
2521
2522	bool fAddRange = true;
2523	BDLERANGE *pRange;
2524
2525	if (cRanges)
2526	{
2527	pRange = &arrRanges[cRanges - 1];
2528
2529	/* Is the current range a direct neighbor of the current BLDE? */
2530	if ((pRange->uAddr + pRange->uSize) == BDLE.Desc.u64BufAddr)
2531	{
2532	/* Expand the current range by the current BDLE's size. */
2533	pRange->uSize += BDLE.Desc.u32BufSize;
2534
2535	/* Adding a new range in this case is not needed anymore. */
2536	fAddRange = false;
2537
2538	LogFunc(("Expanding range %zu by %RU32 (%RU32 total now)\n", cRanges - 1, BDLE.Desc.u32BufSize, pRange->uSize));
2539	}
2540	}
2541
2542	/* Do we need to add a new range? */
2543	if ( fAddRange
2544	&& cRanges < RT_ELEMENTS(arrRanges))
2545	{
2546	pRange = &arrRanges[cRanges];
2547
2548	pRange->uAddr = BDLE.Desc.u64BufAddr;
2549	pRange->uSize = BDLE.Desc.u32BufSize;
2550
2551	LogFunc(("Adding range %zu - 0x%x (%RU32)\n", cRanges, pRange->uAddr, pRange->uSize));
2552
2553	cRanges++;
2554	}
2555	}
2556
2557	LogFunc(("%zu ranges total\n", cRanges));
2558
2559	/*
2560	* Register all ranges as DMA access handlers.
2561	*/
2562
2563	for (size_t i = 0; i < cRanges; i++)
2564	{
2565	BDLERANGE *pRange = &arrRanges[i];
2566
2567	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)RTMemAllocZ(sizeof(HDADMAACCESSHANDLER));
2568	if (!pHandler)
2569	{
2570	rc = VERR_NO_MEMORY;
2571	break;
2572	}
2573
2574	RTListAppend(&pStream->State.lstDMAHandlers, &pHandler->Node);
2575
2576	pHandler->pStream = pStream; /* Save a back reference to the owner. */
2577
2578	char szDesc[32];
2579	RTStrPrintf(szDesc, sizeof(szDesc), "HDA[SD%RU8 - RANGE%02zu]", pStream->u8SD, i);
2580
2581	int rc2 = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
2582	hdaDMAAccessHandler,
2583	NULL, NULL, NULL,
2584	NULL, NULL, NULL,
2585	szDesc, &pHandler->hAccessHandlerType);
2586	AssertRCBreak(rc2);
2587
2588	pHandler->BDLEAddr = pRange->uAddr;
2589	pHandler->BDLESize = pRange->uSize;
2590
2591	/* Get first and last pages of the BDLE range. */
2592	RTGCPHYS pgFirst = pRange->uAddr & ~PAGE_OFFSET_MASK;
2593	RTGCPHYS pgLast = RT_ALIGN(pgFirst + pRange->uSize, PAGE_SIZE);
2594
2595	/* Calculate the region size (in pages). */
2596	RTGCPHYS regionSize = RT_ALIGN(pgLast - pgFirst, PAGE_SIZE);
2597
2598	pHandler->GCPhysFirst = pgFirst;
2599	pHandler->GCPhysLast = pHandler->GCPhysFirst + (regionSize - 1);
2600
2601	LogFunc(("\tRegistering region '%s': 0x%x - 0x%x (region size: %zu)\n",
2602	szDesc, pHandler->GCPhysFirst, pHandler->GCPhysLast, regionSize));
2603	LogFunc(("\tBDLE @ 0x%x - 0x%x (%RU32)\n",
2604	pHandler->BDLEAddr, pHandler->BDLEAddr + pHandler->BDLESize, pHandler->BDLESize));
2605
2606	rc2 = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2607	pHandler->GCPhysFirst, pHandler->GCPhysLast,
2608	pHandler->hAccessHandlerType, pHandler, NIL_RTR0PTR, NIL_RTRCPTR,
2609	szDesc);
2610	AssertRCBreak(rc2);
2611
2612	pHandler->fRegistered = true;
2613	}
2614
2615	LogFunc(("Registration ended with rc=%Rrc\n", rc));
2616
2617	return RT_SUCCESS(rc);
2618	}
2619
2620	/**
2621	* Unregisters access handlers of a stream's BDLEs.
2622	*
2623	* @param pStream HDA stream to unregister BDLE access handlers for.
2624	*/
2625	void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream)
2626	{
2627	LogFunc(("\n"));
2628
2629	PHDADMAACCESSHANDLER pHandler, pHandlerNext;
2630	RTListForEachSafe(&pStream->State.lstDMAHandlers, pHandler, pHandlerNext, HDADMAACCESSHANDLER, Node)
2631	{
2632	if (!pHandler->fRegistered) /* Handler not registered? Skip. */
2633	continue;
2634
2635	LogFunc(("Unregistering 0x%x - 0x%x (%zu)\n",
2636	pHandler->GCPhysFirst, pHandler->GCPhysLast, pHandler->GCPhysLast - pHandler->GCPhysFirst));
2637
2638	int rc2 = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2639	pHandler->GCPhysFirst);
2640	AssertRC(rc2);
2641
2642	RTListNodeRemove(&pHandler->Node);
2643
2644	RTMemFree(pHandler);
2645	pHandler = NULL;
2646	}
2647
2648	Assert(RTListIsEmpty(&pStream->State.lstDMAHandlers));
2649	}
2650
2651	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2652	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2653
2654	/**
2655	* @callback_method_impl{FNRTTHREAD,
2656	* Asynchronous I/O thread for a HDA stream.
2657	*
2658	* This will do the heavy lifting work for us as soon as it's getting notified
2659	* by another thread.}
2660	*/
2661	static DECLCALLBACK(int) hdaR3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
2662	{
2663	PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2664	PHDASTREAMSTATEAIO const pAIO = &pStreamR3->State.AIO;
2665	PHDASTATE const pThis = pStreamR3->pHDAStateShared;
2666	PHDASTATER3 const pThisCC = pStreamR3->pHDAStateR3;
2667	PPDMDEVINS const pDevIns = pThisCC->pDevIns;
2668	PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2669	Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2670	Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2671
2672	/* Signal parent thread that we've started */
2673	ASMAtomicWriteBool(&pAIO->fStarted, true);
2674	RTThreadUserSignal(hThreadSelf);
2675
2676	LogFunc(("[SD%RU8] Started\n", pStreamShared->u8SD));
2677
2678	while (!ASMAtomicReadBool(&pAIO->fShutdown))
2679	{
2680	int rc2 = RTSemEventWait(pAIO->hEvent, RT_INDEFINITE_WAIT);
2681	if (RT_SUCCESS(rc2))
2682	{ /* likely */ }
2683	else
2684	break;
2685
2686	if (!ASMAtomicReadBool(&pAIO->fShutdown))
2687	{ /* likely */ }
2688	else
2689	break;
2690
2691	rc2 = RTCritSectEnter(&pAIO->CritSect);
2692	AssertRC(rc2);
2693	if (RT_SUCCESS(rc2))
2694	{
2695	if (pAIO->fEnabled)
2696	hdaR3StreamUpdate(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, false /* fInTimer */);
2697
2698	int rc3 = RTCritSectLeave(&pAIO->CritSect);
2699	AssertRC(rc3);
2700	}
2701	}
2702
2703	LogFunc(("[SD%RU8] Ended\n", pStreamShared->u8SD));
2704	ASMAtomicWriteBool(&pAIO->fStarted, false);
2705
2706	return VINF_SUCCESS;
2707	}
2708
2709	/**
2710	* Creates the async I/O thread for a specific HDA audio stream.
2711	*
2712	* @returns IPRT status code.
2713	* @param pStreamR3 HDA audio stream to create the async I/O thread for.
2714	*/
2715	int hdaR3StreamAsyncIOCreate(PHDASTREAMR3 pStreamR3)
2716	{
2717	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2718
2719	int rc;
2720
2721	if (!ASMAtomicReadBool(&pAIO->fStarted))
2722	{
2723	pAIO->fShutdown = false;
2724	pAIO->fEnabled = true; /* Enabled by default. */
2725
2726	rc = RTSemEventCreate(&pAIO->hEvent);
2727	if (RT_SUCCESS(rc))
2728	{
2729	rc = RTCritSectInit(&pAIO->CritSect);
2730	if (RT_SUCCESS(rc))
2731	{
2732	rc = RTThreadCreateF(&pAIO->hThread, hdaR3StreamAsyncIOThread, pStreamR3, 0 /cbStack/,
2733	RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "hdaAIO%RU8", pStreamR3->u8SD);
2734	if (RT_SUCCESS(rc))
2735	rc = RTThreadUserWait(pAIO->hThread, 10 * 1000 /* 10s timeout */);
2736	}
2737	}
2738	}
2739	else
2740	rc = VINF_SUCCESS;
2741
2742	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
2743	return rc;
2744	}
2745
2746	/**
2747	* Destroys the async I/O thread of a specific HDA audio stream.
2748	*
2749	* @returns IPRT status code.
2750	* @param pStreamR3 HDA audio stream to destroy the async I/O thread for.
2751	*/
2752	static int hdaR3StreamAsyncIODestroy(PHDASTREAMR3 pStreamR3)
2753	{
2754	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2755
2756	if (!ASMAtomicReadBool(&pAIO->fStarted))
2757	return VINF_SUCCESS;
2758
2759	ASMAtomicWriteBool(&pAIO->fShutdown, true);
2760
2761	int rc = hdaR3StreamAsyncIONotify(pStreamR3);
2762	AssertRC(rc);
2763
2764	int rcThread;
2765	rc = RTThreadWait(pAIO->hThread, 30 * 1000 /* 30s timeout */, &rcThread);
2766	LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
2767
2768	if (RT_SUCCESS(rc))
2769	{
2770	pAIO->hThread = NIL_RTTHREAD;
2771
2772	rc = RTCritSectDelete(&pAIO->CritSect);
2773	AssertRC(rc);
2774
2775	rc = RTSemEventDestroy(pAIO->hEvent);
2776	AssertRC(rc);
2777	pAIO->hEvent = NIL_RTSEMEVENT;
2778
2779	pAIO->fStarted = false;
2780	pAIO->fShutdown = false;
2781	pAIO->fEnabled = false;
2782	}
2783
2784	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
2785	return rc;
2786	}
2787
2788	/**
2789	* Lets the stream's async I/O thread know that there is some data to process.
2790	*
2791	* @returns IPRT status code.
2792	* @param pStreamR3 HDA stream to notify async I/O thread for.
2793	*/
2794	int hdaR3StreamAsyncIONotify(PHDASTREAMR3 pStreamR3)
2795	{
2796	return RTSemEventSignal(pStreamR3->State.AIO.hEvent);
2797	}
2798
2799	/**
2800	* Locks the async I/O thread of a specific HDA audio stream.
2801	*
2802	* @param pStreamR3 HDA stream to lock async I/O thread for.
2803	*/
2804	void hdaR3StreamAsyncIOLock(PHDASTREAMR3 pStreamR3)
2805	{
2806	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2807
2808	if (!ASMAtomicReadBool(&pAIO->fStarted))
2809	return;
2810
2811	int rc2 = RTCritSectEnter(&pAIO->CritSect);
2812	AssertRC(rc2);
2813	}
2814
2815	/**
2816	* Unlocks the async I/O thread of a specific HDA audio stream.
2817	*
2818	* @param pStreamR3 HDA stream to unlock async I/O thread for.
2819	*/
2820	void hdaR3StreamAsyncIOUnlock(PHDASTREAMR3 pStreamR3)
2821	{
2822	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2823
2824	if (!ASMAtomicReadBool(&pAIO->fStarted))
2825	return;
2826
2827	int rc2 = RTCritSectLeave(&pAIO->CritSect);
2828	AssertRC(rc2);
2829	}
2830
2831	/**
2832	* Enables (resumes) or disables (pauses) the async I/O thread.
2833	*
2834	* @param pStreamR3 HDA stream to enable/disable async I/O thread for.
2835	* @param fEnable Whether to enable or disable the I/O thread.
2836	*
2837	* @remarks Does not do locking.
2838	*/
2839	void hdaR3StreamAsyncIOEnable(PHDASTREAMR3 pStreamR3, bool fEnable)
2840	{
2841	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2842	ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
2843	}
2844
2845	# endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
2846	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Audio/HDAStream.cpp@ 88158

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