HDAStream.cpp@ 88163

Last change on this file since 88163 was 88163, checked in by vboxsync, 4 years ago
DevHDA: windows build fix. bugref:9890:
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1	/* $Id: HDAStream.cpp 88163 2021-03-17 17:09:22Z vboxsync $ */
2	/** @file
3	* HDAStream.cpp - Stream functions for HD Audio.
4	*/
5
6	/*
7	* Copyright (C) 2017-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_HDA
23	#include <VBox/log.h>
24
25	#include <iprt/mem.h>
26	#include <iprt/semaphore.h>
27
28	#include <VBox/AssertGuest.h>
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/vmm/pdmaudioinline.h>
32
33	#include "DrvAudio.h"
34
35	#include "DevHDA.h"
36	#include "HDAStream.h"
37
38	#ifdef VBOX_WITH_DTRACE
39	# include "dtrace/VBoxDD.h"
40	#endif
41
42	#ifdef IN_RING3 /* whole file */
43
44
45	/*********************************************************************************************************************************
46	* Internal Functions *
47	*********************************************************************************************************************************/
48	static void hdaR3StreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
49
50	static int hdaR3StreamAsyncIODestroy(PHDASTREAMR3 pStreamR3);
51
52
53
54	/**
55	* Creates an HDA stream.
56	*
57	* @returns IPRT status code.
58	* @param pStreamShared The HDA stream to construct - shared bits.
59	* @param pStreamR3 The HDA stream to construct - ring-3 bits.
60	* @param pThis The shared HDA device instance.
61	* @param pThisCC The ring-3 HDA device instance.
62	* @param uSD Stream descriptor number to assign.
63	*/
64	int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
65	{
66	int rc;
67
68	pStreamR3->u8SD = uSD;
69	pStreamShared->u8SD = uSD;
70	pStreamR3->pMixSink = NULL;
71	pStreamR3->pHDAStateShared = pThis;
72	pStreamR3->pHDAStateR3 = pThisCC;
73	Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
74
75	pStreamShared->State.fInReset = false;
76	pStreamShared->State.fRunning = false;
77	#ifdef HDA_USE_DMA_ACCESS_HANDLER
78	RTListInit(&pStreamR3->State.lstDMAHandlers);
79	#endif
80
81	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
82	AssertPtr(pStreamR3->pHDAStateR3);
83	AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
84	rc = PDMDevHlpCritSectInit(pStreamR3->pHDAStateR3->pDevIns, &pStreamShared->CritSect,
85	RT_SRC_POS, "hda_sd#%RU8", pStreamShared->u8SD);
86	AssertRCReturn(rc, rc);
87	#endif
88
89	rc = hdaR3StreamPeriodCreate(&pStreamShared->State.Period);
90	AssertRCReturn(rc, rc);
91
92	#ifdef DEBUG
93	rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
94	AssertRCReturn(rc, rc);
95	#endif
96
97	const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
98
99	if (fIsInput)
100	{
101	pStreamShared->State.Cfg.u.enmSrc = PDMAUDIORECSRC_UNKNOWN;
102	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
103	}
104	else
105	{
106	pStreamShared->State.Cfg.u.enmDst = PDMAUDIOPLAYBACKDST_UNKNOWN;
107	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
108	}
109
110	pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
111
112	if (pStreamR3->Dbg.Runtime.fEnabled)
113	{
114	char szFile[64];
115	char szPath[RTPATH_MAX];
116
117	/* pFileStream */
118	if (fIsInput)
119	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
120	else
121	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
122
123	int rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
124	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
125	AssertRC(rc2);
126
127	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
128	AssertRC(rc2);
129
130	/* pFileDMARaw */
131	if (fIsInput)
132	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
133	else
134	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
135
136	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
137	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
138	AssertRC(rc2);
139
140	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
141	AssertRC(rc2);
142
143	/* pFileDMAMapped */
144	if (fIsInput)
145	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
146	else
147	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
148
149	rc2 = DrvAudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
150	0 /* uInst */, PDMAUDIOFILETYPE_WAV, PDMAUDIOFILENAME_FLAGS_NONE);
151	AssertRC(rc2);
152
153	rc2 = DrvAudioHlpFileCreate(PDMAUDIOFILETYPE_WAV, szPath, PDMAUDIOFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
154	AssertRC(rc2);
155
156	/* Delete stale debugging files from a former run. */
157	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
158	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
159	DrvAudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
160	}
161
162	return rc;
163	}
164
165	/**
166	* Destroys an HDA stream.
167	*
168	* @param pStreamShared The HDA stream to destroy - shared bits.
169	* @param pStreamR3 The HDA stream to destroy - ring-3 bits.
170	*/
171	void hdaR3StreamDestroy(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
172	{
173	LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamShared->u8SD));
174
175	hdaR3StreamMapDestroy(&pStreamR3->State.Mapping);
176
177	int rc2;
178
179	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
180	rc2 = hdaR3StreamAsyncIODestroy(pStreamR3);
181	AssertRC(rc2);
182	#endif
183
184	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
185	if (PDMCritSectIsInitialized(&pStreamShared->CritSect))
186	{
187	rc2 = PDMR3CritSectDelete(&pStreamShared->CritSect);
188	AssertRC(rc2);
189	}
190	#endif
191
192	if (pStreamR3->State.pCircBuf)
193	{
194	RTCircBufDestroy(pStreamR3->State.pCircBuf);
195	pStreamR3->State.pCircBuf = NULL;
196	}
197
198	hdaR3StreamPeriodDestroy(&pStreamShared->State.Period);
199
200	#ifdef DEBUG
201	if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
202	{
203	rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
204	AssertRC(rc2);
205	}
206	#endif
207
208	if (pStreamR3->Dbg.Runtime.fEnabled)
209	{
210	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
211	pStreamR3->Dbg.Runtime.pFileStream = NULL;
212
213	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
214	pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
215
216	DrvAudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
217	pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
218	}
219
220	LogFlowFuncLeave();
221	}
222
223
224	/**
225	* Appends a item to the scheduler.
226	*
227	* @returns VBox status code.
228	* @param pStreamShared The stream which scheduler should be modified.
229	* @param cbCur The period length in guest bytes.
230	* @param cbMaxPeriod The max period in guest bytes.
231	* @param idxLastBdle The last BDLE in the period.
232	* @param pHostProps The host PCM properties.
233	* @param pGuestProps The guest PCM properties.
234	* @param pcbBorrow Where to account for bytes borrowed across buffers
235	* to align scheduling items on frame boundraries.
236	*/
237	static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod, uint32_t idxLastBdle,
238	PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps, uint32_t *pcbBorrow)
239	{
240	/* Check that we've got room (shouldn't ever be a problem). */
241	size_t idx = pStreamShared->State.cSchedule;
242	AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
243
244	/* Figure out the BDLE range for this period. */
245	uint32_t const idxFirstBdle = idx == 0 ? 0
246	: pStreamShared->State.aSchedule[idx - 1].idxFirst
247	+ pStreamShared->State.aSchedule[idx - 1].cEntries;
248
249	pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
250	pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
251	? idxLastBdle - idxFirstBdle + 1
252	: pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
253
254	/* Deal with borrowing due to unaligned IOC buffers. */
255	uint32_t const cbBorrowed = *pcbBorrow;
256	if (cbBorrowed < cbCur)
257	cbCur -= cbBorrowed;
258	else
259	{
260	/* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
261	ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
262	pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
263	LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
264	pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
265	return VERR_OUT_OF_RANGE;
266	}
267
268	uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbCur);
269	*pcbBorrow = cbCurAligned - cbCur;
270
271	/* Do we need to split up the period? */
272	if (cbCurAligned <= cbMaxPeriod)
273	{
274	uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
275	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
276	pStreamShared->State.aSchedule[idx].cLoops = 1;
277	}
278	else
279	{
280	/* Reduce till we've below the threshold. */
281	uint32_t cbLoop = cbCurAligned;
282	do
283	cbLoop = cbCurAligned / 2;
284	while (cbLoop > cbMaxPeriod);
285	cbLoop = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbLoop);
286
287	/* Complete the scheduling item. */
288	uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbLoop));
289	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
290	pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
291
292	/* If there is a remainder, add it as a separate entry (this is
293	why the schedule must be more than twice the size of the BDL).*/
294	cbCurAligned %= cbLoop;
295	if (cbCurAligned)
296	{
297	pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
298	idx++;
299	cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
300	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
301	pStreamShared->State.aSchedule[idx].cLoops = 1;
302	}
303	}
304
305	/* Done. */
306	pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
307
308	return VINF_SUCCESS;
309	}
310
311	/**
312	* Creates the DMA timer schedule for the stream
313	*
314	* This is called from the stream setup code.
315	*
316	* @returns VBox status code.
317	* @param pStreamShared The stream to create a schedule for. The BDL
318	* must be loaded.
319	* @param cSegments Number of BDL segments.
320	* @param cBufferIrqs Number of the BDLEs with IOC=1.
321	* @param cbTotal The total BDL length in guest bytes.
322	* @param cbMaxPeriod Max period in guest bytes. This is in case the
323	* guest want to play the whole "Der Ring des
324	* Nibelungen" cycle in one go.
325	* @param cTimerTicksPerSec The DMA timer frequency.
326	* @param pHostProps The host PCM properties.
327	* @param pGuestProps The guest PCM properties.
328	*/
329	static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
330	uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec,
331	PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps)
332	{
333	int rc;
334
335	/*
336	* Reset scheduling state.
337	*/
338	RT_ZERO(pStreamShared->State.aSchedule);
339	pStreamShared->State.cSchedule = 0;
340	pStreamShared->State.cSchedulePrologue = 0;
341	pStreamShared->State.idxSchedule = 0;
342	pStreamShared->State.idxScheduleLoop = 0;
343
344	/*
345	* Do the basic schedule compilation.
346	*/
347	uint32_t cPotentialPrologue = 0;
348	uint32_t cbBorrow = 0;
349	uint32_t cbCur = 0;
350	pStreamShared->State.aSchedule[0].idxFirst = 0;
351	for (uint32_t i = 0; i < cSegments; i++)
352	{
353	cbCur += pStreamShared->State.aBdl[i].cb;
354	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
355	{
356	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
357	ASSERT_GUEST_RC_RETURN(rc, rc);
358
359	if (cPotentialPrologue == 0)
360	cPotentialPrologue = pStreamShared->State.cSchedule;
361	cbCur = 0;
362	}
363	}
364	AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
365	pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
366	VERR_INTERNAL_ERROR_3);
367
368	/*
369	* Deal with any loose ends.
370	*/
371	if (cbCur && cBufferIrqs == 0)
372	{
373	/* No IOC. Split the period in two. */
374	Assert(cbCur == cbTotal);
375	cbCur = PDMAudioPropsFloorBytesToFrame(pGuestProps, cbCur / 2);
376	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, cSegments, pHostProps, pGuestProps, &cbBorrow);
377	ASSERT_GUEST_RC_RETURN(rc, rc);
378
379	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbTotal - cbCur, cbMaxPeriod, cSegments,
380	pHostProps, pGuestProps, &cbBorrow);
381	ASSERT_GUEST_RC_RETURN(rc, rc);
382	Assert(cbBorrow == 0);
383	}
384	else if (cbCur)
385	{
386	/* The last BDLE didn't have IOC set, so we must continue processing
387	from the start till we hit one that has. */
388	uint32_t i;
389	for (i = 0; i < cSegments; i++)
390	{
391	cbCur += pStreamShared->State.aBdl[i].cb;
392	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
393	break;
394	}
395	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
396	ASSERT_GUEST_RC_RETURN(rc, rc);
397
398	/* The initial scheduling items covering the wrap around area are
399	considered a prologue and must not repeated later. */
400	Assert(cPotentialPrologue);
401	pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
402	}
403
404	/*
405	* If there is just one BDLE with IOC set, we have to make sure
406	* we've got at least two periods scheduled, otherwise there is
407	* a very good chance the guest will overwrite the start of the
408	* buffer before we ever get around to reading it.
409	*/
410	if (cBufferIrqs == 1)
411	{
412	uint32_t i = pStreamShared->State.cSchedulePrologue;
413	Assert(i < pStreamShared->State.cSchedule);
414	if ( i + 1 == pStreamShared->State.cSchedule
415	&& pStreamShared->State.aSchedule[i].cLoops == 1)
416	{
417	uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pHostProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
418	uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
419	pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
420	if (cbFirstHalf == cbOtherHalf)
421	pStreamShared->State.aSchedule[i].cLoops = 2;
422	else
423	{
424	pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
425	pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
426	pStreamShared->State.cSchedule++;
427	}
428	}
429	}
430
431	/*
432	* Go over the schduling entries and calculate the timer ticks for each period.
433	*/
434	LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
435	pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
436	uint64_t const cbHostPerSec = PDMAudioPropsFramesToBytes(pHostProps, pHostProps->uHz);
437	for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
438	{
439	uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod,
440	cbHostPerSec);
441	AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
442	pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
443	LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
444	pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
445	pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
446	}
447
448	return VINF_SUCCESS;
449	}
450
451
452	/**
453	* Sets up ((re-)iniitalizes) an HDA stream.
454	*
455	* @returns IPRT status code. VINF_NO_CHANGE if the stream does not need
456	* be set-up again because the stream's (hardware) parameters did
457	* not change.
458	* @param pDevIns The device instance.
459	* @param pThis The shared HDA device state (for HW register
460	* parameters).
461	* @param pStreamShared HDA stream to set up, shared portion.
462	* @param pStreamR3 HDA stream to set up, ring-3 portion.
463	* @param uSD Stream descriptor number to assign it.
464	*/
465	int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
466	{
467	/* This must be valid all times. */
468	AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
469
470	/* These member can only change on data corruption, despite what the code does further down (bird). */
471	AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
472	AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
473
474	const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
475	HDA_STREAM_REG(pThis, BDPU, uSD));
476	const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
477	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
478	const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
479	uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
480	const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
481
482	/* Is the bare minimum set of registers configured for the stream?
483	* If not, bail out early, as there's nothing to do here for us (yet). */
484	if ( !u64BDLBase
485	\|\| !u16LVI
486	\|\| !u32CBL
487	\|\| !u8FIFOS
488	\|\| !u8FIFOW
489	\|\| !u16FMT)
490	{
491	LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
492	return VINF_SUCCESS;
493	}
494
495	PDMAUDIOPCMPROPS HostProps;
496	int rc = hdaR3SDFMTToPCMProps(u16FMT, &HostProps);
497	if (RT_FAILURE(rc))
498	{
499	LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
500	return rc;
501	}
502
503	/*
504	* Initialize the stream mapping in any case, regardless if
505	* we support surround audio or not. This is needed to handle
506	* the supported channels within a single audio stream, e.g. mono/stereo.
507	*
508	* In other words, the stream mapping always knows the real
509	* number of channels in a single audio stream.
510	*/
511	/** @todo r=bird: this is not done at the wrong time. We don't have the host
512	* output side set up yet, so we cannot really do proper mapping setup.
513	* However, we really need this further down when we configure the internal DMA
514	* buffer size. For now we just assume it's all stereo on the host side.
515	* This is not compatible with microphone support. */
516	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
517	# error "Implement me!"
518	# endif
519	rc = hdaR3StreamMapInit(&pStreamR3->State.Mapping, 2 /cHostChannels/, &HostProps);
520	AssertRCReturn(rc, rc);
521
522	ASSERT_GUEST_LOGREL_MSG_RETURN( pStreamR3->State.Mapping.cbGuestFrame > 0
523	&& u32CBL % pStreamR3->State.Mapping.cbGuestFrame == 0,
524	("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
525	uSD, u32CBL, pStreamR3->State.Mapping.cbGuestFrame),
526	VERR_INVALID_PARAMETER);
527
528	/* Make sure the guest behaves regarding the stream's FIFO. */
529	ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
530	("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
531	u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
532
533	pStreamShared->u8SD = uSD;
534
535	/* Update all register copies so that we later know that something has changed. */
536	pStreamShared->u64BDLBase = u64BDLBase;
537	pStreamShared->u16LVI = u16LVI;
538	pStreamShared->u32CBL = u32CBL;
539	pStreamShared->u8FIFOS = u8FIFOS;
540	pStreamShared->u8FIFOW = u8FIFOW;
541	pStreamShared->u16FMT = u16FMT;
542
543	PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
544	pCfg->Props = HostProps;
545
546	/* Set the stream's direction. */
547	pCfg->enmDir = hdaGetDirFromSD(uSD);
548
549	/* The the stream's name, based on the direction. */
550	switch (pCfg->enmDir)
551	{
552	case PDMAUDIODIR_IN:
553	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
554	# error "Implement me!"
555	# else
556	pCfg->u.enmSrc = PDMAUDIORECSRC_LINE;
557	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
558	RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
559	# endif
560	break;
561
562	case PDMAUDIODIR_OUT:
563	/* Destination(s) will be set in hdaR3AddStreamOut(),
564	* based on the channels / stream layout. */
565	break;
566
567	default:
568	AssertFailedReturn(VERR_NOT_SUPPORTED);
569	break;
570	}
571
572	LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n",
573	uSD, pStreamShared->u64BDLBase, pStreamShared->u32CBL,
574	PDMAudioPropsBytesToMilli(&pStreamR3->State.Mapping.GuestProps, pStreamShared->u32CBL)));
575
576
577	/*
578	* Load the buffer descriptor list.
579	*
580	* Section 3.6.2 states that "the BDL should not be modified unless the RUN
581	* bit is 0", so it should be within the specs to read it once here and not
582	* re-read any BDLEs later.
583	*/
584	/* Reset BDL state. */
585	RT_ZERO(pStreamShared->State.aBdl);
586	pStreamShared->State.offCurBdle = 0;
587	pStreamShared->State.idxCurBdle = 0;
588
589	uint32_t /const/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
590	if (cTransferFragments <= 1)
591	LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
592	AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
593	pStreamShared->State.cBdles = cTransferFragments;
594
595	/* Load them. */
596	rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
597	sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
598	AssertRC(rc);
599
600	/* Check what we just loaded. Refuse overly large buffer lists. */
601	uint64_t cbTotal = 0;
602	uint32_t cBufferIrqs = 0;
603	for (uint32_t i = 0; i < cTransferFragments; i++)
604	{
605	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
606	cBufferIrqs++;
607	cbTotal += pStreamShared->State.aBdl[i].cb;
608	}
609	ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
610	LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
611	uSD, cbTotal, cbTotal)),
612	VERR_NOT_SUPPORTED);
613	ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
614	LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
615	uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
616	VERR_NOT_SUPPORTED);
617
618	/*
619	* Create a DMA timer schedule.
620	*/
621	rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
622	PDMAudioPropsMilliToBytes(&pStreamR3->State.Mapping.GuestProps, 100 /** @todo make configurable */),
623	PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer),
624	&HostProps, &pStreamR3->State.Mapping.GuestProps);
625	if (RT_FAILURE(rc))
626	return rc;
627
628	pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[0].cbPeriod;
629
630	/*
631	* Calculate the transfer Hz for use in the circular buffer calculation.
632	*/
633	uint32_t cbMaxPeriod = 0;
634	uint32_t cbMinPeriod = UINT32_MAX;
635	uint32_t cPeriods = 0;
636	for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
637	{
638	uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
639	cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
640	cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
641	cPeriods += pStreamShared->State.aSchedule[i].cLoops;
642	}
643	uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
644	4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
645	unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
646	LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
647	uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
648	uTransferHz /= 1000;
649
650	if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
651	LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
652	uSD, uTransferHz));
653
654	pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
655
656	/* For input streams we must determin a pre-buffering requirement.
657	We use the initial delay as a basis here, though we must have at
658	least two max periods worth of data queued up due to the way we
659	work the AIO thread. */
660	pStreamShared->State.fInputPreBuffered = false;
661	pStreamShared->State.cbInputPreBuffer = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay);
662	pStreamShared->State.cbInputPreBuffer = RT_MIN(cbMaxPeriod * 2, pStreamShared->State.cbInputPreBuffer);
663
664	/*
665	* Set up data transfer stuff.
666	*/
667
668	/* Assign the global device rate to the stream I/O timer as default. */
669	pStreamShared->State.uTimerIoHz = pThis->uTimerHz;
670	ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.uTimerIoHz,
671	("I/O timer Hz rate for stream #%RU8 is invalid\n", uSD),
672	pStreamShared->State.uTimerIoHz = HDA_TIMER_HZ_DEFAULT);
673
674	/* Set I/O scheduling hint for the backends. */
675	/** @todo r=bird: This is in the 'Device' portion, yet it's used by the
676	* audio driver. You would think stuff in the 'Device' part is
677	* private to the device. */
678	pCfg->Device.cMsSchedulingHint = RT_MS_1SEC / pStreamShared->State.uTimerIoHz;
679	LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
680
681
682	/* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
683	hdaR3StreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
684
685	#ifdef LOG_ENABLED
686	hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
687	#endif
688
689	/*
690	* Set up internal ring buffer.
691	*/
692
693	/* (Re-)Allocate the stream's internal DMA buffer,
694	* based on the timing and PCM properties we just got above. */
695	if (pStreamR3->State.pCircBuf)
696	{
697	RTCircBufDestroy(pStreamR3->State.pCircBuf);
698	pStreamR3->State.pCircBuf = NULL;
699	}
700	pStreamR3->State.offWrite = 0;
701	pStreamR3->State.offRead = 0;
702
703	/*
704	* The default internal ring buffer size must be:
705	*
706	* - Large enough for at least three periodic DMA transfers.
707	*
708	* It is critically important that we don't experience underruns
709	* in the DMA OUT code, because it will cause the buffer processing
710	* to get skewed and possibly overlap with what the guest is updating.
711	* At the time of writing (2021-03-05) there is no code for getting
712	* back into sync there.
713	*
714	* - Large enough for at least three I/O scheduling hints.
715	*
716	* We want to lag behind a DMA period or two, but there must be
717	* sufficent space for the AIO thread to get schedule and shuffle
718	* data thru the mixer and onto the host audio hardware.
719	*
720	* - Both above with plenty to spare.
721	*
722	* So, just take the longest of the two periods and multipling it by 6.
723	* We aren't not talking about very large base buffers heres, so size isn't
724	* an issue.
725	*
726	* Note: Use pCfg->Props as PCM properties here, as we only want to store the
727	* samples we actually need, in other words, skipping the interleaved
728	* channels we don't support / need to save space.
729	*/
730	uint32_t msCircBuf = RT_MS_1SEC * 6 / RT_MIN(uTransferHz, pStreamShared->State.uTimerIoHz);
731	msCircBuf = RT_MAX(msCircBuf, pThis->msInitialDelay + RT_MS_1SEC * 6 / uTransferHz);
732
733	uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBuf);
734	LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
735	uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
736
737	uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cbCircBufInMs : pThis->cbCircBufOutMs;
738	if (msCircBufCfg) /* Anything set via CFGM? */
739	{
740	cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
741	LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
742	uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
743	}
744
745	/* Serious paranoia: */
746	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % (pCfg->Props.cbSample * pCfg->Props.cChannels) == 0,
747	("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
748	cbCircBuf, uSD, pCfg->Props.cbSample * pCfg->Props.cChannels),
749	rc = VERR_INVALID_PARAMETER);
750	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
751	rc = VERR_INVALID_PARAMETER);
752	if (RT_SUCCESS(rc))
753	{
754	rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
755	if (RT_SUCCESS(rc))
756	{
757	/*
758	* Forward the timer frequency hint to TM as well for better accuracy on
759	* systems w/o preemption timers (also good for 'info timers').
760	*/
761	PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
762	}
763	}
764
765	if (RT_FAILURE(rc))
766	LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
767
768	#ifdef VBOX_WITH_DTRACE
769	VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
770	pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
771	pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
772	#endif
773	return rc;
774	}
775
776	/**
777	* Resets an HDA stream.
778	*
779	* @param pThis The shared HDA device state.
780	* @param pThisCC The ring-3 HDA device state.
781	* @param pStreamShared HDA stream to reset (shared).
782	* @param pStreamR3 HDA stream to reset (ring-3).
783	* @param uSD Stream descriptor (SD) number to use for this stream.
784	*/
785	void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
786	{
787	AssertPtr(pThis);
788	AssertPtr(pStreamShared);
789	AssertPtr(pStreamR3);
790	Assert(uSD < HDA_MAX_STREAMS);
791	AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
792
793	LogFunc(("[SD%RU8] Reset\n", uSD));
794
795	/*
796	* Set reset state.
797	*/
798	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
799	ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
800
801	/*
802	* Second, initialize the registers.
803	*/
804	/* See 6.2.33: Clear on reset. */
805	HDA_STREAM_REG(pThis, STS, uSD) = 0;
806	/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
807	* bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
808	HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 \| (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
809	/* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
810	HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
811	/* See 18.2.38: Always defaults to 0x4 (32 bytes). */
812	HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
813	HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
814	HDA_STREAM_REG(pThis, CBL, uSD) = 0;
815	HDA_STREAM_REG(pThis, LVI, uSD) = 0;
816	HDA_STREAM_REG(pThis, FMT, uSD) = 0;
817	HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
818	HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
819
820	#ifdef HDA_USE_DMA_ACCESS_HANDLER
821	hdaR3StreamUnregisterDMAHandlers(pThis, pStream);
822	#endif
823
824	/* Assign the default mixer sink to the stream. */
825	pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
826
827	/* Reset transfer stuff. */
828	pStreamShared->State.cTransferPendingInterrupts = 0;
829	pStreamShared->State.tsTransferLast = 0;
830	pStreamShared->State.tsTransferNext = 0;
831
832	/* Initialize timestamps. */
833	pStreamShared->State.tsLastTransferNs = 0;
834	pStreamShared->State.tsLastReadNs = 0;
835	pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
836	pStreamShared->State.tsStart = 0;
837
838	RT_ZERO(pStreamShared->State.aBdl);
839	RT_ZERO(pStreamShared->State.aSchedule);
840	pStreamShared->State.offCurBdle = 0;
841	pStreamShared->State.cBdles = 0;
842	pStreamShared->State.idxCurBdle = 0;
843	pStreamShared->State.cSchedulePrologue = 0;
844	pStreamShared->State.cSchedule = 0;
845	pStreamShared->State.idxSchedule = 0;
846	pStreamShared->State.idxScheduleLoop = 0;
847	pStreamShared->State.fInputPreBuffered = false;
848
849	if (pStreamR3->State.pCircBuf)
850	RTCircBufReset(pStreamR3->State.pCircBuf);
851	pStreamR3->State.offWrite = 0;
852	pStreamR3->State.offRead = 0;
853
854	/* Reset the stream's period. */
855	hdaR3StreamPeriodReset(&pStreamShared->State.Period);
856
857	#ifdef DEBUG
858	pStreamR3->Dbg.cReadsTotal = 0;
859	pStreamR3->Dbg.cbReadTotal = 0;
860	pStreamR3->Dbg.tsLastReadNs = 0;
861	pStreamR3->Dbg.cWritesTotal = 0;
862	pStreamR3->Dbg.cbWrittenTotal = 0;
863	pStreamR3->Dbg.cWritesHz = 0;
864	pStreamR3->Dbg.cbWrittenHz = 0;
865	pStreamR3->Dbg.tsWriteSlotBegin = 0;
866	#endif
867
868	/* Report that we're done resetting this stream. */
869	HDA_STREAM_REG(pThis, CTL, uSD) = 0;
870
871	#ifdef VBOX_WITH_DTRACE
872	VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
873	#endif
874	LogFunc(("[SD%RU8] Reset\n", uSD));
875
876	/* Exit reset mode. */
877	ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
878	}
879
880	/**
881	* Enables or disables an HDA audio stream.
882	*
883	* @returns IPRT status code.
884	* @param pStreamShared HDA stream to enable or disable - shared bits.
885	* @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
886	* @param fEnable Whether to enable or disble the stream.
887	*/
888	int hdaR3StreamEnable(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
889	{
890	AssertPtr(pStreamR3);
891	AssertPtr(pStreamShared);
892
893	LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
894
895	int rc = VINF_SUCCESS;
896
897	AUDMIXSINKCMD enmCmd = fEnable
898	? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
899
900	/* First, enable or disable the stream and the stream's sink, if any. */
901	if ( pStreamR3->pMixSink
902	&& pStreamR3->pMixSink->pMixSink)
903	rc = AudioMixerSinkCtl(pStreamR3->pMixSink->pMixSink, enmCmd);
904
905	if ( RT_SUCCESS(rc)
906	&& fEnable
907	&& pStreamR3->Dbg.Runtime.fEnabled)
908	{
909	Assert(DrvAudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
910
911	if (fEnable)
912	{
913	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
914	{
915	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
916	&pStreamShared->State.Cfg.Props);
917	AssertRC(rc2);
918	}
919
920	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
921	{
922	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
923	&pStreamShared->State.Cfg.Props);
924	AssertRC(rc2);
925	}
926
927	if (!DrvAudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
928	{
929	int rc2 = DrvAudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, PDMAUDIOFILE_DEFAULT_OPEN_FLAGS,
930	&pStreamShared->State.Cfg.Props);
931	AssertRC(rc2);
932	}
933	}
934	}
935
936	if (RT_SUCCESS(rc))
937	{
938	pStreamShared->State.fRunning = fEnable;
939	}
940
941	LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
942	return rc;
943	}
944
945	/**
946	* Marks the stream as started.
947	*
948	* Used after the stream has been enabled and the DMA timer has been armed.
949	*/
950	void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
951	{
952	pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
953	pStreamShared->State.tsStart = tsNow;
954	pStreamShared->State.tsAioDelayEnd = tsNow + PDMDevHlpTimerFromMilli(pDevIns, pStreamShared->hTimer, pThis->msInitialDelay);
955	Log3Func(("#%u: tsStart=%RU64 tsAioDelayEnd=%RU64 tsLastReadNs=%RU64\n", pStreamShared->u8SD,
956	pStreamShared->State.tsStart, pStreamShared->State.tsAioDelayEnd, pStreamShared->State.tsLastReadNs));
957
958	}
959
960	/**
961	* Marks the stream as stopped.
962	*/
963	void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
964	{
965	Log3Func(("#%u\n", pStreamShared->u8SD));
966	pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
967	}
968
969
970	#if 0 /* Not used atm. */
971	static uint32_t hdaR3StreamGetPosition(PHDASTATE pThis, PHDASTREAM pStreamShared)
972	{
973	return HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD);
974	}
975	#endif
976
977	/**
978	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
979	* setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
980	*
981	* @param pStreamShared HDA stream to update read / write position for (shared).
982	* @param pDevIns The device instance.
983	* @param pThis The shared HDA device state.
984	* @param uLPIB Absolute position (in bytes) to set current read / write position to.
985	*/
986	static void hdaR3StreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
987	{
988	AssertPtrReturnVoid(pStreamShared);
989	AssertReturnVoid (uLPIB <= pStreamShared->u32CBL); /* Make sure that we don't go out-of-bounds. */
990
991	Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
992
993	/* Update LPIB in any case. */
994	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
995
996	/* Do we need to tell the current DMA position? */
997	if (pThis->fDMAPosition)
998	{
999	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1000	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1001	(void *)&uLPIB, sizeof(uint32_t));
1002	AssertRC(rc2);
1003	}
1004	}
1005
1006	/**
1007	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1008	* adding a value to its associated LPIB register and DMA position buffer (if enabled).
1009	*
1010	* @note Handles automatic CBL wrap-around.
1011	*
1012	* @param pStreamShared HDA stream to update read / write position for (shared).
1013	* @param pDevIns The device instance.
1014	* @param pThis The shared HDA device state.
1015	* @param cbToAdd Position (in bytes) to add to the current read / write position.
1016	*/
1017	void hdaR3StreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1018	{
1019	if (cbToAdd) /* No need to update anything if 0. */
1020	{
1021	uint32_t const uCBL = pStreamShared->u32CBL;
1022	if (uCBL) /* paranoia */
1023	hdaR3StreamSetPositionAbs(pStreamShared, pDevIns, pThis,
1024	(HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd) % uCBL);
1025	}
1026	}
1027
1028	/**
1029	* Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1030	*
1031	* @returns Available data (in bytes).
1032	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
1033	*/
1034	static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1035	{
1036	AssertPtrReturn(pStreamR3, 0);
1037
1038	if (pStreamR3->State.pCircBuf)
1039	return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1040	return 0;
1041	}
1042
1043	/**
1044	* Retrieves the free size of audio data (in bytes) of a given HDA stream.
1045	*
1046	* @returns Free data (in bytes).
1047	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
1048	*/
1049	static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1050	{
1051	AssertPtrReturn(pStreamR3, 0);
1052
1053	if (pStreamR3->State.pCircBuf)
1054	return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1055	return 0;
1056	}
1057
1058	/**
1059	* Get the current address and number of bytes left in the current BDLE.
1060	*
1061	* @returns The current physical address.
1062	* @param pStreamShared The stream to check.
1063	* @param pcbLeft The number of bytes left at the returned address.
1064	*/
1065	DECLINLINE(RTGCPHYS) hdaR3StreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1066	{
1067	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1068	AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1069
1070	uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1071	uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1072	AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1073
1074	*pcbLeft = cbCurBdl - offCurBdle;
1075	return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1076	}
1077
1078	/**
1079	* Get the size of the current BDLE.
1080	*
1081	* @returns The size (in bytes).
1082	* @param pStreamShared The stream to check.
1083	*/
1084	DECLINLINE(RTGCPHYS) hdaR3StreamDmaBufGetSize(PHDASTREAM pStreamShared)
1085	{
1086	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1087	AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1088	return pStreamShared->State.aBdl[idxBdle].cb;
1089	}
1090
1091	/**
1092	* Checks if the current BDLE is completed.
1093	*
1094	* @retval true if complete
1095	* @retval false if not.
1096	* @param pStreamShared The stream to check.
1097	*/
1098	DECLINLINE(bool) hdaR3StreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1099	{
1100	uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1101	AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1102
1103	uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1104	uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1105	Assert(offCurBdle <= cbCurBdl);
1106	return offCurBdle >= cbCurBdl;
1107	}
1108
1109	/**
1110	* Checks if the current BDLE needs a completion IRQ.
1111	*
1112	* @retval true if IRQ is needed.
1113	* @retval false if not.
1114	* @param pStreamShared The stream to check.
1115	*/
1116	DECLINLINE(bool) hdaR3StreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1117	{
1118	uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1119	AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1120	return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1121	}
1122
1123	/**
1124	* Advances the DMA engine to the next BDLE.
1125	*
1126	* @param pStreamShared The stream which DMA engine is to be updated.
1127	*/
1128	DECLINLINE(void) hdaR3StreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1129	{
1130	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1131	Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1132
1133	if (idxBdle < pStreamShared->State.cBdles - 1)
1134	idxBdle++;
1135	else
1136	idxBdle = 0;
1137	pStreamShared->State.idxCurBdle = idxBdle;
1138	pStreamShared->State.offCurBdle = 0;
1139	}
1140
1141	/**
1142	* Common do-DMA prologue code.
1143	*
1144	* @retval true if DMA processing can take place
1145	* @retval false if caller should return immediately.
1146	* @param pDevIns The device instance.
1147	* @param pThis The shared HDA device state.
1148	* @param pStreamShared HDA stream to update (shared).
1149	* @param uSD The stream ID (for asserting).
1150	* @param tsNowNs The current RTTimeNano() value.
1151	* @param pszFunction The function name (for logging).
1152	*/
1153	DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint8_t uSD,
1154	uint64_t tsNowNs, const char *pszFunction)
1155	{
1156	RT_NOREF(uSD, pszFunction);
1157
1158	/*
1159	* Check if we should skip town...
1160	*/
1161	/* Stream not running (anymore)? */
1162	if (pStreamShared->State.fRunning)
1163	{ /* likely */ }
1164	else
1165	{
1166	Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1167	return false;
1168	}
1169
1170	if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1171	{ /* likely */ }
1172	else
1173	{
1174	Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1175	#ifdef HDA_STRICT
1176	/* Timing emulation bug or guest is misbehaving -- let me know. */
1177	AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1178	#endif
1179	return false;
1180	}
1181
1182	/*
1183	* Stream sanity checks.
1184	*/
1185	/* Register sanity checks. */
1186	Assert(uSD < HDA_MAX_STREAMS);
1187	Assert(pStreamShared->u64BDLBase);
1188	Assert(pStreamShared->u32CBL);
1189	Assert(pStreamShared->u8FIFOS);
1190
1191	/* State sanity checks. */
1192	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1193	Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1194
1195	/*
1196	* Some timestamp stuff for logging/debugging.
1197	*/
1198	/const uint64_t tsNowNs = RTTimeNanoTS();/
1199	Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1200	pStreamShared->State.tsLastTransferNs = tsNowNs;
1201	pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1202
1203	/*
1204	* Set the FIFORDY bit on the stream while doing the transfer.
1205	*/
1206	/** @todo r=bird: I don't get the HDA_SDSTS_FIFORDY logic. Unless we're
1207	* assuming SMP guest and that it can get stream registers while we're
1208	* here. Only it cannot do the later because we're sitting on the big
1209	* HDA device lock, see assertions in hdaR3Timer(). So, this is an
1210	* pointless guesture given that we clear it again after the loop. */
1211	HDA_STREAM_REG(pThis, STS, uSD) \|= HDA_SDSTS_FIFORDY;
1212
1213	return true;
1214	}
1215
1216	/**
1217	* Common do-DMA epilogue.
1218	*
1219	* @param pThis The shared HDA device state.
1220	* @param pThisCC The ring-3 HDA device state.
1221	* @param pStreamShared HDA stream to update (shared).
1222	* @param cbProcessed The number of bytes processed.
1223	*/
1224	DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, uint32_t cbProcessed)
1225	{
1226	/*
1227	* Clear the (pointless) FIFORDY bit again.
1228	*/
1229	HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
1230
1231	/*
1232	* Try updating the wall clock.
1233	*
1234	* Note 1) Only certain guests (like Linux' snd_hda_intel) rely on the WALCLK register
1235	* in order to determine the correct timing of the sound device. Other guests
1236	* like Windows 7 + 10 (or even more exotic ones like Haiku) will completely
1237	* ignore this.
1238	*
1239	* Note 2) When updating the WALCLK register too often / early (or even in a non-monotonic
1240	* fashion) this will upset guest device drivers and will completely fuck up the
1241	* sound output. Running VLC on the guest will tell!
1242	*/
1243	uint32_t const cFramesProcessed = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, cbProcessed);
1244	/** @todo this needs to go, but we need it for hdaR3WalClkGetMax below. */
1245	hdaR3StreamPeriodInc(&pStreamShared->State.Period,
1246	RT_MIN(cFramesProcessed, hdaR3StreamPeriodGetRemainingFrames(&pStreamShared->State.Period)));
1247
1248	uint64_t const cWallTicks = hdaR3StreamPeriodFramesToWalClk(&pStreamShared->State.Period, cFramesProcessed);
1249	uint64_t const uWallNew = hdaWalClkGetCurrent(pThis) + cWallTicks;
1250	uint64_t const uWallMax = hdaR3WalClkGetMax(pThis, pThisCC);
1251	bool const fWalClkSet = hdaR3WalClkSet(pThis, pThisCC, RT_MIN(uWallNew, uWallMax), false /* fForce */);
1252	RT_NOREF(fWalClkSet);
1253	}
1254
1255	/**
1256	* Completes a BDLE at the end of a DMA loop iteration, if possible.
1257	*
1258	* @param pDevIns The device instance.
1259	* @param pThis The shared HDA device state.
1260	* @param pThisCC The ring-3 HDA device state.
1261	* @param pStreamShared HDA stream to update (shared).
1262	* @param pStreamR3 HDA stream to update (ring-3).
1263	* @param pszFunction The function name (for logging).
1264	*/
1265	DECLINLINE(void) hdaR3StreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
1266	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, const char *pszFunction)
1267	{
1268	RT_NOREF(pszFunction);
1269
1270	/*
1271	* Is the buffer descriptor complete.
1272	*/
1273	if (hdaR3StreamDmaBufIsComplete(pStreamShared))
1274	{
1275	Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1276	pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1277	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1278	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1279
1280	/* Make sure to also update the wall clock when a BDLE is complete.
1281	* Needed for Windows 10 guests. */
1282	/** @todo there is a rounding error here. */
1283	hdaR3WalClkSet(pThis, pThisCC,
1284	hdaWalClkGetCurrent(pThis)
1285	+ hdaR3StreamPeriodFramesToWalClk(&pStreamShared->State.Period,
1286	hdaR3StreamDmaBufGetSize(pStreamShared)
1287	/ pStreamR3->State.Mapping.cbGuestFrame),
1288	false /* fForce */);
1289
1290	/*
1291	* Update the stream's current position.
1292	*
1293	* Do this as accurate and close to the actual data transfer as possible.
1294	* All guetsts rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1295	*
1296	* Note for Windows 10: The OS' driver is very picky about when the (DMA) positions get updated!
1297	* Not doing this at the right time will result in ugly sound crackles!
1298	*/
1299	hdaR3StreamSetPositionAdd(pStreamShared, pDevIns, pThis, hdaR3StreamDmaBufGetSize(pStreamShared));
1300
1301	/* Does the current BDLE require an interrupt to be sent? */
1302	if (hdaR3StreamDmaBufNeedsIrq(pStreamShared))
1303	{
1304	/* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1305	register is set we need to generate an interrupt. */
1306	if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1307	{
1308	/* Assert the interrupt before actually fetching the next BDLE below. */
1309	pStreamShared->State.cTransferPendingInterrupts = 1;
1310	Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1311
1312	/* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1313	* ending / beginning of a period. */
1314	/** @todo r=bird: What does the above comment mean? */
1315	HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) \|= HDA_SDSTS_BCIS;
1316	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1317	}
1318	}
1319
1320	/*
1321	* Advance to the next BDLE.
1322	*/
1323	hdaR3StreamDmaBufAdvanceToNext(pStreamShared);
1324	}
1325	else
1326	Log3(("%s: [SD%RU8] Not completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1327	pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1328	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1329	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1330	}
1331
1332	/**
1333	* Does DMA transfer for an HDA input stream.
1334	*
1335	* Reads audio data from the HDA stream's internal DMA buffer and writing to
1336	* guest memory.
1337	*
1338	* @param pDevIns The device instance.
1339	* @param pThis The shared HDA device state.
1340	* @param pThisCC The ring-3 HDA device state.
1341	* @param pStreamShared HDA stream to update (shared).
1342	* @param pStreamR3 HDA stream to update (ring-3).
1343	* @param cbToConsume The max amount of data to consume from the
1344	* internal DMA buffer. The caller will make sure
1345	* this is always the transfer size fo the current
1346	* period (unless something is seriously wrong).
1347	* @param fWriteSilence Whether to feed the guest silence rather than
1348	* fetching bytes from the internal DMA buffer.
1349	* This is set initially while we pre-buffer a
1350	* little bit of input, so we can better handle
1351	* time catch-ups and other schduling fun.
1352	* @param tsNowNs The current RTTimeNano() value.
1353	*
1354	* @remarks Caller owns the stream lock.
1355	*/
1356	static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared,
1357	PHDASTREAMR3 pStreamR3, uint32_t cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1358	{
1359	uint8_t const uSD = pStreamShared->u8SD;
1360	LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1361
1362	/*
1363	* Common prologue.
1364	*/
1365	if (hdaR3StreamDoDmaPrologue(pDevIns, pThis, pStreamShared, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1366	{ /* likely */ }
1367	else
1368	return;
1369
1370	/*
1371	*
1372	* The DMA copy loop.
1373	*
1374	*/
1375	uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1376	uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1377	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1378	uint32_t cbLeft = cbToConsume;
1379	Assert(cbLeft == pStreamShared->State.cbTransferSize);
1380	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1381
1382	while (cbLeft > 0)
1383	{
1384	STAM_PROFILE_START(&pThis->StatIn, a);
1385
1386	/*
1387	* Figure out how much we can read & write in this iteration.
1388	*/
1389	uint32_t cbChunk = 0;
1390	RTGCPHYS GCPhys = hdaR3StreamDmaBufGet(pStreamShared, &cbChunk);
1391
1392	/* Need to diverge if the frame format differs or if we're writing silence. */
1393	if ( !pStreamR3->State.Mapping.fMappingNeeded
1394	&& !fWriteSilence)
1395	{
1396	if (cbChunk <= cbLeft)
1397	{ /* very likely */ }
1398	else
1399	cbChunk = cbLeft;
1400
1401	/*
1402	* Write the host data directly into the guest buffers.
1403	*/
1404	while (cbChunk > 0)
1405	{
1406	/* Grab internal DMA buffer space and read into it. */
1407	void /const/ *pvBufSrc;
1408	size_t cbBufSrc;
1409	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1410	AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1411
1412	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1413	AssertRC(rc2);
1414
1415	#ifdef HDA_DEBUG_SILENCE
1416	fix me if relevant;
1417	#endif
1418	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1419	{ /* likely */ }
1420	else
1421	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1422
1423	#ifdef VBOX_WITH_DTRACE
1424	VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamR3->State.offRead);
1425	#endif
1426	pStreamR3->State.offRead += cbBufSrc;
1427	RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1428	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufSrc);
1429
1430	/* advance */
1431	cbChunk -= (uint32_t)cbBufSrc;
1432	GCPhys += cbBufSrc;
1433	cbLeft -= (uint32_t)cbBufSrc;
1434	pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1435	}
1436	}
1437	/*
1438	* Either we've got some initial silence to write, or we need to do
1439	* channel mapping. Both produces guest output into the bounce buffer,
1440	* which is then copied into guest memory. The bounce buffer may keep
1441	* partial frames there for the next BDLE, if an BDLE isn't frame aligned.
1442	*
1443	* Note! cbLeft is relative to the input (host) frame size.
1444	* cbChunk OTOH is relative to output (guest) size.
1445	*/
1446	else
1447	{
1448	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1449	uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps,
1450	PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1451	cbLeft));
1452	if (cbChunk <= cbLeftGuest)
1453	{ /* very likely */ }
1454	else
1455	cbChunk = cbLeftGuest;
1456
1457	/*
1458	* Work till we've covered the chunk.
1459	*/
1460	Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1461	while (cbChunk > 0)
1462	{
1463	/* Figure out how much we need to convert into the bounce buffer: */
1464	uint32_t cbGuest = PDMAudioPropsRoundUpBytesToFrame(&pStreamR3->State.Mapping.GuestProps, cbChunk - cbBounce);
1465	uint32_t cFrames = PDMAudioPropsBytesToFrames(&pStreamR3->State.Mapping.GuestProps,
1466	RT_MIN(cbGuest, sizeof(abBounce) - cbBounce));
1467	size_t cbBufSrc;
1468	if (!fWriteSilence)
1469	{
1470	/** @todo we could loop here to optimize buffer wrap around. Not important now though. */
1471	void /const/ *pvBufSrc;
1472	RTCircBufAcquireReadBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1473	&pvBufSrc, &cbBufSrc);
1474
1475	uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1476	(uint32_t)cbBufSrc);
1477	Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufSrc);
1478	Assert(cFramesToConvert > 0);
1479	Assert(cFramesToConvert <= cFrames);
1480
1481	pStreamR3->State.Mapping.pfnHostToGuest(&abBounce[cbBounce], pvBufSrc, cFramesToConvert,
1482	&pStreamR3->State.Mapping);
1483	Log5Func((" loop1: cbBounce=%#05x cFramesToConvert=%#05x cbBufSrc=%#x%s\n",
1484	cbBounce, cFramesToConvert, cbBufSrc, ASMMemIsZero(pvBufSrc, cbBufSrc) ? " all zero" : ""));
1485	#ifdef HDA_DEBUG_SILENCE
1486	fix me if relevant;
1487	#endif
1488	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1489	{ /* likely */ }
1490	else
1491	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1492
1493	#ifdef VBOX_WITH_DTRACE
1494	VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamR3->State.offRead);
1495	#endif
1496
1497	pStreamR3->State.offRead += cbBufSrc;
1498	RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1499
1500	cFrames = cFramesToConvert;
1501	cbGuest = cbBounce + PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps, cFrames);
1502	}
1503	else
1504	{
1505	cbBufSrc = PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames);
1506	cbGuest = PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps, cFrames);
1507	PDMAudioPropsClearBuffer(&pStreamR3->State.Mapping.GuestProps,
1508	&abBounce[cbBounce], cbGuest, cFrames);
1509	cbGuest += cbBounce;
1510	}
1511
1512	/* Write it to the guest buffer. */
1513	uint32_t cbGuestActual = RT_MIN(cbGuest, cbChunk);
1514	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, abBounce, cbGuestActual);
1515	AssertRC(rc2);
1516	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbGuestActual);
1517
1518	/* advance */
1519	cbLeft -= (uint32_t)cbBufSrc;
1520	cbChunk -= cbGuestActual;
1521	GCPhys += cbGuestActual;
1522	pStreamShared->State.offCurBdle += cbGuestActual;
1523
1524	cbBounce = cbGuest - cbGuestActual;
1525	if (cbBounce)
1526	memmove(abBounce, &abBounce[cbGuestActual], cbBounce);
1527
1528	Log5Func((" loop1: GCPhys=%RGp cbGuestActual=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbGuestActual, cbBounce, cFrames));
1529	}
1530	Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1531	}
1532
1533	STAM_PROFILE_STOP(&pThis->StatIn, a);
1534
1535	/*
1536	* Complete the buffer if necessary (common with the output DMA code).
1537	*/
1538	hdaR3StreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, "hdaR3StreamDoDmaInput");
1539	}
1540
1541	Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1542	AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1543
1544	/*
1545	* Common epilogue.
1546	*/
1547	hdaR3StreamDoDmaEpilogue(pThis, pThisCC, pStreamShared, cbToConsume);
1548
1549	/*
1550	* Log and leave.
1551	*/
1552	Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1553	uSD, cbToConsume, pStreamShared->State.cbTransferSize, pStreamR3->State.offRead - cbToConsume,
1554	pStreamShared->State.cTransferPendingInterrupts));
1555	}
1556
1557
1558	/**
1559	* Input streams: Pulls data from to the host device thru the mixer, putting it
1560	* in the internal DMA buffer.
1561	*
1562	* @param pStreamShared HDA stream to update (shared bits).
1563	* @param pStreamR3 HDA stream to update (ring-3 bits).
1564	* @param pSink The mixer sink to push to.
1565	*/
1566	static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1567	{
1568	RT_NOREF(pStreamShared);
1569	int rc = AudioMixerSinkUpdate(pSink);
1570	AssertRC(rc);
1571
1572	/* Is the sink ready to be read (host input data) from? If so, by how much? */
1573	uint32_t cbSinkReadable = AudioMixerSinkGetReadable(pSink);
1574
1575	/* How much (guest input) data is available for writing at the moment for the HDA stream? */
1576	const uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1577
1578	Log3Func(("[SD%RU8] cbSinkReadable=%RU32, cbStreamFree=%RU32\n", pStreamShared->u8SD, cbSinkReadable, cbStreamFree));
1579
1580	/* Do not read more than the HDA stream can hold at the moment.
1581	* The host sets the overall pace. */
1582	if (cbSinkReadable > cbStreamFree)
1583	cbSinkReadable = cbStreamFree;
1584
1585	/** @todo should we throttle (read less) this if we're far ahead? */
1586
1587	/*
1588	* Copy loop.
1589	*/
1590	while (cbSinkReadable)
1591	{
1592	/* Read a chunk of data. */
1593	uint8_t abBuf[4096];
1594	uint32_t cbRead = 0;
1595	rc = AudioMixerSinkRead(pSink, AUDMIXOP_COPY, abBuf, RT_MIN(cbSinkReadable, sizeof(abBuf)), &cbRead);
1596	AssertRCBreak(rc);
1597	AssertMsg(cbRead > 0, ("Nothing read from sink, even if %RU32 bytes were (still) announced\n", cbSinkReadable));
1598
1599	/* Write it to the internal DMA buffer. */
1600	uint32_t off = 0;
1601	while (off < cbRead)
1602	{
1603	void *pvDstBuf;
1604	size_t cbDstBuf;
1605	RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbRead - off, &pvDstBuf, &cbDstBuf);
1606
1607	memcpy(pvDstBuf, &abBuf[off], cbDstBuf);
1608
1609	#ifdef VBOX_WITH_DTRACE
1610	VBOXDD_HDA_STREAM_AIO_IN((uint32_t)pStreamR3->u8SD, (uint32_t)cbDstBuf, pStreamR3->State.offWrite);
1611	#endif
1612	pStreamR3->State.offWrite += cbDstBuf;
1613
1614	RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
1615
1616	off += (uint32_t)cbDstBuf;
1617	}
1618	Assert(off == cbRead);
1619
1620	/* Write to debug file? */
1621	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1622	{ /* likely */ }
1623	else
1624	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileStream, abBuf, cbRead, 0 /* fFlags */);
1625
1626	/* Advance. */
1627	Assert(cbRead <= cbSinkReadable);
1628	cbSinkReadable -= cbRead;
1629	}
1630	}
1631
1632	/**
1633	* Does DMA transfer for an HDA output stream.
1634	*
1635	* This transfers one DMA timer period worth of data from the guest and into the
1636	* internal DMA buffer.
1637	*
1638	* @param pDevIns The device instance.
1639	* @param pThis The shared HDA device state.
1640	* @param pThisCC The ring-3 HDA device state.
1641	* @param pStreamShared HDA stream to update (shared).
1642	* @param pStreamR3 HDA stream to update (ring-3).
1643	* @param cbToProduce The max amount of data to produce (i.e. put into
1644	* the circular buffer). Unless something is going
1645	* seriously wrong, this will always be transfer
1646	* size for the current period.
1647	* @param tsNowNs The current RTTimeNano() value.
1648	*
1649	* @remarks Caller owns the stream lock.
1650	*/
1651	static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared,
1652	PHDASTREAMR3 pStreamR3, uint32_t cbToProduce, uint64_t tsNowNs)
1653	{
1654	uint8_t const uSD = pStreamShared->u8SD;
1655	LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1656
1657	/*
1658	* Common prologue.
1659	*/
1660	if (hdaR3StreamDoDmaPrologue(pDevIns, pThis, pStreamShared, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1661	{ /* likely */ }
1662	else
1663	return;
1664
1665	/*
1666	*
1667	* The DMA copy loop.
1668	*
1669	*/
1670	uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1671	uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1672	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1673	uint32_t cbLeft = cbToProduce;
1674	Assert(cbLeft == pStreamShared->State.cbTransferSize);
1675	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1676
1677	while (cbLeft > 0)
1678	{
1679	STAM_PROFILE_START(&pThis->StatOut, a);
1680
1681	/*
1682	* Figure out how much we can read & write in this iteration.
1683	*/
1684	uint32_t cbChunk = 0;
1685	RTGCPHYS GCPhys = hdaR3StreamDmaBufGet(pStreamShared, &cbChunk);
1686
1687	/* Need to diverge if the frame format differs. */
1688	if ( !pStreamR3->State.Mapping.fMappingNeeded
1689	/** @todo && pStreamShared->State.fFrameAlignedBuffers */)
1690	{
1691	if (cbChunk <= cbLeft)
1692	{ /* very likely */ }
1693	else
1694	cbChunk = cbLeft;
1695
1696	/*
1697	* Read the guest data directly into the internal DMA buffer.
1698	*/
1699	while (cbChunk > 0)
1700	{
1701	/* Grab internal DMA buffer space and read into it. */
1702	void *pvBufDst;
1703	size_t cbBufDst;
1704	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1705	AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1706
1707	int rc2 = PDMDevHlpPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1708	AssertRC(rc2);
1709
1710	#ifdef HDA_DEBUG_SILENCE
1711	fix me if relevant;
1712	#endif
1713	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1714	{ /* likely */ }
1715	else
1716	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1717
1718	#ifdef VBOX_WITH_DTRACE
1719	VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamR3->State.offWrite);
1720	#endif
1721	pStreamR3->State.offWrite += cbBufDst;
1722	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1723	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1724
1725	/* advance */
1726	cbChunk -= (uint32_t)cbBufDst;
1727	GCPhys += cbBufDst;
1728	cbLeft -= (uint32_t)cbBufDst;
1729	pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1730	}
1731	}
1732	/*
1733	* Need to map the frame content, so we need to read the guest data
1734	* into a temporary buffer, though the output can be directly written
1735	* into the internal buffer as it is assumed to be frame aligned.
1736	*
1737	* Note! cbLeft is relative to the output frame size.
1738	* cbChunk OTOH is relative to input size.
1739	*/
1740	else
1741	{
1742	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1743	uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps,
1744	PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1745	cbLeft));
1746	if (cbChunk <= cbLeftGuest)
1747	{ /* very likely */ }
1748	else
1749	cbChunk = cbLeftGuest;
1750
1751	/*
1752	* Loop till we've covered the chunk.
1753	*/
1754	Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1755	while (cbChunk > 0)
1756	{
1757	/* Read into the bounce buffer. */
1758	uint32_t const cbToRead = RT_MIN(cbChunk, sizeof(abBounce) - cbBounce);
1759	int rc2 = PDMDevHlpPhysRead(pDevIns, GCPhys, &abBounce[cbBounce], cbToRead);
1760	AssertRC(rc2);
1761	cbBounce += cbToRead;
1762
1763	/* Convert the size to whole frames and a remainder. */
1764	uint32_t cFrames = PDMAudioPropsBytesToFrames(&pStreamR3->State.Mapping.GuestProps, cbBounce);
1765	uint32_t const cbRemainder = cbBounce - PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps, cFrames);
1766	Log5Func((" loop1: GCPhys=%RGp cbToRead=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbToRead, cbBounce, cFrames));
1767
1768	/*
1769	* Convert from the bounce buffer and into the internal DMA buffer.
1770	*/
1771	uint32_t offBounce = 0;
1772	while (cFrames > 0)
1773	{
1774	void *pvBufDst;
1775	size_t cbBufDst;
1776	RTCircBufAcquireWriteBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1777	&pvBufDst, &cbBufDst);
1778
1779	uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, (uint32_t)cbBufDst);
1780	Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufDst);
1781	Assert(cFramesToConvert > 0);
1782	Assert(cFramesToConvert <= cFrames);
1783
1784	pStreamR3->State.Mapping.pfnGuestToHost(pvBufDst, &abBounce[offBounce], cFramesToConvert,
1785	&pStreamR3->State.Mapping);
1786	Log5Func((" loop2: offBounce=%#05x cFramesToConvert=%#05x cbBufDst=%#x%s\n",
1787	offBounce, cFramesToConvert, cbBufDst, ASMMemIsZero(pvBufDst, cbBufDst) ? " all zero" : ""));
1788
1789	# ifdef HDA_DEBUG_SILENCE
1790	fix me if relevant;
1791	# endif
1792	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1793	{ /* likely */ }
1794	else
1795	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1796
1797	pStreamR3->State.offWrite += cbBufDst;
1798	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1799	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1800
1801	/* advance */
1802	cbLeft -= (uint32_t)cbBufDst;
1803	cFrames -= cFramesToConvert;
1804	offBounce += PDMAudioPropsFramesToBytes(&pStreamR3->State.Mapping.GuestProps, cFramesToConvert);
1805	}
1806
1807	/* advance */
1808	cbChunk -= cbToRead;
1809	GCPhys += cbToRead;
1810	pStreamShared->State.offCurBdle += cbToRead;
1811	if (cbRemainder)
1812	memmove(&abBounce[0], &abBounce[cbBounce - cbRemainder], cbRemainder);
1813	cbBounce = cbRemainder;
1814	}
1815	Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1816	}
1817
1818	STAM_PROFILE_STOP(&pThis->StatOut, a);
1819
1820	/*
1821	* Complete the buffer if necessary (common with the output DMA code).
1822	*/
1823	hdaR3StreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, "hdaR3StreamDoDmaOutput");
1824	}
1825
1826	Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1827	AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1828
1829	/*
1830	* Common epilogue.
1831	*/
1832	hdaR3StreamDoDmaEpilogue(pThis, pThisCC, pStreamShared, cbToProduce);
1833
1834	/*
1835	* Log and leave.
1836	*/
1837	Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1838	uSD, cbToProduce, pStreamShared->State.cbTransferSize, pStreamR3->State.offWrite - cbToProduce,
1839	pStreamShared->State.cTransferPendingInterrupts));
1840	}
1841
1842	/**
1843	* Output streams: Pushes data from to the mixer and host device.
1844	*
1845	* @param pStreamShared HDA stream to update (shared bits).
1846	* @param pStreamR3 HDA stream to update (ring-3 bits).
1847	* @param pSink The mixer sink to push to.
1848	* @param nsNow The current RTTimeNanoTS() value.
1849	*/
1850	static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
1851	{
1852	/*
1853	* Figure how much that we can push down.
1854	*/
1855	uint32_t const cbSinkWritable = AudioMixerSinkGetWritable(pSink);
1856	uint32_t const cbStreamReadable = hdaR3StreamGetUsed(pStreamR3);
1857	uint32_t cbToReadFromStream = RT_MIN(cbStreamReadable, cbSinkWritable);
1858	/* Make sure that we always align the number of bytes when reading to the stream's PCM properties. */
1859	cbToReadFromStream = PDMAudioPropsFloorBytesToFrame(&pStreamShared->State.Cfg.Props, cbToReadFromStream);
1860
1861	Assert(nsNow >= pStreamShared->State.tsLastReadNs);
1862	Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 cbSinkWritable=%RU32 cbStreamReadable=%RU32 -> cbToReadFromStream=%RU32\n",
1863	pStreamShared->u8SD, nsNow - pStreamShared->State.tsLastReadNs, cbSinkWritable, cbStreamReadable, cbToReadFromStream));
1864	RT_NOREF(pStreamShared, nsNow);
1865
1866	/*
1867	* Do the pushing.
1868	*/
1869	Assert(pStreamR3->State.pCircBuf);
1870	while (cbToReadFromStream > 0)
1871	{
1872	void /const/ *pvSrcBuf;
1873	size_t cbSrcBuf;
1874	RTCircBufAcquireReadBlock(pStreamR3->State.pCircBuf, cbToReadFromStream, &pvSrcBuf, &cbSrcBuf);
1875
1876	if (!pStreamR3->Dbg.Runtime.fEnabled)
1877	{ /* likely */ }
1878	else
1879	DrvAudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileStream, pvSrcBuf, cbSrcBuf, 0 /* fFlags */);
1880
1881	uint32_t cbWritten = 0;
1882	int rc = AudioMixerSinkWrite(pSink, AUDMIXOP_COPY, pvSrcBuf, (uint32_t)cbSrcBuf, &cbWritten);
1883	AssertRC(rc);
1884	Assert(cbWritten <= cbSrcBuf);
1885
1886	Log2Func(("[SD%RU8] %#RX32/%#zx bytes read @ %#RX64\n", pStreamR3->u8SD, cbWritten, cbSrcBuf, pStreamR3->State.offRead));
1887	#ifdef VBOX_WITH_DTRACE
1888	VBOXDD_HDA_STREAM_AIO_OUT(pStreamR3->u8SD, cbWritten, pStreamR3->State.offRead);
1889	#endif
1890	pStreamR3->State.offRead += cbWritten;
1891
1892	RTCircBufReleaseReadBlock(pStreamR3->State.pCircBuf, cbWritten);
1893
1894	/* advance */
1895	cbToReadFromStream -= cbWritten;
1896	}
1897
1898	int rc2 = AudioMixerSinkUpdate(pSink);
1899	AssertRC(rc2);
1900	}
1901
1902	/**
1903	* The stream's main function when called by the timer.
1904	*
1905	* @note This function also will be called without timer invocation when
1906	* starting (enabling) the stream to minimize startup latency.
1907	*
1908	* @returns Current timer time if the timer is enabled, otherwise zero.
1909	* @param pDevIns The device instance.
1910	* @param pThis The shared HDA device state.
1911	* @param pThisCC The ring-3 HDA device state.
1912	* @param pStreamShared HDA stream to update (shared bits).
1913	* @param pStreamR3 HDA stream to update (ring-3 bits).
1914	*/
1915	uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
1916	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1917	{
1918	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1919	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
1920
1921	/* Do the work: */
1922	hdaR3StreamUpdate(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, true /* fInTimer */);
1923
1924	/* Re-arm the timer if the sink is still active: */
1925	if ( pStreamShared->State.fRunning
1926	&& pStreamR3->pMixSink
1927	&& AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
1928	{
1929	/* Advance the schduling: */
1930	uint32_t idxSched = pStreamShared->State.idxSchedule;
1931	AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
1932	uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
1933	if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
1934	{
1935	idxSched += 1;
1936	if ( idxSched > pStreamShared->State.cSchedule
1937	\|\| idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /paranoia^2/)
1938	{
1939	idxSched = pStreamShared->State.cSchedulePrologue;
1940	AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
1941	}
1942	idxLoop = 0;
1943	}
1944	pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
1945
1946	/* Do the arcual timer arming. */
1947	uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
1948	uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
1949	Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
1950	pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
1951	int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
1952	AssertRC(rc);
1953
1954	/* Some legacy stuff: */
1955	pStreamShared->State.tsTransferNext = tsTransferNext;
1956	pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[idxSched].cbPeriod;
1957
1958	return tsNow;
1959	}
1960
1961	Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
1962	return 0;
1963	}
1964
1965	/**
1966	* Updates a HDA stream by doing its required data transfers.
1967	*
1968	* The host sink(s) set the overall pace.
1969	*
1970	* This routine is called by both, the synchronous and the asynchronous
1971	* (VBOX_WITH_AUDIO_HDA_ASYNC_IO), implementations.
1972	*
1973	* When running synchronously, the device DMA transfers and the mixer sink
1974	* processing is within the device timer.
1975	*
1976	* When running asynchronously, only the device DMA transfers are done in the
1977	* device timer, whereas the mixer sink processing then is done in the stream's
1978	* own async I/O thread. This thread also will call this function
1979	* (with fInTimer set to @c false).
1980	*
1981	* @param pDevIns The device instance.
1982	* @param pThis The shared HDA device state.
1983	* @param pThisCC The ring-3 HDA device state.
1984	* @param pStreamShared HDA stream to update (shared bits).
1985	* @param pStreamR3 HDA stream to update (ring-3 bits).
1986	* @param fInTimer Whether to this function was called from the timer
1987	* context or an asynchronous I/O stream thread (if supported).
1988	*/
1989	void hdaR3StreamUpdate(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
1990	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fInTimer)
1991	{
1992	int rc2;
1993
1994	/*
1995	* Make sure we're running and got an active mixer sink.
1996	*/
1997	if (RT_LIKELY(pStreamShared->State.fRunning))
1998	{ /* likely */ }
1999	else
2000	return;
2001
2002	PAUDMIXSINK pSink = NULL;
2003	if (pStreamR3->pMixSink)
2004	pSink = pStreamR3->pMixSink->pMixSink;
2005	if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2006	{ /* likely */ }
2007	else
2008	return;
2009
2010	/*
2011	* Get scheduling info common to both input and output streams.
2012	*/
2013	const uint64_t tsNowNs = RTTimeNanoTS();
2014	uint32_t idxSched = pStreamShared->State.idxSchedule;
2015	AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2016	uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2017
2018	/*
2019	* Output streams (SDO).
2020	*/
2021	if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2022	{
2023	bool fDoRead; /* Whether to push data down the driver stack or not. */
2024	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2025	if (fInTimer)
2026	# endif
2027	{
2028	/*
2029	* Check how much room we have in our DMA buffer. There should be at
2030	* least one period worth of space there or we're in an overflow situation.
2031	*/
2032	uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2033	if (cbStreamFree >= cbPeriod)
2034	{ /* likely */ }
2035	else
2036	{
2037	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2038	Log(("hdaR3StreamUpdate: Warning! Stream #%u has insufficient space free: %u bytes, need %u. Will try move data out of the buffer...\n",
2039	pStreamShared->u8SD, cbStreamFree, cbPeriod));
2040	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2041	int rc = RTCritSectTryEnter(&pStreamR3->State.AIO.CritSect);
2042	if (RT_SUCCESS(rc))
2043	{
2044	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, tsNowNs);
2045	RTCritSectLeave(&pStreamR3->State.AIO.CritSect);
2046	}
2047	else
2048	RTThreadYield();
2049	#else
2050	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, tsNowNs);
2051	#endif
2052	Log(("hdaR3StreamUpdate: Gained %u bytes.\n", hdaR3StreamGetFree(pStreamR3) - cbStreamFree));
2053
2054	cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2055	if (cbStreamFree < cbPeriod)
2056	{
2057	/* Unable to make sufficient space. Drop the whole buffer content.
2058	* This is needed in order to keep the device emulation running at a constant rate,
2059	* at the cost of losing valid (but too much) data. */
2060	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2061	LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data\n",
2062	pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3)));
2063	# ifdef HDA_STRICT
2064	AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
2065	# endif
2066	RTCircBufReset(pStreamR3->State.pCircBuf);
2067	pStreamR3->State.offWrite = 0;
2068	pStreamR3->State.offRead = 0;
2069	cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2070	}
2071	}
2072
2073	/*
2074	* Do the DMA transfer.
2075	*/
2076	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2077	rc2 = PDMDevHlpCritSectEnter(pDevIns, &pStreamShared->CritSect, VERR_IGNORED);
2078	AssertRC(rc2);
2079	# endif
2080
2081	uint64_t const offWriteBefore = pStreamR3->State.offWrite;
2082	hdaR3StreamDoDmaOutput(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2083
2084	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2085	rc2 = PDMDevHlpCritSectLeave(pDevIns, &pStreamShared->CritSect);
2086	AssertRC(rc2);
2087	# endif
2088
2089	/*
2090	* Should we push data to down thru the mixer to and to the host drivers?
2091	*
2092	* We initially delay this by pThis->msInitialDelay, but after than we'll
2093	* kick the AIO thread every time we've put more data in the buffer (which is
2094	* every time) as the host audio device needs to get data in a timely manner.
2095	*
2096	* (We used to try only wake up the AIO thread according to pThis->uIoTimer
2097	* and host wall clock, but that meant we would miss a wakup after the DMA
2098	* timer was called a little late or if TM entered into catch-up mode.)
2099	*/
2100	if (!pStreamShared->State.tsAioDelayEnd)
2101	fDoRead = pStreamR3->State.offWrite > offWriteBefore
2102	\|\| hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2103	else if (PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer) >= pStreamShared->State.tsAioDelayEnd)
2104	{
2105	Log3Func(("Initial delay done: Passed tsAioDelayEnd.\n"));
2106	pStreamShared->State.tsAioDelayEnd = 0;
2107	fDoRead = true;
2108	}
2109	else if (hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2)
2110	{
2111	Log3Func(("Initial delay done: Passed running short on buffer.\n"));
2112	pStreamShared->State.tsAioDelayEnd = 0;
2113	fDoRead = true;
2114	}
2115	else
2116	{
2117	Log3Func(("Initial delay pending...\n"));
2118	fDoRead = false;
2119	}
2120
2121	Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fDoRead=%RTbool\n",
2122	(tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2123	pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2124	pStreamShared->State.cbAvgTransfer * 2, fDoRead));
2125
2126	if (fDoRead)
2127	{
2128	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2129	/* Notify the async I/O worker thread that there's work to do. */
2130	Log5Func(("Notifying AIO thread\n"));
2131	rc2 = hdaR3StreamAsyncIONotify(pStreamR3);
2132	AssertRC(rc2);
2133	# endif
2134	/* Update last read timestamp for logging/debugging. */
2135	pStreamShared->State.tsLastReadNs = tsNowNs;
2136	}
2137	}
2138
2139	/*
2140	* Move data out of the pStreamR3->State.pCircBuf buffer and to
2141	* the mixer and in direction of the host audio devices.
2142	*/
2143	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2144	else
2145	# else
2146	if (fDoRead)
2147	# endif
2148	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, tsNowNs);
2149	}
2150	/*
2151	* Input stream (SDI).
2152	*/
2153	else
2154	{
2155	Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2156
2157	/*
2158	* If we're the async I/O worker, or not using AIO, pull bytes
2159	* from the mixer and into our internal DMA buffer.
2160	*/
2161	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2162	if (!fInTimer)
2163	# endif
2164	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2165	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2166	else /* fInTimer */
2167	# endif
2168	{
2169	/*
2170	* See how much data we've got buffered...
2171	*/
2172	bool fWriteSilence = false;
2173	uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2174	if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2175	{ /likely/ }
2176	/*
2177	* Because it may take a while for the input stream to get going (at
2178	* least with pulseaudio), we feed the guest silence till we've
2179	* pre-buffer a reasonable amount of audio.
2180	*/
2181	else if (!pStreamShared->State.fInputPreBuffered)
2182	{
2183	if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2184	{
2185	Log3(("hdaR3StreamUpdate: Pre-buffering (got %#x out of %#x bytes)...\n",
2186	cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2187	fWriteSilence = true;
2188	}
2189	else
2190	{
2191	Log3(("hdaR3StreamUpdate: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2192	cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2193	pStreamShared->State.fInputPreBuffered = true;
2194	fWriteSilence = true; /* For now, just do the most conservative thing. */
2195	}
2196	cbStreamUsed = cbPeriod;
2197	}
2198	/*
2199	* When we're low on data, we must really try fetch some ourselves
2200	* as buffer underruns must not happen.
2201	*/
2202	else
2203	{
2204	/** @todo We're ending up here to frequently with pulse audio at least (just
2205	* watch the stream stats in the statistcs viewer, and way to often we
2206	* have to inject silence bytes. I suspect part of the problem is
2207	* that the HDA device require a much better latency than what the
2208	* pulse audio is configured for by default (10 ms vs 150ms). */
2209	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2210	Log(("hdaR3StreamUpdate: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2211	pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2212	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2213	int rc = RTCritSectTryEnter(&pStreamR3->State.AIO.CritSect);
2214	if (RT_SUCCESS(rc))
2215	{
2216	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2217	RTCritSectLeave(&pStreamR3->State.AIO.CritSect);
2218	}
2219	else
2220	RTThreadYield();
2221	#else
2222	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2223	#endif
2224	Log(("hdaR3StreamUpdate: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2225	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2226	if (cbStreamUsed < cbPeriod)
2227	{
2228	/* Unable to find sufficient input data by simple prodding.
2229	In order to keep a constant byte stream following thru the DMA
2230	engine into the guest, we will try again and then fall back on
2231	filling the gap with silence. */
2232	uint32_t cbSilence = 0;
2233	do
2234	{
2235	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2236	RTCritSectEnter(&pStreamR3->State.AIO.CritSect);
2237	#endif
2238	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2239	if (cbStreamUsed < cbPeriod)
2240	{
2241	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2242	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2243	while (cbStreamUsed < cbPeriod)
2244	{
2245	void *pvDstBuf;
2246	size_t cbDstBuf;
2247	RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2248	&pvDstBuf, &cbDstBuf);
2249	RT_BZERO(pvDstBuf, cbDstBuf);
2250	RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2251	cbSilence += (uint32_t)cbDstBuf;
2252	cbStreamUsed += (uint32_t)cbDstBuf;
2253	}
2254	}
2255
2256	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2257	RTCritSectLeave(&pStreamR3->State.AIO.CritSect);
2258	#endif
2259	} while (cbStreamUsed < cbPeriod);
2260	if (cbSilence > 0)
2261	{
2262	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2263	STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2264	LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2265	cbSilence, PDMAudioPropsBytesToMicro(&pStreamR3->State.Mapping.GuestProps, cbSilence)));
2266	}
2267	}
2268	}
2269
2270	/*
2271	* Do the DMA'ing.
2272	*/
2273	if (cbStreamUsed)
2274	{
2275	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2276	rc2 = PDMDevHlpCritSectEnter(pDevIns, &pStreamShared->CritSect, VERR_IGNORED);
2277	AssertRC(rc2);
2278	# endif
2279
2280	hdaR3StreamDoDmaInput(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3,
2281	RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2282
2283	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2284	rc2 = PDMDevHlpCritSectLeave(pDevIns, &pStreamShared->CritSect);
2285	AssertRC(rc2);
2286	# endif
2287	}
2288
2289	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2290	/*
2291	* We should always kick the AIO thread.
2292	*/
2293	/** @todo This isn't entirely ideal. If we get into an underrun situation,
2294	* we ideally want the AIO thread to run right before the DMA timer
2295	* rather than right after it ran. */
2296	Log5Func(("Notifying AIO thread\n"));
2297	rc2 = hdaR3StreamAsyncIONotify(pStreamR3);
2298	AssertRC(rc2);
2299	pStreamShared->State.tsLastReadNs = tsNowNs;
2300	# endif
2301	}
2302	}
2303	}
2304
2305	#endif /* IN_RING3 */
2306
2307	/**
2308	* Locks an HDA stream for serialized access.
2309	*
2310	* @returns IPRT status code.
2311	* @param pStreamShared HDA stream to lock (shared bits).
2312	*/
2313	void hdaStreamLock(PHDASTREAM pStreamShared)
2314	{
2315	AssertPtrReturnVoid(pStreamShared);
2316	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2317	int rc2 = PDMCritSectEnter(&pStreamShared->CritSect, VINF_SUCCESS);
2318	AssertRC(rc2);
2319	#endif
2320	}
2321
2322	/**
2323	* Unlocks a formerly locked HDA stream.
2324	*
2325	* @returns IPRT status code.
2326	* @param pStreamShared HDA stream to unlock (shared bits).
2327	*/
2328	void hdaStreamUnlock(PHDASTREAM pStreamShared)
2329	{
2330	AssertPtrReturnVoid(pStreamShared);
2331	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2332	int rc2 = PDMCritSectLeave(&pStreamShared->CritSect);
2333	AssertRC(rc2);
2334	# endif
2335	}
2336
2337	#ifdef IN_RING3
2338
2339	#if 0 /* unused - no prototype even */
2340	/**
2341	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
2342	* updating its associated LPIB register and DMA position buffer (if enabled).
2343	*
2344	* @returns Set LPIB value.
2345	* @param pDevIns The device instance.
2346	* @param pStream HDA stream to update read / write position for.
2347	* @param u32LPIB New LPIB (position) value to set.
2348	*/
2349	uint32_t hdaR3StreamUpdateLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t u32LPIB)
2350	{
2351	AssertMsg(u32LPIB <= pStreamShared->u32CBL,
2352	("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStreamShared->u8SD, u32LPIB, pStreamShared->u32CBL));
2353
2354	u32LPIB = RT_MIN(u32LPIB, pStreamShared->u32CBL);
2355
2356	LogFlowFunc(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
2357	pStreamShared->u8SD, u32LPIB, pThis->fDMAPosition));
2358
2359	/* Update LPIB in any case. */
2360	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = u32LPIB;
2361
2362	/* Do we need to tell the current DMA position? */
2363	if (pThis->fDMAPosition)
2364	{
2365	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
2366	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
2367	(void *)&u32LPIB, sizeof(uint32_t));
2368	AssertRC(rc2);
2369	}
2370
2371	return u32LPIB;
2372	}
2373	#endif
2374
2375	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2376	/**
2377	* Registers access handlers for a stream's BDLE DMA accesses.
2378	*
2379	* @returns true if registration was successful, false if not.
2380	* @param pStream HDA stream to register BDLE access handlers for.
2381	*/
2382	bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream)
2383	{
2384	/* At least LVI and the BDL base must be set. */
2385	if ( !pStreamShared->u16LVI
2386	\|\| !pStreamShared->u64BDLBase)
2387	{
2388	return false;
2389	}
2390
2391	hdaR3StreamUnregisterDMAHandlers(pStream);
2392
2393	LogFunc(("Registering ...\n"));
2394
2395	int rc = VINF_SUCCESS;
2396
2397	/*
2398	* Create BDLE ranges.
2399	*/
2400
2401	struct BDLERANGE
2402	{
2403	RTGCPHYS uAddr;
2404	uint32_t uSize;
2405	} arrRanges[16]; /** @todo Use a define. */
2406
2407	size_t cRanges = 0;
2408
2409	for (uint16_t i = 0; i < pStreamShared->u16LVI + 1; i++)
2410	{
2411	HDABDLE BDLE;
2412	rc = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, i /* Index */);
2413	if (RT_FAILURE(rc))
2414	break;
2415
2416	bool fAddRange = true;
2417	BDLERANGE *pRange;
2418
2419	if (cRanges)
2420	{
2421	pRange = &arrRanges[cRanges - 1];
2422
2423	/* Is the current range a direct neighbor of the current BLDE? */
2424	if ((pRange->uAddr + pRange->uSize) == BDLE.Desc.u64BufAddr)
2425	{
2426	/* Expand the current range by the current BDLE's size. */
2427	pRange->uSize += BDLE.Desc.u32BufSize;
2428
2429	/* Adding a new range in this case is not needed anymore. */
2430	fAddRange = false;
2431
2432	LogFunc(("Expanding range %zu by %RU32 (%RU32 total now)\n", cRanges - 1, BDLE.Desc.u32BufSize, pRange->uSize));
2433	}
2434	}
2435
2436	/* Do we need to add a new range? */
2437	if ( fAddRange
2438	&& cRanges < RT_ELEMENTS(arrRanges))
2439	{
2440	pRange = &arrRanges[cRanges];
2441
2442	pRange->uAddr = BDLE.Desc.u64BufAddr;
2443	pRange->uSize = BDLE.Desc.u32BufSize;
2444
2445	LogFunc(("Adding range %zu - 0x%x (%RU32)\n", cRanges, pRange->uAddr, pRange->uSize));
2446
2447	cRanges++;
2448	}
2449	}
2450
2451	LogFunc(("%zu ranges total\n", cRanges));
2452
2453	/*
2454	* Register all ranges as DMA access handlers.
2455	*/
2456
2457	for (size_t i = 0; i < cRanges; i++)
2458	{
2459	BDLERANGE *pRange = &arrRanges[i];
2460
2461	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)RTMemAllocZ(sizeof(HDADMAACCESSHANDLER));
2462	if (!pHandler)
2463	{
2464	rc = VERR_NO_MEMORY;
2465	break;
2466	}
2467
2468	RTListAppend(&pStream->State.lstDMAHandlers, &pHandler->Node);
2469
2470	pHandler->pStream = pStream; /* Save a back reference to the owner. */
2471
2472	char szDesc[32];
2473	RTStrPrintf(szDesc, sizeof(szDesc), "HDA[SD%RU8 - RANGE%02zu]", pStream->u8SD, i);
2474
2475	int rc2 = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
2476	hdaDMAAccessHandler,
2477	NULL, NULL, NULL,
2478	NULL, NULL, NULL,
2479	szDesc, &pHandler->hAccessHandlerType);
2480	AssertRCBreak(rc2);
2481
2482	pHandler->BDLEAddr = pRange->uAddr;
2483	pHandler->BDLESize = pRange->uSize;
2484
2485	/* Get first and last pages of the BDLE range. */
2486	RTGCPHYS pgFirst = pRange->uAddr & ~PAGE_OFFSET_MASK;
2487	RTGCPHYS pgLast = RT_ALIGN(pgFirst + pRange->uSize, PAGE_SIZE);
2488
2489	/* Calculate the region size (in pages). */
2490	RTGCPHYS regionSize = RT_ALIGN(pgLast - pgFirst, PAGE_SIZE);
2491
2492	pHandler->GCPhysFirst = pgFirst;
2493	pHandler->GCPhysLast = pHandler->GCPhysFirst + (regionSize - 1);
2494
2495	LogFunc(("\tRegistering region '%s': 0x%x - 0x%x (region size: %zu)\n",
2496	szDesc, pHandler->GCPhysFirst, pHandler->GCPhysLast, regionSize));
2497	LogFunc(("\tBDLE @ 0x%x - 0x%x (%RU32)\n",
2498	pHandler->BDLEAddr, pHandler->BDLEAddr + pHandler->BDLESize, pHandler->BDLESize));
2499
2500	rc2 = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2501	pHandler->GCPhysFirst, pHandler->GCPhysLast,
2502	pHandler->hAccessHandlerType, pHandler, NIL_RTR0PTR, NIL_RTRCPTR,
2503	szDesc);
2504	AssertRCBreak(rc2);
2505
2506	pHandler->fRegistered = true;
2507	}
2508
2509	LogFunc(("Registration ended with rc=%Rrc\n", rc));
2510
2511	return RT_SUCCESS(rc);
2512	}
2513
2514	/**
2515	* Unregisters access handlers of a stream's BDLEs.
2516	*
2517	* @param pStream HDA stream to unregister BDLE access handlers for.
2518	*/
2519	void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream)
2520	{
2521	LogFunc(("\n"));
2522
2523	PHDADMAACCESSHANDLER pHandler, pHandlerNext;
2524	RTListForEachSafe(&pStream->State.lstDMAHandlers, pHandler, pHandlerNext, HDADMAACCESSHANDLER, Node)
2525	{
2526	if (!pHandler->fRegistered) /* Handler not registered? Skip. */
2527	continue;
2528
2529	LogFunc(("Unregistering 0x%x - 0x%x (%zu)\n",
2530	pHandler->GCPhysFirst, pHandler->GCPhysLast, pHandler->GCPhysLast - pHandler->GCPhysFirst));
2531
2532	int rc2 = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2533	pHandler->GCPhysFirst);
2534	AssertRC(rc2);
2535
2536	RTListNodeRemove(&pHandler->Node);
2537
2538	RTMemFree(pHandler);
2539	pHandler = NULL;
2540	}
2541
2542	Assert(RTListIsEmpty(&pStream->State.lstDMAHandlers));
2543	}
2544
2545	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2546	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2547
2548	/**
2549	* @callback_method_impl{FNRTTHREAD,
2550	* Asynchronous I/O thread for a HDA stream.
2551	*
2552	* This will do the heavy lifting work for us as soon as it's getting notified
2553	* by another thread.}
2554	*/
2555	static DECLCALLBACK(int) hdaR3StreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
2556	{
2557	PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2558	PHDASTREAMSTATEAIO const pAIO = &pStreamR3->State.AIO;
2559	PHDASTATE const pThis = pStreamR3->pHDAStateShared;
2560	PHDASTATER3 const pThisCC = pStreamR3->pHDAStateR3;
2561	PPDMDEVINS const pDevIns = pThisCC->pDevIns;
2562	PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2563	Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2564	Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2565
2566	/* Signal parent thread that we've started */
2567	ASMAtomicWriteBool(&pAIO->fStarted, true);
2568	RTThreadUserSignal(hThreadSelf);
2569
2570	LogFunc(("[SD%RU8] Started\n", pStreamShared->u8SD));
2571
2572	while (!ASMAtomicReadBool(&pAIO->fShutdown))
2573	{
2574	int rc2 = RTSemEventWait(pAIO->hEvent, RT_INDEFINITE_WAIT);
2575	if (RT_SUCCESS(rc2))
2576	{ /* likely */ }
2577	else
2578	break;
2579
2580	if (!ASMAtomicReadBool(&pAIO->fShutdown))
2581	{ /* likely */ }
2582	else
2583	break;
2584
2585	rc2 = RTCritSectEnter(&pAIO->CritSect);
2586	AssertRC(rc2);
2587	if (RT_SUCCESS(rc2))
2588	{
2589	if (pAIO->fEnabled)
2590	hdaR3StreamUpdate(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3, false /* fInTimer */);
2591
2592	int rc3 = RTCritSectLeave(&pAIO->CritSect);
2593	AssertRC(rc3);
2594	}
2595	}
2596
2597	LogFunc(("[SD%RU8] Ended\n", pStreamShared->u8SD));
2598	ASMAtomicWriteBool(&pAIO->fStarted, false);
2599
2600	return VINF_SUCCESS;
2601	}
2602
2603	/**
2604	* Creates the async I/O thread for a specific HDA audio stream.
2605	*
2606	* @returns IPRT status code.
2607	* @param pStreamR3 HDA audio stream to create the async I/O thread for.
2608	*/
2609	int hdaR3StreamAsyncIOCreate(PHDASTREAMR3 pStreamR3)
2610	{
2611	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2612
2613	int rc;
2614
2615	if (!ASMAtomicReadBool(&pAIO->fStarted))
2616	{
2617	pAIO->fShutdown = false;
2618	pAIO->fEnabled = true; /* Enabled by default. */
2619
2620	rc = RTSemEventCreate(&pAIO->hEvent);
2621	if (RT_SUCCESS(rc))
2622	{
2623	rc = RTCritSectInit(&pAIO->CritSect);
2624	if (RT_SUCCESS(rc))
2625	{
2626	rc = RTThreadCreateF(&pAIO->hThread, hdaR3StreamAsyncIOThread, pStreamR3, 0 /cbStack/,
2627	RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "hdaAIO%RU8", pStreamR3->u8SD);
2628	if (RT_SUCCESS(rc))
2629	rc = RTThreadUserWait(pAIO->hThread, 10 * 1000 /* 10s timeout */);
2630	}
2631	}
2632	}
2633	else
2634	rc = VINF_SUCCESS;
2635
2636	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
2637	return rc;
2638	}
2639
2640	/**
2641	* Destroys the async I/O thread of a specific HDA audio stream.
2642	*
2643	* @returns IPRT status code.
2644	* @param pStreamR3 HDA audio stream to destroy the async I/O thread for.
2645	*/
2646	static int hdaR3StreamAsyncIODestroy(PHDASTREAMR3 pStreamR3)
2647	{
2648	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2649
2650	if (!ASMAtomicReadBool(&pAIO->fStarted))
2651	return VINF_SUCCESS;
2652
2653	ASMAtomicWriteBool(&pAIO->fShutdown, true);
2654
2655	int rc = hdaR3StreamAsyncIONotify(pStreamR3);
2656	AssertRC(rc);
2657
2658	int rcThread;
2659	rc = RTThreadWait(pAIO->hThread, 30 * 1000 /* 30s timeout */, &rcThread);
2660	LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
2661
2662	if (RT_SUCCESS(rc))
2663	{
2664	pAIO->hThread = NIL_RTTHREAD;
2665
2666	rc = RTCritSectDelete(&pAIO->CritSect);
2667	AssertRC(rc);
2668
2669	rc = RTSemEventDestroy(pAIO->hEvent);
2670	AssertRC(rc);
2671	pAIO->hEvent = NIL_RTSEMEVENT;
2672
2673	pAIO->fStarted = false;
2674	pAIO->fShutdown = false;
2675	pAIO->fEnabled = false;
2676	}
2677
2678	LogFunc(("[SD%RU8] Returning %Rrc\n", pStreamR3->u8SD, rc));
2679	return rc;
2680	}
2681
2682	/**
2683	* Lets the stream's async I/O thread know that there is some data to process.
2684	*
2685	* @returns IPRT status code.
2686	* @param pStreamR3 HDA stream to notify async I/O thread for.
2687	*/
2688	int hdaR3StreamAsyncIONotify(PHDASTREAMR3 pStreamR3)
2689	{
2690	return RTSemEventSignal(pStreamR3->State.AIO.hEvent);
2691	}
2692
2693	/**
2694	* Locks the async I/O thread of a specific HDA audio stream.
2695	*
2696	* @param pStreamR3 HDA stream to lock async I/O thread for.
2697	*/
2698	void hdaR3StreamAsyncIOLock(PHDASTREAMR3 pStreamR3)
2699	{
2700	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2701
2702	if (!ASMAtomicReadBool(&pAIO->fStarted))
2703	return;
2704
2705	int rc2 = RTCritSectEnter(&pAIO->CritSect);
2706	AssertRC(rc2);
2707	}
2708
2709	/**
2710	* Unlocks the async I/O thread of a specific HDA audio stream.
2711	*
2712	* @param pStreamR3 HDA stream to unlock async I/O thread for.
2713	*/
2714	void hdaR3StreamAsyncIOUnlock(PHDASTREAMR3 pStreamR3)
2715	{
2716	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2717
2718	if (!ASMAtomicReadBool(&pAIO->fStarted))
2719	return;
2720
2721	int rc2 = RTCritSectLeave(&pAIO->CritSect);
2722	AssertRC(rc2);
2723	}
2724
2725	/**
2726	* Enables (resumes) or disables (pauses) the async I/O thread.
2727	*
2728	* @param pStreamR3 HDA stream to enable/disable async I/O thread for.
2729	* @param fEnable Whether to enable or disable the I/O thread.
2730	*
2731	* @remarks Does not do locking.
2732	*/
2733	void hdaR3StreamAsyncIOEnable(PHDASTREAMR3 pStreamR3, bool fEnable)
2734	{
2735	PHDASTREAMSTATEAIO pAIO = &pStreamR3->State.AIO;
2736	ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
2737	}
2738
2739	# endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
2740	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Audio/HDAStream.cpp@ 88163

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