VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/HDAStream.h@ 88165

Last change on this file since 88165 was 88165, checked in by vboxsync, 4 years ago

DevHDA: Remove the FIFO buffer. Try align the stream state on cache lines. [build fix] bugref:9890

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1/* $Id: HDAStream.h 88165 2021-03-17 17:19:33Z vboxsync $ */
2/** @file
3 * HDAStream.h - Streams for HD Audio.
4 */
5
6/*
7 * Copyright (C) 2017-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VBOX_INCLUDED_SRC_Audio_HDAStream_h
19#define VBOX_INCLUDED_SRC_Audio_HDAStream_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include "DevHDACommon.h"
25#include "HDAStreamMap.h"
26#include "HDAStreamPeriod.h"
27
28
29#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
30/**
31 * HDA stream's state for asynchronous I/O.
32 */
33typedef struct HDASTREAMSTATEAIO
34{
35 /** Thread handle for the actual I/O thread. */
36 RTTHREAD hThread;
37 /** Event for letting the thread know there is some data to process. */
38 RTSEMEVENT hEvent;
39 /** Critical section for synchronizing access. */
40 RTCRITSECT CritSect;
41 /** Started indicator. */
42 volatile bool fStarted;
43 /** Shutdown indicator. */
44 volatile bool fShutdown;
45 /** Whether the thread should do any data processing or not. */
46 volatile bool fEnabled;
47 bool afPadding[1+4];
48} HDASTREAMSTATEAIO;
49/** Pointer to a HDA stream's asynchronous I/O state. */
50typedef HDASTREAMSTATEAIO *PHDASTREAMSTATEAIO;
51#endif
52
53/**
54 * Structure containing HDA stream debug stuff, configurable at runtime.
55 */
56typedef struct HDASTREAMDEBUGRT
57{
58 /** Whether debugging is enabled or not. */
59 bool fEnabled;
60 uint8_t Padding[7];
61 /** File for dumping stream reads / writes.
62 * For input streams, this dumps data being written to the device FIFO,
63 * whereas for output streams this dumps data being read from the device FIFO. */
64 R3PTRTYPE(PPDMAUDIOFILE) pFileStream;
65 /** File for dumping raw DMA reads / writes.
66 * For input streams, this dumps data being written to the device DMA,
67 * whereas for output streams this dumps data being read from the device DMA. */
68 R3PTRTYPE(PPDMAUDIOFILE) pFileDMARaw;
69 /** File for dumping mapped (that is, extracted) DMA reads / writes. */
70 R3PTRTYPE(PPDMAUDIOFILE) pFileDMAMapped;
71} HDASTREAMDEBUGRT;
72
73/**
74 * Structure containing HDA stream debug information.
75 */
76typedef struct HDASTREAMDEBUG
77{
78 /** Runtime debug info. */
79 HDASTREAMDEBUGRT Runtime;
80#ifdef DEBUG
81 /** Critical section to serialize access if needed. */
82 RTCRITSECT CritSect;
83 uint32_t Padding0[2];
84 /** Number of total read accesses. */
85 uint64_t cReadsTotal;
86 /** Number of total DMA bytes read. */
87 uint64_t cbReadTotal;
88 /** Timestamp (in ns) of last read access. */
89 uint64_t tsLastReadNs;
90 /** Number of total write accesses. */
91 uint64_t cWritesTotal;
92 /** Number of total DMA bytes written. */
93 uint64_t cbWrittenTotal;
94 /** Number of total write accesses since last iteration (Hz). */
95 uint64_t cWritesHz;
96 /** Number of total DMA bytes written since last iteration (Hz). */
97 uint64_t cbWrittenHz;
98 /** Timestamp (in ns) of beginning a new write slot. */
99 uint64_t tsWriteSlotBegin;
100 /** Number of current silence samples in a (consecutive) row. */
101 uint64_t csSilence;
102 /** Number of silent samples in a row to consider an audio block as audio gap (silence). */
103 uint64_t cSilenceThreshold;
104 /** How many bytes to skip in an audio stream before detecting silence.
105 * (useful for intros and silence at the beginning of a song). */
106 uint64_t cbSilenceReadMin;
107#else
108 uint64_t au64Alignment[2];
109#endif
110} HDASTREAMDEBUG;
111typedef HDASTREAMDEBUG *PHDASTREAMDEBUG;
112
113/**
114 * Internal state of a HDA stream.
115 */
116typedef struct HDASTREAMSTATE
117{
118 /** Flag indicating whether this stream currently is
119 * in reset mode and therefore not acccessible by the guest. */
120 volatile bool fInReset;
121 /** Flag indicating if the stream is in running state or not. */
122 volatile bool fRunning;
123 /** The stream's I/O timer Hz rate. */
124 uint16_t uTimerIoHz;
125 /** How many interrupts are pending due to
126 * BDLE interrupt-on-completion (IOC) bits set. */
127 uint8_t cTransferPendingInterrupts;
128 /** Unused, padding. */
129 uint8_t abPadding1[2];
130 /** Input streams only: Set when we switch from feeding the guest silence and
131 * commits to proving actual audio input bytes. */
132 bool fInputPreBuffered;
133 /** Input streams only: The number of bytes we need to prebuffer. */
134 uint32_t cbInputPreBuffer;
135 uint32_t u32Padding2;
136 /** Timestamp (absolute, in timer ticks) of the last DMA data transfer. */
137 uint64_t tsTransferLast;
138 /** Timestamp (absolute, in timer ticks) of the next DMA data transfer.
139 * Next for determining the next scheduling window.
140 * Can be 0 if no next transfer is scheduled. */
141 uint64_t tsTransferNext;
142 /** Total transfer size (in bytes) of a transfer period.
143 * @note This is in host side frames, in case we're doing any mapping. */
144 uint32_t cbTransferSize;
145 /** The size of an average transfer. */
146 uint32_t cbAvgTransfer;
147 /** The stream's period. Need for timing. */
148 HDASTREAMPERIOD Period;
149 /** The stream's current host side configuration.
150 * This should match the SDnFMT in all respects but maybe the channel count as
151 * we may need to expand mono or into/from into stereo. The unmodified SDnFMT
152 * properties can be found in HDASTREAMR3::Mapping::PCMProps. */
153 PDMAUDIOSTREAMCFG Cfg;
154 /** Timestamp (real time, in ns) of last DMA transfer. */
155 uint64_t tsLastTransferNs;
156 /** Timestamp (real time, in ns) of last stream read (to backends).
157 * When running in async I/O mode, this differs from \a tsLastTransferNs,
158 * because reading / processing will be done in a separate stream. */
159 uint64_t tsLastReadNs;
160
161 /** This is set to the timer clock time when the msInitialDelay period is over.
162 * Once reached, this is set to zero to avoid unnecessary time queries. */
163 uint64_t tsAioDelayEnd;
164 /** The start time for the playback (on the timer clock). */
165 uint64_t tsStart;
166
167 uint64_t au64Padding[3];
168
169 /** @name DMA engine
170 * @{ */
171 /** The offset into the current BDLE. */
172 uint32_t offCurBdle;
173 /** LVI + 1 */
174 uint16_t cBdles;
175 /** The index of the current BDLE.
176 * This is the entry which period is currently "running" on the DMA timer. */
177 uint8_t idxCurBdle;
178 /** The number of prologue scheduling steps.
179 * This is used when the tail BDLEs doesn't have IOC set. */
180 uint8_t cSchedulePrologue;
181 /** Number of scheduling steps. */
182 uint16_t cSchedule;
183 /** Current scheduling step. */
184 uint16_t idxSchedule;
185 /** Current loop number within the current scheduling step. */
186 uint32_t idxScheduleLoop;
187
188 /** Buffer descriptors and additional timer scheduling state.
189 * (Same as HDABDLEDESC, with more sensible naming.) */
190 struct
191 {
192 /** The buffer address. */
193 uint64_t GCPhys;
194 /** The buffer size (guest bytes). */
195 uint32_t cb;
196 /** The flags (only bit 0 is defined). */
197 uint32_t fFlags;
198 } aBdl[256];
199 /** Scheduling steps. */
200 struct
201 {
202 /** Number of timer ticks per period.
203 * ASSUMES that we don't need a full second and that the timer resolution
204 * isn't much higher than nanoseconds. */
205 uint32_t cPeriodTicks;
206 /** The period length in host bytes. */
207 uint32_t cbPeriod;
208 /** Number of times to repeat the period. */
209 uint32_t cLoops;
210 /** The BDL index of the first entry. */
211 uint8_t idxFirst;
212 /** The number of BDL entries. */
213 uint8_t cEntries;
214 uint8_t abPadding[2];
215 } aSchedule[512+8];
216 /** @} */
217} HDASTREAMSTATE;
218AssertCompileSizeAlignment(HDASTREAMSTATE, 8);
219AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 16);
220AssertCompileMemberAlignment(HDASTREAMSTATE, aSchedule, 16);
221
222/**
223 * An HDA stream (SDI / SDO) - shared.
224 *
225 * @note This HDA stream has nothing to do with a regular audio stream handled
226 * by the audio connector or the audio mixer. This HDA stream is a serial
227 * data in/out stream (SDI/SDO) defined in hardware and can contain
228 * multiple audio streams in one single SDI/SDO (interleaving streams).
229 *
230 * How a specific SDI/SDO is mapped to our internal audio streams relies on the
231 * stream channel mappings.
232 *
233 * Contains only register values which do *not* change until a stream reset
234 * occurs.
235 */
236typedef struct HDASTREAM
237{
238 /** Internal state of this stream. */
239 HDASTREAMSTATE State;
240
241 /** Stream descriptor number (SDn). */
242 uint8_t u8SD;
243 /** Current channel index.
244 * For a stereo stream, this is u8Channel + 1. */
245 uint8_t u8Channel;
246 /** FIFO Watermark (checked + translated in bytes, FIFOW).
247 * This will be update from hdaRegWriteSDFIFOW() and also copied
248 * hdaR3StreamInit() for some reason. */
249 uint8_t u8FIFOW;
250
251 /** @name Register values at stream setup.
252 * These will all be copied in hdaR3StreamInit().
253 * @{ */
254 /** FIFO Size (checked + translated in bytes, FIFOS).
255 * This is supposedly the max number of bytes we'll be DMA'ing in one chunk
256 * and correspondingly the LPIB & wall clock update jumps. However, we're
257 * not at all being honest with the guest about this. */
258 uint8_t u8FIFOS;
259 /** Cyclic Buffer Length (SDnCBL) - Represents the size of the ring buffer. */
260 uint32_t u32CBL;
261 /** Last Valid Index (SDnLVI). */
262 uint16_t u16LVI;
263 /** Format (SDnFMT). */
264 uint16_t u16FMT;
265 uint8_t abPadding[4];
266 /** DMA base address (SDnBDPU - SDnBDPL). */
267 uint64_t u64BDLBase;
268 /** @} */
269
270 /** The timer for pumping data thru the attached LUN drivers. */
271 TMTIMERHANDLE hTimer;
272
273#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
274 /** Pad the structure size to a 64 byte alignment. */
275 uint64_t au64Padding1[2];
276 /** Critical section for serialize access to the stream state between the async
277 * I/O thread and (basically) the guest. */
278 PDMCRITSECT CritSect;
279#endif
280} HDASTREAM;
281AssertCompileMemberAlignment(HDASTREAM, State.aBdl, 16);
282AssertCompileMemberAlignment(HDASTREAM, State.aSchedule, 16);
283AssertCompileSizeAlignment(HDASTREAM, 64);
284/** Pointer to an HDA stream (SDI / SDO). */
285typedef HDASTREAM *PHDASTREAM;
286
287
288/**
289 * An HDA stream (SDI / SDO) - ring-3 bits.
290 */
291typedef struct HDASTREAMR3
292{
293 /** Stream descriptor number (SDn). */
294 uint8_t u8SD;
295 uint8_t abPadding[7];
296 /** The shared state for the parent HDA device. */
297 R3PTRTYPE(PHDASTATE) pHDAStateShared;
298 /** The ring-3 state for the parent HDA device. */
299 R3PTRTYPE(PHDASTATER3) pHDAStateR3;
300 /** Pointer to HDA sink this stream is attached to. */
301 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
302 /** Internal state of this stream. */
303 struct
304 {
305 /** This stream's data mapping. */
306 HDASTREAMMAP Mapping;
307 /** Circular buffer (FIFO) for holding DMA'ed data. */
308 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
309 /** Current circular buffer read offset (for tracing & logging). */
310 uint64_t offRead;
311 /** Current circular buffer write offset (for tracing & logging). */
312 uint64_t offWrite;
313#ifdef HDA_USE_DMA_ACCESS_HANDLER
314 /** List of DMA handlers. */
315 RTLISTANCHORR3 lstDMAHandlers;
316#endif
317#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
318 /** Asynchronous I/O state members. */
319 HDASTREAMSTATEAIO AIO;
320#endif
321 /** Counter for all under/overflows problems. */
322 STAMCOUNTER StatDmaFlowProblems;
323 /** Counter for unresovled under/overflows problems. */
324 STAMCOUNTER StatDmaFlowErrors;
325 /** Number of bytes involved in unresolved flow errors. */
326 STAMCOUNTER StatDmaFlowErrorBytes;
327 } State;
328 /** Debug bits. */
329 HDASTREAMDEBUG Dbg;
330 uint64_t au64Alignment[2];
331} HDASTREAMR3;
332AssertCompileSizeAlignment(HDASTREAMR3, 64);
333/** Pointer to an HDA stream (SDI / SDO). */
334typedef HDASTREAMR3 *PHDASTREAMR3;
335
336/** @name Stream functions (shared).
337 * @{
338 */
339void hdaStreamLock(PHDASTREAM pStreamShared);
340void hdaStreamUnlock(PHDASTREAM pStreamShared);
341/** @} */
342
343#ifdef IN_RING3
344
345/** @name Stream functions (ring-3).
346 * @{
347 */
348int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis,
349 PHDASTATER3 pThisCC, uint8_t uSD);
350void hdaR3StreamDestroy(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
351int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
352 PHDASTREAMR3 pStreamR3, uint8_t uSD);
353void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC,
354 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD);
355int hdaR3StreamEnable(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable);
356void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow);
357void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared);
358
359void hdaR3StreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uToAdd);
360uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
361 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
362void hdaR3StreamUpdate(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
363 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fInTimer);
364PHDASTREAM hdaR3StreamR3ToShared(PHDASTREAMR3 pStreamCC);
365# ifdef HDA_USE_DMA_ACCESS_HANDLER
366bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream);
367void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream);
368# endif
369/** @} */
370
371/** @name Async I/O stream functions (ring-3).
372 * @{
373 */
374# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
375int hdaR3StreamAsyncIOCreate(PHDASTREAMR3 pStreamR3);
376void hdaR3StreamAsyncIOLock(PHDASTREAMR3 pStreamR3);
377void hdaR3StreamAsyncIOUnlock(PHDASTREAMR3 pStreamR3);
378void hdaR3StreamAsyncIOEnable(PHDASTREAMR3 pStreamR3, bool fEnable);
379int hdaR3StreamAsyncIONotify(PHDASTREAMR3 pStreamR3);
380# endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
381/** @} */
382
383#endif /* IN_RING3 */
384#endif /* !VBOX_INCLUDED_SRC_Audio_HDAStream_h */
385
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