VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 107712

Last change on this file since 107712 was 107490, checked in by vboxsync, 5 weeks ago

Devices/Bus/DevIommuAmd: bugref:3409 Added an assert since we index into an array and explicitly cast expression to better convey intent.
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1/* $Id: DevIommuAmd.cpp 107490 2025-01-08 10:09:34Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_IOMMU
33#include <VBox/msi.h>
34#include <VBox/iommu-amd.h>
35#include <VBox/vmm/pdmdev.h>
36
37#include <iprt/x86.h>
38#include <iprt/string.h>
39#include <iprt/avl.h>
40#ifdef IN_RING3
41# include <iprt/mem.h>
42#endif
43
44#include "VBoxDD.h"
45#include "DevIommuAmd.h"
46
47
48/*********************************************************************************************************************************
49* Defined Constants And Macros *
50*********************************************************************************************************************************/
51/** Release log prefix string. */
52#define IOMMU_LOG_PFX "AMD-IOMMU"
53/** The current saved state version. */
54#define IOMMU_SAVED_STATE_VERSION 1
55/** The IOMMU device instance magic. */
56#define IOMMU_MAGIC 0x10acce55
57
58/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
59#ifdef IN_RING3
60# define IOMMU_WITH_IOTLBE_CACHE
61#endif
62/** Enable the interrupt cache. */
63#define IOMMU_WITH_IRTE_CACHE
64
65/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
66#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
67# define IOMMU_WITH_DTE_CACHE
68/** The maximum number of device IDs in the cache. */
69# define IOMMU_DEV_CACHE_COUNT 16
70/** An empty device ID. */
71# define IOMMU_DTE_CACHE_KEY_NIL 0
72#endif
73
74#ifdef IOMMU_WITH_IRTE_CACHE
75/** The maximum number of IRTE cache entries. */
76# define IOMMU_IRTE_CACHE_COUNT 32
77/** A NIL IRTE cache entry key. */
78# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
79/** Gets the device ID from an IRTE cache entry key. */
80#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
81/** Gets the IOVA from the IOTLB entry key. */
82# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
83/** Makes an IRTE cache entry key.
84 *
85 * Bits 31:16 is the device ID (Bus, Device, Function).
86 * Bits 15:0 is the the offset into the IRTE table.
87 */
88# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
89#endif /* IOMMU_WITH_IRTE_CACHE */
90
91#ifdef IOMMU_WITH_IOTLBE_CACHE
92/** The maximum number of IOTLB entries. */
93# define IOMMU_IOTLBE_MAX 64
94/** The mask of bits covering the domain ID in the IOTLBE key. */
95# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
96/** The mask of bits covering the IOVA in the IOTLBE key. */
97# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
98/** The number of bits to shift for the domain ID of the IOTLBE key. */
99# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
100/** A NIL IOTLB key. */
101# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
102/** Gets the domain ID from an IOTLB entry key. */
103# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
104/** Gets the IOVA from the IOTLB entry key. */
105# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
106/** Makes an IOTLB entry key.
107 *
108 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
109 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
110 * so bottom 12 bits are free.
111 *
112 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
113 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
114 */
115# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
116 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
117#endif /* IOMMU_WITH_IOTLBE_CACHE */
118
119#ifdef IOMMU_WITH_DTE_CACHE
120/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
121 *
122 * Some of these flags are "basic" i.e. they correspond directly to their bits in
123 * the DTE. The rest of the flags are based on checks or operations on several DTE
124 * bits.
125 *
126 * The basic flags are:
127 * - VALID (DTE.V)
128 * - IO_PERM_READ (DTE.IR)
129 * - IO_PERM_WRITE (DTE.IW)
130 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
131 * masking consistent)
132 * - SUPPRESS_ALL_IOPF (DTE.SA)
133 * - SUPPRESS_IOPF (DTE.SE)
134 * - INTR_MAP_VALID (DTE.IV)
135 * - IGNORE_UNMAPPED_INTR (DTE.IG)
136 *
137 * @see iommuAmdGetBasicDevFlags()
138 * @{ */
139/** The DTE is present. */
140# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
141/** The DTE is valid. */
142# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
143/** The DTE permissions apply for address translations. */
144# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
145/** DTE permission - I/O read allowed. */
146# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
147/** DTE permission - I/O write allowed. */
148# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
149/** DTE permission - reserved. */
150# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
151/** Address translation required. */
152# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
153/** Suppress all I/O page faults. */
154# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
155/** Suppress I/O page faults. */
156# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
157/** Interrupt map valid. */
158# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
159/** Ignore unmapped interrupts. */
160# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
161/** An I/O page fault has been raised for this device. */
162# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
163/** Fixed and arbitrary interrupt control: Target Abort. */
164# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
165/** Fixed and arbitrary interrupt control: Forward unmapped. */
166# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
167/** Fixed and arbitrary interrupt control: Remapped. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
169/** Fixed and arbitrary interrupt control: Reserved. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
171/** @} */
172
173/** The number of bits to shift I/O device flags for DTE permissions. */
174# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
175/** The mask of DTE permissions in I/O device flags. */
176# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
177/** The number of bits to shift I/O device flags for interrupt control bits. */
178# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
179/** The mask of interrupt control bits in I/O device flags. */
180# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
181/** The number of bits to shift for ignore-unmapped interrupts bit. */
182# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
183
184/** Acquires the cache lock. */
185# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) \
186 do { \
187 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VINF_SUCCESS); \
188 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSectCache, rcLock); \
189 } while (0)
190
191/** Releases the cache lock. */
192# define IOMMU_CACHE_UNLOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
193#endif /* IOMMU_WITH_DTE_CACHE */
194
195/** Acquires the IOMMU lock (returns a_rcBusy on contention). */
196#define IOMMU_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
197 do { \
198 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)); \
199 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
200 { /* likely */ } \
201 else \
202 return rcLock; \
203 } while (0)
204
205/** Acquires the IOMMU lock (can fail under extraordinary circumstance in ring-0). */
206#define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
207 do { \
208 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
209 PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), NULL, rcLock); \
210 } while (0)
211
212/** Checks if the current thread owns the PDM lock. */
213# define IOMMU_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
214 do \
215 { \
216 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner((a_pDevIns))); \
217 NOREF(a_pThisCC); \
218 } while (0)
219
220/** Releases the PDM lock. */
221# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
222
223/** Gets the maximum valid IOVA for the given I/O page-table level. */
224#define IOMMU_GET_MAX_VALID_IOVA(a_Level) ((X86_PAGE_4K_SIZE << ((a_Level) * 9)) - 1)
225
226
227/*********************************************************************************************************************************
228* Structures and Typedefs *
229*********************************************************************************************************************************/
230/**
231 * IOMMU operation (transaction).
232 */
233typedef enum IOMMUOP
234{
235 /** Address translation request. */
236 IOMMUOP_TRANSLATE_REQ = 0,
237 /** Memory read request. */
238 IOMMUOP_MEM_READ,
239 /** Memory write request. */
240 IOMMUOP_MEM_WRITE,
241 /** Interrupt request. */
242 IOMMUOP_INTR_REQ,
243 /** Command. */
244 IOMMUOP_CMD
245} IOMMUOP;
246/** Pointer to a IOMMU operation. */
247typedef IOMMUOP *PIOMMUOP;
248
249/**
250 * I/O page lookup.
251 */
252typedef struct IOPAGELOOKUP
253{
254 /** The translated system physical address. */
255 RTGCPHYS GCPhysSpa;
256 /** The number of offset bits in the system physical address. */
257 uint8_t cShift;
258 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
259 uint8_t fPerm;
260} IOPAGELOOKUP;
261/** Pointer to an I/O page lookup. */
262typedef IOPAGELOOKUP *PIOPAGELOOKUP;
263/** Pointer to a const I/O page lookup. */
264typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
265
266/**
267 * I/O address range.
268 */
269typedef struct IOADDRRANGE
270{
271 /** The address (virtual or physical). */
272 uint64_t uAddr;
273 /** The size of the access in bytes. */
274 size_t cb;
275 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
276 uint8_t fPerm;
277} IOADDRRANGE;
278/** Pointer to an I/O address range. */
279typedef IOADDRRANGE *PIOADDRRANGE;
280/** Pointer to a const I/O address range. */
281typedef IOADDRRANGE const *PCIOADDRRANGE;
282
283#ifdef IOMMU_WITH_DTE_CACHE
284/**
285 * Device Table Entry Cache.
286 */
287typedef struct DTECACHE
288{
289 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
290 uint16_t fFlags;
291 /** The domain ID assigned for this device by software. */
292 uint16_t idDomain;
293} DTECACHE;
294/** Pointer to an I/O device struct. */
295typedef DTECACHE *PDTECACHE;
296/** Pointer to a const I/O device struct. */
297typedef DTECACHE *PCDTECACHE;
298AssertCompileSize(DTECACHE, 4);
299#endif /* IOMMU_WITH_DTE_CACHE */
300
301#ifdef IOMMU_WITH_IOTLBE_CACHE
302/**
303 * I/O TLB Entry.
304 * Keep this as small and aligned as possible.
305 */
306typedef struct IOTLBE
307{
308 /** The AVL tree node. */
309 AVLU64NODECORE Core;
310 /** The least recently used (LRU) list node. */
311 RTLISTNODE NdLru;
312 /** The I/O page lookup results of the translation. */
313 IOPAGELOOKUP PageLookup;
314 /** Whether the entry needs to be evicted from the cache. */
315 bool fEvictPending;
316} IOTLBE;
317/** Pointer to an IOMMU I/O TLB entry struct. */
318typedef IOTLBE *PIOTLBE;
319/** Pointer to a const IOMMU I/O TLB entry struct. */
320typedef IOTLBE const *PCIOTLBE;
321AssertCompileSizeAlignment(IOTLBE, 8);
322AssertCompileMemberOffset(IOTLBE, Core, 0);
323#endif /* IOMMU_WITH_IOTLBE_CACHE */
324
325#ifdef IOMMU_WITH_IRTE_CACHE
326/**
327 * Interrupt Remap Table Entry Cache.
328 */
329typedef struct IRTECACHE
330{
331 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
332 uint32_t uKey;
333 /** The IRTE. */
334 IRTE_T Irte;
335} IRTECACHE;
336/** Pointer to an IRTE cache struct. */
337typedef IRTECACHE *PIRTECACHE;
338/** Pointer to a const IRTE cache struct. */
339typedef IRTECACHE const *PCIRTECACHE;
340AssertCompileSizeAlignment(IRTECACHE, 4);
341#endif /* IOMMU_WITH_IRTE_CACHE */
342
343/**
344 * The shared IOMMU device state.
345 */
346typedef struct IOMMU
347{
348 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
349 uint32_t idxIommu;
350 /** IOMMU magic. */
351 uint32_t u32Magic;
352
353 /** The MMIO handle. */
354 IOMMMIOHANDLE hMmio;
355 /** The event semaphore the command thread waits on. */
356 SUPSEMEVENT hEvtCmdThread;
357 /** Whether the command thread has been signaled for wake up. */
358 bool volatile fCmdThreadSignaled;
359 /** Padding. */
360 bool afPadding0[3];
361 /** The IOMMU PCI address. */
362 PCIBDF uPciAddress;
363
364#ifdef IOMMU_WITH_DTE_CACHE
365 /** The critsect that protects the cache from concurrent access. */
366 PDMCRITSECT CritSectCache;
367 /** Array of device IDs. */
368 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
369 /** Array of DTE cache entries. */
370 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
371#endif
372#ifdef IOMMU_WITH_IRTE_CACHE
373 /** Array of IRTE cache entries. */
374 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
375#endif
376
377 /** @name PCI: Base capability block registers.
378 * @{ */
379 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
380 /** @} */
381
382 /** @name MMIO: Control and status registers.
383 * @{ */
384 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
385 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
386 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
387 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
388 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
389 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
390 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
391 /** @} */
392
393 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
394 * @{ */
395 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
396 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
397 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
398 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
399 /** @} */
400
401 /** @todo IOMMU: SMI filter. */
402
403 /** @name MMIO: Guest Virtual-APIC Log registers.
404 * @{ */
405 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
406 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
407 /** @} */
408
409 /** @name MMIO: Alternate PPR and Event Log registers.
410 * @{ */
411 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
412 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
413 /** @} */
414
415 /** @name MMIO: Device-specific feature registers.
416 * @{ */
417 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
418 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
419 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
420 /** @} */
421
422 /** @name MMIO: MSI Capability Block registers.
423 * @{ */
424 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
425 /** @} */
426
427 /** @name MMIO: Performance Optimization Control registers.
428 * @{ */
429 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
430 /** @} */
431
432 /** @name MMIO: x2APIC Control registers.
433 * @{ */
434 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
435 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
436 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
437 /** @} */
438
439 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
440 * @{ */
441 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
442 /** @} */
443
444 /** @name MMIO: Reserved register.
445 * @{ */
446 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
447 /** @} */
448
449 /** @name MMIO: Command and Event Log pointer registers.
450 * @{ */
451 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
452 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
453 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
454 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
455 /** @} */
456
457 /** @name MMIO: Command and Event Status register.
458 * @{ */
459 IOMMU_STATUS_T Status; /**< IOMMU status register. */
460 /** @} */
461
462 /** @name MMIO: PPR Log Head and Tail pointer registers.
463 * @{ */
464 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
465 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
466 /** @} */
467
468 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
469 * @{ */
470 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
471 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
472 /** @} */
473
474 /** @name MMIO: PPR Log B Head and Tail pointer registers.
475 * @{ */
476 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
477 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
478 /** @} */
479
480 /** @name MMIO: Event Log B Head and Tail pointer registers.
481 * @{ */
482 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
483 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
484 /** @} */
485
486 /** @name MMIO: PPR Log Overflow protection registers.
487 * @{ */
488 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
489 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
490 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
491 /** @} */
492
493 /** @todo IOMMU: IOMMU Event counter registers. */
494
495#ifdef VBOX_WITH_STATISTICS
496 /** @name IOMMU: Stat counters.
497 * @{ */
498 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
499 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
500 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
501 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
502
503 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
504 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
505
506 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
507 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
508 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
509 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
510
511 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
512 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
513 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
514 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
515
516 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
517 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
518 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
519 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
520 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
521 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
522 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
523 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
524 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
525
526 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
527 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
528
529 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
530 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
531
532 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
533 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
534
535 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
536 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
537 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
538 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
539 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
540 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
541 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
542
543 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
544 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
545
546 STAMCOUNTER StatNonStdPageSize; /**< Number of non-standard page size translations. */
547 STAMCOUNTER StatIopfs; /**< Number of I/O page faults. */
548 /** @} */
549#endif
550} IOMMU;
551/** Pointer to the IOMMU device state. */
552typedef IOMMU *PIOMMU;
553/** Pointer to the const IOMMU device state. */
554typedef const IOMMU *PCIOMMU;
555AssertCompileMemberAlignment(IOMMU, hMmio, 8);
556#ifdef IOMMU_WITH_DTE_CACHE
557AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
558AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
559AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
560#endif
561#ifdef IOMMU_WITH_IRTE_CACHE
562AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
563#endif
564AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
565AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
566AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
567AssertCompileMemberAlignment(IOMMU, Status, 8);
568
569/**
570 * The ring-3 IOMMU device state.
571 */
572typedef struct IOMMUR3
573{
574 /** Device instance. */
575 PPDMDEVINSR3 pDevInsR3;
576 /** The IOMMU helpers. */
577 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
578 /** The command thread handle. */
579 R3PTRTYPE(PPDMTHREAD) pCmdThread;
580#ifdef IOMMU_WITH_IOTLBE_CACHE
581 /** Pointer to array of pre-allocated IOTLBEs. */
582 PIOTLBE paIotlbes;
583 /** Maps [DomainId,Iova] to [IOTLBE]. */
584 AVLU64TREE TreeIotlbe;
585 /** LRU list anchor for IOTLB entries. */
586 RTLISTANCHOR LstLruIotlbe;
587 /** Index of the next unused IOTLB. */
588 uint32_t idxUnusedIotlbe;
589 /** Number of cached IOTLB entries in the tree. */
590 uint32_t cCachedIotlbes;
591#endif
592} IOMMUR3;
593/** Pointer to the ring-3 IOMMU device state. */
594typedef IOMMUR3 *PIOMMUR3;
595/** Pointer to the const ring-3 IOMMU device state. */
596typedef const IOMMUR3 *PCIOMMUR3;
597#ifdef IOMMU_WITH_IOTLBE_CACHE
598AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
599AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
600AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
601#endif
602
603/**
604 * The ring-0 IOMMU device state.
605 */
606typedef struct IOMMUR0
607{
608 /** Device instance. */
609 PPDMDEVINSR0 pDevInsR0;
610 /** The IOMMU helpers. */
611 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
612} IOMMUR0;
613/** Pointer to the ring-0 IOMMU device state. */
614typedef IOMMUR0 *PIOMMUR0;
615
616/**
617 * The raw-mode IOMMU device state.
618 */
619typedef struct IOMMURC
620{
621 /** Device instance. */
622 PPDMDEVINSRC pDevInsRC;
623 /** The IOMMU helpers. */
624 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
625} IOMMURC;
626/** Pointer to the raw-mode IOMMU device state. */
627typedef IOMMURC *PIOMMURC;
628
629/** The IOMMU device state for the current context. */
630typedef CTX_SUFF(IOMMU) IOMMUCC;
631/** Pointer to the IOMMU device state for the current context. */
632typedef CTX_SUFF(PIOMMU) PIOMMUCC;
633
634/**
635 * IOMMU register access.
636 */
637typedef struct IOMMUREGACC
638{
639 const char *pszName;
640 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
641 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
642} IOMMUREGACC;
643/** Pointer to an IOMMU register access. */
644typedef IOMMUREGACC *PIOMMUREGACC;
645/** Pointer to a const IOMMU register access. */
646typedef IOMMUREGACC const *PCIOMMUREGACC;
647
648#ifdef IOMMU_WITH_IOTLBE_CACHE
649/**
650 * IOTLBE flush argument.
651 */
652typedef struct IOTLBEFLUSHARG
653{
654 /** The ring-3 IOMMU device state. */
655 PIOMMUR3 pIommuR3;
656 /** The domain ID to flush. */
657 uint16_t idDomain;
658} IOTLBEFLUSHARG;
659/** Pointer to an IOTLBE flush argument. */
660typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
661/** Pointer to a const IOTLBE flush argument. */
662typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
663
664/**
665 * IOTLBE Info. argument.
666 */
667typedef struct IOTLBEINFOARG
668{
669 /** The ring-3 IOMMU device state. */
670 PIOMMUR3 pIommuR3;
671 /** The info helper. */
672 PCDBGFINFOHLP pHlp;
673 /** The domain ID to dump IOTLB entry. */
674 uint16_t idDomain;
675} IOTLBEINFOARG;
676/** Pointer to an IOTLBE flush argument. */
677typedef IOTLBEINFOARG *PIOTLBEINFOARG;
678/** Pointer to a const IOTLBE flush argument. */
679typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
680#endif
681
682/**
683 * IOMMU operation auxiliary info.
684 */
685typedef struct IOMMUOPAUX
686{
687 /** The IOMMU operation being performed. */
688 IOMMUOP enmOp;
689 /** The device table entry (can be NULL). */
690 PCDTE_T pDte;
691 /** The device ID (bus, device, function). */
692 uint16_t idDevice;
693 /** The domain ID (when the DTE isn't provided). */
694 uint16_t idDomain;
695} IOMMUOPAUX;
696/** Pointer to an I/O address lookup struct. */
697typedef IOMMUOPAUX *PIOMMUOPAUX;
698/** Pointer to a const I/O address lookup struct. */
699typedef IOMMUOPAUX const *PCIOMMUOPAUX;
700
701typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
702 PIOPAGELOOKUP pPageLookup));
703typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
704
705
706/*********************************************************************************************************************************
707* Global Variables *
708*********************************************************************************************************************************/
709#ifdef IN_RING3
710/**
711 * An array of the number of device table segments supported.
712 * Indexed by u2DevTabSegSup.
713 */
714static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
715#endif
716
717#if (defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)) || defined(LOG_ENABLED)
718/**
719 * The IOMMU I/O permission names.
720 */
721static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
722#endif
723
724/**
725 * An array of the masks to select the device table segment index from a device ID.
726 */
727static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
728
729/**
730 * An array of the shift values to select the device table segment index from a
731 * device ID.
732 */
733static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
734
735/**
736 * The maximum size (inclusive) of each device table segment (0 to 7).
737 * Indexed by the device table segment index.
738 */
739static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
740
741
742#ifndef VBOX_DEVICE_STRUCT_TESTCASE
743/**
744 * Gets the maximum number of buffer entries for the given buffer length.
745 *
746 * @returns Number of buffer entries.
747 * @param uEncodedLen The length (power-of-2 encoded).
748 */
749DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
750{
751 Assert(uEncodedLen > 7);
752 Assert(uEncodedLen < 16);
753 return 2 << (uEncodedLen - 1);
754}
755
756
757/**
758 * Gets the total length of the buffer given a base register's encoded length.
759 *
760 * @returns The length of the buffer in bytes.
761 * @param uEncodedLen The length (power-of-2 encoded).
762 */
763DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
764{
765 Assert(uEncodedLen > 7);
766 Assert(uEncodedLen < 16);
767 return (2 << (uEncodedLen - 1)) << 4;
768}
769
770
771/**
772 * Gets the number of (unconsumed) entries in the event log.
773 *
774 * @returns The number of entries in the event log.
775 * @param pThis The shared IOMMU device state.
776 */
777static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
778{
779 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
780 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
781 if (idxTail >= idxHead)
782 return idxTail - idxHead;
783
784 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
785 return cMaxEvts - idxHead + idxTail;
786}
787
788
789#if (defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)) || defined(LOG_ENABLED)
790/**
791 * Gets the descriptive I/O permission name for a memory access.
792 *
793 * @returns The I/O permission name.
794 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
795 */
796static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
797{
798 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
799 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
800 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
801}
802#endif
803
804
805#ifdef IOMMU_WITH_DTE_CACHE
806/**
807 * Gets the basic I/O device flags for the given device table entry.
808 *
809 * @returns The basic I/O device flags.
810 * @param pDte The device table entry.
811 */
812static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
813{
814 /* Extract basic flags from bits 127:0 of the DTE. */
815 uint16_t fFlags = 0;
816 if (pDte->n.u1Valid)
817 {
818 fFlags |= IOMMU_DTE_CACHE_F_VALID;
819
820 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
821 if (pDte->n.u1SuppressAllPfEvents)
822 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
823 if (pDte->n.u1SuppressPfEvents)
824 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
825
826 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
827 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
828 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
829 }
830
831 /* Extract basic flags from bits 255:128 of the DTE. */
832 if (pDte->n.u1IntrMapValid)
833 {
834 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
835
836 /** @todo Skip the if check here (shift/mask the relevant bit over). */
837 if (pDte->n.u1IgnoreUnmappedIntrs)
838 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
839
840 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
841 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
842 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
843 }
844 return fFlags;
845}
846#endif
847
848
849/**
850 * Remaps the source MSI to the destination MSI given the IRTE.
851 *
852 * @param pMsiIn The source MSI.
853 * @param pMsiOut Where to store the remapped MSI.
854 * @param pIrte The IRTE used for the remapping.
855 */
856static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
857{
858 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
859 *pMsiOut = *pMsiIn;
860
861 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
862 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
863
864 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
865 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
866}
867
868
869#ifdef IOMMU_WITH_DTE_CACHE
870/**
871 * Looks up an entry in the DTE cache for the given device ID.
872 *
873 * @returns The index of the entry, or the cache capacity if no entry was found.
874 * @param pThis The shared IOMMU device state.
875 * @param idDevice The device ID (bus, device, function).
876 */
877DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
878{
879 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
880 for (uint16_t i = 0; i < cDeviceIds; i++)
881 {
882 if (pThis->aDeviceIds[i] == idDevice)
883 return i;
884 }
885 return cDeviceIds;
886}
887
888
889/**
890 * Gets an free/unused DTE cache entry.
891 *
892 * @returns The index of an unused entry, or cache capacity if the cache is full.
893 * @param pThis The shared IOMMU device state.
894 */
895DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
896{
897 /*
898 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
899 * (the latter being an ugly hack) and cannot be a valid device ID.
900 */
901 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
902 for (uint16_t i = 0; i < cDeviceIds; i++)
903 {
904 if (!pThis->aDeviceIds[i])
905 return i;
906 }
907 return cDeviceIds;
908}
909
910
911/**
912 * Adds a DTE cache entry at the given index.
913 *
914 * @param pThis The shared IOMMU device state.
915 * @param idxDte The index of the DTE cache entry.
916 * @param idDevice The device ID (bus, device, function).
917 * @param fFlags Device flags to set, see IOMMU_DTE_CACHE_F_XXX.
918 * @param idDomain The domain ID.
919 *
920 * @remarks Requires the cache lock to be taken.
921 */
922DECL_FORCE_INLINE(void) iommuAmdDteCacheAddAtIndex(PIOMMU pThis, uint16_t idxDte, uint16_t idDevice, uint16_t fFlags,
923 uint16_t idDomain)
924{
925 pThis->aDeviceIds[idxDte] = idDevice;
926 pThis->aDteCache[idxDte].fFlags = fFlags;
927 pThis->aDteCache[idxDte].idDomain = idDomain;
928}
929
930
931/**
932 * Adds a DTE cache entry.
933 *
934 * @param pDevIns The IOMMU instance data.
935 * @param idDevice The device ID (bus, device, function).
936 * @param pDte The device table entry.
937 */
938static void iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte)
939{
940 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT;
941 uint16_t const idDomain = pDte->n.u16DomainId;
942
943 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
944 IOMMU_CACHE_LOCK(pDevIns, pThis);
945
946 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
947 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
948 if ( idxDte >= cDteCache /* Not found. */
949 && (idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache) /* Get new/unused slot index. */
950 iommuAmdDteCacheAddAtIndex(pThis, idxDte, idDevice, fFlags, idDomain);
951
952 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
953}
954
955
956/**
957 * Updates flags for an existing DTE cache entry given its index.
958 *
959 * @param pThis The shared IOMMU device state.
960 * @param idxDte The index of the DTE cache entry.
961 * @param fOrMask Device flags to add to the existing flags, see
962 * IOMMU_DTE_CACHE_F_XXX.
963 * @param fAndMask Device flags to remove from the existing flags, see
964 * IOMMU_DTE_CACHE_F_XXX.
965 *
966 * @remarks Requires the cache lock to be taken.
967 */
968DECL_FORCE_INLINE(void) iommuAmdDteCacheUpdateFlagsForIndex(PIOMMU pThis, uint16_t idxDte, uint16_t fOrMask, uint16_t fAndMask)
969{
970 uint16_t const fOldFlags = pThis->aDteCache[idxDte].fFlags;
971 uint16_t const fNewFlags = (fOldFlags | fOrMask) & ~fAndMask;
972 Assert(fOldFlags & IOMMU_DTE_CACHE_F_PRESENT);
973 pThis->aDteCache[idxDte].fFlags = fNewFlags;
974}
975
976
977#ifdef IOMMU_WITH_IOTLBE_CACHE
978/**
979 * Adds a new DTE cache entry or updates flags for an existing DTE cache entry.
980 * If the cache is full, nothing happens.
981 *
982 * @param pDevIns The IOMMU instance data.
983 * @param pDte The device table entry.
984 * @param idDevice The device ID (bus, device, function).
985 * @param fOrMask Device flags to add to the existing flags, see
986 * IOMMU_DTE_CACHE_F_XXX.
987 * @param fAndMask Device flags to remove from the existing flags, see
988 * IOMMU_DTE_CACHE_F_XXX.
989 */
990static void iommuAmdDteCacheAddOrUpdateFlags(PPDMDEVINS pDevIns, PCDTE_T pDte, uint16_t idDevice, uint16_t fOrMask,
991 uint16_t fAndMask)
992{
993 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
994 IOMMU_CACHE_LOCK(pDevIns, pThis);
995
996 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
997 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
998 if (idxDte < cDteCache)
999 iommuAmdDteCacheUpdateFlagsForIndex(pThis, idxDte, fOrMask, fAndMask);
1000 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
1001 {
1002 uint16_t const fFlags = (iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask) & ~fAndMask;
1003 iommuAmdDteCacheAddAtIndex(pThis, idxDte, idDevice, fFlags, pDte->n.u16DomainId);
1004 }
1005 /* else: cache is full, shouldn't really happen. */
1006
1007 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1008}
1009#endif
1010
1011
1012/**
1013 * Updates flags for an existing DTE cache entry.
1014 *
1015 * @param pDevIns The IOMMU instance data.
1016 * @param idDevice The device ID (bus, device, function).
1017 * @param fOrMask Device flags to add to the existing flags, see
1018 * IOMMU_DTE_CACHE_F_XXX.
1019 * @param fAndMask Device flags to remove from the existing flags, see
1020 * IOMMU_DTE_CACHE_F_XXX.
1021 */
1022static void iommuAmdDteCacheUpdateFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fOrMask, uint16_t fAndMask)
1023{
1024 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1025 IOMMU_CACHE_LOCK(pDevIns, pThis);
1026
1027 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1028 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1029 if (idxDte < cDteCache)
1030 iommuAmdDteCacheUpdateFlagsForIndex(pThis, idxDte, fOrMask, fAndMask);
1031
1032 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1033}
1034
1035
1036# ifdef IN_RING3
1037/**
1038 * Removes a DTE cache entry.
1039 *
1040 * @param pDevIns The IOMMU instance data.
1041 * @param idDevice The device ID to remove cache entries for.
1042 */
1043static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1044{
1045 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1046 IOMMU_CACHE_LOCK(pDevIns, pThis);
1047
1048 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1049 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1050 if (idxDte < cDteCache)
1051 {
1052 pThis->aDteCache[idxDte].fFlags = 0;
1053 pThis->aDteCache[idxDte].idDomain = 0;
1054 }
1055
1056 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1057}
1058
1059
1060/**
1061 * Removes all entries in the device table entry cache.
1062 *
1063 * @param pDevIns The IOMMU instance data.
1064 */
1065static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1066{
1067 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1068 IOMMU_CACHE_LOCK(pDevIns, pThis);
1069 RT_ZERO(pThis->aDeviceIds);
1070 RT_ZERO(pThis->aDteCache);
1071 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1072}
1073# endif /* IN_RING3 */
1074#endif /* IOMMU_WITH_DTE_CACHE */
1075
1076
1077#ifdef IOMMU_WITH_IOTLBE_CACHE
1078/**
1079 * Moves the IOTLB entry to the least recently used slot.
1080 *
1081 * @param pThisR3 The ring-3 IOMMU device state.
1082 * @param pIotlbe The IOTLB entry to move.
1083 */
1084DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1085{
1086 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1087 {
1088 RTListNodeRemove(&pIotlbe->NdLru);
1089 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1090 }
1091}
1092
1093
1094/**
1095 * Moves the IOTLB entry to the most recently used slot.
1096 *
1097 * @param pThisR3 The ring-3 IOMMU device state.
1098 * @param pIotlbe The IOTLB entry to move.
1099 */
1100DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1101{
1102 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1103 {
1104 RTListNodeRemove(&pIotlbe->NdLru);
1105 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1106 }
1107}
1108
1109
1110# ifdef IN_RING3
1111/**
1112 * Dumps the IOTLB entry via the debug info helper.
1113 *
1114 * @returns VINF_SUCCESS.
1115 * @param pNode Pointer to an IOTLB entry to dump info.
1116 * @param pvUser Pointer to an IOTLBEINFOARG.
1117 */
1118static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1119{
1120 /* Validate. */
1121 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1122 AssertPtr(pArgs);
1123 AssertPtr(pArgs->pIommuR3);
1124 AssertPtr(pArgs->pHlp);
1125 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1126
1127 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1128 if (idDomain == pArgs->idDomain)
1129 {
1130 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1131 AVLU64KEY const uKey = pIotlbe->Core.Key;
1132 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1133 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1134 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1135 size_t const cbPage = RT_BIT_64(cShift);
1136 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1137 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1138 bool const fEvictPending = pIotlbe->fEvictPending;
1139
1140 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1141 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1142 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1143 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1144 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1145 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1146 }
1147
1148 return VINF_SUCCESS;
1149}
1150# endif /* IN_RING3 */
1151
1152
1153/**
1154 * Removes the IOTLB entry if it's associated with the specified domain ID.
1155 *
1156 * @returns VINF_SUCCESS.
1157 * @param pNode Pointer to an IOTLBE.
1158 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1159 */
1160static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1161{
1162 /* Validate. */
1163 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1164 AssertPtr(pArgs);
1165 AssertPtr(pArgs->pIommuR3);
1166 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1167
1168 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1169 if (idDomain == pArgs->idDomain)
1170 {
1171 /* Mark this entry is as invalidated and needs to be evicted later. */
1172 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1173 pIotlbe->fEvictPending = true;
1174 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1175 }
1176 return VINF_SUCCESS;
1177}
1178
1179
1180/**
1181 * Destroys an IOTLB entry that's in the tree.
1182 *
1183 * @returns VINF_SUCCESS.
1184 * @param pNode Pointer to an IOTLBE.
1185 * @param pvUser Opaque data. Currently not used, will be NULL.
1186 */
1187static DECLCALLBACK(int) iommuAmdIotlbEntryDestroy(PAVLU64NODECORE pNode, void *pvUser)
1188{
1189 RT_NOREF(pvUser);
1190 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1191 Assert(pIotlbe);
1192 pIotlbe->NdLru.pNext = NULL;
1193 pIotlbe->NdLru.pPrev = NULL;
1194 RT_ZERO(pIotlbe->PageLookup);
1195 pIotlbe->fEvictPending = false;
1196 return VINF_SUCCESS;
1197}
1198
1199
1200/**
1201 * Inserts an IOTLB entry into the cache.
1202 *
1203 * @param pThis The shared IOMMU device state.
1204 * @param pThisR3 The ring-3 IOMMU device state.
1205 * @param pIotlbe The IOTLB entry to initialize and insert.
1206 * @param idDomain The domain ID.
1207 * @param uIova The I/O virtual address.
1208 * @param pPageLookup The I/O page lookup result of the access.
1209 */
1210static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1211 PCIOPAGELOOKUP pPageLookup)
1212{
1213 /* Initialize the IOTLB entry with results of the I/O page walk. */
1214 AVLU64KEY const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1215 Assert(uKey != IOMMU_IOTLB_KEY_NIL);
1216
1217 /* Check if the entry already exists. */
1218 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1219 if (!pFound)
1220 {
1221 /* Insert the entry into the cache. */
1222 pIotlbe->Core.Key = uKey;
1223 pIotlbe->PageLookup = *pPageLookup;
1224 Assert(!pIotlbe->fEvictPending);
1225
1226 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1227 Assert(fInserted); NOREF(fInserted);
1228 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1229 ++pThisR3->cCachedIotlbes;
1230 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1231 }
1232 else
1233 {
1234 /* Update the existing entry. */
1235 Assert(pFound->Core.Key == uKey);
1236 if (pFound->fEvictPending)
1237 {
1238 pFound->fEvictPending = false;
1239 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1240 }
1241 pFound->PageLookup = *pPageLookup;
1242 }
1243}
1244
1245
1246/**
1247 * Removes an IOTLB entry from the cache for the given key.
1248 *
1249 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1250 * the tree.
1251 * @param pThis The shared IOMMU device state.
1252 * @param pThisR3 The ring-3 IOMMU device state.
1253 * @param uKey The key of the IOTLB entry to remove.
1254 */
1255static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1256{
1257 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1258 if (pIotlbe)
1259 {
1260 if (pIotlbe->fEvictPending)
1261 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1262
1263 RT_ZERO(pIotlbe->Core);
1264 RT_ZERO(pIotlbe->PageLookup);
1265 /* We must not erase the LRU node connections here! */
1266 pIotlbe->fEvictPending = false;
1267 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1268
1269 Assert(pThisR3->cCachedIotlbes > 0);
1270 --pThisR3->cCachedIotlbes;
1271 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1272 }
1273 return pIotlbe;
1274}
1275
1276
1277/**
1278 * Looks up an IOTLB from the cache.
1279 *
1280 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1281 * @param pThis The shared IOMMU device state.
1282 * @param pThisR3 The ring-3 IOMMU device state.
1283 * @param idDomain The domain ID.
1284 * @param uIova The I/O virtual address.
1285 */
1286static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1287{
1288 RT_NOREF(pThis);
1289
1290 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1291 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1292 if ( pIotlbe
1293 && !pIotlbe->fEvictPending)
1294 return pIotlbe;
1295
1296 /*
1297 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1298 * them from the cache immediately. We found an entry pending eviction, just return that
1299 * nothing was found (rather than evicting now).
1300 */
1301 return NULL;
1302}
1303
1304
1305/**
1306 * Adds an IOTLB entry to the cache.
1307 *
1308 * @param pThis The shared IOMMU device state.
1309 * @param pThisR3 The ring-3 IOMMU device state.
1310 * @param idDomain The domain ID.
1311 * @param uIovaPage The I/O virtual address (must be 4K aligned).
1312 * @param pPageLookup The I/O page lookup result of the access.
1313 */
1314static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIovaPage, PCIOPAGELOOKUP pPageLookup)
1315{
1316 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
1317 Assert(pPageLookup);
1318 Assert(pPageLookup->cShift <= 51);
1319 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1320
1321 /*
1322 * If there are no unused IOTLB entries, evict the LRU entry.
1323 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1324 */
1325 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1326 {
1327 /* Grab the least recently used entry. */
1328 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1329 Assert(pIotlbe);
1330
1331 /* If the entry is in the cache, remove it. */
1332 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1333 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1334
1335 /* Initialize and insert the IOTLB entry into the cache. */
1336 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIovaPage, pPageLookup);
1337
1338 /* Move the entry to the most recently used slot. */
1339 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1340 }
1341 else
1342 {
1343 /* Grab an unused IOTLB entry from the pre-allocated list. */
1344 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1345 ++pThisR3->idxUnusedIotlbe;
1346
1347 /* Initialize and insert the IOTLB entry into the cache. */
1348 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIovaPage, pPageLookup);
1349
1350 /* Add the entry to the most recently used slot. */
1351 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1352 }
1353}
1354
1355
1356/**
1357 * Removes all IOTLB entries from the cache.
1358 *
1359 * @param pDevIns The IOMMU instance data.
1360 */
1361static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1362{
1363 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1364 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1365 IOMMU_CACHE_LOCK(pDevIns, pThis);
1366
1367 if (pThisR3->cCachedIotlbes > 0)
1368 {
1369 RTAvlU64Destroy(&pThisR3->TreeIotlbe, iommuAmdIotlbEntryDestroy, NULL /* pvParam */);
1370 RTListInit(&pThisR3->LstLruIotlbe);
1371 pThisR3->idxUnusedIotlbe = 0;
1372 pThisR3->cCachedIotlbes = 0;
1373 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1374 }
1375
1376 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1377}
1378
1379
1380/**
1381 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1382 * domain ID from the cache.
1383 *
1384 * @param pDevIns The IOMMU instance data.
1385 * @param idDomain The domain ID.
1386 * @param uIova The I/O virtual address to invalidate.
1387 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1388 */
1389static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1390{
1391 /* Validate. */
1392 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1393 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1394 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1395
1396 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1397 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1398 IOMMU_CACHE_LOCK(pDevIns, pThis);
1399
1400 do
1401 {
1402 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1403 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1404 if (pIotlbe)
1405 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1406 uIova += X86_PAGE_4K_SIZE;
1407 cbInvalidate -= X86_PAGE_4K_SIZE;
1408 } while (cbInvalidate > 0);
1409
1410 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1411}
1412
1413
1414/**
1415 * Removes all IOTLB entries for the specified domain ID.
1416 *
1417 * @param pDevIns The IOMMU instance data.
1418 * @param idDomain The domain ID.
1419 */
1420static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1421{
1422 /*
1423 * We need to iterate the tree and search based on the domain ID.
1424 * But it seems we cannot remove items while iterating the tree.
1425 * Thus, we simply mark entries for eviction later but move them to the LRU
1426 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1427 */
1428 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1429 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1430 IOMMU_CACHE_LOCK(pDevIns, pThis);
1431
1432 IOTLBEFLUSHARG Args;
1433 Args.pIommuR3 = pThisR3;
1434 Args.idDomain = idDomain;
1435 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1436
1437 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1438}
1439
1440
1441/**
1442 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1443 *
1444 * @param pDevIns The IOMMU instance data.
1445 * @param idDomain The domain ID.
1446 * @param uIovaPage The I/O virtual address (must be 4K aligned).
1447 * @param cbContiguous The size of the access.
1448 * @param pAddrOut The translated I/O address lookup.
1449 *
1450 * @remarks All pages in the range specified by @c cbContiguous must have identical
1451 * permissions and page sizes.
1452 */
1453static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIovaPage, size_t cbContiguous,
1454 PCIOPAGELOOKUP pAddrOut)
1455{
1456 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
1457
1458 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1459 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1460
1461 IOPAGELOOKUP PageLookup;
1462 PageLookup.GCPhysSpa = pAddrOut->GCPhysSpa & X86_PAGE_4K_BASE_MASK;
1463 PageLookup.cShift = pAddrOut->cShift;
1464 PageLookup.fPerm = pAddrOut->fPerm;
1465
1466 size_t const cbIova = RT_ALIGN_Z(cbContiguous, X86_PAGE_4K_SIZE);
1467 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1468 Assert(cbIova >= X86_PAGE_4K_SIZE);
1469
1470 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1471 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1472
1473 IOMMU_CACHE_LOCK(pDevIns, pThis);
1474 /** @todo Re-check DTE cache? */
1475 /*
1476 * Add IOTLB entries for every page in the access.
1477 * The page size and permissions are assumed to be identical to every
1478 * page in this access.
1479 */
1480 while (cPages > 0)
1481 {
1482 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIovaPage, &PageLookup);
1483 uIovaPage += X86_PAGE_4K_SIZE;
1484 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1485 --cPages;
1486 }
1487 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1488}
1489#endif /* IOMMU_WITH_IOTLBE_CACHE */
1490
1491
1492#ifdef IOMMU_WITH_IRTE_CACHE
1493/**
1494 * Looks up an IRTE cache entry.
1495 *
1496 * @returns Index of the found entry, or cache capacity if not found.
1497 * @param pThis The shared IOMMU device state.
1498 * @param idDevice The device ID (bus, device, function).
1499 * @param offIrte The offset into the interrupt remap table.
1500 */
1501static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1502{
1503 /** @todo Consider sorting and binary search when the cache capacity grows.
1504 * For the IRTE cache this should be okay since typically guests do not alter the
1505 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1506 * often. */
1507 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1508 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1509 for (uint16_t i = 0; i < cIrteCache; i++)
1510 if (pThis->aIrteCache[i].uKey == uKey)
1511 return i;
1512 return cIrteCache;
1513}
1514
1515
1516/**
1517 * Gets a free/unused IRTE cache entry.
1518 *
1519 * @returns The index of an unused entry, or cache capacity if the cache is full.
1520 * @param pThis The shared IOMMU device state.
1521 */
1522static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1523{
1524 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1525 for (uint16_t i = 0; i < cIrteCache; i++)
1526 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1527 {
1528 Assert(!pThis->aIrteCache[i].Irte.u32);
1529 return i;
1530 }
1531 return cIrteCache;
1532}
1533
1534
1535/**
1536 * Looks up the IRTE cache for the given MSI.
1537 *
1538 * @returns VBox status code.
1539 * @param pDevIns The IOMMU instance data.
1540 * @param idDevice The device ID (bus, device, function).
1541 * @param enmOp The IOMMU operation being performed.
1542 * @param pMsiIn The source MSI.
1543 * @param pMsiOut Where to store the remapped MSI.
1544 */
1545static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1546{
1547 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1548
1549 int rc = VERR_NOT_FOUND;
1550 /* Deal with such cases in the slower/fallback path. */
1551 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1552 { /* likely */ }
1553 else
1554 return rc;
1555
1556 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1557 IOMMU_CACHE_LOCK(pDevIns, pThis);
1558
1559 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1560 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1561 {
1562 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1563 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1564 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1565 {
1566 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1567
1568 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1569 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1570 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1571 {
1572 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1573 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1574 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1575 {
1576 /* Interrupt table length has been verified prior to adding entries to the cache. */
1577 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1578 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1579 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1580 {
1581 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1582 Assert(pIrte->n.u1RemapEnable);
1583 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1584 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1585 rc = VINF_SUCCESS;
1586 }
1587 }
1588 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1589 {
1590 *pMsiOut = *pMsiIn;
1591 rc = VINF_SUCCESS;
1592 }
1593 }
1594 }
1595 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1596 {
1597 *pMsiOut = *pMsiIn;
1598 rc = VINF_SUCCESS;
1599 }
1600 }
1601
1602 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1603 return rc;
1604}
1605
1606
1607/**
1608 * Adds or updates the IRTE cache for the given IRTE.
1609 *
1610 * @returns VBox status code.
1611 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1612 *
1613 * @param pDevIns The IOMMU instance data.
1614 * @param idDevice The device ID (bus, device, function).
1615 * @param offIrte The offset into the interrupt remap table.
1616 * @param pIrte The IRTE to cache.
1617 */
1618static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1619{
1620 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1621
1622 int rc = VINF_SUCCESS;
1623 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1624 Assert(idDevice != pThis->uPciAddress);
1625 IOMMU_CACHE_LOCK(pDevIns, pThis);
1626
1627 /* Find an existing entry or get an unused slot. */
1628 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1629 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1630 if ( idxIrteCache < cIrteCache
1631 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1632 {
1633 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1634 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1635 }
1636 else
1637 rc = VERR_OUT_OF_RESOURCES;
1638
1639 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1640 return rc;
1641}
1642
1643
1644# ifdef IN_RING3
1645/**
1646 * Removes IRTE cache entries for the given device ID.
1647 *
1648 * @param pDevIns The IOMMU instance data.
1649 * @param idDevice The device ID (bus, device, function).
1650 */
1651static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1652{
1653 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1654 IOMMU_CACHE_LOCK(pDevIns, pThis);
1655 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1656 for (uint16_t i = 0; i < cIrteCache; i++)
1657 {
1658 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1659 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1660 {
1661 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1662 pIrteCache->Irte.u32 = 0;
1663 /* There could multiple IRTE entries for a device ID, continue searching. */
1664 }
1665 }
1666 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1667}
1668
1669
1670/**
1671 * Removes all IRTE cache entries.
1672 *
1673 * @param pDevIns The IOMMU instance data.
1674 */
1675static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1676{
1677 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1678 IOMMU_CACHE_LOCK(pDevIns, pThis);
1679 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1680 for (uint16_t i = 0; i < cIrteCache; i++)
1681 {
1682 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1683 pThis->aIrteCache[i].Irte.u32 = 0;
1684 }
1685 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1686}
1687# endif /* IN_RING3 */
1688#endif /* IOMMU_WITH_IRTE_CACHE */
1689
1690
1691/**
1692 * Atomically reads the control register without locking the IOMMU device.
1693 *
1694 * @returns The control register.
1695 * @param pThis The shared IOMMU device state.
1696 */
1697DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1698{
1699 IOMMU_CTRL_T Ctrl;
1700 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1701 return Ctrl;
1702}
1703
1704
1705/**
1706 * Returns whether MSI is enabled for the IOMMU.
1707 *
1708 * @returns Whether MSI is enabled.
1709 * @param pDevIns The IOMMU device instance.
1710 *
1711 * @note There should be a PCIDevXxx function for this.
1712 */
1713static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1714{
1715 MSI_CAP_HDR_T MsiCapHdr;
1716 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1717 return MsiCapHdr.n.u1MsiEnable;
1718}
1719
1720
1721/**
1722 * Signals a PCI target abort.
1723 *
1724 * @param pDevIns The IOMMU device instance.
1725 */
1726static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1727{
1728 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1729 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1730 PDMPciDevSetStatus(pPciDev, u16Status);
1731}
1732
1733
1734/**
1735 * Wakes up the command thread if there are commands to be processed.
1736 *
1737 * @param pDevIns The IOMMU device instance.
1738 *
1739 * @remarks The IOMMU lock must be held while calling this!
1740 */
1741static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1742{
1743 Log4Func(("\n"));
1744
1745 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1746 if ( pThis->Status.n.u1CmdBufRunning
1747 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1748 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1749 {
1750 Log4Func(("Signaling command thread\n"));
1751 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1752 }
1753}
1754
1755
1756/**
1757 * Reads the Device Table Base Address Register.
1758 */
1759static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1760{
1761 RT_NOREF(pDevIns, offReg);
1762 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1763 return VINF_SUCCESS;
1764}
1765
1766
1767/**
1768 * Reads the Command Buffer Base Address Register.
1769 */
1770static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1771{
1772 RT_NOREF(pDevIns, offReg);
1773 *pu64Value = pThis->CmdBufBaseAddr.u64;
1774 return VINF_SUCCESS;
1775}
1776
1777
1778/**
1779 * Reads the Event Log Base Address Register.
1780 */
1781static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1782{
1783 RT_NOREF(pDevIns, offReg);
1784 *pu64Value = pThis->EvtLogBaseAddr.u64;
1785 return VINF_SUCCESS;
1786}
1787
1788
1789/**
1790 * Reads the Control Register.
1791 */
1792static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1793{
1794 RT_NOREF(pDevIns, offReg);
1795 *pu64Value = pThis->Ctrl.u64;
1796 return VINF_SUCCESS;
1797}
1798
1799
1800/**
1801 * Reads the Exclusion Range Base Address Register.
1802 */
1803static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1804{
1805 RT_NOREF(pDevIns, offReg);
1806 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1807 return VINF_SUCCESS;
1808}
1809
1810
1811/**
1812 * Reads to the Exclusion Range Limit Register.
1813 */
1814static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1815{
1816 RT_NOREF(pDevIns, offReg);
1817 *pu64Value = pThis->ExclRangeLimit.u64;
1818 return VINF_SUCCESS;
1819}
1820
1821
1822/**
1823 * Reads to the Extended Feature Register.
1824 */
1825static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1826{
1827 RT_NOREF(pDevIns, offReg);
1828 *pu64Value = pThis->ExtFeat.u64;
1829 return VINF_SUCCESS;
1830}
1831
1832
1833/**
1834 * Reads to the PPR Log Base Address Register.
1835 */
1836static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1837{
1838 RT_NOREF(pDevIns, offReg);
1839 *pu64Value = pThis->PprLogBaseAddr.u64;
1840 return VINF_SUCCESS;
1841}
1842
1843
1844/**
1845 * Writes the Hardware Event Register (Hi).
1846 */
1847static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1848{
1849 RT_NOREF(pDevIns, offReg);
1850 *pu64Value = pThis->HwEvtHi.u64;
1851 return VINF_SUCCESS;
1852}
1853
1854
1855/**
1856 * Reads the Hardware Event Register (Lo).
1857 */
1858static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1859{
1860 RT_NOREF(pDevIns, offReg);
1861 *pu64Value = pThis->HwEvtLo;
1862 return VINF_SUCCESS;
1863}
1864
1865
1866/**
1867 * Reads the Hardware Event Status Register.
1868 */
1869static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1870{
1871 RT_NOREF(pDevIns, offReg);
1872 *pu64Value = pThis->HwEvtStatus.u64;
1873 return VINF_SUCCESS;
1874}
1875
1876
1877/**
1878 * Reads to the GA Log Base Address Register.
1879 */
1880static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1881{
1882 RT_NOREF(pDevIns, offReg);
1883 *pu64Value = pThis->GALogBaseAddr.u64;
1884 return VINF_SUCCESS;
1885}
1886
1887
1888/**
1889 * Reads to the PPR Log B Base Address Register.
1890 */
1891static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1892{
1893 RT_NOREF(pDevIns, offReg);
1894 *pu64Value = pThis->PprLogBBaseAddr.u64;
1895 return VINF_SUCCESS;
1896}
1897
1898
1899/**
1900 * Reads to the Event Log B Base Address Register.
1901 */
1902static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1903{
1904 RT_NOREF(pDevIns, offReg);
1905 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1906 return VINF_SUCCESS;
1907}
1908
1909
1910/**
1911 * Reads the Device Table Segment Base Address Register.
1912 */
1913static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1914{
1915 RT_NOREF(pDevIns);
1916
1917 /* Paranoia; the MMIO register offset should have been been validated by the caller. */
1918 Assert(offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST <= IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST);
1919
1920 /* Figure out which segment is being written. */
1921 uint8_t const offSegment = (uint8_t)(offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1922 uint8_t const idxSegment = offSegment + 1;
1923 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1924
1925 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1926 return VINF_SUCCESS;
1927}
1928
1929
1930/**
1931 * Reads the Device Specific Feature Extension (DSFX) Register.
1932 */
1933static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1934{
1935 RT_NOREF(pDevIns, offReg);
1936 *pu64Value = pThis->DevSpecificFeat.u64;
1937 return VINF_SUCCESS;
1938}
1939
1940/**
1941 * Reads the Device Specific Control Extension (DSCX) Register.
1942 */
1943static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1944{
1945 RT_NOREF(pDevIns, offReg);
1946 *pu64Value = pThis->DevSpecificCtrl.u64;
1947 return VINF_SUCCESS;
1948}
1949
1950
1951/**
1952 * Reads the Device Specific Status Extension (DSSX) Register.
1953 */
1954static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1955{
1956 RT_NOREF(pDevIns, offReg);
1957 *pu64Value = pThis->DevSpecificStatus.u64;
1958 return VINF_SUCCESS;
1959}
1960
1961
1962/**
1963 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1964 */
1965static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1966{
1967 RT_NOREF(pDevIns, offReg);
1968 uint32_t const uLo = pThis->MiscInfo.au32[0];
1969 uint32_t const uHi = pThis->MiscInfo.au32[1];
1970 *pu64Value = RT_MAKE_U64(uLo, uHi);
1971 return VINF_SUCCESS;
1972}
1973
1974
1975/**
1976 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1977 * Register (32-bit).
1978 */
1979static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1980{
1981 RT_NOREF(pThis, offReg);
1982 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1983 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1984 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1985 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1986 *pu64Value = RT_MAKE_U64(uLo, uHi);
1987 return VINF_SUCCESS;
1988}
1989
1990
1991/**
1992 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1993 */
1994static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1995{
1996 RT_NOREF(pThis, offReg);
1997 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1998 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1999 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
2000 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
2001 *pu64Value = RT_MAKE_U64(uLo, uHi);
2002 return VINF_SUCCESS;
2003}
2004
2005
2006/**
2007 * Reads the Command Buffer Head Pointer Register.
2008 */
2009static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2010{
2011 RT_NOREF(pDevIns, offReg);
2012 *pu64Value = pThis->CmdBufHeadPtr.u64;
2013 return VINF_SUCCESS;
2014}
2015
2016
2017/**
2018 * Reads the Command Buffer Tail Pointer Register.
2019 */
2020static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2021{
2022 RT_NOREF(pDevIns, offReg);
2023 *pu64Value = pThis->CmdBufTailPtr.u64;
2024 return VINF_SUCCESS;
2025}
2026
2027
2028/**
2029 * Reads the Event Log Head Pointer Register.
2030 */
2031static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2032{
2033 RT_NOREF(pDevIns, offReg);
2034 *pu64Value = pThis->EvtLogHeadPtr.u64;
2035 return VINF_SUCCESS;
2036}
2037
2038
2039/**
2040 * Reads the Event Log Tail Pointer Register.
2041 */
2042static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2043{
2044 RT_NOREF(pDevIns, offReg);
2045 *pu64Value = pThis->EvtLogTailPtr.u64;
2046 return VINF_SUCCESS;
2047}
2048
2049
2050/**
2051 * Reads the Status Register.
2052 */
2053static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2054{
2055 RT_NOREF(pDevIns, offReg);
2056 *pu64Value = pThis->Status.u64;
2057 return VINF_SUCCESS;
2058}
2059
2060
2061/**
2062 * Writes the Device Table Base Address Register.
2063 */
2064static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2065{
2066 RT_NOREF(pDevIns, offReg);
2067
2068 /* Mask out all unrecognized bits. */
2069 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2070
2071 /* Update the register. */
2072 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2073
2074 /* Paranoia. */
2075 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
2076 return VINF_SUCCESS;
2077}
2078
2079
2080/**
2081 * Writes the Command Buffer Base Address Register.
2082 */
2083static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2084{
2085 RT_NOREF(pDevIns, offReg);
2086
2087 /*
2088 * While this is not explicitly specified like the event log base address register,
2089 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2090 * Inconsistent specs :/
2091 */
2092 if (pThis->Status.n.u1CmdBufRunning)
2093 {
2094 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2095 return VINF_SUCCESS;
2096 }
2097
2098 /* Mask out all unrecognized bits. */
2099 CMD_BUF_BAR_T CmdBufBaseAddr;
2100 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2101
2102 /* Validate the length. */
2103 if (CmdBufBaseAddr.n.u4Len >= 8)
2104 {
2105 /* Update the register. */
2106 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2107
2108 /*
2109 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2110 * See AMD IOMMU spec. 2.4 "Commands".
2111 */
2112 pThis->CmdBufHeadPtr.u64 = 0;
2113 pThis->CmdBufTailPtr.u64 = 0;
2114 }
2115 else
2116 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2117
2118 return VINF_SUCCESS;
2119}
2120
2121
2122/**
2123 * Writes the Event Log Base Address Register.
2124 */
2125static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2126{
2127 RT_NOREF(pDevIns, offReg);
2128
2129 /*
2130 * IOMMU behavior is undefined when software writes this register when event logging is running.
2131 * In our emulation, we ignore the write entirely.
2132 * See AMD IOMMU spec. "Event Log Base Address Register".
2133 */
2134 if (pThis->Status.n.u1EvtLogRunning)
2135 {
2136 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2137 return VINF_SUCCESS;
2138 }
2139
2140 /* Mask out all unrecognized bits. */
2141 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2142 EVT_LOG_BAR_T EvtLogBaseAddr;
2143 EvtLogBaseAddr.u64 = u64Value;
2144
2145 /* Validate the length. */
2146 if (EvtLogBaseAddr.n.u4Len >= 8)
2147 {
2148 /* Update the register. */
2149 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2150
2151 /*
2152 * Writing the event log base address, clears the event log head and tail pointers.
2153 * See AMD IOMMU spec. 2.5 "Event Logging".
2154 */
2155 pThis->EvtLogHeadPtr.u64 = 0;
2156 pThis->EvtLogTailPtr.u64 = 0;
2157 }
2158 else
2159 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2160
2161 return VINF_SUCCESS;
2162}
2163
2164
2165/**
2166 * Writes the Control Register.
2167 */
2168static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2169{
2170 RT_NOREF(pDevIns, offReg);
2171
2172 /* Mask out all unrecognized bits. */
2173 u64Value &= IOMMU_CTRL_VALID_MASK;
2174 IOMMU_CTRL_T NewCtrl;
2175 NewCtrl.u64 = u64Value;
2176
2177 /* Ensure the device table segments are within limits. */
2178 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2179 {
2180 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2181
2182 /* Update the register. */
2183 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2184
2185 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2186 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2187
2188 /* Enable or disable event logging when the bit transitions. */
2189 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2190 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2191 if ( fOldEvtLogEn != fNewEvtLogEn
2192 || fOldIommuEn != fNewIommuEn)
2193 {
2194 if ( fNewIommuEn
2195 && fNewEvtLogEn)
2196 {
2197 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2198 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2199 }
2200 else
2201 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2202 }
2203
2204 /* Enable or disable command buffer processing when the bit transitions. */
2205 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2206 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2207 if ( fOldCmdBufEn != fNewCmdBufEn
2208 || fOldIommuEn != fNewIommuEn)
2209 {
2210 if ( fNewCmdBufEn
2211 && fNewIommuEn)
2212 {
2213 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2214 LogFunc(("Command buffer enabled\n"));
2215
2216 /* Wake up the command thread to start processing commands if any. */
2217 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2218 }
2219 else
2220 {
2221 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2222 LogFunc(("Command buffer disabled\n"));
2223 }
2224 }
2225 }
2226 else
2227 {
2228 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2229 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2230 }
2231
2232 return VINF_SUCCESS;
2233}
2234
2235
2236/**
2237 * Writes to the Exclusion Range Base Address Register.
2238 */
2239static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2240{
2241 RT_NOREF(pDevIns, offReg);
2242 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2243 return VINF_SUCCESS;
2244}
2245
2246
2247/**
2248 * Writes to the Exclusion Range Limit Register.
2249 */
2250static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2251{
2252 RT_NOREF(pDevIns, offReg);
2253 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2254 u64Value |= UINT64_C(0xfff);
2255 pThis->ExclRangeLimit.u64 = u64Value;
2256 return VINF_SUCCESS;
2257}
2258
2259
2260/**
2261 * Writes the Hardware Event Register (Hi).
2262 */
2263static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2264{
2265 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2266 RT_NOREF(pDevIns, offReg);
2267 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2268 pThis->HwEvtHi.u64 = u64Value;
2269 return VINF_SUCCESS;
2270}
2271
2272
2273/**
2274 * Writes the Hardware Event Register (Lo).
2275 */
2276static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2277{
2278 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2279 RT_NOREF(pDevIns, offReg);
2280 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2281 pThis->HwEvtLo = u64Value;
2282 return VINF_SUCCESS;
2283}
2284
2285
2286/**
2287 * Writes the Hardware Event Status Register.
2288 */
2289static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2290{
2291 RT_NOREF(pDevIns, offReg);
2292
2293 /* Mask out all unrecognized bits. */
2294 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2295
2296 /*
2297 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2298 * If the current status bits or the bits being written are both 0, we've nothing to do.
2299 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2300 */
2301 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2302 if (!(HwStatus & RT_BIT(0)))
2303 return VINF_SUCCESS;
2304 if (u64Value & HwStatus & RT_BIT_64(0))
2305 HwStatus &= ~RT_BIT_64(0);
2306 if (u64Value & HwStatus & RT_BIT_64(1))
2307 HwStatus &= ~RT_BIT_64(1);
2308
2309 /* Update the register. */
2310 pThis->HwEvtStatus.u64 = HwStatus;
2311 return VINF_SUCCESS;
2312}
2313
2314
2315/**
2316 * Writes the Device Table Segment Base Address Register.
2317 */
2318static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2319{
2320 RT_NOREF(pDevIns);
2321
2322 /* Paranoia; the MMIO register offset should have been been validated by the caller. */
2323 Assert(offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST <= IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST);
2324
2325 /* Figure out which segment is being written. */
2326 uint8_t const offSegment = (uint8_t)(offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2327 uint8_t const idxSegment = offSegment + 1;
2328 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2329
2330 /* Mask out all unrecognized bits. */
2331 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2332 DEV_TAB_BAR_T DevTabSegBar;
2333 DevTabSegBar.u64 = u64Value;
2334
2335 /* Validate the size. */
2336 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2337 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2338 if (uSegSize <= uMaxSegSize)
2339 {
2340 /* Update the register. */
2341 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2342 }
2343 else
2344 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2345
2346 return VINF_SUCCESS;
2347}
2348
2349
2350/**
2351 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2352 */
2353static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2354{
2355 RT_NOREF(pDevIns, offReg);
2356
2357 /* MSI Vector Register 0 is read-only. */
2358 /* MSI Vector Register 1. */
2359 uint32_t const uReg = u64Value >> 32;
2360 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2361 return VINF_SUCCESS;
2362}
2363
2364
2365/**
2366 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2367 * Register (32-bit).
2368 */
2369static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2370{
2371 RT_NOREF(pThis, offReg);
2372 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2373 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2374
2375 /* MSI capability header. */
2376 {
2377 uint32_t const uReg = u64Value;
2378 MSI_CAP_HDR_T MsiCapHdr;
2379 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2380 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2381 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2382 }
2383
2384 /* MSI Address Lo. */
2385 {
2386 uint32_t const uReg = u64Value >> 32;
2387 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2388 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2389 }
2390
2391 return VINF_SUCCESS;
2392}
2393
2394
2395/**
2396 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2397 */
2398static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2399{
2400 RT_NOREF(pThis, offReg);
2401 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2402 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2403
2404 /* MSI Address Hi. */
2405 {
2406 uint32_t const uReg = u64Value;
2407 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2408 }
2409
2410 /* MSI Data. */
2411 {
2412 uint32_t const uReg = u64Value >> 32;
2413 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2414 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2415 }
2416
2417 return VINF_SUCCESS;
2418}
2419
2420
2421/**
2422 * Writes the Command Buffer Head Pointer Register.
2423 */
2424static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2425{
2426 RT_NOREF(pDevIns, offReg);
2427
2428 /*
2429 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2430 * In our emulation, we ignore the write entirely.
2431 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2432 */
2433 if (pThis->Status.n.u1CmdBufRunning)
2434 {
2435 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2436 return VINF_SUCCESS;
2437 }
2438
2439 /*
2440 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2441 * In our emulation, we ignore the write entirely.
2442 */
2443 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2444 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2445 Assert(cbBuf <= _512K);
2446 if (offBuf >= cbBuf)
2447 {
2448 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2449 return VINF_SUCCESS;
2450 }
2451
2452 /* Update the register. */
2453 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2454
2455 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2456
2457 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2458 return VINF_SUCCESS;
2459}
2460
2461
2462/**
2463 * Writes the Command Buffer Tail Pointer Register.
2464 */
2465static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2466{
2467 RT_NOREF(pDevIns, offReg);
2468
2469 /*
2470 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2471 * In our emulation, we ignore the write entirely.
2472 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2473 */
2474 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2475 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2476 Assert(cbBuf <= _512K);
2477 if (offBuf >= cbBuf)
2478 {
2479 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2480 return VINF_SUCCESS;
2481 }
2482
2483 /*
2484 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2485 * head pointer after adding one or more commands to the buffer.
2486 *
2487 * However, we cannot enforce this strictly because it's legal for software to shrink the
2488 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2489 * at 0). Software might even make the queue empty by making head and tail equal which is
2490 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2491 * in the foot here. As long as we make sure the offset value is within the circular buffer
2492 * bounds (which we do by masking bits above) it should be sufficient.
2493 */
2494 pThis->CmdBufTailPtr.au32[0] = offBuf;
2495
2496 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2497
2498 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2499 return VINF_SUCCESS;
2500}
2501
2502
2503/**
2504 * Writes the Event Log Head Pointer Register.
2505 */
2506static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2507{
2508 RT_NOREF(pDevIns, offReg);
2509
2510 /*
2511 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2512 * In our emulation, we ignore the write entirely.
2513 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2514 */
2515 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2516 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2517 Assert(cbBuf <= _512K);
2518 if (offBuf >= cbBuf)
2519 {
2520 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2521 return VINF_SUCCESS;
2522 }
2523
2524 /* Update the register. */
2525 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2526
2527 Log4Func(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2528 return VINF_SUCCESS;
2529}
2530
2531
2532/**
2533 * Writes the Event Log Tail Pointer Register.
2534 */
2535static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2536{
2537 RT_NOREF(pDevIns, offReg);
2538 NOREF(pThis);
2539
2540 /*
2541 * IOMMU behavior is undefined when software writes this register when the event log is running.
2542 * In our emulation, we ignore the write entirely.
2543 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2544 */
2545 if (pThis->Status.n.u1EvtLogRunning)
2546 {
2547 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2548 return VINF_SUCCESS;
2549 }
2550
2551 /*
2552 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2553 * In our emulation, we ignore the write entirely.
2554 */
2555 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2556 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2557 Assert(cbBuf <= _512K);
2558 if (offBuf >= cbBuf)
2559 {
2560 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2561 return VINF_SUCCESS;
2562 }
2563
2564 /* Update the register. */
2565 pThis->EvtLogTailPtr.au32[0] = offBuf;
2566
2567 Log4Func(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2568 return VINF_SUCCESS;
2569}
2570
2571
2572/**
2573 * Writes the Status Register.
2574 */
2575static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2576{
2577 RT_NOREF(pDevIns, offReg);
2578
2579 /* Mask out all unrecognized bits. */
2580 u64Value &= IOMMU_STATUS_VALID_MASK;
2581
2582 /*
2583 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2584 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2585 */
2586 IOMMU_STATUS_T const OldStatus = pThis->Status;
2587 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2588 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2589 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2590
2591 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2592
2593 /* Update the register. */
2594 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2595 return VINF_SUCCESS;
2596}
2597
2598
2599/**
2600 * Register access table 0.
2601 * The MMIO offset of each entry must be a multiple of 8!
2602 */
2603static const IOMMUREGACC g_aRegAccess0[] =
2604{
2605 /* MMIO off. Register name Read function Write function */
2606 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2607 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2608 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2609 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2610 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2611 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2612 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2613 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2614 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2615 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2616 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2617 { /* 0x58 */ NULL, NULL, NULL },
2618
2619 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2620 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2621 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2622 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2623 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2624 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2625 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2626 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2627 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2628 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2629 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2630 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2631 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2632 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2633 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2634 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2635
2636 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2637 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2638 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2639 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2640
2641 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2642 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2643 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2644 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2645 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2646 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2647 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2648
2649 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2650 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2651 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2652
2653 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2654 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2655 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2656 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2657
2658 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2659 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2660 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2661};
2662AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2663
2664/**
2665 * Register access table 1.
2666 * The MMIO offset of each entry must be a multiple of 8!
2667 */
2668static const IOMMUREGACC g_aRegAccess1[] =
2669{
2670 /* MMIO offset Register name Read function Write function */
2671 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2672 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2673 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2674 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2675 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2676 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2677 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2678 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2679 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2680 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2681 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2682 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2683};
2684AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2685
2686/**
2687 * Register access table 2.
2688 * The MMIO offset of each entry must be a multiple of 8!
2689 */
2690static const IOMMUREGACC g_aRegAccess2[] =
2691{
2692 /* MMIO offset Register name Read Function Write function */
2693 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2694
2695 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2696 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2697 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2698 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2699
2700 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2701 { /* 0x2028 */ NULL, NULL, NULL },
2702
2703 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2704 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2705
2706 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2707 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2708
2709 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2710 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2711
2712 { /* 0x2060 */ NULL, NULL, NULL },
2713 { /* 0x2068 */ NULL, NULL, NULL },
2714
2715 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2716 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2717
2718 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2719 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2720 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2721};
2722AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2723
2724
2725/**
2726 * Gets the register access structure given its MMIO offset.
2727 *
2728 * @returns The register access structure, or NULL if the offset is invalid.
2729 * @param off The MMIO offset of the register being accessed.
2730 */
2731static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2732{
2733 /* Figure out which table the register belongs to and validate its index. */
2734 PCIOMMUREGACC pReg;
2735 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2736 {
2737 uint32_t const idxReg = off >> 3;
2738 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2739 pReg = &g_aRegAccess0[idxReg];
2740 }
2741 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2742 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2743 {
2744 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2745 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2746 pReg = &g_aRegAccess1[idxReg];
2747 }
2748 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2749 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2750 {
2751 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2752 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2753 pReg = &g_aRegAccess2[idxReg];
2754 }
2755 else
2756 pReg = NULL;
2757 return pReg;
2758}
2759
2760
2761/**
2762 * Writes an IOMMU register (32-bit and 64-bit).
2763 *
2764 * @returns Strict VBox status code.
2765 * @param pDevIns The IOMMU device instance.
2766 * @param off MMIO byte offset to the register.
2767 * @param cb The size of the write access.
2768 * @param uValue The value being written.
2769 *
2770 * @thread EMT.
2771 */
2772static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2773{
2774 /*
2775 * Validate the access in case of IOM bug or incorrect assumption.
2776 */
2777 Assert(off < IOMMU_MMIO_REGION_SIZE);
2778 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2779 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2780
2781 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2782
2783 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2784 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2785 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2786 if (pReg)
2787 { /* likely */ }
2788 else
2789 {
2790 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2791 return VINF_SUCCESS;
2792 }
2793
2794 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2795 if (pReg->pfnWrite)
2796 { /* likely */ }
2797 else
2798 {
2799 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2800 return VINF_SUCCESS;
2801 }
2802
2803 /*
2804 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2805 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2806 * consecutive 32-bit registers.
2807 */
2808 if (cb == 8)
2809 {
2810 if (!(off & 7))
2811 {
2812 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2813 VBOXSTRICTRC rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2814 IOMMU_UNLOCK(pDevIns, pThisCC);
2815 return rcStrict;
2816 }
2817
2818 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2819 return VINF_SUCCESS;
2820 }
2821
2822 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2823 Assert(cb == 4);
2824 if (!(off & 7))
2825 {
2826 VBOXSTRICTRC rcStrict;
2827 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2828
2829 /*
2830 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2831 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2832 */
2833 uint64_t u64Read;
2834 if (pReg->pfnRead)
2835 rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2836 else
2837 {
2838 rcStrict = VINF_SUCCESS;
2839 u64Read = 0;
2840 }
2841
2842 if (RT_SUCCESS(rcStrict))
2843 {
2844 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2845 rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2846 }
2847 else
2848 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2849
2850 IOMMU_UNLOCK(pDevIns, pThisCC);
2851 return rcStrict;
2852 }
2853
2854 /*
2855 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2856 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2857 */
2858 VBOXSTRICTRC rcStrict;
2859 Assert(!(off & 3));
2860 Assert(off & 7);
2861 Assert(off >= 4);
2862 uint64_t u64Read;
2863 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2864 if (pReg->pfnRead)
2865 rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2866 else
2867 {
2868 rcStrict = VINF_SUCCESS;
2869 u64Read = 0;
2870 }
2871
2872 if (RT_SUCCESS(rcStrict))
2873 {
2874 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2875 rcStrict = pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2876 }
2877 else
2878 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2879
2880 IOMMU_UNLOCK(pDevIns, pThisCC);
2881 return rcStrict;
2882}
2883
2884
2885/**
2886 * Reads an IOMMU register (64-bit) given its MMIO offset.
2887 *
2888 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2889 * boundary include the lower half of the subsequent register.
2890 *
2891 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2892 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2893 * software will only perform 32-bit reads on those 32-bit registers that are
2894 * aligned on 8-byte boundaries.
2895 *
2896 * @returns Strict VBox status code.
2897 * @param pDevIns The IOMMU device instance.
2898 * @param off The MMIO offset of the register in bytes.
2899 * @param puResult Where to store the value being read.
2900 *
2901 * @thread EMT.
2902 */
2903static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2904{
2905 Assert(off < IOMMU_MMIO_REGION_SIZE);
2906 Assert(!(off & 7) || !(off & 3));
2907
2908 Log4Func(("off=%#x\n", off));
2909
2910 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2911 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2912 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2913 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2914
2915 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2916 if (pReg)
2917 { /* likely */ }
2918 else
2919 {
2920 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2921 return VINF_IOM_MMIO_UNUSED_FF;
2922 }
2923
2924 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2925 if (pReg->pfnRead)
2926 { /* likely */ }
2927 else
2928 {
2929 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2930 return VINF_IOM_MMIO_UNUSED_00;
2931 }
2932
2933 /*
2934 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2935 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2936 */
2937 if (!(off & 7))
2938 {
2939 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2940 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, puResult);
2941 IOMMU_UNLOCK(pDevIns, pThisCC);
2942 return rcStrict;
2943 }
2944
2945 /*
2946 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2947 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2948 */
2949 Assert(!(off & 3));
2950 Assert(off & 7);
2951 Assert(off >= 4);
2952 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2953 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2954 IOMMU_UNLOCK(pDevIns, pThisCC);
2955 if (RT_SUCCESS(rcStrict))
2956 *puResult >>= 32;
2957 else
2958 {
2959 *puResult = 0;
2960 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2961 }
2962
2963 return rcStrict;
2964}
2965
2966
2967/**
2968 * Raises the MSI interrupt for the IOMMU device.
2969 *
2970 * @param pDevIns The IOMMU device instance.
2971 *
2972 * @thread Any.
2973 * @remarks The IOMMU lock may or may not be held.
2974 */
2975static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2976{
2977 LogFlowFunc(("\n"));
2978 if (iommuAmdIsMsiEnabled(pDevIns))
2979 {
2980 LogFunc(("Raising MSI\n"));
2981 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2982 }
2983}
2984
2985#if 0
2986/**
2987 * Clears the MSI interrupt for the IOMMU device.
2988 *
2989 * @param pDevIns The IOMMU device instance.
2990 *
2991 * @thread Any.
2992 * @remarks The IOMMU lock may or may not be held.
2993 */
2994static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2995{
2996 if (iommuAmdIsMsiEnabled(pDevIns))
2997 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2998}
2999#endif
3000
3001/**
3002 * Writes an entry to the event log in memory.
3003 *
3004 * @returns VBox status code.
3005 * @param pDevIns The IOMMU device instance.
3006 * @param pEvent The event to log.
3007 *
3008 * @thread Any.
3009 * @remarks The IOMMU lock must be held while calling this function.
3010 */
3011static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3012{
3013 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3014 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3015
3016 IOMMU_LOCK(pDevIns, pThisCC);
3017
3018 /* Check if event logging is active and the log has not overflowed. */
3019 IOMMU_STATUS_T const Status = pThis->Status;
3020 if ( Status.n.u1EvtLogRunning
3021 && !Status.n.u1EvtOverflow)
3022 {
3023 uint32_t const cbEvt = sizeof(*pEvent);
3024
3025 /* Get the offset we need to write the event to in memory (circular buffer offset). */
3026 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3027 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3028
3029 /* Ensure we have space in the event log. */
3030 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3031 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3032 if (cEvts + 1 < cMaxEvts)
3033 {
3034 /* Write the event log entry to memory. */
3035 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3036 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3037 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3038 if (RT_FAILURE(rc))
3039 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3040
3041 /* Increment the event log tail pointer. */
3042 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3043 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3044
3045 /* Indicate that an event log entry was written. */
3046 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3047
3048 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3049 if (pThis->Ctrl.n.u1EvtIntrEn)
3050 iommuAmdMsiInterruptRaise(pDevIns);
3051 }
3052 else
3053 {
3054 /* Indicate that the event log has overflowed. */
3055 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3056
3057 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3058 if (pThis->Ctrl.n.u1EvtIntrEn)
3059 iommuAmdMsiInterruptRaise(pDevIns);
3060 }
3061 }
3062
3063 IOMMU_UNLOCK(pDevIns, pThisCC);
3064
3065 return VINF_SUCCESS;
3066}
3067
3068
3069/**
3070 * Sets an event in the hardware error registers.
3071 *
3072 * @param pDevIns The IOMMU device instance.
3073 * @param pEvent The event.
3074 *
3075 * @thread Any.
3076 */
3077static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3078{
3079 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3080 if (pThis->ExtFeat.n.u1HwErrorSup)
3081 {
3082 if (pThis->HwEvtStatus.n.u1Valid)
3083 pThis->HwEvtStatus.n.u1Overflow = 1;
3084 pThis->HwEvtStatus.n.u1Valid = 1;
3085 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3086 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3087 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
3088 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
3089 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3090 }
3091}
3092
3093
3094/**
3095 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
3096 *
3097 * @param idDevice The device ID (bus, device, function).
3098 * @param idDomain The domain ID.
3099 * @param GCPhysPtEntity The system physical address of the page table
3100 * entity.
3101 * @param enmOp The IOMMU operation being performed.
3102 * @param pEvtPageTabHwErr Where to store the initialized event.
3103 */
3104static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3105 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3106{
3107 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3108 pEvtPageTabHwErr->n.u16DevId = idDevice;
3109 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3110 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3111 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3112 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3113 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3114 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3115 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3116 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3117}
3118
3119
3120/**
3121 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3122 *
3123 * @param pDevIns The IOMMU device instance.
3124 * @param enmOp The IOMMU operation being performed.
3125 * @param pEvtPageTabHwErr The page table hardware error event.
3126 *
3127 * @thread Any.
3128 */
3129static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3130{
3131 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3132 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3133
3134 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3135 IOMMU_LOCK(pDevIns, pThisCC);
3136
3137 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3138 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3139 if (enmOp != IOMMUOP_CMD)
3140 iommuAmdSetPciTargetAbort(pDevIns);
3141
3142 IOMMU_UNLOCK(pDevIns, pThisCC);
3143
3144 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3145 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3146 pEvtPageTabHwErr->n.u2Type));
3147}
3148
3149
3150#ifdef IN_RING3
3151/**
3152 * Initializes a COMMAND_HARDWARE_ERROR event.
3153 *
3154 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3155 * @param pEvtCmdHwErr Where to store the initialized event.
3156 */
3157static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3158{
3159 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3160 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3161 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3162 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3163}
3164
3165
3166/**
3167 * Raises a COMMAND_HARDWARE_ERROR event.
3168 *
3169 * @param pDevIns The IOMMU device instance.
3170 * @param pEvtCmdHwErr The command hardware error event.
3171 *
3172 * @thread Any.
3173 */
3174static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3175{
3176 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3177 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3178 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3179
3180 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3181 IOMMU_LOCK(pDevIns, pThisCC);
3182
3183 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3184 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3185 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3186
3187 IOMMU_UNLOCK(pDevIns, pThisCC);
3188
3189 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3190}
3191#endif /* IN_RING3 */
3192
3193
3194/**
3195 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3196 *
3197 * @param idDevice The device ID (bus, device, function).
3198 * @param GCPhysDte The system physical address of the failed device table
3199 * access.
3200 * @param enmOp The IOMMU operation being performed.
3201 * @param pEvtDevTabHwErr Where to store the initialized event.
3202 */
3203static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3204 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3205{
3206 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3207 pEvtDevTabHwErr->n.u16DevId = idDevice;
3208 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3209 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3210 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3211 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3212 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3213 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3214 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3215}
3216
3217
3218/**
3219 * Raises a DEV_TAB_HARDWARE_ERROR event.
3220 *
3221 * @param pDevIns The IOMMU device instance.
3222 * @param enmOp The IOMMU operation being performed.
3223 * @param pEvtDevTabHwErr The device table hardware error event.
3224 *
3225 * @thread Any.
3226 */
3227static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3228{
3229 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3230 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3231
3232 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3233 IOMMU_LOCK(pDevIns, pThisCC);
3234
3235 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3236 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3237 if (enmOp != IOMMUOP_CMD)
3238 iommuAmdSetPciTargetAbort(pDevIns);
3239
3240 IOMMU_UNLOCK(pDevIns, pThisCC);
3241
3242 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3243 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3244}
3245
3246
3247#ifdef IN_RING3
3248/**
3249 * Initializes an ILLEGAL_COMMAND_ERROR event.
3250 *
3251 * @param GCPhysCmd The system physical address of the failed command
3252 * access.
3253 * @param pEvtIllegalCmd Where to store the initialized event.
3254 */
3255static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3256{
3257 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3258 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3259 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3260 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3261}
3262
3263
3264/**
3265 * Raises an ILLEGAL_COMMAND_ERROR event.
3266 *
3267 * @param pDevIns The IOMMU device instance.
3268 * @param pEvtIllegalCmd The illegal command error event.
3269 */
3270static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3271{
3272 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3273 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3274 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3275
3276 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3277 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3278
3279 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3280}
3281#endif /* IN_RING3 */
3282
3283
3284/**
3285 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3286 *
3287 * @param idDevice The device ID (bus, device, function).
3288 * @param uIova The I/O virtual address.
3289 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3290 * event was caused by an invalid level encoding in the
3291 * DTE.
3292 * @param enmOp The IOMMU operation being performed.
3293 * @param pEvtIllegalDte Where to store the initialized event.
3294 */
3295static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3296 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3297{
3298 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3299 pEvtIllegalDte->n.u16DevId = idDevice;
3300 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3301 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3302 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3303 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3304 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3305 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3306 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3307 * IOMMU spec here but not for this field for I/O page fault event. */
3308 Assert(!(uIova & UINT64_C(0x3)));
3309}
3310
3311
3312/**
3313 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3314 *
3315 * @param pDevIns The IOMMU instance data.
3316 * @param enmOp The IOMMU operation being performed.
3317 * @param pEvtIllegalDte The illegal device table entry event.
3318 * @param enmEvtType The illegal device table entry event type.
3319 *
3320 * @thread Any.
3321 */
3322static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3323 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3324{
3325 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3326 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3327
3328 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3329 if (enmOp != IOMMUOP_CMD)
3330 iommuAmdSetPciTargetAbort(pDevIns);
3331
3332 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3333 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3334 NOREF(enmEvtType);
3335}
3336
3337
3338/**
3339 * Initializes an IO_PAGE_FAULT event.
3340 *
3341 * @param idDevice The device ID (bus, device, function).
3342 * @param idDomain The domain ID.
3343 * @param uIova The I/O virtual address being accessed.
3344 * @param fPresent Transaction to a page marked as present (including
3345 * DTE.V=1) or interrupt marked as remapped
3346 * (IRTE.RemapEn=1).
3347 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3348 * the I/O page fault was caused by invalid level
3349 * encoding.
3350 * @param fPermDenied Permission denied for the address being accessed.
3351 * @param enmOp The IOMMU operation being performed.
3352 * @param pEvtIoPageFault Where to store the initialized event.
3353 */
3354static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3355 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3356{
3357 Assert(!fPermDenied || fPresent);
3358 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3359 pEvtIoPageFault->n.u16DevId = idDevice;
3360 //pEvtIoPageFault->n.u4PasidHi = 0;
3361 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3362 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3363 //pEvtIoPageFault->n.u1NoExecute = 0;
3364 //pEvtIoPageFault->n.u1User = 0;
3365 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3366 pEvtIoPageFault->n.u1Present = fPresent;
3367 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3368 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3369 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3370 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3371 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3372 pEvtIoPageFault->n.u64Addr = uIova;
3373}
3374
3375
3376/**
3377 * Raises an IO_PAGE_FAULT event.
3378 *
3379 * @param pDevIns The IOMMU instance data.
3380 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3381 * @param pIrte The interrupt remapping table entry, can be NULL.
3382 * @param enmOp The IOMMU operation being performed.
3383 * @param pEvtIoPageFault The I/O page fault event.
3384 * @param enmEvtType The I/O page fault event type.
3385 *
3386 * @thread Any.
3387 */
3388static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3389 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3390{
3391 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3392 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3393 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3394 STAM_COUNTER_INC(&pThis->StatIopfs); NOREF(pThis);
3395
3396#ifdef IOMMU_WITH_DTE_CACHE
3397# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheUpdateFlags((a_pDevIns), (a_DevId), \
3398 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED, \
3399 0 /* fAndMask */)
3400#else
3401# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3402#endif
3403
3404 bool fSuppressEvtLogging = false;
3405 if ( enmOp == IOMMUOP_MEM_READ
3406 || enmOp == IOMMUOP_MEM_WRITE)
3407 {
3408 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3409 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3410 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3411 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3412 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3413 {
3414 fSuppressEvtLogging = true;
3415 }
3416 }
3417 else if (enmOp == IOMMUOP_INTR_REQ)
3418 {
3419 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3420 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3421 fSuppressEvtLogging = true;
3422 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3423 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3424 }
3425 /* else: Events are never suppressed for commands. */
3426
3427 switch (enmEvtType)
3428 {
3429 case kIoPageFaultType_PermDenied:
3430 {
3431 /* Cannot be triggered by a command. */
3432 Assert(enmOp != IOMMUOP_CMD);
3433 RT_FALL_THRU();
3434 }
3435 case kIoPageFaultType_DteRsvdPagingMode:
3436 case kIoPageFaultType_PteInvalidPageSize:
3437 case kIoPageFaultType_PteInvalidLvlEncoding:
3438 case kIoPageFaultType_SkippedLevelIovaNotZero:
3439 case kIoPageFaultType_PteRsvdNotZero:
3440 case kIoPageFaultType_PteValidNotSet:
3441 case kIoPageFaultType_DteTranslationDisabled:
3442 case kIoPageFaultType_PasidInvalidRange:
3443 {
3444 /*
3445 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3446 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3447 */
3448 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3449 {
3450 if (!fSuppressEvtLogging)
3451 {
3452 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3453 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3454 }
3455 if (enmOp != IOMMUOP_CMD)
3456 iommuAmdSetPciTargetAbort(pDevIns);
3457 }
3458 break;
3459 }
3460
3461 case kIoPageFaultType_UserSupervisor:
3462 {
3463 /* Access is blocked and only creates an event log entry. */
3464 if (!fSuppressEvtLogging)
3465 {
3466 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3467 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3468 }
3469 break;
3470 }
3471
3472 case kIoPageFaultType_IrteAddrInvalid:
3473 case kIoPageFaultType_IrteRsvdNotZero:
3474 case kIoPageFaultType_IrteRemapEn:
3475 case kIoPageFaultType_IrteRsvdIntType:
3476 case kIoPageFaultType_IntrReqAborted:
3477 case kIoPageFaultType_IntrWithPasid:
3478 {
3479 /* Only trigerred by interrupt requests. */
3480 Assert(enmOp == IOMMUOP_INTR_REQ);
3481 if (!fSuppressEvtLogging)
3482 {
3483 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3484 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3485 }
3486 iommuAmdSetPciTargetAbort(pDevIns);
3487 break;
3488 }
3489
3490 case kIoPageFaultType_SmiFilterMismatch:
3491 {
3492 /* Not supported and probably will never be, assert. */
3493 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3494 break;
3495 }
3496
3497 case kIoPageFaultType_DevId_Invalid:
3498 {
3499 /* Cannot be triggered by a command. */
3500 Assert(enmOp != IOMMUOP_CMD);
3501 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3502 if (!fSuppressEvtLogging)
3503 {
3504 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3505 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3506 }
3507 if ( enmOp == IOMMUOP_MEM_READ
3508 || enmOp == IOMMUOP_MEM_WRITE)
3509 iommuAmdSetPciTargetAbort(pDevIns);
3510 break;
3511 }
3512 }
3513
3514#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3515}
3516
3517
3518/**
3519 * Raises an IO_PAGE_FAULT event given the DTE.
3520 *
3521 * @param pDevIns The IOMMU instance data.
3522 * @param pDte The device table entry.
3523 * @param pIrte The interrupt remapping table entry, can be NULL.
3524 * @param enmOp The IOMMU operation being performed.
3525 * @param pEvtIoPageFault The I/O page fault event.
3526 * @param enmEvtType The I/O page fault event type.
3527 *
3528 * @thread Any.
3529 */
3530static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3531 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3532{
3533 Assert(pDte);
3534 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3535 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3536}
3537
3538
3539/**
3540 * Reads a device table entry for the given the device ID.
3541 *
3542 * @returns VBox status code.
3543 * @param pDevIns The IOMMU device instance.
3544 * @param idDevice The device ID (bus, device, function).
3545 * @param enmOp The IOMMU operation being performed.
3546 * @param pDte Where to store the device table entry.
3547 *
3548 * @thread Any.
3549 */
3550static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3551{
3552 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3553 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3554
3555 IOMMU_LOCK(pDevIns, pThisCC);
3556
3557 /* Figure out which device table segment is being accessed. */
3558 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3559 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3560
3561 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3562 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3563 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3564
3565 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3566 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3567 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3568
3569 /* Ensure the DTE falls completely within the device table segment. */
3570 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3571
3572 IOMMU_UNLOCK(pDevIns, pThisCC);
3573
3574 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3575 {
3576 /* Read the device table entry from guest memory. */
3577 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3578 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3579 if (RT_SUCCESS(rc))
3580 return VINF_SUCCESS;
3581
3582 /* Raise a device table hardware error. */
3583 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3584
3585 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3586 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3587 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3588 return VERR_IOMMU_DTE_READ_FAILED;
3589 }
3590
3591 /* Raise an I/O page fault for out-of-bounds acccess. */
3592 LogFunc(("Out-of-bounds device table entry. idDevice=%#x offDte=%u cbDevTabSeg=%u -> IOPF\n", idDevice, offDte, cbDevTabSeg));
3593 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3594 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3595 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3596 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3597 kIoPageFaultType_DevId_Invalid);
3598 return VERR_IOMMU_DTE_BAD_OFFSET;
3599}
3600
3601
3602/**
3603 * Performs pre-translation checks for the given device table entry.
3604 *
3605 * @returns VBox status code.
3606 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3607 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3608 * translation is disabled.
3609 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3610 * corresponding event was raised.
3611 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3612 * permissions.
3613 *
3614 * @param pDevIns The IOMMU device instance.
3615 * @param uIova The I/O virtual address to translate.
3616 * @param idDevice The device ID (bus, device, function).
3617 * @param fPerm The I/O permissions for this access, see
3618 * IOMMU_IO_PERM_XXX.
3619 * @param pDte The device table entry.
3620 * @param enmOp The IOMMU operation being performed.
3621 *
3622 * @thread Any.
3623 */
3624static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3625 IOMMUOP enmOp)
3626{
3627 /*
3628 * Check if the translation is valid, otherwise raise an I/O page fault.
3629 */
3630 if (pDte->n.u1TranslationValid)
3631 { /* likely */ }
3632 else
3633 {
3634 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3635 * doesn't explicitly say whether an I/O page fault is raised. From other
3636 * places in the spec. it seems early page walk terminations (starting with
3637 * the DTE) return the state computed so far and raises an I/O page fault. So
3638 * returning an invalid translation rather than skipping translation. */
3639 LogFunc(("Translation valid bit not set -> IOPF\n"));
3640 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3641 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3642 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3643 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3644 kIoPageFaultType_DteTranslationDisabled);
3645 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3646 }
3647
3648 /*
3649 * Check permissions bits in the DTE.
3650 * Note: This MUST be checked prior to checking the root page table level below!
3651 */
3652 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3653 if ((fPerm & fDtePerm) == fPerm)
3654 { /* likely */ }
3655 else
3656 {
3657 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3658 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3659 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3660 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3661 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3662 kIoPageFaultType_PermDenied);
3663 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3664 }
3665
3666 /*
3667 * If the root page table level is 0, translation is disabled and GPA=SPA and
3668 * the DTE.IR and DTE.IW bits control permissions (verified above).
3669 */
3670 uint8_t const uMaxLevel = pDte->n.u3Mode;
3671 if (uMaxLevel != 0)
3672 { /* likely */ }
3673 else
3674 {
3675 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3676 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3677 }
3678
3679 /*
3680 * If the root page table level exceeds the allowed host-address translation level,
3681 * page walk is terminated and translation fails.
3682 */
3683 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3684 { /* likely */ }
3685 else
3686 {
3687 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3688 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3689 * I'm just going with I/O page fault. */
3690 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3691 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3692 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3693 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3694 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3695 kIoPageFaultType_PteInvalidLvlEncoding);
3696 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3697 }
3698
3699 /* The DTE allows translations for this device. */
3700 return VINF_SUCCESS;
3701}
3702
3703
3704/**
3705 * Walks the I/O page table to translate the I/O virtual address to a system
3706 * physical address.
3707 *
3708 * @returns VBox status code.
3709 * @param pDevIns The IOMMU device instance.
3710 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3711 * @param fPerm The I/O permissions for this access, see
3712 * IOMMU_IO_PERM_XXX.
3713 * @param idDevice The device ID (bus, device, function).
3714 * @param pDte The device table entry.
3715 * @param enmOp The IOMMU operation being performed.
3716 * @param pPageLookup Where to store the results of the I/O page lookup. This
3717 * is only updated when VINF_SUCCESS is returned.
3718 *
3719 * @thread Any.
3720 */
3721static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3722 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3723{
3724 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3725 Assert(pDte->n.u1Valid);
3726 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3727
3728 /* The virtual address bits indexing table. */
3729 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3730 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3731
3732 /*
3733 * Traverse the I/O page table starting with the page directory in the DTE.
3734 *
3735 * The Valid (Present bit), Translation Valid and Mode (Next-Level bits) in
3736 * the DTE have been validated already, see iommuAmdPreTranslateChecks.
3737 */
3738 IOPTENTITY_T PtEntity;
3739 PtEntity.u64 = pDte->au64[0];
3740 for (;;)
3741 {
3742 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3743
3744 /* Read the page table entity at the current level. */
3745 {
3746 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3747 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3748 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3749 uint64_t const offPte = idxPte << 3;
3750 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3751 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3752 if (RT_FAILURE(rc))
3753 {
3754 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3755 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3756 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3757 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3758 return VERR_IOMMU_IPE_2;
3759 }
3760 }
3761
3762 /* Check present bit. */
3763 if (PtEntity.n.u1Present)
3764 { /* likely */ }
3765 else
3766 {
3767 LogFunc(("Page table entry not present. idDevice=%#x uIova=%#RX64 -> IOPF\n", idDevice, uIova));
3768 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3769 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3770 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3771 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3772 kIoPageFaultType_PermDenied);
3773 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3774 }
3775
3776 /* Validate the encoding of the next level. */
3777 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3778#if IOMMU_MAX_HOST_PT_LEVEL < 6
3779 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3780 { /* likely */ }
3781 else
3782 {
3783 LogFunc(("Next-level/paging-mode field of the paging entity invalid. uNextLevel=%#x -> IOPF\n", uNextLevel));
3784 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3785 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, true /* fRsvdNotZero */,
3786 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3787 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3788 kIoPageFaultType_PteInvalidLvlEncoding);
3789 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3790 }
3791#endif
3792
3793 /* Check reserved bits. */
3794 uint64_t const fRsvdMask = uNextLevel == 0 || uNextLevel == 7 ? IOMMU_PTE_RSVD_MASK : IOMMU_PDE_RSVD_MASK;
3795 if (!(PtEntity.u64 & fRsvdMask))
3796 { /* likely */ }
3797 else
3798 {
3799 LogFunc(("Page table entity (%#RX64 level=%u) reserved bits set -> IOPF\n", PtEntity.u64, uNextLevel));
3800 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3801 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, true /* fRsvdNotZero */,
3802 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3803 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3804 kIoPageFaultType_PteRsvdNotZero);
3805 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3806 }
3807
3808 /* Check permission bits. */
3809 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3810 if ((fPerm & fPtePerm) == fPerm)
3811 { /* likely */ }
3812 else
3813 {
3814 LogFunc(("Page table entry access denied. idDevice=%#x fPerm=%#x fPtePerm=%#x -> IOPF\n", idDevice, fPerm, fPtePerm));
3815 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3816 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3817 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3818 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3819 kIoPageFaultType_PermDenied);
3820 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3821 }
3822
3823 /* If the next level is 0 or 7, this is the final level PTE. */
3824 if (uNextLevel == 0)
3825 {
3826 /* The page size of the translation is the default size for the level. */
3827 uint8_t const cShift = s_acIovaLevelShifts[uLevel];
3828 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3829 pPageLookup->GCPhysSpa = GCPhysPte & X86_GET_PAGE_BASE_MASK(cShift);
3830 pPageLookup->cShift = cShift;
3831 pPageLookup->fPerm = fPtePerm;
3832 return VINF_SUCCESS;
3833 }
3834 if (uNextLevel == 7)
3835 {
3836 /* The default page size of the translation is overridden. */
3837 uint8_t cShift = X86_PAGE_4K_SHIFT;
3838 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3839 while (GCPhysPte & RT_BIT_64(cShift++))
3840 ;
3841
3842 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3843 if ( cShift > s_acIovaLevelShifts[uLevel]
3844 && cShift < s_acIovaLevelShifts[uLevel + 1])
3845 {
3846 pPageLookup->GCPhysSpa = GCPhysPte & X86_GET_PAGE_BASE_MASK(cShift);
3847 pPageLookup->cShift = cShift;
3848 pPageLookup->fPerm = fPtePerm;
3849 STAM_COUNTER_INC(&pThis->StatNonStdPageSize); NOREF(pThis);
3850 return VINF_SUCCESS;
3851 }
3852
3853 LogFunc(("Page size invalid. idDevice=%#x cShift=%u -> IOPF\n", idDevice, cShift));
3854 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3855 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3856 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3857 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3858 kIoPageFaultType_PteInvalidPageSize);
3859 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3860 }
3861
3862 /* Validate level transition. */
3863 if (uNextLevel < uLevel)
3864 { /* likely */ }
3865 else
3866 {
3867 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3868 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3869 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3870 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3871 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3872 kIoPageFaultType_PteInvalidLvlEncoding);
3873 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3874 }
3875
3876 /* Ensure IOVA bits of skipped levels (if any) are zero. */
3877 uint64_t const fIovaSkipMask = IOMMU_GET_MAX_VALID_IOVA(uLevel - 1) - IOMMU_GET_MAX_VALID_IOVA(uNextLevel);
3878 if (!(uIova & fIovaSkipMask))
3879 { /* likely */ }
3880 else
3881 {
3882 LogFunc(("IOVA of skipped levels are not zero. uIova=%#RX64 fSkipMask=%#RX64 -> IOPF\n", uIova, fIovaSkipMask));
3883 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3884 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3885 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3886 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3887 kIoPageFaultType_SkippedLevelIovaNotZero);
3888 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3889 }
3890
3891 /* Traverse to the next level. */
3892 }
3893}
3894
3895
3896/**
3897 * Page lookup callback for finding an I/O page from guest memory.
3898 *
3899 * @returns VBox status code.
3900 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3901 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3902 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3903 * insufficient to what is requested.
3904 *
3905 * @param pDevIns The IOMMU instance data.
3906 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3907 * 4K aligned).
3908 * @param fPerm The I/O permissions for this access, see
3909 * IOMMU_IO_PERM_XXX.
3910 * @param pAux The auxiliary information required during lookup.
3911 * @param pPageLookup Where to store the looked up I/O page.
3912 */
3913static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3914 PIOPAGELOOKUP pPageLookup)
3915{
3916 AssertPtr(pAux);
3917 AssertPtr(pPageLookup);
3918 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3919
3920 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3921 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3922 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3923 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3924 return rc;
3925}
3926
3927
3928/**
3929 * Looks up a range of I/O virtual addresses.
3930 *
3931 * @returns VBox status code.
3932 * @param pDevIns The IOMMU instance data.
3933 * @param pfnIoPageLookup The lookup function to use.
3934 * @param pAddrIn The I/O address range to lookup.
3935 * @param pAux The auxiliary information required by the lookup
3936 * function.
3937 * @param pAddrOut Where to store the translated I/O address page
3938 * lookup.
3939 * @param pcbContiguous Where to store the size of the access.
3940 */
3941static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3942 PCIOMMUOPAUX pAux, PIOPAGELOOKUP pAddrOut, size_t *pcbContiguous)
3943{
3944 int rc;
3945 size_t const cbIova = pAddrIn->cb;
3946 uint8_t const fPerm = pAddrIn->fPerm;
3947 uint64_t const uIova = pAddrIn->uAddr;
3948 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3949 size_t cbRemaining = cbIova;
3950 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3951 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3952 size_t const cbPage = X86_PAGE_4K_SIZE;
3953
3954 IOPAGELOOKUP PageLookupPrev;
3955 RT_ZERO(PageLookupPrev);
3956 for (;;)
3957 {
3958 /* Lookup the physical page corresponding to the I/O virtual address. */
3959 IOPAGELOOKUP PageLookup;
3960 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3961 if (RT_SUCCESS(rc))
3962 {
3963 /*
3964 * Validate results of the translation.
3965 */
3966 /* The IOTLB cache preserves the original page sizes even though the IOVAs are split into 4K pages. */
3967 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT && PageLookup.cShift <= 51);
3968 Assert( pfnIoPageLookup != iommuAmdDteLookupPage
3969 || !(PageLookup.GCPhysSpa & X86_GET_PAGE_OFFSET_MASK(PageLookup.cShift)));
3970 Assert((PageLookup.fPerm & fPerm) == fPerm);
3971
3972 /* Store the translated address before continuing to access more pages. */
3973 if (cbRemaining == cbIova)
3974 {
3975 uint64_t const offSpa = uIova & X86_GET_PAGE_OFFSET_MASK(PageLookup.cShift);
3976 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3977 }
3978 /*
3979 * Check if translated address results in a physically contiguous region.
3980 *
3981 * Also ensure that the permissions for all pages in this range are identical
3982 * because we specify a common permission while adding pages in this range
3983 * to the IOTLB cache.
3984 *
3985 * The page size must also be identical since we need to know how many offset
3986 * bits to copy into the final translated address (while retrieving 4K sized
3987 * pages from the IOTLB cache).
3988 */
3989 else if ( PageLookup.GCPhysSpa == PageLookupPrev.GCPhysSpa + cbPage
3990 && PageLookup.fPerm == PageLookupPrev.fPerm
3991 && PageLookup.cShift == PageLookupPrev.cShift)
3992 { /* likely */ }
3993 else
3994 {
3995 Assert(cbRemaining > 0);
3996 rc = VERR_OUT_OF_RANGE;
3997 break;
3998 }
3999
4000 /* Store the page lookup result from the first/previous page. */
4001 PageLookupPrev = PageLookup;
4002
4003 /* Check if we need to access more pages. */
4004 if (cbRemaining > cbPage - offIova)
4005 {
4006 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
4007 uIovaPage += cbPage; /* Update address of the next access. */
4008 offIova = 0; /* After the first page, remaining pages are accessed from offset 0. */
4009 }
4010 else
4011 {
4012 /* Caller (PDM) doesn't expect more data accessed than what was requested. */
4013 cbRemaining = 0;
4014 break;
4015 }
4016 }
4017 else
4018 break;
4019 }
4020
4021 pAddrOut->GCPhysSpa = GCPhysSpa; /* Update the translated address. */
4022 pAddrOut->cShift = PageLookupPrev.cShift; /* Update the page size of the lookup. */
4023 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
4024 *pcbContiguous = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
4025 return rc;
4026}
4027
4028
4029/**
4030 * Looks up an I/O virtual address from the device table.
4031 *
4032 * @returns VBox status code.
4033 * @param pDevIns The IOMMU instance data.
4034 * @param idDevice The device ID (bus, device, function).
4035 * @param uIova The I/O virtual address to lookup.
4036 * @param cbIova The size of the access.
4037 * @param fPerm The I/O permissions for this access, see
4038 * IOMMU_IO_PERM_XXX.
4039 * @param enmOp The IOMMU operation being performed.
4040 * @param pGCPhysSpa Where to store the translated system physical address.
4041 * @param pcbContiguous Where to store the number of contiguous bytes translated
4042 * and permission-checked.
4043 *
4044 * @thread Any.
4045 */
4046static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
4047 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4048{
4049 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4050 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
4051 size_t cbContiguous = 0;
4052
4053 /* Read the device table entry from memory. */
4054 DTE_T Dte;
4055 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4056 if (RT_SUCCESS(rc))
4057 {
4058 if (Dte.n.u1Valid)
4059 {
4060 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4061 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4062 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4063 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4064 {
4065 /*
4066 * Check if the DTE is configured for translating addresses.
4067 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
4068 * so there's no need to check the address exclusion base/limit here.
4069 */
4070 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
4071 if (rc == VINF_SUCCESS)
4072 {
4073 IOADDRRANGE AddrIn;
4074 AddrIn.uAddr = uIova;
4075 AddrIn.cb = cbIova;
4076 AddrIn.fPerm = fPerm;
4077
4078 IOMMUOPAUX Aux;
4079 Aux.enmOp = enmOp;
4080 Aux.pDte = &Dte;
4081 Aux.idDevice = idDevice;
4082 Aux.idDomain = Dte.n.u16DomainId;
4083
4084 /* Lookup the address from the DTE and I/O page tables.*/
4085 IOPAGELOOKUP AddrOut;
4086 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbContiguous);
4087 GCPhysSpa = AddrOut.GCPhysSpa;
4088
4089 /*
4090 * If we stopped since translation resulted in non-contiguous physical addresses
4091 * or permissions aren't identical for all pages in the access, what we translated
4092 * thus far is still valid.
4093 */
4094 if (rc == VERR_OUT_OF_RANGE)
4095 {
4096 Assert(cbContiguous > 0 && cbContiguous < cbIova);
4097 rc = VINF_SUCCESS;
4098 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
4099 }
4100 else if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
4101 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4102
4103#ifdef IOMMU_WITH_IOTLBE_CACHE
4104 if (RT_SUCCESS(rc))
4105 {
4106 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
4107 iommuAmdDteCacheAddOrUpdateFlags(pDevIns, &Dte, idDevice, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE,
4108 0 /* fAndMask */);
4109 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
4110 iommuAmdIotlbAddRange(pDevIns, Aux.idDomain, uIova & X86_PAGE_4K_BASE_MASK, cbContiguous, &AddrOut);
4111 }
4112#endif
4113 }
4114 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
4115 {
4116 /*
4117 * Translation is disabled for this device (root paging mode is 0).
4118 * GPA=SPA, but the permission bits are important and controls accesses.
4119 */
4120 GCPhysSpa = uIova;
4121 cbContiguous = cbIova;
4122 rc = VINF_SUCCESS;
4123
4124#ifdef IOMMU_WITH_IOTLBE_CACHE
4125 /* Update that addresses permissions of DTE apply (but omit address translation). */
4126 iommuAmdDteCacheAddOrUpdateFlags(pDevIns, &Dte, idDevice, IOMMU_DTE_CACHE_F_IO_PERM,
4127 IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
4128#endif
4129 }
4130 else
4131 {
4132 /* Address translation failed or access is denied. */
4133 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4134 GCPhysSpa = NIL_RTGCPHYS;
4135 cbContiguous = 0;
4136 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4137 }
4138 }
4139 else
4140 {
4141 /* Invalid reserved bits in the DTE, raise an error event. */
4142 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4143 EVT_ILLEGAL_DTE_T Event;
4144 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4145 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4146 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4147 }
4148 }
4149 else
4150 {
4151 /*
4152 * The DTE is not valid, forward addresses untranslated.
4153 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4154 */
4155 GCPhysSpa = uIova;
4156 cbContiguous = cbIova;
4157 }
4158 }
4159 else
4160 {
4161 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4162 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4163 }
4164
4165 *pGCPhysSpa = GCPhysSpa;
4166 *pcbContiguous = cbContiguous;
4167 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4168 return rc;
4169}
4170
4171
4172#ifdef IOMMU_WITH_IOTLBE_CACHE
4173/**
4174 * I/O page lookup callback for finding an I/O page from the IOTLB.
4175 *
4176 * @returns VBox status code.
4177 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4178 * @retval VERR_NOT_FOUND when the page is not found.
4179 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4180 * insufficient to what is requested.
4181 *
4182 * @param pDevIns The IOMMU instance data.
4183 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4184 * 4K aligned).
4185 * @param fPerm The I/O permissions for this access, see
4186 * IOMMU_IO_PERM_XXX.
4187 * @param pAux The auxiliary information required during lookup.
4188 * @param pPageLookup Where to store the looked up I/O page.
4189 */
4190static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4191 PIOPAGELOOKUP pPageLookup)
4192{
4193 Assert(pAux);
4194 Assert(pPageLookup);
4195 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4196
4197 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4198 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4199
4200 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4201 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4202 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4203 if (pIotlbe)
4204 {
4205 *pPageLookup = pIotlbe->PageLookup;
4206 if ((pPageLookup->fPerm & fPerm) == fPerm)
4207 {
4208 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4209 return VINF_SUCCESS;
4210 }
4211 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4212 }
4213 return VERR_NOT_FOUND;
4214}
4215
4216
4217/**
4218 * Lookups a memory access from the IOTLB cache.
4219 *
4220 * @returns VBox status code.
4221 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4222 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4223 * address region.
4224 * @retval VERR_NOT_FOUND if the access was not cached.
4225 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4226 * are insufficient.
4227 *
4228 * @param pDevIns The IOMMU instance data.
4229 * @param idDevice The device ID (bus, device, function).
4230 * @param uIova The I/O virtual address to lookup.
4231 * @param cbIova The size of the access.
4232 * @param fPerm The I/O permissions for this access, see
4233 * IOMMU_IO_PERM_XXX.
4234 * @param enmOp The IOMMU operation being performed.
4235 * @param pGCPhysSpa Where to store the translated system physical address.
4236 * @param pcbContiguous Where to store the number of contiguous bytes translated
4237 * and permission-checked.
4238 */
4239static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4240 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4241{
4242 int rc;
4243 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4244
4245#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4246 do { \
4247 *pGCPhysSpa = NIL_RTGCPHYS; \
4248 *pcbContiguous = 0; \
4249 rc = (a_rc); \
4250 } while (0)
4251
4252 /*
4253 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4254 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4255 */
4256 IOMMU_CACHE_LOCK(pDevIns, pThis);
4257
4258 /* Lookup the DTE cache entry. */
4259 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4260 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4261 {
4262 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4263 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4264 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4265 {
4266 /* Lookup IOTLB entries. */
4267 IOADDRRANGE AddrIn;
4268 AddrIn.uAddr = uIova;
4269 AddrIn.cb = cbIova;
4270 AddrIn.fPerm = fPerm;
4271
4272 IOMMUOPAUX Aux;
4273 Aux.enmOp = enmOp;
4274 Aux.pDte = NULL;
4275 Aux.idDevice = idDevice;
4276 Aux.idDomain = pDteCache->idDomain;
4277
4278 IOPAGELOOKUP AddrOut;
4279 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, pcbContiguous);
4280 *pGCPhysSpa = AddrOut.GCPhysSpa;
4281 Assert(*pcbContiguous <= cbIova);
4282 }
4283 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4284 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4285 {
4286 /* Address translation is disabled, but DTE permissions apply. */
4287 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4288 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4289 if ((fDtePerm & fPerm) == fPerm)
4290 {
4291 *pGCPhysSpa = uIova;
4292 *pcbContiguous = cbIova;
4293 rc = VINF_SUCCESS;
4294 }
4295 else
4296 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4297 }
4298 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4299 {
4300 /* Forward addresses untranslated, without checking permissions. */
4301 *pGCPhysSpa = uIova;
4302 *pcbContiguous = cbIova;
4303 rc = VINF_SUCCESS;
4304 }
4305 else
4306 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4307 }
4308 else
4309 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4310
4311 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
4312
4313 return rc;
4314
4315#undef IOMMU_IOTLB_LOOKUP_FAILED
4316}
4317#endif /* IOMMU_WITH_IOTLBE_CACHE */
4318
4319
4320/**
4321 * Gets the I/O permission and IOMMU operation type for the given access flags.
4322 *
4323 * @param pThis The shared IOMMU device state.
4324 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4325 * @param penmOp Where to store the IOMMU operation.
4326 * @param pfPerm Where to store the IOMMU I/O permission.
4327 * @param fBulk Whether this is a bulk read or write.
4328 */
4329DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4330{
4331 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4332 {
4333 *penmOp = IOMMUOP_MEM_WRITE;
4334 *pfPerm = IOMMU_IO_PERM_WRITE;
4335#ifdef VBOX_WITH_STATISTICS
4336 if (!fBulk)
4337 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4338 else
4339 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4340#else
4341 RT_NOREF2(pThis, fBulk);
4342#endif
4343 }
4344 else
4345 {
4346 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4347 *penmOp = IOMMUOP_MEM_READ;
4348 *pfPerm = IOMMU_IO_PERM_READ;
4349#ifdef VBOX_WITH_STATISTICS
4350 if (!fBulk)
4351 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4352 else
4353 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4354#else
4355 RT_NOREF2(pThis, fBulk);
4356#endif
4357 }
4358}
4359
4360
4361/**
4362 * Memory access transaction from a device.
4363 *
4364 * @returns VBox status code.
4365 * @param pDevIns The IOMMU device instance.
4366 * @param idDevice The device ID (bus, device, function).
4367 * @param uIova The I/O virtual address being accessed.
4368 * @param cbIova The size of the access.
4369 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4370 * @param pGCPhysSpa Where to store the translated system physical address.
4371 * @param pcbContiguous Where to store the number of contiguous bytes translated
4372 * and permission-checked.
4373 *
4374 * @thread Any.
4375 */
4376static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4377 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4378{
4379 /* Validate. */
4380 AssertPtr(pDevIns);
4381 AssertPtr(pGCPhysSpa);
4382 Assert(cbIova > 0);
4383 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4384
4385 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4386 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4387 if (Ctrl.n.u1IommuEn)
4388 {
4389 IOMMUOP enmOp;
4390 uint8_t fPerm;
4391 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4392 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4393
4394 int rc;
4395#ifdef IOMMU_WITH_IOTLBE_CACHE
4396 /* Lookup the IOVA from the cache. */
4397 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4398 if (rc == VINF_SUCCESS)
4399 {
4400 /* All pages in the access were found in the cache with sufficient permissions. */
4401 Assert(*pcbContiguous == cbIova);
4402 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4403 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4404 return VINF_SUCCESS;
4405 }
4406 if (rc != VERR_OUT_OF_RANGE)
4407 { /* likely */ }
4408 else
4409 {
4410 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4411 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4412 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4413 return VINF_SUCCESS;
4414 }
4415
4416 /*
4417 * Access incomplete as not all pages were in the cache.
4418 * Or permissions were denied for the access (which typically doesn't happen)
4419 * so go through the slower path and raise the required event.
4420 */
4421 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4422 uIova += *pcbContiguous;
4423 cbIova -= *pcbContiguous;
4424 /* We currently are including any permission denied pages as cache misses too.*/
4425 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4426#endif
4427
4428 /* Lookup the IOVA from the device table. */
4429 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4430 if (RT_SUCCESS(rc))
4431 { /* likely */ }
4432 else
4433 {
4434 Assert(rc != VERR_OUT_OF_RANGE);
4435 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4436 cbIova, rc));
4437 }
4438
4439 return rc;
4440 }
4441
4442 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4443 *pGCPhysSpa = uIova;
4444 *pcbContiguous = cbIova;
4445 return VINF_SUCCESS;
4446}
4447
4448
4449/**
4450 * Memory access bulk (one or more 4K pages) request from a device.
4451 *
4452 * @returns VBox status code.
4453 * @param pDevIns The IOMMU device instance.
4454 * @param idDevice The device ID (bus, device, function).
4455 * @param cIovas The number of addresses being accessed.
4456 * @param pauIovas The I/O virtual addresses for each page being accessed.
4457 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4458 * @param paGCPhysSpa Where to store the translated physical addresses.
4459 *
4460 * @thread Any.
4461 */
4462static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4463 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4464{
4465 /* Validate. */
4466 AssertPtr(pDevIns);
4467 Assert(cIovas > 0);
4468 AssertPtr(pauIovas);
4469 AssertPtr(paGCPhysSpa);
4470 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4471
4472 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4473 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4474 if (Ctrl.n.u1IommuEn)
4475 {
4476 IOMMUOP enmOp;
4477 uint8_t fPerm;
4478 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4479 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4480
4481 for (size_t i = 0; i < cIovas; i++)
4482 {
4483 int rc;
4484 size_t cbContig;
4485
4486#ifdef IOMMU_WITH_IOTLBE_CACHE
4487 /* Lookup the IOVA from the IOTLB cache. */
4488 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4489 &cbContig);
4490 if (rc == VINF_SUCCESS)
4491 {
4492 Assert(cbContig == X86_PAGE_SIZE);
4493 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4494 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4495 continue;
4496 }
4497 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4498 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4499#endif
4500
4501 /* Lookup the IOVA from the device table. */
4502 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4503 if (RT_SUCCESS(rc))
4504 { /* likely */ }
4505 else
4506 {
4507 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4508 return rc;
4509 }
4510 Assert(cbContig == X86_PAGE_SIZE);
4511 }
4512 }
4513 else
4514 {
4515 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4516 for (size_t i = 0; i < cIovas; i++)
4517 paGCPhysSpa[i] = pauIovas[i];
4518 }
4519
4520 return VINF_SUCCESS;
4521}
4522
4523
4524/**
4525 * Reads an interrupt remapping table entry from guest memory given its DTE.
4526 *
4527 * @returns VBox status code.
4528 * @param pDevIns The IOMMU device instance.
4529 * @param idDevice The device ID (bus, device, function).
4530 * @param pDte The device table entry.
4531 * @param GCPhysIn The source MSI address (used for reporting errors).
4532 * @param uDataIn The source MSI data.
4533 * @param enmOp The IOMMU operation being performed.
4534 * @param pIrte Where to store the interrupt remapping table entry.
4535 *
4536 * @thread Any.
4537 */
4538static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4539 IOMMUOP enmOp, PIRTE_T pIrte)
4540{
4541 /* Ensure the IRTE length is valid. */
4542 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4543
4544 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4545 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4546 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4547 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4548
4549 /* Ensure the IRTE falls completely within the interrupt table. */
4550 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4551 { /* likely */ }
4552 else
4553 {
4554 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4555 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4556
4557 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4558 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4559 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4560 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4561 kIoPageFaultType_IrteAddrInvalid);
4562 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4563 }
4564
4565 /* Read the IRTE from memory. */
4566 Assert(!(GCPhysIrte & 3));
4567 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4568 if (RT_SUCCESS(rc))
4569 return VINF_SUCCESS;
4570
4571 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4572 * situation. Is it an I/O page fault or a device table hardware error?
4573 * There's no interrupt table hardware error event, but it's unclear what
4574 * we should do here. */
4575 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4576 return VERR_IOMMU_IPE_4;
4577}
4578
4579
4580/**
4581 * Remaps the interrupt using the interrupt remapping table.
4582 *
4583 * @returns VBox status code.
4584 * @param pDevIns The IOMMU instance data.
4585 * @param idDevice The device ID (bus, device, function).
4586 * @param pDte The device table entry.
4587 * @param enmOp The IOMMU operation being performed.
4588 * @param pMsiIn The source MSI.
4589 * @param pMsiOut Where to store the remapped MSI.
4590 *
4591 * @thread Any.
4592 */
4593static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4594 PMSIMSG pMsiOut)
4595{
4596 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4597
4598 IRTE_T Irte;
4599 uint32_t const uMsiInData = pMsiIn->Data.u32;
4600 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4601 if (RT_SUCCESS(rc))
4602 {
4603 bool const fRemapEnable = RT_BOOL(Irte.n.u1RemapEnable);
4604 if (fRemapEnable)
4605 {
4606 if (!Irte.n.u1GuestMode)
4607 {
4608 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4609 {
4610 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4611#ifdef IOMMU_WITH_IRTE_CACHE
4612 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4613#endif
4614 return VINF_SUCCESS;
4615 }
4616
4617 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4618 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4619 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, fRemapEnable,
4620 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4621 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4622 kIoPageFaultType_IrteRsvdIntType);
4623 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4624 }
4625
4626 LogFunc(("Guest mode not supported -> IOPF\n"));
4627 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4628 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, fRemapEnable,
4629 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4630 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4631 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4632 }
4633
4634 LogFunc(("Remapping disabled -> IOPF\n"));
4635 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4636 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, fRemapEnable,
4637 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4638 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4639 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4640 }
4641
4642 return rc;
4643}
4644
4645
4646/**
4647 * Looks up an MSI interrupt from the interrupt remapping table.
4648 *
4649 * @returns VBox status code.
4650 * @param pDevIns The IOMMU instance data.
4651 * @param idDevice The device ID (bus, device, function).
4652 * @param enmOp The IOMMU operation being performed.
4653 * @param pMsiIn The source MSI.
4654 * @param pMsiOut Where to store the remapped MSI.
4655 *
4656 * @thread Any.
4657 */
4658static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4659{
4660 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4661 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4662 enmOp));
4663
4664 /* Read the device table entry from memory. */
4665 DTE_T Dte;
4666 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4667 if (RT_SUCCESS(rc))
4668 {
4669#ifdef IOMMU_WITH_IRTE_CACHE
4670 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte);
4671#endif
4672 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4673 if (Dte.n.u1IntrMapValid)
4674 {
4675 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4676 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4677 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4678 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4679 { /* likely */ }
4680 else
4681 {
4682 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4683 EVT_ILLEGAL_DTE_T Event;
4684 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4685 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4686 return VERR_IOMMU_INTR_REMAP_FAILED;
4687 }
4688
4689 /*
4690 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4691 * that's connected through HyperTransport it might be possible; but for us, it
4692 * doesn't seem we need to specially handle these pins.
4693 */
4694
4695 /*
4696 * Validate the MSI source address.
4697 *
4698 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4699 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4700 * claims the region as I/O space.
4701 *
4702 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4703 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4704 * See Intel spec. 10.11.1 "Message Address Register Format".
4705 */
4706 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4707 {
4708 /*
4709 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4710 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4711 */
4712 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4713 bool fPassThru = false;
4714 switch (u8DeliveryMode)
4715 {
4716 case VBOX_MSI_DELIVERY_MODE_FIXED:
4717 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4718 {
4719 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4720 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4721 {
4722 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4723 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4724 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4725 {
4726 /*
4727 * We don't support guest interrupt remapping yet. When we do, we'll need to
4728 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4729 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4730 * already reads the control register, add that as a parameter when we eventually
4731 * support guest interrupt remapping. For now, just assert.
4732 */
4733 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4734 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4735 NOREF(pThis);
4736
4737 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4738 }
4739
4740 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4741 EVT_ILLEGAL_DTE_T Event;
4742 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4743 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4744 return VERR_IOMMU_INTR_REMAP_FAILED;
4745 }
4746
4747 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4748 {
4749 fPassThru = true;
4750 break;
4751 }
4752
4753 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4754 {
4755 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4756 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4757 iommuAmdSetPciTargetAbort(pDevIns);
4758 return VERR_IOMMU_INTR_REMAP_DENIED;
4759 }
4760
4761 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4762 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4763 EVT_ILLEGAL_DTE_T Event;
4764 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4765 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4766 return VERR_IOMMU_INTR_REMAP_FAILED;
4767 }
4768
4769 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4770 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4771 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4772 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4773 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4774 default:
4775 {
4776 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4777 u8DeliveryMode));
4778 iommuAmdSetPciTargetAbort(pDevIns);
4779 return VERR_IOMMU_INTR_REMAP_FAILED;
4780 }
4781 }
4782
4783 /*
4784 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4785 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4786 */
4787 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4788 || !pMsiIn->Addr.n.u1DestMode)
4789 {
4790 if (fPassThru)
4791 {
4792 *pMsiOut = *pMsiIn;
4793 return VINF_SUCCESS;
4794 }
4795 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4796 pMsiIn->Data.n.u8Vector));
4797 }
4798 else
4799 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4800 IOMMU_LOG_PFX, u8DeliveryMode));
4801
4802 iommuAmdSetPciTargetAbort(pDevIns);
4803 return VERR_IOMMU_INTR_REMAP_DENIED;
4804 }
4805 else
4806 {
4807 /** @todo should be cause a PCI target abort here? */
4808 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4809 return VERR_IOMMU_INTR_REMAP_FAILED;
4810 }
4811 }
4812 else
4813 {
4814 LogFlowFunc(("DTE interrupt map not valid\n"));
4815 *pMsiOut = *pMsiIn;
4816 return VINF_SUCCESS;
4817 }
4818 }
4819
4820 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4821 return VERR_IOMMU_INTR_REMAP_FAILED;
4822}
4823
4824
4825/**
4826 * Interrupt remap request from a device.
4827 *
4828 * @returns VBox status code.
4829 * @param pDevIns The IOMMU device instance.
4830 * @param idDevice The device ID (bus, device, function).
4831 * @param pMsiIn The source MSI.
4832 * @param pMsiOut Where to store the remapped MSI.
4833 */
4834static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4835{
4836 /* Validate. */
4837 Assert(pDevIns);
4838 Assert(pMsiIn);
4839 Assert(pMsiOut);
4840
4841 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4842
4843 /* If this MSI was generated by the IOMMU itself, it's not subject to remapping, see @bugref{9654#c104}. */
4844 if (idDevice == pThis->uPciAddress)
4845 return VERR_IOMMU_CANNOT_CALL_SELF;
4846
4847 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4848 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4849 if (Ctrl.n.u1IommuEn)
4850 {
4851 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4852
4853 int rc;
4854#ifdef IOMMU_WITH_IRTE_CACHE
4855 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4856 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4857 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4858 if (RT_SUCCESS(rc))
4859 {
4860 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4861 return VINF_SUCCESS;
4862 }
4863 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4864#endif
4865
4866 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4867 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4868 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4869 return rc;
4870 }
4871
4872 *pMsiOut = *pMsiIn;
4873 return VINF_SUCCESS;
4874}
4875
4876
4877/**
4878 * @callback_method_impl{FNIOMMMIONEWWRITE}
4879 */
4880static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4881{
4882 NOREF(pvUser);
4883 Assert(cb == 4 || cb == 8);
4884 Assert(!(off & (cb - 1)));
4885
4886 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4887 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4888
4889 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4890 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4891}
4892
4893
4894/**
4895 * @callback_method_impl{FNIOMMMIONEWREAD}
4896 */
4897static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4898{
4899 NOREF(pvUser);
4900 Assert(cb == 4 || cb == 8);
4901 Assert(!(off & (cb - 1)));
4902
4903 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4904 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4905
4906 uint64_t uResult;
4907 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4908 if (rcStrict == VINF_SUCCESS)
4909 {
4910 if (cb == 8)
4911 *(uint64_t *)pv = uResult;
4912 else
4913 *(uint32_t *)pv = (uint32_t)uResult;
4914 }
4915
4916 return rcStrict;
4917}
4918
4919
4920#ifdef IN_RING3
4921/**
4922 * Processes an IOMMU command.
4923 *
4924 * @returns VBox status code.
4925 * @param pDevIns The IOMMU device instance.
4926 * @param pCmd The command to process.
4927 * @param GCPhysCmd The system physical address of the command.
4928 * @param pEvtError Where to store the error event in case of failures.
4929 *
4930 * @thread Command thread.
4931 */
4932static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4933{
4934 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4935 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4936
4937 STAM_COUNTER_INC(&pThis->StatCmd);
4938
4939 uint8_t const bCmd = pCmd->n.u4Opcode;
4940 switch (bCmd)
4941 {
4942 case IOMMU_CMD_COMPLETION_WAIT:
4943 {
4944 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4945
4946 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4947 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4948
4949 /* Validate reserved bits in the command. */
4950 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4951 {
4952 /* If Completion Store is requested, write the StoreData to the specified address. */
4953 if (pCmdComWait->n.u1Store)
4954 {
4955 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4956 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4957 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4958 if (RT_FAILURE(rc))
4959 {
4960 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4961 GCPhysStore, rc));
4962 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4963 return VERR_IOMMU_CMD_HW_ERROR;
4964 }
4965 }
4966
4967 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4968 if (pCmdComWait->n.u1Interrupt)
4969 {
4970 IOMMU_LOCK(pDevIns, pThisR3);
4971 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4972 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4973 IOMMU_UNLOCK(pDevIns, pThisR3);
4974 if (fRaiseInt)
4975 iommuAmdMsiInterruptRaise(pDevIns);
4976 }
4977 return VINF_SUCCESS;
4978 }
4979 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4980 return VERR_IOMMU_CMD_INVALID_FORMAT;
4981 }
4982
4983 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4984 {
4985 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4986 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4987 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4988
4989 /* Validate reserved bits in the command. */
4990 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4991 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4992 {
4993#ifdef IOMMU_WITH_DTE_CACHE
4994 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4995#endif
4996 return VINF_SUCCESS;
4997 }
4998 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4999 return VERR_IOMMU_CMD_INVALID_FORMAT;
5000 }
5001
5002 case IOMMU_CMD_INV_IOMMU_PAGES:
5003 {
5004 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
5005 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
5006 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
5007
5008 /* Validate reserved bits in the command. */
5009 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
5010 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
5011 {
5012#ifdef IOMMU_WITH_IOTLBE_CACHE
5013 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
5014 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
5015 uint8_t cShift;
5016 if (!pCmdInvPages->n.u1Size)
5017 cShift = X86_PAGE_4K_SHIFT;
5018 else
5019 {
5020 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
5021 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
5022 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
5023
5024 /*
5025 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
5026 * would do the right thing by clearing the entire cache for the specified domain ID.
5027 *
5028 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
5029 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
5030 * A debug-time assert is in place here to let us know if any software tries this.
5031 *
5032 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
5033 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
5034 */
5035 Assert(uIova != UINT64_C(0xfffffffffffff000));
5036 }
5037
5038 /*
5039 * Validate invalidation size.
5040 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
5041 */
5042 if ( cShift >= 12 /* 4 KB */
5043 && cShift <= 51 /* 2 PB */)
5044 {
5045 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
5046 size_t const cbIova = RT_BIT_64(cShift);
5047 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
5048 }
5049 else
5050 {
5051 /*
5052 * The guest provided size is invalid or exceeds the largest, meaningful page size.
5053 * In such situations we must remove all ranges for the specified domain ID.
5054 */
5055 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
5056 }
5057#endif
5058 return VINF_SUCCESS;
5059 }
5060 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5061 return VERR_IOMMU_CMD_INVALID_FORMAT;
5062 }
5063
5064 case IOMMU_CMD_INV_IOTLB_PAGES:
5065 {
5066 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
5067
5068 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
5069 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
5070 {
5071 /** @todo IOMMU: Implement remote IOTLB invalidation. */
5072 return VERR_NOT_IMPLEMENTED;
5073 }
5074 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5075 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5076 }
5077
5078 case IOMMU_CMD_INV_INTR_TABLE:
5079 {
5080 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
5081
5082 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
5083 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
5084
5085 /* Validate reserved bits in the command. */
5086 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
5087 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
5088 {
5089#ifdef IOMMU_WITH_IRTE_CACHE
5090 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
5091#endif
5092 return VINF_SUCCESS;
5093 }
5094 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5095 return VERR_IOMMU_CMD_INVALID_FORMAT;
5096 }
5097
5098 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
5099 {
5100 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
5101 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
5102 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
5103 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5104 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5105 }
5106
5107 case IOMMU_CMD_COMPLETE_PPR_REQ:
5108 {
5109 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
5110
5111 /* We don't support PPR requests yet. */
5112 Assert(!pThis->ExtFeat.n.u1PprSup);
5113 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5114 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5115 }
5116
5117 case IOMMU_CMD_INV_IOMMU_ALL:
5118 {
5119 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
5120 if (pThis->ExtFeat.n.u1InvAllSup)
5121 {
5122 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
5123 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
5124
5125 /* Validate reserved bits in the command. */
5126 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
5127 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
5128 {
5129#ifdef IOMMU_WITH_DTE_CACHE
5130 iommuAmdDteCacheRemoveAll(pDevIns);
5131#endif
5132#ifdef IOMMU_WITH_IOTLBE_CACHE
5133 iommuAmdIotlbRemoveAll(pDevIns);
5134#endif
5135 return VINF_SUCCESS;
5136 }
5137 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5138 return VERR_IOMMU_CMD_INVALID_FORMAT;
5139 }
5140 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5141 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5142 }
5143 }
5144
5145 STAM_COUNTER_DEC(&pThis->StatCmd);
5146 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5147 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5148 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5149}
5150
5151
5152/**
5153 * The IOMMU command thread.
5154 *
5155 * @returns VBox status code.
5156 * @param pDevIns The IOMMU device instance.
5157 * @param pThread The command thread.
5158 */
5159static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5160{
5161 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5162 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5163
5164 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5165 return VINF_SUCCESS;
5166
5167 /*
5168 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5169 * This avoid trashing the heap as well as not wasting time allocating
5170 * and freeing buffers while processing commands.
5171 */
5172 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5173 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5174 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5175
5176 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5177 {
5178 /*
5179 * Sleep perpetually until we are woken up to process commands.
5180 */
5181 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5182 if (!fSignaled)
5183 {
5184 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5185 AssertLogRelMsgReturnStmt(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), RTMemFree(pvCmds), rc);
5186 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5187 break;
5188 Log4Func(("Woken up with rc=%Rrc\n", rc));
5189 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5190 }
5191
5192 /*
5193 * Fetch and process IOMMU commands.
5194 */
5195 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5196 * temporary host buffer before processing them as a batch. If we want to
5197 * save on host memory a bit, we could (once PGM has the necessary APIs)
5198 * lock the page mappings page mappings and access them directly. */
5199 IOMMU_LOCK(pDevIns, pThisR3);
5200
5201 if (pThis->Status.n.u1CmdBufRunning)
5202 {
5203 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5204 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5205 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5206 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5207
5208 /* Validate. */
5209 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5210 Assert(offHead < cbCmdBuf);
5211 Assert(cbCmdBuf <= cbMaxCmdBuf);
5212
5213 if (offHead != offTail)
5214 {
5215 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5216 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5217
5218 IOMMU_UNLOCK(pDevIns, pThisR3);
5219 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5220 IOMMU_LOCK(pDevIns, pThisR3);
5221
5222 if (RT_SUCCESS(rc))
5223 {
5224 /* Indicate to software we've fetched all commands from the buffer. */
5225 pThis->CmdBufHeadPtr.n.off = offTail;
5226
5227 /* Allow IOMMU to do other work while we process commands. */
5228 IOMMU_UNLOCK(pDevIns, pThisR3);
5229
5230 /* Process the fetched commands. */
5231 EVT_GENERIC_T EvtError;
5232 do
5233 {
5234 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5235 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5236 if (RT_FAILURE(rc))
5237 {
5238 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5239 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5240 {
5241 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5242 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5243 }
5244 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5245 {
5246 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5247 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5248 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5249 }
5250 break;
5251 }
5252
5253 /* Move to the next command in the circular buffer. */
5254 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5255 } while (offHead != offTail);
5256 }
5257 else
5258 {
5259 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5260 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5261 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5262 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5263
5264 IOMMU_UNLOCK(pDevIns, pThisR3);
5265 }
5266 }
5267 else
5268 IOMMU_UNLOCK(pDevIns, pThisR3);
5269 }
5270 else
5271 IOMMU_UNLOCK(pDevIns, pThisR3);
5272 }
5273
5274 RTMemFree(pvCmds);
5275 LogFlowFunc(("Command thread terminating\n"));
5276 return VINF_SUCCESS;
5277}
5278
5279
5280/**
5281 * Wakes up the command thread so it can respond to a state change.
5282 *
5283 * @returns VBox status code.
5284 * @param pDevIns The IOMMU device instance.
5285 * @param pThread The command thread.
5286 */
5287static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5288{
5289 RT_NOREF(pThread);
5290 Log4Func(("\n"));
5291 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5292 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5293}
5294
5295
5296/**
5297 * @callback_method_impl{FNPCICONFIGREAD}
5298 */
5299static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5300 unsigned cb, uint32_t *pu32Value)
5301{
5302 /** @todo IOMMU: PCI config read stat counter. */
5303 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5304 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5305 return rcStrict;
5306}
5307
5308
5309/**
5310 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5311 * register write).
5312 *
5313 * @returns VBox status code.
5314 * @param pDevIns The IOMMU instance data.
5315 *
5316 * @remarks Call this function only when the IOMMU BAR is enabled.
5317 */
5318static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5319{
5320 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5321 Assert(pThis->IommuBar.n.u1Enable);
5322 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5323 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5324 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5325 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5326
5327 /* If the MMIO region is already mapped at the specified address, we're done. */
5328 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5329 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5330 return VINF_SUCCESS;
5331
5332 /* Unmap the previous MMIO region (which is at a different address). */
5333 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5334 {
5335 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5336 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5337 if (RT_FAILURE(rc))
5338 {
5339 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5340 return rc;
5341 }
5342 }
5343
5344 /* Map the newly specified MMIO region. */
5345 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5346 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5347 if (RT_FAILURE(rc))
5348 {
5349 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5350 return rc;
5351 }
5352
5353 return VINF_SUCCESS;
5354}
5355
5356
5357/**
5358 * @callback_method_impl{FNPCICONFIGWRITE}
5359 */
5360static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5361 unsigned cb, uint32_t u32Value)
5362{
5363 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5364
5365 /*
5366 * Discard writes to read-only registers that are specific to the IOMMU.
5367 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5368 * See PCI spec. 6.1. "Configuration Space Organization".
5369 */
5370 switch (uAddress)
5371 {
5372 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5373 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5374 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5375 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5376 {
5377 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5378 return VINF_SUCCESS;
5379 }
5380 }
5381
5382 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5383 IOMMU_LOCK(pDevIns, pThisR3);
5384
5385 VBOXSTRICTRC rcStrict;
5386 switch (uAddress)
5387 {
5388 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5389 {
5390 if (!pThis->IommuBar.n.u1Enable)
5391 {
5392 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5393 if (pThis->IommuBar.n.u1Enable)
5394 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5395 else
5396 rcStrict = VINF_SUCCESS;
5397 }
5398 else
5399 {
5400 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5401 rcStrict = VINF_SUCCESS;
5402 }
5403 break;
5404 }
5405
5406 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5407 {
5408 if (!pThis->IommuBar.n.u1Enable)
5409 {
5410 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5411 pThis->IommuBar.au32[1] = u32Value;
5412 }
5413 else
5414 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5415 rcStrict = VINF_SUCCESS;
5416 break;
5417 }
5418
5419 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5420 {
5421 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5422 RT_FALL_THRU();
5423 }
5424 default:
5425 {
5426 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5427 break;
5428 }
5429 }
5430
5431 IOMMU_UNLOCK(pDevIns, pThisR3);
5432
5433 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5434 return rcStrict;
5435}
5436
5437
5438/**
5439 * @callback_method_impl{FNDBGFHANDLERDEV}
5440 */
5441static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5442{
5443 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5444 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5445 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5446
5447 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
5448
5449 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5450 /* Device Table Base Addresses (all segments). */
5451 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5452 {
5453 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5454 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5455 if (fVerbose)
5456 {
5457 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5458 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5459 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5460 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5461 }
5462 }
5463 /* Command Buffer Base Address Register. */
5464 {
5465 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5466 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5467 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5468 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5469 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5470 if (fVerbose)
5471 {
5472 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5473 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5474 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5475 cEntries, cbBuffer);
5476 }
5477 }
5478 /* Event Log Base Address Register. */
5479 {
5480 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5481 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5482 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5483 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5484 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5485 if (fVerbose)
5486 {
5487 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5488 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5489 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5490 cEntries, cbBuffer);
5491 }
5492 }
5493 /* IOMMU Control Register. */
5494 {
5495 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5496 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5497 if (fVerbose)
5498 {
5499 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5500 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5501 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5502 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5503 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5504 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5505 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5506 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5507 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5508 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5509 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5510 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5511 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5512 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5513 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5514 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5515 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5516 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5517 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5518 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5519 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5520 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5521 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5522 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5523 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5524 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5525 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5526 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5527 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5528 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5529 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5530 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5531 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5532 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5533 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5534 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5535 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5536 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5537 }
5538 }
5539 /* Exclusion Base Address Register. */
5540 {
5541 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5542 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5543 if (fVerbose)
5544 {
5545 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5546 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5547 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5548 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5549 }
5550 }
5551 /* Exclusion Range Limit Register. */
5552 {
5553 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5554 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5555 if (fVerbose)
5556 {
5557 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5558 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5559 }
5560 }
5561 /* Extended Feature Register. */
5562 {
5563 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5564 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5565 if (fVerbose)
5566 {
5567 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5568 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5569 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5570 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5571 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5572 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5573 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5574 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5575 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5576 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5577 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5578 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5579 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5580 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5581 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5582 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5583 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5584 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5585 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5586 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5587 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5588 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5589 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5590 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5591 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5592 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5593 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5594 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5595 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5596 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5597 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5598 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5599 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5600 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5601 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5602 }
5603 }
5604 /* PPR Log Base Address Register. */
5605 {
5606 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5607 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5608 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5609 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5610 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5611 if (fVerbose)
5612 {
5613 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5614 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5615 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5616 cEntries, cbBuffer);
5617 }
5618 }
5619 /* Hardware Event (Hi) Register. */
5620 {
5621 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5622 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5623 if (fVerbose)
5624 {
5625 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5626 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5627 }
5628 }
5629 /* Hardware Event (Lo) Register. */
5630 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5631 /* Hardware Event Status. */
5632 {
5633 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5634 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5635 if (fVerbose)
5636 {
5637 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5638 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5639 }
5640 }
5641 /* Guest Virtual-APIC Log Base Address Register. */
5642 {
5643 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5644 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5645 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5646 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5647 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5648 if (fVerbose)
5649 {
5650 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5651 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5652 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5653 cEntries, cbBuffer);
5654 }
5655 }
5656 /* Guest Virtual-APIC Log Tail Address Register. */
5657 {
5658 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5659 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5660 if (fVerbose)
5661 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5662 }
5663 /* PPR Log B Base Address Register. */
5664 {
5665 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5666 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5667 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5668 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5669 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5670 if (fVerbose)
5671 {
5672 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5673 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5674 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5675 cEntries, cbBuffer);
5676 }
5677 }
5678 /* Event Log B Base Address Register. */
5679 {
5680 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5681 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5682 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5683 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5684 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5685 if (fVerbose)
5686 {
5687 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5688 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5689 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5690 cEntries, cbBuffer);
5691 }
5692 }
5693 /* Device-Specific Feature Extension Register. */
5694 {
5695 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5696 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5697 if (fVerbose)
5698 {
5699 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5700 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5701 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5702 }
5703 }
5704 /* Device-Specific Control Extension Register. */
5705 {
5706 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5707 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5708 if (fVerbose)
5709 {
5710 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5711 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5712 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5713 }
5714 }
5715 /* Device-Specific Status Extension Register. */
5716 {
5717 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5718 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5719 if (fVerbose)
5720 {
5721 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5722 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5723 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5724 }
5725 }
5726 /* Miscellaneous Information Register (Lo and Hi). */
5727 {
5728 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5729 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5730 if (fVerbose)
5731 {
5732 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5733 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5734 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5735 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5736 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5737 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5738 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5739 }
5740 }
5741 /* MSI Capability Header. */
5742 {
5743 MSI_CAP_HDR_T MsiCapHdr;
5744 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5745 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5746 if (fVerbose)
5747 {
5748 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5749 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5750 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5751 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5752 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5753 }
5754 }
5755 /* MSI Address Register (Lo and Hi). */
5756 {
5757 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5758 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5759 MSIADDR MsiAddr;
5760 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5761 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5762 if (fVerbose)
5763 {
5764 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5765 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5766 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5767 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5768 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5769 }
5770 }
5771 /* MSI Data. */
5772 {
5773 MSIDATA MsiData;
5774 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5775 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5776 if (fVerbose)
5777 {
5778 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5779 MsiData.n.u8Vector);
5780 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5781 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5782 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5783 "level" : "edge");
5784 }
5785 }
5786 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5787 {
5788 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5789 MsiMapCapHdr.u32 = 0;
5790 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5791 if (fVerbose)
5792 {
5793 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5794 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5795 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5796 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5797 }
5798 }
5799 /* Performance Optimization Control Register. */
5800 {
5801 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5802 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5803 if (fVerbose)
5804 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5805 }
5806 /* XT (x2APIC) General Interrupt Control Register. */
5807 {
5808 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5809 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5810 if (fVerbose)
5811 {
5812 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5813 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5814 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5815 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5816 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5817 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5818 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5819 }
5820 }
5821 /* XT (x2APIC) PPR Interrupt Control Register. */
5822 {
5823 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5824 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5825 if (fVerbose)
5826 {
5827 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5828 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5829 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5830 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5831 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5832 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5833 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5834 }
5835 }
5836 /* XT (X2APIC) GA Log Interrupt Control Register. */
5837 {
5838 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5839 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5840 if (fVerbose)
5841 {
5842 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5843 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5844 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5845 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5846 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5847 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5848 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5849 }
5850 }
5851 /* MARC Registers. */
5852 {
5853 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5854 {
5855 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5856 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5857 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5858
5859 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5860 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5861 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5862 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5863
5864 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5865 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5866 }
5867 }
5868 /* Reserved Register. */
5869 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5870 /* Command Buffer Head Pointer Register. */
5871 {
5872 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5873 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5874 CmdBufHeadPtr.n.off);
5875 }
5876 /* Command Buffer Tail Pointer Register. */
5877 {
5878 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5879 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5880 CmdBufTailPtr.n.off);
5881 }
5882 /* Event Log Head Pointer Register. */
5883 {
5884 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5885 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5886 EvtLogHeadPtr.n.off);
5887 }
5888 /* Event Log Tail Pointer Register. */
5889 {
5890 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5891 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5892 EvtLogTailPtr.n.off);
5893 }
5894 /* Status Register. */
5895 {
5896 IOMMU_STATUS_T const Status = pThis->Status;
5897 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5898 if (fVerbose)
5899 {
5900 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5901 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5902 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5903 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5904 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5905 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5906 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5907 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5908 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5909 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5910 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5911 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5912 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5913 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5914 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5915 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5916 }
5917 }
5918 /* PPR Log Head Pointer. */
5919 {
5920 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5921 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5922 PprLogHeadPtr.n.off);
5923 }
5924 /* PPR Log Tail Pointer. */
5925 {
5926 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5927 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5928 PprLogTailPtr.n.off);
5929 }
5930 /* Guest Virtual-APIC Log Head Pointer. */
5931 {
5932 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5933 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5934 GALogHeadPtr.n.u12GALogPtr);
5935 }
5936 /* Guest Virtual-APIC Log Tail Pointer. */
5937 {
5938 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5939 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5940 GALogTailPtr.n.u12GALogPtr);
5941 }
5942 /* PPR Log B Head Pointer. */
5943 {
5944 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5945 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5946 PprLogBHeadPtr.n.off);
5947 }
5948 /* PPR Log B Tail Pointer. */
5949 {
5950 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5951 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5952 PprLogBTailPtr.n.off);
5953 }
5954 /* Event Log B Head Pointer. */
5955 {
5956 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5957 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5958 EvtLogBHeadPtr.n.off);
5959 }
5960 /* Event Log B Tail Pointer. */
5961 {
5962 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5963 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5964 EvtLogBTailPtr.n.off);
5965 }
5966 /* PPR Log Auto Response Register. */
5967 {
5968 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5969 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5970 if (fVerbose)
5971 {
5972 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5973 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5974 }
5975 }
5976 /* PPR Log Overflow Early Warning Indicator Register. */
5977 {
5978 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5979 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5980 if (fVerbose)
5981 {
5982 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5983 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5984 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5985 }
5986 }
5987 /* PPR Log Overflow Early Warning Indicator Register. */
5988 {
5989 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5990 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5991 if (fVerbose)
5992 {
5993 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5994 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5995 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5996 }
5997 }
5998}
5999
6000
6001/**
6002 * Dumps the DTE via the info callback helper.
6003 *
6004 * @param pHlp The info helper.
6005 * @param pDte The device table entry.
6006 * @param pszPrefix The string prefix.
6007 */
6008static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
6009{
6010 AssertReturnVoid(pHlp);
6011 AssertReturnVoid(pDte);
6012 AssertReturnVoid(pszPrefix);
6013
6014 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
6015 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
6016 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
6017 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
6018 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
6019 pDte->n.u40PageTableRootPtrLo << 12);
6020 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
6021 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
6022 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
6023 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
6024 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
6025 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
6026 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
6027 (pDte->n.u21GstCr3TableRootPtrHi << 31)
6028 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
6029 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
6030 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
6031 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
6032 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
6033 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
6034 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
6035 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
6036 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
6037 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
6038 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
6039 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
6040 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
6041 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
6042 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
6043 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
6044 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
6045 {
6046 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
6047 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
6048 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
6049 cbIntrTable);
6050 }
6051 else
6052 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
6053 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
6054 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
6055 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
6056 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
6057 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
6058 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
6059 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
6060 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
6061 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
6062 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
6063 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
6064 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
6065 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
6066 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
6067 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
6068 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
6069 pHlp->pfnPrintf(pHlp, "\n");
6070}
6071
6072
6073/**
6074 * @callback_method_impl{FNDBGFHANDLERDEV}
6075 */
6076static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6077{
6078 if (pszArgs)
6079 {
6080 uint16_t idDevice = 0;
6081 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
6082 if (RT_SUCCESS(rc))
6083 {
6084 DTE_T Dte;
6085 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
6086 if (RT_SUCCESS(rc))
6087 {
6088 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
6089 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
6090 return;
6091 }
6092 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
6093 }
6094 else
6095 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
6096 }
6097 else
6098 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
6099}
6100
6101
6102# ifdef IOMMU_WITH_DTE_CACHE
6103/**
6104 * @callback_method_impl{FNDBGFHANDLERDEV}
6105 */
6106static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6107{
6108 RT_NOREF(pszArgs);
6109 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6110 IOMMU_CACHE_LOCK(pDevIns, pThis);
6111
6112 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
6113 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
6114 for (uint16_t i = 0; i < cDteCache; i++)
6115 {
6116 uint16_t const idDevice = pThis->aDeviceIds[i];
6117 if (idDevice)
6118 {
6119 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
6120 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6121 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6122 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6123
6124 PCDTECACHE pDteCache = &pThis->aDteCache[i];
6125 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
6126 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
6127 pHlp->pfnPrintf(pHlp, "\n");
6128 }
6129 }
6130 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6131}
6132# endif /* IOMMU_WITH_DTE_CACHE */
6133
6134
6135# ifdef IOMMU_WITH_IOTLBE_CACHE
6136/**
6137 * @callback_method_impl{FNDBGFHANDLERDEV}
6138 */
6139static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6140{
6141 if (pszArgs)
6142 {
6143 uint16_t idDomain = 0;
6144 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6145 if (RT_SUCCESS(rc))
6146 {
6147 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6148 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6149 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6150 IOTLBEINFOARG Args;
6151 Args.pIommuR3 = pThisR3;
6152 Args.pHlp = pHlp;
6153 Args.idDomain = idDomain;
6154
6155 IOMMU_CACHE_LOCK(pDevIns, pThis);
6156 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6157 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6158 }
6159 else
6160 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6161 }
6162 else
6163 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6164}
6165# endif /* IOMMU_WITH_IOTLBE_CACHE */
6166
6167
6168# ifdef IOMMU_WITH_IRTE_CACHE
6169/**
6170 * Gets the interrupt type name for an interrupt type in the IRTE.
6171 *
6172 * @returns The interrupt type name.
6173 * @param uIntrType The interrupt type (as specified in the IRTE).
6174 */
6175static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6176{
6177 switch (uIntrType)
6178 {
6179 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6180 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6181 default: return "<Reserved>";
6182 }
6183}
6184
6185
6186/**
6187 * @callback_method_impl{FNDBGFHANDLERDEV}
6188 */
6189static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6190{
6191 RT_NOREF(pszArgs);
6192
6193 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6194 IOMMU_CACHE_LOCK(pDevIns, pThis);
6195
6196 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6197 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6198 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6199 {
6200 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6201 uint32_t const uKey = pIrteCache->uKey;
6202 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6203 {
6204 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6205 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6206 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6207 idxIrte, offIrte, idDevice,
6208 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6209 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6210 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6211
6212 PCIRTE_T pIrte = &pIrteCache->Irte;
6213 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6214 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6215 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6216 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6217 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6218 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6219 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6220 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6221 pHlp->pfnPrintf(pHlp, "\n");
6222 }
6223 }
6224 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6225}
6226# endif /* IOMMU_WITH_IRTE_CACHE */
6227
6228
6229/**
6230 * @callback_method_impl{FNDBGFHANDLERDEV}
6231 */
6232static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6233{
6234 RT_NOREF(pszArgs);
6235
6236 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6237 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6238 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6239 NOREF(pPciDev);
6240
6241 uint8_t cSegments = 0;
6242 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6243 {
6244 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6245 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6246 if (GCPhysDevTab)
6247 ++cSegments;
6248 }
6249
6250 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6251 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6252 if (!cSegments)
6253 return;
6254
6255 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6256 {
6257 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6258 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6259 if (GCPhysDevTab)
6260 {
6261 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6262 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6263
6264 void *pvDevTab = RTMemAllocZ(cbDevTab);
6265 if (RT_LIKELY(pvDevTab))
6266 {
6267 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6268 if (RT_SUCCESS(rc))
6269 {
6270 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6271 {
6272 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6273 if ( pDte->n.u1Valid
6274 && pDte->n.u1TranslationValid
6275 && pDte->n.u3Mode != 0)
6276 {
6277 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6278 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6279 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6280 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6281 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6282 pHlp->pfnPrintf(pHlp, "\n");
6283 }
6284 }
6285 pHlp->pfnPrintf(pHlp, "\n");
6286 }
6287 else
6288 {
6289 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6290 cbDevTab, rc);
6291 }
6292
6293 RTMemFree(pvDevTab);
6294 }
6295 else
6296 {
6297 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6298 return;
6299 }
6300 }
6301 }
6302}
6303
6304
6305/**
6306 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6307 */
6308static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6309{
6310 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6311 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6312 LogFlowFunc(("\n"));
6313
6314 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6315 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6316 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6317 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6318 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6319 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6320 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6321
6322 /* Next, save all registers that can be modified by the guest. */
6323 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6324
6325 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6326 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6327 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6328 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6329
6330 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6331 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6332 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6333 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6334 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6335 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6336#if 0
6337 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6338#endif
6339
6340 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6341 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6342 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6343 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6344
6345 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6346 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6347
6348 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6349 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6350
6351#if 0
6352 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6353 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6354 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6355
6356 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6357#endif
6358 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6359
6360 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6361 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6362 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6363
6364 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6365 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6366 for (size_t i = 0; i < cMarcApers; i++)
6367 {
6368 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6369 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6370 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6371 }
6372
6373#if 0
6374 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6375#endif
6376
6377 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6378 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6379 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6380 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6381
6382 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6383
6384 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6385 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6386
6387 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6388 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6389
6390 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6391 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6392
6393 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6394 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6395
6396 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6397 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6398 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6399
6400 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6401}
6402
6403
6404/**
6405 * @callback_method_impl{FNSSMDEVLOADEXEC}
6406 */
6407static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6408{
6409 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6410 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6411 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6412 LogFlowFunc(("\n"));
6413
6414 /* Validate. */
6415 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6416 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6417 {
6418 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6419 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6420 }
6421
6422 /* Load ExtFeat and other read-only registers first. */
6423 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6424 AssertRCReturn(rc, rc);
6425 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6426 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6427 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6428 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6429 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6430 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6431 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6432
6433 /* IOMMU base address register. */
6434 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6435 AssertRCReturn(rc, rc);
6436 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6437
6438 /* Device table base address registers. */
6439 uint8_t cDevTabBaseAddrs;
6440 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6441 AssertRCReturn(rc, rc);
6442 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6443 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6444 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6445 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6446 {
6447 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6448 AssertRCReturn(rc, rc);
6449 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6450 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6451 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6452 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6453 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6454 }
6455
6456 /* Command buffer base address register. */
6457 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6458 AssertRCReturn(rc, rc);
6459 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6460 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6461 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6462
6463 /* Event log base address register. */
6464 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6465 AssertRCReturn(rc, rc);
6466 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6467 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6468 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6469
6470 /* Control register. */
6471 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6472 AssertRCReturn(rc, rc);
6473 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6474 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6475 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6476
6477 /* Exclusion range base address register. */
6478 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6479 AssertRCReturn(rc, rc);
6480 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6481
6482 /* Exclusion range limit register. */
6483 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6484 AssertRCReturn(rc, rc);
6485 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6486 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6487
6488#if 0
6489 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6490#endif
6491
6492 /* PPR log base address register. */
6493 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6494 AssertRCReturn(rc, rc);
6495 Assert(!pThis->ExtFeat.n.u1PprSup);
6496
6497 /* Hardware event (Hi) register. */
6498 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6499 AssertRCReturn(rc, rc);
6500
6501 /* Hardware event (Lo) register. */
6502 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6503 AssertRCReturn(rc, rc);
6504
6505 /* Hardware event status register. */
6506 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6507 AssertRCReturn(rc, rc);
6508 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6509
6510 /* Guest Virtual-APIC log base address register. */
6511 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6512 AssertRCReturn(rc, rc);
6513 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6514
6515 /* Guest Virtual-APIC log tail address register. */
6516 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6517 AssertRCReturn(rc, rc);
6518 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6519
6520 /* PPR log-B base address register. */
6521 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6522 AssertRCReturn(rc, rc);
6523 Assert(!pThis->ExtFeat.n.u1PprSup);
6524
6525 /* Event log-B base address register. */
6526 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6527 AssertRCReturn(rc, rc);
6528 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6529
6530#if 0
6531 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6532 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6533 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6534
6535 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6536#endif
6537
6538 /* Performance optimization control register. */
6539 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6540 AssertRCReturn(rc, rc);
6541 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6542
6543 /* x2APIC registers. */
6544 {
6545 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6546
6547 /* x2APIC general interrupt control register. */
6548 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6549 AssertRCReturn(rc, rc);
6550
6551 /* x2APIC PPR interrupt control register. */
6552 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6553 AssertRCReturn(rc, rc);
6554
6555 /* x2APIC GA log interrupt control register. */
6556 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6557 AssertRCReturn(rc, rc);
6558 }
6559
6560 /* MARC (Memory Access and Routing) registers. */
6561 {
6562 uint8_t cMarcApers;
6563 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6564 AssertRCReturn(rc, rc);
6565 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6566 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6567 for (uint8_t i = 0; i < cMarcApers; i++)
6568 {
6569 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6570 AssertRCReturn(rc, rc);
6571
6572 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6573 AssertRCReturn(rc, rc);
6574
6575 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6576 AssertRCReturn(rc, rc);
6577 }
6578 Assert(!pThis->ExtFeat.n.u2MarcSup);
6579 }
6580
6581#if 0
6582 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6583#endif
6584
6585 /* Command buffer head pointer register. */
6586 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6587 AssertRCReturn(rc, rc);
6588 {
6589 /*
6590 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6591 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6592 * we shouldn't see such values in the saved state.
6593 */
6594 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6595 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6596 Assert(cbBuf <= _512K);
6597 AssertLogRelMsgReturn(offBuf < cbBuf,
6598 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6599 }
6600
6601 /* Command buffer tail pointer register. */
6602 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6603 AssertRCReturn(rc, rc);
6604 {
6605 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6606 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6607 Assert(cbBuf <= _512K);
6608 AssertLogRelMsgReturn(offBuf < cbBuf,
6609 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6610 }
6611
6612 /* Event log head pointer register. */
6613 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6614 AssertRCReturn(rc, rc);
6615 {
6616 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6617 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6618 Assert(cbBuf <= _512K);
6619 AssertLogRelMsgReturn(offBuf < cbBuf,
6620 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6621 }
6622
6623 /* Event log tail pointer register. */
6624 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6625 AssertRCReturn(rc, rc);
6626 {
6627 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6628 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6629 Assert(cbBuf <= _512K);
6630 AssertLogRelMsgReturn(offBuf < cbBuf,
6631 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6632 }
6633
6634 /* Status register. */
6635 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6636 AssertRCReturn(rc, rc);
6637 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6638
6639 /* PPR log head pointer register. */
6640 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6641 AssertRCReturn(rc, rc);
6642 Assert(!pThis->ExtFeat.n.u1PprSup);
6643
6644 /* PPR log tail pointer register. */
6645 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6646 AssertRCReturn(rc, rc);
6647 Assert(!pThis->ExtFeat.n.u1PprSup);
6648
6649 /* Guest Virtual-APIC log head pointer register. */
6650 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6651 AssertRCReturn(rc, rc);
6652 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6653
6654 /* Guest Virtual-APIC log tail pointer register. */
6655 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6656 AssertRCReturn(rc, rc);
6657 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6658
6659 /* PPR log-B head pointer register. */
6660 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6661 AssertRCReturn(rc, rc);
6662 Assert(!pThis->ExtFeat.n.u1PprSup);
6663
6664 /* PPR log-B head pointer register. */
6665 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6666 AssertRCReturn(rc, rc);
6667 Assert(!pThis->ExtFeat.n.u1PprSup);
6668
6669 /* Event log-B head pointer register. */
6670 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6671 AssertRCReturn(rc, rc);
6672 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6673
6674 /* Event log-B tail pointer register. */
6675 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6676 AssertRCReturn(rc, rc);
6677 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6678
6679 /* PPR log auto response register. */
6680 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6681 AssertRCReturn(rc, rc);
6682 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6683
6684 /* PPR log overflow early indicator register. */
6685 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6686 AssertRCReturn(rc, rc);
6687 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6688
6689 /* PPR log-B overflow early indicator register. */
6690 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6691 AssertRCReturn(rc, rc);
6692 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6693
6694 /* End marker. */
6695 {
6696 uint32_t uEndMarker;
6697 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6698 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6699 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6700 rcErr);
6701 }
6702
6703 return rc;
6704}
6705
6706
6707/**
6708 * @callback_method_impl{FNSSMDEVLOADDONE}
6709 */
6710static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6711{
6712 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6713 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6714 RT_NOREF(pSSM);
6715 LogFlowFunc(("\n"));
6716
6717 /* Sanity. */
6718 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6719 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6720
6721 int rc;
6722 IOMMU_LOCK(pDevIns, pThisR3);
6723
6724 /* Map MMIO regions if the IOMMU BAR is enabled. */
6725 if (pThis->IommuBar.n.u1Enable)
6726 rc = iommuAmdR3MmioSetup(pDevIns);
6727 else
6728 rc = VINF_SUCCESS;
6729
6730 /* Wake up the command thread if commands need processing. */
6731 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6732
6733 IOMMU_UNLOCK(pDevIns, pThisR3);
6734
6735 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6736 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6737 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6738 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6739 pThis->ExtFeat.u64));
6740 return rc;
6741}
6742
6743
6744/**
6745 * @interface_method_impl{PDMDEVREG,pfnReset}
6746 */
6747static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6748{
6749 /*
6750 * Resets read-write portion of the IOMMU state.
6751 *
6752 * NOTE! State not initialized here is expected to be initialized during
6753 * device construction and remain read-only through the lifetime of the VM.
6754 */
6755 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6756 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6757 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6758 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6759 LogFlowFunc(("\n"));
6760
6761 IOMMU_LOCK(pDevIns, pThisR3);
6762
6763 RT_ZERO(pThis->aDevTabBaseAddrs);
6764
6765 pThis->CmdBufBaseAddr.u64 = 0;
6766 pThis->CmdBufBaseAddr.n.u4Len = 8;
6767
6768 pThis->EvtLogBaseAddr.u64 = 0;
6769 pThis->EvtLogBaseAddr.n.u4Len = 8;
6770
6771 pThis->Ctrl.u64 = 0;
6772 pThis->Ctrl.n.u1Coherent = 1;
6773 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6774
6775 pThis->ExclRangeBaseAddr.u64 = 0;
6776 pThis->ExclRangeLimit.u64 = 0;
6777
6778 pThis->PprLogBaseAddr.u64 = 0;
6779 pThis->PprLogBaseAddr.n.u4Len = 8;
6780
6781 pThis->HwEvtHi.u64 = 0;
6782 pThis->HwEvtLo = 0;
6783 pThis->HwEvtStatus.u64 = 0;
6784
6785 pThis->GALogBaseAddr.u64 = 0;
6786 pThis->GALogBaseAddr.n.u4Len = 8;
6787 pThis->GALogTailAddr.u64 = 0;
6788
6789 pThis->PprLogBBaseAddr.u64 = 0;
6790 pThis->PprLogBBaseAddr.n.u4Len = 8;
6791
6792 pThis->EvtLogBBaseAddr.u64 = 0;
6793 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6794
6795 pThis->PerfOptCtrl.u32 = 0;
6796
6797 pThis->XtGenIntrCtrl.u64 = 0;
6798 pThis->XtPprIntrCtrl.u64 = 0;
6799 pThis->XtGALogIntrCtrl.u64 = 0;
6800
6801 RT_ZERO(pThis->aMarcApers);
6802
6803 pThis->CmdBufHeadPtr.u64 = 0;
6804 pThis->CmdBufTailPtr.u64 = 0;
6805 pThis->EvtLogHeadPtr.u64 = 0;
6806 pThis->EvtLogTailPtr.u64 = 0;
6807
6808 pThis->Status.u64 = 0;
6809
6810 pThis->PprLogHeadPtr.u64 = 0;
6811 pThis->PprLogTailPtr.u64 = 0;
6812
6813 pThis->GALogHeadPtr.u64 = 0;
6814 pThis->GALogTailPtr.u64 = 0;
6815
6816 pThis->PprLogBHeadPtr.u64 = 0;
6817 pThis->PprLogBTailPtr.u64 = 0;
6818
6819 pThis->EvtLogBHeadPtr.u64 = 0;
6820 pThis->EvtLogBTailPtr.u64 = 0;
6821
6822 pThis->PprLogAutoResp.u64 = 0;
6823 pThis->PprLogOverflowEarly.u64 = 0;
6824 pThis->PprLogBOverflowEarly.u64 = 0;
6825
6826 pThis->IommuBar.u64 = 0;
6827 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6828 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6829
6830 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6831
6832 IOMMU_UNLOCK(pDevIns, pThisR3);
6833
6834#ifdef IOMMU_WITH_DTE_CACHE
6835 iommuAmdDteCacheRemoveAll(pDevIns);
6836#endif
6837#ifdef IOMMU_WITH_IOTLBE_CACHE
6838 iommuAmdIotlbRemoveAll(pDevIns);
6839#endif
6840#ifdef IOMMU_WITH_IRTE_CACHE
6841 iommuAmdIrteCacheRemoveAll(pDevIns);
6842#endif
6843}
6844
6845
6846/**
6847 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6848 */
6849static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6850{
6851 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6852 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6853 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6854 LogFlowFunc(("\n"));
6855
6856 IOMMU_LOCK(pDevIns, pThisR3);
6857
6858 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6859 {
6860 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6861 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6862 }
6863
6864#ifdef IOMMU_WITH_IOTLBE_CACHE
6865 if (pThisR3->paIotlbes)
6866 {
6867 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6868 pThisR3->paIotlbes = NULL;
6869 pThisR3->idxUnusedIotlbe = 0;
6870 }
6871#endif
6872
6873 IOMMU_UNLOCK(pDevIns, pThisR3);
6874 return VINF_SUCCESS;
6875}
6876
6877
6878/**
6879 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6880 */
6881static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6882{
6883 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6884
6885 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6886 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6887 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6888
6889 pThis->u32Magic = IOMMU_MAGIC;
6890 pThisR3->pDevInsR3 = pDevIns;
6891
6892 LogFlowFunc(("iInstance=%d\n", iInstance));
6893
6894 /*
6895 * Validate and read the configuration.
6896 */
6897 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "PCIAddress", "");
6898 int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
6899 if (RT_FAILURE(rc))
6900 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
6901 if (!PCIBDF_IS_VALID(pThis->uPciAddress))
6902 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed \"PCIAddress\" of the AMD IOMMU cannot be invalid"));
6903
6904 /*
6905 * Register the IOMMU with PDM.
6906 */
6907 PDMIOMMUREGR3 IommuReg;
6908 RT_ZERO(IommuReg);
6909 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6910 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6911 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6912 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6913 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6914 rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6915 if (RT_FAILURE(rc))
6916 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6917 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6918 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6919 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6920 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6921 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6922 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6923 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6924 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6925 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
6926 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
6927 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
6928 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
6929
6930 /*
6931 * We will use PDM's critical section (via helpers) for the IOMMU device.
6932 */
6933 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6934 AssertRCReturn(rc, rc);
6935
6936 /*
6937 * Initialize read-only PCI configuration space.
6938 */
6939 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6940 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6941
6942 /* Header. */
6943 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6944 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6945 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6946 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6947 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6948 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6949 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6950 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6951 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6952 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6953 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6954 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6955 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6956 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6957
6958 /* Capability Header. */
6959 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6960 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6961 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6962 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6963 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6964 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6965 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6966 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6967 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6968 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6969 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6970
6971 /* Base Address Register. */
6972 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6973 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6974
6975 /* IOMMU Range Register. */
6976 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6977
6978 /* Misc. Information Register. */
6979 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6980 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6981 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6982 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6983 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6984 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6985 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6986 uint32_t const uMiscInfoReg1 = 0;
6987 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6988 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6989
6990 /* MSI Capability Header register. */
6991 PDMMSIREG MsiReg;
6992 RT_ZERO(MsiReg);
6993 MsiReg.cMsiVectors = 1;
6994 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6995 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6996 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6997
6998 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6999#if 0
7000 /* MSI Address Lo. */
7001 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
7002 /* MSI Address Hi. */
7003 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
7004 /* MSI Data. */
7005 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
7006#endif
7007
7008#if 0
7009 /** @todo IOMMU: I don't know if we need to support this, enable later if
7010 * required. */
7011 /* MSI Mapping Capability Header register. */
7012 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
7013 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
7014 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
7015 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
7016 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
7017 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
7018 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
7019#endif
7020
7021 /*
7022 * Register the PCI function with PDM.
7023 */
7024 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
7025 AssertLogRelRCReturn(rc, rc);
7026
7027 /*
7028 * Register MSI support for the PCI device.
7029 * This must be done -after- registering it as a PCI device!
7030 */
7031 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
7032 AssertRCReturn(rc, rc);
7033
7034 /*
7035 * Intercept PCI config. space accesses.
7036 */
7037 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
7038 AssertLogRelRCReturn(rc, rc);
7039
7040 /*
7041 * Create the MMIO region.
7042 * Mapping of the region is done when software configures it via PCI config space.
7043 */
7044 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
7045 NULL /* pvUser */,
7046 IOMMMIO_FLAGS_READ_DWORD_QWORD
7047 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
7048 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
7049 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
7050 "AMD-IOMMU", &pThis->hMmio);
7051 AssertLogRelRCReturn(rc, rc);
7052
7053 /*
7054 * Register saved state handlers.
7055 */
7056 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
7057 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
7058 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
7059 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
7060 AssertLogRelRCReturn(rc, rc);
7061
7062 /*
7063 * Register debugger info items.
7064 */
7065 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
7066 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
7067 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
7068#ifdef IOMMU_WITH_IOTLBE_CACHE
7069 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
7070#endif
7071#ifdef IOMMU_WITH_DTE_CACHE
7072 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
7073#endif
7074#ifdef IOMMU_WITH_IRTE_CACHE
7075 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
7076#endif
7077
7078# ifdef VBOX_WITH_STATISTICS
7079 /*
7080 * Statistics.
7081 */
7082 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
7083 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
7084
7085 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
7086 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
7087
7088 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
7089 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
7090
7091 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
7092 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
7093
7094 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
7095 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
7096
7097 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
7098 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
7099
7100 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
7101 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
7102
7103 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
7104 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
7105 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
7106 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
7107 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
7108 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
7109 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
7110 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
7111 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
7112
7113
7114 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
7115 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
7116
7117 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
7118 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
7119
7120 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
7121 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
7122
7123 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7124 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7125 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
7126 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
7127 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
7128 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
7129 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
7130
7131 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7132 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7133
7134 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatNonStdPageSize, STAMTYPE_COUNTER, "MemAccess/NonStdPageSize", STAMUNIT_OCCURENCES, "Number of non-standard page size translations.");
7135 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIopfs, STAMTYPE_COUNTER, "MemAccess/IOPFs", STAMUNIT_OCCURENCES, "Number of I/O page faults.");
7136# endif
7137
7138 /*
7139 * Create the command thread and its event semaphore.
7140 */
7141 char szDevIommu[64];
7142 RT_ZERO(szDevIommu);
7143 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
7144 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
7145 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
7146 AssertLogRelRCReturn(rc, rc);
7147
7148 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7149 AssertLogRelRCReturn(rc, rc);
7150
7151#ifdef IOMMU_WITH_DTE_CACHE
7152 /*
7153 * Initialize the critsect of the cache.
7154 */
7155 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7156 AssertLogRelRCReturn(rc, rc);
7157
7158 /* Several places in this code relies on this basic assumption - assert it! */
7159 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7160#endif
7161
7162#ifdef IOMMU_WITH_IOTLBE_CACHE
7163 /*
7164 * Allocate IOTLB entries.
7165 * This is allocated upfront since we expect a relatively small number of entries,
7166 * is more cache-line efficient and easier to track least recently used entries for
7167 * eviction when the cache is full. This also avoids unpredictable behavior during
7168 * the lifetime of the VM if the hyperheap gets full.
7169 */
7170 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7171 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7172 if (!pThisR3->paIotlbes)
7173 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7174 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7175 RTListInit(&pThisR3->LstLruIotlbe);
7176 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7177#endif
7178
7179 /*
7180 * Initialize read-only registers.
7181 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7182 */
7183 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7184 pThis->ExtFeat.u64 = 0;
7185 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7186 //pThis->ExtFeat.n.u1PprSup = 0;
7187 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7188 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7189 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7190 pThis->ExtFeat.n.u1InvAllSup = 1;
7191 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7192 pThis->ExtFeat.n.u1HwErrorSup = 1;
7193 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7194 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7195 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7196 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7197 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7198 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7199 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7200 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7201 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7202 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7203 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7204 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7205 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7206 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7207 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7208 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7209 //pThis->ExtFeat.n.u2MarcSup = 0;
7210 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7211 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7212 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7213 //pThis->ExtFeat.n.u1GstIoSup = 0;
7214 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7215 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7216 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7217 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7218 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7219 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7220 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7221
7222 pThis->DevSpecificFeat.u64 = 0;
7223 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7224 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7225
7226 pThis->DevSpecificCtrl.u64 = 0;
7227 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7228 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7229
7230 pThis->DevSpecificStatus.u64 = 0;
7231 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7232 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7233
7234 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7235
7236 pThis->RsvdReg = 0;
7237
7238 /*
7239 * Initialize parts of the IOMMU state as it would during reset.
7240 * Also initializes non-zero initial values like IRTE cache keys.
7241 * Must be called -after- initializing PCI config. space registers.
7242 */
7243 iommuAmdR3Reset(pDevIns);
7244
7245 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7246 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7247 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7248 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7249 pThis->ExtFeat.u64));
7250 return VINF_SUCCESS;
7251}
7252
7253#else
7254
7255/**
7256 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7257 */
7258static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7259{
7260 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7261 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7262 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7263 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7264
7265 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7266 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7267 AssertRCReturn(rc, rc);
7268
7269 /* Set up the MMIO RZ handlers. */
7270 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7271 AssertRCReturn(rc, rc);
7272
7273 /* Set up the IOMMU RZ callbacks. */
7274 PDMIOMMUREGCC IommuReg;
7275 RT_ZERO(IommuReg);
7276 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7277 IommuReg.idxIommu = pThis->idxIommu;
7278 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7279 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7280 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7281 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7282 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7283 AssertRCReturn(rc, rc);
7284 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7285 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7286 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7287 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
7288 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
7289 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
7290 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
7291 return VINF_SUCCESS;
7292}
7293#endif
7294
7295
7296/**
7297 * The device registration structure.
7298 */
7299const PDMDEVREG g_DeviceIommuAmd =
7300{
7301 /* .u32Version = */ PDM_DEVREG_VERSION,
7302 /* .uReserved0 = */ 0,
7303 /* .szName = */ "iommu-amd",
7304 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7305 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7306 /* .cMaxInstances = */ 1,
7307 /* .uSharedVersion = */ 42,
7308 /* .cbInstanceShared = */ sizeof(IOMMU),
7309 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7310 /* .cbInstanceRC = */ sizeof(IOMMURC),
7311 /* .cMaxPciDevices = */ 1,
7312 /* .cMaxMsixVectors = */ 0,
7313 /* .pszDescription = */ "IOMMU (AMD)",
7314#if defined(IN_RING3)
7315 /* .pszRCMod = */ "VBoxDDRC.rc",
7316 /* .pszR0Mod = */ "VBoxDDR0.r0",
7317 /* .pfnConstruct = */ iommuAmdR3Construct,
7318 /* .pfnDestruct = */ iommuAmdR3Destruct,
7319 /* .pfnRelocate = */ NULL,
7320 /* .pfnMemSetup = */ NULL,
7321 /* .pfnPowerOn = */ NULL,
7322 /* .pfnReset = */ iommuAmdR3Reset,
7323 /* .pfnSuspend = */ NULL,
7324 /* .pfnResume = */ NULL,
7325 /* .pfnAttach = */ NULL,
7326 /* .pfnDetach = */ NULL,
7327 /* .pfnQueryInterface = */ NULL,
7328 /* .pfnInitComplete = */ NULL,
7329 /* .pfnPowerOff = */ NULL,
7330 /* .pfnSoftReset = */ NULL,
7331 /* .pfnReserved0 = */ NULL,
7332 /* .pfnReserved1 = */ NULL,
7333 /* .pfnReserved2 = */ NULL,
7334 /* .pfnReserved3 = */ NULL,
7335 /* .pfnReserved4 = */ NULL,
7336 /* .pfnReserved5 = */ NULL,
7337 /* .pfnReserved6 = */ NULL,
7338 /* .pfnReserved7 = */ NULL,
7339#elif defined(IN_RING0)
7340 /* .pfnEarlyConstruct = */ NULL,
7341 /* .pfnConstruct = */ iommuAmdRZConstruct,
7342 /* .pfnDestruct = */ NULL,
7343 /* .pfnFinalDestruct = */ NULL,
7344 /* .pfnRequest = */ NULL,
7345 /* .pfnReserved0 = */ NULL,
7346 /* .pfnReserved1 = */ NULL,
7347 /* .pfnReserved2 = */ NULL,
7348 /* .pfnReserved3 = */ NULL,
7349 /* .pfnReserved4 = */ NULL,
7350 /* .pfnReserved5 = */ NULL,
7351 /* .pfnReserved6 = */ NULL,
7352 /* .pfnReserved7 = */ NULL,
7353#elif defined(IN_RC)
7354 /* .pfnConstruct = */ iommuAmdRZConstruct,
7355 /* .pfnReserved0 = */ NULL,
7356 /* .pfnReserved1 = */ NULL,
7357 /* .pfnReserved2 = */ NULL,
7358 /* .pfnReserved3 = */ NULL,
7359 /* .pfnReserved4 = */ NULL,
7360 /* .pfnReserved5 = */ NULL,
7361 /* .pfnReserved6 = */ NULL,
7362 /* .pfnReserved7 = */ NULL,
7363#else
7364# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7365#endif
7366 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7367};
7368
7369#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7370
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