DevIommuAmd.cpp@ 83383

Last change on this file since 83383 was 83377, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 Bits.
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1	/* $Id: DevIommuAmd.cpp 83377 2020-03-24 07:56:05Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/vmm/pdmdev.h>
24
25	#include "VBoxDD.h"
26
27
28	/*********************************************************************************************************************************
29	* Defined Constants And Macros *
30	*********************************************************************************************************************************/
31	/**
32	* @name Commands.
33	* In accordance with the AMD spec.
34	* @{
35	*/
36	#define IOMMU_CMD_COMPLETION_WAIT 0x01
37	#define IOMMU_CMD_INV_DEVTAB_ENTRY 0x02
38	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
39	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
40	#define IOMMU_CMD_INV_INTR_TABLE 0x05
41	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
42	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
43	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
44	/** @} */
45
46	/**
47	* @name Event codes.
48	* In accordance with the AMD spec.
49	* @{
50	*/
51	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
52	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
53	#define IOMMU_EVT_DEV_TAB_HARDWARE_ERROR 0x03
54	#define IOMMU_EVT_PAGE_TAB_HARDWARE_ERROR 0x04
55	#define IOMMU_EVT_ILLEGAL_COMMAND_ERROR 0x05
56	#define IOMMU_EVT_COMMAND_HARDWARE_ERROR 0x06
57	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
58	#define IOMMU_EVT_INVALID_DEVICE_REQUEST 0x08
59	#define IOMMU_EVT_INVALID_PPR_REQUEST 0x09
60	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
61	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
62	/** @} */
63
64	/**
65	* @name Capability Header.
66	* In accordance with the AMD spec.
67	* @{
68	*/
69	/** CapId: Capability ID. */
70	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
71	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
72	/** CapPtr: Capability Pointer. */
73	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
74	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
75	/** CapType: Capability Type. */
76	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
77	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
78	/** CapRev: Capability Revision. */
79	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
80	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
81	/** IoTlbSup: IO TLB Support. */
82	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
83	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
84	/** HtTunnel: HyperTransport Tunnel translation support. */
85	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
86	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
87	/** NpCache: Not Present table entries Cached. */
88	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
89	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
90	/** EFRSup: Extended Feature Register (EFR) Supported. */
91	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
92	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
93	/** CapExt: Miscellaneous Information Register Supported . */
94	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
95	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
96	/** Bits 31:29 reserved. */
97	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
98	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
99	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
100	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
101	/** @} */
102
103	/**
104	* @name Base Address Low Register.
105	* In accordance with the AMD spec.
106	* @{
107	*/
108	/** Enable: Enables access to the address specified in the Base Address Register. */
109	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
110	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
111	/** Bits 13:1 reserved. */
112	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
113	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
114	/** Base Address[18:14]: Low Base address (Lo) of IOMMU control registers. */
115	#define IOMMU_BF_BASEADDR_LO_ADDR_LO_SHIFT 14
116	#define IOMMU_BF_BASEADDR_LO_ADDR_LO_MASK UINT32_C(0x0007c000)
117	/** Base Address[31:19]: Low Base address (Hi) of IOMMU control registers. */
118	#define IOMMU_BF_BASEADDR_LO_ADDR_HI_SHIFT 19
119	#define IOMMU_BF_BASEADDR_LO_ADDR_HI_MASK UINT32_C(0xfff80000)
120	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
121	(ENABLE, RSVD_1_13, ADDR_LO, ADDR_HI));
122	/** @} */
123
124	/**
125	* @name Range Register.
126	* In accordance with the AMD spec.
127	* @{
128	*/
129	/** UnitID: HyperTransport Unit ID. */
130	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
131	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
132	/** Bits 6:5 reserved. */
133	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
134	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
135	/** RngValid: Range valid. */
136	#define IOMMU_BF_RANGE_VALID_SHIFT 7
137	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
138	/** BusNumber: Device range bus number. */
139	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
140	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
141	/** First Device. */
142	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
143	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
144	/** Last Device. */
145	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
146	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
147	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
148	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
149	/** @} */
150
151	/**
152	* @name Miscellaneous Information Register 0.
153	* In accordance with the AMD spec.
154	* @{
155	*/
156	/** MsiNum: MSI message number. */
157	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
158	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
159	/** GvaSize: Guest Virtual Address Size. */
160	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
161	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
162	/** PaSize: Physical Address Size. */
163	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
164	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
165	/** VaSize: Virtual Address Size. */
166	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
167	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
168	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
169	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
170	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
171	/** Bits 26:23 reserved. */
172	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
173	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
174	/** MsiNumPPR: Peripheral Page Request MSI message number. */
175	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
176	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
177	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
178	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
179	/** @} */
180
181	/**
182	* @name Miscellaneous Information Register 1.
183	* In accordance with the AMD spec.
184	* @{
185	*/
186	/** MsiNumGA: MSI message number for guest vAPIC. */
187	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
188	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
189	/** Bits 31:5 reserved. */
190	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
191	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
192	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
193	(MSI_NUM_GA, RSVD_5_31));
194	/** @} */
195
196	/**
197	* @name MSI Capability Header Register.
198	* In accordance with the AMD spec.
199	* @{
200	*/
201	/** MsiCapId: Capability ID. */
202	#define IOMMU_BF_MSI_CAPHDR_CAP_ID_SHIFT 0
203	#define IOMMU_BF_MSI_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
204	/** MsiCapPtr: Pointer (PCI config offset) to the next capability register. */
205	#define IOMMU_BF_MSI_CAPHDR_CAP_PTR_SHIFT 8
206	#define IOMMU_BF_MSI_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
207	/** MsiEn: Message Signal Interrupt enable. */
208	#define IOMMU_BF_MSI_CAPHDR_EN_SHIFT 16
209	#define IOMMU_BF_MSI_CAPHDR_EN_MASK UINT32_C(0x00010000)
210	/** MsiMultMessCap: MSI Multi-Message Capability. */
211	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_CAP_SHIFT 17
212	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
213	/** MsiMultMessEn: MSI Mult-Message Enable. */
214	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_EN_SHIFT 20
215	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
216	/** Msi64BitEn: MSI 64-bit Enabled. */
217	#define IOMMU_BF_MSI_CAPHDR_64BIT_EN_SHIFT 23
218	#define IOMMU_BF_MSI_CAPHDR_64BIT_EN_MASK UINT32_C(0x00800000)
219	/** Bits 31:24 reserved. */
220	#define IOMMU_BF_MSI_CAPHDR_RSVD_24_31_SHIFT 24
221	#define IOMMU_BF_MSI_CAPHDR_RSVD_24_31_MASK UINT32_C(0xff000000)
222	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAPHDR_, UINT32_C(0), UINT32_MAX,
223	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
224	/** @} */
225
226	/**
227	* @name MSI Mapping Capability Header Register.
228	* In accordance with the AMD spec.
229	* @{
230	*/
231	/** MsiMapCapId: Capability ID. */
232	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
233	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
234	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability register. */
235	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
236	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
237	/** MsiMapEn: MSI mapping capability enable. */
238	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
239	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
240	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
241	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
242	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
243	/** Bits 18:28 reserved. */
244	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
245	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
246	/** MsiMapCapType: MSI mapping capability. */
247	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
248	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
249	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
250	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
251	/** @} */
252
253	/** @name Miscellaneous IOMMU defines.
254	* @{ */
255	#define IOMMU_LOG_PFX "AMD_IOMMU" /*< Log prefix string. /
256	#define IOMMU_PCI_VENDOR_ID 0x1022 /*< AMD's vendor ID. /
257	#define IOMMU_PCI_DEVICE_ID 0xc0de /*< VirtualBox IOMMU Device ID. /
258	#define IOMMU_PCI_REVISION_ID 0x01 /*< VirtualBox IOMMU Device Revision ID. /
259	/** @} */
260
261
262	/*********************************************************************************************************************************
263	* Structures and Typedefs *
264	*********************************************************************************************************************************/
265	/**
266	* The Device ID.
267	* In accordance with the AMD spec.
268	*/
269	typedef union
270	{
271	struct
272	{
273	uint16_t uFunction : 3; /*< Bits 2:0 - Function. /
274	uint16_t uDevice : 5; /*< Bits 7:3 - Device. /
275	uint16_t uBus : 8; /*< Bits 15:8 - Bus. /
276	} n;
277	/** The unsigned integer view. */
278	uint16_t u;
279	} DEVICE_ID_T;
280	AssertCompileSize(DEVICE_ID_T, 2);
281
282	/**
283	* Device Table Entry (DTE).
284	* In accordance with the AMD spec.
285	*/
286	typedef union
287	{
288	struct
289	{
290	uint32_t u1Valid : 1; /*< Bit 0 - V: Valid. /
291	uint32_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
292	uint32_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
293	uint32_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
294	uint32_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
295	uint32_t u20PageTableRootPtrLo : 20; /*< Bits 31:12 - Page Table Root Pointer (Lo). /
296	uint32_t u20PageTableRootPtrHi : 20; /*< Bits 51:32 - Page Table Root Pointer (Hi). /
297	uint32_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
298	uint32_t u1Grpr : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
299	uint32_t u1GIov : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
300	uint32_t u1GValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
301	uint32_t u2Glx : 2; /*< Bits 57:56 - GLX: Guest Levels Translated. /
302	uint32_t u3GCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Pointer (Lo). /
303	uint32_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
304	uint32_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
305	uint32_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
306	uint32_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
307	uint32_t u16GCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Pointer (Mid). /
308	uint32_t u1IotlbEnable : 1; /*< Bit 96 - IOTLB Enable. /
309	uint32_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
310	uint32_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
311	uint32_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
312	uint32_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
313	uint32_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
314	uint32_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
315	uint32_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
316	uint32_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
317	uint32_t u21Gcr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Pointer (Hi). /
318	uint32_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
319	uint32_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
320	uint32_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
321	uint32_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
322	uint32_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
323	uint32_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
324	uint32_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
325	uint32_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
326	uint32_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
327	uint32_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
328	uint32_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
329	uint32_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 (Legacy PIC NMI) Pass-thru. /
330	uint32_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 (Legacy PIC NMI) Pass-thru. /
331	uint32_t u32Rsvd0; /*< Bits 223:192 - Reserved. /
332	uint32_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
333	uint32_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
334	uint32_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
335	uint32_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
336	} n;
337	/** The 32-bit unsigned integer view. */
338	uint32_t au32[8];
339	} DEV_TAB_ENTRY_T;
340	AssertCompileSize(DEV_TAB_ENTRY_T, 32);
341
342	/**
343	* I/O Page Table Entry.
344	* In accordance with the AMD spec.
345	*/
346	typedef union
347	{
348	struct
349	{
350	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
351	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
352	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
353	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
354	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
355	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
356	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
357	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
358	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
359	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
360	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
361	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
362	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
363	} n;
364	/** The 64-bit unsigned integer view. */
365	uint64_t u;
366	} IOPTE_T;
367	AssertCompileSize(IOPTE_T, 8);
368
369	/**
370	* I/O Page Directory Entry.
371	* In accordance with the AMD spec.
372	*/
373	typedef union
374	{
375	struct
376	{
377	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
378	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
379	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
380	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
381	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
382	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
383	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
384	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
385	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
386	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
387	} n;
388	/** The 64-bit unsigned integer view. */
389	uint64_t u;
390	} IOPDE_T;
391	AssertCompileSize(IOPDE_T, 8);
392
393	/**
394	* Interrupt Remapping Table Entry.
395	* In accordance with the AMD spec.
396	*/
397	typedef union
398	{
399	struct
400	{
401	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap enable. /
402	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
403	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
404	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
405	uint32_t u1DstMode : 1; /*< Bit 6 - DM: Destination Mode. /
406	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
407	uint32_t u8Dst : 8; /*< Bits 15:8 - Destination. /
408	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
409	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
410	} n;
411	/** The 32-bit unsigned integer view. */
412	uint32_t u;
413	} IRTE_T;
414	AssertCompileSize(IRTE_T, 4);
415
416	/**
417	* Command: Generic Command Buffer Entry.
418	* In accordance with the AMD spec.
419	*/
420	typedef union
421	{
422	struct
423	{
424	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
425	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
426	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
427	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
428	} n;
429	/** The 64-bit unsigned integer view. */
430	uint64_t au64[2];
431	} CMD_GENERIC_T;
432	AssertCompileSize(CMD_GENERIC_T, 16);
433
434	/**
435	* Command: COMPLETION_WAIT.
436	* In accordance with the AMD spec.
437	*/
438	typedef union
439	{
440	struct
441	{
442	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
443	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
444	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
445	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
446	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
447	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
448	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
449	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
450	} n;
451	/** The 64-bit unsigned integer view. */
452	uint32_t au64[2];
453	} CMD_COMPLETION_WAIT_T;
454	AssertCompileSize(CMD_COMPLETION_WAIT_T, 16);
455
456	/**
457	* Command: INVALIDATE_DEVTAB_ENTRY.
458	* In accordance with the AMD spec.
459	*/
460	typedef union
461	{
462	struct
463	{
464	uint16_t u16DeviceId; /*< Bits 15:0 - DeviceID. /
465	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
466	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
467	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
468	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
469	} n;
470	/** The 64-bit unsigned integer view. */
471	uint64_t au64[2];
472	} CMD_INV_DEV_TAB_ENTRY_T;
473	AssertCompileSize(CMD_INV_DEV_TAB_ENTRY_T, 16);
474
475	/**
476	* Command: INVALIDATE_IOMMU_PAGES.
477	* In accordance with the AMD spec.
478	*/
479	typedef union
480	{
481	struct
482	{
483	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
484	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
485	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
486	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
487	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
488	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
489	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
490	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
491	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
492	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
493	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
494	} n;
495	/** The 64-bit unsigned integer view. */
496	uint64_t au64[2];
497	} CMD_INV_IOMMU_PAGES_T;
498	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
499
500	/**
501	* Command: INVALIDATE_IOTLB_PAGES.
502	* In accordance with the AMD spec.
503	*/
504	typedef union
505	{
506	struct
507	{
508	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
509	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
510	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
511	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
512	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
513	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
514	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
515	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
516	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
517	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
518	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
519	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
520	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
521	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
522	} n;
523	/** The 64-bit unsigned integer view. */
524	uint64_t au64[2];
525	} CMD_INV_IOTLB_PAGES_T;
526	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
527
528	/**
529	* Command: INVALIDATE_INTR_TABLE.
530	* In accordance with the AMD spec.
531	*/
532	typedef union
533	{
534	struct
535	{
536	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
537	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
538	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
539	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
540	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
541	} u;
542	/** The 64-bit unsigned integer view. */
543	uint64_t au64[2];
544	} CMD_INV_INTR_TABLE_T;
545	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
546
547	/**
548	* Command: COMPLETE_PPR_REQ.
549	* In accordance with the AMD spec.
550	*/
551	typedef union
552	{
553	struct
554	{
555	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
556	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
557	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
558	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
559	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
560	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
561	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
562	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
563	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
564	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
565	} n;
566	/** The 64-bit unsigned integer view. */
567	uint64_t au64[2];
568	} CMD_COMPLETE_PPR_REQ_T;
569	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
570
571	/**
572	* Command: INV_IOMMU_ALL.
573	* In accordance with the AMD spec.
574	*/
575	typedef union
576	{
577	struct
578	{
579	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
580	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
581	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
582	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
583	} n;
584	/** The 64-bit unsigned integer view. */
585	uint64_t au64[2];
586	} CMD_IOMMU_ALL_T;
587	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
588
589	/**
590	* Event Log Entry: Generic.
591	* In accordance with the AMD spec.
592	*/
593	typedef union
594	{
595	struct
596	{
597	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
598	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
599	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
600	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
601	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
602	} n;
603	/** The 32-bit unsigned integer view. */
604	uint32_t au32[4];
605	} EVT_GENERIC_T;
606	AssertCompileSize(EVT_GENERIC_T, 16);
607
608	/**
609	* Event Log Entry: ILLEGAL_DEV_TAB_ENTRY.
610	* In accordance with the AMD spec.
611	*/
612	typedef union
613	{
614	struct
615	{
616	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
617	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
618	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
619	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
620	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
621	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
622	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
623	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
624	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
625	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
626	uint16_t u1RsvdZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. /
627	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
628	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
629	uint16_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
630	uint32_t u2Rsvd1 : 2; /*< Bits 65:64 - Reserved. /
631	uint32_t u30AddrLo : 2; /*< Bits 95:66 - Address: Device Virtual Address (Lo). /
632	uint32_t u30AddrHi; /*< Bits 127:96 - Address: Device Virtual Address (Hi). /
633	} n;
634	/** The 32-bit unsigned integer view. */
635	uint32_t au32[4];
636	} EVT_ILLEGAL_DEV_TAB_ENTRY_T;
637	AssertCompileSize(EVT_ILLEGAL_DEV_TAB_ENTRY_T, 16);
638
639	/**
640	* Event Log Entry: IO_PAGE_FAULT_EVENT.
641	* In accordance with the AMD spec.
642	*/
643	typedef union
644	{
645	struct
646	{
647	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
648	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
649	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
650	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
651	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
652	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
653	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
654	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
655	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
656	uint16_t u1Perm : 1; /*< Bit 54 - PE: Permission Indicator. /
657	uint16_t u1RsvdZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. /
658	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
659	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
660	uint16_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
661	uint64_t u64Addr; /*< Bits 127:64 - Address: Device Virtual Address. /
662	} n;
663	/** The 32-bit unsigned integer view. */
664	uint32_t au32[4];
665	} EVT_IO_PAGE_FAULT_T;
666	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
667
668	/**
669	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
670	* In accordance with the AMD spec.
671	*/
672	typedef union
673	{
674	struct
675	{
676	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
677	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
678	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
679	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt. /
680	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
681	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
682	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
683	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
684	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
685	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
686	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
687	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
688	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: System Physical Address (Lo). /
689	uint32_t u32AddrHi; /*< Bits 127:96 - Address: System Physical Address (Hi). /
690	} n;
691	/** The 32-bit unsigned integer view. */
692	uint32_t au32[4];
693	} EVT_DEV_TAB_HARDWARE_ERROR;
694	AssertCompileSize(EVT_DEV_TAB_HARDWARE_ERROR, 16);
695
696	/**
697	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
698	* In accordance with the AMD spec.
699	*/
700	typedef union
701	{
702	struct
703	{
704	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
705	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
706	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
707	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
708	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
709	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
710	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
711	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
712	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
713	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
714	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
715	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
716	uint32_t u4EventCode : 4; /*< Bit 63:60 - Event code. /
717	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
718	* table 58 mentions Addr[31:4]. Looks like a typo in the figure. Use
719	* table as it makes more sense and matches address size in
720	* EVT_DEV_TAB_HARDWARE_ERROR. See AMD AMD IOMMU spec (3.05-PUB, Jan
721	* 2020). */
722	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
723	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of page table entry (Lo). /
724	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of page table entry (Hi). /
725	} n;
726	/** The 32-bit unsigned integer view. */
727	uint32_t au32[4];
728	} EVT_PAGE_TAB_HARDWARE_ERROR;
729	AssertCompileSize(EVT_PAGE_TAB_HARDWARE_ERROR, 16);
730
731	/**
732	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
733	* In accordance with the AMD spec.
734	*/
735	typedef union
736	{
737	struct
738	{
739	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
740	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
741	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
742	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
743	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalid command (Lo). /
744	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalid command (Hi). /
745	} n;
746	/** The 32-bit unsigned integer view. */
747	uint32_t au32[4];
748	} EVT_ILLEGAL_COMMAND_ENTRY;
749	AssertCompileSize(EVT_ILLEGAL_COMMAND_ENTRY, 16);
750
751	/**
752	* Event Log Entry: COMMAND_HARDWARE_ERROR.
753	* In accordance with the AMD spec.
754	*/
755	typedef union
756	{
757	struct
758	{
759	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
760	uint32_t u4Rsvd0 : 4; /*< Bits 35:32 - Reserved. /
761	uint32_t u28AddrLo : 28; /*< Bits 63:36 - Address: SPA of the attempted access (Lo). /
762	uint32_t u32AddrHi; /*< Bits 95:64 - Address: SPA of the attempted access (Hi). /
763	} n;
764	/** The 32-bit unsigned integer view. */
765	uint32_t au32[3];
766	} EVT_COMMAND_HARDWARE_ERROR;
767	AssertCompileSize(EVT_COMMAND_HARDWARE_ERROR, 12);
768
769	/**
770	* Event Log Entry: IOTLB_INV_TIMEOUT.
771	* In accordance with the AMD spec.
772	*/
773	typedef union
774	{
775	struct
776	{
777	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
778	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
779	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
780	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
781	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
782	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
783	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
784	} n;
785	/** The 32-bit unsigned integer view. */
786	uint32_t au32[4];
787	} EVT_IOTLB_INV_TIMEOUT;
788	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT, 16);
789
790	/**
791	* Event Log Entry: INVALID_DEVICE_REQUEST.
792	* In accordance with the AMD spec.
793	*/
794	typedef union
795	{
796	struct
797	{
798	uint32_t u16DeviceId : 16; /**< Bits 15:0 - Device ID. /
799	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
800	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
801	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
802	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
803	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
804	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
805	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
806	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
807	uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. /
808	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
809	} n;
810	/** The 32-bit unsigned integer view. */
811	uint32_t au32[4];
812	} EVT_INVALID_DEVICE_REQUEST;
813	AssertCompileSize(EVT_INVALID_DEVICE_REQUEST, 16);
814
815	/**
816	* Event Log Entry: EVENT_COUNTER_ZERO.
817	* In accordance with the AMD spec.
818	*/
819	typedef union
820	{
821	struct
822	{
823	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
824	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
825	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
826	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
827	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
828	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
829	} n;
830	/** The 32-bit unsigned integer view. */
831	uint32_t au32[4];
832	} EVT_EVENT_COUNTER_ZERO;
833	AssertCompileSize(EVT_EVENT_COUNTER_ZERO, 16);
834
835
836	/**
837	* The IOMMU device state.
838	*/
839	typedef struct IOMMU
840	{
841	bool fRootComplex;
842	} IOMMU;
843	/** Pointer to the IOMMU device state. */
844	typedef struct IOMMU *PIOMMU;
845
846	/**
847	* The ring-3 IOMMU device state.
848	*/
849	typedef struct IOMMUR3
850	{
851	/** The IOMMU helpers. */
852	PCPDMIOMMUHLPR3 pIommuHlp;
853	} IOMMUR3;
854	/** Pointer to the ring-3 IOMMU device state. */
855	typedef IOMMUR3 *PIOMMUR3;
856
857	/**
858	* The ring-0 IOMMU device state.
859	*/
860	typedef struct IOMMUR0
861	{
862	/** The IOMMU helpers. */
863	PCPDMIOMMUHLPR0 pIommuHlp;
864	} IOMMUR0;
865	/** Pointer to the ring-0 IOMMU device state. */
866	typedef IOMMUR0 *PIOMMUR0;
867
868	/**
869	* The raw-mode IOMMU device state.
870	*/
871	typedef struct IOMMURC
872	{
873	/** The IOMMU helpers. */
874	PCPDMIOMMUHLPRC pIommuHlp;
875	} IOMMURC;
876	/** Pointer to the raw-mode IOMMU device state. */
877	typedef IOMMURC *PIOMMURC;
878
879	/** The IOMMU device state for the current context. */
880	typedef CTX_SUFF(IOMMU) IOMMUCC;
881	/** Pointer to the IOMMU device state for the current context. */
882	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
883
884
885	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
886
887	# ifdef IN_RING3
888	/**
889	* @interface_method_impl{PDMDEVREG,pfnReset}
890	*/
891	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
892	{
893	NOREF(pDevIns);
894	}
895
896
897	/**
898	* @interface_method_impl{PDMDEVREG,pfnDestruct}
899	*/
900	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
901	{
902	NOREF(pDevIns);
903	return VINF_SUCCESS;
904	}
905
906
907	/**
908	* @interface_method_impl{PDMDEVREG,pfnConstruct}
909	*/
910	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
911	{
912	NOREF(iInstance);
913	NOREF(pCfg);
914
915	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
916	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
917	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
918	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
919	int rc;
920	LogFlowFunc(("\n"));
921
922	NOREF(pThisCC); /** @todo IOMMU: populate CC data. */
923
924	/*
925	* Validate and read the configuration.
926	*/
927	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RootComplex", "");
928
929	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RootComplex", &pThis->fRootComplex, true);
930	AssertLogRelRCReturn(rc, rc);
931
932	/*
933	* Initialize the PCI configuration space.
934	*/
935	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
936	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
937
938	uint8_t const offCapHdr = 0x40;
939	uint8_t const offBaseAddrLo = offCapHdr + 0x4;
940	uint8_t const offBaseAddrHi = offCapHdr + 0x8;
941	uint8_t const offRange = offCapHdr + 0xc;
942	uint8_t const offMiscInfo0 = offCapHdr + 0x10;
943	uint8_t const offMiscInfo1 = offCapHdr + 0x14;
944	uint8_t const offMsiCapHdr = offCapHdr + 0x24;
945	uint8_t const offMsiMapCapHdr = offCapHdr + 0x34;
946
947	/* Header. */
948	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* RO - AMD */
949	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* RO - VirtualBox IOMMU device */
950	PDMPciDevSetCommand(pPciDev, 0); /* RW - Command */
951	PDMPciDevSetStatus(pPciDev, 0x5); /* RW - Status - CapList supported */
952	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* RO - VirtualBox specific device implementation revision */
953	PDMPciDevSetClassBase(pPciDev, 0x08); /* RO - System Base Peripheral */
954	PDMPciDevSetClassSub(pPciDev, 0x06); /* RO - IOMMU */
955	PDMPciDevSetClassProg(pPciDev, 0x00); /* RO - IOMMU Programming interface */
956	PDMPciDevSetHeaderType(pPciDev, 0x00); /* RO - Single function, type 0. */
957	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* RO - AMD */
958	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* RO - VirtualBox IOMMU device */
959	PDMPciDevSetCapabilityList(pPciDev, offCapHdr); /* RO - Offset into capability registers. */
960	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* RO - INTA#. */
961	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* RW - For software compatibility; no effect on hardware. */
962
963	/* Capability Header. */
964	PDMPciDevSetDWord(pPciDev, offCapHdr,
965	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
966	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, offMsiCapHdr) /* RO - Offset to next capability block */
967	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
968	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
969	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
970	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
971	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache Not-present page table entries */
972	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
973	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
974
975	/* Base Address Low Register. */
976	PDMPciDevSetDWord(pPciDev, offBaseAddrLo,
977	RT_BF_MAKE(IOMMU_BF_BASEADDR_LO_ENABLE, 0x0) /* RW - Enable */
978	\| RT_BF_MAKE(IOMMU_BF_BASEADDR_LO_ADDR_LO, 0x0) /* RW - Base address low (lo) */
979	\| RT_BF_MAKE(IOMMU_BF_BASEADDR_LO_ADDR_HI, 0x0)); /* RW - Base address low (hi) */
980
981	/* Base Address High Register. */
982	PDMPciDevSetDWord(pPciDev, offBaseAddrHi, 0); /* RW - Base address high */
983
984	/* IOMMU Range Register. */
985	PDMPciDevSetDWord(pPciDev, offRange,
986	RT_BF_MAKE(IOMMU_BF_RANGE_UNIT_ID, 0x0) /* RO - HyperTransport Unit ID */
987	\| RT_BF_MAKE(IOMMU_BF_RANGE_VALID, 0x0) /* RW - Range Valid */
988	\| RT_BF_MAKE(IOMMU_BF_RANGE_BUS_NUMBER, 0x0) /* RO - Bus number */
989	\| RT_BF_MAKE(IOMMU_BF_RANGE_FIRST_DEVICE, 0x0) /* RO - First device */
990	\| RT_BF_MAKE(IOMMU_BF_RANGE_LAST_DEVICE, 0x0)); /* RO - Last device */
991
992	/* Misc. Information Register 0. */
993	PDMPciDevSetDWord(pPciDev, offMiscInfo0,
994	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
995	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
996	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
997	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
998	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
999	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
1000
1001	/* Misc. Information Register 1. */
1002	PDMPciDevSetDWord(pPciDev, offMiscInfo1, 0);
1003
1004	/* MSI Capability Header register. */
1005	PDMPciDevSetDWord(pPciDev, offMsiCapHdr,
1006	RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_CAP_ID, 0x5) /* RO - Capability ID. */
1007	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_CAP_PTR, offMsiMapCapHdr) /* RO - Offset to mapping capability block */
1008	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_EN, 0x0) /* RW - MSI capability enable */
1009	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_MULTMESS_CAP, 0x0) /* RO - MSI multi-message capability */
1010	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_MULTMESS_EN, 0x0) /* RW - MSI multi-message enable */
1011	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_64BIT_EN, 0x1)); /* RO - MSI 64-bit enable */
1012
1013	/* MSI Mapping Capability header register. */
1014	PDMPciDevSetDWord(pPciDev, offMsiMapCapHdr,
1015	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
1016	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
1017	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
1018	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
1019	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
1020
1021	return VINF_SUCCESS;
1022	}
1023
1024	# else /* !IN_RING3 */
1025
1026	/**
1027	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1028	*/
1029	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
1030	{
1031	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1032	return VINF_SUCCESS;
1033	}
1034
1035	# endif /* !IN_RING3 */
1036
1037	/**
1038	* The device registration structure.
1039	*/
1040	const PDMDEVREG g_DeviceIommuAmd =
1041	{
1042	/* .u32Version = */ PDM_DEVREG_VERSION,
1043	/* .uReserved0 = */ 0,
1044	/* .szName = */ "iommu-amd",
1045	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1046	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
1047	/* .cMaxInstances = */ ~0U,
1048	/* .uSharedVersion = */ 42,
1049	/* .cbInstanceShared = */ sizeof(IOMMU),
1050	/* .cbInstanceCC = */ sizeof(IOMMUCC),
1051	/* .cbInstanceRC = */ sizeof(IOMMURC),
1052	/* .cMaxPciDevices = */ 1,
1053	/* .cMaxMsixVectors = */ 0,
1054	/* .pszDescription = */ "IOMMU (AMD)",
1055	#if defined(IN_RING3)
1056	/* .pszRCMod = */ "VBoxDDRC.rc",
1057	/* .pszR0Mod = */ "VBoxDDR0.r0",
1058	/* .pfnConstruct = */ iommuAmdR3Construct,
1059	/* .pfnDestruct = */ iommuAmdR3Destruct,
1060	/* .pfnRelocate = */ NULL,
1061	/* .pfnMemSetup = */ NULL,
1062	/* .pfnPowerOn = */ NULL,
1063	/* .pfnReset = */ iommuAmdR3Reset,
1064	/* .pfnSuspend = */ NULL,
1065	/* .pfnResume = */ NULL,
1066	/* .pfnAttach = */ NULL,
1067	/* .pfnDetach = */ NULL,
1068	/* .pfnQueryInterface = */ NULL,
1069	/* .pfnInitComplete = */ NULL,
1070	/* .pfnPowerOff = */ NULL,
1071	/* .pfnSoftReset = */ NULL,
1072	/* .pfnReserved0 = */ NULL,
1073	/* .pfnReserved1 = */ NULL,
1074	/* .pfnReserved2 = */ NULL,
1075	/* .pfnReserved3 = */ NULL,
1076	/* .pfnReserved4 = */ NULL,
1077	/* .pfnReserved5 = */ NULL,
1078	/* .pfnReserved6 = */ NULL,
1079	/* .pfnReserved7 = */ NULL,
1080	#elif defined(IN_RING0)
1081	/* .pfnEarlyConstruct = */ NULL,
1082	/* .pfnConstruct = */ iommuAmdRZConstruct,
1083	/* .pfnDestruct = */ NULL,
1084	/* .pfnFinalDestruct = */ NULL,
1085	/* .pfnRequest = */ NULL,
1086	/* .pfnReserved0 = */ NULL,
1087	/* .pfnReserved1 = */ NULL,
1088	/* .pfnReserved2 = */ NULL,
1089	/* .pfnReserved3 = */ NULL,
1090	/* .pfnReserved4 = */ NULL,
1091	/* .pfnReserved5 = */ NULL,
1092	/* .pfnReserved6 = */ NULL,
1093	/* .pfnReserved7 = */ NULL,
1094	#elif defined(IN_RC)
1095	/* .pfnConstruct = */ iommuAmdRZConstruct,
1096	/* .pfnReserved0 = */ NULL,
1097	/* .pfnReserved1 = */ NULL,
1098	/* .pfnReserved2 = */ NULL,
1099	/* .pfnReserved3 = */ NULL,
1100	/* .pfnReserved4 = */ NULL,
1101	/* .pfnReserved5 = */ NULL,
1102	/* .pfnReserved6 = */ NULL,
1103	/* .pfnReserved7 = */ NULL,
1104	#else
1105	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1106	#endif
1107	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1108	};
1109
1110	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1111

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 83383

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