VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86679

Last change on this file since 86679 was 86662, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Doxygen fix.
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1/* $Id: DevIommuAmd.cpp 86662 2020-10-21 12:02:38Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31
32#include "VBoxDD.h"
33#include "DevIommuAmd.h"
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** Release log prefix string. */
40#define IOMMU_LOG_PFX "AMD-IOMMU"
41/** The current saved state version. */
42#define IOMMU_SAVED_STATE_VERSION 1
43/** The IOTLB entry magic. */
44#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46#ifndef DEBUG_ramshankar
47/** Temporary, make permanent later (get rid of define entirely and remove old
48 * code). This allow ssub-qword accesses to qword registers. Write accesses
49 * seems to work (needs testing one sub-path of the code), Read accesses not yet
50 * converted. */
51# define IOMMU_NEW_REGISTER_ACCESS
52#endif
53
54
55/*********************************************************************************************************************************
56* Structures and Typedefs *
57*********************************************************************************************************************************/
58/**
59 * Acquires the IOMMU PDM lock.
60 * This will make a long jump to ring-3 to acquire the lock if necessary.
61 */
62#define IOMMU_LOCK(a_pDevIns) \
63 do { \
64 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
65 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
66 { /* likely */ } \
67 else \
68 return rcLock; \
69 } while (0)
70
71/**
72 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
73 * This will make a long jump to ring-3 to acquire the lock if necessary.
74 */
75#define IOMMU_LOCK_NORET(a_pDevIns) \
76 do { \
77 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
78 AssertRC(rcLock); \
79 } while (0)
80
81/**
82 * Releases the IOMMU PDM lock.
83 */
84#define IOMMU_UNLOCK(a_pDevIns) \
85 do { \
86 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
87 } while (0)
88
89/**
90 * Asserts that the critsect is owned by this thread.
91 */
92#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
93 do { \
94 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95 } while (0)
96
97/**
98 * Asserts that the critsect is not owned by this thread.
99 */
100#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
101 do { \
102 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
103 } while (0)
104
105/**
106 * IOMMU operations (transaction) types.
107 */
108typedef enum IOMMUOP
109{
110 /** Address translation request. */
111 IOMMUOP_TRANSLATE_REQ = 0,
112 /** Memory read request. */
113 IOMMUOP_MEM_READ,
114 /** Memory write request. */
115 IOMMUOP_MEM_WRITE,
116 /** Interrupt request. */
117 IOMMUOP_INTR_REQ,
118 /** Command. */
119 IOMMUOP_CMD
120} IOMMUOP;
121AssertCompileSize(IOMMUOP, 4);
122
123/**
124 * I/O page walk result.
125 */
126typedef struct
127{
128 /** The translated system physical address. */
129 RTGCPHYS GCPhysSpa;
130 /** The number of offset bits in the system physical address. */
131 uint8_t cShift;
132 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
133 uint8_t fIoPerm;
134 /** Padding. */
135 uint8_t abPadding[2];
136} IOWALKRESULT;
137/** Pointer to an I/O walk result struct. */
138typedef IOWALKRESULT *PIOWALKRESULT;
139/** Pointer to a const I/O walk result struct. */
140typedef IOWALKRESULT *PCIOWALKRESULT;
141
142/**
143 * IOMMU I/O TLB Entry.
144 * Keep this as small and aligned as possible.
145 */
146typedef struct
147{
148 /** The translated system physical address (SPA) of the page. */
149 RTGCPHYS GCPhysSpa;
150 /** The index of the 4K page within a large page. */
151 uint32_t idxSubPage;
152 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
153 uint8_t fIoPerm;
154 /** The number of offset bits in the translation indicating page size. */
155 uint8_t cShift;
156 /** Alignment padding. */
157 uint8_t afPadding[2];
158} IOTLBE_T;
159AssertCompileSize(IOTLBE_T, 16);
160/** Pointer to an IOMMU I/O TLB entry struct. */
161typedef IOTLBE_T *PIOTLBE_T;
162/** Pointer to a const IOMMU I/O TLB entry struct. */
163typedef IOTLBE_T const *PCIOTLBE_T;
164
165/**
166 * The shared IOMMU device state.
167 */
168typedef struct IOMMU
169{
170 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
171 uint32_t idxIommu;
172 /** Alignment padding. */
173 uint32_t uPadding0;
174
175 /** Whether the command thread is sleeping. */
176 bool volatile fCmdThreadSleeping;
177 /** Alignment padding. */
178 uint8_t afPadding0[3];
179 /** Whether the command thread has been signaled for wake up. */
180 bool volatile fCmdThreadSignaled;
181 /** Alignment padding. */
182 uint8_t afPadding1[3];
183
184 /** The event semaphore the command thread waits on. */
185 SUPSEMEVENT hEvtCmdThread;
186 /** The MMIO handle. */
187 IOMMMIOHANDLE hMmio;
188
189 /** @name PCI: Base capability block registers.
190 * @{ */
191 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
192 /** @} */
193
194 /** @name MMIO: Control and status registers.
195 * @{ */
196 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
197 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
198 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
199 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
200 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
201 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
202 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
203 /** @} */
204
205 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
206 * @{ */
207 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
208 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
209 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
210 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
211 /** @} */
212
213 /** @todo IOMMU: SMI filter. */
214
215 /** @name MMIO: Guest Virtual-APIC Log registers.
216 * @{ */
217 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
218 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
219 /** @} */
220
221 /** @name MMIO: Alternate PPR and Event Log registers.
222 * @{ */
223 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
224 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
225 /** @} */
226
227 /** @name MMIO: Device-specific feature registers.
228 * @{ */
229 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
230 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
231 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
232 /** @} */
233
234 /** @name MMIO: MSI Capability Block registers.
235 * @{ */
236 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
237 /** @} */
238
239 /** @name MMIO: Performance Optimization Control registers.
240 * @{ */
241 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
242 /** @} */
243
244 /** @name MMIO: x2APIC Control registers.
245 * @{ */
246 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
247 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
248 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
249 /** @} */
250
251 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
252 * @{ */
253 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
254 /** @} */
255
256 /** @name MMIO: Reserved register.
257 * @{ */
258 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
259 /** @} */
260
261 /** @name MMIO: Command and Event Log pointer registers.
262 * @{ */
263 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
264 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
265 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
266 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
267 /** @} */
268
269 /** @name MMIO: Command and Event Status register.
270 * @{ */
271 IOMMU_STATUS_T Status; /**< IOMMU status register. */
272 /** @} */
273
274 /** @name MMIO: PPR Log Head and Tail pointer registers.
275 * @{ */
276 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
277 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
278 /** @} */
279
280 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
281 * @{ */
282 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
283 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
284 /** @} */
285
286 /** @name MMIO: PPR Log B Head and Tail pointer registers.
287 * @{ */
288 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
289 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
290 /** @} */
291
292 /** @name MMIO: Event Log B Head and Tail pointer registers.
293 * @{ */
294 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
295 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
296 /** @} */
297
298 /** @name MMIO: PPR Log Overflow protection registers.
299 * @{ */
300 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
301 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
302 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
303 /** @} */
304
305 /** @todo IOMMU: IOMMU Event counter registers. */
306
307#ifdef VBOX_WITH_STATISTICS
308 /** @name IOMMU: Stat counters.
309 * @{ */
310 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
311 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
312
313 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
314 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
315
316 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
317 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
318
319 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
320 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
321 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
322 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
323
324 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
325 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
326
327 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory read bulk translation requests in R3. */
328 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory read bulk translation requests in RZ. */
329
330 STAMCOUNTER StatCmd; /**< Number of commands processed. */
331 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
332 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
333 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
334 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
335 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
336 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
337 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
338 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
339 /** @} */
340#endif
341} IOMMU;
342/** Pointer to the IOMMU device state. */
343typedef struct IOMMU *PIOMMU;
344/** Pointer to the const IOMMU device state. */
345typedef const struct IOMMU *PCIOMMU;
346AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
347AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
348AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
349AssertCompileMemberAlignment(IOMMU, hMmio, 8);
350AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
351
352/**
353 * The ring-3 IOMMU device state.
354 */
355typedef struct IOMMUR3
356{
357 /** Device instance. */
358 PPDMDEVINSR3 pDevInsR3;
359 /** The IOMMU helpers. */
360 PCPDMIOMMUHLPR3 pIommuHlpR3;
361 /** The command thread handle. */
362 R3PTRTYPE(PPDMTHREAD) pCmdThread;
363} IOMMUR3;
364/** Pointer to the ring-3 IOMMU device state. */
365typedef IOMMUR3 *PIOMMUR3;
366
367/**
368 * The ring-0 IOMMU device state.
369 */
370typedef struct IOMMUR0
371{
372 /** Device instance. */
373 PPDMDEVINSR0 pDevInsR0;
374 /** The IOMMU helpers. */
375 PCPDMIOMMUHLPR0 pIommuHlpR0;
376} IOMMUR0;
377/** Pointer to the ring-0 IOMMU device state. */
378typedef IOMMUR0 *PIOMMUR0;
379
380/**
381 * The raw-mode IOMMU device state.
382 */
383typedef struct IOMMURC
384{
385 /** Device instance. */
386 PPDMDEVINSR0 pDevInsRC;
387 /** The IOMMU helpers. */
388 PCPDMIOMMUHLPRC pIommuHlpRC;
389} IOMMURC;
390/** Pointer to the raw-mode IOMMU device state. */
391typedef IOMMURC *PIOMMURC;
392
393/** The IOMMU device state for the current context. */
394typedef CTX_SUFF(IOMMU) IOMMUCC;
395/** Pointer to the IOMMU device state for the current context. */
396typedef CTX_SUFF(PIOMMU) PIOMMUCC;
397
398/**
399 * IOMMU register access.
400 */
401typedef struct IOMMUREGACC
402{
403 const char *pszName;
404 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
405 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
406} IOMMUREGACC;
407/** Pointer to an IOMMU register access. */
408typedef IOMMUREGACC *PIOMMUREGACC;
409/** Pointer to a const IOMMU register access. */
410typedef IOMMUREGACC const *PCIOMMUREGACC;
411
412
413/*********************************************************************************************************************************
414* Global Variables *
415*********************************************************************************************************************************/
416/**
417 * An array of the number of device table segments supported.
418 * Indexed by u2DevTabSegSup.
419 */
420static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
421
422/**
423 * An array of the masks to select the device table segment index from a device ID.
424 */
425static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
426
427/**
428 * An array of the shift values to select the device table segment index from a
429 * device ID.
430 */
431static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
432
433/**
434 * The maximum size (inclusive) of each device table segment (0 to 7).
435 * Indexed by the device table segment index.
436 */
437static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
438
439
440#ifndef VBOX_DEVICE_STRUCT_TESTCASE
441/**
442 * Gets the maximum number of buffer entries for the given buffer length.
443 *
444 * @returns Number of buffer entries.
445 * @param uEncodedLen The length (power-of-2 encoded).
446 */
447DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
448{
449 Assert(uEncodedLen > 7);
450 return 2 << (uEncodedLen - 1);
451}
452
453
454/**
455 * Gets the total length of the buffer given a base register's encoded length.
456 *
457 * @returns The length of the buffer in bytes.
458 * @param uEncodedLen The length (power-of-2 encoded).
459 */
460DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
461{
462 Assert(uEncodedLen > 7);
463 return (2 << (uEncodedLen - 1)) << 4;
464}
465
466
467/**
468 * Gets the number of (unconsumed) entries in the event log.
469 *
470 * @returns The number of entries in the event log.
471 * @param pThis The IOMMU device state.
472 */
473static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
474{
475 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
476 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
477 if (idxTail >= idxHead)
478 return idxTail - idxHead;
479
480 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
481 return cMaxEvts - idxHead + idxTail;
482}
483
484
485#if 0
486/**
487 * Gets the number of (unconsumed) commands in the command buffer.
488 *
489 * @returns The number of commands in the command buffer.
490 * @param pThis The IOMMU device state.
491 */
492static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
493{
494 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
495 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
496 if (idxTail >= idxHead)
497 return idxTail - idxHead;
498
499 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
500 return cMaxCmds - idxHead + idxTail;
501}
502#endif
503
504
505DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
506{
507 IOMMU_STATUS_T Status;
508 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
509 return Status;
510}
511
512
513DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
514{
515 IOMMU_CTRL_T Ctrl;
516 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
517 return Ctrl;
518}
519
520
521/**
522 * Returns whether MSI is enabled for the IOMMU.
523 *
524 * @returns Whether MSI is enabled.
525 * @param pDevIns The IOMMU device instance.
526 *
527 * @note There should be a PCIDevXxx function for this.
528 */
529static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
530{
531 MSI_CAP_HDR_T MsiCapHdr;
532 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
533 return MsiCapHdr.n.u1MsiEnable;
534}
535
536
537/**
538 * Signals a PCI target abort.
539 *
540 * @param pDevIns The IOMMU device instance.
541 */
542static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
543{
544 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
545 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
546 PDMPciDevSetStatus(pPciDev, u16Status);
547}
548
549
550/**
551 * Wakes up the command thread if there are commands to be processed or if
552 * processing is requested to be stopped by software.
553 *
554 * @param pDevIns The IOMMU device instance.
555 */
556static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
557{
558 IOMMU_ASSERT_LOCKED(pDevIns);
559 Log5Func(("\n"));
560
561 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
562 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
563 if (Status.n.u1CmdBufRunning)
564 {
565 Log5Func(("Signaling command thread\n"));
566 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
567 }
568}
569
570
571/**
572 * Reads the Device Table Base Address Register.
573 */
574static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
575{
576 RT_NOREF(pDevIns, offReg);
577 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
578 return VINF_SUCCESS;
579}
580
581
582/**
583 * Reads the Command Buffer Base Address Register.
584 */
585static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
586{
587 RT_NOREF(pDevIns, offReg);
588 *pu64Value = pThis->CmdBufBaseAddr.u64;
589 return VINF_SUCCESS;
590}
591
592
593/**
594 * Reads the Event Log Base Address Register.
595 */
596static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
597{
598 RT_NOREF(pDevIns, offReg);
599 *pu64Value = pThis->EvtLogBaseAddr.u64;
600 return VINF_SUCCESS;
601}
602
603
604/**
605 * Reads the Control Register.
606 */
607static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
608{
609 RT_NOREF(pDevIns, offReg);
610 *pu64Value = pThis->Ctrl.u64;
611 return VINF_SUCCESS;
612}
613
614
615/**
616 * Reads the Exclusion Range Base Address Register.
617 */
618static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
619{
620 RT_NOREF(pDevIns, offReg);
621 *pu64Value = pThis->ExclRangeBaseAddr.u64;
622 return VINF_SUCCESS;
623}
624
625
626/**
627 * Reads to the Exclusion Range Limit Register.
628 */
629static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
630{
631 RT_NOREF(pDevIns, offReg);
632 *pu64Value = pThis->ExclRangeLimit.u64;
633 return VINF_SUCCESS;
634}
635
636
637/**
638 * Reads to the Extended Feature Register.
639 */
640static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
641{
642 RT_NOREF(pDevIns, offReg);
643 *pu64Value = pThis->ExtFeat.u64;
644 return VINF_SUCCESS;
645}
646
647
648/**
649 * Reads to the PPR Log Base Address Register.
650 */
651static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
652{
653 RT_NOREF(pDevIns, offReg);
654 *pu64Value = pThis->PprLogBaseAddr.u64;
655 return VINF_SUCCESS;
656}
657
658
659/**
660 * Writes the Hardware Event Register (Hi).
661 */
662static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
663{
664 RT_NOREF(pDevIns, offReg);
665 *pu64Value = pThis->HwEvtHi.u64;
666 return VINF_SUCCESS;
667}
668
669
670/**
671 * Reads the Hardware Event Register (Lo).
672 */
673static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
674{
675 RT_NOREF(pDevIns, offReg);
676 *pu64Value = pThis->HwEvtLo;
677 return VINF_SUCCESS;
678}
679
680
681/**
682 * Reads the Hardware Event Status Register.
683 */
684static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
685{
686 RT_NOREF(pDevIns, offReg);
687 *pu64Value = pThis->HwEvtStatus.u64;
688 return VINF_SUCCESS;
689}
690
691
692/**
693 * Reads to the GA Log Base Address Register.
694 */
695static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
696{
697 RT_NOREF(pDevIns, offReg);
698 *pu64Value = pThis->GALogBaseAddr.u64;
699 return VINF_SUCCESS;
700}
701
702
703/**
704 * Reads to the PPR Log B Base Address Register.
705 */
706static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
707{
708 RT_NOREF(pDevIns, offReg);
709 *pu64Value = pThis->PprLogBBaseAddr.u64;
710 return VINF_SUCCESS;
711}
712
713
714/**
715 * Reads to the Event Log B Base Address Register.
716 */
717static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
718{
719 RT_NOREF(pDevIns, offReg);
720 *pu64Value = pThis->EvtLogBBaseAddr.u64;
721 return VINF_SUCCESS;
722}
723
724
725/**
726 * Reads the Device Table Segment Base Address Register.
727 */
728static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
729{
730 RT_NOREF(pDevIns);
731
732 /* Figure out which segment is being written. */
733 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
734 uint8_t const idxSegment = offSegment + 1;
735 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
736
737 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
738 return VINF_SUCCESS;
739}
740
741
742/**
743 * Reads the Device Specific Feature Extension (DSFX) Register.
744 */
745static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
746{
747 RT_NOREF(pDevIns, offReg);
748 *pu64Value = pThis->DevSpecificFeat.u64;
749 return VINF_SUCCESS;
750}
751
752/**
753 * Reads the Device Specific Control Extension (DSCX) Register.
754 */
755static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
756{
757 RT_NOREF(pDevIns, offReg);
758 *pu64Value = pThis->DevSpecificCtrl.u64;
759 return VINF_SUCCESS;
760}
761
762
763/**
764 * Reads the Device Specific Status Extension (DSSX) Register.
765 */
766static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
767{
768 RT_NOREF(pDevIns, offReg);
769 *pu64Value = pThis->DevSpecificStatus.u64;
770 return VINF_SUCCESS;
771}
772
773
774/**
775 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
776 */
777static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
778{
779 RT_NOREF(pDevIns, offReg);
780 uint32_t const uLo = pThis->MiscInfo.au32[0];
781 uint32_t const uHi = pThis->MiscInfo.au32[1];
782 *pu64Value = RT_MAKE_U64(uLo, uHi);
783 return VINF_SUCCESS;
784}
785
786
787#ifdef IOMMU_NEW_REGISTER_ACCESS
788/**
789 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
790 * Register (32-bit).
791 */
792static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
793{
794 RT_NOREF(pThis, offReg);
795 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
796 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
797 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
798 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
799 *pu64Value = RT_MAKE_U64(uLo, uHi);
800 return VINF_SUCCESS;
801}
802
803
804/**
805 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
806 */
807static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
808{
809 RT_NOREF(pThis, offReg);
810 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
811 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
812 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
813 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
814 *pu64Value = RT_MAKE_U64(uLo, uHi);
815 return VINF_SUCCESS;
816}
817#endif
818
819
820/**
821 * Reads the Command Buffer Head Pointer Register.
822 */
823static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
824{
825 RT_NOREF(pDevIns, offReg);
826 *pu64Value = pThis->CmdBufHeadPtr.u64;
827 return VINF_SUCCESS;
828}
829
830
831/**
832 * Reads the Command Buffer Tail Pointer Register.
833 */
834static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
835{
836 RT_NOREF(pDevIns, offReg);
837 *pu64Value = pThis->CmdBufTailPtr.u64;
838 return VINF_SUCCESS;
839}
840
841
842/**
843 * Reads the Event Log Head Pointer Register.
844 */
845static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
846{
847 RT_NOREF(pDevIns, offReg);
848 *pu64Value = pThis->EvtLogHeadPtr.u64;
849 return VINF_SUCCESS;
850}
851
852
853/**
854 * Reads the Event Log Tail Pointer Register.
855 */
856static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
857{
858 RT_NOREF(pDevIns, offReg);
859 *pu64Value = pThis->EvtLogTailPtr.u64;
860 return VINF_SUCCESS;
861}
862
863
864/**
865 * Reads the Status Register.
866 */
867static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
868{
869 RT_NOREF(pDevIns, offReg);
870 *pu64Value = pThis->Status.u64;
871 return VINF_SUCCESS;
872}
873
874#ifndef IOMMU_NEW_REGISTER_ACCESS
875static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
876{
877 RT_NOREF(pDevIns, pThis, offReg, u64Value);
878 return VINF_SUCCESS;
879}
880#endif
881
882
883/**
884 * Writes the Device Table Base Address Register.
885 */
886static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
887{
888 RT_NOREF(pDevIns, offReg);
889
890 /* Mask out all unrecognized bits. */
891 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
892
893 /* Update the register. */
894 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
895 return VINF_SUCCESS;
896}
897
898
899/**
900 * Writes the Command Buffer Base Address Register.
901 */
902static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
903{
904 RT_NOREF(pDevIns, offReg);
905
906 /*
907 * While this is not explicitly specified like the event log base address register,
908 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
909 * Inconsistent specs :/
910 */
911 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
912 if (Status.n.u1CmdBufRunning)
913 {
914 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
915 return VINF_SUCCESS;
916 }
917
918 /* Mask out all unrecognized bits. */
919 CMD_BUF_BAR_T CmdBufBaseAddr;
920 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
921
922 /* Validate the length. */
923 if (CmdBufBaseAddr.n.u4Len >= 8)
924 {
925 /* Update the register. */
926 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
927
928 /*
929 * Writing the command buffer base address, clears the command buffer head and tail pointers.
930 * See AMD spec. 2.4 "Commands".
931 */
932 pThis->CmdBufHeadPtr.u64 = 0;
933 pThis->CmdBufTailPtr.u64 = 0;
934 }
935 else
936 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
937
938 return VINF_SUCCESS;
939}
940
941
942/**
943 * Writes the Event Log Base Address Register.
944 */
945static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
946{
947 RT_NOREF(pDevIns, offReg);
948
949 /*
950 * IOMMU behavior is undefined when software writes this register when event logging is running.
951 * In our emulation, we ignore the write entirely.
952 * See AMD IOMMU spec. "Event Log Base Address Register".
953 */
954 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
955 if (Status.n.u1EvtLogRunning)
956 {
957 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
958 return VINF_SUCCESS;
959 }
960
961 /* Mask out all unrecognized bits. */
962 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
963 EVT_LOG_BAR_T EvtLogBaseAddr;
964 EvtLogBaseAddr.u64 = u64Value;
965
966 /* Validate the length. */
967 if (EvtLogBaseAddr.n.u4Len >= 8)
968 {
969 /* Update the register. */
970 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
971
972 /*
973 * Writing the event log base address, clears the event log head and tail pointers.
974 * See AMD spec. 2.5 "Event Logging".
975 */
976 pThis->EvtLogHeadPtr.u64 = 0;
977 pThis->EvtLogTailPtr.u64 = 0;
978 }
979 else
980 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
981
982 return VINF_SUCCESS;
983}
984
985
986/**
987 * Writes the Control Register.
988 */
989static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
990{
991 RT_NOREF(pDevIns, offReg);
992
993 /* Mask out all unrecognized bits. */
994 u64Value &= IOMMU_CTRL_VALID_MASK;
995 IOMMU_CTRL_T NewCtrl;
996 NewCtrl.u64 = u64Value;
997
998 /* Ensure the device table segments are within limits. */
999 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
1000 {
1001 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
1002
1003 /* Update the register. */
1004 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
1005
1006 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
1007 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
1008
1009 /* Enable or disable event logging when the bit transitions. */
1010 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
1011 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1012 if ( fOldEvtLogEn != fNewEvtLogEn
1013 || fOldIommuEn != fNewIommuEn)
1014 {
1015 if ( fNewIommuEn
1016 && fNewEvtLogEn)
1017 {
1018 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1019 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1020 }
1021 else
1022 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1023 }
1024
1025 /* Enable or disable command buffer processing when the bit transitions. */
1026 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1027 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1028 if ( fOldCmdBufEn != fNewCmdBufEn
1029 || fOldIommuEn != fNewIommuEn)
1030 {
1031 if ( fNewCmdBufEn
1032 && fNewIommuEn)
1033 {
1034 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1035 LogFunc(("Command buffer enabled\n"));
1036
1037 /* Wake up the command thread to start processing commands. */
1038 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1039 }
1040 else
1041 {
1042 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1043 LogFunc(("Command buffer disabled\n"));
1044 }
1045 }
1046 }
1047 else
1048 {
1049 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1050 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1051 }
1052
1053 return VINF_SUCCESS;
1054}
1055
1056
1057/**
1058 * Writes to the Exclusion Range Base Address Register.
1059 */
1060static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1061{
1062 RT_NOREF(pDevIns, offReg);
1063 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1064 return VINF_SUCCESS;
1065}
1066
1067
1068/**
1069 * Writes to the Exclusion Range Limit Register.
1070 */
1071static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1072{
1073 RT_NOREF(pDevIns, offReg);
1074 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1075 u64Value |= UINT64_C(0xfff);
1076 pThis->ExclRangeLimit.u64 = u64Value;
1077 return VINF_SUCCESS;
1078}
1079
1080
1081/**
1082 * Writes the Hardware Event Register (Hi).
1083 */
1084static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1085{
1086 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1087 RT_NOREF(pDevIns, offReg);
1088 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1089 pThis->HwEvtHi.u64 = u64Value;
1090 return VINF_SUCCESS;
1091}
1092
1093
1094/**
1095 * Writes the Hardware Event Register (Lo).
1096 */
1097static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1098{
1099 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1100 RT_NOREF(pDevIns, offReg);
1101 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1102 pThis->HwEvtLo = u64Value;
1103 return VINF_SUCCESS;
1104}
1105
1106
1107/**
1108 * Writes the Hardware Event Status Register.
1109 */
1110static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1111{
1112 RT_NOREF(pDevIns, offReg);
1113
1114 /* Mask out all unrecognized bits. */
1115 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1116
1117 /*
1118 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1119 * If the current status bits or the bits being written are both 0, we've nothing to do.
1120 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1121 */
1122 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1123 if (!(HwStatus & RT_BIT(0)))
1124 return VINF_SUCCESS;
1125 if (u64Value & HwStatus & RT_BIT_64(0))
1126 HwStatus &= ~RT_BIT_64(0);
1127 if (u64Value & HwStatus & RT_BIT_64(1))
1128 HwStatus &= ~RT_BIT_64(1);
1129
1130 /* Update the register. */
1131 pThis->HwEvtStatus.u64 = HwStatus;
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/**
1137 * Writes the Device Table Segment Base Address Register.
1138 */
1139static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1140{
1141 RT_NOREF(pDevIns);
1142
1143 /* Figure out which segment is being written. */
1144 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1145 uint8_t const idxSegment = offSegment + 1;
1146 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1147
1148 /* Mask out all unrecognized bits. */
1149 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1150 DEV_TAB_BAR_T DevTabSegBar;
1151 DevTabSegBar.u64 = u64Value;
1152
1153 /* Validate the size. */
1154 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1155 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1156 if (uSegSize <= uMaxSegSize)
1157 {
1158 /* Update the register. */
1159 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1160 }
1161 else
1162 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1163
1164 return VINF_SUCCESS;
1165}
1166
1167
1168#ifndef IOMMU_NEW_REGISTER_ACCESS
1169/**
1170 * Writes the MSI Capability Header Register.
1171 */
1172static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1173{
1174 RT_NOREF(pThis, offReg);
1175 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1176 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1177 MSI_CAP_HDR_T MsiCapHdr;
1178 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1179 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1180 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1181 return VINF_SUCCESS;
1182}
1183
1184
1185/**
1186 * Writes the MSI Address (Lo) Register (32-bit).
1187 */
1188static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1189{
1190 RT_NOREF(pThis, offReg);
1191 Assert(!RT_HI_U32(u64Value));
1192 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1193 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1194 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
1195 return VINF_SUCCESS;
1196}
1197
1198
1199/**
1200 * Writes the MSI Address (Hi) Register (32-bit).
1201 */
1202static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1203{
1204 RT_NOREF(pThis, offReg);
1205 Assert(!RT_HI_U32(u64Value));
1206 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1207 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1208 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
1209 return VINF_SUCCESS;
1210}
1211
1212
1213/**
1214 * Writes the MSI Data Register (32-bit).
1215 */
1216static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1217{
1218 RT_NOREF(pThis, offReg);
1219 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1220 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1221 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
1222 return VINF_SUCCESS;
1223}
1224#else
1225/**
1226 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1227 */
1228static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1229{
1230 RT_NOREF(pDevIns, offReg);
1231
1232 /* MSI Vector Register 0 is read-only. */
1233 /* MSI Vector Register 1. */
1234 uint32_t const uReg = u64Value >> 32;
1235 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
1236 return VINF_SUCCESS;
1237}
1238
1239
1240/**
1241 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1242 * Register (32-bit).
1243 */
1244static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1245{
1246 RT_NOREF(pThis, offReg);
1247 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1248 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1249
1250 /* MSI capability header. */
1251 {
1252 uint32_t const uReg = u64Value;
1253 MSI_CAP_HDR_T MsiCapHdr;
1254 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1255 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1256 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1257 }
1258
1259 /* MSI Address Lo. */
1260 {
1261 uint32_t const uReg = u64Value >> 32;
1262 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
1263 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1264 }
1265
1266 return VINF_SUCCESS;
1267}
1268
1269
1270/**
1271 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1272 */
1273static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1274{
1275 RT_NOREF(pThis, offReg);
1276 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1277 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1278
1279 /* MSI Address Hi. */
1280 {
1281 uint32_t const uReg = u64Value;
1282 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
1283 }
1284
1285 /* MSI Data. */
1286 {
1287 uint32_t const uReg = u64Value >> 32;
1288 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
1289 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1290 }
1291
1292 return VINF_SUCCESS;
1293}
1294#endif
1295
1296
1297/**
1298 * Writes the Command Buffer Head Pointer Register.
1299 */
1300static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1301{
1302 RT_NOREF(pDevIns, offReg);
1303
1304 /*
1305 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1306 * In our emulation, we ignore the write entirely.
1307 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1308 */
1309 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1310 if (Status.n.u1CmdBufRunning)
1311 {
1312 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1313 return VINF_SUCCESS;
1314 }
1315
1316 /*
1317 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1318 * In our emulation, we ignore the write entirely.
1319 */
1320 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1321 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1322 Assert(cbBuf <= _512K);
1323 if (offBuf >= cbBuf)
1324 {
1325 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1326 return VINF_SUCCESS;
1327 }
1328
1329 /* Update the register. */
1330 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1331
1332 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1333
1334 Log5Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1335 return VINF_SUCCESS;
1336}
1337
1338
1339/**
1340 * Writes the Command Buffer Tail Pointer Register.
1341 */
1342static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1343{
1344 RT_NOREF(pDevIns, offReg);
1345
1346 /*
1347 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1348 * In our emulation, we ignore the write entirely.
1349 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1350 */
1351 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1352 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1353 Assert(cbBuf <= _512K);
1354 if (offBuf >= cbBuf)
1355 {
1356 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1357 return VINF_SUCCESS;
1358 }
1359
1360 /*
1361 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1362 * head pointer after adding one or more commands to the buffer.
1363 *
1364 * However, we cannot enforce this strictly because it's legal for software to shrink the
1365 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1366 * at 0). Software might even make the queue empty by making head and tail equal which is
1367 * allowed. I don't think we can or should try too hard to prevent software shooting itself
1368 * in the foot here. As long as we make sure the offset value is within the circular buffer
1369 * bounds (which we do by masking bits above) it should be sufficient.
1370 */
1371 pThis->CmdBufTailPtr.au32[0] = offBuf;
1372
1373 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1374
1375 Log5Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1376 return VINF_SUCCESS;
1377}
1378
1379
1380/**
1381 * Writes the Event Log Head Pointer Register.
1382 */
1383static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1384{
1385 RT_NOREF(pDevIns, offReg);
1386
1387 /*
1388 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1389 * In our emulation, we ignore the write entirely.
1390 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1391 */
1392 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1393 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1394 Assert(cbBuf <= _512K);
1395 if (offBuf >= cbBuf)
1396 {
1397 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1398 return VINF_SUCCESS;
1399 }
1400
1401 /* Update the register. */
1402 pThis->EvtLogHeadPtr.au32[0] = offBuf;
1403
1404 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1405 return VINF_SUCCESS;
1406}
1407
1408
1409/**
1410 * Writes the Event Log Tail Pointer Register.
1411 */
1412static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1413{
1414 RT_NOREF(pDevIns, offReg);
1415 NOREF(pThis);
1416
1417 /*
1418 * IOMMU behavior is undefined when software writes this register when the event log is running.
1419 * In our emulation, we ignore the write entirely.
1420 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1421 */
1422 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1423 if (Status.n.u1EvtLogRunning)
1424 {
1425 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1426 return VINF_SUCCESS;
1427 }
1428
1429 /*
1430 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1431 * In our emulation, we ignore the write entirely.
1432 */
1433 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1434 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1435 Assert(cbBuf <= _512K);
1436 if (offBuf >= cbBuf)
1437 {
1438 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1439 return VINF_SUCCESS;
1440 }
1441
1442 /* Update the register. */
1443 pThis->EvtLogTailPtr.au32[0] = offBuf;
1444
1445 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1446 return VINF_SUCCESS;
1447}
1448
1449
1450/**
1451 * Writes the Status Register.
1452 */
1453static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1454{
1455 RT_NOREF(pDevIns, offReg);
1456
1457 /* Mask out all unrecognized bits. */
1458 u64Value &= IOMMU_STATUS_VALID_MASK;
1459
1460 /*
1461 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1462 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1463 */
1464 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1465 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1466 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1467 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1468
1469 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1470
1471 /* Update the register. */
1472 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1473 return VINF_SUCCESS;
1474}
1475
1476#ifdef IOMMU_NEW_REGISTER_ACCESS
1477/**
1478 * Register access table 0.
1479 * The MMIO offset of each entry must be a multiple of 8!
1480 */
1481static const IOMMUREGACC g_aRegAccess0[] =
1482{
1483 /* MMIO off. Register name Read function Write function */
1484 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
1485 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
1486 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
1487 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
1488 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
1489 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
1490 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
1491 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
1492 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
1493 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
1494 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
1495 { /* 0x58 */ NULL, NULL, NULL },
1496
1497 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
1498 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
1499 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
1500 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
1501 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
1502 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
1503 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
1504 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
1505 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
1506 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
1507 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
1508 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
1509 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
1510 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
1511 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
1512 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
1513
1514 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
1515 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
1516 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
1517 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
1518
1519 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1520 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1521 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1522 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1523 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1524 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1525 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1526
1527 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
1528 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
1529 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
1530
1531 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
1532 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
1533 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
1534 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
1535
1536 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
1537 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
1538 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
1539};
1540AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1541
1542/**
1543 * Register access table 1.
1544 * The MMIO offset of each entry must be a multiple of 8!
1545 */
1546static const IOMMUREGACC g_aRegAccess1[] =
1547{
1548 /* MMIO offset Register name Read function Write function */
1549 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
1550 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
1551 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
1552 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
1553 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
1554 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
1555 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
1556 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
1557 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
1558 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
1559 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
1560 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
1561};
1562AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1563
1564/**
1565 * Register access table 2.
1566 * The MMIO offset of each entry must be a multiple of 8!
1567 */
1568static const IOMMUREGACC g_aRegAccess2[] =
1569{
1570 /* MMIO offset Register name Read Function Write function */
1571 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
1572
1573 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
1574 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
1575 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
1576 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
1577
1578 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
1579 { /* 0x2028 */ NULL, NULL, NULL },
1580
1581 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
1582 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
1583
1584 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
1585 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
1586
1587 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
1588 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
1589
1590 { /* 0x2060 */ NULL, NULL, NULL },
1591 { /* 0x2068 */ NULL, NULL, NULL },
1592
1593 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
1594 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
1595
1596 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
1597 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
1598 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
1599};
1600AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1601
1602
1603/**
1604 * Gets the register access structure given its MMIO offset.
1605 *
1606 * @returns The register access structure, or NULL if the offset is invalid.
1607 * @param off The MMIO offset of the register being accessed.
1608 */
1609static PCIOMMUREGACC iommuAmdGetRegAccessForOffset(uint32_t off)
1610{
1611 /* Figure out which table the register belongs to and validate its index. */
1612 PCIOMMUREGACC pReg;
1613 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1614 {
1615 uint32_t const idxReg = off >> 3;
1616 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1617 pReg = &g_aRegAccess0[idxReg];
1618 }
1619 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1620 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1621 {
1622 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1623 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1624 pReg = &g_aRegAccess1[idxReg];
1625 }
1626 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1627 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1628 {
1629 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1630 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1631 pReg = &g_aRegAccess2[idxReg];
1632 }
1633 else
1634 return NULL;
1635
1636 return pReg;
1637}
1638#endif
1639
1640
1641/**
1642 * Writes an IOMMU register (32-bit and 64-bit).
1643 *
1644 * @returns Strict VBox status code.
1645 * @param pDevIns The IOMMU device instance.
1646 * @param off MMIO byte offset to the register.
1647 * @param cb The size of the write access.
1648 * @param uValue The value being written.
1649 *
1650 * @thread EMT.
1651 */
1652static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1653{
1654 /*
1655 * Validate the access in case of IOM bug or incorrect assumption.
1656 */
1657 Assert(off < IOMMU_MMIO_REGION_SIZE);
1658 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1659 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1660
1661 Log5Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1662
1663 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1664#ifndef IOMMU_NEW_REGISTER_ACCESS
1665 switch (off)
1666 {
1667 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1668 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1669 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1670 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1671 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1672 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1673 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1674
1675 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1676 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1677 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1678 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1679
1680 case IOMMU_MMIO_OFF_GALOG_BAR:
1681 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1682
1683 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1684 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1685
1686 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1687 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1688 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1689 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1690 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1691 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1692 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1693
1694 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1695 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1696 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1697
1698 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1699 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1700 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1701 {
1702 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1703 if (cb == 4 || RT_FAILURE(rcStrict))
1704 return rcStrict;
1705 uValue >>= 32;
1706 RT_FALL_THRU();
1707 }
1708 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1709 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1710 {
1711 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1712 if (cb == 4 || RT_FAILURE(rcStrict))
1713 return rcStrict;
1714 uValue >>= 32;
1715 RT_FALL_THRU();
1716 }
1717 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1718 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1719
1720 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1721
1722 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1723 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1724 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1725
1726 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1727 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1728 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1729 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1730 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1731 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1732 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1733 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1734 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1735 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1736 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1737 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1738
1739 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1740
1741 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1742 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1743 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1744 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1745
1746 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1747
1748 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1749 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1750
1751 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1752 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1753
1754 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1755 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1756
1757 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1758 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1759
1760 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1761 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1762 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1763
1764 /* Not implemented. */
1765 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1766 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1767 {
1768 LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1769 return VINF_SUCCESS;
1770 }
1771
1772 /* Unknown. */
1773 default:
1774 {
1775 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1776 return VINF_SUCCESS;
1777 }
1778 }
1779#else
1780 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1781 if (pReg)
1782 { /* likely */ }
1783 else
1784 {
1785 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
1786 return VINF_SUCCESS;
1787 }
1788
1789 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
1790 if (pReg->pfnWrite)
1791 { /* likely */ }
1792 else
1793 {
1794 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1795 return VINF_SUCCESS;
1796 }
1797
1798 /*
1799 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
1800 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
1801 * consecutive 32-bit registers.
1802 */
1803 if (cb == 8)
1804 {
1805 if (!(off & 7))
1806 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1807
1808 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1809 return VINF_SUCCESS;
1810 }
1811
1812 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
1813 Assert(cb == 4);
1814 if (!(off & 7))
1815 {
1816 /*
1817 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
1818 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1819 */
1820 uint64_t u64Read;
1821 if (pReg->pfnRead)
1822 {
1823 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1824 if (RT_FAILURE(rcStrict))
1825 {
1826 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1827 return rcStrict;
1828 }
1829 }
1830 else
1831 u64Read = 0;
1832
1833 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
1834 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1835 }
1836
1837 /*
1838 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
1839 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1840 */
1841 Assert(!(off & 3));
1842 Assert(off & 7);
1843 Assert(off >= 4);
1844 uint64_t u64Read;
1845 if (pReg->pfnRead)
1846 {
1847 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1848 if (RT_FAILURE(rcStrict))
1849 {
1850 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1851 return rcStrict;
1852 }
1853 }
1854 else
1855 u64Read = 0;
1856
1857 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
1858 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1859#endif
1860}
1861
1862
1863/**
1864 * Reads an IOMMU register (64-bit) given its MMIO offset.
1865 *
1866 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1867 * boundary include the lower half of the subsequent register.
1868 *
1869 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1870 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1871 * software will only perform 32-bit reads on those 32-bit registers that are
1872 * aligned on 8-byte boundaries.
1873 *
1874 * @returns Strict VBox status code.
1875 * @param pDevIns The IOMMU device instance.
1876 * @param off The MMIO offset of the register in bytes.
1877 * @param puResult Where to store the value being read.
1878 *
1879 * @thread EMT.
1880 */
1881static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1882{
1883 Assert(off < IOMMU_MMIO_REGION_SIZE);
1884 Assert(!(off & 7) || !(off & 3));
1885
1886 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1887 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1888 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1889
1890 Log5Func(("off=%#x\n", off));
1891
1892#ifndef IOMMU_NEW_REGISTER_ACCESS
1893 /** @todo IOMMU: fine-grained locking? */
1894 uint64_t uReg;
1895 switch (off)
1896 {
1897 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1898 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1899 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1900 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1901 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1902 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1903 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1904
1905 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1906 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1907 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1908 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1909
1910 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1911 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1912
1913 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1914 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1915
1916 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1917 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1918 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1919 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1920 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1921 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1922 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1923 {
1924 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1925 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1926 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1927 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1928 break;
1929 }
1930
1931 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1932 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1933 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1934
1935 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1936 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1937 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1938 {
1939 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1940 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1941 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1942 break;
1943 }
1944 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1945 {
1946 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1947 break;
1948 }
1949 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1950 {
1951 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1952 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1953 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1954 break;
1955 }
1956 case IOMMU_MMIO_OFF_MSI_DATA:
1957 {
1958 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1959 break;
1960 }
1961 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1962 {
1963 /*
1964 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1965 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1966 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1967 * 0 for this register.
1968 */
1969 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1970 break;
1971 }
1972
1973 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1974
1975 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1976 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1977 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1978
1979 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1980 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1981 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1982 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1983 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1984 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1985 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1986 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1987 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1988 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1989 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1990 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1991
1992 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1993
1994 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1995 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1996 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1997 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1998
1999 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
2000
2001 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
2002 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
2003
2004 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
2005 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
2006
2007 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
2008 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
2009
2010 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
2011 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
2012
2013 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
2014 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
2015 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
2016
2017 /* Not implemented. */
2018 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
2019 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
2020 {
2021 LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
2022 uReg = 0;
2023 break;
2024 }
2025
2026 /* Unknown. */
2027 default:
2028 {
2029 LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
2030 uReg = 0;
2031 return VINF_IOM_MMIO_UNUSED_00;
2032 }
2033 }
2034
2035 *puResult = uReg;
2036 return VINF_SUCCESS;
2037#else
2038 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
2039 if (pReg)
2040 { /* likely */ }
2041 else
2042 {
2043 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2044 return VINF_IOM_MMIO_UNUSED_FF;
2045 }
2046
2047 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2048 if (pReg->pfnRead)
2049 { /* likely */ }
2050 else
2051 {
2052 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2053 return VINF_IOM_MMIO_UNUSED_00;
2054 }
2055
2056 /*
2057 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2058 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2059 */
2060 if (!(off & 7))
2061 return pReg->pfnRead(pDevIns, pThis, off, puResult);
2062
2063 /*
2064 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2065 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2066 */
2067 Assert(!(off & 3));
2068 Assert(off & 7);
2069 Assert(off >= 4);
2070 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2071 if (RT_SUCCESS(rcStrict))
2072 *puResult >>= 32;
2073 else
2074 {
2075 *puResult = 0;
2076 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2077 }
2078
2079 return rcStrict;
2080#endif
2081}
2082
2083
2084/**
2085 * Raises the MSI interrupt for the IOMMU device.
2086 *
2087 * @param pDevIns The IOMMU device instance.
2088 *
2089 * @thread Any.
2090 * @remarks The IOMMU lock may or may not be held.
2091 */
2092static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
2093{
2094 LogFlowFunc(("\n"));
2095 if (iommuAmdIsMsiEnabled(pDevIns))
2096 {
2097 LogFunc(("Raising MSI\n"));
2098 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2099 }
2100}
2101
2102#if 0
2103/**
2104 * Clears the MSI interrupt for the IOMMU device.
2105 *
2106 * @param pDevIns The IOMMU device instance.
2107 *
2108 * @thread Any.
2109 * @remarks The IOMMU lock may or may not be held.
2110 */
2111static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
2112{
2113 if (iommuAmdIsMsiEnabled(pDevIns))
2114 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2115}
2116#endif
2117
2118/**
2119 * Writes an entry to the event log in memory.
2120 *
2121 * @returns VBox status code.
2122 * @param pDevIns The IOMMU device instance.
2123 * @param pEvent The event to log.
2124 *
2125 * @thread Any.
2126 */
2127static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2128{
2129 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2130
2131 IOMMU_ASSERT_LOCKED(pDevIns);
2132
2133 /* Check if event logging is active and the log has not overflowed. */
2134 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2135 if ( Status.n.u1EvtLogRunning
2136 && !Status.n.u1EvtOverflow)
2137 {
2138 uint32_t const cbEvt = sizeof(*pEvent);
2139
2140 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2141 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2142 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2143
2144 /* Ensure we have space in the event log. */
2145 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2146 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2147 if (cEvts + 1 < cMaxEvts)
2148 {
2149 /* Write the event log entry to memory. */
2150 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2151 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2152 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2153 if (RT_FAILURE(rc))
2154 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2155
2156 /* Increment the event log tail pointer. */
2157 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2158 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2159
2160 /* Indicate that an event log entry was written. */
2161 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2162
2163 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2164 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2165 if (Ctrl.n.u1EvtIntrEn)
2166 iommuAmdRaiseMsiInterrupt(pDevIns);
2167 }
2168 else
2169 {
2170 /* Indicate that the event log has overflowed. */
2171 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2172
2173 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2174 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2175 if (Ctrl.n.u1EvtIntrEn)
2176 iommuAmdRaiseMsiInterrupt(pDevIns);
2177 }
2178 }
2179
2180 return VINF_SUCCESS;
2181}
2182
2183
2184/**
2185 * Sets an event in the hardware error registers.
2186 *
2187 * @param pDevIns The IOMMU device instance.
2188 * @param pEvent The event.
2189 *
2190 * @thread Any.
2191 */
2192static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2193{
2194 IOMMU_ASSERT_LOCKED(pDevIns);
2195
2196 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2197 if (pThis->ExtFeat.n.u1HwErrorSup)
2198 {
2199 if (pThis->HwEvtStatus.n.u1Valid)
2200 pThis->HwEvtStatus.n.u1Overflow = 1;
2201 pThis->HwEvtStatus.n.u1Valid = 1;
2202 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2203 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2204 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2205 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2206 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2207 }
2208}
2209
2210
2211/**
2212 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2213 *
2214 * @param uDevId The device ID.
2215 * @param uDomainId The domain ID.
2216 * @param GCPhysPtEntity The system physical address of the page table
2217 * entity.
2218 * @param enmOp The IOMMU operation being performed.
2219 * @param pEvtPageTabHwErr Where to store the initialized event.
2220 */
2221static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2222 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2223{
2224 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2225 pEvtPageTabHwErr->n.u16DevId = uDevId;
2226 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
2227 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
2228 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2229 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2230 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2231 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2232 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
2233 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
2234}
2235
2236
2237/**
2238 * Raises a PAGE_TAB_HARDWARE_ERROR event.
2239 *
2240 * @param pDevIns The IOMMU device instance.
2241 * @param enmOp The IOMMU operation being performed.
2242 * @param pEvtPageTabHwErr The page table hardware error event.
2243 *
2244 * @thread Any.
2245 */
2246static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2247{
2248 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
2249 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
2250
2251 IOMMU_LOCK_NORET(pDevIns);
2252
2253 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2254 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2255 if (enmOp != IOMMUOP_CMD)
2256 iommuAmdSetPciTargetAbort(pDevIns);
2257
2258 IOMMU_UNLOCK(pDevIns);
2259
2260 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
2261 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
2262 pEvtPageTabHwErr->n.u2Type));
2263}
2264
2265
2266#ifdef IN_RING3
2267/**
2268 * Initializes a COMMAND_HARDWARE_ERROR event.
2269 *
2270 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
2271 * @param pEvtCmdHwErr Where to store the initialized event.
2272 */
2273static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2274{
2275 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
2276 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
2277 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
2278 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
2279}
2280
2281
2282/**
2283 * Raises a COMMAND_HARDWARE_ERROR event.
2284 *
2285 * @param pDevIns The IOMMU device instance.
2286 * @param pEvtCmdHwErr The command hardware error event.
2287 *
2288 * @thread Any.
2289 */
2290static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2291{
2292 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
2293 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
2294 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2295
2296 IOMMU_LOCK_NORET(pDevIns);
2297
2298 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2299 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2300 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2301
2302 IOMMU_UNLOCK(pDevIns);
2303
2304 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
2305}
2306#endif /* IN_RING3 */
2307
2308
2309/**
2310 * Initializes a DEV_TAB_HARDWARE_ERROR event.
2311 *
2312 * @param uDevId The device ID.
2313 * @param GCPhysDte The system physical address of the failed device table
2314 * access.
2315 * @param enmOp The IOMMU operation being performed.
2316 * @param pEvtDevTabHwErr Where to store the initialized event.
2317 */
2318static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
2319 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2320{
2321 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
2322 pEvtDevTabHwErr->n.u16DevId = uDevId;
2323 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2324 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
2325 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2326 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2327 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2328 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
2329 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
2330}
2331
2332
2333/**
2334 * Raises a DEV_TAB_HARDWARE_ERROR event.
2335 *
2336 * @param pDevIns The IOMMU device instance.
2337 * @param enmOp The IOMMU operation being performed.
2338 * @param pEvtDevTabHwErr The device table hardware error event.
2339 *
2340 * @thread Any.
2341 */
2342static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2343{
2344 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2345 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2346
2347 IOMMU_LOCK_NORET(pDevIns);
2348
2349 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2350 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2351 if (enmOp != IOMMUOP_CMD)
2352 iommuAmdSetPciTargetAbort(pDevIns);
2353
2354 IOMMU_UNLOCK(pDevIns);
2355
2356 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2357 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2358}
2359
2360#ifdef IN_RING3
2361/**
2362 * Initializes an ILLEGAL_COMMAND_ERROR event.
2363 *
2364 * @param GCPhysCmd The system physical address of the failed command
2365 * access.
2366 * @param pEvtIllegalCmd Where to store the initialized event.
2367 */
2368static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2369{
2370 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2371 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2372 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2373 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2374}
2375
2376
2377/**
2378 * Raises an ILLEGAL_COMMAND_ERROR event.
2379 *
2380 * @param pDevIns The IOMMU device instance.
2381 * @param pEvtIllegalCmd The illegal command error event.
2382 */
2383static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2384{
2385 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2386 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2387 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2388
2389 IOMMU_LOCK_NORET(pDevIns);
2390
2391 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2392 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2393
2394 IOMMU_UNLOCK(pDevIns);
2395
2396 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2397}
2398#endif /* IN_RING3 */
2399
2400
2401/**
2402 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2403 *
2404 * @param uDevId The device ID.
2405 * @param uIova The I/O virtual address.
2406 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2407 * event was caused by an invalid level encoding in the
2408 * DTE.
2409 * @param enmOp The IOMMU operation being performed.
2410 * @param pEvtIllegalDte Where to store the initialized event.
2411 */
2412static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2413 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2414{
2415 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2416 pEvtIllegalDte->n.u16DevId = uDevId;
2417 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2418 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2419 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2420 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2421 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2422 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2423 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2424 * IOMMU spec here but not for this field for I/O page fault event. */
2425 Assert(!(uIova & UINT64_C(0x3)));
2426}
2427
2428
2429/**
2430 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2431 *
2432 * @param pDevIns The IOMMU instance data.
2433 * @param enmOp The IOMMU operation being performed.
2434 * @param pEvtIllegalDte The illegal device table entry event.
2435 * @param enmEvtType The illegal device table entry event type.
2436 *
2437 * @thread Any.
2438 */
2439static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2440 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2441{
2442 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2443 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2444
2445 IOMMU_LOCK_NORET(pDevIns);
2446
2447 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2448 if (enmOp != IOMMUOP_CMD)
2449 iommuAmdSetPciTargetAbort(pDevIns);
2450
2451 IOMMU_UNLOCK(pDevIns);
2452
2453 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2454 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2455 NOREF(enmEvtType);
2456}
2457
2458
2459/**
2460 * Initializes an IO_PAGE_FAULT event.
2461 *
2462 * @param uDevId The device ID.
2463 * @param uDomainId The domain ID.
2464 * @param uIova The I/O virtual address being accessed.
2465 * @param fPresent Transaction to a page marked as present (including
2466 * DTE.V=1) or interrupt marked as remapped
2467 * (IRTE.RemapEn=1).
2468 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2469 * the I/O page fault was caused by invalid level
2470 * encoding.
2471 * @param fPermDenied Permission denied for the address being accessed.
2472 * @param enmOp The IOMMU operation being performed.
2473 * @param pEvtIoPageFault Where to store the initialized event.
2474 */
2475static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2476 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2477{
2478 Assert(!fPermDenied || fPresent);
2479 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2480 pEvtIoPageFault->n.u16DevId = uDevId;
2481 //pEvtIoPageFault->n.u4PasidHi = 0;
2482 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2483 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2484 //pEvtIoPageFault->n.u1NoExecute = 0;
2485 //pEvtIoPageFault->n.u1User = 0;
2486 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2487 pEvtIoPageFault->n.u1Present = fPresent;
2488 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2489 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2490 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2491 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2492 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2493 pEvtIoPageFault->n.u64Addr = uIova;
2494}
2495
2496
2497/**
2498 * Raises an IO_PAGE_FAULT event.
2499 *
2500 * @param pDevIns The IOMMU instance data.
2501 * @param pDte The device table entry. Optional, can be NULL
2502 * depending on @a enmOp.
2503 * @param pIrte The interrupt remapping table entry. Optional, can
2504 * be NULL depending on @a enmOp.
2505 * @param enmOp The IOMMU operation being performed.
2506 * @param pEvtIoPageFault The I/O page fault event.
2507 * @param enmEvtType The I/O page fault event type.
2508 *
2509 * @thread Any.
2510 */
2511static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2512 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2513{
2514 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2515 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2516
2517 IOMMU_LOCK_NORET(pDevIns);
2518
2519 bool fSuppressEvtLogging = false;
2520 if ( enmOp == IOMMUOP_MEM_READ
2521 || enmOp == IOMMUOP_MEM_WRITE)
2522 {
2523 if ( pDte
2524 && pDte->n.u1Valid)
2525 {
2526 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2527 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2528 * suppression. Perhaps will be possible when we complete IOTLB/cache
2529 * handling. */
2530 }
2531 }
2532 else if (enmOp == IOMMUOP_INTR_REQ)
2533 {
2534 if ( pDte
2535 && pDte->n.u1IntrMapValid)
2536 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2537
2538 if ( !fSuppressEvtLogging
2539 && pIrte)
2540 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2541 }
2542 /* else: Events are never suppressed for commands. */
2543
2544 switch (enmEvtType)
2545 {
2546 case kIoPageFaultType_PermDenied:
2547 {
2548 /* Cannot be triggered by a command. */
2549 Assert(enmOp != IOMMUOP_CMD);
2550 RT_FALL_THRU();
2551 }
2552 case kIoPageFaultType_DteRsvdPagingMode:
2553 case kIoPageFaultType_PteInvalidPageSize:
2554 case kIoPageFaultType_PteInvalidLvlEncoding:
2555 case kIoPageFaultType_SkippedLevelIovaNotZero:
2556 case kIoPageFaultType_PteRsvdNotZero:
2557 case kIoPageFaultType_PteValidNotSet:
2558 case kIoPageFaultType_DteTranslationDisabled:
2559 case kIoPageFaultType_PasidInvalidRange:
2560 {
2561 /*
2562 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2563 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
2564 */
2565 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2566 {
2567 if (!fSuppressEvtLogging)
2568 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2569 if (enmOp != IOMMUOP_CMD)
2570 iommuAmdSetPciTargetAbort(pDevIns);
2571 }
2572 break;
2573 }
2574
2575 case kIoPageFaultType_UserSupervisor:
2576 {
2577 /* Access is blocked and only creates an event log entry. */
2578 if (!fSuppressEvtLogging)
2579 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2580 break;
2581 }
2582
2583 case kIoPageFaultType_IrteAddrInvalid:
2584 case kIoPageFaultType_IrteRsvdNotZero:
2585 case kIoPageFaultType_IrteRemapEn:
2586 case kIoPageFaultType_IrteRsvdIntType:
2587 case kIoPageFaultType_IntrReqAborted:
2588 case kIoPageFaultType_IntrWithPasid:
2589 {
2590 /* Only trigerred by interrupt requests. */
2591 Assert(enmOp == IOMMUOP_INTR_REQ);
2592 if (!fSuppressEvtLogging)
2593 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2594 iommuAmdSetPciTargetAbort(pDevIns);
2595 break;
2596 }
2597
2598 case kIoPageFaultType_SmiFilterMismatch:
2599 {
2600 /* Not supported and probably will never be, assert. */
2601 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2602 break;
2603 }
2604
2605 case kIoPageFaultType_DevId_Invalid:
2606 {
2607 /* Cannot be triggered by a command. */
2608 Assert(enmOp != IOMMUOP_CMD);
2609 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2610 if (!fSuppressEvtLogging)
2611 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2612 if ( enmOp == IOMMUOP_MEM_READ
2613 || enmOp == IOMMUOP_MEM_WRITE)
2614 iommuAmdSetPciTargetAbort(pDevIns);
2615 break;
2616 }
2617 }
2618
2619 IOMMU_UNLOCK(pDevIns);
2620}
2621
2622
2623/**
2624 * Returns whether the I/O virtual address is to be excluded from translation and
2625 * permission checks.
2626 *
2627 * @returns @c true if the DVA is excluded, @c false otherwise.
2628 * @param pThis The IOMMU device state.
2629 * @param pDte The device table entry.
2630 * @param uIova The I/O virtual address.
2631 *
2632 * @remarks Ensure the exclusion range is enabled prior to calling this function.
2633 *
2634 * @thread Any.
2635 */
2636static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2637{
2638 /* Ensure the exclusion range is enabled. */
2639 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2640
2641 /* Check if the IOVA falls within the exclusion range. */
2642 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2643 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2644 if (uIovaExclLast - uIova >= uIovaExclFirst)
2645 {
2646 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2647 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2648 || pDte->n.u1AllowExclusion)
2649 return true;
2650 }
2651 return false;
2652}
2653
2654
2655/**
2656 * Reads a device table entry from guest memory given the device ID.
2657 *
2658 * @returns VBox status code.
2659 * @param pDevIns The IOMMU device instance.
2660 * @param uDevId The device ID.
2661 * @param enmOp The IOMMU operation being performed.
2662 * @param pDte Where to store the device table entry.
2663 *
2664 * @thread Any.
2665 */
2666static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2667{
2668 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2669 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2670
2671 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2672 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2673
2674 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2675 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2676 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
2677
2678 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2679 uint16_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2680 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2681
2682 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2683 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2684 if (RT_FAILURE(rc))
2685 {
2686 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2687
2688 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2689 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2690 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2691 return VERR_IOMMU_IPE_1;
2692 }
2693
2694 return rc;
2695}
2696
2697
2698/**
2699 * Walks the I/O page table to translate the I/O virtual address to a system
2700 * physical address.
2701 *
2702 * @returns VBox status code.
2703 * @param pDevIns The IOMMU device instance.
2704 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2705 * @param uDevId The device ID.
2706 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2707 * permissions for the access being made.
2708 * @param pDte The device table entry.
2709 * @param enmOp The IOMMU operation being performed.
2710 * @param pWalkResult Where to store the results of the I/O page walk. This is
2711 * only updated when VINF_SUCCESS is returned.
2712 *
2713 * @thread Any.
2714 */
2715static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2716 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2717{
2718 Assert(pDte->n.u1Valid);
2719 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2720
2721 /* If the translation is not valid, raise an I/O page fault. */
2722 if (pDte->n.u1TranslationValid)
2723 { /* likely */ }
2724 else
2725 {
2726 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2727 * doesn't explicitly say whether an I/O page fault is raised. From other
2728 * places in the spec. it seems early page walk terminations (starting with
2729 * the DTE) return the state computed so far and raises an I/O page fault. So
2730 * returning an invalid translation rather than skipping translation. */
2731 LogFunc(("Translation valid bit not set -> IOPF\n"));
2732 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2733 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2734 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2735 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2736 kIoPageFaultType_DteTranslationDisabled);
2737 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2738 }
2739
2740 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2741 uint8_t const uMaxLevel = pDte->n.u3Mode;
2742 if (uMaxLevel != 0)
2743 { /* likely */ }
2744 else
2745 {
2746 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2747 if ((fAccess & fDtePerm) != fAccess)
2748 {
2749 LogFunc(("Access denied for IOVA %#RX64. uDevId=%#x fAccess=%#x fDtePerm=%#x\n", uIova, uDevId, fAccess, fDtePerm));
2750 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2751 }
2752 pWalkResult->GCPhysSpa = uIova;
2753 pWalkResult->cShift = 0;
2754 pWalkResult->fIoPerm = fDtePerm;
2755 return VINF_SUCCESS;
2756 }
2757
2758 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2759 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2760 { /* likely */ }
2761 else
2762 {
2763 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2764 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2765 * I'm just going with I/O page fault. */
2766 LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
2767 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2768 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2769 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2770 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2771 kIoPageFaultType_PteInvalidLvlEncoding);
2772 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2773 }
2774
2775 /* Check permissions bits of the root page table. */
2776 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2777 if ((fAccess & fRootPtePerm) == fAccess)
2778 { /* likely */ }
2779 else
2780 {
2781 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2782 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2783 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2784 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2785 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2786 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2787 }
2788
2789 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2790 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2791 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2792 * table entry every time. Not sure if it's worth optimizing that case now
2793 * or if at all. */
2794
2795 /* The virtual address bits indexing table. */
2796 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2797 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2798 UINT64_C(0x00000000001ff000),
2799 UINT64_C(0x000000003fe00000),
2800 UINT64_C(0x0000007fc0000000),
2801 UINT64_C(0x0000ff8000000000),
2802 UINT64_C(0x01ff000000000000),
2803 UINT64_C(0xfe00000000000000),
2804 UINT64_C(0x0000000000000000) };
2805 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2806 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2807
2808 /* Traverse the I/O page table starting with the page directory in the DTE. */
2809 IOPTENTITY_T PtEntity;
2810 PtEntity.u64 = pDte->au64[0];
2811 for (;;)
2812 {
2813 /* Figure out the system physical address of the page table at the current level. */
2814 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2815
2816 /* Read the page table entity at the current level. */
2817 {
2818 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2819 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2820 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2821 uint64_t const offPte = idxPte << 3;
2822 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2823 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2824 if (RT_FAILURE(rc))
2825 {
2826 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2827 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2828 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2829 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2830 return VERR_IOMMU_IPE_2;
2831 }
2832 }
2833
2834 /* Check present bit. */
2835 if (PtEntity.n.u1Present)
2836 { /* likely */ }
2837 else
2838 {
2839 LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
2840 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2841 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2842 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2843 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2844 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2845 }
2846
2847 /* Check permission bits. */
2848 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2849 if ((fAccess & fPtePerm) == fAccess)
2850 { /* likely */ }
2851 else
2852 {
2853 LogFunc(("Page table entry access denied (uDevId=%#x fAccess=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fAccess, fPtePerm));
2854 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2855 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2856 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2857 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2858 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2859 }
2860
2861 /* If this is a PTE, we're at the final level and we're done. */
2862 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2863 if (uNextLevel == 0)
2864 {
2865 /* The page size of the translation is the default (4K). */
2866 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2867 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2868 pWalkResult->fIoPerm = fPtePerm;
2869 return VINF_SUCCESS;
2870 }
2871 if (uNextLevel == 7)
2872 {
2873 /* The default page size of the translation is overridden. */
2874 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2875 uint8_t cShift = X86_PAGE_4K_SHIFT;
2876 while (GCPhysPte & RT_BIT_64(cShift++))
2877 ;
2878
2879 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2880 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2881 if ( cShift > s_acIovaLevelShifts[uLevel]
2882 && cShift < s_acIovaLevelShifts[uLevel + 1])
2883 {
2884 pWalkResult->GCPhysSpa = GCPhysPte;
2885 pWalkResult->cShift = cShift;
2886 pWalkResult->fIoPerm = fPtePerm;
2887 return VINF_SUCCESS;
2888 }
2889
2890 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2891 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2892 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2893 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2894 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2895 kIoPageFaultType_PteInvalidPageSize);
2896 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2897 }
2898
2899 /* Validate the next level encoding of the PDE. */
2900#if IOMMU_MAX_HOST_PT_LEVEL < 6
2901 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2902 { /* likely */ }
2903 else
2904 {
2905 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2906 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2907 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2908 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2909 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2910 kIoPageFaultType_PteInvalidLvlEncoding);
2911 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2912 }
2913#else
2914 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2915#endif
2916
2917 /* Validate level transition. */
2918 if (uNextLevel < uLevel)
2919 { /* likely */ }
2920 else
2921 {
2922 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2923 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2924 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2925 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2926 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2927 kIoPageFaultType_PteInvalidLvlEncoding);
2928 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2929 }
2930
2931 /* Ensure IOVA bits of skipped levels are zero. */
2932 Assert(uLevel > 0);
2933 uint64_t uIovaSkipMask = 0;
2934 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2935 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2936 if (!(uIova & uIovaSkipMask))
2937 { /* likely */ }
2938 else
2939 {
2940 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2941 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2942 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2943 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2944 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2945 kIoPageFaultType_SkippedLevelIovaNotZero);
2946 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2947 }
2948
2949 /* Continue with traversing the page directory at this level. */
2950 }
2951}
2952
2953
2954/**
2955 * Looks up an I/O virtual address from the device table.
2956 *
2957 * @returns VBox status code.
2958 * @param pDevIns The IOMMU instance data.
2959 * @param uDevId The device ID.
2960 * @param uIova The I/O virtual address to lookup.
2961 * @param cbAccess The size of the access.
2962 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2963 * permissions for the access being made.
2964 * @param enmOp The IOMMU operation being performed.
2965 * @param pGCPhysSpa Where to store the translated system physical address. Only
2966 * valid when translation succeeds and VINF_SUCCESS is
2967 * returned!
2968 *
2969 * @thread Any.
2970 */
2971static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2972 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2973{
2974 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2975
2976 /* Read the device table entry from memory. */
2977 DTE_T Dte;
2978 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2979 if (RT_SUCCESS(rc))
2980 {
2981 /* If the DTE is not valid, addresses are forwarded without translation */
2982 if (Dte.n.u1Valid)
2983 { /* likely */ }
2984 else
2985 {
2986 /** @todo IOMMU: Add to IOLTB cache. */
2987 *pGCPhysSpa = uIova;
2988 return VINF_SUCCESS;
2989 }
2990
2991 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2992 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2993 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2994 if (RT_LIKELY( !fRsvd0
2995 && !fRsvd1))
2996 { /* likely */ }
2997 else
2998 {
2999 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
3000 EVT_ILLEGAL_DTE_T Event;
3001 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
3002 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3003 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3004 }
3005
3006 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
3007 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable /** @todo lock or make atomic read? */
3008 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
3009 { /* likely */ }
3010 else
3011 {
3012 /** @todo IOMMU: Add to IOLTB cache. */
3013 *pGCPhysSpa = uIova;
3014 return VINF_SUCCESS;
3015 }
3016
3017 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
3018 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
3019
3020 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
3021 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
3022 uint64_t cbRemaining = cbAccess;
3023 for (;;)
3024 {
3025 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
3026 IOWALKRESULT WalkResult;
3027 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
3028 if (RT_SUCCESS(rc))
3029 {
3030 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
3031
3032 /* Store the translated base address before continuing to check permissions for any more pages. */
3033 if (cbRemaining == cbAccess)
3034 {
3035 uint64_t const offMask = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
3036 uint64_t const offSpa = uIova & offMask;
3037 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
3038 }
3039
3040 /* If the access exceeds the page size, check permissions for the subsequent page. */
3041 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
3042 if (cbRemaining > cbPhysPage - offIova)
3043 {
3044 cbRemaining -= (cbPhysPage - offIova);
3045 uBaseIova += cbPhysPage; /** @todo r=ramshankar: Should we mask the offset based on page size here? */
3046 offIova = 0;
3047 }
3048 else
3049 break;
3050 }
3051 else
3052 {
3053 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
3054 uBaseIova, fAccess, rc));
3055 *pGCPhysSpa = NIL_RTGCPHYS;
3056 return rc;
3057 }
3058 }
3059
3060 return rc;
3061 }
3062
3063 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3064 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3065}
3066
3067
3068/**
3069 * Memory access transaction from a device.
3070 *
3071 * @returns VBox status code.
3072 * @param pDevIns The IOMMU device instance.
3073 * @param uDevId The device ID (bus, device, function).
3074 * @param uIova The I/O virtual address being accessed.
3075 * @param cbAccess The number of bytes being accessed.
3076 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3077 * @param pGCPhysSpa Where to store the translated system physical address.
3078 *
3079 * @thread Any.
3080 */
3081static DECLCALLBACK(int) iommuAmdDeviceMemAccess(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
3082 uint32_t fFlags, PRTGCPHYS pGCPhysSpa)
3083{
3084 /* Validate. */
3085 AssertPtr(pDevIns);
3086 AssertPtr(pGCPhysSpa);
3087 Assert(cbAccess > 0);
3088 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3089
3090 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3091 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3092 if (Ctrl.n.u1IommuEn)
3093 {
3094 IOMMUOP enmOp;
3095 uint8_t fAccess;
3096 if (fFlags & PDMIOMMU_MEM_F_READ)
3097 {
3098 enmOp = IOMMUOP_MEM_READ;
3099 fAccess = IOMMU_IO_PERM_READ;
3100 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
3101 }
3102 else
3103 {
3104 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
3105 enmOp = IOMMUOP_MEM_WRITE;
3106 fAccess = IOMMU_IO_PERM_WRITE;
3107 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
3108 }
3109
3110#ifdef LOG_ENABLED
3111 static const char * const s_apszAccess[] = { "none", "read", "write" };
3112 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
3113 const char *pszAccess = s_apszAccess[fAccess];
3114 LogFlowFunc(("uDevId=%#x uIova=%#RX64 szAccess=%s cbAccess=%zu\n", uDevId, uIova, pszAccess, cbAccess));
3115#endif
3116
3117 /** @todo IOMMU: IOTLB cache lookup. */
3118
3119 /* Lookup the IOVA from the device table. */
3120 int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbAccess, fAccess, enmOp, pGCPhysSpa);
3121 if (RT_SUCCESS(rc))
3122 { /* likely */ }
3123 else
3124 LogFunc(("DTE lookup failed! uDevId=%#x uIova=%#RX64 fAccess=%s cbAccess=%zu rc=%Rrc\n", uDevId, uIova, fAccess,
3125 cbAccess, rc));
3126 return rc;
3127 }
3128
3129 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3130 *pGCPhysSpa = uIova;
3131 return VINF_SUCCESS;
3132}
3133
3134
3135/**
3136 * Memory access bulk (one or more 4K pages) request from a device.
3137 *
3138 * @returns VBox status code.
3139 * @param pDevIns The IOMMU device instance.
3140 * @param uDevId The device ID (bus, device, function).
3141 * @param cIovas The number of addresses being accessed.
3142 * @param pauIovas The I/O virtual addresses for each page being accessed.
3143 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3144 * @param paGCPhysSpa Where to store the translated physical addresses.
3145 *
3146 * @thread Any.
3147 */
3148static DECLCALLBACK(int) iommuAmdDeviceMemBulkAccess(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas,
3149 uint64_t const *pauIovas, uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
3150{
3151 /* Validate. */
3152 AssertPtr(pDevIns);
3153 Assert(cIovas > 0);
3154 AssertPtr(pauIovas);
3155 AssertPtr(paGCPhysSpa);
3156 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3157
3158 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3159 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3160 if (Ctrl.n.u1IommuEn)
3161 {
3162 IOMMUOP enmOp;
3163 uint8_t fAccess;
3164 if (fFlags & PDMIOMMU_MEM_F_READ)
3165 {
3166 enmOp = IOMMUOP_MEM_READ;
3167 fAccess = IOMMU_IO_PERM_READ;
3168 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
3169 }
3170 else
3171 {
3172 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
3173 enmOp = IOMMUOP_MEM_WRITE;
3174 fAccess = IOMMU_IO_PERM_WRITE;
3175 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
3176 }
3177
3178#ifdef LOG_ENABLED
3179 static const char * const s_apszAccess[] = { "none", "read", "write" };
3180 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
3181 const char *pszAccess = s_apszAccess[fAccess];
3182 LogFlowFunc(("uDevId=%#x cIovas=%zu szAccess=%s\n", uDevId, cIovas, pszAccess));
3183#endif
3184
3185 /** @todo IOMMU: IOTLB cache lookup. */
3186
3187 /* Lookup each IOVA from the device table. */
3188 for (size_t i = 0; i < cIovas; i++)
3189 {
3190 int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, pauIovas[i], X86_PAGE_SIZE, fAccess, enmOp, &paGCPhysSpa[i]);
3191 if (RT_SUCCESS(rc))
3192 { /* likely */ }
3193 else
3194 {
3195 LogFunc(("Failed! uDevId=%#x uIova=%#RX64 fAccess=%u rc=%Rrc\n", uDevId, pauIovas[i], fAccess, rc));
3196 return rc;
3197 }
3198 }
3199 }
3200 else
3201 {
3202 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3203 for (size_t i = 0; i < cIovas; i++)
3204 paGCPhysSpa[i] = pauIovas[i];
3205 }
3206
3207 return VINF_SUCCESS;
3208}
3209
3210
3211
3212/**
3213 * Reads an interrupt remapping table entry from guest memory given its DTE.
3214 *
3215 * @returns VBox status code.
3216 * @param pDevIns The IOMMU device instance.
3217 * @param uDevId The device ID.
3218 * @param pDte The device table entry.
3219 * @param GCPhysIn The source MSI address.
3220 * @param uDataIn The source MSI data.
3221 * @param enmOp The IOMMU operation being performed.
3222 * @param pIrte Where to store the interrupt remapping table entry.
3223 *
3224 * @thread Any.
3225 */
3226static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
3227 IOMMUOP enmOp, PIRTE_T pIrte)
3228{
3229 /* Ensure the IRTE length is valid. */
3230 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
3231
3232 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
3233 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
3234 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
3235 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
3236
3237 /* Ensure the IRTE falls completely within the interrupt table. */
3238 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
3239 { /* likely */ }
3240 else
3241 {
3242 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
3243 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
3244
3245 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3246 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
3247 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3248 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3249 kIoPageFaultType_IrteAddrInvalid);
3250 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3251 }
3252
3253 /* Read the IRTE from memory. */
3254 Assert(!(GCPhysIrte & 3));
3255 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
3256 if (RT_SUCCESS(rc))
3257 return VINF_SUCCESS;
3258
3259 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
3260 * situation. Is it an I/O page fault or a device table hardware error?
3261 * There's no interrupt table hardware error event, but it's unclear what
3262 * we should do here. */
3263 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
3264 return VERR_IOMMU_IPE_4;
3265}
3266
3267
3268/**
3269 * Remaps the interrupt using the interrupt remapping table.
3270 *
3271 * @returns VBox status code.
3272 * @param pDevIns The IOMMU instance data.
3273 * @param uDevId The device ID.
3274 * @param pDte The device table entry.
3275 * @param enmOp The IOMMU operation being performed.
3276 * @param pMsiIn The source MSI.
3277 * @param pMsiOut Where to store the remapped MSI.
3278 *
3279 * @thread Any.
3280 */
3281static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
3282 PMSIMSG pMsiOut)
3283{
3284 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
3285
3286 IRTE_T Irte;
3287 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
3288 if (RT_SUCCESS(rc))
3289 {
3290 if (Irte.n.u1RemapEnable)
3291 {
3292 if (!Irte.n.u1GuestMode)
3293 {
3294 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
3295 {
3296 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
3297 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
3298 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
3299 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
3300
3301 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
3302 pMsiOut->Data.u32 = pMsiIn->Data.u32;
3303 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
3304 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
3305
3306 return VINF_SUCCESS;
3307 }
3308
3309 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3310 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3311 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3312 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3313 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
3314 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3315 }
3316
3317 LogFunc(("Guest mode not supported -> IOPF\n"));
3318 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3319 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3320 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3321 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3322 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3323 }
3324
3325 LogFunc(("Remapping disabled -> IOPF\n"));
3326 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3327 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3328 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3329 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3330 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3331 }
3332
3333 return rc;
3334}
3335
3336
3337/**
3338 * Looks up an MSI interrupt from the interrupt remapping table.
3339 *
3340 * @returns VBox status code.
3341 * @param pDevIns The IOMMU instance data.
3342 * @param uDevId The device ID.
3343 * @param enmOp The IOMMU operation being performed.
3344 * @param pMsiIn The source MSI.
3345 * @param pMsiOut Where to store the remapped MSI.
3346 *
3347 * @thread Any.
3348 */
3349static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3350{
3351 /* Read the device table entry from memory. */
3352 LogFlowFunc(("uDevId=%#x enmOp=%u\n", uDevId, enmOp));
3353
3354 DTE_T Dte;
3355 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3356 if (RT_SUCCESS(rc))
3357 {
3358 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
3359 if (Dte.n.u1IntrMapValid)
3360 {
3361 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3362 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3363 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3364 if (RT_LIKELY( !fRsvd0
3365 && !fRsvd1))
3366 { /* likely */ }
3367 else
3368 {
3369 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3370 fRsvd1));
3371 EVT_ILLEGAL_DTE_T Event;
3372 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3373 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3374 return VERR_IOMMU_INTR_REMAP_FAILED;
3375 }
3376
3377 /*
3378 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3379 * that's connected through HyperTransport it might be possible; but for us, it
3380 * doesn't seem we need to specially handle these pins.
3381 */
3382
3383 /*
3384 * Validate the MSI source address.
3385 *
3386 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3387 * CPU is concerned, the MSI region is fixed and we must ensure no other device
3388 * claims the region as I/O space.
3389 *
3390 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3391 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3392 * See Intel spec. 10.11.1 "Message Address Register Format".
3393 */
3394 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3395 {
3396 /*
3397 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3398 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3399 */
3400 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3401 bool fPassThru = false;
3402 switch (u8DeliveryMode)
3403 {
3404 case VBOX_MSI_DELIVERY_MODE_FIXED:
3405 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3406 {
3407 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3408 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3409 {
3410 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
3411 iommuAmdSetPciTargetAbort(pDevIns);
3412 return VERR_IOMMU_INTR_REMAP_DENIED;
3413 }
3414
3415 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3416 {
3417 fPassThru = true;
3418 break;
3419 }
3420
3421 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3422 {
3423 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3424 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3425 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3426 {
3427 /*
3428 * We don't support guest interrupt remapping yet. When we do, we'll need to
3429 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3430 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3431 * already reads the control register, add that as a parameter when we eventually
3432 * support guest interrupt remapping. For now, just assert.
3433 */
3434 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3435 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3436 NOREF(pThis);
3437
3438 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3439 }
3440
3441 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3442 EVT_ILLEGAL_DTE_T Event;
3443 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3444 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3445 return VERR_IOMMU_INTR_REMAP_FAILED;
3446 }
3447
3448 /* Paranoia. */
3449 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
3450
3451 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3452
3453 EVT_ILLEGAL_DTE_T Event;
3454 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3455 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3456 return VERR_IOMMU_INTR_REMAP_FAILED;
3457 }
3458
3459 /* SMIs are passed through unmapped. We don't implement SMI filters. */
3460 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3461 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3462 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3463 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3464 default:
3465 {
3466 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3467 iommuAmdSetPciTargetAbort(pDevIns);
3468 return VERR_IOMMU_INTR_REMAP_FAILED;
3469 }
3470 }
3471
3472 if (fPassThru)
3473 {
3474 *pMsiOut = *pMsiIn;
3475 return VINF_SUCCESS;
3476 }
3477
3478 iommuAmdSetPciTargetAbort(pDevIns);
3479 return VERR_IOMMU_INTR_REMAP_DENIED;
3480 }
3481 else
3482 {
3483 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3484 return VERR_IOMMU_INTR_REMAP_FAILED;
3485 }
3486 }
3487 else
3488 {
3489 /** @todo IOMMU: Add to interrupt remapping cache. */
3490 LogFlowFunc(("DTE interrupt map not valid\n"));
3491 *pMsiOut = *pMsiIn;
3492 return VINF_SUCCESS;
3493 }
3494 }
3495
3496 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3497 return VERR_IOMMU_INTR_REMAP_FAILED;
3498}
3499
3500
3501/**
3502 * Interrupt remap request from a device.
3503 *
3504 * @returns VBox status code.
3505 * @param pDevIns The IOMMU device instance.
3506 * @param uDevId The device ID (bus, device, function).
3507 * @param pMsiIn The source MSI.
3508 * @param pMsiOut Where to store the remapped MSI.
3509 */
3510static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3511{
3512 /* Validate. */
3513 Assert(pDevIns);
3514 Assert(pMsiIn);
3515 Assert(pMsiOut);
3516
3517 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3518
3519 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3520 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3521 if (Ctrl.n.u1IommuEn)
3522 {
3523 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3524 LogFlowFunc(("uDevId=%#x\n", uDevId));
3525 /** @todo Cache? */
3526
3527 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3528 }
3529
3530 *pMsiOut = *pMsiIn;
3531 return VINF_SUCCESS;
3532}
3533
3534
3535/**
3536 * @callback_method_impl{FNIOMMMIONEWWRITE}
3537 */
3538static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3539{
3540 NOREF(pvUser);
3541 Assert(cb == 4 || cb == 8);
3542 Assert(!(off & (cb - 1)));
3543
3544 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3545 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3546
3547 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
3548 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
3549}
3550
3551
3552/**
3553 * @callback_method_impl{FNIOMMMIONEWREAD}
3554 */
3555static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3556{
3557 NOREF(pvUser);
3558 Assert(cb == 4 || cb == 8);
3559 Assert(!(off & (cb - 1)));
3560
3561 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3562 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3563
3564 uint64_t uResult;
3565 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
3566 if (cb == 8)
3567 *(uint64_t *)pv = uResult;
3568 else
3569 *(uint32_t *)pv = (uint32_t)uResult;
3570
3571 return rcStrict;
3572}
3573
3574# ifdef IN_RING3
3575
3576/**
3577 * Processes an IOMMU command.
3578 *
3579 * @returns VBox status code.
3580 * @param pDevIns The IOMMU device instance.
3581 * @param pCmd The command to process.
3582 * @param GCPhysCmd The system physical address of the command.
3583 * @param pEvtError Where to store the error event in case of failures.
3584 *
3585 * @thread Command thread.
3586 */
3587static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3588{
3589 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3590
3591 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3592 STAM_COUNTER_INC(&pThis->StatCmd);
3593
3594 uint8_t const bCmd = pCmd->n.u4Opcode;
3595 switch (bCmd)
3596 {
3597 case IOMMU_CMD_COMPLETION_WAIT:
3598 {
3599 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3600
3601 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3602 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
3603
3604 /* Validate reserved bits in the command. */
3605 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3606 {
3607 /* If Completion Store is requested, write the StoreData to the specified address. */
3608 if (pCmdComWait->n.u1Store)
3609 {
3610 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3611 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3612 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3613 if (RT_FAILURE(rc))
3614 {
3615 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3616 GCPhysStore, rc));
3617 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3618 return VERR_IOMMU_CMD_HW_ERROR;
3619 }
3620 }
3621
3622 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3623 if (pCmdComWait->n.u1Interrupt)
3624 {
3625 IOMMU_LOCK(pDevIns);
3626 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3627 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3628 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3629 IOMMU_UNLOCK(pDevIns);
3630
3631 if (fRaiseInt)
3632 iommuAmdRaiseMsiInterrupt(pDevIns);
3633 }
3634 return VINF_SUCCESS;
3635 }
3636 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3637 return VERR_IOMMU_CMD_INVALID_FORMAT;
3638 }
3639
3640 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3641 {
3642 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3643 * then. */
3644 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3645 return VINF_SUCCESS;
3646 }
3647
3648 case IOMMU_CMD_INV_IOMMU_PAGES:
3649 {
3650 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3651 * then. */
3652 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3653 return VINF_SUCCESS;
3654 }
3655
3656 case IOMMU_CMD_INV_IOTLB_PAGES:
3657 {
3658 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3659
3660 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3661 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3662 {
3663 /** @todo IOMMU: Implement remote IOTLB invalidation. */
3664 return VERR_NOT_IMPLEMENTED;
3665 }
3666 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3667 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3668 }
3669
3670 case IOMMU_CMD_INV_INTR_TABLE:
3671 {
3672 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3673 * then. */
3674 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3675 return VINF_SUCCESS;
3676 }
3677
3678 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3679 {
3680 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3681 if (pThis->ExtFeat.n.u1PrefetchSup)
3682 {
3683 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
3684 return VINF_SUCCESS;
3685 }
3686 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3687 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3688 }
3689
3690 case IOMMU_CMD_COMPLETE_PPR_REQ:
3691 {
3692 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3693
3694 /* We don't support PPR requests yet. */
3695 Assert(!pThis->ExtFeat.n.u1PprSup);
3696 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3697 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3698 }
3699
3700 case IOMMU_CMD_INV_IOMMU_ALL:
3701 {
3702 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3703
3704 if (pThis->ExtFeat.n.u1InvAllSup)
3705 {
3706 /** @todo IOMMU: Invalidate all. Pretend success until then. */
3707 return VINF_SUCCESS;
3708 }
3709 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3710 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3711 }
3712 }
3713
3714 STAM_COUNTER_DEC(&pThis->StatCmd);
3715 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3716 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3717 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3718}
3719
3720
3721/**
3722 * The IOMMU command thread.
3723 *
3724 * @returns VBox status code.
3725 * @param pDevIns The IOMMU device instance.
3726 * @param pThread The command thread.
3727 */
3728static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3729{
3730 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3731
3732 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3733 return VINF_SUCCESS;
3734
3735 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3736 {
3737 /*
3738 * Sleep perpetually until we are woken up to process commands.
3739 */
3740 {
3741 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3742 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3743 if (!fSignaled)
3744 {
3745 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3746 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3747 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3748 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3749 break;
3750 Log5Func(("Woken up with rc=%Rrc\n", rc));
3751 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3752 }
3753 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3754 }
3755
3756 /*
3757 * Fetch and process IOMMU commands.
3758 */
3759 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
3760 * at a time) and is expensive due to calls to PGM for fetching guest memory.
3761 * We could optimize by fetching a bunch of commands at a time reducing
3762 * number of calls to PGM. In the longer run we could lock the memory and
3763 * mappings and accessing them directly. */
3764 IOMMU_LOCK(pDevIns);
3765
3766 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3767 if (Status.n.u1CmdBufRunning)
3768 {
3769 /* Get the offset we need to read the command from memory (circular buffer offset). */
3770 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3771 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3772 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3773 Assert(offHead < cbCmdBuf);
3774 while (offHead != pThis->CmdBufTailPtr.n.off)
3775 {
3776 /* Read the command from memory. */
3777 CMD_GENERIC_T Cmd;
3778 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3779 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3780 if (RT_SUCCESS(rc))
3781 {
3782 /* Increment the command buffer head pointer. */
3783 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3784 pThis->CmdBufHeadPtr.n.off = offHead;
3785
3786 /* Process the fetched command. */
3787 EVT_GENERIC_T EvtError;
3788 IOMMU_UNLOCK(pDevIns);
3789 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3790 IOMMU_LOCK(pDevIns);
3791 if (RT_FAILURE(rc))
3792 {
3793 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3794 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3795 {
3796 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3797 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3798 }
3799 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3800 {
3801 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3802 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", Cmd.n.u4Opcode));
3803 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3804 }
3805 break;
3806 }
3807 }
3808 else
3809 {
3810 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmd, rc));
3811 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3812 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3813 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3814 break;
3815 }
3816 }
3817 }
3818
3819 IOMMU_UNLOCK(pDevIns);
3820 }
3821
3822 LogFlowFunc(("Command thread terminating\n"));
3823 return VINF_SUCCESS;
3824}
3825
3826
3827/**
3828 * Wakes up the command thread so it can respond to a state change.
3829 *
3830 * @returns VBox status code.
3831 * @param pDevIns The IOMMU device instance.
3832 * @param pThread The command thread.
3833 */
3834static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3835{
3836 RT_NOREF(pThread);
3837 LogFlowFunc(("\n"));
3838 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3839 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3840}
3841
3842
3843/**
3844 * @callback_method_impl{FNPCICONFIGREAD}
3845 */
3846static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3847 unsigned cb, uint32_t *pu32Value)
3848{
3849 /** @todo IOMMU: PCI config read stat counter. */
3850 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3851 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3852 return rcStrict;
3853}
3854
3855
3856/**
3857 * @callback_method_impl{FNPCICONFIGWRITE}
3858 */
3859static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3860 unsigned cb, uint32_t u32Value)
3861{
3862 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3863
3864 /*
3865 * Discard writes to read-only registers that are specific to the IOMMU.
3866 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3867 * See PCI spec. 6.1. "Configuration Space Organization".
3868 */
3869 switch (uAddress)
3870 {
3871 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3872 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3873 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3874 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3875 {
3876 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3877 return VINF_SUCCESS;
3878 }
3879 }
3880
3881 IOMMU_LOCK(pDevIns);
3882
3883 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3884 switch (uAddress)
3885 {
3886 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3887 {
3888 if (pThis->IommuBar.n.u1Enable)
3889 {
3890 rcStrict = VINF_SUCCESS;
3891 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3892 break;
3893 }
3894
3895 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3896 if (pThis->IommuBar.n.u1Enable)
3897 {
3898 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3899 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3900 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3901 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
3902
3903 /* If the MMIO region is already mapped at the specified address, we're done. */
3904 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
3905 if (GCPhysMmioBasePrev == GCPhysMmioBase)
3906 {
3907 rcStrict = VINF_SUCCESS;
3908 break;
3909 }
3910
3911 /* Unmap the previous MMIO region (which is at a different address). */
3912 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
3913 {
3914 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
3915 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3916 if (RT_FAILURE(rcStrict))
3917 {
3918 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3919 break;
3920 }
3921 }
3922
3923 /* Map the newly specified MMIO region. */
3924 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
3925 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3926 if (RT_FAILURE(rcStrict))
3927 {
3928 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3929 break;
3930 }
3931 }
3932 else
3933 rcStrict = VINF_SUCCESS;
3934 break;
3935 }
3936
3937 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3938 {
3939 if (!pThis->IommuBar.n.u1Enable)
3940 pThis->IommuBar.au32[1] = u32Value;
3941 else
3942 {
3943 rcStrict = VINF_SUCCESS;
3944 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3945 }
3946 break;
3947 }
3948
3949 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3950 {
3951 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3952 RT_FALL_THRU();
3953 }
3954 default:
3955 {
3956 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3957 break;
3958 }
3959 }
3960
3961 IOMMU_UNLOCK(pDevIns);
3962
3963 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
3964 return rcStrict;
3965}
3966
3967
3968/**
3969 * @callback_method_impl{FNDBGFHANDLERDEV}
3970 */
3971static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3972{
3973 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3974 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3975 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3976
3977 bool fVerbose;
3978 if ( pszArgs
3979 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3980 fVerbose = true;
3981 else
3982 fVerbose = false;
3983
3984 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3985 /* Device Table Base Addresses (all segments). */
3986 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3987 {
3988 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3989 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3990 if (fVerbose)
3991 {
3992 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3993 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
3994 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3995 }
3996 }
3997 /* Command Buffer Base Address Register. */
3998 {
3999 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
4000 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
4001 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4002 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4003 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
4004 if (fVerbose)
4005 {
4006 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
4007 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4008 cEntries, cbBuffer);
4009 }
4010 }
4011 /* Event Log Base Address Register. */
4012 {
4013 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
4014 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
4015 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4016 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4017 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
4018 if (fVerbose)
4019 {
4020 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4021 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4022 cEntries, cbBuffer);
4023 }
4024 }
4025 /* IOMMU Control Register. */
4026 {
4027 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
4028 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
4029 if (fVerbose)
4030 {
4031 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
4032 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
4033 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
4034 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4035 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4036 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
4037 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
4038 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
4039 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
4040 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
4041 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
4042 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
4043 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
4044 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
4045 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
4046 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
4047 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
4048 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
4049 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
4050 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
4051 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
4052 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
4053 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
4054 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
4055 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
4056 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
4057 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
4058 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
4059 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
4060 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
4061 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
4062 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
4063 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
4064 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
4065 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
4066 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
4067 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
4068 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
4069 }
4070 }
4071 /* Exclusion Base Address Register. */
4072 {
4073 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
4074 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
4075 if (fVerbose)
4076 {
4077 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
4078 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
4079 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
4080 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
4081 }
4082 }
4083 /* Exclusion Range Limit Register. */
4084 {
4085 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
4086 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
4087 if (fVerbose)
4088 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
4089 }
4090 /* Extended Feature Register. */
4091 {
4092 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
4093 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
4094 if (fVerbose)
4095 {
4096 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
4097 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
4098 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
4099 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
4100 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
4101 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
4102 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
4103 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
4104 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
4105 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
4106 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
4107 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
4108 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
4109 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
4110 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
4111 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
4112 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
4113 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
4114 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
4115 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
4116 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
4117 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
4118 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
4119 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
4120 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
4121 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
4122 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
4123 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
4124 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
4125 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
4126 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
4127 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
4128 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
4129 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
4130 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
4131 }
4132 }
4133 /* PPR Log Base Address Register. */
4134 {
4135 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
4136 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
4137 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4138 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4139 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
4140 if (fVerbose)
4141 {
4142 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4143 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4144 cEntries, cbBuffer);
4145 }
4146 }
4147 /* Hardware Event (Hi) Register. */
4148 {
4149 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4150 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4151 if (fVerbose)
4152 {
4153 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4154 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4155 }
4156 }
4157 /* Hardware Event (Lo) Register. */
4158 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4159 /* Hardware Event Status. */
4160 {
4161 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4162 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4163 if (fVerbose)
4164 {
4165 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4166 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4167 }
4168 }
4169 /* Guest Virtual-APIC Log Base Address Register. */
4170 {
4171 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4172 uint8_t const uEncodedLen = GALogBar.n.u4Len;
4173 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4174 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4175 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4176 if (fVerbose)
4177 {
4178 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4179 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4180 cEntries, cbBuffer);
4181 }
4182 }
4183 /* Guest Virtual-APIC Log Tail Address Register. */
4184 {
4185 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4186 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4187 if (fVerbose)
4188 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4189 }
4190 /* PPR Log B Base Address Register. */
4191 {
4192 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4193 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4194 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4195 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4196 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4197 if (fVerbose)
4198 {
4199 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4200 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4201 cEntries, cbBuffer);
4202 }
4203 }
4204 /* Event Log B Base Address Register. */
4205 {
4206 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4207 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4208 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4209 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4210 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4211 if (fVerbose)
4212 {
4213 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4214 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4215 cEntries, cbBuffer);
4216 }
4217 }
4218 /* Device-Specific Feature Extension Register. */
4219 {
4220 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4221 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4222 if (fVerbose)
4223 {
4224 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4225 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4226 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4227 }
4228 }
4229 /* Device-Specific Control Extension Register. */
4230 {
4231 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4232 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4233 if (fVerbose)
4234 {
4235 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4236 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4237 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4238 }
4239 }
4240 /* Device-Specific Status Extension Register. */
4241 {
4242 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4243 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
4244 if (fVerbose)
4245 {
4246 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4247 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4248 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4249 }
4250 }
4251 /* Miscellaneous Information Register (Lo and Hi). */
4252 {
4253 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
4254 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
4255 if (fVerbose)
4256 {
4257 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
4258 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
4259 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
4260 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
4261 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
4262 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
4263 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
4264 }
4265 }
4266 /* MSI Capability Header. */
4267 {
4268 MSI_CAP_HDR_T MsiCapHdr;
4269 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4270 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4271 if (fVerbose)
4272 {
4273 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4274 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4275 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4276 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4277 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4278 }
4279 }
4280 /* MSI Address Register (Lo and Hi). */
4281 {
4282 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4283 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4284 MSIADDR MsiAddr;
4285 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4286 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4287 if (fVerbose)
4288 {
4289 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
4290 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
4291 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
4292 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
4293 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
4294 }
4295 }
4296 /* MSI Data. */
4297 {
4298 MSIDATA MsiData;
4299 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4300 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4301 if (fVerbose)
4302 {
4303 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
4304 MsiData.n.u8Vector);
4305 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
4306 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
4307 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4308 "level" : "edge");
4309 }
4310 }
4311 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4312 {
4313 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4314 MsiMapCapHdr.u32 = 0;
4315 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4316 if (fVerbose)
4317 {
4318 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4319 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4320 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4321 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4322 }
4323 }
4324 /* Performance Optimization Control Register. */
4325 {
4326 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4327 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4328 if (fVerbose)
4329 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4330 }
4331 /* XT (x2APIC) General Interrupt Control Register. */
4332 {
4333 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4334 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4335 if (fVerbose)
4336 {
4337 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4338 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4339 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4340 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4341 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4342 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4343 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4344 }
4345 }
4346 /* XT (x2APIC) PPR Interrupt Control Register. */
4347 {
4348 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4349 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4350 if (fVerbose)
4351 {
4352 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4353 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4354 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4355 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4356 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4357 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4358 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4359 }
4360 }
4361 /* XT (X2APIC) GA Log Interrupt Control Register. */
4362 {
4363 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4364 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4365 if (fVerbose)
4366 {
4367 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4368 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4369 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4370 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4371 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4372 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4373 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4374 }
4375 }
4376 /* MARC Registers. */
4377 {
4378 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4379 {
4380 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4381 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4382 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4383
4384 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4385 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4386 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4387 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4388
4389 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4390 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4391 }
4392 }
4393 /* Reserved Register. */
4394 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4395 /* Command Buffer Head Pointer Register. */
4396 {
4397 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4398 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4399 CmdBufHeadPtr.n.off);
4400 }
4401 /* Command Buffer Tail Pointer Register. */
4402 {
4403 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4404 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4405 CmdBufTailPtr.n.off);
4406 }
4407 /* Event Log Head Pointer Register. */
4408 {
4409 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4410 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4411 EvtLogHeadPtr.n.off);
4412 }
4413 /* Event Log Tail Pointer Register. */
4414 {
4415 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4416 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4417 EvtLogTailPtr.n.off);
4418 }
4419 /* Status Register. */
4420 {
4421 IOMMU_STATUS_T const Status = pThis->Status;
4422 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4423 if (fVerbose)
4424 {
4425 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4426 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4427 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4428 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4429 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4430 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4431 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4432 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4433 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4434 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4435 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4436 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4437 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4438 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4439 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4440 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4441 }
4442 }
4443 /* PPR Log Head Pointer. */
4444 {
4445 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4446 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4447 PprLogHeadPtr.n.off);
4448 }
4449 /* PPR Log Tail Pointer. */
4450 {
4451 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4452 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4453 PprLogTailPtr.n.off);
4454 }
4455 /* Guest Virtual-APIC Log Head Pointer. */
4456 {
4457 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4458 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4459 GALogHeadPtr.n.u12GALogPtr);
4460 }
4461 /* Guest Virtual-APIC Log Tail Pointer. */
4462 {
4463 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4464 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4465 GALogTailPtr.n.u12GALogPtr);
4466 }
4467 /* PPR Log B Head Pointer. */
4468 {
4469 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4470 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4471 PprLogBHeadPtr.n.off);
4472 }
4473 /* PPR Log B Tail Pointer. */
4474 {
4475 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4476 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4477 PprLogBTailPtr.n.off);
4478 }
4479 /* Event Log B Head Pointer. */
4480 {
4481 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4482 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4483 EvtLogBHeadPtr.n.off);
4484 }
4485 /* Event Log B Tail Pointer. */
4486 {
4487 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4488 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4489 EvtLogBTailPtr.n.off);
4490 }
4491 /* PPR Log Auto Response Register. */
4492 {
4493 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4494 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4495 if (fVerbose)
4496 {
4497 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4498 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4499 }
4500 }
4501 /* PPR Log Overflow Early Warning Indicator Register. */
4502 {
4503 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4504 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4505 if (fVerbose)
4506 {
4507 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4508 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4509 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4510 }
4511 }
4512 /* PPR Log Overflow Early Warning Indicator Register. */
4513 {
4514 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4515 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4516 if (fVerbose)
4517 {
4518 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4519 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4520 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4521 }
4522 }
4523}
4524
4525
4526/**
4527 * Dumps the DTE via the info callback helper.
4528 *
4529 * @param pHlp The info helper.
4530 * @param pDte The device table entry.
4531 * @param pszPrefix The string prefix.
4532 */
4533static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4534{
4535 AssertReturnVoid(pHlp);
4536 AssertReturnVoid(pDte);
4537 AssertReturnVoid(pszPrefix);
4538
4539 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4540 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4541 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4542 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4543 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4544 pDte->n.u40PageTableRootPtrLo << 12);
4545 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4546 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4547 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4548 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4549 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4550 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4551 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4552 (pDte->n.u21GstCr3TableRootPtrHi << 31)
4553 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
4554 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
4555 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4556 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4557 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4558 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4559 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4560 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4561 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4562 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4563 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4564 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4565 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4566 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4567 pHlp->pfnPrintf(pHlp, "\n");
4568
4569 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4570 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4571 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4572 {
4573 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4574 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4575 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4576 cbIntrTable);
4577 }
4578 else
4579 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4580 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4581 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4582 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4583 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4584 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4585 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4586 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4587 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4588 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4589 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4590 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4591 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4592 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4593 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4594 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4595 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4596}
4597
4598
4599/**
4600 * @callback_method_impl{FNDBGFHANDLERDEV}
4601 */
4602static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4603{
4604 if (pszArgs)
4605 {
4606 uint16_t uDevId = 0;
4607 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4608 if (RT_SUCCESS(rc))
4609 {
4610 DTE_T Dte;
4611 rc = iommuAmdReadDte(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4612 if (RT_SUCCESS(rc))
4613 {
4614 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4615 return;
4616 }
4617
4618 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4619 }
4620 else
4621 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4622 }
4623 else
4624 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4625}
4626
4627
4628#if 0
4629/**
4630 * @callback_method_impl{FNDBGFHANDLERDEV}
4631 */
4632static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4633{
4634 RT_NOREF(pszArgs);
4635
4636 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4637 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4638 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4639
4640 uint8_t cTables = 0;
4641 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4642 {
4643 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4644 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4645 if (GCPhysDevTab)
4646 ++cTables;
4647 }
4648
4649 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4650 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4651 if (!cTables)
4652 return;
4653
4654 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4655 {
4656 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4657 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4658 if (GCPhysDevTab)
4659 {
4660 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4661 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4662 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4663
4664 void *pvDevTab = RTMemAllocZ(cbDevTab);
4665 if (RT_LIKELY(pvDevTab))
4666 {
4667 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4668 if (RT_SUCCESS(rc))
4669 {
4670 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4671 {
4672 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
4673 if ( pDte->n.u1Valid
4674 || pDte->n.u1IntrMapValid)
4675 {
4676 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4677 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4678 }
4679 }
4680 pHlp->pfnPrintf(pHlp, "\n");
4681 }
4682 else
4683 {
4684 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4685 cbDevTab, rc);
4686 }
4687
4688 RTMemFree(pvDevTab);
4689 }
4690 else
4691 {
4692 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4693 return;
4694 }
4695 }
4696 }
4697}
4698#endif
4699
4700/**
4701 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4702 */
4703static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4704{
4705 /** @todo IOMMU: Save state. */
4706 RT_NOREF2(pDevIns, pSSM);
4707 LogFlowFunc(("\n"));
4708 return VERR_NOT_IMPLEMENTED;
4709}
4710
4711
4712/**
4713 * @callback_method_impl{FNSSMDEVLOADEXEC}
4714 */
4715static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4716{
4717 /** @todo IOMMU: Load state. */
4718 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4719 LogFlowFunc(("\n"));
4720 return VERR_NOT_IMPLEMENTED;
4721}
4722
4723
4724/**
4725 * @interface_method_impl{PDMDEVREG,pfnReset}
4726 */
4727static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4728{
4729 /*
4730 * Resets read-write portion of the IOMMU state.
4731 *
4732 * NOTE! State not initialized here is expected to be initialized during
4733 * device construction and remain read-only through the lifetime of the VM.
4734 */
4735 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4736 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4737 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4738
4739 IOMMU_LOCK_NORET(pDevIns);
4740
4741 LogFlowFunc(("\n"));
4742
4743 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4744
4745 pThis->CmdBufBaseAddr.u64 = 0;
4746 pThis->CmdBufBaseAddr.n.u4Len = 8;
4747
4748 pThis->EvtLogBaseAddr.u64 = 0;
4749 pThis->EvtLogBaseAddr.n.u4Len = 8;
4750
4751 pThis->Ctrl.u64 = 0;
4752 pThis->Ctrl.n.u1Coherent = 1;
4753 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4754
4755 pThis->ExclRangeBaseAddr.u64 = 0;
4756 pThis->ExclRangeLimit.u64 = 0;
4757
4758 pThis->PprLogBaseAddr.u64 = 0;
4759 pThis->PprLogBaseAddr.n.u4Len = 8;
4760
4761 pThis->HwEvtHi.u64 = 0;
4762 pThis->HwEvtLo = 0;
4763 pThis->HwEvtStatus.u64 = 0;
4764
4765 pThis->GALogBaseAddr.u64 = 0;
4766 pThis->GALogBaseAddr.n.u4Len = 8;
4767 pThis->GALogTailAddr.u64 = 0;
4768
4769 pThis->PprLogBBaseAddr.u64 = 0;
4770 pThis->PprLogBBaseAddr.n.u4Len = 8;
4771
4772 pThis->EvtLogBBaseAddr.u64 = 0;
4773 pThis->EvtLogBBaseAddr.n.u4Len = 8;
4774
4775 pThis->PerfOptCtrl.u32 = 0;
4776
4777 pThis->XtGenIntrCtrl.u64 = 0;
4778 pThis->XtPprIntrCtrl.u64 = 0;
4779 pThis->XtGALogIntrCtrl.u64 = 0;
4780
4781 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4782
4783 pThis->CmdBufHeadPtr.u64 = 0;
4784 pThis->CmdBufTailPtr.u64 = 0;
4785 pThis->EvtLogHeadPtr.u64 = 0;
4786 pThis->EvtLogTailPtr.u64 = 0;
4787
4788 pThis->Status.u64 = 0;
4789
4790 pThis->PprLogHeadPtr.u64 = 0;
4791 pThis->PprLogTailPtr.u64 = 0;
4792
4793 pThis->GALogHeadPtr.u64 = 0;
4794 pThis->GALogTailPtr.u64 = 0;
4795
4796 pThis->PprLogBHeadPtr.u64 = 0;
4797 pThis->PprLogBTailPtr.u64 = 0;
4798
4799 pThis->EvtLogBHeadPtr.u64 = 0;
4800 pThis->EvtLogBTailPtr.u64 = 0;
4801
4802 pThis->PprLogAutoResp.u64 = 0;
4803 pThis->PprLogOverflowEarly.u64 = 0;
4804 pThis->PprLogBOverflowEarly.u64 = 0;
4805
4806 pThis->IommuBar.u64 = 0;
4807 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4808 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4809
4810 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4811
4812 IOMMU_UNLOCK(pDevIns);
4813}
4814
4815
4816/**
4817 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4818 */
4819static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4820{
4821 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4822 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4823 LogFlowFunc(("\n"));
4824
4825 /* Close the command thread semaphore. */
4826 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4827 {
4828 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4829 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4830 }
4831 return VINF_SUCCESS;
4832}
4833
4834
4835/**
4836 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4837 */
4838static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4839{
4840 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4841 RT_NOREF(pCfg);
4842
4843 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4844 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4845 pThisCC->pDevInsR3 = pDevIns;
4846
4847 LogFlowFunc(("iInstance=%d\n", iInstance));
4848
4849 /*
4850 * Register the IOMMU with PDM.
4851 */
4852 PDMIOMMUREGR3 IommuReg;
4853 RT_ZERO(IommuReg);
4854 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4855 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
4856 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
4857 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4858 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4859 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4860 if (RT_FAILURE(rc))
4861 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4862 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4863 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4864 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4865 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4866 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4867 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4868 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4869 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4870
4871 /*
4872 * Initialize read-only PCI configuration space.
4873 */
4874 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4875 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4876
4877 /* Header. */
4878 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4879 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4880 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
4881 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4882 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4883 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4884 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4885 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4886 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4887 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4888 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4889 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4890 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4891 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4892
4893 /* Capability Header. */
4894 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4895 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4896 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4897 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
4898 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4899 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4900 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4901 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4902 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4903 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4904 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4905
4906 /* Base Address Register. */
4907 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4908 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4909
4910 /* IOMMU Range Register. */
4911 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4912
4913 /* Misc. Information Register. */
4914 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4915 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4916 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4917 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4918 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4919 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4920 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4921 uint32_t const uMiscInfoReg1 = 0;
4922 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4923 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4924
4925 /* MSI Capability Header register. */
4926 PDMMSIREG MsiReg;
4927 RT_ZERO(MsiReg);
4928 MsiReg.cMsiVectors = 1;
4929 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4930 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4931 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4932
4933 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4934#if 0
4935 /* MSI Address Lo. */
4936 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4937 /* MSI Address Hi. */
4938 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4939 /* MSI Data. */
4940 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4941#endif
4942
4943#if 0
4944 /** @todo IOMMU: I don't know if we need to support this, enable later if
4945 * required. */
4946 /* MSI Mapping Capability Header register. */
4947 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4948 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4949 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4950 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4951 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4952 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4953 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4954#endif
4955
4956 /*
4957 * Register the PCI function with PDM.
4958 */
4959 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4960 AssertLogRelRCReturn(rc, rc);
4961
4962 /*
4963 * Register MSI support for the PCI device.
4964 * This must be done -after- register it as a PCI device!
4965 */
4966 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4967 AssertRCReturn(rc, rc);
4968
4969 /*
4970 * Intercept PCI config. space accesses.
4971 */
4972 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4973 AssertLogRelRCReturn(rc, rc);
4974
4975 /*
4976 * Create the MMIO region.
4977 * Mapping of the region is done when software configures it via PCI config space.
4978 */
4979 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4980 NULL /* pvUser */,
4981 IOMMMIO_FLAGS_READ_DWORD_QWORD
4982 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
4983 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
4984 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
4985 "AMD-IOMMU", &pThis->hMmio);
4986 AssertLogRelRCReturn(rc, rc);
4987
4988 /*
4989 * Register saved state.
4990 */
4991 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4992 NULL, NULL, NULL,
4993 NULL, iommuAmdR3SaveExec, NULL,
4994 NULL, iommuAmdR3LoadExec, NULL);
4995 AssertLogRelRCReturn(rc, rc);
4996
4997 /*
4998 * Register debugger info items.
4999 */
5000 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
5001 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
5002#if 0
5003 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
5004#endif
5005
5006# ifdef VBOX_WITH_STATISTICS
5007 /*
5008 * Statistics.
5009 */
5010 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
5011 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
5012
5013 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
5014 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
5015
5016 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
5017 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
5018
5019 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
5020 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
5021
5022 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
5023 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
5024
5025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
5026 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
5027
5028 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
5029 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
5030
5031 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
5032 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
5033 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
5034 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
5035 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
5036 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
5037 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
5038 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
5039 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
5040# endif
5041
5042 /*
5043 * Create the command thread and its event semaphore.
5044 */
5045 char szDevIommu[64];
5046 RT_ZERO(szDevIommu);
5047 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
5048 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5049 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
5050 AssertLogRelRCReturn(rc, rc);
5051
5052 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5053 AssertLogRelRCReturn(rc, rc);
5054
5055 /*
5056 * Initialize read-only registers.
5057 * NOTE! Fields here must match their corresponding field in the ACPI tables.
5058 */
5059 /* Don't remove the commented lines below as it lets us see all features at a glance. */
5060 pThis->ExtFeat.u64 = 0;
5061 //pThis->ExtFeat.n.u1PrefetchSup = 0;
5062 //pThis->ExtFeat.n.u1PprSup = 0;
5063 //pThis->ExtFeat.n.u1X2ApicSup = 0;
5064 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
5065 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
5066 pThis->ExtFeat.n.u1InvAllSup = 1;
5067 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5068 pThis->ExtFeat.n.u1HwErrorSup = 1;
5069 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
5070 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
5071 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
5072 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
5073 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
5074 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
5075 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
5076 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5077 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
5078 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5079 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
5080 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5081 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5082 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5083 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5084 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5085 //pThis->ExtFeat.n.u2MarcSup = 0;
5086 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5087 //pThis->ExtFeat.n.u1PerfOptSup = 0;
5088 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5089 //pThis->ExtFeat.n.u1GstIoSup = 0;
5090 //pThis->ExtFeat.n.u1HostAccessSup = 0;
5091 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5092 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
5093 //pThis->ExtFeat.n.u1HostDirtySup = 0;
5094 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5095 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5096 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5097
5098 pThis->RsvdReg = 0;
5099
5100 pThis->DevSpecificFeat.u64 = 0;
5101 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
5102 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
5103
5104 pThis->DevSpecificCtrl.u64 = 0;
5105 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
5106 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
5107
5108 pThis->DevSpecificStatus.u64 = 0;
5109 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
5110 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
5111
5112 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
5113
5114 /*
5115 * Initialize parts of the IOMMU state as it would during reset.
5116 * Must be called -after- initializing PCI config. space registers.
5117 */
5118 iommuAmdR3Reset(pDevIns);
5119
5120 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
5121 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
5122 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
5123 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
5124 pThis->ExtFeat.u64));
5125 return VINF_SUCCESS;
5126}
5127
5128# else /* !IN_RING3 */
5129
5130/**
5131 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5132 */
5133static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5134{
5135 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5136 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5137 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5138
5139 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5140
5141 /* Set up the MMIO RZ handlers. */
5142 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5143 AssertRCReturn(rc, rc);
5144
5145 /* Set up the IOMMU RZ callbacks. */
5146 PDMIOMMUREGCC IommuReg;
5147 RT_ZERO(IommuReg);
5148 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5149 IommuReg.idxIommu = pThis->idxIommu;
5150 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
5151 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
5152 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5153 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5154 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5155 AssertRCReturn(rc, rc);
5156
5157 return VINF_SUCCESS;
5158}
5159
5160# endif /* !IN_RING3 */
5161
5162/**
5163 * The device registration structure.
5164 */
5165const PDMDEVREG g_DeviceIommuAmd =
5166{
5167 /* .u32Version = */ PDM_DEVREG_VERSION,
5168 /* .uReserved0 = */ 0,
5169 /* .szName = */ "iommu-amd",
5170 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
5171 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
5172 /* .cMaxInstances = */ ~0U,
5173 /* .uSharedVersion = */ 42,
5174 /* .cbInstanceShared = */ sizeof(IOMMU),
5175 /* .cbInstanceCC = */ sizeof(IOMMUCC),
5176 /* .cbInstanceRC = */ sizeof(IOMMURC),
5177 /* .cMaxPciDevices = */ 1,
5178 /* .cMaxMsixVectors = */ 0,
5179 /* .pszDescription = */ "IOMMU (AMD)",
5180#if defined(IN_RING3)
5181 /* .pszRCMod = */ "VBoxDDRC.rc",
5182 /* .pszR0Mod = */ "VBoxDDR0.r0",
5183 /* .pfnConstruct = */ iommuAmdR3Construct,
5184 /* .pfnDestruct = */ iommuAmdR3Destruct,
5185 /* .pfnRelocate = */ NULL,
5186 /* .pfnMemSetup = */ NULL,
5187 /* .pfnPowerOn = */ NULL,
5188 /* .pfnReset = */ iommuAmdR3Reset,
5189 /* .pfnSuspend = */ NULL,
5190 /* .pfnResume = */ NULL,
5191 /* .pfnAttach = */ NULL,
5192 /* .pfnDetach = */ NULL,
5193 /* .pfnQueryInterface = */ NULL,
5194 /* .pfnInitComplete = */ NULL,
5195 /* .pfnPowerOff = */ NULL,
5196 /* .pfnSoftReset = */ NULL,
5197 /* .pfnReserved0 = */ NULL,
5198 /* .pfnReserved1 = */ NULL,
5199 /* .pfnReserved2 = */ NULL,
5200 /* .pfnReserved3 = */ NULL,
5201 /* .pfnReserved4 = */ NULL,
5202 /* .pfnReserved5 = */ NULL,
5203 /* .pfnReserved6 = */ NULL,
5204 /* .pfnReserved7 = */ NULL,
5205#elif defined(IN_RING0)
5206 /* .pfnEarlyConstruct = */ NULL,
5207 /* .pfnConstruct = */ iommuAmdRZConstruct,
5208 /* .pfnDestruct = */ NULL,
5209 /* .pfnFinalDestruct = */ NULL,
5210 /* .pfnRequest = */ NULL,
5211 /* .pfnReserved0 = */ NULL,
5212 /* .pfnReserved1 = */ NULL,
5213 /* .pfnReserved2 = */ NULL,
5214 /* .pfnReserved3 = */ NULL,
5215 /* .pfnReserved4 = */ NULL,
5216 /* .pfnReserved5 = */ NULL,
5217 /* .pfnReserved6 = */ NULL,
5218 /* .pfnReserved7 = */ NULL,
5219#elif defined(IN_RC)
5220 /* .pfnConstruct = */ iommuAmdRZConstruct,
5221 /* .pfnReserved0 = */ NULL,
5222 /* .pfnReserved1 = */ NULL,
5223 /* .pfnReserved2 = */ NULL,
5224 /* .pfnReserved3 = */ NULL,
5225 /* .pfnReserved4 = */ NULL,
5226 /* .pfnReserved5 = */ NULL,
5227 /* .pfnReserved6 = */ NULL,
5228 /* .pfnReserved7 = */ NULL,
5229#else
5230# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5231#endif
5232 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
5233};
5234
5235#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5236
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