/* $Id: DevIommuAmd.cpp 83263 2020-03-11 16:34:33Z vboxsync $ */ /** @file * IOMMU - Input/Output Memory Management Unit - AMD implementation. */ /* * Copyright (C) 2020 Oracle Corporation * * This file is part of VirtualBox Open Source Edition (OSE), as * available from http://www.virtualbox.org. This file is free software; * you can redistribute it and/or modify it under the terms of the GNU * General Public License (GPL) as published by the Free Software * Foundation, in version 2 as it comes in the "COPYING" file of the * VirtualBox OSE distribution. VirtualBox OSE is distributed in the * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind. */ /********************************************************************************************************************************* * Header Files * *********************************************************************************************************************************/ #define LOG_GROUP LOG_GROUP_DEV_IOMMU #include #include "VBoxDD.h" /********************************************************************************************************************************* * Defined Constants And Macros * *********************************************************************************************************************************/ /** * @name Commands. * In accordance with the AMD spec. * @{ */ #define IOMMU_CMD_COMPLETION_WAIT 0x01 #define IOMMU_CMD_INV_DEVTAB_ENTRY 0x02 #define IOMMU_CMD_INV_IOMMU_PAGES 0x03 #define IOMMU_CMD_INV_IOTLB_PAGES 0x04 #define IOMMU_CMD_INV_INTR_TABLE 0x05 #define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06 #define IOMMU_CMD_COMPLETE_PPR_REQ 0x07 #define IOMMU_CMD_INV_IOMMU_ALL 0x08 /** @} */ /** * @name Event codes. * In accordance with the AMD spec. * @{ */ #define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01 #define IOMMU_EVT_IO_PAGE_FAULT 0x02 #define IOMMU_EVT_DEV_TAB_HARDWARE_ERROR 0x03 #define IOMMU_EVT_PAGE_TAB_HARDWARE_ERROR 0x04 #define IOMMU_EVT_ILLEGAL_COMMAND_ERROR 0x05 #define IOMMU_EVT_COMMAND_HARDWARE_ERROR 0x06 #define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07 #define IOMMU_EVT_INVALID_DEVICE_REQUEST 0x08 #define IOMMU_EVT_INVALID_PPR_REQUEST 0x09 #define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10 #define IOMMU_EVT_GUEST_EVENT_FAULT 0x11 /** @} */ /** * @name Capability Header. * In accordance with the AMD spec. * @{ */ /** CapId: Capability ID. */ #define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0 #define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff) /** CapPtr: Capability Pointer. */ #define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8 #define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00) /** CapType: Capability Type. */ #define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16 #define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000) /** CapRev: Capability Revision. */ #define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19 #define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000) /** IoTlbSup: IO TLB Support. */ #define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24 #define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000) /** HtTunnel: HyperTransport Tunnel translation support. */ #define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25 #define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000) /** NpCache: Not Present table entries Cached. */ #define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26 #define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000) /** EFRSup: Extended Feature Register (EFR) Supported. */ #define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27 #define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000) /** CapExt: Miscellaneous Information Register Supported . */ #define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28 #define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000) /** Bits 31:29 reserved. */ #define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29 #define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000) RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX, (CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31)); /** @} */ /** * @name Base Address Low Register. * In accordance with the AMD spec. * @{ */ /** Enable: Enables access to the address specified in the Base Address Register. */ #define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0 #define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001) /** Bits 13:1 reserved. */ #define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1 #define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe) /** Base Address[18:14]: Low Base address (Lo) of IOMMU control registers. */ #define IOMMU_BF_BASEADDR_LO_ADDR_LO_SHIFT 14 #define IOMMU_BF_BASEADDR_LO_ADDR_LO_MASK UINT32_C(0x0007c000) /** Base Address[31:19]: Low Base address (Hi) of IOMMU control registers. */ #define IOMMU_BF_BASEADDR_LO_ADDR_HI_SHIFT 19 #define IOMMU_BF_BASEADDR_LO_ADDR_HI_MASK UINT32_C(0xfff80000) RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX, (ENABLE, RSVD_1_13, ADDR_LO, ADDR_HI)); /** @} */ /** * @name Range Register. * In accordance with the AMD spec. * @{ */ /** UnitID: HyperTransport Unit ID. */ #define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0 #define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f) /** Bits 6:5 reserved. */ #define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5 #define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060) /** RngValid: Range valid. */ #define IOMMU_BF_RANGE_VALID_SHIFT 7 #define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080) /** BusNumber: Device range bus number. */ #define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8 #define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00) /** First Device. */ #define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16 #define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000) /** Last Device. */ #define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24 #define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000) RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX, (UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE)); /** @} */ /** * @name Miscellaneous Information Register 0. * In accordance with the AMD spec. * @{ */ /** MsiNum: MSI message number. */ #define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0 #define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f) /** GvaSize: Guest Virtual Address Size. */ #define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5 #define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0) /** PaSize: Physical Address Size. */ #define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8 #define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00) /** VaSize: Virtual Address Size. */ #define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15 #define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000) /** HtAtsResv: HyperTransport ATS Response Address range Reserved. */ #define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22 #define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000) /** Bits 26:23 reserved. */ #define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23 #define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000) /** MsiNumPPR: Peripheral Page Request MSI message number. */ #define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27 #define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000) RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX, (MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR)); /** @} */ /** * @name Miscellaneous Information Register 1. * In accordance with the AMD spec. * @{ */ /** MsiNumGA: MSI message number for guest vAPIC. */ #define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0 #define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f) /** Bits 31:5 reserved. */ #define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5 #define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0) RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX, (MSI_NUM_GA, RSVD_5_31)); /** @} */ /********************************************************************************************************************************* * Structures and Typedefs * *********************************************************************************************************************************/ /** * The Device ID. * In accordance with the AMD spec. */ typedef union { struct { uint16_t uFunction : 3; /**< Bits 2:0 - Function. */ uint16_t uDevice : 5; /**< Bits 7:3 - Device. */ uint16_t uBus : 8; /**< Bits 15:8 - Bus. */ } n; /** The unsigned integer view. */ uint16_t u; } DEVICE_ID_T; AssertCompileSize(DEVICE_ID_T, 2); /** * Device Table Entry (DTE). * In accordance with the AMD spec. */ typedef union { struct { uint32_t u1Valid : 1; /**< Bit 0 - V: Valid. */ uint32_t u1TranslationValid : 1; /**< Bit 1 - TV: Translation information Valid. */ uint32_t u5Rsvd0 : 5; /**< Bits 6:2 - Reserved. */ uint32_t u2Had : 2; /**< Bits 8:7 - HAD: Host Access Dirty. */ uint32_t u3Mode : 3; /**< Bits 11:9 - Mode: Paging mode. */ uint32_t u20PageTableRootPtrLo : 20; /**< Bits 31:12 - Page Table Root Pointer (Lo). */ uint32_t u20PageTableRootPtrHi : 20; /**< Bits 51:32 - Page Table Root Pointer (Hi). */ uint32_t u1Ppr : 1; /**< Bit 52 - PPR: Peripheral Page Request. */ uint32_t u1Grpr : 1; /**< Bit 53 - GRPR: Guest PPR Response with PASID. */ uint32_t u1GIov : 1; /**< Bit 54 - GIoV: Guest I/O Protection Valid. */ uint32_t u1GValid : 1; /**< Bit 55 - GV: Guest translation Valid. */ uint32_t u2Glx : 2; /**< Bits 57:56 - GLX: Guest Levels Translated. */ uint32_t u3GCr3TableRootPtrLo : 2; /**< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Pointer (Lo). */ uint32_t u1IoRead : 1; /**< Bit 61 - IR: I/O Read permission. */ uint32_t u1IoWrite : 1; /**< Bit 62 - IW: I/O Write permission. */ uint32_t u1Rsvd0 : 1; /**< Bit 63 - Reserved. */ uint32_t u16DomainId : 1; /**< Bits 79:64 - Domain ID. */ uint32_t u16GCr3TableRootPtrMed : 16; /**< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Pointer (Mid). */ uint32_t u1IotlbEnable : 1; /**< Bit 96 - IOTLB Enable. */ uint32_t u1SuppressPfEvents : 1; /**< Bit 97 - SE: Supress Page-fault events. */ uint32_t u1SuppressAllPfEvents : 1; /**< Bit 98 - SA: Supress All Page-fault events. */ uint32_t u2IoCtl : 1; /**< Bits 100:99 - IoCtl: Port I/O Control. */ uint32_t u1Cache : 1; /**< Bit 101 - Cache: IOTLB Cache Hint. */ uint32_t u1SnoopDisable : 1; /**< Bit 102 - SD: Snoop Disable. */ uint32_t u1AllowExclusion : 1; /**< Bit 103 - EX: Allow Exclusion. */ uint32_t u2SysMgt : 2; /**< Bits 105:104 - SysMgt: System Management message enable. */ uint32_t u1Rsvd1 : 1; /**< Bit 106 - Reserved. */ uint32_t u21Gcr3TableRootPtrHi : 21; /**< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Pointer (Hi). */ uint32_t u1IntrMapValid : 1; /**< Bit 128 - IV: Interrupt map Valid. */ uint32_t u4IntrTableLength : 4; /**< Bits 132:129 - IntTabLen: Interrupt Table Length. */ uint32_t u1IgnoreUnmappedIntrs : 1; /**< Bits 133 - IG: Ignore unmapped interrupts. */ uint32_t u26IntrTableRootPtr : 26; /**< Bits 159:134 - Interrupt Root Table Pointer (Lo). */ uint32_t u20IntrTableRootPtr : 20; /**< Bits 179:160 - Interrupt Root Table Pointer (Hi). */ uint32_t u4Rsvd0 : 4; /**< Bits 183:180 - Reserved. */ uint32_t u1InitPassthru : 1; /**< Bits 184 - INIT Pass-through. */ uint32_t u1ExtIntPassthru : 1; /**< Bits 185 - External Interrupt Pass-through. */ uint32_t u1NmiPassthru : 1; /**< Bits 186 - NMI Pass-through. */ uint32_t u1Rsvd2 : 1; /**< Bits 187 - Reserved. */ uint32_t u2IntrCtrl : 2; /**< Bits 189:188 - IntCtl: Interrupt Control. */ uint32_t u1Lint0Passthru : 1; /**< Bit 190 - Lint0Pass: LINT0 (Legacy PIC NMI) Pass-thru. */ uint32_t u1Lint1Passthru : 1; /**< Bit 191 - Lint1Pass: LINT1 (Legacy PIC NMI) Pass-thru. */ uint32_t u32Rsvd0; /**< Bits 223:192 - Reserved. */ uint32_t u22Rsvd0 : 22; /**< Bits 245:224 - Reserved. */ uint32_t u1AttrOverride : 1; /**< Bit 246 - AttrV: Attribute Override. */ uint32_t u1Mode0FC: 1; /**< Bit 247 - Mode0FC. */ uint32_t u8SnoopAttr: 1; /**< Bits 255:248 - Snoop Attribute. */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[8]; } DEV_TAB_ENTRY_T; AssertCompileSize(DEV_TAB_ENTRY_T, 32); /** * I/O Page Table Entry. * In accordance with the AMD spec. */ typedef union { struct { RT_GCC_EXTENSION uint64_t u1Present : 1; /**< Bit 0 - PR: Present. */ RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /**< Bits 4:1 - Ignored. */ RT_GCC_EXTENSION uint64_t u1Accessed : 1; /**< Bit 5 - A: Accessed. */ RT_GCC_EXTENSION uint64_t u1Dirty : 1; /**< Bit 6 - D: Dirty. */ RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /**< Bits 8:7 - Ignored. */ RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /**< Bits 11:9 - Next Level: Next page translation level. */ RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /**< Bits 51:12 - Page address. */ RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /**< Bits 58:52 - Reserved. */ RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /**< Bit 59 - U: Untranslated Access Only. */ RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /**< Bit 60 - FC: Force Coherent. */ RT_GCC_EXTENSION uint64_t u1IoRead : 1; /**< Bit 61 - IR: I/O Read permission. */ RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /**< Bit 62 - IW: I/O Wead permission. */ RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /**< Bit 63 - Ignored. */ } n; /** The 64-bit unsigned integer view. */ uint64_t u; } IOPTE_T; AssertCompileSize(IOPTE_T, 8); /** * I/O Page Directory Entry. * In accordance with the AMD spec. */ typedef union { struct { RT_GCC_EXTENSION uint64_t u1Present : 1; /**< Bit 0 - PR: Present. */ RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /**< Bits 4:1 - Ignored. */ RT_GCC_EXTENSION uint64_t u1Accessed : 1; /**< Bit 5 - A: Accessed. */ RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /**< Bits 8:6 - Ignored. */ RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /**< Bits 11:9 - Next Level: Next page translation level. */ RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /**< Bits 51:12 - Page address (Next Table Address). */ RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /**< Bits 60:52 - Reserved. */ RT_GCC_EXTENSION uint64_t u1IoRead : 1; /**< Bit 61 - IR: I/O Read permission. */ RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /**< Bit 62 - IW: I/O Wead permission. */ RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /**< Bit 63 - Ignored. */ } n; /** The 64-bit unsigned integer view. */ uint64_t u; } IOPDE_T; AssertCompileSize(IOPDE_T, 8); /** * Interrupt Remapping Table Entry. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u1RemapEnable : 1; /**< Bit 0 - RemapEn: Remap enable. */ uint32_t u1SuppressPf : 1; /**< Bit 1 - SupIOPF: Supress I/O Page Fault. */ uint32_t u3IntrType : 1; /**< Bits 4:2 - IntType: Interrupt Type. */ uint32_t u1ReqEoi : 1; /**< Bit 5 - RqEoi: Request EOI. */ uint32_t u1DstMode : 1; /**< Bit 6 - DM: Destination Mode. */ uint32_t u1GuestMode : 1; /**< Bit 7 - GuestMode. */ uint32_t u8Dst : 8; /**< Bits 15:8 - Destination. */ uint32_t u8Vector : 8; /**< Bits 23:16 - Vector. */ uint32_t u8Rsvd0 : 8; /**< Bits 31:24 - Reserved. */ } n; /** The 32-bit unsigned integer view. */ uint32_t u; } IRTE_T; AssertCompileSize(IRTE_T, 4); /** * Command: Generic Command Buffer Entry. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u32Operand1Lo; /**< Bits 31:0 - Operand 1 (Lo). */ uint32_t u32Operand1Hi : 28; /**< Bits 59:32 - Operand 1 (Hi). */ uint32_t u4Opcode : 4; /**< Bits 63:60 - Op Code. */ uint64_t u64Operand2; /**< Bits 127:64 - Operand 2. */ } n; /** The 64-bit unsigned integer view. */ uint64_t au64[2]; } CMD_GENERIC_T; AssertCompileSize(CMD_GENERIC_T, 16); /** * Command: COMPLETION_WAIT. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u1Store : 1; /**< Bit 0 - S: Completion Store. */ uint32_t u1Interrupt : 1; /**< Bit 1 - I: Completion Interrupt. */ uint32_t u1Flush : 1; /**< Bit 2 - F: Flush Queue. */ uint32_t u29StoreAddrLo : 29; /**< Bits 31:3 - Store Address (Lo). */ uint32_t u20StoreAddrHi : 20; /**< Bits 51:32 - Store Address (Hi). */ uint32_t u8Rsvd0 : 8; /**< Bits 59:52 - Reserved. */ uint32_t u4OpCode : 4; /**< Bits 63:60 - OpCode (Command). */ uint64_t u64StoreData; /**< Bits 127:64 - Store Data. */ } n; /** The 64-bit unsigned integer view. */ uint32_t au64[2]; } CMD_COMPLETION_WAIT_T; AssertCompileSize(CMD_COMPLETION_WAIT_T, 16); /** * Command: INVALIDATE_DEVTAB_ENTRY. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - DeviceID. */ uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */ uint32_t u28Rsvd0 : 28; /**< Bits 59:32 - Reserved. */ uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */ uint64_t u64Rsvd0; /**< Bits 127:64 - Reserved. */ } n; /** The 64-bit unsigned integer view. */ uint64_t au64[2]; } CMD_INV_DEV_TAB_ENTRY_T; AssertCompileSize(CMD_INV_DEV_TAB_ENTRY_T, 16); /** * Command: INVALIDATE_IOMMU_PAGES. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u20Pasid : 20; /**< Bits 19:0 - PASID: Process Address-Space ID. */ uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. */ uint32_t u16DomainId : 16; /**< Bits 47:32 - Domain ID. */ uint32_t u12Rsvd1 : 12; /**< Bits 59:48 - Reserved. */ uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */ uint32_t u1Size : 1; /**< Bit 64 - S: Size. */ uint32_t u1PageDirEntries : 1; /**< Bit 65 - PDE: Page Directory Entries. */ uint32_t u1GuestOrNested : 1; /**< Bit 66 - GN: Guest (GPA) or Nested (GVA). */ uint32_t u9Rsvd0 : 9; /**< Bits 75:67 - Reserved. */ uint32_t u20AddrLo : 20; /**< Bits 95:76 - Address (Lo). */ uint32_t u32AddrHi; /**< Bits 127:96 - Address (Hi). */ } n; /** The 64-bit unsigned integer view. */ uint64_t au64[2]; } CMD_INV_IOMMU_PAGES_T; AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16); /** * Command: INVALIDATE_IOTLB_PAGES. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - Device ID. */ uint8_t u8PasidLo; /**< Bits 23:16 - PASID: Process Address-Space ID (Lo). */ uint8_t u8MaxPend; /**< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. */ uint32_t u16QueueId : 16; /**< Bits 47:32 - Queue ID. */ uint32_t u12PasidHi : 12; /**< Bits 59:48 - PASID: Process Address-Space ID (Hi). */ uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */ uint32_t u1Size : 1; /**< Bit 64 - S: Size. */ uint32_t u1Rsvd0: 1; /**< Bit 65 - Reserved. */ uint32_t u1GuestOrNested : 1; /**< Bit 66 - GN: Guest (GPA) or Nested (GVA). */ uint32_t u1Rsvd1 : 1; /**< Bit 67 - Reserved. */ uint32_t u2Type : 2; /**< Bit 69:68 - Type. */ uint32_t u6Rsvd0 : 6; /**< Bits 75:70 - Reserved. */ uint32_t u20AddrLo : 20; /**< Bits 95:76 - Address (Lo). */ uint32_t u32AddrHi; /**< Bits 127:96 - Address (Hi). */ } n; /** The 64-bit unsigned integer view. */ uint64_t au64[2]; } CMD_INV_IOTLB_PAGES_T; AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16); /** * Command: INVALIDATE_INTR_TABLE. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - Device ID. */ uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */ uint32_t u32Rsvd0 : 28; /**< Bits 59:32 - Reserved. */ uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */ uint64_t u64Rsvd0; /**< Bits 127:64 - Reserved. */ } u; /** The 64-bit unsigned integer view. */ uint64_t au64[2]; } CMD_INV_INTR_TABLE_T; AssertCompileSize(CMD_INV_INTR_TABLE_T, 16); /** * Command: COMPLETE_PPR_REQ. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - Device ID. */ uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */ uint32_t u20Pasid : 20; /**< Bits 51:32 - PASID: Process Address-Space ID. */ uint32_t u8Rsvd0 : 8; /**< Bits 59:52 - Reserved. */ uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */ uint32_t u2Rsvd0 : 2; /**< Bits 65:64 - Reserved. */ uint32_t u1GuestOrNested : 1; /**< Bit 66 - GN: Guest (GPA) or Nested (GVA). */ uint32_t u29Rsvd0 : 29; /**< Bits 95:67 - Reserved. */ uint32_t u16CompletionTag : 16; /**< Bits 111:96 - Completion Tag. */ uint32_t u16Rsvd1 : 16; /**< Bits 127:112 - Reserved. */ } n; /** The 64-bit unsigned integer view. */ uint64_t au64[2]; } CMD_COMPLETE_PPR_REQ_T; AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16); /** * Command: INV_IOMMU_ALL. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u32Rsvd0; /**< Bits 31:0 - Reserved. */ uint32_t u28Rsvd0 : 28; /**< Bits 59:32 - Reserved. */ uint32_t u4OpCode : 4; /**< Bits 63:60 - Op Code (Command). */ uint64_t u64Rsvd0; /**< Bits 127:64 - Reserved. */ } n; /** The 64-bit unsigned integer view. */ uint64_t au64[2]; } CMD_IOMMU_ALL_T; AssertCompileSize(CMD_IOMMU_ALL_T, 16); /** * Event Log Entry: Generic. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u32Operand1Lo; /**< Bits 31:0 - Operand 1 (Lo). */ uint32_t u32Operand1Hi : 28; /**< Bits 59:32 - Operand 1 (Hi). */ uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. */ uint32_t u32Operand2Lo; /**< Bits 95:64 - Operand 2 (Lo). */ uint32_t u32Operand2Hi; /**< Bits 127:96 - Operand 2 (Hi). */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_GENERIC_T; AssertCompileSize(EVT_GENERIC_T, 16); /** * Event Log Entry: ILLEGAL_DEV_TAB_ENTRY. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - Device ID. */ uint16_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). */ uint16_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. */ uint16_t u16PasidLo; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). */ uint16_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). */ uint16_t u2Rsvd0 : 2; /**< Bits 50:49 - Reserved. */ uint16_t u1Interrupt : 1; /**< Bit 51 - I: Interrupt. */ uint16_t u1Rsvd0 : 1; /**< Bit 52 - Reserved. */ uint16_t u1ReadWrite : 1; /**< Bit 53 - RW: Read/Write. */ uint16_t u1Rsvd1 : 1; /**< Bit 54 - Reserved. */ uint16_t u1RsvdZero : 1; /**< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. */ uint16_t u1Translation : 1; /**< Bit 56 - TN: Translation. */ uint16_t u3Rsvd0 : 3; /**< Bits 59:57 - Reserved. */ uint16_t u4EventCode : 4; /**< Bits 63:60 - Event code. */ uint32_t u2Rsvd1 : 2; /**< Bits 65:64 - Reserved. */ uint32_t u30AddrLo : 2; /**< Bits 95:66 - Address: Device Virtual Address (Lo). */ uint32_t u30AddrHi; /**< Bits 127:96 - Address: Device Virtual Address (Hi). */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_ILLEGAL_DEV_TAB_ENTRY_T; AssertCompileSize(EVT_ILLEGAL_DEV_TAB_ENTRY_T, 16); /** * Event Log Entry: IO_PAGE_FAULT_EVENT. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - Device ID. */ uint16_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). */ uint16_t u16DomainOrPasidLo; /**< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). */ uint16_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). */ uint16_t u1NoExecute : 1; /**< Bit 49 - NX: No Execute. */ uint16_t u1User : 1; /**< Bit 50 - US: User/Supervisor. */ uint16_t u1Interrupt : 1; /**< Bit 51 - I: Interrupt. */ uint16_t u1Present : 1; /**< Bit 52 - PR: Present. */ uint16_t u1ReadWrite : 1; /**< Bit 53 - RW: Read/Write. */ uint16_t u1Perm : 1; /**< Bit 54 - PE: Permission Indicator. */ uint16_t u1RsvdZero : 1; /**< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. */ uint16_t u1Translation : 1; /**< Bit 56 - TN: Translation. */ uint16_t u3Rsvd0 : 3; /**< Bit 59:57 - Reserved. */ uint16_t u4EventCode : 4; /**< Bits 63:60 - Event code. */ uint64_t u64Addr; /**< Bits 127:64 - Address: Device Virtual Address. */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_IO_PAGE_FAULT_T; AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16); /** * Event Log Entry: DEV_TAB_HARDWARE_ERROR. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - Device ID. */ uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */ uint32_t u19Rsvd0 : 19; /**< Bits 50:32 - Reserved. */ uint32_t u1Intr : 1; /**< Bit 51 - I: Interrupt. */ uint32_t u1Rsvd0 : 1; /**< Bit 52 - Reserved. */ uint32_t u1ReadWrite : 1; /**< Bit 53 - RW: Read/Write. */ uint32_t u2Rsvd0 : 2; /**< Bits 55:54 - Reserved. */ uint32_t u1Translation : 1; /**< Bit 56 - TR: Translation. */ uint32_t u2Type : 2; /**< Bits 58:57 - Type: The type of hardware error. */ uint32_t u1Rsvd1 : 1; /**< Bit 59 - Reserved. */ uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. */ uint32_t u4Rsvd0 : 4; /**< Bits 67:64 - Reserved. */ uint32_t u28AddrLo : 28; /**< Bits 95:68 - Address: System Physical Address (Lo). */ uint32_t u32AddrHi; /**< Bits 127:96 - Address: System Physical Address (Hi). */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_DEV_TAB_HARDWARE_ERROR; AssertCompileSize(EVT_DEV_TAB_HARDWARE_ERROR, 16); /** * Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - Device ID. */ uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved. */ uint32_t u16DomainOrPasidLo : 16; /**< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). */ uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). */ uint32_t u2Rsvd0 : 2; /**< Bits 50:49 - Reserved. */ uint32_t u1Interrupt : 1; /**< Bit 51 - I: Interrupt. */ uint32_t u1Rsvd0 : 1; /**< Bit 52 - Reserved. */ uint32_t u1ReadWrite : 1; /**< Bit 53 - RW: Read/Write. */ uint32_t u2Rsvd1 : 2; /**< Bit 55:54 - Reserved. */ uint32_t u1Translation : 1; /**< Bit 56 - TR: Translation. */ uint32_t u2Type : 2; /**< Bits 58:57 - Type: The type of hardware error. */ uint32_t u1Rsvd1 : 1; /**< Bit 59 - Reserved. */ uint32_t u4EventCode : 4; /**< Bit 63:60 - Event code. */ /** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but * table 58 mentions Addr[31:4]. Looks like a typo in the figure. Use * table as it makes more sense and matches address size in * EVT_DEV_TAB_HARDWARE_ERROR. See AMD AMD IOMMU spec (3.05-PUB, Jan * 2020). */ uint32_t u4Rsvd0 : 4; /**< Bits 67:64 - Reserved. */ uint32_t u28AddrLo : 28; /**< Bits 95:68 - Address: SPA of page table entry (Lo). */ uint32_t u32AddrHi; /**< Bits 127:96 - Address: SPA of page table entry (Hi). */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_PAGE_TAB_HARDWARE_ERROR; AssertCompileSize(EVT_PAGE_TAB_HARDWARE_ERROR, 16); /** * Event Log Entry: ILLEGAL_COMMAND_ERROR. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u32Rsvd0; /**< Bits 31:0 - Reserved. */ uint32_t u28Rsvd0 : 28; /**< Bits 47:32 - Reserved. */ uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. */ uint32_t u4Rsvd0 : 4; /**< Bits 67:64 - Reserved. */ uint32_t u28AddrLo : 28; /**< Bits 95:68 - Address: SPA of the invalid command (Lo). */ uint32_t u32AddrHi; /**< Bits 127:96 - Address: SPA of the invalid command (Hi). */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_ILLEGAL_COMMAND_ENTRY; AssertCompileSize(EVT_ILLEGAL_COMMAND_ENTRY, 16); /** * Event Log Entry: COMMAND_HARDWARE_ERROR. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u32Rsvd0; /**< Bits 31:0 - Reserved. */ uint32_t u4Rsvd0 : 4; /**< Bits 35:32 - Reserved. */ uint32_t u28AddrLo : 28; /**< Bits 63:36 - Address: SPA of the attempted access (Lo). */ uint32_t u32AddrHi; /**< Bits 95:64 - Address: SPA of the attempted access (Hi). */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[3]; } EVT_COMMAND_HARDWARE_ERROR; AssertCompileSize(EVT_COMMAND_HARDWARE_ERROR, 12); /** * Event Log Entry: IOTLB_INV_TIMEOUT. * In accordance with the AMD spec. */ typedef union { struct { uint16_t u16DeviceId; /**< Bits 15:0 - Device ID. */ uint16_t u16Rsvd0; /**< Bits 31:16 - Reserved.*/ uint32_t u28Rsvd0 : 28; /**< Bits 59:32 - Reserved. */ uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. */ uint32_t u4Rsvd0 : 4; /**< Bits 67:64 - Reserved. */ uint32_t u28AddrLo : 28; /**< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). */ uint32_t u32AddrHi; /**< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_IOTLB_INV_TIMEOUT; AssertCompileSize(EVT_IOTLB_INV_TIMEOUT, 16); /** * Event Log Entry: INVALID_DEVICE_REQUEST. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u16DeviceId : 16; /***< Bits 15:0 - Device ID. */ uint32_t u4PasidHi : 4; /***< Bits 19:16 - PASID: Process Address-Space ID (Hi). */ uint32_t u12Rsvd0 : 12; /***< Bits 31:20 - Reserved. */ uint32_t u16PasidLo : 16; /***< Bits 47:32 - PASID: Process Address-Space ID (Lo). */ uint32_t u1GuestOrNested : 1; /***< Bit 48 - GN: Guest (GPA) or Nested (GVA). */ uint32_t u1User : 1; /***< Bit 49 - US: User/Supervisor. */ uint32_t u6Rsvd0 : 6; /***< Bits 55:50 - Reserved. */ uint32_t u1Translation: 1; /***< Bit 56 - TR: Translation. */ uint32_t u3Type: 3; /***< Bits 59:57 - Type: The type of hardware error. */ uint32_t u4EventCode : 4; /***< Bits 63:60 - Event code. */ uint64_t u64Addr; /***< Bits 127:64 - Address: Translation or access address. */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_INVALID_DEVICE_REQUEST; AssertCompileSize(EVT_INVALID_DEVICE_REQUEST, 16); /** * Event Log Entry: EVENT_COUNTER_ZERO. * In accordance with the AMD spec. */ typedef union { struct { uint32_t u32Rsvd0; /**< Bits 31:0 - Reserved. */ uint32_t u28Rsvd0 : 28; /**< Bits 59:32 - Reserved. */ uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. */ uint32_t u20CounterNoteHi : 20; /**< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). */ uint32_t u12Rsvd0 : 12; /**< Bits 95:84 - Reserved. */ uint32_t u32CounterNoteLo; /**< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). */ } n; /** The 32-bit unsigned integer view. */ uint32_t au32[4]; } EVT_EVENT_COUNTER_ZERO; AssertCompileSize(EVT_EVENT_COUNTER_ZERO, 16); /** * The IOMMU device state. */ typedef struct IOMMU { } IOMMU; /** Pointer to the IOMMU device state. */ typedef struct IOMMU *PIOMMU; /** * The ring-3 IOMMU device state. */ typedef struct IOMMUR3 { } IOMMUR3; /** Pointer to the ring-3 IOMMU device state. */ typedef IOMMUR3 *PIOMMUR3; /** * The ring-0 IOMMU device state. */ typedef struct IOMMUR0 { uint64_t uUnused; } IOMMUR0; /** Pointer to the ring-0 IOMMU device state. */ typedef IOMMUR0 *PIOMMUR0; /** * The raw-mode IOMMU device state. */ typedef struct IOMMURC { uint64_t uUnused; } IOMMURC; /** Pointer to the raw-mode IOMMU device state. */ typedef IOMMURC *PIOMMURC; /** The IOMMU device state for the current context. */ typedef CTX_SUFF(IOMMU) IOMMUCC; /** Pointer to the IOMMU device state for the current context. */ typedef CTX_SUFF(PIOMMU) PIOMMUCC; #ifndef VBOX_DEVICE_STRUCT_TESTCASE # ifdef IN_RING3 /** * @interface_method_impl{PDMDEVREG,pfnReset} */ static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns) { NOREF(pDevIns); } /** * @interface_method_impl{PDMDEVREG,pfnDestruct} */ static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns) { NOREF(pDevIns); return VINF_SUCCESS; } /** * @interface_method_impl{PDMDEVREG,pfnConstruct} */ static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg) { NOREF(iInstance); NOREF(pCfg); PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); #if 0 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU); PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC); PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3; int rc; LogFlowFunc(("\n")); /* * Validate and read the configuration. */ //PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "", ""); #endif return VINF_SUCCESS; } # else /* !IN_RING3 */ /** * @callback_method_impl{PDMDEVREGR0,pfnConstruct} */ static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns) { PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); return VINF_SUCCESS; } # endif /* !IN_RING3 */ /** * The device registration structure. */ const PDMDEVREG g_DeviceIommuAmd = { /* .u32Version = */ PDM_DEVREG_VERSION, /* .uReserved0 = */ 0, /* .szName = */ "iommu-amd", /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE, /* .fClass = */ PDM_DEVREG_CLASS_BUS_ISA, /* Instantiate after PDM_DEVREG_CLASS_BUS_PCI */ /* .cMaxInstances = */ ~0U, /* .uSharedVersion = */ 42, /* .cbInstanceShared = */ sizeof(IOMMU), /* .cbInstanceCC = */ sizeof(IOMMUCC), /* .cbInstanceRC = */ sizeof(IOMMURC), /* .cMaxPciDevices = */ 1, /* .cMaxMsixVectors = */ 0, /* .pszDescription = */ "IOMMU (AMD)", #if defined(IN_RING3) /* .pszRCMod = */ "VBoxDDRC.rc", /* .pszR0Mod = */ "VBoxDDR0.r0", /* .pfnConstruct = */ iommuAmdR3Construct, /* .pfnDestruct = */ iommuAmdR3Destruct, /* .pfnRelocate = */ NULL, /* .pfnMemSetup = */ NULL, /* .pfnPowerOn = */ NULL, /* .pfnReset = */ iommuAmdR3Reset, /* .pfnSuspend = */ NULL, /* .pfnResume = */ NULL, /* .pfnAttach = */ NULL, /* .pfnDetach = */ NULL, /* .pfnQueryInterface = */ NULL, /* .pfnInitComplete = */ NULL, /* .pfnPowerOff = */ NULL, /* .pfnSoftReset = */ NULL, /* .pfnReserved0 = */ NULL, /* .pfnReserved1 = */ NULL, /* .pfnReserved2 = */ NULL, /* .pfnReserved3 = */ NULL, /* .pfnReserved4 = */ NULL, /* .pfnReserved5 = */ NULL, /* .pfnReserved6 = */ NULL, /* .pfnReserved7 = */ NULL, #elif defined(IN_RING0) /* .pfnEarlyConstruct = */ NULL, /* .pfnConstruct = */ iommuAmdRZConstruct, /* .pfnDestruct = */ NULL, /* .pfnFinalDestruct = */ NULL, /* .pfnRequest = */ NULL, /* .pfnReserved0 = */ NULL, /* .pfnReserved1 = */ NULL, /* .pfnReserved2 = */ NULL, /* .pfnReserved3 = */ NULL, /* .pfnReserved4 = */ NULL, /* .pfnReserved5 = */ NULL, /* .pfnReserved6 = */ NULL, /* .pfnReserved7 = */ NULL, #elif defined(IN_RC) /* .pfnConstruct = */ iommuAmdRZConstruct, /* .pfnReserved0 = */ NULL, /* .pfnReserved1 = */ NULL, /* .pfnReserved2 = */ NULL, /* .pfnReserved3 = */ NULL, /* .pfnReserved4 = */ NULL, /* .pfnReserved5 = */ NULL, /* .pfnReserved6 = */ NULL, /* .pfnReserved7 = */ NULL, #else # error "Not in IN_RING3, IN_RING0 or IN_RC!" #endif /* .u32VersionEnd = */ PDM_DEVREG_VERSION }; #endif /* !VBOX_DEVICE_STRUCT_TESTCASE */