DevIommuAmd.cpp@ 83448

Last change on this file since 83448 was 83448, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 Bits.
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1	/* $Id: DevIommuAmd.cpp 83448 2020-03-26 18:09:34Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/vmm/pdmdev.h>
24
25	#include "VBoxDD.h"
26
27
28	/*********************************************************************************************************************************
29	* Defined Constants And Macros *
30	*********************************************************************************************************************************/
31	/**
32	* @name Commands.
33	* In accordance with the AMD spec.
34	* @{
35	*/
36	#define IOMMU_CMD_COMPLETION_WAIT 0x01
37	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
38	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
39	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
40	#define IOMMU_CMD_INV_INTR_TABLE 0x05
41	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
42	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
43	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
44	/** @} */
45
46	/**
47	* @name Event codes.
48	* In accordance with the AMD spec.
49	* @{
50	*/
51	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
52	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
53	#define IOMMU_EVT_DEV_TAB_HARDWARE_ERROR 0x03
54	#define IOMMU_EVT_PAGE_TAB_HARDWARE_ERROR 0x04
55	#define IOMMU_EVT_ILLEGAL_COMMAND_ERROR 0x05
56	#define IOMMU_EVT_COMMAND_HARDWARE_ERROR 0x06
57	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
58	#define IOMMU_EVT_INVALID_DEVICE_REQUEST 0x08
59	#define IOMMU_EVT_INVALID_PPR_REQUEST 0x09
60	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
61	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
62	/** @} */
63
64	/**
65	* @name Capability Header.
66	* In accordance with the AMD spec.
67	* @{
68	*/
69	/** CapId: Capability ID. */
70	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
71	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
72	/** CapPtr: Capability Pointer. */
73	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
74	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
75	/** CapType: Capability Type. */
76	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
77	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
78	/** CapRev: Capability Revision. */
79	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
80	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
81	/** IoTlbSup: IO TLB Support. */
82	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
83	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
84	/** HtTunnel: HyperTransport Tunnel translation support. */
85	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
86	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
87	/** NpCache: Not Present table entries Cached. */
88	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
89	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
90	/** EFRSup: Extended Feature Register (EFR) Supported. */
91	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
92	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
93	/** CapExt: Miscellaneous Information Register Supported . */
94	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
95	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
96	/** Bits 31:29 reserved. */
97	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
98	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
99	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
100	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
101	/** @} */
102
103	/**
104	* @name Base Address Low Register.
105	* In accordance with the AMD spec.
106	* @{
107	*/
108	/** Enable: Enables access to the address specified in the Base Address Register. */
109	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
110	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
111	/** Bits 13:1 reserved. */
112	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
113	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
114	/** Base Address[18:14]: Low Base address (Lo) of IOMMU control registers. */
115	#define IOMMU_BF_BASEADDR_LO_ADDR_LO_SHIFT 14
116	#define IOMMU_BF_BASEADDR_LO_ADDR_LO_MASK UINT32_C(0x0007c000)
117	/** Base Address[31:19]: Low Base address (Hi) of IOMMU control registers. */
118	#define IOMMU_BF_BASEADDR_LO_ADDR_HI_SHIFT 19
119	#define IOMMU_BF_BASEADDR_LO_ADDR_HI_MASK UINT32_C(0xfff80000)
120	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
121	(ENABLE, RSVD_1_13, ADDR_LO, ADDR_HI));
122	/** @} */
123
124	/**
125	* @name Range Register.
126	* In accordance with the AMD spec.
127	* @{
128	*/
129	/** UnitID: HyperTransport Unit ID. */
130	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
131	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
132	/** Bits 6:5 reserved. */
133	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
134	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
135	/** RngValid: Range valid. */
136	#define IOMMU_BF_RANGE_VALID_SHIFT 7
137	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
138	/** BusNumber: Device range bus number. */
139	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
140	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
141	/** First Device. */
142	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
143	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
144	/** Last Device. */
145	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
146	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
147	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
148	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
149	/** @} */
150
151	/**
152	* @name Miscellaneous Information Register 0.
153	* In accordance with the AMD spec.
154	* @{
155	*/
156	/** MsiNum: MSI message number. */
157	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
158	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
159	/** GvaSize: Guest Virtual Address Size. */
160	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
161	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
162	/** PaSize: Physical Address Size. */
163	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
164	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
165	/** VaSize: Virtual Address Size. */
166	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
167	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
168	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
169	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
170	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
171	/** Bits 26:23 reserved. */
172	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
173	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
174	/** MsiNumPPR: Peripheral Page Request MSI message number. */
175	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
176	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
177	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
178	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
179	/** @} */
180
181	/**
182	* @name Miscellaneous Information Register 1.
183	* In accordance with the AMD spec.
184	* @{
185	*/
186	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
187	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
188	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
189	/** Bits 31:5 reserved. */
190	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
191	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
192	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
193	(MSI_NUM_GA, RSVD_5_31));
194	/** @} */
195
196	/**
197	* @name MSI Capability Header Register.
198	* In accordance with the AMD spec.
199	* @{
200	*/
201	/** MsiCapId: Capability ID. */
202	#define IOMMU_BF_MSI_CAPHDR_CAP_ID_SHIFT 0
203	#define IOMMU_BF_MSI_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
204	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
205	#define IOMMU_BF_MSI_CAPHDR_CAP_PTR_SHIFT 8
206	#define IOMMU_BF_MSI_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
207	/** MsiEn: Message Signal Interrupt enable. */
208	#define IOMMU_BF_MSI_CAPHDR_EN_SHIFT 16
209	#define IOMMU_BF_MSI_CAPHDR_EN_MASK UINT32_C(0x00010000)
210	/** MsiMultMessCap: MSI Multi-Message Capability. */
211	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_CAP_SHIFT 17
212	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
213	/** MsiMultMessEn: MSI Mult-Message Enable. */
214	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_EN_SHIFT 20
215	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
216	/** Msi64BitEn: MSI 64-bit Enabled. */
217	#define IOMMU_BF_MSI_CAPHDR_64BIT_EN_SHIFT 23
218	#define IOMMU_BF_MSI_CAPHDR_64BIT_EN_MASK UINT32_C(0x00800000)
219	/** Bits 31:24 reserved. */
220	#define IOMMU_BF_MSI_CAPHDR_RSVD_24_31_SHIFT 24
221	#define IOMMU_BF_MSI_CAPHDR_RSVD_24_31_MASK UINT32_C(0xff000000)
222	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAPHDR_, UINT32_C(0), UINT32_MAX,
223	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
224	/** @} */
225
226	/**
227	* @name MSI Mapping Capability Header Register.
228	* In accordance with the AMD spec.
229	* @{
230	*/
231	/** MsiMapCapId: Capability ID. */
232	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
233	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
234	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
235	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
236	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
237	/** MsiMapEn: MSI mapping capability enable. */
238	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
239	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
240	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
241	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
242	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
243	/** Bits 18:28 reserved. */
244	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
245	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
246	/** MsiMapCapType: MSI mapping capability. */
247	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
248	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
249	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
250	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
251	/** @} */
252
253	/** @name Miscellaneous IOMMU defines.
254	* @{ */
255	#define IOMMU_LOG_PFX "AMD_IOMMU" /*< Log prefix string. /
256	#define IOMMU_PCI_VENDOR_ID 0x1022 /*< AMD's vendor ID. /
257	#define IOMMU_PCI_DEVICE_ID 0xc0de /*< VirtualBox IOMMU Device ID. /
258	#define IOMMU_PCI_REVISION_ID 0x01 /*< VirtualBox IOMMU Device Revision ID. /
259	/** @} */
260
261
262	/*********************************************************************************************************************************
263	* Structures and Typedefs *
264	*********************************************************************************************************************************/
265	/**
266	* The Device ID.
267	* In accordance with the AMD spec.
268	*/
269	typedef union
270	{
271	struct
272	{
273	uint16_t uFunction : 3; /*< Bits 2:0 - Function. /
274	uint16_t uDevice : 5; /*< Bits 7:3 - Device. /
275	uint16_t uBus : 8; /*< Bits 15:8 - Bus. /
276	} n;
277	/** The unsigned integer view. */
278	uint16_t u;
279	} DEVICE_ID_T;
280	AssertCompileSize(DEVICE_ID_T, 2);
281
282	/**
283	* Device Table Entry (DTE).
284	* In accordance with the AMD spec.
285	*/
286	typedef union
287	{
288	struct
289	{
290	uint32_t u1Valid : 1; /*< Bit 0 - V: Valid. /
291	uint32_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
292	uint32_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
293	uint32_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
294	uint32_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
295	uint32_t u20PageTableRootPtrLo : 20; /*< Bits 31:12 - Page Table Root Pointer (Lo). /
296	uint32_t u20PageTableRootPtrHi : 20; /*< Bits 51:32 - Page Table Root Pointer (Hi). /
297	uint32_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
298	uint32_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
299	uint32_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
300	uint32_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
301	uint32_t u2GstCr3RootTblTranslated : 2; /*< Bits 57:56 - GLX: Guest Levels Translated. /
302	uint32_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Pointer (Lo). /
303	uint32_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
304	uint32_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
305	uint32_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
306	uint32_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
307	uint32_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Pointer (Mid). /
308	uint32_t u1IoTlbEnable : 1; /*< Bit 96 - IOTLB Enable. /
309	uint32_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
310	uint32_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
311	uint32_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
312	uint32_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
313	uint32_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
314	uint32_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
315	uint32_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
316	uint32_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
317	uint32_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Pointer (Hi). /
318	uint32_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
319	uint32_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
320	uint32_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
321	uint32_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
322	uint32_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
323	uint32_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
324	uint32_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
325	uint32_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
326	uint32_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
327	uint32_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
328	uint32_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
329	uint32_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 (Legacy PIC NMI) Pass-thru. /
330	uint32_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 (Legacy PIC NMI) Pass-thru. /
331	uint32_t u32Rsvd0; /*< Bits 223:192 - Reserved. /
332	uint32_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
333	uint32_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
334	uint32_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
335	uint32_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
336	} n;
337	/** The 32-bit unsigned integer view. */
338	uint32_t au32[8];
339	} DEV_TAB_ENTRY_T;
340	AssertCompileSize(DEV_TAB_ENTRY_T, 32);
341
342	/**
343	* I/O Page Table Entry.
344	* In accordance with the AMD spec.
345	*/
346	typedef union
347	{
348	struct
349	{
350	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
351	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
352	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
353	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
354	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
355	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
356	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
357	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
358	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
359	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
360	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
361	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
362	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
363	} n;
364	/** The 64-bit unsigned integer view. */
365	uint64_t u;
366	} IOPTE_T;
367	AssertCompileSize(IOPTE_T, 8);
368
369	/**
370	* I/O Page Directory Entry.
371	* In accordance with the AMD spec.
372	*/
373	typedef union
374	{
375	struct
376	{
377	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
378	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
379	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
380	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
381	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
382	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
383	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
384	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
385	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
386	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
387	} n;
388	/** The 64-bit unsigned integer view. */
389	uint64_t u;
390	} IOPDE_T;
391	AssertCompileSize(IOPDE_T, 8);
392
393	/**
394	* Interrupt Remapping Table Entry.
395	* In accordance with the AMD spec.
396	*/
397	typedef union
398	{
399	struct
400	{
401	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
402	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
403	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
404	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
405	uint32_t u1DstMode : 1; /*< Bit 6 - DM: Destination Mode. /
406	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
407	uint32_t u8Dst : 8; /*< Bits 15:8 - Destination. /
408	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
409	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
410	} n;
411	/** The 32-bit unsigned integer view. */
412	uint32_t u;
413	} IRTE_T;
414	AssertCompileSize(IRTE_T, 4);
415
416	/**
417	* Command: Generic Command Buffer Entry.
418	* In accordance with the AMD spec.
419	*/
420	typedef union
421	{
422	struct
423	{
424	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
425	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
426	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
427	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
428	} n;
429	/** The 64-bit unsigned integer view. */
430	uint64_t au64[2];
431	} CMD_GENERIC_T;
432	AssertCompileSize(CMD_GENERIC_T, 16);
433
434	/**
435	* Command: COMPLETION_WAIT.
436	* In accordance with the AMD spec.
437	*/
438	typedef union
439	{
440	struct
441	{
442	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
443	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
444	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
445	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
446	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
447	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
448	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
449	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
450	} n;
451	/** The 64-bit unsigned integer view. */
452	uint32_t au64[2];
453	} CMD_COMPLETION_WAIT_T;
454	AssertCompileSize(CMD_COMPLETION_WAIT_T, 16);
455
456	/**
457	* Command: INVALIDATE_DEVTAB_ENTRY.
458	* In accordance with the AMD spec.
459	*/
460	typedef union
461	{
462	struct
463	{
464	uint16_t u16DeviceId; /*< Bits 15:0 - DeviceID. /
465	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
466	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
467	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
468	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
469	} n;
470	/** The 64-bit unsigned integer view. */
471	uint64_t au64[2];
472	} CMD_INV_DEV_TAB_ENTRY_T;
473	AssertCompileSize(CMD_INV_DEV_TAB_ENTRY_T, 16);
474
475	/**
476	* Command: INVALIDATE_IOMMU_PAGES.
477	* In accordance with the AMD spec.
478	*/
479	typedef union
480	{
481	struct
482	{
483	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
484	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
485	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
486	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
487	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
488	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
489	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
490	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
491	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
492	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
493	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
494	} n;
495	/** The 64-bit unsigned integer view. */
496	uint64_t au64[2];
497	} CMD_INV_IOMMU_PAGES_T;
498	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
499
500	/**
501	* Command: INVALIDATE_IOTLB_PAGES.
502	* In accordance with the AMD spec.
503	*/
504	typedef union
505	{
506	struct
507	{
508	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
509	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
510	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
511	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
512	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
513	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
514	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
515	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
516	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
517	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
518	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
519	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
520	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
521	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
522	} n;
523	/** The 64-bit unsigned integer view. */
524	uint64_t au64[2];
525	} CMD_INV_IOTLB_PAGES_T;
526	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
527
528	/**
529	* Command: INVALIDATE_INTR_TABLE.
530	* In accordance with the AMD spec.
531	*/
532	typedef union
533	{
534	struct
535	{
536	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
537	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
538	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
539	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
540	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
541	} u;
542	/** The 64-bit unsigned integer view. */
543	uint64_t au64[2];
544	} CMD_INV_INTR_TABLE_T;
545	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
546
547	/**
548	* Command: COMPLETE_PPR_REQ.
549	* In accordance with the AMD spec.
550	*/
551	typedef union
552	{
553	struct
554	{
555	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
556	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
557	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
558	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
559	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
560	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
561	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
562	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
563	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
564	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
565	} n;
566	/** The 64-bit unsigned integer view. */
567	uint64_t au64[2];
568	} CMD_COMPLETE_PPR_REQ_T;
569	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
570
571	/**
572	* Command: INV_IOMMU_ALL.
573	* In accordance with the AMD spec.
574	*/
575	typedef union
576	{
577	struct
578	{
579	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
580	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
581	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
582	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
583	} n;
584	/** The 64-bit unsigned integer view. */
585	uint64_t au64[2];
586	} CMD_IOMMU_ALL_T;
587	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
588
589	/**
590	* Event Log Entry: Generic.
591	* In accordance with the AMD spec.
592	*/
593	typedef union
594	{
595	struct
596	{
597	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
598	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
599	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
600	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
601	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
602	} n;
603	/** The 32-bit unsigned integer view. */
604	uint32_t au32[4];
605	} EVT_GENERIC_T;
606	AssertCompileSize(EVT_GENERIC_T, 16);
607
608	/**
609	* Event Log Entry: ILLEGAL_DEV_TAB_ENTRY.
610	* In accordance with the AMD spec.
611	*/
612	typedef union
613	{
614	struct
615	{
616	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
617	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
618	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
619	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
620	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
621	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
622	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
623	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
624	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
625	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
626	uint16_t u1RsvdZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. /
627	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
628	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
629	uint16_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
630	uint32_t u2Rsvd1 : 2; /*< Bits 65:64 - Reserved. /
631	uint32_t u30AddrLo : 2; /*< Bits 95:66 - Address: Device Virtual Address (Lo). /
632	uint32_t u30AddrHi; /*< Bits 127:96 - Address: Device Virtual Address (Hi). /
633	} n;
634	/** The 32-bit unsigned integer view. */
635	uint32_t au32[4];
636	} EVT_ILLEGAL_DEV_TAB_ENTRY_T;
637	AssertCompileSize(EVT_ILLEGAL_DEV_TAB_ENTRY_T, 16);
638
639	/**
640	* Event Log Entry: IO_PAGE_FAULT_EVENT.
641	* In accordance with the AMD spec.
642	*/
643	typedef union
644	{
645	struct
646	{
647	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
648	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
649	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
650	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
651	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
652	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
653	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
654	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
655	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
656	uint16_t u1Perm : 1; /*< Bit 54 - PE: Permission Indicator. /
657	uint16_t u1RsvdZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. /
658	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
659	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
660	uint16_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
661	uint64_t u64Addr; /*< Bits 127:64 - Address: Device Virtual Address. /
662	} n;
663	/** The 32-bit unsigned integer view. */
664	uint32_t au32[4];
665	} EVT_IO_PAGE_FAULT_T;
666	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
667
668	/**
669	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
670	* In accordance with the AMD spec.
671	*/
672	typedef union
673	{
674	struct
675	{
676	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
677	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
678	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
679	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt. /
680	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
681	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
682	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
683	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
684	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
685	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
686	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
687	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
688	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: System Physical Address (Lo). /
689	uint32_t u32AddrHi; /*< Bits 127:96 - Address: System Physical Address (Hi). /
690	} n;
691	/** The 32-bit unsigned integer view. */
692	uint32_t au32[4];
693	} EVT_DEV_TAB_HARDWARE_ERROR;
694	AssertCompileSize(EVT_DEV_TAB_HARDWARE_ERROR, 16);
695
696	/**
697	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
698	* In accordance with the AMD spec.
699	*/
700	typedef union
701	{
702	struct
703	{
704	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
705	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
706	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
707	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
708	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
709	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
710	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
711	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
712	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
713	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
714	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
715	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
716	uint32_t u4EventCode : 4; /*< Bit 63:60 - Event code. /
717	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
718	* table 58 mentions Addr[31:4]. Looks like a typo in the figure. Use
719	* table as it makes more sense and matches address size in
720	* EVT_DEV_TAB_HARDWARE_ERROR. See AMD AMD IOMMU spec (3.05-PUB, Jan
721	* 2020). */
722	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
723	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of page table entry (Lo). /
724	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of page table entry (Hi). /
725	} n;
726	/** The 32-bit unsigned integer view. */
727	uint32_t au32[4];
728	} EVT_PAGE_TAB_HARDWARE_ERROR;
729	AssertCompileSize(EVT_PAGE_TAB_HARDWARE_ERROR, 16);
730
731	/**
732	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
733	* In accordance with the AMD spec.
734	*/
735	typedef union
736	{
737	struct
738	{
739	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
740	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
741	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
742	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
743	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalid command (Lo). /
744	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalid command (Hi). /
745	} n;
746	/** The 32-bit unsigned integer view. */
747	uint32_t au32[4];
748	} EVT_ILLEGAL_COMMAND_ENTRY;
749	AssertCompileSize(EVT_ILLEGAL_COMMAND_ENTRY, 16);
750
751	/**
752	* Event Log Entry: COMMAND_HARDWARE_ERROR.
753	* In accordance with the AMD spec.
754	*/
755	typedef union
756	{
757	struct
758	{
759	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
760	uint32_t u4Rsvd0 : 4; /*< Bits 35:32 - Reserved. /
761	uint32_t u28AddrLo : 28; /*< Bits 63:36 - Address: SPA of the attempted access (Lo). /
762	uint32_t u32AddrHi; /*< Bits 95:64 - Address: SPA of the attempted access (Hi). /
763	} n;
764	/** The 32-bit unsigned integer view. */
765	uint32_t au32[3];
766	} EVT_COMMAND_HARDWARE_ERROR;
767	AssertCompileSize(EVT_COMMAND_HARDWARE_ERROR, 12);
768
769	/**
770	* Event Log Entry: IOTLB_INV_TIMEOUT.
771	* In accordance with the AMD spec.
772	*/
773	typedef union
774	{
775	struct
776	{
777	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
778	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
779	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
780	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
781	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
782	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
783	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
784	} n;
785	/** The 32-bit unsigned integer view. */
786	uint32_t au32[4];
787	} EVT_IOTLB_INV_TIMEOUT;
788	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT, 16);
789
790	/**
791	* Event Log Entry: INVALID_DEVICE_REQUEST.
792	* In accordance with the AMD spec.
793	*/
794	typedef union
795	{
796	struct
797	{
798	uint32_t u16DeviceId : 16; /**< Bits 15:0 - Device ID. /
799	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
800	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
801	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
802	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
803	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
804	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
805	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
806	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
807	uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. /
808	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
809	} n;
810	/** The 32-bit unsigned integer view. */
811	uint32_t au32[4];
812	} EVT_INVALID_DEVICE_REQUEST;
813	AssertCompileSize(EVT_INVALID_DEVICE_REQUEST, 16);
814
815	/**
816	* Event Log Entry: EVENT_COUNTER_ZERO.
817	* In accordance with the AMD spec.
818	*/
819	typedef union
820	{
821	struct
822	{
823	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
824	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
825	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
826	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
827	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
828	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
829	} n;
830	/** The 32-bit unsigned integer view. */
831	uint32_t au32[4];
832	} EVT_EVENT_COUNTER_ZERO;
833	AssertCompileSize(EVT_EVENT_COUNTER_ZERO, 16);
834
835	/**
836	* Device Table Base Address Register (MMIO).
837	* In accordance with the AMD spec.
838	*/
839	typedef union
840	{
841	struct
842	{
843	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
844	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
845	RT_GCC_EXTENSION uint64_t u40DevTabBase : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
846	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
847	} n;
848	/** The 64-bit unsigned integer view. */
849	uint64_t u64;
850	} DEV_TAB_BAR_T;
851	AssertCompileSize(DEV_TAB_BAR_T, 8);
852
853	/**
854	* Command Buffer Base Address Register (MMIO).
855	* In accordance with the AMD spec.
856	*/
857	typedef union
858	{
859	struct
860	{
861	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
862	RT_GCC_EXTENSION uint64_t u40CmdBase : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
863	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
864	RT_GCC_EXTENSION uint64_t u4CmdLen : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
865	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
866	} n;
867	/** The 64-bit unsigned integer view. */
868	uint64_t u64;
869	} CMD_BUF_BAR_T;
870	AssertCompileSize(CMD_BUF_BAR_T, 8);
871
872	/**
873	* Event Log Base Address Register (MMIO).
874	* In accordance with the AMD spec.
875	*/
876	typedef union
877	{
878	struct
879	{
880	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
881	RT_GCC_EXTENSION uint64_t u40EvtBase : 40; /*< Bits 51:12 - EventBase: Event log base address. /
882	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
883	RT_GCC_EXTENSION uint64_t u4EvtLen : 4; /*< Bits 59:56 - EventLen: Event log length. /
884	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
885	} n;
886	/** The 64-bit unsigned integer view. */
887	uint64_t u64;
888	} EVT_LOG_BUF_BAR_T;
889	AssertCompileSize(EVT_LOG_BUF_BAR_T, 8);
890
891	/**
892	* IOMMU Control Register (MMIO).
893	* In accordance with the AMD spec.
894	*/
895	typedef union
896	{
897	struct
898	{
899	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
900	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
901	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
902	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
903	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
904	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
905	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
906	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
907	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
908	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
909	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
910	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
911	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
912	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
913	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
914	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
915	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
916	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
917	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
918	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
919	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
920	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
921	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
922	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
923	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
924	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
925	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
926	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
927	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
928	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
929	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
930	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
931	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
932	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
933	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
934	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
935	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
936	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
937	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
938	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
939	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
940	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
941	} n;
942	/** The 64-bit unsigned integer view. */
943	uint64_t u64;
944	} IOMMU_CTRL_T;
945	AssertCompileSize(IOMMU_CTRL_T, 8);
946
947	/**
948	* IOMMU Exclusion Base Register (MMIO).
949	* In accordance with the AMD spec.
950	*/
951	typedef union
952	{
953	struct
954	{
955	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
956	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
957	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
958	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
959	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
960	} n;
961	/** The 64-bit unsigned integer view. */
962	uint64_t u64;
963	} IOMMU_EXCL_BASE_T;
964	AssertCompileSize(IOMMU_EXCL_BASE_T, 8);
965
966	/**
967	* IOMMU Exclusion Range Limit Register (MMIO).
968	* In accordance with the AMD spec.
969	*/
970	typedef union
971	{
972	struct
973	{
974	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
975	RT_GCC_EXTENSION uint64_t u40ExclLimit : 40; /*< Bits 51:12 - Exclusion Range Limit. /
976	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
977	} n;
978	/** The 64-bit unsigned integer view. */
979	uint64_t u64;
980	} IOMMU_EXCL_RANGE_LIMIT_T;
981	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
982
983	/**
984	* IOMMU Extended Feature Register (MMIO).
985	* In accordance with the AMD spec.
986	*/
987	typedef union
988	{
989	struct
990	{
991	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
992	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
993	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
994	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
995	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations Support. /
996	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
997	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
998	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
999	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1000	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1001	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1002	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1003	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1004	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1005	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1006	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1007	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1008	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1009	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1010	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1011
1012	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1013	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1014	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1015	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1016	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1017	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1018	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1019	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1020	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1021	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1022	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1023	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1024	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1025	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1026	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1027	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1028	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1029	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1030	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1031	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1032	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1033	} n;
1034	/** The 64-bit unsigned integer view. */
1035	uint64_t u64;
1036	} IOMMU_EFR_T;
1037	AssertCompileSize(IOMMU_EFR_T, 8);
1038
1039	/**
1040	* Peripheral Page Request Log Base Address Register (MMIO).
1041	* In accordance with the AMD spec.
1042	*/
1043	typedef union
1044	{
1045	struct
1046	{
1047	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1048	RT_GCC_EXTENSION uint64_t u40PprLogBase : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1049	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1050	RT_GCC_EXTENSION uint64_t u4PprLogLen : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1051	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1052	} n;
1053	/** The 64-bit unsigned integer view. */
1054	uint64_t u64;
1055	} PPR_LOG_BAR_T;
1056	AssertCompileSize(PPR_LOG_BAR_T, 8);
1057
1058	/**
1059	* IOMMU Hardware Event Upper Register (MMIO).
1060	* In accordance with the AMD spec.
1061	*/
1062	typedef union
1063	{
1064	struct
1065	{
1066	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1067	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1068	} n;
1069	/** The 64-bit unsigned integer view. */
1070	uint64_t u64;
1071	} IOMMU_HW_EVT_HI_T;
1072	AssertCompileSize(PPR_LOG_BAR_T, 8);
1073
1074	/**
1075	* IOMMU Hardware Event Lower Register (MMIO).
1076	* In accordance with the AMD spec.
1077	*/
1078	typedef uint64_t IOMMU_HW_EVT_LO_T;
1079
1080	/**
1081	* IOMMU Hardware Event Status (MMIO).
1082	* In accordance with the AMD spec.
1083	*/
1084	typedef union
1085	{
1086	struct
1087	{
1088	uint32_t u1HwEventValid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1089	uint32_t u1HwEventOverflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1090	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1091	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1092	} n;
1093	/** The 64-bit unsigned integer view. */
1094	uint64_t u64;
1095	} IOMMU_HW_EVT_STATUS_T;
1096	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1097
1098	/**
1099	* Device Table Segment Register (MMIO).
1100	* In accordance with the AMD spec.
1101	*/
1102	typedef union
1103	{
1104	struct
1105	{
1106	RT_GCC_EXTENSION uint64_t u8Size : 8; /*< Bits 7:0 - Size: Size of the Device Table segment. /
1107	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 11:8 - Reserved. /
1108	RT_GCC_EXTENSION uint64_t u40DevTabBase : 40; /*< Bits 51:12 - DevTabBase: Device Table Segment Base Address. /
1109	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1110	} n;
1111	/** The 64-bit unsigned integer view. */
1112	uint64_t u64;
1113	} DEV_TAB_SEG_BAR_T;
1114	AssertCompileSize(DEV_TAB_SEG_BAR_T, 8);
1115
1116	/**
1117	* Device-specific Feature Extension (DSFX) Register (MMIO).
1118	* In accordance with the AMD spec.
1119	*/
1120	typedef union
1121	{
1122	struct
1123	{
1124	uint32_t u24DevSpecFeatSup : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1125	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1126	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1127	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1128	} n;
1129	/** The 64-bit unsigned integer view. */
1130	uint64_t u64;
1131	} DEV_SPECIFIC_FEAT_T;
1132	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1133
1134	/**
1135	* Device-specific Control Extension (DSCX) Register (MMIO).
1136	* In accordance with the AMD spec.
1137	*/
1138	typedef union
1139	{
1140	struct
1141	{
1142	uint32_t u24DevSpecFeatSup : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1143	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1144	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1145	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1146	} n;
1147	/** The 64-bit unsigned integer view. */
1148	uint64_t u64;
1149	} DEV_SPECIFIC_CTRL_T;
1150	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1151
1152	/**
1153	* Device-specific Status Extension (DSSX) Register (MMIO).
1154	* In accordance with the AMD spec.
1155	*/
1156	typedef union
1157	{
1158	struct
1159	{
1160	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1161	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1162	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1163	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1164	} n;
1165	/** The 64-bit unsigned integer view. */
1166	uint64_t u64;
1167	} DEV_SPECIFIC_STATUS_T;
1168	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1169
1170	/**
1171	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1172	* In accordance with the AMD spec.
1173	*/
1174	typedef union
1175	{
1176	struct
1177	{
1178	uint32_t u5MsiNum : 5; /*< Bits 4:0 - MsiNum: MSI Vector used for interrupt messages generated by the IOMMU. /
1179	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1180	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1181	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1182	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1183	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1184	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1185	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1186	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1187	} n;
1188	/** The 32-bit unsigned integer view. */
1189	uint32_t au32[2];
1190	/** The 64-bit unsigned integer view. */
1191	uint64_t u64;
1192	} MSI_MISC_INFO_T;
1193	AssertCompileSize(MSI_MISC_INFO_T, 8);
1194	/** MSI Vector Register 0 and 1 (MMIO). */
1195	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1196
1197	/**
1198	* MSI Capability Header Register (PCI + MMIO).
1199	* In accordance with the AMD spec.
1200	*/
1201	typedef union
1202	{
1203	struct
1204	{
1205	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1206	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1207	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1208	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1209	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1210	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1211	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1212	} n;
1213	/** The 32-bit unsigned integer view. */
1214	uint32_t u32;
1215	} MSI_CAP_HDR_T;
1216	AssertCompileSize(MSI_CAP_HDR_T, 4);
1217
1218	/**
1219	* MSI Address Register (PCI + MMIO).
1220	* In accordance with the AMD spec.
1221	*/
1222	typedef union
1223	{
1224	struct
1225	{
1226	uint32_t u2Rsvd : 2; /*< Bits 1:0 - Reserved. /
1227	uint32_t u30MsiAddrLo : 30; /*< Bits 31:2 - MsiAddr: MSI Address (Lo). /
1228	uint32_t u32MsiAddrHi; /*< Bits 63:32 - MsiAddr: MSI Address (Hi). /
1229	} n;
1230	/** The 32-bit unsigned integer view. */
1231	uint32_t au32[2];
1232	/** The 64-bit unsigned integer view. */
1233	uint64_t u64;
1234	} MSI_ADDR_T;
1235	AssertCompileSize(MSI_ADDR_T, 8);
1236
1237	/**
1238	* MSI Data Register (PCI + MMIO).
1239	* In accordance with the AMD spec.
1240	*/
1241	typedef union
1242	{
1243	struct
1244	{
1245	uint16_t u16MsiData; /*< Bits 15:0 - MsiData: MSI Data. /
1246	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1247	} n;
1248	/** The 32-bit unsigned integer view. */
1249	uint32_t u32;
1250	} MSI_DATA_T;
1251	AssertCompileSize(MSI_DATA_T, 4);
1252
1253	/**
1254	* MSI Mapping Capability Header Register (PCI + MMIO).
1255	* In accordance with the AMD spec.
1256	*/
1257	typedef union
1258	{
1259	struct
1260	{
1261	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1262	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1263	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1264	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1265	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1266	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1267	} n;
1268	/** The 32-bit unsigned integer view. */
1269	uint32_t u32;
1270	} MSI_MAP_CAP_HDR_T;
1271	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1272
1273	/**
1274	* Performance Optimization Control Register (MMIO).
1275	* In accordance with the AMD spec.
1276	*/
1277	typedef union
1278	{
1279	struct
1280	{
1281	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1282	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1283	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1284	} n;
1285	/** The 32-bit unsigned integer view. */
1286	uint32_t u32;
1287	} IOMMU_PERF_OPT_CTRL_T;
1288	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1289
1290	/**
1291	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1292	* In accordance with the AMD spec.
1293	*/
1294	typedef union
1295	{
1296	struct
1297	{
1298	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1299	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1300	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1301	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1302	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1303	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1304	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1305	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1306	} n;
1307	/** The 64-bit unsigned integer view. */
1308	uint64_t u64;
1309	} IOMMU_XT_GEN_INTR_CTRL_T;
1310	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1311
1312	/**
1313	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1314	* In accordance with the AMD spec.
1315	*/
1316	typedef union
1317	{
1318	struct
1319	{
1320	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1321	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1322	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1323	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1324	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1325	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1326	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1327	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1328	} n;
1329	/** The 64-bit unsigned integer view. */
1330	uint64_t u64;
1331	} IOMMU_XT_INTR_CTRL_T;
1332	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1333
1334	/**
1335	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1336	* In accordance with the AMD spec.
1337	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1338	*/
1339	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1340
1341	/**
1342	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1343	* In accordance with the AMD spec.
1344	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1345	*/
1346	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1347
1348	/**
1349	* IOMMU Reserved Register (MMIO).
1350	* In accordance with the AMD spec.
1351	* This register is reserved for hardware use (although RW?).
1352	*/
1353	typedef uint64_t IOMMU_RSVD_REG_T;
1354
1355	/**
1356	* Command Buffer Head Pointer Register (MMIO).
1357	* In accordance with the AMD spec.
1358	*/
1359	typedef union
1360	{
1361	struct
1362	{
1363	uint32_t u4Rsvd0 : 4; /*< Bits 3:0 - Reserved. /
1364	uint32_t u15Ptr : 15; /*< Bits 18:14 - Buffer pointer. /
1365	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1366	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1367	} n;
1368	/** The 32-bit unsigned integer view. */
1369	uint32_t au32[2];
1370	/** The 64-bit unsigned integer view. */
1371	uint64_t u64;
1372	} CMD_BUF_HEAD_PTR_T;
1373	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1374
1375	/**
1376	* Command Buffer Tail Pointer Register (MMIO).
1377	* In accordance with the AMD spec.
1378	* Currently identical to CMD_BUF_HEAD_PTR_T.
1379	*/
1380	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1381
1382	/**
1383	* Event Log Head Pointer Register (MMIO).
1384	* In accordance with the AMD spec.
1385	* Currently identical to CMD_BUF_HEAD_PTR_T.
1386	*/
1387	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1388
1389	/**
1390	* Event Log Tail Pointer Register (MMIO).
1391	* In accordance with the AMD spec.
1392	* Currently identical to CMD_BUF_HEAD_PTR_T.
1393	*/
1394	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1395
1396	/**
1397	* IOMMU Status Register (MMIO).
1398	* In accordance with the AMD spec.
1399	*/
1400	typedef union
1401	{
1402	struct
1403	{
1404	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
1405	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
1406	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
1407	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
1408	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
1409	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
1410	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
1411	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
1412	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
1413	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
1414	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
1415	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
1416	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
1417	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
1418	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
1419	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
1420	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
1421	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
1422	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1423	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
1424	} n;
1425	/** The 32-bit unsigned integer view. */
1426	uint32_t au32[2];
1427	/** The 64-bit unsigned integer view. */
1428	uint64_t u64;
1429	} IOMMU_STATUS_T;
1430	AssertCompileSize(IOMMU_STATUS_T, 8);
1431
1432	/**
1433	* PPR Log Head Pointer Register (MMIO).
1434	* In accordance with the AMD spec.
1435	* Currently identical to CMD_BUF_HEAD_PTR_T.
1436	*/
1437	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
1438
1439	/**
1440	* PPR Log Tail Pointer Register (MMIO).
1441	* In accordance with the AMD spec.
1442	* Currently identical to CMD_BUF_HEAD_PTR_T.
1443	*/
1444	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
1445
1446
1447	/**
1448	* The shared IOMMU device state.
1449	*/
1450	typedef struct IOMMU
1451	{
1452	/** Whether this IOMMU is at the top of the PCI tree hierarchy or not. */
1453	bool fRootComplex;
1454	/** Alignment padding. */
1455	bool afPadding[3];
1456
1457	/** @name MMIO: Control and status registers.
1458	* @{ */
1459	DEV_TAB_BAR_T DevTabBaseAddr; /*< Device table base address register. /
1460	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
1461	EVT_LOG_BUF_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
1462	IOMMU_CTRL_T IommuCtrl; /*< IOMMU control register. /
1463	IOMMU_EXCL_BASE_T ExclBase; /*< IOMMU exclusion base register. /
1464	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
1465	IOMMU_EFR_T ExtFeat; /*< IOMMU extended feature register. /
1466	/** @} */
1467
1468	/** @name MMIO: PPR Log registers.
1469	* @{ */
1470	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
1471	IOMMU_HW_EVT_HI_T IommuHwEvtHi; /*< IOMMU hardware event register (Hi). /
1472	IOMMU_HW_EVT_LO_T IommuHwEvtLo; /*< IOMMU hardware event register (Lo). /
1473	IOMMU_HW_EVT_STATUS_T IommuHwEvtStatus; /*< IOMMU hardware event status. /
1474	/** @} */
1475
1476	/** @name MMIO: Device table segment registers.
1477	* @{ */
1478	DEV_TAB_SEG_BAR_T DevTabSeg[7]; /*< Device Table Segment base address register. /
1479	/** @} */
1480
1481	/** @name MMIO: Device-specific feature registers.
1482	* @{ */
1483	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
1484	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
1485	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
1486	/** @} */
1487
1488	/** @name MMIO: MSI Capability Block registers.
1489	* @{ */
1490	MSI_MISC_INFO_T MsiMiscInfo0; /*< MSI Misc. info registers / MSI Vector registers. /
1491	MSI_CAP_HDR_T MsiCapHdr; /*< MSI Capability header register. /
1492	MSI_ADDR_T MsiAddr; /*< MSI Address register./
1493	MSI_DATA_T MsiData; /*< MSI Data register. /
1494	MSI_MAP_CAP_HDR_T MsiMapCapHdr; /*< MSI Capping capability header register. /
1495	/** @} */
1496
1497	/** @name MMIO: Performance Optimization Control registers.
1498	* @{ */
1499	IOMMU_PERF_OPT_CTRL_T IommuPerfOptCtrl; /*< IOMMU Performance optimization control register. /
1500	/** @} */
1501
1502	/** @name MMIO: x2APIC Control registers.
1503	* @{ */
1504	IOMMU_XT_GEN_INTR_CTRL_T IommuXtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
1505	IOMMU_XT_PPR_INTR_CTRL_T IommuXtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
1506	IOMMU_XT_GALOG_INTR_CTRL_T IommuXtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
1507	/** @} */
1508
1509	/** @name MMIO: Reserved register.
1510	* @{ */
1511	IOMMU_RSVD_REG_T IommuRsvdReg; /*< IOMMU Reserved Register. /
1512	/** @} */
1513
1514	/** @name MMIO: Command and Event Log registers.
1515	* @{ */
1516	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
1517	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
1518	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
1519	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
1520	/** @} */
1521
1522	/** @name MMIO: Command Event status register.
1523	* @{ */
1524	IOMMU_STATUS_T IommuStatus; /*< IOMMU status register. /
1525	/** @} */
1526
1527	/** @name MMIO: PPR Log Head and Tail Pointer registers.
1528	* @{ */
1529	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
1530	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
1531	/** @} */
1532	} IOMMU;
1533	/** Pointer to the IOMMU device state. */
1534	typedef struct IOMMU *PIOMMU;
1535
1536	/**
1537	* The ring-3 IOMMU device state.
1538	*/
1539	typedef struct IOMMUR3
1540	{
1541	/** The IOMMU helpers. */
1542	PCPDMIOMMUHLPR3 pIommuHlp;
1543	} IOMMUR3;
1544	/** Pointer to the ring-3 IOMMU device state. */
1545	typedef IOMMUR3 *PIOMMUR3;
1546
1547	/**
1548	* The ring-0 IOMMU device state.
1549	*/
1550	typedef struct IOMMUR0
1551	{
1552	/** The IOMMU helpers. */
1553	PCPDMIOMMUHLPR0 pIommuHlp;
1554	} IOMMUR0;
1555	/** Pointer to the ring-0 IOMMU device state. */
1556	typedef IOMMUR0 *PIOMMUR0;
1557
1558	/**
1559	* The raw-mode IOMMU device state.
1560	*/
1561	typedef struct IOMMURC
1562	{
1563	/** The IOMMU helpers. */
1564	PCPDMIOMMUHLPRC pIommuHlp;
1565	} IOMMURC;
1566	/** Pointer to the raw-mode IOMMU device state. */
1567	typedef IOMMURC *PIOMMURC;
1568
1569	/** The IOMMU device state for the current context. */
1570	typedef CTX_SUFF(IOMMU) IOMMUCC;
1571	/** Pointer to the IOMMU device state for the current context. */
1572	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
1573
1574
1575	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
1576
1577	# ifdef IN_RING3
1578	/**
1579	* @interface_method_impl{PDMDEVREG,pfnReset}
1580	*/
1581	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
1582	{
1583	NOREF(pDevIns);
1584	}
1585
1586
1587	/**
1588	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1589	*/
1590	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
1591	{
1592	NOREF(pDevIns);
1593	return VINF_SUCCESS;
1594	}
1595
1596
1597	/**
1598	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1599	*/
1600	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1601	{
1602	NOREF(iInstance);
1603	NOREF(pCfg);
1604
1605	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1606	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1607	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
1608	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
1609	int rc;
1610	LogFlowFunc(("\n"));
1611
1612	NOREF(pThisCC); /** @todo IOMMU: populate CC data. */
1613
1614	/*
1615	* Validate and read the configuration.
1616	*/
1617	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "RootComplex", "");
1618
1619	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RootComplex", &pThis->fRootComplex, true);
1620	AssertLogRelRCReturn(rc, rc);
1621
1622	/*
1623	* Initialize the PCI configuration space.
1624	*/
1625	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1626	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1627
1628	uint8_t const offCapHdr = 0x40;
1629	uint8_t const offBaseAddrLo = offCapHdr + 0x4;
1630	uint8_t const offBaseAddrHi = offCapHdr + 0x8;
1631	uint8_t const offRange = offCapHdr + 0xc;
1632	uint8_t const offMiscInfo0 = offCapHdr + 0x10;
1633	uint8_t const offMiscInfo1 = offCapHdr + 0x14;
1634	uint8_t const offMsiCapHdr = offCapHdr + 0x24;
1635	uint8_t const offMsiAddrLo = offCapHdr + 0x28;
1636	uint8_t const offMsiAddrHi = offCapHdr + 0x2c;
1637	uint8_t const offMsiData = offCapHdr + 0x30;
1638	uint8_t const offMsiMapCapHdr = offCapHdr + 0x34;
1639
1640	/* Header. */
1641	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* RO - AMD */
1642	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* RO - VirtualBox IOMMU device */
1643	PDMPciDevSetCommand(pPciDev, 0); /* RW - Command */
1644	PDMPciDevSetStatus(pPciDev, 0x5); /* RW - Status - CapList supported */
1645	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* RO - VirtualBox specific device implementation revision */
1646	PDMPciDevSetClassBase(pPciDev, 0x08); /* RO - System Base Peripheral */
1647	PDMPciDevSetClassSub(pPciDev, 0x06); /* RO - IOMMU */
1648	PDMPciDevSetClassProg(pPciDev, 0x00); /* RO - IOMMU Programming interface */
1649	PDMPciDevSetHeaderType(pPciDev, 0x00); /* RO - Single function, type 0. */
1650	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* RO - AMD */
1651	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* RO - VirtualBox IOMMU device */
1652	PDMPciDevSetCapabilityList(pPciDev, offCapHdr); /* RO - Offset into capability registers. */
1653	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* RO - INTA#. */
1654	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* RW - For software compatibility; no effect on hardware. */
1655
1656	/* Capability Header. */
1657	PDMPciDevSetDWord(pPciDev, offCapHdr,
1658	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
1659	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, offMsiCapHdr) /* RO - Offset to next capability block */
1660	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
1661	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
1662	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
1663	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
1664	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache Not-present page table entries */
1665	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
1666	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
1667
1668	/* Base Address Low Register. */
1669	PDMPciDevSetDWord(pPciDev, offBaseAddrLo,
1670	RT_BF_MAKE(IOMMU_BF_BASEADDR_LO_ENABLE, 0x0) /* RW - Enable */
1671	\| RT_BF_MAKE(IOMMU_BF_BASEADDR_LO_ADDR_LO, 0x0) /* RW - Base address low (lo) */
1672	\| RT_BF_MAKE(IOMMU_BF_BASEADDR_LO_ADDR_HI, 0x0)); /* RW - Base address low (hi) */
1673
1674	/* Base Address High Register. */
1675	PDMPciDevSetDWord(pPciDev, offBaseAddrHi, 0); /* RW - Base address high */
1676
1677	/* IOMMU Range Register. */
1678	PDMPciDevSetDWord(pPciDev, offRange,
1679	RT_BF_MAKE(IOMMU_BF_RANGE_UNIT_ID, 0x0) /* RO - HyperTransport Unit ID */
1680	\| RT_BF_MAKE(IOMMU_BF_RANGE_VALID, 0x0) /* RW - Range Valid */
1681	\| RT_BF_MAKE(IOMMU_BF_RANGE_BUS_NUMBER, 0x0) /* RO - Bus number */
1682	\| RT_BF_MAKE(IOMMU_BF_RANGE_FIRST_DEVICE, 0x0) /* RO - First device */
1683	\| RT_BF_MAKE(IOMMU_BF_RANGE_LAST_DEVICE, 0x0)); /* RO - Last device */
1684
1685	/* Misc. Information Register 0. */
1686	PDMPciDevSetDWord(pPciDev, offMiscInfo0,
1687	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
1688	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
1689	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
1690	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
1691	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
1692	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
1693
1694	/* Misc. Information Register 1. */
1695	PDMPciDevSetDWord(pPciDev, offMiscInfo1, 0);
1696
1697	/* MSI Capability Header register. */
1698	PDMPciDevSetDWord(pPciDev, offMsiCapHdr,
1699	RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_CAP_ID, 0x5) /* RO - Capability ID. */
1700	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_CAP_PTR, offMsiMapCapHdr) /* RO - Offset to mapping capability block */
1701	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_EN, 0x0) /* RW - MSI capability enable */
1702	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_MULTMESS_CAP, 0x0) /* RO - MSI multi-message capability */
1703	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_MULTMESS_EN, 0x0) /* RW - MSI multi-message enable */
1704	\| RT_BF_MAKE(IOMMU_BF_MSI_CAPHDR_64BIT_EN, 0x1)); /* RO - MSI 64-bit enable */
1705
1706	/* MSI Address Lo. */
1707	PDMPciDevSetDWord(pPciDev, offMsiAddrLo, 0); /* RW - MSI message address (Lo). */
1708
1709	/* MSI Address Hi. */
1710	PDMPciDevSetDWord(pPciDev, offMsiAddrHi, 0); /* RW - MSI message address (Hi). */
1711
1712	/* MSI Data. */
1713	PDMPciDevSetDWord(pPciDev, offMsiData, 0); /* RW - MSI data. */
1714
1715	/* MSI Mapping Capability Header register. */
1716	PDMPciDevSetDWord(pPciDev, offMsiMapCapHdr,
1717	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
1718	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
1719	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
1720	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
1721	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
1722
1723	return VINF_SUCCESS;
1724	}
1725
1726	# else /* !IN_RING3 */
1727
1728	/**
1729	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1730	*/
1731	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
1732	{
1733	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1734	return VINF_SUCCESS;
1735	}
1736
1737	# endif /* !IN_RING3 */
1738
1739	/**
1740	* The device registration structure.
1741	*/
1742	const PDMDEVREG g_DeviceIommuAmd =
1743	{
1744	/* .u32Version = */ PDM_DEVREG_VERSION,
1745	/* .uReserved0 = */ 0,
1746	/* .szName = */ "iommu-amd",
1747	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1748	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
1749	/* .cMaxInstances = */ ~0U,
1750	/* .uSharedVersion = */ 42,
1751	/* .cbInstanceShared = */ sizeof(IOMMU),
1752	/* .cbInstanceCC = */ sizeof(IOMMUCC),
1753	/* .cbInstanceRC = */ sizeof(IOMMURC),
1754	/* .cMaxPciDevices = */ 1,
1755	/* .cMaxMsixVectors = */ 0,
1756	/* .pszDescription = */ "IOMMU (AMD)",
1757	#if defined(IN_RING3)
1758	/* .pszRCMod = */ "VBoxDDRC.rc",
1759	/* .pszR0Mod = */ "VBoxDDR0.r0",
1760	/* .pfnConstruct = */ iommuAmdR3Construct,
1761	/* .pfnDestruct = */ iommuAmdR3Destruct,
1762	/* .pfnRelocate = */ NULL,
1763	/* .pfnMemSetup = */ NULL,
1764	/* .pfnPowerOn = */ NULL,
1765	/* .pfnReset = */ iommuAmdR3Reset,
1766	/* .pfnSuspend = */ NULL,
1767	/* .pfnResume = */ NULL,
1768	/* .pfnAttach = */ NULL,
1769	/* .pfnDetach = */ NULL,
1770	/* .pfnQueryInterface = */ NULL,
1771	/* .pfnInitComplete = */ NULL,
1772	/* .pfnPowerOff = */ NULL,
1773	/* .pfnSoftReset = */ NULL,
1774	/* .pfnReserved0 = */ NULL,
1775	/* .pfnReserved1 = */ NULL,
1776	/* .pfnReserved2 = */ NULL,
1777	/* .pfnReserved3 = */ NULL,
1778	/* .pfnReserved4 = */ NULL,
1779	/* .pfnReserved5 = */ NULL,
1780	/* .pfnReserved6 = */ NULL,
1781	/* .pfnReserved7 = */ NULL,
1782	#elif defined(IN_RING0)
1783	/* .pfnEarlyConstruct = */ NULL,
1784	/* .pfnConstruct = */ iommuAmdRZConstruct,
1785	/* .pfnDestruct = */ NULL,
1786	/* .pfnFinalDestruct = */ NULL,
1787	/* .pfnRequest = */ NULL,
1788	/* .pfnReserved0 = */ NULL,
1789	/* .pfnReserved1 = */ NULL,
1790	/* .pfnReserved2 = */ NULL,
1791	/* .pfnReserved3 = */ NULL,
1792	/* .pfnReserved4 = */ NULL,
1793	/* .pfnReserved5 = */ NULL,
1794	/* .pfnReserved6 = */ NULL,
1795	/* .pfnReserved7 = */ NULL,
1796	#elif defined(IN_RC)
1797	/* .pfnConstruct = */ iommuAmdRZConstruct,
1798	/* .pfnReserved0 = */ NULL,
1799	/* .pfnReserved1 = */ NULL,
1800	/* .pfnReserved2 = */ NULL,
1801	/* .pfnReserved3 = */ NULL,
1802	/* .pfnReserved4 = */ NULL,
1803	/* .pfnReserved5 = */ NULL,
1804	/* .pfnReserved6 = */ NULL,
1805	/* .pfnReserved7 = */ NULL,
1806	#else
1807	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1808	#endif
1809	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1810	};
1811
1812	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1813

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 83448

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