DevIommuAmd.cpp@ 83851

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AMD IOMMU: bugref:9654 Bits.
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1	/* $Id: DevIommuAmd.cpp 83851 2020-04-20 11:35:38Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/vmm/pdmdev.h>
24	#include <VBox/AssertGuest.h>
25
26	#include "VBoxDD.h"
27	#include <iprt/x86.h>
28	#include <iprt/string.h>
29
30
31	/*********************************************************************************************************************************
32	* Defined Constants And Macros *
33	*********************************************************************************************************************************/
34	/**
35	* @name PCI configuration register offsets.
36	* In accordance with the AMD spec.
37	* @{
38	*/
39	#define IOMMU_PCI_OFF_CAP_HDR 0x40
40	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
42	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
43	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
44	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
45	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
46	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
47	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
48	#define IOMMU_PCI_OFF_MSI_DATA 0x70
49	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
50	/** @} */
51
52	/**
53	* @name MMIO register offsets.
54	* In accordance with the AMD spec.
55	* @{
56	*/
57	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
58	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
59	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
60	#define IOMMU_MMIO_OFF_CTRL 0x18
61	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
62	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
63	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
64
65	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
66	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
67	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
68	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
69
70	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
71	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
72
73	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
74	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
75
76	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
77	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
78
79	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
81
82	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
83	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
84	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
85
86	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
87	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
88	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
89	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
90	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
91	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
92	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
93
94	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
95
96	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
97	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
98	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
99
100	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
101	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
102	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
103	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
104	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
105	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
106	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
107	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
108	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
109	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
110	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
111	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
112
113	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
114
115	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
116	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
117	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
118	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
119
120	#define IOMMU_MMIO_OFF_STATUS 0x2020
121
122	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
123	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
124
125	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
126	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
127
128	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
129	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
130
131	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
132	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
133
134	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
135	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
137	/** @} */
138
139	/**
140	* @name MMIO register-access table offsets.
141	* Each table [first..last] (both inclusive) represents the range of registers
142	* covered by a distinct register-access table. This is done due to arbitrary large
143	* gaps in the MMIO register offsets themselves.
144	* @{
145	*/
146	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
147	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
148
149	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
150	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
151	/** @} */
152
153	/**
154	* @name Commands.
155	* In accordance with the AMD spec.
156	* @{
157	*/
158	#define IOMMU_CMD_COMPLETION_WAIT 0x01
159	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
160	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
161	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
162	#define IOMMU_CMD_INV_INTR_TABLE 0x05
163	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
164	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
165	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
166	/** @} */
167
168	/**
169	* @name Event codes.
170	* In accordance with the AMD spec.
171	* @{
172	*/
173	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
174	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
175	#define IOMMU_EVT_DEV_TAB_HARDWARE_ERROR 0x03
176	#define IOMMU_EVT_PAGE_TAB_HARDWARE_ERROR 0x04
177	#define IOMMU_EVT_ILLEGAL_COMMAND_ERROR 0x05
178	#define IOMMU_EVT_COMMAND_HARDWARE_ERROR 0x06
179	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
180	#define IOMMU_EVT_INVALID_DEVICE_REQUEST 0x08
181	#define IOMMU_EVT_INVALID_PPR_REQUEST 0x09
182	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
183	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
184	/** @} */
185
186	/**
187	* @name IOMMU Capability Header.
188	* In accordance with the AMD spec.
189	* @{
190	*/
191	/** CapId: Capability ID. */
192	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
193	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
194	/** CapPtr: Capability Pointer. */
195	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
196	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
197	/** CapType: Capability Type. */
198	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
199	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
200	/** CapRev: Capability Revision. */
201	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
202	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
203	/** IoTlbSup: IO TLB Support. */
204	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
205	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
206	/** HtTunnel: HyperTransport Tunnel translation support. */
207	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
208	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
209	/** NpCache: Not Present table entries Cached. */
210	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
211	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
212	/** EFRSup: Extended Feature Register (EFR) Supported. */
213	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
214	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
215	/** CapExt: Miscellaneous Information Register Supported . */
216	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
217	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
218	/** Bits 31:29 reserved. */
219	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
220	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
221	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
222	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
223	/** @} */
224
225	/**
226	* @name IOMMU Base Address Low Register.
227	* In accordance with the AMD spec.
228	* @{
229	*/
230	/** Enable: Enables access to the address specified in the Base Address Register. */
231	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
232	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
233	/** Bits 13:1 reserved. */
234	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
235	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
236	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
237	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
238	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
239	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
240	(ENABLE, RSVD_1_13, ADDR));
241	/** @} */
242
243	/**
244	* @name IOMMU Range Register.
245	* In accordance with the AMD spec.
246	* @{
247	*/
248	/** UnitID: HyperTransport Unit ID. */
249	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
250	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
251	/** Bits 6:5 reserved. */
252	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
253	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
254	/** RngValid: Range valid. */
255	#define IOMMU_BF_RANGE_VALID_SHIFT 7
256	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
257	/** BusNumber: Device range bus number. */
258	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
259	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
260	/** First Device. */
261	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
262	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
263	/** Last Device. */
264	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
265	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
266	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
267	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
268	/** @} */
269
270	/**
271	* @name IOMMU Miscellaneous Information Register 0.
272	* In accordance with the AMD spec.
273	* @{
274	*/
275	/** MsiNum: MSI message number. */
276	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
277	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
278	/** GvaSize: Guest Virtual Address Size. */
279	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
280	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
281	/** PaSize: Physical Address Size. */
282	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
283	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
284	/** VaSize: Virtual Address Size. */
285	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
286	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
287	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
288	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
289	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
290	/** Bits 26:23 reserved. */
291	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
292	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
293	/** MsiNumPPR: Peripheral Page Request MSI message number. */
294	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
295	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
296	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
297	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
298	/** @} */
299
300	/**
301	* @name IOMMU Miscellaneous Information Register 1.
302	* In accordance with the AMD spec.
303	* @{
304	*/
305	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
306	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
307	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
308	/** Bits 31:5 reserved. */
309	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
310	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
311	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
312	(MSI_NUM_GA, RSVD_5_31));
313	/** @} */
314
315	/**
316	* @name MSI Capability Header Register.
317	* In accordance with the AMD spec.
318	* @{
319	*/
320	/** MsiCapId: Capability ID. */
321	#define IOMMU_BF_MSI_CAPHDR_CAP_ID_SHIFT 0
322	#define IOMMU_BF_MSI_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
323	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
324	#define IOMMU_BF_MSI_CAPHDR_CAP_PTR_SHIFT 8
325	#define IOMMU_BF_MSI_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
326	/** MsiEn: Message Signal Interrupt enable. */
327	#define IOMMU_BF_MSI_CAPHDR_EN_SHIFT 16
328	#define IOMMU_BF_MSI_CAPHDR_EN_MASK UINT32_C(0x00010000)
329	/** MsiMultMessCap: MSI Multi-Message Capability. */
330	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_CAP_SHIFT 17
331	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
332	/** MsiMultMessEn: MSI Mult-Message Enable. */
333	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_EN_SHIFT 20
334	#define IOMMU_BF_MSI_CAPHDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
335	/** Msi64BitEn: MSI 64-bit Enabled. */
336	#define IOMMU_BF_MSI_CAPHDR_64BIT_EN_SHIFT 23
337	#define IOMMU_BF_MSI_CAPHDR_64BIT_EN_MASK UINT32_C(0x00800000)
338	/** Bits 31:24 reserved. */
339	#define IOMMU_BF_MSI_CAPHDR_RSVD_24_31_SHIFT 24
340	#define IOMMU_BF_MSI_CAPHDR_RSVD_24_31_MASK UINT32_C(0xff000000)
341	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAPHDR_, UINT32_C(0), UINT32_MAX,
342	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
343	/** @} */
344
345	/**
346	* @name MSI Mapping Capability Header Register.
347	* In accordance with the AMD spec.
348	* @{
349	*/
350	/** MsiMapCapId: Capability ID. */
351	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
352	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
353	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
354	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
355	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
356	/** MsiMapEn: MSI mapping capability enable. */
357	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
358	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
359	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
360	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
361	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
362	/** Bits 18:28 reserved. */
363	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
364	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
365	/** MsiMapCapType: MSI mapping capability. */
366	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
367	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
368	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
369	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
370	/** @} */
371
372	/** @name Miscellaneous IOMMU defines.
373	* @{ */
374	#define IOMMU_LOG_PFX "AMD_IOMMU" /*< Log prefix string. /
375	#define IOMMU_SAVED_STATE_VERSION 1 /*< The current saved state version. /
376	#define IOMMU_PCI_VENDOR_ID 0x1022 /*< AMD's vendor ID. /
377	#define IOMMU_PCI_DEVICE_ID 0xc0de /*< VirtualBox IOMMU device ID. /
378	#define IOMMU_PCI_REVISION_ID 0x01 /*< VirtualBox IOMMU device revision ID. /
379	#define IOMMU_MMIO_REGION_SIZE _16K /*< Size of the MMIO region in bytes. /
380	/** @} */
381
382	/**
383	* Acquires the IOMMU PDM lock or returns @a a_rcBusy if it's busy.
384	*/
385	#define IOMMU_LOCK_RET(a_pDevIns, a_pThis, a_rcBusy) \
386	do { \
387	NOREF(pThis); \
388	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), (a_rcBusy)); \
389	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
390	{ /* likely */ } \
391	else \
392	return rcLock; \
393	} while (0)
394
395	/**
396	* Releases the IOMMU PDM lock.
397	*/
398	#define IOMMU_UNLOCK(a_pDevIns, a_pThis) \
399	do { \
400	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
401	} while (0)
402
403
404	/*********************************************************************************************************************************
405	* Structures and Typedefs *
406	*********************************************************************************************************************************/
407	/**
408	* The Device ID.
409	* In accordance with the AMD spec.
410	*/
411	typedef union
412	{
413	struct
414	{
415	uint16_t uFunction : 3; /*< Bits 2:0 - Function. /
416	uint16_t uDevice : 5; /*< Bits 7:3 - Device. /
417	uint16_t uBus : 8; /*< Bits 15:8 - Bus. /
418	} n;
419	/** The unsigned integer view. */
420	uint16_t u;
421	} DEVICE_ID_T;
422	AssertCompileSize(DEVICE_ID_T, 2);
423
424	/**
425	* Device Table Entry (DTE).
426	* In accordance with the AMD spec.
427	*/
428	typedef union
429	{
430	struct
431	{
432	uint32_t u1Valid : 1; /*< Bit 0 - V: Valid. /
433	uint32_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
434	uint32_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
435	uint32_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
436	uint32_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
437	uint32_t u20PageTableRootPtrLo : 20; /*< Bits 31:12 - Page Table Root Pointer (Lo). /
438	uint32_t u20PageTableRootPtrHi : 20; /*< Bits 51:32 - Page Table Root Pointer (Hi). /
439	uint32_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
440	uint32_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
441	uint32_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
442	uint32_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
443	uint32_t u2GstCr3RootTblTranslated : 2; /*< Bits 57:56 - GLX: Guest Levels Translated. /
444	uint32_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Pointer (Lo). /
445	uint32_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
446	uint32_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
447	uint32_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
448	uint32_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
449	uint32_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Pointer (Mid). /
450	uint32_t u1IoTlbEnable : 1; /*< Bit 96 - IOTLB Enable. /
451	uint32_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
452	uint32_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
453	uint32_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
454	uint32_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
455	uint32_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
456	uint32_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
457	uint32_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
458	uint32_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
459	uint32_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Pointer (Hi). /
460	uint32_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
461	uint32_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
462	uint32_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
463	uint32_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
464	uint32_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
465	uint32_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
466	uint32_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
467	uint32_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
468	uint32_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
469	uint32_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
470	uint32_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
471	uint32_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 (Legacy PIC NMI) Pass-thru. /
472	uint32_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 (Legacy PIC NMI) Pass-thru. /
473	uint32_t u32Rsvd0; /*< Bits 223:192 - Reserved. /
474	uint32_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
475	uint32_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
476	uint32_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
477	uint32_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
478	} n;
479	/** The 32-bit unsigned integer view. */
480	uint32_t au32[8];
481	} DEV_TAB_ENTRY_T;
482	AssertCompileSize(DEV_TAB_ENTRY_T, 32);
483
484	/**
485	* I/O Page Table Entry.
486	* In accordance with the AMD spec.
487	*/
488	typedef union
489	{
490	struct
491	{
492	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
493	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
494	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
495	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
496	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
497	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
498	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
499	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
500	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
501	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
502	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
503	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
504	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
505	} n;
506	/** The 64-bit unsigned integer view. */
507	uint64_t u;
508	} IOPTE_T;
509	AssertCompileSize(IOPTE_T, 8);
510
511	/**
512	* I/O Page Directory Entry.
513	* In accordance with the AMD spec.
514	*/
515	typedef union
516	{
517	struct
518	{
519	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
520	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
521	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
522	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
523	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
524	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
525	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
526	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
527	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
528	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
529	} n;
530	/** The 64-bit unsigned integer view. */
531	uint64_t u;
532	} IOPDE_T;
533	AssertCompileSize(IOPDE_T, 8);
534
535	/**
536	* Interrupt Remapping Table Entry.
537	* In accordance with the AMD spec.
538	*/
539	typedef union
540	{
541	struct
542	{
543	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
544	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
545	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
546	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
547	uint32_t u1DstMode : 1; /*< Bit 6 - DM: Destination Mode. /
548	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
549	uint32_t u8Dst : 8; /*< Bits 15:8 - Destination. /
550	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
551	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
552	} n;
553	/** The 32-bit unsigned integer view. */
554	uint32_t u;
555	} IRTE_T;
556	AssertCompileSize(IRTE_T, 4);
557
558	/**
559	* Command: Generic Command Buffer Entry.
560	* In accordance with the AMD spec.
561	*/
562	typedef union
563	{
564	struct
565	{
566	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
567	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
568	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
569	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
570	} n;
571	/** The 64-bit unsigned integer view. */
572	uint64_t au64[2];
573	} CMD_GENERIC_T;
574	AssertCompileSize(CMD_GENERIC_T, 16);
575
576	/**
577	* Command: COMPLETION_WAIT.
578	* In accordance with the AMD spec.
579	*/
580	typedef union
581	{
582	struct
583	{
584	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
585	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
586	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
587	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
588	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
589	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
590	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
591	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
592	} n;
593	/** The 64-bit unsigned integer view. */
594	uint32_t au64[2];
595	} CMD_COMPLETION_WAIT_T;
596	AssertCompileSize(CMD_COMPLETION_WAIT_T, 16);
597
598	/**
599	* Command: INVALIDATE_DEVTAB_ENTRY.
600	* In accordance with the AMD spec.
601	*/
602	typedef union
603	{
604	struct
605	{
606	uint16_t u16DeviceId; /*< Bits 15:0 - DeviceID. /
607	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
608	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
609	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
610	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
611	} n;
612	/** The 64-bit unsigned integer view. */
613	uint64_t au64[2];
614	} CMD_INV_DEV_TAB_ENTRY_T;
615	AssertCompileSize(CMD_INV_DEV_TAB_ENTRY_T, 16);
616
617	/**
618	* Command: INVALIDATE_IOMMU_PAGES.
619	* In accordance with the AMD spec.
620	*/
621	typedef union
622	{
623	struct
624	{
625	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
626	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
627	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
628	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
629	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
630	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
631	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
632	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
633	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
634	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
635	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
636	} n;
637	/** The 64-bit unsigned integer view. */
638	uint64_t au64[2];
639	} CMD_INV_IOMMU_PAGES_T;
640	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
641
642	/**
643	* Command: INVALIDATE_IOTLB_PAGES.
644	* In accordance with the AMD spec.
645	*/
646	typedef union
647	{
648	struct
649	{
650	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
651	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
652	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
653	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
654	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
655	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
656	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
657	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
658	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
659	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
660	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
661	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
662	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
663	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
664	} n;
665	/** The 64-bit unsigned integer view. */
666	uint64_t au64[2];
667	} CMD_INV_IOTLB_PAGES_T;
668	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
669
670	/**
671	* Command: INVALIDATE_INTR_TABLE.
672	* In accordance with the AMD spec.
673	*/
674	typedef union
675	{
676	struct
677	{
678	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
679	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
680	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
681	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
682	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
683	} u;
684	/** The 64-bit unsigned integer view. */
685	uint64_t au64[2];
686	} CMD_INV_INTR_TABLE_T;
687	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
688
689	/**
690	* Command: COMPLETE_PPR_REQ.
691	* In accordance with the AMD spec.
692	*/
693	typedef union
694	{
695	struct
696	{
697	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
698	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
699	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
700	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
701	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
702	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
703	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
704	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
705	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
706	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
707	} n;
708	/** The 64-bit unsigned integer view. */
709	uint64_t au64[2];
710	} CMD_COMPLETE_PPR_REQ_T;
711	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
712
713	/**
714	* Command: INV_IOMMU_ALL.
715	* In accordance with the AMD spec.
716	*/
717	typedef union
718	{
719	struct
720	{
721	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
722	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
723	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
724	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
725	} n;
726	/** The 64-bit unsigned integer view. */
727	uint64_t au64[2];
728	} CMD_IOMMU_ALL_T;
729	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
730
731	/**
732	* Event Log Entry: Generic.
733	* In accordance with the AMD spec.
734	*/
735	typedef union
736	{
737	struct
738	{
739	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
740	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
741	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
742	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
743	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
744	} n;
745	/** The 32-bit unsigned integer view. */
746	uint32_t au32[4];
747	} EVT_GENERIC_T;
748	AssertCompileSize(EVT_GENERIC_T, 16);
749
750	/**
751	* Event Log Entry: ILLEGAL_DEV_TAB_ENTRY.
752	* In accordance with the AMD spec.
753	*/
754	typedef union
755	{
756	struct
757	{
758	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
759	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
760	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
761	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
762	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
763	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
764	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
765	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
766	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
767	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
768	uint16_t u1RsvdZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. /
769	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
770	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
771	uint16_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
772	uint32_t u2Rsvd1 : 2; /*< Bits 65:64 - Reserved. /
773	uint32_t u30AddrLo : 2; /*< Bits 95:66 - Address: Device Virtual Address (Lo). /
774	uint32_t u30AddrHi; /*< Bits 127:96 - Address: Device Virtual Address (Hi). /
775	} n;
776	/** The 32-bit unsigned integer view. */
777	uint32_t au32[4];
778	} EVT_ILLEGAL_DEV_TAB_ENTRY_T;
779	AssertCompileSize(EVT_ILLEGAL_DEV_TAB_ENTRY_T, 16);
780
781	/**
782	* Event Log Entry: IO_PAGE_FAULT_EVENT.
783	* In accordance with the AMD spec.
784	*/
785	typedef union
786	{
787	struct
788	{
789	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
790	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
791	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
792	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
793	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
794	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
795	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
796	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
797	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
798	uint16_t u1Perm : 1; /*< Bit 54 - PE: Permission Indicator. /
799	uint16_t u1RsvdZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero or invalid level encoding. /
800	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
801	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
802	uint16_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
803	uint64_t u64Addr; /*< Bits 127:64 - Address: Device Virtual Address. /
804	} n;
805	/** The 32-bit unsigned integer view. */
806	uint32_t au32[4];
807	} EVT_IO_PAGE_FAULT_T;
808	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
809
810	/**
811	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
812	* In accordance with the AMD spec.
813	*/
814	typedef union
815	{
816	struct
817	{
818	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
819	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
820	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
821	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt. /
822	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
823	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
824	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
825	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
826	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
827	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
828	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
829	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
830	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: System Physical Address (Lo). /
831	uint32_t u32AddrHi; /*< Bits 127:96 - Address: System Physical Address (Hi). /
832	} n;
833	/** The 32-bit unsigned integer view. */
834	uint32_t au32[4];
835	} EVT_DEV_TAB_HARDWARE_ERROR;
836	AssertCompileSize(EVT_DEV_TAB_HARDWARE_ERROR, 16);
837
838	/**
839	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
840	* In accordance with the AMD spec.
841	*/
842	typedef union
843	{
844	struct
845	{
846	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
847	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
848	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
849	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
850	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
851	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
852	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
853	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
854	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
855	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
856	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
857	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
858	uint32_t u4EventCode : 4; /*< Bit 63:60 - Event code. /
859	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
860	* table 58 mentions Addr[31:4]. Looks like a typo in the figure. Use
861	* table as it makes more sense and matches address size in
862	* EVT_DEV_TAB_HARDWARE_ERROR. See AMD AMD IOMMU spec (3.05-PUB, Jan
863	* 2020). */
864	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
865	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of page table entry (Lo). /
866	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of page table entry (Hi). /
867	} n;
868	/** The 32-bit unsigned integer view. */
869	uint32_t au32[4];
870	} EVT_PAGE_TAB_HARDWARE_ERROR;
871	AssertCompileSize(EVT_PAGE_TAB_HARDWARE_ERROR, 16);
872
873	/**
874	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
875	* In accordance with the AMD spec.
876	*/
877	typedef union
878	{
879	struct
880	{
881	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
882	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
883	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
884	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
885	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalid command (Lo). /
886	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalid command (Hi). /
887	} n;
888	/** The 32-bit unsigned integer view. */
889	uint32_t au32[4];
890	} EVT_ILLEGAL_COMMAND_ENTRY;
891	AssertCompileSize(EVT_ILLEGAL_COMMAND_ENTRY, 16);
892
893	/**
894	* Event Log Entry: COMMAND_HARDWARE_ERROR.
895	* In accordance with the AMD spec.
896	*/
897	typedef union
898	{
899	struct
900	{
901	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
902	uint32_t u4Rsvd0 : 4; /*< Bits 35:32 - Reserved. /
903	uint32_t u28AddrLo : 28; /*< Bits 63:36 - Address: SPA of the attempted access (Lo). /
904	uint32_t u32AddrHi; /*< Bits 95:64 - Address: SPA of the attempted access (Hi). /
905	} n;
906	/** The 32-bit unsigned integer view. */
907	uint32_t au32[3];
908	} EVT_COMMAND_HARDWARE_ERROR;
909	AssertCompileSize(EVT_COMMAND_HARDWARE_ERROR, 12);
910
911	/**
912	* Event Log Entry: IOTLB_INV_TIMEOUT.
913	* In accordance with the AMD spec.
914	*/
915	typedef union
916	{
917	struct
918	{
919	uint16_t u16DeviceId; /*< Bits 15:0 - Device ID. /
920	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
921	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
922	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
923	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
924	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
925	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
926	} n;
927	/** The 32-bit unsigned integer view. */
928	uint32_t au32[4];
929	} EVT_IOTLB_INV_TIMEOUT;
930	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT, 16);
931
932	/**
933	* Event Log Entry: INVALID_DEVICE_REQUEST.
934	* In accordance with the AMD spec.
935	*/
936	typedef union
937	{
938	struct
939	{
940	uint32_t u16DeviceId : 16; /**< Bits 15:0 - Device ID. /
941	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
942	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
943	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
944	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
945	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
946	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
947	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
948	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
949	uint32_t u4EventCode : 4; /**< Bits 63:60 - Event code. /
950	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
951	} n;
952	/** The 32-bit unsigned integer view. */
953	uint32_t au32[4];
954	} EVT_INVALID_DEVICE_REQUEST;
955	AssertCompileSize(EVT_INVALID_DEVICE_REQUEST, 16);
956
957	/**
958	* Event Log Entry: EVENT_COUNTER_ZERO.
959	* In accordance with the AMD spec.
960	*/
961	typedef union
962	{
963	struct
964	{
965	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
966	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
967	uint32_t u4EventCode : 4; /*< Bits 63:60 - Event code. /
968	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
969	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
970	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
971	} n;
972	/** The 32-bit unsigned integer view. */
973	uint32_t au32[4];
974	} EVT_EVENT_COUNTER_ZERO;
975	AssertCompileSize(EVT_EVENT_COUNTER_ZERO, 16);
976
977	/* Not needed as we can initialize from bitfields and set/get using PCI config PDM helpers. */
978	#if 0
979	/**
980	* IOMMU Capability Header (PCI).
981	* In accordance with the AMD spec.
982	*/
983	typedef union
984	{
985	struct
986	{
987	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
988	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
989	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
990	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
991	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
992	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
993	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
994	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
995	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
996	uint32_t u4Rsvd0 : 4; /*< Bits 31:29 - Reserved. /
997	} n;
998	/** The 32-bit unsigned integer view. */
999	uint32_t u32;
1000	} IOMMU_CAP_HDR_T;
1001	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1002	#endif
1003
1004	/**
1005	* IOMMU Base Address (Lo and Hi) Register (PCI).
1006	* In accordance with the AMD spec.
1007	*/
1008	typedef union
1009	{
1010	struct
1011	{
1012	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1013	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1014	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1015	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1016	} n;
1017	/** The 32-bit unsigned integer view. */
1018	uint32_t au32[2];
1019	/** The 64-bit unsigned integer view. */
1020	uint64_t u64;
1021	} IOMMU_BAR_T;
1022	AssertCompileSize(IOMMU_BAR_T, 8);
1023	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1024
1025	/**
1026	* IOMMU Range Register (PCI).
1027	* In accordance with the AMD spec.
1028	*/
1029	typedef union
1030	{
1031	struct
1032	{
1033	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1034	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1035	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1036	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1037	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1038	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1039	} n;
1040	/** The 32-bit unsigned integer view. */
1041	uint32_t u32;
1042	} IOMMU_RANGE_T;
1043	AssertCompileSize(IOMMU_RANGE_T, 4);
1044
1045	/**
1046	* Device Table Base Address Register (MMIO).
1047	* In accordance with the AMD spec.
1048	*/
1049	typedef union
1050	{
1051	struct
1052	{
1053	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1054	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1055	RT_GCC_EXTENSION uint64_t u40DevTabBase : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1056	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1057	} n;
1058	/** The 64-bit unsigned integer view. */
1059	uint64_t u64;
1060	} DEV_TAB_BAR_T;
1061	AssertCompileSize(DEV_TAB_BAR_T, 8);
1062	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff3ff)
1063
1064	/**
1065	* Command Buffer Base Address Register (MMIO).
1066	* In accordance with the AMD spec.
1067	*/
1068	typedef union
1069	{
1070	struct
1071	{
1072	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1073	RT_GCC_EXTENSION uint64_t u40CmdBase : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1074	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1075	RT_GCC_EXTENSION uint64_t u4CmdLen : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1076	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1077	} n;
1078	/** The 64-bit unsigned integer view. */
1079	uint64_t u64;
1080	} CMD_BUF_BAR_T;
1081	AssertCompileSize(CMD_BUF_BAR_T, 8);
1082	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1083
1084	/**
1085	* Event Log Base Address Register (MMIO).
1086	* In accordance with the AMD spec.
1087	*/
1088	typedef union
1089	{
1090	struct
1091	{
1092	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1093	RT_GCC_EXTENSION uint64_t u40EvtBase : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1094	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1095	RT_GCC_EXTENSION uint64_t u4EvtLen : 4; /*< Bits 59:56 - EventLen: Event log length. /
1096	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1097	} n;
1098	/** The 64-bit unsigned integer view. */
1099	uint64_t u64;
1100	} EVT_LOG_BAR_T;
1101	AssertCompileSize(EVT_LOG_BAR_T, 8);
1102	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1103
1104	/**
1105	* IOMMU Control Register (MMIO).
1106	* In accordance with the AMD spec.
1107	*/
1108	typedef union
1109	{
1110	struct
1111	{
1112	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1113	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1114	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1115	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1116	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1117	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1118	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1119	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1120	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1121	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1122	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1123	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1124	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1125	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1126	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1127	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1128	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1129	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1130	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1131	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1132	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1133	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1134	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1135	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1136	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1137	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1138	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1139	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1140	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1141	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1142	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1143	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1144	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1145	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1146	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1147	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1148	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1149	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1150	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1151	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1152	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1153	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1154	} n;
1155	/** The 64-bit unsigned integer view. */
1156	uint64_t u64;
1157	} IOMMU_CTRL_T;
1158	AssertCompileSize(IOMMU_CTRL_T, 8);
1159
1160	/**
1161	* IOMMU Exclusion Base Register (MMIO).
1162	* In accordance with the AMD spec.
1163	*/
1164	typedef union
1165	{
1166	struct
1167	{
1168	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1169	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1170	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1171	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1172	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1173	} n;
1174	/** The 64-bit unsigned integer view. */
1175	uint64_t u64;
1176	} IOMMU_EXCL_RANGE_BAR_T;
1177	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1178	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1179
1180	/**
1181	* IOMMU Exclusion Range Limit Register (MMIO).
1182	* In accordance with the AMD spec.
1183	*/
1184	typedef union
1185	{
1186	struct
1187	{
1188	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1189	RT_GCC_EXTENSION uint64_t u40ExclLimit : 40; /*< Bits 51:12 - Exclusion Range Limit. /
1190	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1191	} n;
1192	/** The 64-bit unsigned integer view. */
1193	uint64_t u64;
1194	} IOMMU_EXCL_RANGE_LIMIT_T;
1195	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1196	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000ffffffffff000)
1197
1198	/**
1199	* IOMMU Extended Feature Register (MMIO).
1200	* In accordance with the AMD spec.
1201	*/
1202	typedef union
1203	{
1204	struct
1205	{
1206	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1207	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1208	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1209	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1210	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations Support. /
1211	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1212	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1213	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1214	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1215	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1216	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1217	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1218	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1219	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1220	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1221	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1222	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1223	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1224	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1225	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1226	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1227	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1228	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1229	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1230	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1231	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1232	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1233	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1234	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1235	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1236	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1237	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1238	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1239	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1240	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1241	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1242	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1243	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1244	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1245	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1246	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1247	} n;
1248	/** The 64-bit unsigned integer view. */
1249	uint64_t u64;
1250	} IOMMU_EXT_FEAT_T;
1251	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1252
1253	/**
1254	* Peripheral Page Request Log Base Address Register (MMIO).
1255	* In accordance with the AMD spec.
1256	*/
1257	typedef union
1258	{
1259	struct
1260	{
1261	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1262	RT_GCC_EXTENSION uint64_t u40PprLogBase : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1263	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1264	RT_GCC_EXTENSION uint64_t u4PprLogLen : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1265	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1266	} n;
1267	/** The 64-bit unsigned integer view. */
1268	uint64_t u64;
1269	} PPR_LOG_BAR_T;
1270	AssertCompileSize(PPR_LOG_BAR_T, 8);
1271	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1272
1273	/**
1274	* IOMMU Hardware Event Upper Register (MMIO).
1275	* In accordance with the AMD spec.
1276	*/
1277	typedef union
1278	{
1279	struct
1280	{
1281	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1282	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1283	} n;
1284	/** The 64-bit unsigned integer view. */
1285	uint64_t u64;
1286	} IOMMU_HW_EVT_HI_T;
1287	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1288
1289	/**
1290	* IOMMU Hardware Event Lower Register (MMIO).
1291	* In accordance with the AMD spec.
1292	*/
1293	typedef uint64_t IOMMU_HW_EVT_LO_T;
1294
1295	/**
1296	* IOMMU Hardware Event Status (MMIO).
1297	* In accordance with the AMD spec.
1298	*/
1299	typedef union
1300	{
1301	struct
1302	{
1303	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1304	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1305	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1306	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1307	} n;
1308	/** The 64-bit unsigned integer view. */
1309	uint64_t u64;
1310	} IOMMU_HW_EVT_STATUS_T;
1311	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1312	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1313
1314	/**
1315	* Guest Virtual-APIC Log Base Address Register (MMIO).
1316	* In accordance with the AMD spec.
1317	*/
1318	typedef union
1319	{
1320	struct
1321	{
1322	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1323	RT_GCC_EXTENSION uint64_t u40GALogBase : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1324	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1325	RT_GCC_EXTENSION uint64_t u4GALogLen : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1326	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1327	} n;
1328	/** The 64-bit unsigned integer view. */
1329	uint64_t u64;
1330	} GALOG_BAR_T;
1331	AssertCompileSize(GALOG_BAR_T, 8);
1332
1333	/**
1334	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1335	* In accordance with the AMD spec.
1336	*/
1337	typedef union
1338	{
1339	struct
1340	{
1341	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1342	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1343	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1344	} n;
1345	/** The 64-bit unsigned integer view. */
1346	uint64_t u64;
1347	} GALOG_TAIL_ADDR_T;
1348	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1349
1350	/**
1351	* PPR Log B Base Address Register (MMIO).
1352	* In accordance with the AMD spec.
1353	* Currently identical to PPR_LOG_BAR_T.
1354	*/
1355	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1356
1357	/**
1358	* Event Log B Base Address Register (MMIO).
1359	* In accordance with the AMD spec.
1360	* Currently identical to EVT_LOG_BAR_T.
1361	*/
1362	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1363
1364	/**
1365	* Device Table Segment Register (MMIO).
1366	* In accordance with the AMD spec.
1367	*/
1368	typedef union
1369	{
1370	struct
1371	{
1372	RT_GCC_EXTENSION uint64_t u8Size : 8; /*< Bits 7:0 - Size: Size of the Device Table segment. /
1373	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 11:8 - Reserved. /
1374	RT_GCC_EXTENSION uint64_t u40DevTabBase : 40; /*< Bits 51:12 - DevTabBase: Device Table Segment Base Address. /
1375	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1376	} n;
1377	/** The 64-bit unsigned integer view. */
1378	uint64_t u64;
1379	} DEV_TAB_SEG_BAR_T;
1380	AssertCompileSize(DEV_TAB_SEG_BAR_T, 8);
1381
1382	/**
1383	* Device-specific Feature Extension (DSFX) Register (MMIO).
1384	* In accordance with the AMD spec.
1385	*/
1386	typedef union
1387	{
1388	struct
1389	{
1390	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1391	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1392	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1393	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1394	} n;
1395	/** The 64-bit unsigned integer view. */
1396	uint64_t u64;
1397	} DEV_SPECIFIC_FEAT_T;
1398	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1399
1400	/**
1401	* Device-specific Control Extension (DSCX) Register (MMIO).
1402	* In accordance with the AMD spec.
1403	*/
1404	typedef union
1405	{
1406	struct
1407	{
1408	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1409	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1410	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1411	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1412	} n;
1413	/** The 64-bit unsigned integer view. */
1414	uint64_t u64;
1415	} DEV_SPECIFIC_CTRL_T;
1416	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1417
1418	/**
1419	* Device-specific Status Extension (DSSX) Register (MMIO).
1420	* In accordance with the AMD spec.
1421	*/
1422	typedef union
1423	{
1424	struct
1425	{
1426	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1427	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1428	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1429	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1430	} n;
1431	/** The 64-bit unsigned integer view. */
1432	uint64_t u64;
1433	} DEV_SPECIFIC_STATUS_T;
1434	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1435
1436	/**
1437	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1438	* In accordance with the AMD spec.
1439	*/
1440	typedef union
1441	{
1442	struct
1443	{
1444	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1445	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1446	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1447	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1448	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1449	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1450	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1451	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1452	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1453	} n;
1454	/** The 32-bit unsigned integer view. */
1455	uint32_t au32[2];
1456	/** The 64-bit unsigned integer view. */
1457	uint64_t u64;
1458	} MSI_MISC_INFO_T;
1459	AssertCompileSize(MSI_MISC_INFO_T, 8);
1460	/** MSI Vector Register 0 and 1 (MMIO). */
1461	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1462
1463	/**
1464	* MSI Capability Header Register (PCI + MMIO).
1465	* In accordance with the AMD spec.
1466	*/
1467	typedef union
1468	{
1469	struct
1470	{
1471	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1472	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1473	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1474	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1475	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1476	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1477	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1478	} n;
1479	/** The 32-bit unsigned integer view. */
1480	uint32_t u32;
1481	} MSI_CAP_HDR_T;
1482	AssertCompileSize(MSI_CAP_HDR_T, 4);
1483
1484	/**
1485	* MSI Address Register (PCI + MMIO).
1486	* In accordance with the AMD spec.
1487	*/
1488	typedef union
1489	{
1490	struct
1491	{
1492	RT_GCC_EXTENSION uint64_t u2Rsvd : 2; /*< Bits 1:0 - Reserved. /
1493	RT_GCC_EXTENSION uint64_t u62MsiAddr : 62; /*< Bits 31:2 - MsiAddr: MSI Address. /
1494	} n;
1495	/** The 32-bit unsigned integer view. */
1496	uint32_t au32[2];
1497	/** The 64-bit unsigned integer view. */
1498	uint64_t u64;
1499	} MSI_ADDR_T;
1500	AssertCompileSize(MSI_ADDR_T, 8);
1501	#define IOMMU_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc)
1502
1503	/**
1504	* MSI Data Register (PCI + MMIO).
1505	* In accordance with the AMD spec.
1506	*/
1507	typedef union
1508	{
1509	struct
1510	{
1511	uint16_t u16MsiData; /*< Bits 15:0 - MsiData: MSI Data. /
1512	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1513	} n;
1514	/** The 32-bit unsigned integer view. */
1515	uint32_t u32;
1516	} MSI_DATA_T;
1517	AssertCompileSize(MSI_DATA_T, 4);
1518	#define IOMMU_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff)
1519
1520	/**
1521	* MSI Mapping Capability Header Register (PCI + MMIO).
1522	* In accordance with the AMD spec.
1523	*/
1524	typedef union
1525	{
1526	struct
1527	{
1528	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1529	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1530	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1531	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1532	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1533	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1534	} n;
1535	/** The 32-bit unsigned integer view. */
1536	uint32_t u32;
1537	} MSI_MAP_CAP_HDR_T;
1538	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1539
1540	/**
1541	* Performance Optimization Control Register (MMIO).
1542	* In accordance with the AMD spec.
1543	*/
1544	typedef union
1545	{
1546	struct
1547	{
1548	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1549	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1550	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1551	} n;
1552	/** The 32-bit unsigned integer view. */
1553	uint32_t u32;
1554	} IOMMU_PERF_OPT_CTRL_T;
1555	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1556
1557	/**
1558	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1559	* In accordance with the AMD spec.
1560	*/
1561	typedef union
1562	{
1563	struct
1564	{
1565	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1566	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1567	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1568	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1569	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1570	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1571	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1572	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1573	} n;
1574	/** The 64-bit unsigned integer view. */
1575	uint64_t u64;
1576	} IOMMU_XT_GEN_INTR_CTRL_T;
1577	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1578
1579	/**
1580	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1581	* In accordance with the AMD spec.
1582	*/
1583	typedef union
1584	{
1585	struct
1586	{
1587	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1588	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1589	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1590	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1591	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1592	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1593	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1594	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1595	} n;
1596	/** The 64-bit unsigned integer view. */
1597	uint64_t u64;
1598	} IOMMU_XT_INTR_CTRL_T;
1599	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1600
1601	/**
1602	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1603	* In accordance with the AMD spec.
1604	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1605	*/
1606	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1607
1608	/**
1609	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1610	* In accordance with the AMD spec.
1611	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1612	*/
1613	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1614
1615	/**
1616	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1617	* In accordance with the AMD spec.
1618	*/
1619	typedef union
1620	{
1621	struct
1622	{
1623	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1624	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1625	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1626	} n;
1627	/** The 64-bit unsigned integer view. */
1628	uint64_t u64;
1629	} MARC_APER_BAR_T;
1630	AssertCompileSize(MARC_APER_BAR_T, 8);
1631
1632	/**
1633	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1634	* In accordance with the AMD spec.
1635	*/
1636	typedef union
1637	{
1638	struct
1639	{
1640	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1641	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1642	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1643	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1644	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1645	} n;
1646	/** The 64-bit unsigned integer view. */
1647	uint64_t u64;
1648	} MARC_APER_RELOC_T;
1649	AssertCompileSize(MARC_APER_RELOC_T, 8);
1650
1651	/**
1652	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1653	* In accordance with the AMD spec.
1654	*/
1655	typedef union
1656	{
1657	struct
1658	{
1659	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1660	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1661	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1662	} n;
1663	/** The 64-bit unsigned integer view. */
1664	uint64_t u64;
1665	} MARC_APER_LEN_T;
1666
1667	/**
1668	* Memory Access and Routing Control (MARC) Aperture Register.
1669	* This combines other registers to match the MMIO layout for convenient access.
1670	*/
1671	typedef struct
1672	{
1673	MARC_APER_BAR_T Base;
1674	MARC_APER_RELOC_T Reloc;
1675	MARC_APER_LEN_T Length;
1676	} MARC_APER_T;
1677	AssertCompileSize(MARC_APER_T, 24);
1678
1679	/**
1680	* IOMMU Reserved Register (MMIO).
1681	* In accordance with the AMD spec.
1682	* This register is reserved for hardware use (although RW?).
1683	*/
1684	typedef uint64_t IOMMU_RSVD_REG_T;
1685
1686	/**
1687	* Command Buffer Head Pointer Register (MMIO).
1688	* In accordance with the AMD spec.
1689	*/
1690	typedef union
1691	{
1692	struct
1693	{
1694	uint32_t u4Rsvd0 : 4; /*< Bits 3:0 - Reserved. /
1695	uint32_t u15Ptr : 15; /*< Bits 18:4 - Buffer pointer. /
1696	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1697	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1698	} n;
1699	/** The 32-bit unsigned integer view. */
1700	uint32_t au32[2];
1701	/** The 64-bit unsigned integer view. */
1702	uint64_t u64;
1703	} CMD_BUF_HEAD_PTR_T;
1704	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1705	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1706
1707	/**
1708	* Command Buffer Tail Pointer Register (MMIO).
1709	* In accordance with the AMD spec.
1710	* Currently identical to CMD_BUF_HEAD_PTR_T.
1711	*/
1712	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1713	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1714
1715
1716	/**
1717	* Event Log Head Pointer Register (MMIO).
1718	* In accordance with the AMD spec.
1719	* Currently identical to CMD_BUF_HEAD_PTR_T.
1720	*/
1721	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1722
1723	/**
1724	* Event Log Tail Pointer Register (MMIO).
1725	* In accordance with the AMD spec.
1726	* Currently identical to CMD_BUF_HEAD_PTR_T.
1727	*/
1728	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1729
1730	/**
1731	* IOMMU Status Register (MMIO).
1732	* In accordance with the AMD spec.
1733	*/
1734	typedef union
1735	{
1736	struct
1737	{
1738	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
1739	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
1740	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
1741	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
1742	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
1743	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
1744	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
1745	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
1746	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
1747	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
1748	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
1749	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
1750	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
1751	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
1752	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
1753	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
1754	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
1755	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
1756	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1757	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
1758	} n;
1759	/** The 32-bit unsigned integer view. */
1760	uint32_t au32[2];
1761	/** The 64-bit unsigned integer view. */
1762	uint64_t u64;
1763	} IOMMU_STATUS_T;
1764	AssertCompileSize(IOMMU_STATUS_T, 8);
1765
1766	/**
1767	* PPR Log Head Pointer Register (MMIO).
1768	* In accordance with the AMD spec.
1769	* Currently identical to CMD_BUF_HEAD_PTR_T.
1770	*/
1771	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
1772
1773	/**
1774	* PPR Log Tail Pointer Register (MMIO).
1775	* In accordance with the AMD spec.
1776	* Currently identical to CMD_BUF_HEAD_PTR_T.
1777	*/
1778	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
1779
1780	/**
1781	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
1782	* In accordance with the AMD spec.
1783	*/
1784	typedef union
1785	{
1786	struct
1787	{
1788	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
1789	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
1790	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
1791	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1792	} n;
1793	/** The 32-bit unsigned integer view. */
1794	uint32_t au32[2];
1795	/** The 64-bit unsigned integer view. */
1796	uint64_t u64;
1797	} GALOG_HEAD_PTR_T;
1798	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
1799
1800	/**
1801	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
1802	* In accordance with the AMD spec.
1803	* Currently identical to GALOG_HEAD_PTR_T.
1804	*/
1805	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
1806
1807	/**
1808	* PPR Log B Head Pointer Register (MMIO).
1809	* In accordance with the AMD spec.
1810	* Currently identical to CMD_BUF_HEAD_PTR_T.
1811	*/
1812	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
1813
1814	/**
1815	* PPR Log B Tail Pointer Register (MMIO).
1816	* In accordance with the AMD spec.
1817	* Currently identical to CMD_BUF_HEAD_PTR_T.
1818	*/
1819	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
1820
1821	/**
1822	* Event Log B Head Pointer Register (MMIO).
1823	* In accordance with the AMD spec.
1824	* Currently identical to CMD_BUF_HEAD_PTR_T.
1825	*/
1826	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
1827
1828	/**
1829	* Event Log B Tail Pointer Register (MMIO).
1830	* In accordance with the AMD spec.
1831	* Currently identical to CMD_BUF_HEAD_PTR_T.
1832	*/
1833	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
1834
1835	/**
1836	* PPR Log Auto Response Register (MMIO).
1837	* In accordance with the AMD spec.
1838	*/
1839	typedef union
1840	{
1841	struct
1842	{
1843	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
1844	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
1845	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
1846	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1847	} n;
1848	/** The 32-bit unsigned integer view. */
1849	uint32_t au32[2];
1850	/** The 64-bit unsigned integer view. */
1851	uint64_t u64;
1852	} PPR_LOG_AUTO_RESP_T;
1853	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
1854
1855	/**
1856	* PPR Log Overflow Early Indicator Register (MMIO).
1857	* In accordance with the AMD spec.
1858	*/
1859	typedef union
1860	{
1861	struct
1862	{
1863	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
1864	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
1865	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
1866	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
1867	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1868	} n;
1869	/** The 32-bit unsigned integer view. */
1870	uint32_t au32[2];
1871	/** The 64-bit unsigned integer view. */
1872	uint64_t u64;
1873	} PPR_LOG_OVERFLOW_EARLY_T;
1874	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
1875
1876	/**
1877	* PPR Log B Overflow Early Indicator Register (MMIO).
1878	* In accordance with the AMD spec.
1879	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
1880	*/
1881	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
1882
1883
1884	/**
1885	* The shared IOMMU device state.
1886	*/
1887	typedef struct IOMMU
1888	{
1889	/** IOMMU device index. */
1890	uint32_t idxIommu;
1891	/** Alignment padding. */
1892	uint32_t uPadding0;
1893	/** The event semaphore the command thread waits on. */
1894	SUPSEMEVENT hEvtCmdThread;
1895	/** The MMIO handle. */
1896	IOMMMIOHANDLE hMmio;
1897	/** Whether this IOMMU is at the top of the PCI tree hierarchy or not. */
1898	bool fRootComplex;
1899	/** Alignment padding. */
1900	bool afPadding[7];
1901
1902	/** @name PCI: Base capability block registers.
1903	* @{ */
1904	IOMMU_BAR_T IommuBar;
1905	/** @} */
1906
1907	/** @name MMIO: Control and status registers.
1908	* @{ */
1909	DEV_TAB_BAR_T DevTabBaseAddr; /*< Device table base address register. /
1910	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
1911	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
1912	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
1913	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
1914	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
1915	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
1916	/** @} */
1917
1918	/** @name MMIO: PPR Log registers.
1919	* @{ */
1920	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
1921	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
1922	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
1923	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
1924	/** @} */
1925
1926	/** @todo IOMMU: SMI filter. */
1927
1928	/** @name MMIO: Guest Virtual-APIC Log registers.
1929	* @{ */
1930	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
1931	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
1932	/** @} */
1933
1934	/** @name MMIO: Alternate PPR and Event Log registers.
1935	* @{ */
1936	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
1937	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
1938	/** @} */
1939
1940	/** @name MMIO: Device table segment registers.
1941	* @{ */
1942	DEV_TAB_SEG_BAR_T DevTabSeg[7]; /*< Device Table Segment base address register. /
1943	/** @} */
1944
1945	/** @name MMIO: Device-specific feature registers.
1946	* @{ */
1947	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
1948	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
1949	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
1950	/** @} */
1951
1952	/** @name MMIO: MSI Capability Block registers.
1953	* @{ */
1954	MSI_MISC_INFO_T MsiMiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
1955	/** @} */
1956
1957	/** @name MMIO: Performance Optimization Control registers.
1958	* @{ */
1959	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
1960	/** @} */
1961
1962	/** @name MMIO: x2APIC Control registers.
1963	* @{ */
1964	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
1965	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
1966	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
1967	/** @} */
1968
1969	/** @name MMIO: MARC registers.
1970	* @{ */
1971	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
1972	/** @} */
1973
1974	/** @name MMIO: Reserved register.
1975	* @{ */
1976	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
1977	/** @} */
1978
1979	/** @name MMIO: Command and Event Log pointer registers.
1980	* @{ */
1981	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
1982	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
1983	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
1984	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
1985	/** @} */
1986
1987	/** @name MMIO: Command and Event Status register.
1988	* @{ */
1989	IOMMU_STATUS_T Status; /*< IOMMU status register. /
1990	/** @} */
1991
1992	/** @name MMIO: PPR Log Head and Tail pointer registers.
1993	* @{ */
1994	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
1995	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
1996	/** @} */
1997
1998	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
1999	* @{ */
2000	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
2001	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
2002	/** @} */
2003
2004	/** @name MMIO: PPR Log B Head and Tail pointer registers.
2005	* @{ */
2006	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
2007	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
2008	/** @} */
2009
2010	/** @name MMIO: Event Log B Head and Tail pointer registers.
2011	* @{ */
2012	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
2013	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
2014	/** @} */
2015
2016	/** @name MMIO: PPR Log Overflow protection registers.
2017	* @{ */
2018	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
2019	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
2020	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
2021	/** @} */
2022
2023	/** @todo IOMMU: IOMMU Event counter registers. */
2024
2025	/** @todo IOMMU: Stat counters. */
2026	} IOMMU;
2027	/** Pointer to the IOMMU device state. */
2028	typedef struct IOMMU *PIOMMU;
2029	/** Pointer to the const IOMMU device state. */
2030	typedef const struct IOMMU *PCIOMMU;
2031
2032	/**
2033	* The ring-3 IOMMU device state.
2034	*/
2035	typedef struct IOMMUR3
2036	{
2037	/** Device instance. */
2038	PPDMDEVINSR3 pDevInsR3;
2039	/** The IOMMU helpers. */
2040	PCPDMIOMMUHLPR3 pIommuHlpR3;
2041	/** The command thread handle. */
2042	R3PTRTYPE(PPDMTHREAD) pCmdThread;
2043	} IOMMUR3;
2044	/** Pointer to the ring-3 IOMMU device state. */
2045	typedef IOMMUR3 *PIOMMUR3;
2046
2047	/**
2048	* The ring-0 IOMMU device state.
2049	*/
2050	typedef struct IOMMUR0
2051	{
2052	/** Device instance. */
2053	PPDMDEVINSR0 pDevInsR0;
2054	/** The IOMMU helpers. */
2055	PCPDMIOMMUHLPR0 pIommuHlpR0;
2056	} IOMMUR0;
2057	/** Pointer to the ring-0 IOMMU device state. */
2058	typedef IOMMUR0 *PIOMMUR0;
2059
2060	/**
2061	* The raw-mode IOMMU device state.
2062	*/
2063	typedef struct IOMMURC
2064	{
2065	/** Device instance. */
2066	PPDMDEVINSR0 pDevInsRC;
2067	/** The IOMMU helpers. */
2068	PCPDMIOMMUHLPRC pIommuHlpRC;
2069	} IOMMURC;
2070	/** Pointer to the raw-mode IOMMU device state. */
2071	typedef IOMMURC *PIOMMURC;
2072
2073	/** The IOMMU device state for the current context. */
2074	typedef CTX_SUFF(IOMMU) IOMMUCC;
2075	/** Pointer to the IOMMU device state for the current context. */
2076	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
2077
2078	/**
2079	* IOMMU register access routines.
2080	*/
2081	typedef struct
2082	{
2083	const char *pszName;
2084	VBOXSTRICTRC (pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t pu64Value);
2085	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
2086	bool f64BitReg;
2087	} IOMMUREGACC;
2088
2089
2090	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
2091
2092	/**
2093	* Gets the buffer length length corresponding to a base address.
2094	*
2095	* @param uEncodedLen The length to decode (power-of-2 encoded).
2096	* @param pcEntries Where to store the number of entries. Optional, can be
2097	* NULL.
2098	* @param pcbBuffer Where to store the size of the buffer. Optional, can be
2099	* NULL.
2100	*
2101	* @remarks Both @a pcEntries and @a pcbBuffer cannot both be NULL.
2102	*/
2103	static void iommuAmdGetBaseBufferLength(uint8_t uEncodedLen, uint32_t pcEntries, uint32_t pcbBuffer)
2104	{
2105	uint32_t cEntries;
2106	uint32_t cbBuffer;
2107	if (uEncodedLen > 7)
2108	{
2109	cEntries = 2 << (uEncodedLen - 1);
2110	cbBuffer = *pcEntries << 4;
2111	}
2112	else
2113	cEntries = cbBuffer = 0;
2114
2115	Assert(pcEntries \|\| pcbBuffer);
2116	if (pcEntries)
2117	*pcEntries = cEntries;
2118	if (pcbBuffer)
2119	*pcbBuffer = cbBuffer;
2120	}
2121
2122
2123	DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
2124	{
2125	IOMMU_STATUS_T Status;
2126	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
2127	return Status;
2128	}
2129
2130
2131	/**
2132	* Logs if the buffer length is invalid.
2133	*
2134	* @param uEncodedLen The length to decode.
2135	* @param pszFunc Name of the calling function for logging purposes.
2136	*/
2137	DECLINLINE(void) iommuAmdCheckBufferLength(uint8_t uEncodedLen, const char *pszFunc)
2138	{
2139	#ifdef VBOX_STRICT
2140	uint32_t cEntries;
2141	iommuAmdGetBaseBufferLength(uEncodedLen, &cEntries, NULL /* pcbBuffer */);
2142	if (!cEntries)
2143	Log((IOMMU_LOG_PFX ": %s: Invalid length %#x\n", pszFunc, uEncodedLen));
2144	#else
2145	RT_NOREF(uEncodedLen, pszFunc);
2146	#endif
2147	}
2148
2149
2150	/**
2151	* Writes to a read-only register.
2152	*/
2153	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2154	{
2155	RT_NOREF(pDevIns, pThis, iReg, u64Value);
2156	Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
2157	return VINF_SUCCESS;
2158	}
2159
2160
2161	/**
2162	* Writes the Device Table Base Address Register.
2163	*/
2164	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2165	{
2166	RT_NOREF(pDevIns, iReg);
2167	pThis->DevTabBaseAddr.u64 = u64Value & IOMMU_DEV_TAB_BAR_VALID_MASK;
2168	return VINF_SUCCESS;
2169	}
2170
2171
2172	/**
2173	* Writes the Command Buffer Base Address Register.
2174	*/
2175	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2176	{
2177	RT_NOREF(pDevIns, iReg);
2178	pThis->CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2179	iommuAmdCheckBufferLength(pThis->CmdBufBaseAddr.n.u4CmdLen, __PRETTY_FUNCTION__);
2180
2181	/*
2182	* While this is not explicitly specified like the event log base address register,
2183	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2184	* Inconsistent specs :/
2185	*/
2186	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2187	if (Status.n.u1CmdBufRunning)
2188	{
2189	Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2190	return VINF_SUCCESS;
2191	}
2192
2193	/*
2194	* Writing the command log base address, clears the command buffer head and tail pointers.
2195	* See AMD spec. 2.4 "Commands".
2196	*/
2197	pThis->CmdBufHeadPtr.u64 = 0;
2198	pThis->CmdBufTailPtr.u64 = 0;
2199
2200	return VINF_SUCCESS;
2201	}
2202
2203
2204	/**
2205	* Writes the Event Log Base Address Register.
2206	*/
2207	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2208	{
2209	RT_NOREF(pDevIns, iReg);
2210
2211	/*
2212	* IOMMU behavior is undefined when software writes this register when event logging is running.
2213	* In our emulation, we ignore the write entirely.
2214	* See AMD IOMMU spec. "Event Log Base Address Register".
2215	*/
2216	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2217	if (Status.n.u1EvtLogRunning)
2218	{
2219	Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2220	return VINF_SUCCESS;
2221	}
2222
2223	pThis->EvtLogBaseAddr.u64 = u64Value & IOMMU_EVT_LOG_BAR_VALID_MASK;
2224	iommuAmdCheckBufferLength(pThis->EvtLogBaseAddr.n.u4EvtLen, __PRETTY_FUNCTION__);
2225
2226	/*
2227	* Writing the event log base address, clears the event log head and tail pointers.
2228	* See AMD spec. 2.5 "Event Logging".
2229	*/
2230	pThis->EvtLogHeadPtr.u64 = 0;
2231	pThis->EvtLogTailPtr.u64 = 0;
2232
2233	return VINF_SUCCESS;
2234	}
2235
2236
2237	/**
2238	* Writes to the Excluse Range Base Address Register.
2239	*/
2240	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2241	{
2242	RT_NOREF(pDevIns, iReg);
2243	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2244	return VINF_SUCCESS;
2245	}
2246
2247
2248	/**
2249	* Writes to the Excluse Range Limit Register.
2250	*/
2251	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2252	{
2253	RT_NOREF(pDevIns, iReg);
2254	pThis->ExclRangeLimit.u64 = u64Value & IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2255	return VINF_SUCCESS;
2256	}
2257
2258
2259	/**
2260	* Writes the PPR Log Base Address Register.
2261	*/
2262	static VBOXSTRICTRC iommuAmdPprLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2263	{
2264	RT_NOREF(pDevIns, iReg);
2265	pThis->PprLogBaseAddr.u64 = u64Value & IOMMU_PPR_LOG_BAR_VALID_MASK;
2266	iommuAmdCheckBufferLength(pThis->PprLogBaseAddr.n.u4PprLogLen, __PRETTY_FUNCTION__);
2267	return VINF_SUCCESS;
2268	}
2269
2270
2271	/**
2272	* Writes the Hardware Event Register (Hi).
2273	*/
2274	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2275	{
2276	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2277	RT_NOREF(pDevIns, iReg);
2278	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2279	pThis->HwEvtHi.u64 = u64Value;
2280	return VINF_SUCCESS;
2281	}
2282
2283
2284	/**
2285	* Writes the Hardware Event Register (Lo).
2286	*/
2287	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2288	{
2289	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2290	RT_NOREF(pDevIns, iReg);
2291	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2292	pThis->HwEvtLo = u64Value;
2293	return VINF_SUCCESS;
2294	}
2295
2296
2297	/**
2298	* Writes the Hardware Event Status Register.
2299	*/
2300	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2301	{
2302	RT_NOREF(pDevIns, iReg);
2303
2304	/* Ignore all unrecognized bits. */
2305	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2306
2307	/*
2308	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2309	* If the current status bits or the bits being written are both 0, we've nothing to do.
2310	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2311	*/
2312	uint64_t HwStatus = pThis->HwEvtStatus.u64;
2313	if (!(HwStatus & RT_BIT(0)))
2314	return VINF_SUCCESS;
2315	if (u64Value & HwStatus & RT_BIT_64(0))
2316	HwStatus &= ~RT_BIT_64(0);
2317	if (u64Value & HwStatus & RT_BIT_64(1))
2318	HwStatus &= ~RT_BIT_64(1);
2319	pThis->HwEvtStatus.u64 = HwStatus;
2320	return VINF_SUCCESS;
2321	}
2322
2323
2324	/**
2325	* Writes the MSI Address (Lo) Register (32-bit).
2326	*/
2327	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2328	{
2329	RT_NOREF(pThis, iReg);
2330	Assert(!RT_HI_U32(u64Value));
2331	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2332	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2333	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & IOMMU_MSI_ADDR_VALID_MASK);
2334	return VINF_SUCCESS;
2335	}
2336
2337
2338	/**
2339	* Writes the MSI Address (Hi) Register (32-bit).
2340	*/
2341	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2342	{
2343	RT_NOREF(pThis, iReg);
2344	Assert(!RT_HI_U32(u64Value));
2345	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2346	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2347	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
2348	return VINF_SUCCESS;
2349	}
2350
2351
2352	/**
2353	* Writes the MSI Data Register (32-bit).
2354	*/
2355	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2356	{
2357	RT_NOREF(pThis, iReg);
2358	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2359	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2360	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & IOMMU_MSI_DATA_VALID_MASK);
2361	return VINF_SUCCESS;
2362	}
2363
2364
2365	/**
2366	* Writes the Command Buffer Head Pointer Register (32-bit).
2367	*/
2368	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2369	{
2370	RT_NOREF(pDevIns, iReg);
2371
2372	/*
2373	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
2374	* In our emulation, we ignore the write entirely.
2375	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2376	*/
2377	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2378	if (Status.n.u1CmdBufRunning)
2379	{
2380	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2381	return VINF_SUCCESS;
2382	}
2383
2384	/*
2385	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2386	* In our emulation, we ignore the write entirely.
2387	*/
2388	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2389	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
2390	uint32_t cbBuf;
2391	iommuAmdGetBaseBufferLength(CmdBufBar.n.u4CmdLen, NULL, &cbBuf);
2392	if (offBuf >= cbBuf)
2393	{
2394	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
2395	offBuf, cbBuf));
2396	return VINF_SUCCESS;
2397	}
2398
2399	pThis->CmdBufHeadPtr.u64 = offBuf;
2400	LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
2401	return VINF_SUCCESS;
2402	}
2403
2404
2405	/**
2406	* Writes the Command Buffer Tail Pointer Register (32-bit).
2407	*/
2408	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2409	{
2410	RT_NOREF(pDevIns, iReg);
2411
2412	/*
2413	* IOMMU behavior is undefined when software advances this register equal or beyond its head pointer.
2414	* In our emulation, we ignore the write entirely.
2415	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2416	*/
2417	uint32_t const offBufTail = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2418	NOREF(offBufTail);
2419	NOREF(pThis);
2420	return VINF_SUCCESS;
2421	}
2422
2423
2424	/**
2425	* Writes the Event Log Head Pointer Register (32-bit).
2426	*/
2427	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2428	{
2429	RT_NOREF(pDevIns, iReg);
2430	NOREF(pThis);
2431	NOREF(u64Value);
2432	return VINF_SUCCESS;
2433	}
2434
2435
2436	/**
2437	* Writes the Event Log Tail Pointer Register (32-bit).
2438	*/
2439	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2440	{
2441	RT_NOREF(pDevIns, iReg);
2442	NOREF(pThis);
2443	NOREF(u64Value);
2444	return VINF_SUCCESS;
2445	}
2446
2447
2448	/**
2449	* The IOMMU command thread.
2450	*
2451	* @returns VBox status code.
2452	* @param pDevIns The device instance.
2453	* @param pThread The command thread.
2454	*/
2455	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2456	{
2457	RT_NOREF(pDevIns, pThread);
2458	}
2459
2460
2461	/**
2462	* Unblocks the command thread so it can respond to a state change.
2463	*
2464	* @returns VBox status code.
2465	* @param pDevIns The device instance.
2466	* @param pThread The command thread.
2467	*/
2468	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2469	{
2470	NOREF(pThread);
2471	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2472	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2473	}
2474
2475
2476	#if 0
2477	/**
2478	* Table 0: Registers-access table.
2479	*/
2480	static const IOMMUREGACC g_aTable0Regs[] =
2481	{
2482
2483	};
2484
2485	/**
2486	* Table 1: Registers-access table.
2487	*/
2488	static const IOMMUREGACC g_aTable1Regs[] =
2489	{
2490	};
2491	#endif
2492
2493	/**
2494	* Writes an IOMMU register (32-bit and 64-bit).
2495	*
2496	* @returns Strict VBox status code.
2497	* @param pDevIns The device instance.
2498	* @param off MMIO byte offset to the register.
2499	* @param cb The size of the write access.
2500	* @param uValue The value being written.
2501	*/
2502	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2503	{
2504	Assert(off < IOMMU_MMIO_REGION_SIZE);
2505	Assert(cb == 4 \|\| cb == 8);
2506	Assert(!(off & (cb - 1)));
2507
2508	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2509	Assert(pThis);
2510
2511	switch (off)
2512	{
2513	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
2514	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
2515	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
2516	case IOMMU_MMIO_OFF_CTRL: /** @todo IOMMU: Control register. */
2517	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
2518	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
2519	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2520
2521	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdPprLogBar_w(pDevIns, pThis, off, uValue);
2522	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
2523	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
2524	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
2525
2526	case IOMMU_MMIO_OFF_GALOG_BAR:
2527	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2528
2529	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
2530	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2531
2532	case IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST:
2533	case IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST:
2534	{
2535	uint8_t const idxDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2536	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->DevTabSeg));
2537	return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2538	}
2539
2540	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
2541	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
2542	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2543
2544	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
2545	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2546	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
2547	{
2548	VBOXSTRICTRC rcStrict = iommuAmdIgnore_w(pDevIns, pThis, off, (uint32_t)uValue);
2549	if (cb == 4 \|\| RT_FAILURE(rcStrict))
2550	return rcStrict;
2551	uValue >>= 32;
2552	RT_FALL_THRU();
2553	}
2554	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
2555	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
2556	{
2557	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
2558	if (cb == 4 \|\| RT_FAILURE(rcStrict))
2559	return rcStrict;
2560	uValue >>= 32;
2561	RT_FALL_THRU();
2562	}
2563	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
2564	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2565
2566	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2567
2568	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
2569	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
2570	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2571
2572	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
2573	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
2574	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
2575	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
2576	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
2577	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
2578	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
2579	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
2580	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
2581	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
2582	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
2583	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2584
2585	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2586
2587	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
2588	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
2589	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
2590	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
2591
2592	case IOMMU_MMIO_OFF_STATUS:
2593
2594	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
2595	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
2596
2597	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
2598	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
2599
2600	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
2601	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
2602
2603	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
2604	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
2605
2606	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
2607	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
2608	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
2609
2610	/* Not implemented. */
2611	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
2612	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
2613	{
2614	Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
2615	(off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
2616	return VINF_SUCCESS;
2617	}
2618
2619	/* Unknown. */
2620	default:
2621	{
2622	Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
2623	return VINF_SUCCESS;
2624	}
2625	}
2626	}
2627
2628
2629	/**
2630	* Reads an IOMMU register (64-bit).
2631	*
2632	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2633	* boundary include the lower half of the subsequent register.
2634	*
2635	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
2636	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2637	* guests will only perform 32-bit reads on those 32-bit registers that are aligned
2638	* on 8-byte boundaries.
2639	*
2640	* @returns Strict VBox status code.
2641	* @param pDevIns The device instance.
2642	* @param off Offset in bytes.
2643	* @param puResult Where to store the value being read.
2644	*/
2645	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2646	{
2647	Assert(off < IOMMU_MMIO_REGION_SIZE);
2648	Assert(!(off & 7) \|\| !(off & 3));
2649
2650	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2651	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2652
2653	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2654	Assert(pThis);
2655
2656	/** @todo IOMMU: fine-grained locking? */
2657	uint64_t uReg;
2658	switch (off)
2659	{
2660	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->DevTabBaseAddr.u64; break;
2661	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
2662	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
2663	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
2664	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
2665	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
2666	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
2667
2668	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
2669	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
2670	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
2671	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
2672
2673	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
2674	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
2675
2676	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
2677	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
2678
2679	case IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST:
2680	case IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST:
2681	{
2682	uint8_t const idxDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2683	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->DevTabSeg));
2684	uReg = pThis->DevTabSeg[idxDevTabSeg].u64;
2685	break;
2686	}
2687
2688	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
2689	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
2690	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
2691
2692	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MsiMiscInfo.u64; break;
2693	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MsiMiscInfo.au32[1]; break;
2694	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
2695	{
2696	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2697	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
2698	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
2699	break;
2700	}
2701	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
2702	{
2703	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
2704	break;
2705	}
2706	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
2707	{
2708	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
2709	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
2710	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
2711	break;
2712	}
2713	case IOMMU_MMIO_OFF_MSI_DATA:
2714	{
2715	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
2716	break;
2717	}
2718	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
2719	{
2720	/*
2721	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
2722	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
2723	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
2724	* 0 for this register.
2725	*/
2726	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
2727	break;
2728	}
2729
2730	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
2731
2732	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
2733	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
2734	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
2735
2736	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
2737	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
2738	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
2739	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
2740	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
2741	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
2742	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
2743	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
2744	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
2745	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
2746	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
2747	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
2748
2749	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
2750
2751	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
2752	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
2753	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
2754	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
2755
2756	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
2757
2758	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
2759	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
2760
2761	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
2762	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
2763
2764	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
2765	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
2766
2767	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
2768	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
2769
2770	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
2771	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
2772	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
2773
2774	/* Not implemented. */
2775	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
2776	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
2777	{
2778	Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
2779	uReg = 0;
2780	break;
2781	}
2782
2783	/* Unknown. */
2784	default:
2785	{
2786	Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
2787	uReg = 0;
2788	return VINF_IOM_MMIO_UNUSED_00;
2789	}
2790	}
2791
2792	*puResult = uReg;
2793	return VINF_SUCCESS;
2794	}
2795
2796	/**
2797	* @callback_method_impl{FNIOMMMIONEWWRITE}
2798	*/
2799	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
2800	{
2801	NOREF(pvUser);
2802	Assert(cb == 4 \|\| cb == 8);
2803	Assert(!(off & (cb - 1)));
2804
2805	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
2806	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
2807	}
2808
2809
2810	/**
2811	* @callback_method_impl{FNIOMMMIONEWREAD}
2812	*/
2813	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
2814	{
2815	NOREF(pvUser);
2816	Assert(cb == 4 \|\| cb == 8);
2817	Assert(!(off & (cb - 1)));
2818
2819	uint64_t uResult;
2820	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
2821	if (cb == 8)
2822	(uint64_t )pv = uResult;
2823	else
2824	(uint32_t )pv = (uint32_t)uResult;
2825
2826	return rcStrict;
2827	}
2828
2829
2830	# ifdef IN_RING3
2831	/**
2832	* @callback_method_impl{FNPCICONFIGREAD}
2833	*/
2834	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
2835	unsigned cb, uint32_t *pu32Value)
2836	{
2837	/** @todo IOMMU: PCI config read stat counter. */
2838	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
2839	Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
2840	VBOXSTRICTRC_VAL(rcStrict)));
2841	return rcStrict;
2842	}
2843
2844
2845	/**
2846	* @callback_method_impl{FNPCICONFIGWRITE}
2847	*/
2848	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
2849	unsigned cb, uint32_t u32Value)
2850	{
2851	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2852	Assert(pThis);
2853
2854	/*
2855	* Discard writes to read-only registers that are specific to the IOMMU.
2856	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
2857	* See PCI spec. 6.1. "Configuration Space Organization".
2858	*/
2859	switch (uAddress)
2860	{
2861	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
2862	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
2863	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
2864	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
2865	{
2866	Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
2867	return VINF_SUCCESS;
2868	}
2869	}
2870
2871	IOMMU_LOCK_RET(pDevIns, pThis, VERR_IGNORED);
2872
2873	VBOXSTRICTRC rcStrict;
2874	switch (uAddress)
2875	{
2876	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
2877	{
2878	IOMMU_BAR_T const IommuBar = pThis->IommuBar;
2879	if (!IommuBar.n.u1Enable)
2880	{
2881	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
2882	Assert(pThis->hMmio == NIL_IOMMMIOHANDLE);
2883	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.n.u18BaseAddrLo, pThis->IommuBar.n.u32BaseAddrHi);
2884	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
2885	if (RT_FAILURE(rcStrict))
2886	Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
2887	}
2888	else
2889	{
2890	rcStrict = VINF_SUCCESS;
2891	Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
2892	}
2893	break;
2894	}
2895
2896	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
2897	{
2898	IOMMU_BAR_T const IommuBar = pThis->IommuBar;
2899	if (!IommuBar.n.u1Enable)
2900	pThis->IommuBar.au32[1] = u32Value;
2901	else
2902	{
2903	rcStrict = VINF_SUCCESS;
2904	Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
2905	}
2906	break;
2907	}
2908
2909	case IOMMU_PCI_OFF_MSI_CAP_HDR:
2910	{
2911	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
2912	RT_FALL_THRU();
2913	}
2914
2915	default:
2916	{
2917	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
2918	break;
2919	}
2920	}
2921
2922	IOMMU_UNLOCK(pDevIns, pThis);
2923
2924	Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
2925	return rcStrict;
2926	}
2927
2928
2929	/**
2930	* @callback_method_impl{FNDBGFHANDLERDEV}
2931	*/
2932	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2933	{
2934	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2935	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2936
2937	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2938	Assert(pThis);
2939
2940	LogFlow((IOMMU_LOG_PFX ": %s: pThis=%p pszArgs=%s\n", __PRETTY_FUNCTION__, pThis, pszArgs));
2941	bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
2942
2943	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
2944	/* Device Table Base Address. */
2945	{
2946	DEV_TAB_BAR_T const DevTabBar = pThis->DevTabBaseAddr;
2947	pHlp->pfnPrintf(pHlp, " Device Table BAR = %#RX64\n", DevTabBar.u64);
2948	if (fVerbose)
2949	{
2950	pHlp->pfnPrintf(pHlp, " Size = %u (%u bytes)\n", DevTabBar.n.u9Size,
2951	(DevTabBar.n.u9Size + 1) * _4K);
2952	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40DevTabBase);
2953	}
2954	}
2955	/* Command Buffer Base Address Register. */
2956	{
2957	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
2958	uint32_t cEntries;
2959	uint32_t cbBuffer;
2960	uint8_t const uEncodedLen = CmdBufBar.n.u4CmdLen;
2961	iommuAmdGetBaseBufferLength(uEncodedLen, &cEntries, &cbBuffer);
2962	pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
2963	if (fVerbose)
2964	{
2965	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40CmdBase);
2966	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
2967	cEntries, cbBuffer);
2968	}
2969	}
2970	/* Event Log Base Address Register. */
2971	{
2972	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
2973	uint32_t cEntries;
2974	uint32_t cbBuffer;
2975	uint8_t const uEncodedLen = EvtLogBar.n.u4EvtLen;
2976	iommuAmdGetBaseBufferLength(uEncodedLen, &cEntries, &cbBuffer);
2977	pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
2978	if (fVerbose)
2979	{
2980	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40EvtBase);
2981	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
2982	cEntries, cbBuffer);
2983	}
2984	}
2985	/* IOMMU Control Register. */
2986	{
2987	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
2988	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
2989	if (fVerbose)
2990	{
2991	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
2992	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
2993	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
2994	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
2995	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
2996	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
2997	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
2998	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
2999	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3000	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3001	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3002	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3003	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3004	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3005	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3006	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3007	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3008	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3009	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3010	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3011	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3012	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3013	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3014	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3015	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3016	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3017	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3018	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3019	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3020	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3021	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3022	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3023	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3024	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3025	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3026	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3027	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3028	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3029	}
3030	}
3031	/* Exclusion Base Address Register. */
3032	{
3033	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3034	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3035	if (fVerbose)
3036	{
3037	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3038	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3039	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", ExclRangeBar.n.u40ExclRangeBase);
3040	}
3041	}
3042	/* Exclusion Range Limit Register. */
3043	{
3044	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3045	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3046	if (fVerbose)
3047	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u40ExclLimit);
3048	}
3049	/* Extended Feature Register. */
3050	{
3051	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3052	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3053	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3054	if (fVerbose)
3055	{
3056	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3057	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3058	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3059	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3060	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3061	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3062	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3063	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3064	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3065	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3066	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3067	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3068	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3069	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3070	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3071	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3072	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3073	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3074	pHlp->pfnPrintf(pHlp, " Device table segments supported = %u\n", (ExtFeat.n.u2DevTabSegSup << 1));
3075	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3076	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3077	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3078	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3079	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3080	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3081	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3082	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3083	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3084	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3085	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3086	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3087	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3088	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3089	}
3090	}
3091	/* PPR Log Base Address Register. */
3092	{
3093	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3094	uint32_t cEntries;
3095	uint32_t cbBuffer;
3096	uint8_t const uEncodedLen = PprLogBar.n.u4PprLogLen;
3097	iommuAmdGetBaseBufferLength(uEncodedLen, &cEntries, &cbBuffer);
3098	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3099	if (fVerbose)
3100	{
3101	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40PprLogBase);
3102	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3103	cEntries, cbBuffer);
3104	}
3105	}
3106	/* Hardware Event (Hi) Register. */
3107	{
3108	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
3109	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
3110	if (fVerbose)
3111	{
3112	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
3113	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
3114	}
3115	}
3116	/* Hardware Event (Lo) Register. */
3117	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
3118	/* Hardware Event Status. */
3119	{
3120	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
3121	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
3122	if (fVerbose)
3123	{
3124	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
3125	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
3126	}
3127	}
3128	/* Guest Virtual-APIC Log Base Address Register. */
3129	{
3130	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
3131	uint32_t cEntries;
3132	uint32_t cbBuffer;
3133	uint8_t const uEncodedLen = GALogBar.n.u4GALogLen;
3134	iommuAmdGetBaseBufferLength(uEncodedLen, &cEntries, &cbBuffer);
3135	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
3136	if (fVerbose)
3137	{
3138	pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40GALogBase);
3139	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3140	cEntries, cbBuffer);
3141	}
3142	}
3143	/* Guest Virtual-APIC Log Tail Address Register. */
3144	{
3145	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
3146	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
3147	if (fVerbose)
3148	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
3149	}
3150	/* PPR Log B Base Address Register. */
3151	{
3152	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
3153	uint32_t cEntries;
3154	uint32_t cbBuffer;
3155	uint8_t const uEncodedLen = PprLogBBar.n.u4PprLogLen;
3156	iommuAmdGetBaseBufferLength(uEncodedLen, &cEntries, &cbBuffer);
3157	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
3158	if (fVerbose)
3159	{
3160	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40PprLogBase);
3161	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3162	cEntries, cbBuffer);
3163	}
3164	}
3165	/* Event Log B Base Address Register. */
3166	{
3167	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
3168	uint32_t cEntries;
3169	uint32_t cbBuffer;
3170	uint8_t const uEncodedLen = EvtLogBBar.n.u4EvtLen;
3171	iommuAmdGetBaseBufferLength(uEncodedLen, &cEntries, &cbBuffer);
3172	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
3173	if (fVerbose)
3174	{
3175	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40EvtBase);
3176	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3177	cEntries, cbBuffer);
3178	}
3179	}
3180	/* Device Table Segment Registers. */
3181	for (unsigned i = 0; i < RT_ELEMENTS(pThis->DevTabSeg); i++)
3182	{
3183	DEV_TAB_SEG_BAR_T const DevTabSeg = pThis->DevTabSeg[i];
3184	pHlp->pfnPrintf(pHlp, " Device Table Segment BAR [%u] = %#RX64\n", DevTabSeg.u64);
3185	if (fVerbose)
3186	{
3187	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabSeg.n.u40DevTabBase);
3188	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabSeg.n.u8Size,
3189	(DevTabSeg.n.u8Size + 1) << X86_PAGE_4K_SHIFT);
3190	}
3191	}
3192	/* Device-Specific Feature Extension Register. */
3193	{
3194	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
3195	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
3196	if (fVerbose)
3197	{
3198	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
3199	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
3200	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
3201	}
3202	}
3203	/* Device-Specific Control Extension Register. */
3204	{
3205	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
3206	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
3207	if (fVerbose)
3208	{
3209	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
3210	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
3211	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
3212	}
3213	}
3214	/* Device-Specific Status Extension Register. */
3215	{
3216	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
3217	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
3218	if (fVerbose)
3219	{
3220	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
3221	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
3222	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
3223	}
3224	}
3225	/* MSI Miscellaneous Information Register (Lo and Hi). */
3226	{
3227	MSI_MISC_INFO_T const MsiMiscInfo = pThis->MsiMiscInfo;
3228	pHlp->pfnPrintf(pHlp, " MSI Misc. Info. Register = %#RX64\n", MsiMiscInfo.u64);
3229	if (fVerbose)
3230	{
3231	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumEvtLog);
3232	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MsiMiscInfo.n.u3GstVirtAddrSize);
3233	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MsiMiscInfo.n.u7PhysAddrSize);
3234	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MsiMiscInfo.n.u7VirtAddrSize);
3235	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MsiMiscInfo.n.u1HtAtsResv);
3236	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumPpr);
3237	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumGa);
3238	}
3239	}
3240	/* MSI Capability Header. */
3241	{
3242	MSI_CAP_HDR_T MsiCapHdr;
3243	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3244	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
3245	if (fVerbose)
3246	{
3247	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
3248	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
3249	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
3250	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
3251	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
3252	}
3253	}
3254	/* MSI Address Register (Lo and Hi). */
3255	{
3256	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3257	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3258	MSI_ADDR_T MsiAddr;
3259	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
3260	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
3261	if (fVerbose)
3262	pHlp->pfnPrintf(pHlp, " Address = %#RX64\n", MsiAddr.n.u62MsiAddr);
3263	}
3264	/* MSI Data. */
3265	{
3266	MSI_DATA_T MsiData;
3267	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3268	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
3269	if (fVerbose)
3270	pHlp->pfnPrintf(pHlp, " Data = %#x\n", MsiData.n.u16MsiData);
3271	}
3272	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
3273	{
3274	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
3275	MsiMapCapHdr.u32 = 0;
3276	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
3277	if (fVerbose)
3278	{
3279	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
3280	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
3281	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
3282	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
3283	}
3284	}
3285	/* Performance Optimization Control Register. */
3286	{
3287	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
3288	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
3289	if (fVerbose)
3290	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
3291	}
3292	/* XT (x2APIC) General Interrupt Control Register. */
3293	{
3294	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
3295	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
3296	if (fVerbose)
3297	{
3298	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3299	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3300	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3301	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
3302	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
3303	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3304	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3305	}
3306	}
3307	/* XT (x2APIC) PPR Interrupt Control Register. */
3308	{
3309	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
3310	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
3311	if (fVerbose)
3312	{
3313	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3314	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3315	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3316	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
3317	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
3318	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3319	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3320	}
3321	}
3322	/* XT (X2APIC) GA Log Interrupt Control Register. */
3323	{
3324	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
3325	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
3326	if (fVerbose)
3327	{
3328	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3329	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3330	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3331	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
3332	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
3333	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3334	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3335	}
3336	}
3337	/* MARC Registers. */
3338	{
3339	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
3340	{
3341	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
3342	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
3343	pHlp->pfnPrintf(pHlp, " Base = %#RX64 (addr: %#RX64)\n", MarcAperBar.u64, MarcAperBar.n.u40MarcBaseAddr);
3344
3345	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
3346	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
3347	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr, MarcAperReloc.n.u1ReadOnly,
3348	MarcAperReloc.n.u1RelocEn);
3349
3350	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
3351	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
3352	}
3353	}
3354	/* Reserved Register. */
3355	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
3356	/* Command Buffer Head Pointer Register. */
3357	{
3358	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
3359	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
3360	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.u15Ptr);
3361	}
3362	/* Command Buffer Tail Pointer Register. */
3363	{
3364	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
3365	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
3366	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.u15Ptr);
3367	}
3368	/* Event Log Head Pointer Register. */
3369	{
3370	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
3371	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
3372	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.u15Ptr);
3373	}
3374	/* Event Log Tail Pointer Register. */
3375	{
3376	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
3377	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
3378	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.u15Ptr);
3379	}
3380	/* Status Register. */
3381	{
3382	IOMMU_STATUS_T const Status = pThis->Status;
3383	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
3384	if (fVerbose)
3385	{
3386	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
3387	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
3388	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
3389	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
3390	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
3391	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
3392	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
3393	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
3394	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
3395	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
3396	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
3397	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
3398	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
3399	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
3400	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
3401	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
3402	}
3403	}
3404	/* PPR Log Head Pointer. */
3405	{
3406	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
3407	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
3408	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.u15Ptr);
3409	}
3410	/* PPR Log Tail Pointer. */
3411	{
3412	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
3413	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
3414	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.u15Ptr);
3415	}
3416	/* Guest Virtual-APIC Log Head Pointer. */
3417	{
3418	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
3419	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
3420	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
3421	}
3422	/* Guest Virtual-APIC Log Tail Pointer. */
3423	{
3424	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
3425	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
3426	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
3427	}
3428	/* PPR Log B Head Pointer. */
3429	{
3430	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
3431	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
3432	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.u15Ptr);
3433	}
3434	/* PPR Log B Tail Pointer. */
3435	{
3436	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
3437	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
3438	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.u15Ptr);
3439	}
3440	/* Event Log B Head Pointer. */
3441	{
3442	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
3443	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
3444	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.u15Ptr);
3445	}
3446	/* Event Log B Tail Pointer. */
3447	{
3448	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
3449	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
3450	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.u15Ptr);
3451	}
3452	/* PPR Log Auto Response Register. */
3453	{
3454	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
3455	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
3456	if (fVerbose)
3457	{
3458	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
3459	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
3460	}
3461	}
3462	/* PPR Log Overflow Early Warning Indicator Register. */
3463	{
3464	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
3465	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
3466	if (fVerbose)
3467	{
3468	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
3469	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
3470	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
3471	}
3472	}
3473	/* PPR Log Overflow Early Warning Indicator Register. */
3474	{
3475	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
3476	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
3477	if (fVerbose)
3478	{
3479	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
3480	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
3481	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
3482	}
3483	}
3484	}
3485
3486
3487	/**
3488	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3489	*/
3490	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3491	{
3492	/** @todo IOMMU: Save state. */
3493	RT_NOREF2(pDevIns, pSSM);
3494	return VERR_NOT_IMPLEMENTED;
3495	}
3496
3497
3498	/**
3499	* @callback_method_impl{FNSSMDEVLOADEXEC}
3500	*/
3501	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3502	{
3503	/** @todo IOMMU: Load state. */
3504	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
3505	return VERR_NOT_IMPLEMENTED;
3506	}
3507
3508
3509	/**
3510	* @interface_method_impl{PDMDEVREG,pfnReset}
3511	*/
3512	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
3513	{
3514	/*
3515	* Resets read-write portion of the IOMMU state.
3516	*
3517	* State data not initialized here is expected to be initialized during
3518	* device construction and remain read-only through the lifetime of the VM.
3519	*/
3520	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3521	Assert(pThis);
3522
3523	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3524	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3525
3526	pThis->DevTabBaseAddr.u64 = 0;
3527	pThis->CmdBufBaseAddr.u64 = 0;
3528	pThis->EvtLogBaseAddr.u64 = 0;
3529	pThis->Ctrl.u64 = 0;
3530	pThis->ExclRangeBaseAddr.u64 = 0;
3531	pThis->ExclRangeLimit.u64 = 0;
3532	pThis->ExtFeat.n.u1PrefetchSup = 0;
3533	pThis->ExtFeat.n.u1PprSup = 0;
3534	pThis->ExtFeat.n.u1X2ApicSup = 0;
3535	pThis->ExtFeat.n.u1NoExecuteSup = 0;
3536	pThis->ExtFeat.n.u1GstTranslateSup = 0;
3537	pThis->ExtFeat.n.u1InvAllSup = 0;
3538	pThis->ExtFeat.n.u1GstVirtApicSup = 0;
3539	pThis->ExtFeat.n.u1HwErrorSup = 1;
3540	pThis->ExtFeat.n.u1PerfCounterSup = 0;
3541	pThis->ExtFeat.n.u2HostAddrTranslateSize = 0; /* Requires GstTranslateSup. */
3542	pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
3543	pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
3544	pThis->ExtFeat.n.u2SmiFilterSup = 0;
3545	pThis->ExtFeat.n.u3SmiFilterCount = 0;
3546	pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
3547	pThis->ExtFeat.n.u2DualPprLogSup = 0;
3548	pThis->ExtFeat.n.u2DualEvtLogSup = 0;
3549	pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
3550	pThis->ExtFeat.n.u1UserSupervisorSup = 0;
3551	pThis->ExtFeat.n.u2DevTabSegSup = 0;
3552	pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
3553	pThis->ExtFeat.n.u1PprAutoRespSup = 0;
3554	pThis->ExtFeat.n.u2MarcSup = 0;
3555	pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
3556	pThis->ExtFeat.n.u1PerfOptSup = 0;
3557	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
3558	pThis->ExtFeat.n.u1GstIoSup = 0;
3559	pThis->ExtFeat.n.u1HostAccessSup = 0;
3560	pThis->ExtFeat.n.u1EnhancedPprSup = 0;
3561	pThis->ExtFeat.n.u1AttrForwardSup = 0;
3562	pThis->ExtFeat.n.u1HostDirtySup = 0;
3563	pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
3564	pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
3565	pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
3566	pThis->PprLogBaseAddr.u64 = 0;
3567	pThis->HwEvtHi.u64 = 0;
3568	pThis->HwEvtLo = 0;
3569	pThis->HwEvtStatus.u64 = 0;
3570	pThis->GALogBaseAddr.n.u40GALogBase = 0;
3571	pThis->GALogBaseAddr.n.u4GALogLen = 8;
3572	pThis->GALogTailAddr.u64 = 0;
3573	pThis->PprLogBBaseAddr.n.u40PprLogBase = 0;
3574	pThis->PprLogBBaseAddr.n.u4PprLogLen = 8;
3575	pThis->EvtLogBBaseAddr.n.u40EvtBase = 0;
3576	pThis->EvtLogBBaseAddr.n.u4EvtLen = 8;
3577	memset(&pThis->DevTabSeg[0], 0, sizeof(pThis->DevTabSeg));
3578	pThis->DevSpecificFeat.u64 = 0;
3579	pThis->DevSpecificCtrl.u64 = 0;
3580	pThis->DevSpecificStatus.u64 = 0;
3581	pThis->MsiMiscInfo.u64 = 0;
3582	pThis->PerfOptCtrl.u32 = 0;
3583	pThis->XtGenIntrCtrl.u64 = 0;
3584	pThis->XtPprIntrCtrl.u64 = 0;
3585	pThis->XtGALogIntrCtrl.u64 = 0;
3586	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
3587	pThis->RsvdReg = 0;
3588	pThis->CmdBufHeadPtr.u64 = 0;
3589	pThis->CmdBufTailPtr.u64 = 0;
3590	pThis->EvtLogHeadPtr.u64 = 0;
3591	pThis->EvtLogTailPtr.u64 = 0;
3592	pThis->Status.u64 = 0;
3593	pThis->PprLogHeadPtr.u64 = 0;
3594	pThis->PprLogTailPtr.u64 = 0;
3595	pThis->GALogHeadPtr.u64 = 0;
3596	pThis->GALogTailPtr.u64 = 0;
3597	pThis->PprLogBHeadPtr.u64 = 0;
3598	pThis->PprLogBTailPtr.u64 = 0;
3599	pThis->EvtLogBHeadPtr.u64 = 0;
3600	pThis->EvtLogBTailPtr.u64 = 0;
3601	pThis->PprLogAutoResp.u64 = 0;
3602	pThis->PprLogOverflowEarly.u64 = 0;
3603	pThis->PprLogBOverflowEarly.u64 = 0;
3604
3605	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
3606	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
3607	}
3608
3609
3610	/**
3611	* @interface_method_impl{PDMDEVREG,pfnDestruct}
3612	*/
3613	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
3614	{
3615	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3616	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3617	LogFlowFunc(("\n"));
3618
3619	/* Close the command thread semaphore. */
3620	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
3621	{
3622	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
3623	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
3624	}
3625	return VINF_SUCCESS;
3626	}
3627
3628
3629	/**
3630	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3631	*/
3632	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3633	{
3634	NOREF(iInstance);
3635
3636	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3637	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3638	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3639	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3640	int rc;
3641	LogFlowFunc(("\n"));
3642
3643	pThisCC->pDevInsR3 = pDevIns;
3644
3645	/*
3646	* Validate and read the configuration.
3647	*/
3648	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Device\|Function", "");
3649
3650	uint8_t uPciDevice;
3651	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Device", &uPciDevice, 0);
3652	if (RT_FAILURE(rc))
3653	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Device\""));
3654
3655	uint8_t uPciFunction;
3656	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Function", &uPciFunction, 2);
3657	if (RT_FAILURE(rc))
3658	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Function\""));
3659
3660	/*
3661	* Register the IOMMU with PDM.
3662	*/
3663	PDMIOMMUREGCC IommuReg;
3664	RT_ZERO(IommuReg);
3665	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3666	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3667	rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3668	if (RT_FAILURE(rc))
3669	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3670	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3671	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3672	N_("IOMMU helper version mismatch; got %#x expected %#x"),
3673	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3674	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3675	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3676	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3677	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3678
3679	/*
3680	* Initialize read-only PCI configuration space.
3681	*/
3682	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3683	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3684
3685	/* Header. */
3686	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
3687	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
3688	PDMPciDevSetCommand(pPciDev, 0); /* Command */
3689	PDMPciDevSetStatus(pPciDev, 0x5); /* Status - CapList supported */
3690	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3691	PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
3692	PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
3693	PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
3694	PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
3695	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
3696	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
3697	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
3698	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
3699	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
3700	/* Capability Header. */
3701	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
3702	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
3703	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability block */
3704	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
3705	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
3706	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
3707	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
3708	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
3709	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
3710	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
3711	/* Base Address Low Register. */
3712	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
3713	/* Base Address High Register. */
3714	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
3715	/* IOMMU Range Register. */
3716	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
3717	/* Misc. Information Register 0. */
3718	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0,
3719	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
3720	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
3721	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
3722	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
3723	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
3724	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
3725	/* Misc. Information Register 1. */
3726	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, 0);
3727	/* MSI Capability Header register. */
3728	PDMMSIREG MsiReg;
3729	RT_ZERO(MsiReg);
3730	MsiReg.cMsiVectors = 1;
3731	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
3732	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
3733	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
3734	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3735	AssertRCReturn(rc, rc);
3736
3737	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
3738	#if 0
3739	/* MSI Address Lo. */
3740	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
3741	/* MSI Address Hi. */
3742	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
3743	/* MSI Data. */
3744	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
3745	#endif
3746
3747	#if 0
3748	/** @todo IOMMU: I don't know if we need to support this, enable later if
3749	* required. */
3750	/* MSI Mapping Capability Header register. */
3751	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
3752	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
3753	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
3754	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
3755	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
3756	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
3757	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
3758	#endif
3759
3760	/*
3761	* Register the PCI function with PDM.
3762	*/
3763	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /* fFlags */, uPciDevice, uPciFunction, "amd-iommu");
3764	AssertLogRelRCReturn(rc, rc);
3765
3766	/*
3767	* Intercept PCI config. space accesses.
3768	*/
3769	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
3770	AssertLogRelRCReturn(rc, rc);
3771
3772	/*
3773	* Create the MMIO region.
3774	* Mapping of the region is done when software configures it via PCI config space.
3775	*/
3776	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
3777	NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
3778	"AMD-IOMMU", &pThis->hMmio);
3779	AssertLogRelRCReturn(rc, rc);
3780
3781	/*
3782	* Register saved state.
3783	*/
3784	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
3785	NULL, NULL, NULL,
3786	NULL, iommuAmdR3SaveExec, NULL,
3787	NULL, iommuAmdR3LoadExec, NULL);
3788	AssertLogRelRCReturn(rc, rc);
3789
3790	/*
3791	* Register debugger info item.
3792	*/
3793	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
3794	AssertLogRelRCReturn(rc, rc);
3795
3796	/*
3797	* Create the command thread and its event semaphore.
3798	*/
3799	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
3800	0 /* cbStack */, RTTHREADTYPE_IO, "AMD-IOMMU");
3801	AssertLogRelRCReturn(rc, rc);
3802
3803	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
3804	AssertLogRelRCReturn(rc, rc);
3805
3806	/*
3807	* Initialize parts of the IOMMU state as it would during reset.
3808	* Must be called -after- initializing PCI config. space registers.
3809	*/
3810	iommuAmdR3Reset(pDevIns);
3811
3812	return VINF_SUCCESS;
3813	}
3814
3815	# else /* !IN_RING3 */
3816
3817	/**
3818	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
3819	*/
3820	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
3821	{
3822	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3823	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3824	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3825
3826	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
3827
3828	/* Set up the MMIO RZ handlers. */
3829	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
3830	AssertRCReturn(rc, rc);
3831
3832	/* Set up the IOMMU RZ callbacks. */
3833	PDMIOMMUREGCC IommuReg;
3834	RT_ZERO(IommuReg);
3835	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3836	IommuReg.idxIommu = pThis->idxIommu;
3837	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3838	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
3839	AssertRCReturn(rc, rc);
3840
3841	return VINF_SUCCESS;
3842	}
3843
3844	# endif /* !IN_RING3 */
3845
3846	/**
3847	* The device registration structure.
3848	*/
3849	const PDMDEVREG g_DeviceIommuAmd =
3850	{
3851	/* .u32Version = */ PDM_DEVREG_VERSION,
3852	/* .uReserved0 = */ 0,
3853	/* .szName = */ "iommu-amd",
3854	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
3855	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
3856	/* .cMaxInstances = */ ~0U,
3857	/* .uSharedVersion = */ 42,
3858	/* .cbInstanceShared = */ sizeof(IOMMU),
3859	/* .cbInstanceCC = */ sizeof(IOMMUCC),
3860	/* .cbInstanceRC = */ sizeof(IOMMURC),
3861	/* .cMaxPciDevices = */ 1,
3862	/* .cMaxMsixVectors = */ 0,
3863	/* .pszDescription = */ "IOMMU (AMD)",
3864	#if defined(IN_RING3)
3865	/* .pszRCMod = */ "VBoxDDRC.rc",
3866	/* .pszR0Mod = */ "VBoxDDR0.r0",
3867	/* .pfnConstruct = */ iommuAmdR3Construct,
3868	/* .pfnDestruct = */ iommuAmdR3Destruct,
3869	/* .pfnRelocate = */ NULL,
3870	/* .pfnMemSetup = */ NULL,
3871	/* .pfnPowerOn = */ NULL,
3872	/* .pfnReset = */ iommuAmdR3Reset,
3873	/* .pfnSuspend = */ NULL,
3874	/* .pfnResume = */ NULL,
3875	/* .pfnAttach = */ NULL,
3876	/* .pfnDetach = */ NULL,
3877	/* .pfnQueryInterface = */ NULL,
3878	/* .pfnInitComplete = */ NULL,
3879	/* .pfnPowerOff = */ NULL,
3880	/* .pfnSoftReset = */ NULL,
3881	/* .pfnReserved0 = */ NULL,
3882	/* .pfnReserved1 = */ NULL,
3883	/* .pfnReserved2 = */ NULL,
3884	/* .pfnReserved3 = */ NULL,
3885	/* .pfnReserved4 = */ NULL,
3886	/* .pfnReserved5 = */ NULL,
3887	/* .pfnReserved6 = */ NULL,
3888	/* .pfnReserved7 = */ NULL,
3889	#elif defined(IN_RING0)
3890	/* .pfnEarlyConstruct = */ NULL,
3891	/* .pfnConstruct = */ iommuAmdRZConstruct,
3892	/* .pfnDestruct = */ NULL,
3893	/* .pfnFinalDestruct = */ NULL,
3894	/* .pfnRequest = */ NULL,
3895	/* .pfnReserved0 = */ NULL,
3896	/* .pfnReserved1 = */ NULL,
3897	/* .pfnReserved2 = */ NULL,
3898	/* .pfnReserved3 = */ NULL,
3899	/* .pfnReserved4 = */ NULL,
3900	/* .pfnReserved5 = */ NULL,
3901	/* .pfnReserved6 = */ NULL,
3902	/* .pfnReserved7 = */ NULL,
3903	#elif defined(IN_RC)
3904	/* .pfnConstruct = */ iommuAmdRZConstruct,
3905	/* .pfnReserved0 = */ NULL,
3906	/* .pfnReserved1 = */ NULL,
3907	/* .pfnReserved2 = */ NULL,
3908	/* .pfnReserved3 = */ NULL,
3909	/* .pfnReserved4 = */ NULL,
3910	/* .pfnReserved5 = */ NULL,
3911	/* .pfnReserved6 = */ NULL,
3912	/* .pfnReserved7 = */ NULL,
3913	#else
3914	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
3915	#endif
3916	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
3917	};
3918
3919	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
3920

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 83851

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