DevIommuAmd.cpp@ 84170

Last change on this file since 84170 was 84170, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 Bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 226.1 KB

Line
1	/* $Id: DevIommuAmd.cpp 84170 2020-05-06 16:50:36Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/msi.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/AssertGuest.h>
26
27	#include "VBoxDD.h"
28	#include <iprt/x86.h>
29	#include <iprt/string.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/**
36	* @name PCI configuration register offsets.
37	* In accordance with the AMD spec.
38	* @{
39	*/
40	#define IOMMU_PCI_OFF_CAP_HDR 0x40
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
42	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
43	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
44	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
45	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
46	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
47	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
48	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
49	#define IOMMU_PCI_OFF_MSI_DATA 0x70
50	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
51	/** @} */
52
53	/**
54	* @name MMIO register offsets.
55	* In accordance with the AMD spec.
56	* @{
57	*/
58	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
59	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
60	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
61	#define IOMMU_MMIO_OFF_CTRL 0x18
62	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
63	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
64	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
65
66	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
67	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
68	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
69	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
70
71	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
72	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
73
74	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
75	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
76
77	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
78	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
79
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
81	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
82	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
83	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
84	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
85	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
86	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
87	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
88	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
89
90	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
91	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
92	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
93
94	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
95	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
96	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
97	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
98	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
99	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
100	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
101
102	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
103
104	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
105	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
106	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
107
108	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
109	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
110	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
111	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
112	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
113	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
114	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
115	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
116	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
117	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
118	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
119	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
120
121	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
122
123	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
124	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
125	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
126	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
127
128	#define IOMMU_MMIO_OFF_STATUS 0x2020
129
130	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
131	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
132
133	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
134	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
135
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
137	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
138
139	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
140	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
141
142	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
143	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
144	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
145	/** @} */
146
147	/**
148	* @name MMIO register-access table offsets.
149	* Each table [first..last] (both inclusive) represents the range of registers
150	* covered by a distinct register-access table. This is done due to arbitrary large
151	* gaps in the MMIO register offsets themselves.
152	* @{
153	*/
154	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
155	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
156
157	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
158	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
159	/** @} */
160
161	/**
162	* @name Commands.
163	* In accordance with the AMD spec.
164	* @{
165	*/
166	#define IOMMU_CMD_COMPLETION_WAIT 0x01
167	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
168	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
169	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
170	#define IOMMU_CMD_INV_INTR_TABLE 0x05
171	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
172	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
173	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
174	/** @} */
175
176	/**
177	* @name Event codes.
178	* In accordance with the AMD spec.
179	* @{
180	*/
181	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
182	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
183	#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
184	#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
185	#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
186	#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
187	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
188	#define IOMMU_EVT_INVALID_DEV_REQ 0x08
189	#define IOMMU_EVT_INVALID_PPR_REQ 0x09
190	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
191	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
192	/** @} */
193
194	/**
195	* @name IOMMU Capability Header.
196	* In accordance with the AMD spec.
197	* @{
198	*/
199	/** CapId: Capability ID. */
200	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
201	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
202	/** CapPtr: Capability Pointer. */
203	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
204	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
205	/** CapType: Capability Type. */
206	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
207	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
208	/** CapRev: Capability Revision. */
209	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
210	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
211	/** IoTlbSup: IO TLB Support. */
212	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
213	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
214	/** HtTunnel: HyperTransport Tunnel translation support. */
215	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
216	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
217	/** NpCache: Not Present table entries Cached. */
218	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
219	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
220	/** EFRSup: Extended Feature Register (EFR) Supported. */
221	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
222	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
223	/** CapExt: Miscellaneous Information Register Supported . */
224	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
225	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
226	/** Bits 31:29 reserved. */
227	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
228	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
229	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
230	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
231	/** @} */
232
233	/**
234	* @name IOMMU Base Address Low Register.
235	* In accordance with the AMD spec.
236	* @{
237	*/
238	/** Enable: Enables access to the address specified in the Base Address Register. */
239	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
240	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
241	/** Bits 13:1 reserved. */
242	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
243	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
244	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
245	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
246	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
247	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
248	(ENABLE, RSVD_1_13, ADDR));
249	/** @} */
250
251	/**
252	* @name IOMMU Range Register.
253	* In accordance with the AMD spec.
254	* @{
255	*/
256	/** UnitID: HyperTransport Unit ID. */
257	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
258	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
259	/** Bits 6:5 reserved. */
260	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
261	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
262	/** RngValid: Range valid. */
263	#define IOMMU_BF_RANGE_VALID_SHIFT 7
264	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
265	/** BusNumber: Device range bus number. */
266	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
267	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
268	/** First Device. */
269	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
270	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
271	/** Last Device. */
272	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
273	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
274	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
275	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
276	/** @} */
277
278	/**
279	* @name IOMMU Miscellaneous Information Register 0.
280	* In accordance with the AMD spec.
281	* @{
282	*/
283	/** MsiNum: MSI message number. */
284	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
285	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
286	/** GvaSize: Guest Virtual Address Size. */
287	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
288	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
289	/** PaSize: Physical Address Size. */
290	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
291	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
292	/** VaSize: Virtual Address Size. */
293	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
294	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
295	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
296	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
297	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
298	/** Bits 26:23 reserved. */
299	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
300	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
301	/** MsiNumPPR: Peripheral Page Request MSI message number. */
302	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
303	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
304	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
305	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
306	/** @} */
307
308	/**
309	* @name IOMMU Miscellaneous Information Register 1.
310	* In accordance with the AMD spec.
311	* @{
312	*/
313	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
314	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
315	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
316	/** Bits 31:5 reserved. */
317	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
318	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
319	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
320	(MSI_NUM_GA, RSVD_5_31));
321	/** @} */
322
323	/**
324	* @name MSI Capability Header Register.
325	* In accordance with the AMD spec.
326	* @{
327	*/
328	/** MsiCapId: Capability ID. */
329	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
330	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
331	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
332	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
333	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
334	/** MsiEn: Message Signal Interrupt enable. */
335	#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
336	#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
337	/** MsiMultMessCap: MSI Multi-Message Capability. */
338	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
339	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
340	/** MsiMultMessEn: MSI Mult-Message Enable. */
341	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
342	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
343	/** Msi64BitEn: MSI 64-bit Enabled. */
344	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
345	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
346	/** Bits 31:24 reserved. */
347	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
348	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
349	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
350	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
351	/** @} */
352
353	/**
354	* @name MSI Mapping Capability Header Register.
355	* In accordance with the AMD spec.
356	* @{
357	*/
358	/** MsiMapCapId: Capability ID. */
359	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
360	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
361	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
362	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
363	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
364	/** MsiMapEn: MSI mapping capability enable. */
365	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
366	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
367	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
368	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
369	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
370	/** Bits 18:28 reserved. */
371	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
372	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
373	/** MsiMapCapType: MSI mapping capability. */
374	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
375	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
376	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
377	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
378	/** @} */
379
380	/**
381	* @name IOMMU Status Register Bits.
382	* In accordance with the AMD spec.
383	* @{
384	*/
385	/** EventOverflow: Event log overflow. */
386	#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
387	/** EventLogInt: Event log interrupt. */
388	#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
389	/** ComWaitInt: Completion wait interrupt. */
390	#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
391	/** EventLogRun: Event log is running. */
392	#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
393	/** CmdBufRun: Command buffer is running. */
394	#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
395	/** PprOverflow: Peripheral page request log overflow. */
396	#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
397	/** PprInt: Peripheral page request log interrupt. */
398	#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
399	/** PprLogRun: Peripheral page request log is running. */
400	#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
401	/** GALogRun: Guest virtual-APIC log is running. */
402	#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
403	/** GALOverflow: Guest virtual-APIC log overflow. */
404	#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
405	/** GAInt: Guest virtual-APIC log interrupt. */
406	#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
407	/** PprOvrflwB: PPR Log B overflow. */
408	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
409	/** PprLogActive: PPR Log B is active. */
410	#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
411	/** EvtOvrflwB: Event log B overflow. */
412	#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
413	/** EventLogActive: Event log B active. */
414	#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
415	/** PprOvrflwEarlyB: PPR log B overflow early warning. */
416	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
417	/** PprOverflowEarly: PPR log overflow early warning. */
418	#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
419	/** @} */
420
421	/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
422	* In accordance with the AMD spec.
423	*
424	* These values match the shifted values of the IR and IW field of the DTE and the
425	* PTE, PDE of the I/O page tables.
426	*
427	* @{ */
428	#define IOMMU_IO_PERM_NONE (0)
429	#define IOMMU_IO_PERM_READ RT_BIT_64(0)
430	#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
431	#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ \| IOMMU_IO_PERM_WRITE)
432	#define IOMMU_IO_PERM_SHIFT 61
433	#define IOMMU_IO_PERM_MASK 0x3
434	/** @} */
435
436	/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
437	* In accordance with the AMD spec.
438	* @{ */
439	#define SYSMGTTYPE_DMA_DENY (0)
440	#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
441	#define SYSMGTTYPE_MSG_INT_ALLOW (2)
442	#define SYSMGTTYPE_DMA_ALLOW (3)
443	/** @} */
444
445	/**
446	* @name IOMMU Control Register Bits.
447	* In accordance with the AMD spec.
448	* @{
449	*/
450	/** IommuEn: Enable the IOMMU. */
451	#define IOMMU_CTRL_IOMMU_EN RT_BIT_64(0)
452	/** HtTunEn: HyperTransport tunnel translation enable. */
453	#define IOMMU_CTRL_HT_TUNNEL_EN RT_BIT_64(1)
454	/** EventLogEn: Event log enable. */
455	#define IOMMU_CTRL_EVT_LOG_EN RT_BIT_64(2)
456	/** EventIntEn: Event interrupt enable. */
457	#define IOMMU_CTRL_EVT_INTR_EN RT_BIT_64(3)
458	/** ComWaitIntEn: Completion wait interrupt enable. */
459	#define IOMMU_CTRL_COMPLETION_WAIT_INTR_EN RT_BIT_64(4)
460	/** InvTimeout: Invalidation timeout. */
461	#define IOMMU_CTRL_INV_TIMEOUT RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7)
462	/** @todo IOMMU: the rest or remove it. */
463	/** @} */
464
465	/** @name Miscellaneous IOMMU defines.
466	* @{ */
467	/** Log prefix string. */
468	#define IOMMU_LOG_PFX "AMD_IOMMU"
469	/** The current saved state version. */
470	#define IOMMU_SAVED_STATE_VERSION 1
471	/** AMD's vendor ID. */
472	#define IOMMU_PCI_VENDOR_ID 0x1022
473	/** VirtualBox IOMMU device ID. */
474	#define IOMMU_PCI_DEVICE_ID 0xc0de
475	/** VirtualBox IOMMU device revision ID. */
476	#define IOMMU_PCI_REVISION_ID 0x01
477	/** Size of the MMIO region in bytes. */
478	#define IOMMU_MMIO_REGION_SIZE _16K
479	/** Number of device table segments supported (power of 2). */
480	#define IOMMU_MAX_DEV_TAB_SEGMENTS 3
481	/** Maximum number of host address translation levels supported. */
482	#define IOMMU_MAX_HOST_PT_LEVEL 6
483	/** @} */
484
485	/**
486	* Acquires the IOMMU PDM lock or returns @a a_rcBusy if it's busy.
487	*/
488	#define IOMMU_LOCK_RET(a_pDevIns, a_pThis, a_rcBusy) \
489	do { \
490	NOREF(pThis); \
491	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), (a_rcBusy)); \
492	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
493	{ /* likely */ } \
494	else \
495	return rcLock; \
496	} while (0)
497
498	/**
499	* Releases the IOMMU PDM lock.
500	*/
501	#define IOMMU_UNLOCK(a_pDevIns, a_pThis) \
502	do { \
503	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
504	} while (0)
505
506	/**
507	* Asserts that the critsect is owned by this thread.
508	*/
509	#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
510	do { \
511	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
512	} while (0)
513
514	/**
515	* Gets the device table size given the size field.
516	*/
517	#define IOMMU_GET_DEV_TAB_SIZE(a_uSize) (((a_uSize) + 1) << X86_PAGE_4K_SHIFT)
518
519
520	/*********************************************************************************************************************************
521	* Structures and Typedefs *
522	*********************************************************************************************************************************/
523	/**
524	* The Device ID.
525	* In accordance with VirtualBox's PCI configuration.
526	*/
527	typedef union
528	{
529	struct
530	{
531	uint16_t u3Function : 3; /*< Bits 2:0 - Function. /
532	uint16_t u9Device : 9; /*< Bits 11:3 - Device. /
533	uint16_t u4Bus : 4; /*< Bits 15:12 - Bus. /
534	} n;
535	/** The unsigned integer view. */
536	uint16_t u;
537	} DEVICE_ID_T;
538	AssertCompileSize(DEVICE_ID_T, 2);
539
540	/**
541	* Device Table Entry (DTE).
542	* In accordance with the AMD spec.
543	*/
544	typedef union
545	{
546	struct
547	{
548	RT_GCC_EXTENSION uint64_t u1Valid : 1; /*< Bit 0 - V: Valid. /
549	RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
550	RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
551	RT_GCC_EXTENSION uint64_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
552	RT_GCC_EXTENSION uint64_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
553	RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /*< Bits 51:12 - Page Table Root Pointer. /
554	RT_GCC_EXTENSION uint64_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
555	RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
556	RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
557	RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
558	RT_GCC_EXTENSION uint64_t u2GstMode : 2; /*< Bits 57:56 - GLX: Guest Paging mode levels. /
559	RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). /
560	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
561	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
562	RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
563	RT_GCC_EXTENSION uint64_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
564	RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). /
565	RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /*< Bit 96 - I: IOTLB Enable. /
566	RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
567	RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
568	RT_GCC_EXTENSION uint64_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
569	RT_GCC_EXTENSION uint64_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
570	RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
571	RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
572	RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
573	RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
574	RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). /
575	RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
576	RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
577	RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
578	RT_GCC_EXTENSION uint64_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
579	RT_GCC_EXTENSION uint64_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
580	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
581	RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
582	RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
583	RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
584	RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
585	RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
586	RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 Pass-through. /
587	RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 Pass-through. /
588	RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /*< Bits 223:192 - Reserved. /
589	RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
590	RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
591	RT_GCC_EXTENSION uint64_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
592	RT_GCC_EXTENSION uint64_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
593	} n;
594	/** The 32-bit unsigned integer view. */
595	uint32_t au32[8];
596	/** The 64-bit unsigned integer view. */
597	uint64_t au64[4];
598	} DTE_T;
599	AssertCompileSize(DTE_T, 32);
600	/** Pointer to a device table entry. */
601	typedef DTE_T *PDTE_T;
602	/** Pointer to a const device table entry. */
603	typedef DTE_T const *PCDTE_T;
604
605	/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
606	* Support) features (bits 52:53). */
607	#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
608
609	/** Mask of valid bits for GTSup (Guest Translation Support) features (bits
610	* 55:60, bits 80:95). */
611	#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
612	#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
613
614	/* Mask of valid bits for GIoSup (Guest I/O Protection Support) features (bit 54). */
615	#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
616
617	/* Mask of all valid DTE feature bits. */
618	#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
619	\| IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
620	\| IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
621	#define IOMMU_DTE_QWORD_1_FEAT_MASK (IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
622
623	/* Mask of all valid DTE bits. */
624	#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
625	#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
626	#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xf70fffffffffffff)
627	#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
628
629	/**
630	* I/O Page Table Entry.
631	* In accordance with the AMD spec.
632	*/
633	typedef union
634	{
635	struct
636	{
637	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
638	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
639	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
640	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
641	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
642	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
643	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
644	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
645	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
646	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
647	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
648	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
649	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
650	} n;
651	/** The 64-bit unsigned integer view. */
652	uint64_t u;
653	} IOPTE_T;
654	AssertCompileSize(IOPTE_T, 8);
655
656	/**
657	* I/O Page Directory Entry.
658	* In accordance with the AMD spec.
659	*/
660	typedef union
661	{
662	struct
663	{
664	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
665	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
666	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
667	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
668	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
669	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
670	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
671	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
672	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
673	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
674	} n;
675	/** The 64-bit unsigned integer view. */
676	uint64_t u;
677	} IOPDE_T;
678	AssertCompileSize(IOPDE_T, 8);
679
680	/**
681	* I/O Page Table Generic Entity.
682	* In accordance with the AMD spec.
683	*
684	* This a common subset of a page table entry.
685	* Can be either an IOPTE_T or and IOPDE_T.
686	*/
687	typedef union
688	{
689	struct
690	{
691	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
692	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
693	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
694	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
695	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
696	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
697	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
698	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
699	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
700	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
701	} n;
702	} IOPTENTITY_T;
703	AssertCompileSize(IOPDE_T, 8);
704	/** Pointer to an IOPT_ENTITY_T struct. */
705	typedef IOPTENTITY_T *PIOPTENTITY_T;
706	/** Pointer to a const IOPT_ENTITY_T struct. */
707	typedef IOPTENTITY_T const *PCIOPTENTITY_T;
708
709	/**
710	* Interrupt Remapping Table Entry.
711	* In accordance with the AMD spec.
712	*/
713	typedef union
714	{
715	struct
716	{
717	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
718	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
719	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
720	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
721	uint32_t u1DstMode : 1; /*< Bit 6 - DM: Destination Mode. /
722	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
723	uint32_t u8Dst : 8; /*< Bits 15:8 - Destination. /
724	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
725	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
726	} n;
727	/** The 32-bit unsigned integer view. */
728	uint32_t u;
729	} IRTE_T;
730	AssertCompileSize(IRTE_T, 4);
731
732	/**
733	* Command: Generic Command Buffer Entry.
734	* In accordance with the AMD spec.
735	*/
736	typedef union
737	{
738	struct
739	{
740	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
741	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
742	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
743	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
744	} n;
745	/** The 64-bit unsigned integer view. */
746	uint64_t au64[2];
747	} CMD_GENERIC_T;
748	AssertCompileSize(CMD_GENERIC_T, 16);
749	/** Number of bits to shift the byte offset of a command in the command buffer to
750	* get its index. */
751	#define IOMMU_CMD_GENERIC_SHIFT 4
752
753	/**
754	* Command: COMPLETION_WAIT.
755	* In accordance with the AMD spec.
756	*/
757	typedef union
758	{
759	struct
760	{
761	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
762	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
763	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
764	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
765	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
766	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
767	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
768	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
769	} n;
770	/** The 64-bit unsigned integer view. */
771	uint32_t au64[2];
772	} CMD_COMPLETION_WAIT_T;
773	AssertCompileSize(CMD_COMPLETION_WAIT_T, 16);
774
775	/**
776	* Command: INVALIDATE_DEVTAB_ENTRY.
777	* In accordance with the AMD spec.
778	*/
779	typedef union
780	{
781	struct
782	{
783	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
784	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
785	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
786	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
787	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
788	} n;
789	/** The 64-bit unsigned integer view. */
790	uint64_t au64[2];
791	} CMD_INV_DTE_T;
792	AssertCompileSize(CMD_INV_DTE_T, 16);
793
794	/**
795	* Command: INVALIDATE_IOMMU_PAGES.
796	* In accordance with the AMD spec.
797	*/
798	typedef union
799	{
800	struct
801	{
802	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
803	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
804	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
805	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
806	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
807	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
808	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
809	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
810	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
811	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
812	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
813	} n;
814	/** The 64-bit unsigned integer view. */
815	uint64_t au64[2];
816	} CMD_INV_IOMMU_PAGES_T;
817	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
818
819	/**
820	* Command: INVALIDATE_IOTLB_PAGES.
821	* In accordance with the AMD spec.
822	*/
823	typedef union
824	{
825	struct
826	{
827	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
828	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
829	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
830	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
831	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
832	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
833	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
834	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
835	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
836	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
837	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
838	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
839	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
840	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
841	} n;
842	/** The 64-bit unsigned integer view. */
843	uint64_t au64[2];
844	} CMD_INV_IOTLB_PAGES_T;
845	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
846
847	/**
848	* Command: INVALIDATE_INTR_TABLE.
849	* In accordance with the AMD spec.
850	*/
851	typedef union
852	{
853	struct
854	{
855	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
856	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
857	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
858	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
859	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
860	} u;
861	/** The 64-bit unsigned integer view. */
862	uint64_t au64[2];
863	} CMD_INV_INTR_TABLE_T;
864	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
865
866	/**
867	* Command: COMPLETE_PPR_REQ.
868	* In accordance with the AMD spec.
869	*/
870	typedef union
871	{
872	struct
873	{
874	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
875	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
876	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
877	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
878	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
879	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
880	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
881	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
882	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
883	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
884	} n;
885	/** The 64-bit unsigned integer view. */
886	uint64_t au64[2];
887	} CMD_COMPLETE_PPR_REQ_T;
888	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
889
890	/**
891	* Command: INV_IOMMU_ALL.
892	* In accordance with the AMD spec.
893	*/
894	typedef union
895	{
896	struct
897	{
898	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
899	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
900	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
901	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
902	} n;
903	/** The 64-bit unsigned integer view. */
904	uint64_t au64[2];
905	} CMD_IOMMU_ALL_T;
906	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
907
908	/**
909	* Event Log Entry: Generic.
910	* In accordance with the AMD spec.
911	*/
912	typedef union
913	{
914	struct
915	{
916	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
917	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
918	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
919	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
920	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
921	} n;
922	/** The 32-bit unsigned integer view. */
923	uint32_t au32[4];
924	} EVT_GENERIC_T;
925	AssertCompileSize(EVT_GENERIC_T, 16);
926	/** Number of bits to shift the byte offset of an event entry in the event log
927	* buffer to get its index. */
928	#define IOMMU_EVT_GENERIC_SHIFT 4
929	/** Pointer to a generic event log entry. */
930	typedef EVT_GENERIC_T *PEVT_GENERIC_T;
931	/** Pointer to a const generic event log entry. */
932	typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
933
934	/**
935	* Hardware event types.
936	* In accordance with the AMD spec.
937	*/
938	typedef enum HWEVTTYPE
939	{
940	HWEVTTYPE_RSVD = 0,
941	HWEVTTYPE_MASTER_ABORT,
942	HWEVTTYPE_TARGET_ABORT,
943	HWEVTTYPE_DATA_ERROR
944	} HWEVTTYPE;
945	AssertCompileSize(HWEVTTYPE, 4);
946
947	/**
948	* Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
949	* In accordance with the AMD spec.
950	*/
951	typedef union
952	{
953	struct
954	{
955	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
956	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
957	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
958	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
959	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
960	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
961	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
962	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
963	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
964	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
965	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
966	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
967	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
968	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
969	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
970	} n;
971	/** The 32-bit unsigned integer view. */
972	uint32_t au32[4];
973	} EVT_ILLEGAL_DTE_T;
974	AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
975	/** Pointer to an illegal device table entry event. */
976	typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
977
978	/**
979	* Event Log Entry: IO_PAGE_FAULT_EVENT.
980	* In accordance with the AMD spec.
981	*/
982	typedef union
983	{
984	struct
985	{
986	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
987	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
988	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
989	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
990	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
991	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
992	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
993	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
994	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
995	uint16_t u1Perm : 1; /*< Bit 54 - PE: Permission Indicator. /
996	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
997	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
998	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
999	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1000	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1001	} n;
1002	/** The 32-bit unsigned integer view. */
1003	uint32_t au32[4];
1004	} EVT_IO_PAGE_FAULT_T;
1005	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
1006	/** Pointer to an I/O page fault event. */
1007	typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
1008
1009	/**
1010	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
1011	* In accordance with the AMD spec.
1012	*/
1013	typedef union
1014	{
1015	struct
1016	{
1017	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1018	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1019	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
1020	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). /
1021	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1022	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). /
1023	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
1024	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation (1=translation, 0=transaction). /
1025	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1026	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1027	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1028	uint64_t u64Addr; /*< Bits 127:64 - Address. /
1029	} n;
1030	/** The 32-bit unsigned integer view. */
1031	uint32_t au32[4];
1032	} EVT_DEV_TAB_HW_ERROR_T;
1033	AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1034	/** Pointer to a device table hardware error event. */
1035	typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1036
1037	/**
1038	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1039	* In accordance with the AMD spec.
1040	*/
1041	typedef union
1042	{
1043	struct
1044	{
1045	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1046	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1047	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1048	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1049	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1050	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1051	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1052	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1053	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
1054	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
1055	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1056	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1057	uint32_t u4EvtCode : 4; /*< Bit 63:60 - Event code. /
1058	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1059	* table 58 mentions Addr[31:4]. Looks like a typo in the figure. Use
1060	* table as it makes more sense and matches address size in
1061	* EVT_DEV_TAB_HARDWARE_ERROR. See AMD AMD IOMMU spec (3.05-PUB, Jan
1062	* 2020). */
1063	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1064	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of page table entry (Lo). /
1065	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of page table entry (Hi). /
1066	} n;
1067	/** The 32-bit unsigned integer view. */
1068	uint32_t au32[4];
1069	} EVT_PAGE_TAB_HW_ERR_T;
1070	AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1071
1072	/**
1073	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
1074	* In accordance with the AMD spec.
1075	*/
1076	typedef union
1077	{
1078	struct
1079	{
1080	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1081	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
1082	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1083	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1084	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalid command (Lo). /
1085	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalid command (Hi). /
1086	} n;
1087	/** The 32-bit unsigned integer view. */
1088	uint32_t au32[4];
1089	} EVT_ILLEGAL_CMD_ERR_T;
1090	AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1091
1092	/**
1093	* Event Log Entry: COMMAND_HARDWARE_ERROR.
1094	* In accordance with the AMD spec.
1095	*/
1096	typedef union
1097	{
1098	struct
1099	{
1100	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1101	uint32_t u4Rsvd0 : 4; /*< Bits 35:32 - Reserved. /
1102	uint32_t u28AddrLo : 28; /*< Bits 63:36 - Address: SPA of the attempted access (Lo). /
1103	uint32_t u32AddrHi; /*< Bits 95:64 - Address: SPA of the attempted access (Hi). /
1104	} n;
1105	/** The 32-bit unsigned integer view. */
1106	uint32_t au32[3];
1107	} EVT_CMD_HW_ERROR_T;
1108	AssertCompileSize(EVT_CMD_HW_ERROR_T, 12);
1109
1110	/**
1111	* Event Log Entry: IOTLB_INV_TIMEOUT.
1112	* In accordance with the AMD spec.
1113	*/
1114	typedef union
1115	{
1116	struct
1117	{
1118	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1119	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
1120	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1121	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1122	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1123	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
1124	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
1125	} n;
1126	/** The 32-bit unsigned integer view. */
1127	uint32_t au32[4];
1128	} EVT_IOTLB_INV_TIMEOUT_T;
1129	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1130
1131	/**
1132	* Event Log Entry: INVALID_DEVICE_REQUEST.
1133	* In accordance with the AMD spec.
1134	*/
1135	typedef union
1136	{
1137	struct
1138	{
1139	uint32_t u16DevId : 16; /**< Bits 15:0 - Device ID. /
1140	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1141	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
1142	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1143	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1144	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
1145	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
1146	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
1147	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
1148	uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. /
1149	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
1150	} n;
1151	/** The 32-bit unsigned integer view. */
1152	uint32_t au32[4];
1153	} EVT_INVALID_DEV_REQ_T;
1154	AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1155
1156	/**
1157	* Event Log Entry: EVENT_COUNTER_ZERO.
1158	* In accordance with the AMD spec.
1159	*/
1160	typedef union
1161	{
1162	struct
1163	{
1164	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1165	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1166	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1167	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
1168	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
1169	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
1170	} n;
1171	/** The 32-bit unsigned integer view. */
1172	uint32_t au32[4];
1173	} EVT_EVENT_COUNTER_ZERO_T;
1174	AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1175
1176	/**
1177	* IOMMU Capability Header (PCI).
1178	* In accordance with the AMD spec.
1179	*/
1180	typedef union
1181	{
1182	struct
1183	{
1184	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
1185	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
1186	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
1187	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
1188	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
1189	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
1190	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
1191	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
1192	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
1193	uint32_t u3Rsvd0 : 3; /*< Bits 31:29 - Reserved. /
1194	} n;
1195	/** The 32-bit unsigned integer view. */
1196	uint32_t u32;
1197	} IOMMU_CAP_HDR_T;
1198	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1199
1200	/**
1201	* IOMMU Base Address (Lo and Hi) Register (PCI).
1202	* In accordance with the AMD spec.
1203	*/
1204	typedef union
1205	{
1206	struct
1207	{
1208	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1209	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1210	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1211	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1212	} n;
1213	/** The 32-bit unsigned integer view. */
1214	uint32_t au32[2];
1215	/** The 64-bit unsigned integer view. */
1216	uint64_t u64;
1217	} IOMMU_BAR_T;
1218	AssertCompileSize(IOMMU_BAR_T, 8);
1219	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1220
1221	/**
1222	* IOMMU Range Register (PCI).
1223	* In accordance with the AMD spec.
1224	*/
1225	typedef union
1226	{
1227	struct
1228	{
1229	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1230	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1231	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1232	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1233	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1234	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1235	} n;
1236	/** The 32-bit unsigned integer view. */
1237	uint32_t u32;
1238	} IOMMU_RANGE_T;
1239	AssertCompileSize(IOMMU_RANGE_T, 4);
1240
1241	/**
1242	* Device Table Base Address Register (MMIO).
1243	* In accordance with the AMD spec.
1244	*/
1245	typedef union
1246	{
1247	struct
1248	{
1249	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1250	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1251	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1252	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1253	} n;
1254	/** The 64-bit unsigned integer view. */
1255	uint64_t u64;
1256	} DEV_TAB_BAR_T;
1257	AssertCompileSize(DEV_TAB_BAR_T, 8);
1258	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1259	#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1260
1261	/**
1262	* Command Buffer Base Address Register (MMIO).
1263	* In accordance with the AMD spec.
1264	*/
1265	typedef union
1266	{
1267	struct
1268	{
1269	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1270	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1271	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1272	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1273	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1274	} n;
1275	/** The 64-bit unsigned integer view. */
1276	uint64_t u64;
1277	} CMD_BUF_BAR_T;
1278	AssertCompileSize(CMD_BUF_BAR_T, 8);
1279	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1280
1281	/**
1282	* Event Log Base Address Register (MMIO).
1283	* In accordance with the AMD spec.
1284	*/
1285	typedef union
1286	{
1287	struct
1288	{
1289	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1290	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1291	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1292	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - EventLen: Event log length. /
1293	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1294	} n;
1295	/** The 64-bit unsigned integer view. */
1296	uint64_t u64;
1297	} EVT_LOG_BAR_T;
1298	AssertCompileSize(EVT_LOG_BAR_T, 8);
1299	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1300
1301	/**
1302	* IOMMU Control Register (MMIO).
1303	* In accordance with the AMD spec.
1304	*/
1305	typedef union
1306	{
1307	struct
1308	{
1309	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1310	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1311	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1312	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1313	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1314	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1315	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1316	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1317	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1318	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1319	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1320	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1321	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1322	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1323	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1324	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1325	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1326	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1327	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1328	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1329	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1330	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1331	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1332	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1333	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1334	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1335	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1336	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1337	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1338	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1339	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1340	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1341	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1342	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1343	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1344	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1345	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1346	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1347	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1348	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1349	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1350	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1351	} n;
1352	/** The 64-bit unsigned integer view. */
1353	uint64_t u64;
1354	} IOMMU_CTRL_T;
1355	AssertCompileSize(IOMMU_CTRL_T, 8);
1356	#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1357
1358	/**
1359	* IOMMU Exclusion Base Register (MMIO).
1360	* In accordance with the AMD spec.
1361	*/
1362	typedef union
1363	{
1364	struct
1365	{
1366	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1367	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1368	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1369	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1370	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1371	} n;
1372	/** The 64-bit unsigned integer view. */
1373	uint64_t u64;
1374	} IOMMU_EXCL_RANGE_BAR_T;
1375	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1376	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1377
1378	/**
1379	* IOMMU Exclusion Range Limit Register (MMIO).
1380	* In accordance with the AMD spec.
1381	*/
1382	typedef union
1383	{
1384	struct
1385	{
1386	RT_GCC_EXTENSION uint64_t u52ExclLimit : 52; /*< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). /
1387	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1388	} n;
1389	/** The 64-bit unsigned integer view. */
1390	uint64_t u64;
1391	} IOMMU_EXCL_RANGE_LIMIT_T;
1392	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1393	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1394
1395	/**
1396	* IOMMU Extended Feature Register (MMIO).
1397	* In accordance with the AMD spec.
1398	*/
1399	typedef union
1400	{
1401	struct
1402	{
1403	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1404	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1405	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1406	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1407	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations (for GVAs) Support. /
1408	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1409	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1410	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1411	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1412	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1413	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1414	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1415	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1416	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1417	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1418	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1419	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1420	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1421	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1422	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1423	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1424	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1425	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1426	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1427	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1428	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1429	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1430	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1431	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1432	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1433	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1434	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1435	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1436	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1437	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1438	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1439	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1440	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1441	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1442	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1443	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1444	} n;
1445	/** The 64-bit unsigned integer view. */
1446	uint64_t u64;
1447	} IOMMU_EXT_FEAT_T;
1448	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1449
1450	/**
1451	* Peripheral Page Request Log Base Address Register (MMIO).
1452	* In accordance with the AMD spec.
1453	*/
1454	typedef union
1455	{
1456	struct
1457	{
1458	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1459	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1460	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1461	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1462	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1463	} n;
1464	/** The 64-bit unsigned integer view. */
1465	uint64_t u64;
1466	} PPR_LOG_BAR_T;
1467	AssertCompileSize(PPR_LOG_BAR_T, 8);
1468	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1469
1470	/**
1471	* IOMMU Hardware Event Upper Register (MMIO).
1472	* In accordance with the AMD spec.
1473	*/
1474	typedef union
1475	{
1476	struct
1477	{
1478	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1479	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1480	} n;
1481	/** The 64-bit unsigned integer view. */
1482	uint64_t u64;
1483	} IOMMU_HW_EVT_HI_T;
1484	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1485
1486	/**
1487	* IOMMU Hardware Event Lower Register (MMIO).
1488	* In accordance with the AMD spec.
1489	*/
1490	typedef uint64_t IOMMU_HW_EVT_LO_T;
1491
1492	/**
1493	* IOMMU Hardware Event Status (MMIO).
1494	* In accordance with the AMD spec.
1495	*/
1496	typedef union
1497	{
1498	struct
1499	{
1500	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1501	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1502	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1503	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1504	} n;
1505	/** The 64-bit unsigned integer view. */
1506	uint64_t u64;
1507	} IOMMU_HW_EVT_STATUS_T;
1508	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1509	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1510
1511	/**
1512	* Guest Virtual-APIC Log Base Address Register (MMIO).
1513	* In accordance with the AMD spec.
1514	*/
1515	typedef union
1516	{
1517	struct
1518	{
1519	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1520	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1521	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1522	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1523	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1524	} n;
1525	/** The 64-bit unsigned integer view. */
1526	uint64_t u64;
1527	} GALOG_BAR_T;
1528	AssertCompileSize(GALOG_BAR_T, 8);
1529
1530	/**
1531	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1532	* In accordance with the AMD spec.
1533	*/
1534	typedef union
1535	{
1536	struct
1537	{
1538	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1539	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1540	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1541	} n;
1542	/** The 64-bit unsigned integer view. */
1543	uint64_t u64;
1544	} GALOG_TAIL_ADDR_T;
1545	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1546
1547	/**
1548	* PPR Log B Base Address Register (MMIO).
1549	* In accordance with the AMD spec.
1550	* Currently identical to PPR_LOG_BAR_T.
1551	*/
1552	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1553
1554	/**
1555	* Event Log B Base Address Register (MMIO).
1556	* In accordance with the AMD spec.
1557	* Currently identical to EVT_LOG_BAR_T.
1558	*/
1559	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1560
1561	/**
1562	* Device-specific Feature Extension (DSFX) Register (MMIO).
1563	* In accordance with the AMD spec.
1564	*/
1565	typedef union
1566	{
1567	struct
1568	{
1569	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1570	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1571	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1572	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1573	} n;
1574	/** The 64-bit unsigned integer view. */
1575	uint64_t u64;
1576	} DEV_SPECIFIC_FEAT_T;
1577	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1578
1579	/**
1580	* Device-specific Control Extension (DSCX) Register (MMIO).
1581	* In accordance with the AMD spec.
1582	*/
1583	typedef union
1584	{
1585	struct
1586	{
1587	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1588	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1589	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1590	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1591	} n;
1592	/** The 64-bit unsigned integer view. */
1593	uint64_t u64;
1594	} DEV_SPECIFIC_CTRL_T;
1595	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1596
1597	/**
1598	* Device-specific Status Extension (DSSX) Register (MMIO).
1599	* In accordance with the AMD spec.
1600	*/
1601	typedef union
1602	{
1603	struct
1604	{
1605	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1606	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1607	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1608	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1609	} n;
1610	/** The 64-bit unsigned integer view. */
1611	uint64_t u64;
1612	} DEV_SPECIFIC_STATUS_T;
1613	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1614
1615	/**
1616	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1617	* In accordance with the AMD spec.
1618	*/
1619	typedef union
1620	{
1621	struct
1622	{
1623	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1624	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1625	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1626	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1627	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1628	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1629	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1630	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1631	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1632	} n;
1633	/** The 32-bit unsigned integer view. */
1634	uint32_t au32[2];
1635	/** The 64-bit unsigned integer view. */
1636	uint64_t u64;
1637	} MSI_MISC_INFO_T;
1638	AssertCompileSize(MSI_MISC_INFO_T, 8);
1639	/** MSI Vector Register 0 and 1 (MMIO). */
1640	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1641
1642	/**
1643	* MSI Capability Header Register (PCI + MMIO).
1644	* In accordance with the AMD spec.
1645	*/
1646	typedef union
1647	{
1648	struct
1649	{
1650	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1651	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1652	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1653	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1654	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1655	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1656	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1657	} n;
1658	/** The 32-bit unsigned integer view. */
1659	uint32_t u32;
1660	} MSI_CAP_HDR_T;
1661	AssertCompileSize(MSI_CAP_HDR_T, 4);
1662	#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1663
1664	/**
1665	* MSI Address Register (PCI + MMIO).
1666	* In accordance with the AMD spec.
1667	*/
1668	typedef union
1669	{
1670	struct
1671	{
1672	RT_GCC_EXTENSION uint64_t u2Rsvd : 2; /*< Bits 1:0 - Reserved. /
1673	RT_GCC_EXTENSION uint64_t u62MsiAddr : 62; /*< Bits 31:2 - MsiAddr: MSI Address. /
1674	} n;
1675	/** The 32-bit unsigned integer view. */
1676	uint32_t au32[2];
1677	/** The 64-bit unsigned integer view. */
1678	uint64_t u64;
1679	} MSI_ADDR_T;
1680	AssertCompileSize(MSI_ADDR_T, 8);
1681	#define IOMMU_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc)
1682
1683	/**
1684	* MSI Data Register (PCI + MMIO).
1685	* In accordance with the AMD spec.
1686	*/
1687	typedef union
1688	{
1689	struct
1690	{
1691	uint16_t u16MsiData; /*< Bits 15:0 - MsiData: MSI Data. /
1692	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1693	} n;
1694	/** The 32-bit unsigned integer view. */
1695	uint32_t u32;
1696	} MSI_DATA_T;
1697	AssertCompileSize(MSI_DATA_T, 4);
1698	#define IOMMU_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff)
1699
1700	/**
1701	* MSI Mapping Capability Header Register (PCI + MMIO).
1702	* In accordance with the AMD spec.
1703	*/
1704	typedef union
1705	{
1706	struct
1707	{
1708	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1709	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1710	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1711	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1712	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1713	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1714	} n;
1715	/** The 32-bit unsigned integer view. */
1716	uint32_t u32;
1717	} MSI_MAP_CAP_HDR_T;
1718	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1719
1720	/**
1721	* Performance Optimization Control Register (MMIO).
1722	* In accordance with the AMD spec.
1723	*/
1724	typedef union
1725	{
1726	struct
1727	{
1728	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1729	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1730	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1731	} n;
1732	/** The 32-bit unsigned integer view. */
1733	uint32_t u32;
1734	} IOMMU_PERF_OPT_CTRL_T;
1735	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1736
1737	/**
1738	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1739	* In accordance with the AMD spec.
1740	*/
1741	typedef union
1742	{
1743	struct
1744	{
1745	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1746	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1747	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1748	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1749	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1750	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1751	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1752	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1753	} n;
1754	/** The 64-bit unsigned integer view. */
1755	uint64_t u64;
1756	} IOMMU_XT_GEN_INTR_CTRL_T;
1757	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1758
1759	/**
1760	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1761	* In accordance with the AMD spec.
1762	*/
1763	typedef union
1764	{
1765	struct
1766	{
1767	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1768	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1769	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1770	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1771	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1772	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1773	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1774	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1775	} n;
1776	/** The 64-bit unsigned integer view. */
1777	uint64_t u64;
1778	} IOMMU_XT_INTR_CTRL_T;
1779	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1780
1781	/**
1782	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1783	* In accordance with the AMD spec.
1784	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1785	*/
1786	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1787
1788	/**
1789	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1790	* In accordance with the AMD spec.
1791	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1792	*/
1793	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1794
1795	/**
1796	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1797	* In accordance with the AMD spec.
1798	*/
1799	typedef union
1800	{
1801	struct
1802	{
1803	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1804	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1805	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1806	} n;
1807	/** The 64-bit unsigned integer view. */
1808	uint64_t u64;
1809	} MARC_APER_BAR_T;
1810	AssertCompileSize(MARC_APER_BAR_T, 8);
1811
1812	/**
1813	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1814	* In accordance with the AMD spec.
1815	*/
1816	typedef union
1817	{
1818	struct
1819	{
1820	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1821	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1822	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1823	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1824	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1825	} n;
1826	/** The 64-bit unsigned integer view. */
1827	uint64_t u64;
1828	} MARC_APER_RELOC_T;
1829	AssertCompileSize(MARC_APER_RELOC_T, 8);
1830
1831	/**
1832	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1833	* In accordance with the AMD spec.
1834	*/
1835	typedef union
1836	{
1837	struct
1838	{
1839	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1840	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1841	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1842	} n;
1843	/** The 64-bit unsigned integer view. */
1844	uint64_t u64;
1845	} MARC_APER_LEN_T;
1846
1847	/**
1848	* Memory Access and Routing Control (MARC) Aperture Register.
1849	* This combines other registers to match the MMIO layout for convenient access.
1850	*/
1851	typedef struct
1852	{
1853	MARC_APER_BAR_T Base;
1854	MARC_APER_RELOC_T Reloc;
1855	MARC_APER_LEN_T Length;
1856	} MARC_APER_T;
1857	AssertCompileSize(MARC_APER_T, 24);
1858
1859	/**
1860	* IOMMU Reserved Register (MMIO).
1861	* In accordance with the AMD spec.
1862	* This register is reserved for hardware use (although RW?).
1863	*/
1864	typedef uint64_t IOMMU_RSVD_REG_T;
1865
1866	/**
1867	* Command Buffer Head Pointer Register (MMIO).
1868	* In accordance with the AMD spec.
1869	*/
1870	typedef union
1871	{
1872	struct
1873	{
1874	uint32_t off; /*< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). /
1875	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1876	} n;
1877	/** The 32-bit unsigned integer view. */
1878	uint32_t au32[2];
1879	/** The 64-bit unsigned integer view. */
1880	uint64_t u64;
1881	} CMD_BUF_HEAD_PTR_T;
1882	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1883	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1884
1885	/**
1886	* Command Buffer Tail Pointer Register (MMIO).
1887	* In accordance with the AMD spec.
1888	* Currently identical to CMD_BUF_HEAD_PTR_T.
1889	*/
1890	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1891	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1892
1893	/**
1894	* Event Log Head Pointer Register (MMIO).
1895	* In accordance with the AMD spec.
1896	* Currently identical to CMD_BUF_HEAD_PTR_T.
1897	*/
1898	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1899	#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1900
1901	/**
1902	* Event Log Tail Pointer Register (MMIO).
1903	* In accordance with the AMD spec.
1904	* Currently identical to CMD_BUF_HEAD_PTR_T.
1905	*/
1906	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1907	#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1908
1909
1910	/**
1911	* IOMMU Status Register (MMIO).
1912	* In accordance with the AMD spec.
1913	*/
1914	typedef union
1915	{
1916	struct
1917	{
1918	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
1919	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
1920	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
1921	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
1922	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
1923	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
1924	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
1925	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
1926	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
1927	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
1928	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
1929	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
1930	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
1931	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
1932	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
1933	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
1934	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
1935	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
1936	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1937	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
1938	} n;
1939	/** The 32-bit unsigned integer view. */
1940	uint32_t au32[2];
1941	/** The 64-bit unsigned integer view. */
1942	uint64_t u64;
1943	} IOMMU_STATUS_T;
1944	AssertCompileSize(IOMMU_STATUS_T, 8);
1945	#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
1946	#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
1947
1948	/**
1949	* PPR Log Head Pointer Register (MMIO).
1950	* In accordance with the AMD spec.
1951	* Currently identical to CMD_BUF_HEAD_PTR_T.
1952	*/
1953	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
1954
1955	/**
1956	* PPR Log Tail Pointer Register (MMIO).
1957	* In accordance with the AMD spec.
1958	* Currently identical to CMD_BUF_HEAD_PTR_T.
1959	*/
1960	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
1961
1962	/**
1963	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
1964	* In accordance with the AMD spec.
1965	*/
1966	typedef union
1967	{
1968	struct
1969	{
1970	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
1971	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
1972	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
1973	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1974	} n;
1975	/** The 32-bit unsigned integer view. */
1976	uint32_t au32[2];
1977	/** The 64-bit unsigned integer view. */
1978	uint64_t u64;
1979	} GALOG_HEAD_PTR_T;
1980	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
1981
1982	/**
1983	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
1984	* In accordance with the AMD spec.
1985	* Currently identical to GALOG_HEAD_PTR_T.
1986	*/
1987	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
1988
1989	/**
1990	* PPR Log B Head Pointer Register (MMIO).
1991	* In accordance with the AMD spec.
1992	* Currently identical to CMD_BUF_HEAD_PTR_T.
1993	*/
1994	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
1995
1996	/**
1997	* PPR Log B Tail Pointer Register (MMIO).
1998	* In accordance with the AMD spec.
1999	* Currently identical to CMD_BUF_HEAD_PTR_T.
2000	*/
2001	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
2002
2003	/**
2004	* Event Log B Head Pointer Register (MMIO).
2005	* In accordance with the AMD spec.
2006	* Currently identical to CMD_BUF_HEAD_PTR_T.
2007	*/
2008	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
2009
2010	/**
2011	* Event Log B Tail Pointer Register (MMIO).
2012	* In accordance with the AMD spec.
2013	* Currently identical to CMD_BUF_HEAD_PTR_T.
2014	*/
2015	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
2016
2017	/**
2018	* PPR Log Auto Response Register (MMIO).
2019	* In accordance with the AMD spec.
2020	*/
2021	typedef union
2022	{
2023	struct
2024	{
2025	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
2026	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
2027	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
2028	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
2029	} n;
2030	/** The 32-bit unsigned integer view. */
2031	uint32_t au32[2];
2032	/** The 64-bit unsigned integer view. */
2033	uint64_t u64;
2034	} PPR_LOG_AUTO_RESP_T;
2035	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
2036
2037	/**
2038	* PPR Log Overflow Early Indicator Register (MMIO).
2039	* In accordance with the AMD spec.
2040	*/
2041	typedef union
2042	{
2043	struct
2044	{
2045	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
2046	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
2047	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
2048	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
2049	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2050	} n;
2051	/** The 32-bit unsigned integer view. */
2052	uint32_t au32[2];
2053	/** The 64-bit unsigned integer view. */
2054	uint64_t u64;
2055	} PPR_LOG_OVERFLOW_EARLY_T;
2056	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2057
2058	/**
2059	* PPR Log B Overflow Early Indicator Register (MMIO).
2060	* In accordance with the AMD spec.
2061	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2062	*/
2063	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2064
2065	/**
2066	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2067	* In accordance with the AMD spec.
2068	*/
2069	typedef enum EVT_ILLEGAL_DTE_TYPE_T
2070	{
2071	kIllegalDteType_RsvdNotZero = 0,
2072	kIllegalDteType_RsvdIntTab,
2073	kIllegalDteType_RsvdIoCtl,
2074	kIllegalDteType_RsvdIntCtl
2075	} EVT_ILLEGAL_DTE_TYPE_T;
2076
2077	/**
2078	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2079	* In accordance with the AMD spec.
2080	*/
2081	typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2082	{
2083	/* Memory transaction. */
2084	kIoPageFaultType_DteRsvdPagingMode = 0,
2085	kIoPageFaultType_PteInvalidPageSize,
2086	kIoPageFaultType_PteInvalidLvlEncoding,
2087	kIoPageFaultType_InvalidSkippedPageLvl,
2088	kIoPageFaultType_PteRsvdNotZero,
2089	kIoPageFaultType_PteValidNotSet,
2090	kIoPageFaultType_DteTranslationDisabled,
2091	kIoPageFaultType_PasidInvalidRange,
2092	kIoPageFaultType_ReadProtect,
2093	kIoPageFaultType_WriteProtect,
2094	kIoPageFaultType_ExecuteProtect,
2095	kIoPageFaultType_UserSupervisor,
2096	/* Interrupt remapping */
2097	kIoPageFaultType_IrteAddrInvalid,
2098	kIoPageFaultType_IrteRsvdNotZero,
2099	kIoPageFaultType_IrteRemapEn,
2100	kIoPageFaultType_IrteRsvdIntType,
2101	kIoPageFaultType_IntrReqAborted,
2102	kIoPageFaultType_IntrWithPasid,
2103	kIoPageFaultType_SmiFilterMismatch,
2104	/* Memory transaction or interrupt remapping. */
2105	kIoPageFaultType_DevId_Invalid
2106	} EVT_IO_PAGE_FAULT_TYPE_T;
2107
2108	/**
2109	* DEV_TAB_HARDWARE_ERROR Event Types.
2110	* In accordance with the AMD spec.
2111	*/
2112	typedef enum EVT_DEV_TAB_HW_ERROR_TYPE_T
2113	{
2114	kDevTabHwErrType_MasterAbort = 0,
2115	kDevTabHwErrType_TargetAbort,
2116	kDevTabHwErrType_PoisonedData
2117	} EVT_DEV_TAB_HW_ERROR_TYPE_T;
2118
2119	/**
2120	* PAGE_TAB_HARDWARE_ERROR Even Types.
2121	* In accordance with the AMD spec.
2122	*/
2123	typedef enum EVT_PAGE_TAB_HW_ERR_TYPE_T
2124	{
2125	kPageTabHwErrType_MasterAbort = 0,
2126	kPageTabHwErrType_TargetAbort,
2127	kPageTabHwErrType_PoisonedData,
2128	} EVT_PAGE_TAB_HW_ERR_TYPE_T;
2129
2130	/**
2131	* COMMAND_HARDWARE_ERROR Event Types.
2132	* In accordance with the AMD spec.
2133	*/
2134	typedef enum EVT_CMD_HW_ERROR_TYPE_T
2135	{
2136	kCmdHwErrType_MasterAbort = 0,
2137	kCmdHwErrType_TargetAbort,
2138	kCmdHwErrType_PoisonedData
2139	} EVT_CMD_HW_ERROR_TYPE_T;
2140
2141	/**
2142	* ILLEGAL_COMMAND_ERROR Event Types.
2143	* In accordance with the AMD spec.
2144	*/
2145	typedef enum EVT_ILLEGAL_CMD_ERR_TYPE_T
2146	{
2147	kIllegalCmdErrType_RsvdNotZero = 0,
2148	kIllegalCmdErrType_CmdNotSupported,
2149	kIllegalCmdErrType_IotlbNotSupported
2150	} EVT_ILLEGAL_CMD_ERR_TYPE_T;
2151
2152	/**
2153	* IOTLB_INV_TIMEOUT Event Types.
2154	* In accordance with the AMD spec.
2155	*/
2156	typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2157	{
2158	InvTimeoutType_NoResponse = 0
2159	} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2160
2161	/**
2162	* INVALID_DEVICE_REQUEST Event Types.
2163	* In accordance with the AMD spec.
2164	*/
2165	typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2166	{
2167	/* Access. */
2168	kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2169	kInvalidDevReqType_PretranslatedTransaction,
2170	kInvalidDevReqType_PortIo,
2171	kInvalidDevReqType_SysMgt,
2172	kInvalidDevReqType_IntrRange,
2173	kInvalidDevReqType_RsvdIntrRange,
2174	kInvalidDevReqType_SysMgtAddr,
2175	/* Translation Request. */
2176	kInvalidDevReqType_TrAccessInvalid,
2177	kInvalidDevReqType_TrDisabled,
2178	kInvalidDevReqType_DevIdInvalid,
2179	} EVT_INVALID_DEV_REQ_TYPE_T;
2180
2181	/**
2182	* INVALID_PPR_REQUEST Event Types.
2183	* In accordance with the AMD spec.
2184	*/
2185	typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2186	{
2187	kInvalidPprReqType_PriNotSupported,
2188	kInvalidPprReqType_GstTranslateDisabled
2189	} EVT_INVALID_PPR_REQ_TYPE_T;
2190
2191	/**
2192	* IOMMU operations (transaction) types.
2193	*/
2194	typedef enum IOMMUOP
2195	{
2196	/** Address translation request. */
2197	IOMMUOP_TRANSLATE_REQ = 0,
2198	/** Memory read request. */
2199	IOMMUOP_MEM_READ,
2200	/** Memory write request. */
2201	IOMMUOP_MEM_WRITE,
2202	/** Interrupt request. */
2203	IOMMUOP_INTR_REQ,
2204	/** Command. */
2205	IOMMUOP_CMD
2206	} IOMMUOP;
2207	AssertCompileSize(IOMMUOP, 4);
2208
2209	/**
2210	* IOMMU I/O TLB Entry.
2211	* @note Update iommuAmdInitIotlbe() when changes are made.
2212	*/
2213	typedef struct
2214	{
2215	/** The device ID. */
2216	uint16_t uDevId;
2217	/** The domain ID. */
2218	uint16_t uDomainId;
2219	/** @todo Shouldn't we also store how many bits are the offset into the page for
2220	* pages > 4K? */
2221	/** The I/O virtual address. */
2222	uint64_t uIova;
2223	/** The translated system physical address. */
2224	RTGCPHYS GCPhysSpa;
2225	/** The I/O access permissions (IOMMU_IO_PERM_XXX). */
2226	uint8_t fIoPerm;
2227	/** Alignment padding. */
2228	uint8_t fRsvd0;
2229	/** Reserved for future (eviction hints?). */
2230	uint32_t uPadding0;
2231	} IOTLBE_T;
2232	AssertCompileSizeAlignment(IOTLBE_T, 8);
2233	/** Pointer to an IOMMU I/O TLB entry struct. */
2234	typedef IOTLBE_T *PIOTLBE_T;
2235	/** Pointer to a const IOMMU I/O TLB entry struct. */
2236	typedef IOTLBE_T const *PCIOTLBE_T;
2237
2238	/**
2239	* The shared IOMMU device state.
2240	*/
2241	typedef struct IOMMU
2242	{
2243	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
2244	uint32_t idxIommu;
2245	/** Alignment padding. */
2246	uint32_t uPadding0;
2247	/** The event semaphore the command thread waits on. */
2248	SUPSEMEVENT hEvtCmdThread;
2249	/** The MMIO handle. */
2250	IOMMMIOHANDLE hMmio;
2251
2252	/** @name PCI: Base capability block registers.
2253	* @{ */
2254	IOMMU_BAR_T IommuBar; /*< IOMMU base address register. /
2255	/** @} */
2256
2257	/** @name MMIO: Control and status registers.
2258	* @{ */
2259	DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /*< Device table base address registers. /
2260	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
2261	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
2262	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
2263	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
2264	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
2265	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
2266	/** @} */
2267
2268	/** @name MMIO: PPR Log registers.
2269	* @{ */
2270	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
2271	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
2272	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
2273	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
2274	/** @} */
2275
2276	/** @todo IOMMU: SMI filter. */
2277
2278	/** @name MMIO: Guest Virtual-APIC Log registers.
2279	* @{ */
2280	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
2281	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
2282	/** @} */
2283
2284	/** @name MMIO: Alternate PPR and Event Log registers.
2285	* @{ */
2286	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
2287	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
2288	/** @} */
2289
2290	/** @name MMIO: Device-specific feature registers.
2291	* @{ */
2292	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
2293	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
2294	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
2295	/** @} */
2296
2297	/** @name MMIO: MSI Capability Block registers.
2298	* @{ */
2299	MSI_MISC_INFO_T MsiMiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
2300	/** @} */
2301
2302	/** @name MMIO: Performance Optimization Control registers.
2303	* @{ */
2304	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
2305	/** @} */
2306
2307	/** @name MMIO: x2APIC Control registers.
2308	* @{ */
2309	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
2310	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
2311	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
2312	/** @} */
2313
2314	/** @name MMIO: MARC registers.
2315	* @{ */
2316	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
2317	/** @} */
2318
2319	/** @name MMIO: Reserved register.
2320	* @{ */
2321	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
2322	/** @} */
2323
2324	/** @name MMIO: Command and Event Log pointer registers.
2325	* @{ */
2326	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
2327	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
2328	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
2329	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
2330	/** @} */
2331
2332	/** @name MMIO: Command and Event Status register.
2333	* @{ */
2334	IOMMU_STATUS_T Status; /*< IOMMU status register. /
2335	/** @} */
2336
2337	/** @name MMIO: PPR Log Head and Tail pointer registers.
2338	* @{ */
2339	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
2340	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
2341	/** @} */
2342
2343	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
2344	* @{ */
2345	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
2346	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
2347	/** @} */
2348
2349	/** @name MMIO: PPR Log B Head and Tail pointer registers.
2350	* @{ */
2351	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
2352	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
2353	/** @} */
2354
2355	/** @name MMIO: Event Log B Head and Tail pointer registers.
2356	* @{ */
2357	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
2358	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
2359	/** @} */
2360
2361	/** @name MMIO: PPR Log Overflow protection registers.
2362	* @{ */
2363	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
2364	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
2365	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
2366	/** @} */
2367
2368	/** @todo IOMMU: IOMMU Event counter registers. */
2369
2370	/** @todo IOMMU: Stat counters. */
2371	} IOMMU;
2372	/** Pointer to the IOMMU device state. */
2373	typedef struct IOMMU *PIOMMU;
2374	/** Pointer to the const IOMMU device state. */
2375	typedef const struct IOMMU *PCIOMMU;
2376	AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
2377	AssertCompileMemberAlignment(IOMMU, hMmio, 8);
2378	AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
2379
2380
2381	/**
2382	* The ring-3 IOMMU device state.
2383	*/
2384	typedef struct IOMMUR3
2385	{
2386	/** Device instance. */
2387	PPDMDEVINSR3 pDevInsR3;
2388	/** The IOMMU helpers. */
2389	PCPDMIOMMUHLPR3 pIommuHlpR3;
2390	/** The command thread handle. */
2391	R3PTRTYPE(PPDMTHREAD) pCmdThread;
2392	} IOMMUR3;
2393	/** Pointer to the ring-3 IOMMU device state. */
2394	typedef IOMMUR3 *PIOMMUR3;
2395
2396	/**
2397	* The ring-0 IOMMU device state.
2398	*/
2399	typedef struct IOMMUR0
2400	{
2401	/** Device instance. */
2402	PPDMDEVINSR0 pDevInsR0;
2403	/** The IOMMU helpers. */
2404	PCPDMIOMMUHLPR0 pIommuHlpR0;
2405	} IOMMUR0;
2406	/** Pointer to the ring-0 IOMMU device state. */
2407	typedef IOMMUR0 *PIOMMUR0;
2408
2409	/**
2410	* The raw-mode IOMMU device state.
2411	*/
2412	typedef struct IOMMURC
2413	{
2414	/** Device instance. */
2415	PPDMDEVINSR0 pDevInsRC;
2416	/** The IOMMU helpers. */
2417	PCPDMIOMMUHLPRC pIommuHlpRC;
2418	} IOMMURC;
2419	/** Pointer to the raw-mode IOMMU device state. */
2420	typedef IOMMURC *PIOMMURC;
2421
2422	/** The IOMMU device state for the current context. */
2423	typedef CTX_SUFF(IOMMU) IOMMUCC;
2424	/** Pointer to the IOMMU device state for the current context. */
2425	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
2426
2427	/**
2428	* IOMMU register access routines.
2429	*/
2430	typedef struct
2431	{
2432	const char *pszName;
2433	VBOXSTRICTRC (pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t pu64Value);
2434	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
2435	bool f64BitReg;
2436	} IOMMUREGACC;
2437
2438
2439	/*********************************************************************************************************************************
2440	* Global Variables *
2441	*********************************************************************************************************************************/
2442	/**
2443	* An array of the number of device table segments supported.
2444	* Indexed by u2DevTabSegSup.
2445	*/
2446	static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
2447
2448	/**
2449	* An array of the masks to select the device table segment index from a device ID.
2450	*/
2451	static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
2452
2453	/**
2454	* The maximum size (inclusive) of each device table segment (0 to 7).
2455	* Indexed by the device table segment index.
2456	*/
2457	static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
2458
2459
2460	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
2461	/**
2462	* Gets the maximum number of buffer entries for the given buffer length.
2463	*
2464	* @returns Number of buffer entries.
2465	* @param uEncodedLen The length (power-of-2 encoded).
2466	*/
2467	DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
2468	{
2469	Assert(uEncodedLen > 7);
2470	return 2 << (uEncodedLen - 1);
2471	}
2472
2473
2474	/**
2475	* Gets the total length of the buffer given a base register's encoded length.
2476	*
2477	* @returns The length of the buffer in bytes.
2478	* @param uEncodedLen The length (power-of-2 encoded).
2479	*/
2480	DECLINLINE(uint32_t) iommuAmdGetBufLength(uint8_t uEncodedLen)
2481	{
2482	Assert(uEncodedLen > 7);
2483	return (2 << (uEncodedLen - 1)) << 4;
2484	}
2485
2486
2487	/**
2488	* Gets the number of (unconsumed) entries in the event log.
2489	*
2490	* @returns The number of entries in the event log.
2491	* @param pThis The IOMMU device state.
2492	*/
2493	static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
2494	{
2495	uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2496	uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2497	if (idxTail >= idxHead)
2498	return idxTail - idxHead;
2499
2500	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2501	return cMaxEvts - idxHead + idxTail;
2502	}
2503
2504
2505	/**
2506	* Gets the number of (unconsumed) commands in the command buffer.
2507	*
2508	* @returns The number of commands in the command buffer.
2509	* @param pThis The IOMMU device state.
2510	*/
2511	static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
2512	{
2513	uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2514	uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2515	if (idxTail >= idxHead)
2516	return idxTail - idxHead;
2517
2518	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
2519	return cMaxEvts - idxHead + idxTail;
2520	}
2521
2522
2523	DECLINLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
2524	{
2525	IOMMU_STATUS_T Status;
2526	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
2527	return Status;
2528	}
2529
2530
2531	DECLINLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
2532	{
2533	IOMMU_CTRL_T Ctrl;
2534	Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
2535	return Ctrl;
2536	}
2537
2538
2539	/**
2540	* Returns whether MSI is enabled for the IOMMU.
2541	*
2542	* @returns Whether MSI is enabled.
2543	* @param pDevIns The IOMMU device instance.
2544	*
2545	* @note There should be a PCIDevXxx function for this.
2546	*/
2547	static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
2548	{
2549	MSI_CAP_HDR_T MsiCapHdr;
2550	MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
2551	return MsiCapHdr.n.u1MsiEnable;
2552	}
2553
2554
2555	/**
2556	* Signals a PCI target abort.
2557	*
2558	* @param pDevIns The IOMMU device instance.
2559	*/
2560	static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
2561	{
2562	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2563	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2564	PDMPciDevSetStatus(pPciDev, u16Status);
2565	}
2566
2567
2568	/**
2569	* The IOMMU command thread.
2570	*
2571	* @returns VBox status code.
2572	* @param pDevIns The IOMMU device instance.
2573	* @param pThread The command thread.
2574	*/
2575	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2576	{
2577	RT_NOREF(pDevIns, pThread);
2578	}
2579
2580
2581	/**
2582	* Unblocks the command thread so it can respond to a state change.
2583	*
2584	* @returns VBox status code.
2585	* @param pDevIns The IOMMU device instance.
2586	* @param pThread The command thread.
2587	*/
2588	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2589	{
2590	RT_NOREF(pThread);
2591	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2592	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2593	}
2594
2595
2596	/**
2597	* Writes to a read-only register.
2598	*/
2599	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2600	{
2601	RT_NOREF(pDevIns, pThis, iReg, u64Value);
2602	Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
2603	return VINF_SUCCESS;
2604	}
2605
2606
2607	/**
2608	* Writes the Device Table Base Address Register.
2609	*/
2610	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2611	{
2612	RT_NOREF(pDevIns, iReg);
2613
2614	/* Mask out all unrecognized bits. */
2615	u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2616
2617	/* Update the register. */
2618	pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2619	return VINF_SUCCESS;
2620	}
2621
2622
2623	/**
2624	* Writes the Command Buffer Base Address Register.
2625	*/
2626	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2627	{
2628	RT_NOREF(pDevIns, iReg);
2629
2630	/*
2631	* While this is not explicitly specified like the event log base address register,
2632	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2633	* Inconsistent specs :/
2634	*/
2635	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2636	if (Status.n.u1CmdBufRunning)
2637	{
2638	Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2639	return VINF_SUCCESS;
2640	}
2641
2642	/* Mask out all unrecognized bits. */
2643	CMD_BUF_BAR_T CmdBufBaseAddr;
2644	CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2645
2646	/* Validate the length. */
2647	if (CmdBufBaseAddr.n.u4Len >= 8)
2648	{
2649	/* Update the register. */
2650	pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2651
2652	/*
2653	* Writing the command buffer base address, clears the command buffer head and tail pointers.
2654	* See AMD spec. 2.4 "Commands".
2655	*/
2656	pThis->CmdBufHeadPtr.u64 = 0;
2657	pThis->CmdBufTailPtr.u64 = 0;
2658	}
2659	else
2660	Log((IOMMU_LOG_PFX ": Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2661
2662	return VINF_SUCCESS;
2663	}
2664
2665
2666	/**
2667	* Writes the Event Log Base Address Register.
2668	*/
2669	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2670	{
2671	RT_NOREF(pDevIns, iReg);
2672
2673	/*
2674	* IOMMU behavior is undefined when software writes this register when event logging is running.
2675	* In our emulation, we ignore the write entirely.
2676	* See AMD IOMMU spec. "Event Log Base Address Register".
2677	*/
2678	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2679	if (Status.n.u1EvtLogRunning)
2680	{
2681	Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2682	return VINF_SUCCESS;
2683	}
2684
2685	/* Mask out all unrecognized bits. */
2686	u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2687	EVT_LOG_BAR_T EvtLogBaseAddr;
2688	EvtLogBaseAddr.u64 = u64Value;
2689
2690	/* Validate the length. */
2691	if (EvtLogBaseAddr.n.u4Len >= 8)
2692	{
2693	/* Update the register. */
2694	pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2695
2696	/*
2697	* Writing the event log base address, clears the event log head and tail pointers.
2698	* See AMD spec. 2.5 "Event Logging".
2699	*/
2700	pThis->EvtLogHeadPtr.u64 = 0;
2701	pThis->EvtLogTailPtr.u64 = 0;
2702	}
2703	else
2704	Log((IOMMU_LOG_PFX ": Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2705
2706	return VINF_SUCCESS;
2707	}
2708
2709
2710	/**
2711	* Writes the Control Register.
2712	*/
2713	static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2714	{
2715	RT_NOREF(pDevIns, iReg);
2716
2717	/* Mask out all unrecognized bits. */
2718	u64Value &= IOMMU_CTRL_VALID_MASK;
2719
2720	IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
2721	IOMMU_CTRL_T NewCtrl;
2722	NewCtrl.u64 = u64Value;
2723
2724	/* Enable or disable event logging when the bit transitions. */
2725	if (OldCtrl.n.u1EvtLogEn != NewCtrl.n.u1EvtLogEn)
2726	{
2727	if (NewCtrl.n.u1EvtLogEn)
2728	{
2729	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2730	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2731	}
2732	else
2733	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2734	}
2735
2736	/* Update the register. */
2737	ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2738
2739	/* Enable or disable command buffer processing when the bit transitions. */
2740	if (OldCtrl.n.u1CmdBufEn != NewCtrl.n.u1CmdBufEn)
2741	{
2742	if (NewCtrl.n.u1CmdBufEn)
2743	{
2744	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2745
2746	/* If the command buffer isn't empty, kick the command thread to start processing commands. */
2747	if (pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off)
2748	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2749	}
2750	else
2751	{
2752	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2753	/* Kick the command thread to stop processing commands. */
2754	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2755	}
2756	}
2757	}
2758
2759
2760	/**
2761	* Writes to the Excluse Range Base Address Register.
2762	*/
2763	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2764	{
2765	RT_NOREF(pDevIns, iReg);
2766	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2767	return VINF_SUCCESS;
2768	}
2769
2770
2771	/**
2772	* Writes to the Excluse Range Limit Register.
2773	*/
2774	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2775	{
2776	RT_NOREF(pDevIns, iReg);
2777	u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2778	u64Value \|= UINT64_C(0xfff);
2779	pThis->ExclRangeLimit.u64 = u64Value;
2780	return VINF_SUCCESS;
2781	}
2782
2783
2784	/**
2785	* Writes the Hardware Event Register (Hi).
2786	*/
2787	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2788	{
2789	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2790	RT_NOREF(pDevIns, iReg);
2791	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2792	pThis->HwEvtHi.u64 = u64Value;
2793	return VINF_SUCCESS;
2794	}
2795
2796
2797	/**
2798	* Writes the Hardware Event Register (Lo).
2799	*/
2800	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2801	{
2802	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2803	RT_NOREF(pDevIns, iReg);
2804	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2805	pThis->HwEvtLo = u64Value;
2806	return VINF_SUCCESS;
2807	}
2808
2809
2810	/**
2811	* Writes the Hardware Event Status Register.
2812	*/
2813	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2814	{
2815	RT_NOREF(pDevIns, iReg);
2816
2817	/* Mask out all unrecognized bits. */
2818	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2819
2820	/*
2821	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2822	* If the current status bits or the bits being written are both 0, we've nothing to do.
2823	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2824	*/
2825	uint64_t HwStatus = pThis->HwEvtStatus.u64;
2826	if (!(HwStatus & RT_BIT(0)))
2827	return VINF_SUCCESS;
2828	if (u64Value & HwStatus & RT_BIT_64(0))
2829	HwStatus &= ~RT_BIT_64(0);
2830	if (u64Value & HwStatus & RT_BIT_64(1))
2831	HwStatus &= ~RT_BIT_64(1);
2832
2833	/* Update the register. */
2834	pThis->HwEvtStatus.u64 = HwStatus;
2835	return VINF_SUCCESS;
2836	}
2837
2838
2839	/**
2840	* Writes the Device Table Segment Base Address Register.
2841	*/
2842	static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2843	{
2844	RT_NOREF(pDevIns);
2845
2846	/* Figure out which segment is being written. */
2847	uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2848	uint8_t const idxSegment = offSegment + 1;
2849	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2850
2851	/* Mask out all unrecognized bits. */
2852	u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2853	DEV_TAB_BAR_T DevTabSegBar;
2854	DevTabSegBar.u64 = u64Value;
2855
2856	/* Validate the size. */
2857	uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2858	uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2859	if (uSegSize <= uMaxSegSize)
2860	{
2861	/* Update the register. */
2862	pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2863	}
2864	else
2865	Log((IOMMU_LOG_PFX ": Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2866
2867	return VINF_SUCCESS;
2868	}
2869
2870
2871	/**
2872	* Writes the MSI Capability Header Register.
2873	*/
2874	static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2875	{
2876	RT_NOREF(pThis, iReg);
2877	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2878	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2879	MSI_CAP_HDR_T MsiCapHdr;
2880	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2881	MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2882	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2883	return VINF_SUCCESS;
2884	}
2885
2886
2887	/**
2888	* Writes the MSI Address (Lo) Register (32-bit).
2889	*/
2890	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2891	{
2892	RT_NOREF(pThis, iReg);
2893	Assert(!RT_HI_U32(u64Value));
2894	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2895	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2896	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & IOMMU_MSI_ADDR_VALID_MASK);
2897	return VINF_SUCCESS;
2898	}
2899
2900
2901	/**
2902	* Writes the MSI Address (Hi) Register (32-bit).
2903	*/
2904	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2905	{
2906	RT_NOREF(pThis, iReg);
2907	Assert(!RT_HI_U32(u64Value));
2908	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2909	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2910	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
2911	return VINF_SUCCESS;
2912	}
2913
2914
2915	/**
2916	* Writes the MSI Data Register (32-bit).
2917	*/
2918	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2919	{
2920	RT_NOREF(pThis, iReg);
2921	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2922	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2923	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & IOMMU_MSI_DATA_VALID_MASK);
2924	return VINF_SUCCESS;
2925	}
2926
2927
2928	/**
2929	* Writes the Command Buffer Head Pointer Register (32-bit).
2930	*/
2931	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2932	{
2933	RT_NOREF(pDevIns, iReg);
2934
2935	/*
2936	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
2937	* In our emulation, we ignore the write entirely.
2938	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2939	*/
2940	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2941	if (Status.n.u1CmdBufRunning)
2942	{
2943	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2944	return VINF_SUCCESS;
2945	}
2946
2947	/*
2948	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2949	* In our emulation, we ignore the write entirely.
2950	*/
2951	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2952	uint32_t const cbBuf = iommuAmdGetBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2953	Assert(cbBuf <= _512K);
2954	if (offBuf >= cbBuf)
2955	{
2956	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
2957	offBuf, cbBuf));
2958	return VINF_SUCCESS;
2959	}
2960
2961	/* Update the register. */
2962	pThis->CmdBufHeadPtr.au32[0] = offBuf;
2963
2964	LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
2965	return VINF_SUCCESS;
2966	}
2967
2968
2969	/**
2970	* Writes the Command Buffer Tail Pointer Register (32-bit).
2971	*/
2972	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2973	{
2974	RT_NOREF(pDevIns, iReg);
2975
2976	/*
2977	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2978	* In our emulation, we ignore the write entirely.
2979	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2980	*/
2981	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2982	uint32_t const cbBuf = iommuAmdGetBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2983	Assert(cbBuf <= _512K);
2984	if (offBuf >= cbBuf)
2985	{
2986	Log((IOMMU_LOG_PFX ": Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
2987	offBuf, cbBuf));
2988	return VINF_SUCCESS;
2989	}
2990
2991	/*
2992	* IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2993	* head pointer after adding one or more commands to the buffer.
2994	*
2995	* However, we cannot enforce this strictly because it's legal for software to shrink the
2996	* command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2997	* at 0). Software might even make the queue empty by making head and tail equal which is
2998	* allowed. I don't think we can or should try too hard to prevent software shooting itself
2999	* in the foot here. As long as we make sure the offset value is within the circular buffer
3000	* bounds (which we do by masking bits above) it should be sufficient.
3001	*/
3002	pThis->CmdBufTailPtr.au32[0] = offBuf;
3003
3004	LogFlow((IOMMU_LOG_PFX ": Set CmdBufTailPtr to %#RX32\n", offBuf));
3005	return VINF_SUCCESS;
3006	}
3007
3008
3009	/**
3010	* Writes the Event Log Head Pointer Register (32-bit).
3011	*/
3012	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3013	{
3014	RT_NOREF(pDevIns, iReg);
3015
3016	/*
3017	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3018	* In our emulation, we ignore the write entirely.
3019	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3020	*/
3021	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
3022	uint32_t const cbBuf = iommuAmdGetBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3023	Assert(cbBuf <= _512K);
3024	if (offBuf >= cbBuf)
3025	{
3026	Log((IOMMU_LOG_PFX ": Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3027	offBuf, cbBuf));
3028	return VINF_SUCCESS;
3029	}
3030
3031	/* Update the register. */
3032	pThis->EvtLogHeadPtr.au32[0] = offBuf;
3033
3034	LogFlow((IOMMU_LOG_PFX ": Set EvtLogHeadPtr to %#RX32\n", offBuf));
3035	return VINF_SUCCESS;
3036	}
3037
3038
3039	/**
3040	* Writes the Event Log Tail Pointer Register (32-bit).
3041	*/
3042	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3043	{
3044	RT_NOREF(pDevIns, iReg);
3045	NOREF(pThis);
3046
3047	/*
3048	* IOMMU behavior is undefined when software writes this register when the event log is running.
3049	* In our emulation, we ignore the write entirely.
3050	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3051	*/
3052	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3053	if (Status.n.u1EvtLogRunning)
3054	{
3055	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
3056	return VINF_SUCCESS;
3057	}
3058
3059	/*
3060	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3061	* In our emulation, we ignore the write entirely.
3062	*/
3063	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
3064	uint32_t const cbBuf = iommuAmdGetBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3065	Assert(cbBuf <= _512K);
3066	if (offBuf >= cbBuf)
3067	{
3068	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3069	offBuf, cbBuf));
3070	return VINF_SUCCESS;
3071	}
3072
3073	/* Update the register. */
3074	pThis->EvtLogTailPtr.au32[0] = offBuf;
3075
3076	LogFlow((IOMMU_LOG_PFX ": Set EvtLogTailPtr to %#RX32\n", offBuf));
3077	return VINF_SUCCESS;
3078	}
3079
3080
3081	/**
3082	* Writes the Status Register (64-bit).
3083	*/
3084	static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3085	{
3086	RT_NOREF(pDevIns, iReg);
3087
3088	/* Mask out all unrecognized bits. */
3089	u64Value &= IOMMU_STATUS_VALID_MASK;
3090
3091	/*
3092	* Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
3093	* Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
3094	*/
3095	IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
3096	uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
3097	uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
3098	uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
3099
3100	uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) \| fOldRoBits;
3101
3102	/* Update the register. */
3103	ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
3104	return VINF_SUCCESS;
3105	}
3106
3107
3108	#if 0
3109	/**
3110	* Table 0: Registers-access table.
3111	*/
3112	static const IOMMUREGACC g_aTable0Regs[] =
3113	{
3114
3115	};
3116
3117	/**
3118	* Table 1: Registers-access table.
3119	*/
3120	static const IOMMUREGACC g_aTable1Regs[] =
3121	{
3122	};
3123	#endif
3124
3125
3126	/**
3127	* Writes an IOMMU register (32-bit and 64-bit).
3128	*
3129	* @returns Strict VBox status code.
3130	* @param pDevIns The IOMMU device instance.
3131	* @param off MMIO byte offset to the register.
3132	* @param cb The size of the write access.
3133	* @param uValue The value being written.
3134	*/
3135	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
3136	{
3137	Assert(off < IOMMU_MMIO_REGION_SIZE);
3138	Assert(cb == 4 \|\| cb == 8);
3139	Assert(!(off & (cb - 1)));
3140
3141	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3142	switch (off)
3143	{
3144	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
3145	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
3146	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
3147	case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
3148	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
3149	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
3150	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3151
3152	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3153	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
3154	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
3155	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
3156
3157	case IOMMU_MMIO_OFF_GALOG_BAR:
3158	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3159
3160	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
3161	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3162
3163	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3164	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3165	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3166	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3167	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3168	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3169	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
3170
3171	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
3172	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
3173	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3174
3175	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
3176	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3177	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3178	{
3179	VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
3180	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3181	return rcStrict;
3182	uValue >>= 32;
3183	RT_FALL_THRU();
3184	}
3185	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
3186	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3187	{
3188	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
3189	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3190	return rcStrict;
3191	uValue >>= 32;
3192	RT_FALL_THRU();
3193	}
3194	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
3195	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3196
3197	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3198
3199	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
3200	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
3201	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3202
3203	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
3204	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
3205	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
3206	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
3207	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
3208	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
3209	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
3210	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
3211	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
3212	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
3213	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
3214	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3215
3216	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3217
3218	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
3219	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
3220	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
3221	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
3222
3223	case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
3224
3225	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
3226	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
3227
3228	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
3229	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
3230
3231	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
3232	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
3233
3234	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
3235	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3236
3237	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
3238	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
3239	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
3240
3241	/* Not implemented. */
3242	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3243	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3244	{
3245	Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
3246	(off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3247	return VINF_SUCCESS;
3248	}
3249
3250	/* Unknown. */
3251	default:
3252	{
3253	Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
3254	return VINF_SUCCESS;
3255	}
3256	}
3257	}
3258
3259
3260	/**
3261	* Reads an IOMMU register (64-bit) given its MMIO offset.
3262	*
3263	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
3264	* boundary include the lower half of the subsequent register.
3265	*
3266	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
3267	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
3268	* software will only perform 32-bit reads on those 32-bit registers that are
3269	* aligned on 8-byte boundaries.
3270	*
3271	* @returns Strict VBox status code.
3272	* @param pDevIns The IOMMU device instance.
3273	* @param off The MMIO offset of the register in bytes.
3274	* @param puResult Where to store the value being read.
3275	*/
3276	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
3277	{
3278	Assert(off < IOMMU_MMIO_REGION_SIZE);
3279	Assert(!(off & 7) \|\| !(off & 3));
3280
3281	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3282	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3283	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3284
3285	/** @todo IOMMU: fine-grained locking? */
3286	uint64_t uReg;
3287	switch (off)
3288	{
3289	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
3290	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
3291	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
3292	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
3293	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
3294	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
3295	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
3296
3297	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
3298	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
3299	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
3300	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
3301
3302	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
3303	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
3304
3305	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
3306	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
3307
3308	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3309	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3310	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3311	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3312	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3313	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3314	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
3315	{
3316	uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
3317	uint8_t const idxDevTabSeg = offDevTabSeg + 1;
3318	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3319	uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
3320	break;
3321	}
3322
3323	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
3324	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
3325	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
3326
3327	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MsiMiscInfo.u64; break;
3328	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MsiMiscInfo.au32[1]; break;
3329	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3330	{
3331	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3332	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3333	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
3334	break;
3335	}
3336	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
3337	{
3338	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3339	break;
3340	}
3341	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3342	{
3343	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3344	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3345	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
3346	break;
3347	}
3348	case IOMMU_MMIO_OFF_MSI_DATA:
3349	{
3350	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3351	break;
3352	}
3353	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
3354	{
3355	/*
3356	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
3357	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
3358	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
3359	* 0 for this register.
3360	*/
3361	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
3362	break;
3363	}
3364
3365	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
3366
3367	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
3368	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
3369	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
3370
3371	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
3372	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
3373	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
3374	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
3375	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
3376	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
3377	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
3378	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
3379	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
3380	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
3381	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
3382	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
3383
3384	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
3385
3386	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
3387	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
3388	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
3389	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
3390
3391	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
3392
3393	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
3394	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
3395
3396	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
3397	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
3398
3399	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
3400	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
3401
3402	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
3403	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
3404
3405	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
3406	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
3407	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
3408
3409	/* Not implemented. */
3410	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3411	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3412	{
3413	Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3414	uReg = 0;
3415	break;
3416	}
3417
3418	/* Unknown. */
3419	default:
3420	{
3421	Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
3422	uReg = 0;
3423	return VINF_IOM_MMIO_UNUSED_00;
3424	}
3425	}
3426
3427	*puResult = uReg;
3428	return VINF_SUCCESS;
3429	}
3430
3431
3432	/**
3433	* Raises the MSI interrupt for the IOMMU device.
3434	*
3435	* @param pDevIns The IOMMU device instance.
3436	*/
3437	static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
3438	{
3439	if (iommuAmdIsMsiEnabled(pDevIns))
3440	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
3441	}
3442
3443
3444	/**
3445	* Clears the MSI interrupt for the IOMMU device.
3446	*
3447	* @param pDevIns The IOMMU device instance.
3448	*/
3449	static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
3450	{
3451	if (iommuAmdIsMsiEnabled(pDevIns))
3452	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3453	}
3454
3455
3456	/**
3457	* Writes an entry to the event log in memory.
3458	*
3459	* @returns VBox status code.
3460	* @param pDevIns The IOMMU device instance.
3461	* @param pEvent The event to log.
3462	*
3463	* @thread Any.
3464	*/
3465	static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3466	{
3467	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3468	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3469
3470	/* Check if event logging is active and the log has not overflowed. */
3471	if ( Status.n.u1EvtLogRunning
3472	&& !Status.n.u1EvtOverflow)
3473	{
3474	uint32_t const cbEvt = sizeof(*pEvent);
3475
3476	/* Get the offset we need to write the event to in memory (circular buffer offset). */
3477	uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3478	Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3479
3480	/* Ensure we have space in the event log. */
3481	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3482	uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3483	if (cEvts + 1 < cMaxEvts)
3484	{
3485	/* Write the event log entry to memory. */
3486	RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3487	RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3488	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3489	if (RT_FAILURE(rc))
3490	Log((IOMMU_LOG_PFX ": Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3491
3492	/* Increment the event log tail pointer. */
3493	uint32_t const cbEvtLog = iommuAmdGetBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3494	pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3495
3496	/* Indicate that an event log entry was written. */
3497	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3498
3499	/* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3500	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3501	if (Ctrl.n.u1EvtIntrEn)
3502	iommuAmdRaiseMsiInterrupt(pDevIns);
3503	}
3504	else
3505	{
3506	/* Indicate that the event log has overflowed. */
3507	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3508
3509	/* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3510	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3511	if (Ctrl.n.u1EvtIntrEn)
3512	iommuAmdRaiseMsiInterrupt(pDevIns);
3513	}
3514	}
3515	}
3516
3517
3518	/**
3519	* Sets an event in the hardware error registers.
3520	*
3521	* @param pDevIns The IOMMU device instance.
3522	* @param pEvent The event.
3523	*
3524	* @thread Any.
3525	*/
3526	static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3527	{
3528	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3529	if (pThis->ExtFeat.n.u1HwErrorSup)
3530	{
3531	if (pThis->HwEvtStatus.n.u1Valid)
3532	pThis->HwEvtStatus.n.u1Overflow = 1;
3533	pThis->HwEvtStatus.n.u1Valid = 1;
3534	pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3535	pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3536	Assert(pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR);
3537	}
3538	}
3539
3540
3541	/**
3542	* Initializes a DEV_TAB_HARDWARE_ERROR event.
3543	*
3544	* @param uDevId The device ID.
3545	* @param GCPhysDte The system physical address of the failed device table
3546	* access.
3547	* @param enmOp The IOMMU operation being performed.
3548	* @param pEvent Where to store the initialized event.
3549	*
3550	* @thread Any.
3551	*/
3552	static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp, PEVT_GENERIC_T pEvent)
3553	{
3554	memset(pEvent, 0, sizeof(*pEvent));
3555	AssertCompile(sizeof(EVT_DEV_TAB_HW_ERROR_T) == sizeof(EVT_GENERIC_T));
3556	PEVT_DEV_TAB_HW_ERROR_T pDevTabHwErr = (PEVT_DEV_TAB_HW_ERROR_T)pEvent;
3557	pDevTabHwErr->n.u16DevId = uDevId;
3558	pDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3559	/** @todo r=ramshankar: Any other transaction type that can set read/write bit? */
3560	pDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3561	pDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3562	pDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3563	pDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3564	pDevTabHwErr->n.u64Addr = GCPhysDte;
3565	}
3566
3567
3568	/**
3569	* Raises a DEV_TAB_HARDWARE_ERROR event.
3570	*
3571	* @param pDevIns The IOMMU device instance.
3572	* @param uDevId The device ID.
3573	* @param GCPhysDte The system physical address of the failed device table
3574	* access.
3575	* @param enmOp The IOMMU operation being performed.
3576	* @param enmEvtType The device table hardware error event type.
3577	*/
3578	static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3579	EVT_DEV_TAB_HW_ERROR_TYPE_T enmEvtType)
3580	{
3581	EVT_GENERIC_T Event;
3582	iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &Event);
3583	iommuAmdSetHwError(pDevIns, &Event);
3584	iommuAmdWriteEvtLogEntry(pDevIns, &Event);
3585	if (enmOp != IOMMUOP_CMD)
3586	iommuAmdSetPciTargetAbort(pDevIns);
3587
3588	Log((IOMMU_LOG_PFX ": Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u enmType=%u\n", uDevId, GCPhysDte,
3589	enmOp, enmEvtType));
3590	NOREF(enmEvtType);
3591	}
3592
3593
3594	/**
3595	* Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3596	*
3597	* @param uDevId The device ID.
3598	* @param uIova The I/O virtual address.
3599	* @param enmOp The IOMMU operation being performed.
3600	* @param enmEvtType The illegal DTE event type.
3601	* @param pEvent Where to store the initialized event.
3602	*/
3603	static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, IOMMUOP enmOp, EVT_ILLEGAL_DTE_TYPE_T enmEvtType,
3604	PEVT_GENERIC_T pEvent)
3605	{
3606	memset(pEvent, 0, sizeof(*pEvent));
3607	AssertCompile(sizeof(EVT_ILLEGAL_DTE_T) == sizeof(EVT_GENERIC_T));
3608	PEVT_ILLEGAL_DTE_T pIllegalDteErr = (PEVT_ILLEGAL_DTE_T)pEvent;
3609	pIllegalDteErr->n.u16DevId = uDevId;
3610	pIllegalDteErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3611	pIllegalDteErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3612	pIllegalDteErr->n.u1RsvdNotZero = RT_BOOL(enmEvtType == kIllegalDteType_RsvdNotZero);
3613	pIllegalDteErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3614	pIllegalDteErr->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3615	pIllegalDteErr->n.u64Addr = uIova & ~UINT64_C(0x3);
3616	/** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3617	* IOMMU spec here but not for this field for I/O page fault event. */
3618	Assert(!(uIova & UINT64_C(0x3)));
3619	}
3620
3621
3622	/**
3623	* Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3624	*
3625	* @param pDevIns The IOMMU instance data.
3626	* @param uDevId The device ID.
3627	* @param uIova The I/O virtual address.
3628	* @param enmOp The IOMMU operation being performed.
3629	* @param enmEvtType The illegal DTE event type.
3630	*/
3631	static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, IOMMUOP enmOp,
3632	EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3633	{
3634	EVT_GENERIC_T Event;
3635	iommuAmdInitIllegalDteEvent(uDevId, uIova, enmOp, enmEvtType, &Event);
3636	iommuAmdWriteEvtLogEntry(pDevIns, &Event);
3637	if (enmOp != IOMMUOP_CMD)
3638	iommuAmdSetPciTargetAbort(pDevIns);
3639
3640	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmType=%u\n", uDevId, uIova, enmOp,
3641	enmEvtType));
3642	NOREF(enmEvtType);
3643	}
3644
3645
3646	/**
3647	* Initializes an IO_PAGE_FAULT event.
3648	*
3649	* @param uDevId The device ID.
3650	* @param uDomainId The domain ID.
3651	* @param uIova The I/O virtual address being accessed.
3652	* @param fPresent Transaction to a page marked as present (including
3653	* DTE.V=1) or interrupt marked as remapped
3654	* (IRTE.RemapEn=1).
3655	* @param enmOp The IOMMU operation being performed.
3656	* @param enmEvtType The I/O page fault event type.
3657	* @param pEvent Where to store the initialized event.
3658	*/
3659	static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent,
3660	IOMMUOP enmOp, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType, PEVT_GENERIC_T pEvent)
3661	{
3662	memset(pEvent, 0, sizeof(*pEvent));
3663	AssertCompile(sizeof(EVT_IO_PAGE_FAULT_T) == sizeof(EVT_GENERIC_T));
3664	PEVT_IO_PAGE_FAULT_T pIoPageFault = (PEVT_IO_PAGE_FAULT_T)pEvent;
3665	pIoPageFault->n.u16DevId = uDevId;
3666	//pIoPageFault->n.u4PasidHi = 0;
3667	pIoPageFault->n.u16DomainOrPasidLo = uDomainId;
3668	//pIoPageFault->n.u1GuestOrNested = 0;
3669	//pIoPageFault->n.u1NoExecute = 0;
3670	//pIoPageFault->n.u1User = 0;
3671	pIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3672	pIoPageFault->n.u1Present = fPresent;
3673	pIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3674	//pIoPageFault->n.u1PermIndicator = 0;
3675	pIoPageFault->n.u1RsvdNotZero = RT_BOOL( enmEvtType == kIoPageFaultType_PteRsvdNotZero
3676	\|\| enmEvtType == kIoPageFaultType_IrteRemapEn);
3677	pIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3678	pIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3679	pIoPageFault->n.u64Addr = uIova;
3680	}
3681
3682
3683	/**
3684	* Raises an IO_PAGE_FAULT event.
3685	*
3686	* @param pDevIns The IOMMU instance data.
3687	* @param uDevId The device ID.
3688	* @param uDomainId The domain ID.
3689	* @param uIova The I/O virtual address being accessed.
3690	* @param fPresentOrValid Transaction to a page marked as present (including
3691	* DTE.V=1) or interrupt marked as remapped
3692	* (IRTE.RemapEn=1).
3693	* @param enmOp The IOMMU operation being performed.
3694	* @param enmEvtType The I/O page fault event type.
3695	*/
3696	static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, uint16_t uDevId, uint16_t uDomainId, uint64_t uIova,
3697	bool fPresentOrValid, IOMMUOP enmOp, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3698	{
3699	EVT_GENERIC_T Event;
3700	iommuAmdInitIoPageFaultEvent(uDevId, uDomainId, uIova, fPresentOrValid, enmOp, enmEvtType, &Event);
3701
3702	switch (enmEvtType)
3703	{
3704	case kIoPageFaultType_ReadProtect:
3705	case kIoPageFaultType_WriteProtect:
3706	case kIoPageFaultType_ExecuteProtect:
3707	{
3708	/* Cannot be triggered by a command. */
3709	Assert(enmOp != IOMMUOP_CMD);
3710	RT_FALL_THRU();
3711	}
3712	case kIoPageFaultType_DteRsvdPagingMode:
3713	case kIoPageFaultType_PteInvalidPageSize:
3714	case kIoPageFaultType_PteInvalidLvlEncoding:
3715	case kIoPageFaultType_InvalidSkippedPageLvl:
3716	case kIoPageFaultType_PteRsvdNotZero:
3717	case kIoPageFaultType_PteValidNotSet:
3718	case kIoPageFaultType_DteTranslationDisabled:
3719	case kIoPageFaultType_PasidInvalidRange:
3720	{
3721	/*
3722	* For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3723	* create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
3724	*/
3725	if (enmOp != IOMMUOP_TRANSLATE_REQ)
3726	{
3727	iommuAmdWriteEvtLogEntry(pDevIns, &Event);
3728	if (enmOp != IOMMUOP_CMD)
3729	iommuAmdSetPciTargetAbort(pDevIns);
3730	}
3731	break;
3732	}
3733
3734	case kIoPageFaultType_UserSupervisor:
3735	{
3736	/* Access is blocked and only creates an event log entry. */
3737	iommuAmdWriteEvtLogEntry(pDevIns, &Event);
3738	break;
3739	}
3740
3741	case kIoPageFaultType_IrteAddrInvalid:
3742	case kIoPageFaultType_IrteRsvdNotZero:
3743	case kIoPageFaultType_IrteRemapEn:
3744	case kIoPageFaultType_IrteRsvdIntType:
3745	case kIoPageFaultType_IntrReqAborted:
3746	case kIoPageFaultType_IntrWithPasid:
3747	{
3748	/* Only trigerred by interrupt requests. */
3749	Assert(enmOp == IOMMUOP_INTR_REQ);
3750	iommuAmdWriteEvtLogEntry(pDevIns, &Event);
3751	iommuAmdSetPciTargetAbort(pDevIns);
3752	break;
3753	}
3754
3755	case kIoPageFaultType_SmiFilterMismatch:
3756	{
3757	/* Not supported and probably will never be, assert. */
3758	AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3759	break;
3760	}
3761
3762	case kIoPageFaultType_DevId_Invalid:
3763	{
3764	/* Cannot be triggered by a command. */
3765	Assert(enmOp != IOMMUOP_CMD);
3766	Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3767	iommuAmdWriteEvtLogEntry(pDevIns, &Event);
3768	if ( enmOp == IOMMUOP_MEM_READ
3769	\|\| enmOp == IOMMUOP_MEM_WRITE)
3770	iommuAmdSetPciTargetAbort(pDevIns);
3771	break;
3772	}
3773	}
3774
3775
3776	}
3777
3778
3779	/**
3780	* Initializes an IOTLB entry.
3781	*
3782	* @param uDevId The device ID.
3783	* @param uDomainId The domain ID.
3784	* @param fIoPerm The I/O access permissions (IOMMU_IO_PERM_XXX).
3785	* @param uIova The I/O virtual address.
3786	* @param GCPhysSpa The translated system physical address.
3787	* @param pIotlbe Where to store the initialized IOTLB entry.
3788	*/
3789	static void iommuAmdInitIotlbe(uint16_t uDevId, uint16_t uDomainId, uint8_t fIoPerm, uint64_t uIova, RTGCPHYS GCPhysSpa,
3790	PIOTLBE_T pIotlbe)
3791	{
3792	pIotlbe->uDevId = uDevId;
3793	pIotlbe->uDomainId = uDomainId;
3794	pIotlbe->fIoPerm = fIoPerm;
3795	pIotlbe->fRsvd0 = 0;
3796	pIotlbe->uPadding0 = 0;
3797	pIotlbe->uIova = uIova;
3798	pIotlbe->GCPhysSpa = GCPhysSpa;
3799	}
3800
3801
3802	/**
3803	* Returns whether the I/O virtual address is to be excluded from translation and
3804	* permission checks.
3805	*
3806	* @returns @c true if the DVA is excluded, @c false otherwise.
3807	* @param pThis The IOMMU device state.
3808	* @param pDte The device table entry.
3809	* @param uIova The I/O virtual address.
3810	*
3811	* @remarks Ensure the exclusion range is enabled prior to calling this function.
3812	*/
3813	static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
3814	{
3815	/* Ensure the exclusion range is enabled. */
3816	Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
3817
3818	/* Check if the IOVA falls within the exclusion range. */
3819	uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
3820	uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
3821	if (uIovaExclLast - uIova >= uIovaExclFirst)
3822	{
3823	/* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
3824	if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
3825	\|\| pDte->n.u1AllowExclusion)
3826	return true;
3827	}
3828	return false;
3829	}
3830
3831
3832	/**
3833	* Reads a device table entry from guest memory given the device ID.
3834	*
3835	* @returns VBox status code.
3836	* @param pDevIns The IOMMU device instance.
3837	* @param uDevId The device ID.
3838	* @param enmOp The IOMMU operation being performed.
3839	* @param pDte Where to store the device table entry.
3840	*
3841	* @thread Any.
3842	*/
3843	static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
3844	{
3845	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3846	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3847
3848	uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
3849	Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
3850
3851	uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
3852	Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3853
3854	RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3855	uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
3856	RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3857
3858	Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3859	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3860	if (RT_FAILURE(rc))
3861	{
3862	Log((IOMMU_LOG_PFX ": Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3863	iommuAmdRaiseDevTabHwErrorEvent(pDevIns, uDevId, GCPhysDte, enmOp, kDevTabHwErrType_TargetAbort);
3864	}
3865
3866	return rc;
3867	}
3868
3869
3870	/**
3871	* Walks the I/O page table(s) to translate the I/O virtual address to a system
3872	* physical address.
3873	*
3874	* @returns VBox status code.
3875	* @param pDevIns The IOMMU device instance.
3876	* @param uIova The I/O virtual address to translate.
3877	* @param uDevId The device ID.
3878	* @param cbAccess The size of the access.
3879	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
3880	* permissions for the access being made.
3881	* @param enmOp The IOMMU operation being performed.
3882	* @param pGCPhysSpa Where to store the system physical address.
3883	* @param pfIoPerm Where to store the I/O access permissions. This is the
3884	* permission of what access is allowed.
3885	*/
3886	static int iommuAmdWalkIoPageTables(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
3887	PCDTE_T pDte, IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, uint8_t *pfIoPerm)
3888	{
3889	NOREF(pDevIns);
3890	Assert(pDte->n.u1Valid);
3891	Assert(pDte->n.u1TranslationValid);
3892	Assert(cbAccess > 0);
3893
3894	if (pDte->n.u1TranslationValid)
3895	{ /* likely */ }
3896	else
3897	{
3898	iommuAmdRaiseIoPageFaultEvent(pDevIns, uDevId, pDte->n.u16DomainId, uIova, true /* fPresentOrValid */,
3899	enmOp, kIoPageFaultType_DteTranslationDisabled);
3900	*pGCPhysSpa = 0;
3901	*pfIoPerm = 0;
3902	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3903	}
3904
3905	/* If the page table depth is 0, translation is disabled and access is controlled by IR and IW bits. */
3906	if (pDte->n.u3Mode == 0)
3907	{
3908	uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3909	if ((fAccess & fDtePerm) != fAccess)
3910	{
3911	Log((IOMMU_LOG_PFX ": Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
3912	return VERR_IOMMU_ADDR_ACCESS_DENIED;
3913	}
3914	*pGCPhysSpa = uIova;
3915	*pfIoPerm = fDtePerm;
3916	return VINF_SUCCESS;
3917	}
3918
3919	/* If the paging mode exceeds the host-address translation levels, translation fails. */
3920	if (pDte->n.u3Mode > IOMMU_MAX_HOST_PT_LEVEL)
3921	{
3922	/** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3923	* raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3924	* I'm just going with this one... */
3925	*pGCPhysSpa = 0;
3926	*pfIoPerm = IOMMU_IO_PERM_NONE;
3927	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3928	}
3929
3930	/** @todo IOMMU: page walk. */
3931
3932	return VERR_NOT_IMPLEMENTED;
3933	}
3934
3935	/**
3936	* Looks up an I/O virtual address from the device table(s).
3937	*
3938	* @returns VBox status code.
3939	* @param pDevIns The IOMMU instance data.
3940	* @param uDevId The device ID.
3941	* @param uIova The I/O virtual address to lookup.
3942	* @param cbAccess The size of the access.
3943	* @param enmOp The IOMMU operation being performed.
3944	* @param pIotlbe The IOTLBE to update.
3945	*
3946	* @remarks Only the translated address and permission bits are updated in @a
3947	* pIotlbe when this function returns VINF_SUCCESS. Caller is expected to
3948	* know and fill in the rest already.
3949	*/
3950	static int iommuAmdLookupDeviceTables(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, IOMMUOP enmOp,
3951	PIOTLBE_T pIotlbe)
3952	{
3953	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3954
3955	/* Read the device table entry. */
3956	DTE_T Dte;
3957	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3958	if (RT_SUCCESS(rc))
3959	{
3960	RTGCPHYS GCPhysSpa = 0;
3961	uint8_t fIoPerm = IOMMU_IO_PERM_NONE;
3962
3963	if (Dte.n.u1Valid)
3964	{
3965	/* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3966	uint64_t const fRsvdQword0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3967	uint64_t const fRsvdQword1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3968	if ( fRsvdQword0
3969	\|\| fRsvdQword1)
3970	{
3971	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvdQword0,
3972	fRsvdQword1));
3973	iommuAmdRaiseIllegalDteEvent(pDevIns, uDevId, uIova, enmOp, kIllegalDteType_RsvdNotZero);
3974	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3975	}
3976
3977	/* Ensure the IOVA is not in the exclusion range. */
3978	if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
3979	\|\| !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
3980	{
3981	rc = iommuAmdWalkIoPageTables(pDevIns, uDevId, uIova, cbAccess, IOMMU_IO_PERM_READ, &Dte, enmOp, &GCPhysSpa,
3982	&fIoPerm);
3983	if (RT_FAILURE(rc))
3984	Log((IOMMU_LOG_PFX ": I/O page table walk failed. rc=%Rrc\n"));
3985	}
3986	else
3987	{
3988	/* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
3989	GCPhysSpa = uIova;
3990	fIoPerm = IOMMU_IO_PERM_READ_WRITE;
3991	}
3992	}
3993	else
3994	{
3995	/* Addresses are forwarded without translation when DTE.V is 0. */
3996	GCPhysSpa = uIova;
3997	fIoPerm = IOMMU_IO_PERM_READ_WRITE;
3998	}
3999
4000	pIotlbe->GCPhysSpa = GCPhysSpa;
4001	pIotlbe->fIoPerm = fIoPerm;
4002	}
4003	else
4004	{
4005	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4006	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4007	}
4008
4009	return rc;
4010	}
4011
4012
4013	/**
4014	* Memory read request from a device.
4015	*
4016	* @returns VBox status code.
4017	* @param pDevIns The IOMMU device instance.
4018	* @param uDevId The device ID (bus, device, function).
4019	* @param uIova The I/O virtual address being read.
4020	* @param cbRead The number of bytes being read.
4021	* @param pGCPhysSpa Where to store the translated system physical address.
4022	*
4023	* @thread Any.
4024	*/
4025	static int iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, PRTGCPHYS pGCPhysSpa)
4026	{
4027	Assert(pDevIns);
4028	Assert(pGCPhysSpa);
4029	Assert(cbRead > 0);
4030
4031	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4032
4033	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4034	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4035	if (Ctrl.n.u1IommuEn)
4036	{
4037	IOTLBE_T Iotlbe;
4038	iommuAmdInitIotlbe(uDevId, 0 /* uDomainId /, IOMMU_IO_PERM_NONE, uIova, 0 / GCPhySpa */, &Iotlbe);
4039
4040	/** @todo IOMMU: IOTLB cache lookup. */
4041
4042	/* Lookup the IOVA from the device tables. */
4043	int rc = iommuAmdLookupDeviceTables(pDevIns, uDevId, uIova, cbRead, IOMMUOP_MEM_READ, &Iotlbe);
4044
4045	/** @todo IOMMU: Cache translation. */
4046
4047	*pGCPhysSpa = Iotlbe.GCPhysSpa;
4048	return rc;
4049	}
4050
4051	*pGCPhysSpa = uIova;
4052	return VINF_SUCCESS;
4053	}
4054
4055
4056	/**
4057	* Memory write request from a device.
4058	*
4059	* @returns VBox status code.
4060	* @param pDevIns The IOMMU device instance.
4061	* @param uDevId The device ID (bus, device, function).
4062	* @param uIova The I/O virtual address being written.
4063	* @param cbWrite The number of bytes being written.
4064	* @param pGCPhysSpa Where to store the translated physical address.
4065	*
4066	* @thread Any.
4067	*/
4068	static int iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite, PRTGCPHYS pGCPhysSpa)
4069	{
4070	RT_NOREF(pDevIns, uDevId, uIova, cbWrite, pGCPhysSpa);
4071	return VERR_NOT_IMPLEMENTED;
4072	}
4073
4074
4075	/**
4076	* @callback_method_impl{FNIOMMMIONEWWRITE}
4077	*/
4078	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
4079	{
4080	NOREF(pvUser);
4081	Assert(cb == 4 \|\| cb == 8);
4082	Assert(!(off & (cb - 1)));
4083
4084	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
4085	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
4086	}
4087
4088
4089	/**
4090	* @callback_method_impl{FNIOMMMIONEWREAD}
4091	*/
4092	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
4093	{
4094	NOREF(pvUser);
4095	Assert(cb == 4 \|\| cb == 8);
4096	Assert(!(off & (cb - 1)));
4097
4098	uint64_t uResult;
4099	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
4100	if (cb == 8)
4101	(uint64_t )pv = uResult;
4102	else
4103	(uint32_t )pv = (uint32_t)uResult;
4104
4105	return rcStrict;
4106	}
4107
4108
4109	# ifdef IN_RING3
4110	/**
4111	* @callback_method_impl{FNPCICONFIGREAD}
4112	*/
4113	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4114	unsigned cb, uint32_t *pu32Value)
4115	{
4116	/** @todo IOMMU: PCI config read stat counter. */
4117	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4118	Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
4119	VBOXSTRICTRC_VAL(rcStrict)));
4120	return rcStrict;
4121	}
4122
4123
4124	/**
4125	* @callback_method_impl{FNPCICONFIGWRITE}
4126	*/
4127	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4128	unsigned cb, uint32_t u32Value)
4129	{
4130	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4131
4132	/*
4133	* Discard writes to read-only registers that are specific to the IOMMU.
4134	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
4135	* See PCI spec. 6.1. "Configuration Space Organization".
4136	*/
4137	switch (uAddress)
4138	{
4139	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
4140	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
4141	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
4142	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
4143	{
4144	Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
4145	return VINF_SUCCESS;
4146	}
4147	}
4148
4149	IOMMU_LOCK_RET(pDevIns, pThis, VERR_IGNORED);
4150
4151	VBOXSTRICTRC rcStrict;
4152	switch (uAddress)
4153	{
4154	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
4155	{
4156	if (pThis->IommuBar.n.u1Enable)
4157	{
4158	rcStrict = VINF_SUCCESS;
4159	Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
4160	break;
4161	}
4162
4163	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
4164	if (pThis->IommuBar.n.u1Enable)
4165	{
4166	Assert(pThis->hMmio == NIL_IOMMMIOHANDLE);
4167	Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
4168	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
4169	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
4170	if (RT_FAILURE(rcStrict))
4171	Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
4172	}
4173	break;
4174	}
4175
4176	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
4177	{
4178	if (!pThis->IommuBar.n.u1Enable)
4179	pThis->IommuBar.au32[1] = u32Value;
4180	else
4181	{
4182	rcStrict = VINF_SUCCESS;
4183	Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
4184	}
4185	break;
4186	}
4187
4188	case IOMMU_PCI_OFF_MSI_CAP_HDR:
4189	{
4190	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
4191	RT_FALL_THRU();
4192	}
4193
4194	default:
4195	{
4196	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4197	break;
4198	}
4199	}
4200
4201	IOMMU_UNLOCK(pDevIns, pThis);
4202
4203	Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
4204	return rcStrict;
4205	}
4206
4207
4208	/**
4209	* @callback_method_impl{FNDBGFHANDLERDEV}
4210	*/
4211	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4212	{
4213	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4214	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4215	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4216
4217	LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
4218	bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
4219
4220	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
4221	/* Device Table Base Addresses (all segments). */
4222	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4223	{
4224	DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
4225	pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
4226	if (fVerbose)
4227	{
4228	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
4229	IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
4230	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
4231	}
4232	}
4233	/* Command Buffer Base Address Register. */
4234	{
4235	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
4236	uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
4237	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4238	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4239	pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
4240	if (fVerbose)
4241	{
4242	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
4243	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4244	cEntries, cbBuffer);
4245	}
4246	}
4247	/* Event Log Base Address Register. */
4248	{
4249	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
4250	uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
4251	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4252	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4253	pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
4254	if (fVerbose)
4255	{
4256	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4257	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4258	cEntries, cbBuffer);
4259	}
4260	}
4261	/* IOMMU Control Register. */
4262	{
4263	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
4264	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
4265	if (fVerbose)
4266	{
4267	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
4268	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
4269	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
4270	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4271	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4272	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
4273	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
4274	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
4275	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
4276	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
4277	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
4278	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
4279	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
4280	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
4281	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
4282	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
4283	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
4284	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
4285	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
4286	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
4287	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
4288	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
4289	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
4290	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
4291	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
4292	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
4293	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
4294	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
4295	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
4296	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
4297	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
4298	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
4299	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
4300	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
4301	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
4302	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
4303	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
4304	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
4305	}
4306	}
4307	/* Exclusion Base Address Register. */
4308	{
4309	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
4310	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
4311	if (fVerbose)
4312	{
4313	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
4314	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
4315	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
4316	ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
4317	}
4318	}
4319	/* Exclusion Range Limit Register. */
4320	{
4321	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
4322	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
4323	if (fVerbose)
4324	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
4325	}
4326	/* Extended Feature Register. */
4327	{
4328	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
4329	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
4330	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
4331	if (fVerbose)
4332	{
4333	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
4334	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
4335	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
4336	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
4337	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
4338	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
4339	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
4340	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
4341	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
4342	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
4343	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
4344	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
4345	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
4346	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
4347	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
4348	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
4349	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
4350	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
4351	pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
4352	g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
4353	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
4354	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
4355	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
4356	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
4357	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
4358	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
4359	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
4360	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
4361	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
4362	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
4363	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
4364	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
4365	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
4366	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
4367	}
4368	}
4369	/* PPR Log Base Address Register. */
4370	{
4371	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
4372	uint8_t const uEncodedLen = PprLogBar.n.u4Len;
4373	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4374	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4375	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
4376	if (fVerbose)
4377	{
4378	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4379	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4380	cEntries, cbBuffer);
4381	}
4382	}
4383	/* Hardware Event (Hi) Register. */
4384	{
4385	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4386	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4387	if (fVerbose)
4388	{
4389	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4390	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4391	}
4392	}
4393	/* Hardware Event (Lo) Register. */
4394	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4395	/* Hardware Event Status. */
4396	{
4397	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4398	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4399	if (fVerbose)
4400	{
4401	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4402	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4403	}
4404	}
4405	/* Guest Virtual-APIC Log Base Address Register. */
4406	{
4407	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4408	uint8_t const uEncodedLen = GALogBar.n.u4Len;
4409	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4410	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4411	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4412	if (fVerbose)
4413	{
4414	pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4415	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4416	cEntries, cbBuffer);
4417	}
4418	}
4419	/* Guest Virtual-APIC Log Tail Address Register. */
4420	{
4421	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4422	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4423	if (fVerbose)
4424	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4425	}
4426	/* PPR Log B Base Address Register. */
4427	{
4428	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4429	uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4430	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4431	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4432	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4433	if (fVerbose)
4434	{
4435	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4436	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4437	cEntries, cbBuffer);
4438	}
4439	}
4440	/* Event Log B Base Address Register. */
4441	{
4442	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4443	uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4444	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4445	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4446	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4447	if (fVerbose)
4448	{
4449	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4450	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4451	cEntries, cbBuffer);
4452	}
4453	}
4454	/* Device-Specific Feature Extension Register. */
4455	{
4456	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4457	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4458	if (fVerbose)
4459	{
4460	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4461	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4462	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4463	}
4464	}
4465	/* Device-Specific Control Extension Register. */
4466	{
4467	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4468	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4469	if (fVerbose)
4470	{
4471	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4472	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4473	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4474	}
4475	}
4476	/* Device-Specific Status Extension Register. */
4477	{
4478	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4479	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
4480	if (fVerbose)
4481	{
4482	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4483	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4484	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4485	}
4486	}
4487	/* MSI Miscellaneous Information Register (Lo and Hi). */
4488	{
4489	MSI_MISC_INFO_T const MsiMiscInfo = pThis->MsiMiscInfo;
4490	pHlp->pfnPrintf(pHlp, " MSI Misc. Info. Register = %#RX64\n", MsiMiscInfo.u64);
4491	if (fVerbose)
4492	{
4493	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumEvtLog);
4494	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MsiMiscInfo.n.u3GstVirtAddrSize);
4495	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MsiMiscInfo.n.u7PhysAddrSize);
4496	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MsiMiscInfo.n.u7VirtAddrSize);
4497	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MsiMiscInfo.n.u1HtAtsResv);
4498	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumPpr);
4499	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumGa);
4500	}
4501	}
4502	/* MSI Capability Header. */
4503	{
4504	MSI_CAP_HDR_T MsiCapHdr;
4505	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4506	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4507	if (fVerbose)
4508	{
4509	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4510	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4511	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4512	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4513	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4514	}
4515	}
4516	/* MSI Address Register (Lo and Hi). */
4517	{
4518	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4519	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4520	MSI_ADDR_T MsiAddr;
4521	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4522	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4523	if (fVerbose)
4524	pHlp->pfnPrintf(pHlp, " Address = %#RX64\n", MsiAddr.n.u62MsiAddr);
4525	}
4526	/* MSI Data. */
4527	{
4528	MSI_DATA_T MsiData;
4529	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4530	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4531	if (fVerbose)
4532	pHlp->pfnPrintf(pHlp, " Data = %#x\n", MsiData.n.u16MsiData);
4533	}
4534	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4535	{
4536	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4537	MsiMapCapHdr.u32 = 0;
4538	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4539	if (fVerbose)
4540	{
4541	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4542	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4543	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4544	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4545	}
4546	}
4547	/* Performance Optimization Control Register. */
4548	{
4549	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4550	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4551	if (fVerbose)
4552	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4553	}
4554	/* XT (x2APIC) General Interrupt Control Register. */
4555	{
4556	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4557	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4558	if (fVerbose)
4559	{
4560	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4561	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4562	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4563	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4564	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4565	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
4566	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4567	}
4568	}
4569	/* XT (x2APIC) PPR Interrupt Control Register. */
4570	{
4571	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4572	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4573	if (fVerbose)
4574	{
4575	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4576	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4577	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4578	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4579	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4580	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
4581	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4582	}
4583	}
4584	/* XT (X2APIC) GA Log Interrupt Control Register. */
4585	{
4586	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4587	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4588	if (fVerbose)
4589	{
4590	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4591	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4592	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4593	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4594	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4595	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
4596	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4597	}
4598	}
4599	/* MARC Registers. */
4600	{
4601	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4602	{
4603	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4604	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4605	pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4606
4607	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4608	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4609	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4610	MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4611
4612	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4613	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4614	}
4615	}
4616	/* Reserved Register. */
4617	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4618	/* Command Buffer Head Pointer Register. */
4619	{
4620	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4621	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
4622	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
4623	}
4624	/* Command Buffer Tail Pointer Register. */
4625	{
4626	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4627	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
4628	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
4629	}
4630	/* Event Log Head Pointer Register. */
4631	{
4632	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4633	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
4634	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
4635	}
4636	/* Event Log Tail Pointer Register. */
4637	{
4638	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4639	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
4640	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
4641	}
4642	/* Status Register. */
4643	{
4644	IOMMU_STATUS_T const Status = pThis->Status;
4645	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4646	if (fVerbose)
4647	{
4648	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4649	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4650	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4651	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4652	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4653	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4654	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4655	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4656	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4657	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4658	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4659	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4660	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4661	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4662	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4663	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4664	}
4665	}
4666	/* PPR Log Head Pointer. */
4667	{
4668	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4669	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
4670	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
4671	}
4672	/* PPR Log Tail Pointer. */
4673	{
4674	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4675	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
4676	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
4677	}
4678	/* Guest Virtual-APIC Log Head Pointer. */
4679	{
4680	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4681	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
4682	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
4683	}
4684	/* Guest Virtual-APIC Log Tail Pointer. */
4685	{
4686	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4687	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
4688	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
4689	}
4690	/* PPR Log B Head Pointer. */
4691	{
4692	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4693	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
4694	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
4695	}
4696	/* PPR Log B Tail Pointer. */
4697	{
4698	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4699	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
4700	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
4701	}
4702	/* Event Log B Head Pointer. */
4703	{
4704	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4705	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
4706	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
4707	}
4708	/* Event Log B Tail Pointer. */
4709	{
4710	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4711	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
4712	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
4713	}
4714	/* PPR Log Auto Response Register. */
4715	{
4716	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4717	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4718	if (fVerbose)
4719	{
4720	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4721	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4722	}
4723	}
4724	/* PPR Log Overflow Early Warning Indicator Register. */
4725	{
4726	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4727	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4728	if (fVerbose)
4729	{
4730	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4731	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4732	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4733	}
4734	}
4735	/* PPR Log Overflow Early Warning Indicator Register. */
4736	{
4737	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4738	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4739	if (fVerbose)
4740	{
4741	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4742	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4743	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4744	}
4745	}
4746	}
4747
4748
4749	/**
4750	* @callback_method_impl{FNSSMDEVSAVEEXEC}
4751	*/
4752	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4753	{
4754	/** @todo IOMMU: Save state. */
4755	RT_NOREF2(pDevIns, pSSM);
4756	return VERR_NOT_IMPLEMENTED;
4757	}
4758
4759
4760	/**
4761	* @callback_method_impl{FNSSMDEVLOADEXEC}
4762	*/
4763	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4764	{
4765	/** @todo IOMMU: Load state. */
4766	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4767	return VERR_NOT_IMPLEMENTED;
4768	}
4769
4770
4771	/**
4772	* @interface_method_impl{PDMDEVREG,pfnReset}
4773	*/
4774	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4775	{
4776	/*
4777	* Resets read-write portion of the IOMMU state.
4778	*
4779	* State data not initialized here is expected to be initialized during
4780	* device construction and remain read-only through the lifetime of the VM.
4781	*/
4782	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4783	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4784	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4785
4786	memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4787
4788	pThis->CmdBufBaseAddr.u64 = 0;
4789	pThis->CmdBufBaseAddr.n.u4Len = 8;
4790
4791	pThis->EvtLogBaseAddr.u64 = 0;
4792	pThis->EvtLogBaseAddr.n.u4Len = 8;
4793
4794	pThis->Ctrl.u64 = 0;
4795
4796	pThis->ExclRangeBaseAddr.u64 = 0;
4797	pThis->ExclRangeLimit.u64 = 0;
4798
4799	pThis->PprLogBaseAddr.u64 = 0;
4800	pThis->PprLogBaseAddr.n.u4Len = 8;
4801
4802	pThis->HwEvtHi.u64 = 0;
4803	pThis->HwEvtLo = 0;
4804	pThis->HwEvtStatus.u64 = 0;
4805
4806	pThis->GALogBaseAddr.u64 = 0;
4807	pThis->GALogBaseAddr.n.u4Len = 8;
4808	pThis->GALogTailAddr.u64 = 0;
4809
4810	pThis->PprLogBBaseAddr.u64 = 0;
4811	pThis->PprLogBBaseAddr.n.u4Len = 8;
4812
4813	pThis->EvtLogBBaseAddr.u64 = 0;
4814	pThis->EvtLogBBaseAddr.n.u4Len = 8;
4815
4816	pThis->DevSpecificFeat.u64 = 0;
4817	pThis->DevSpecificCtrl.u64 = 0;
4818	pThis->DevSpecificStatus.u64 = 0;
4819
4820	pThis->MsiMiscInfo.u64 = 0;
4821	pThis->PerfOptCtrl.u32 = 0;
4822
4823	pThis->XtGenIntrCtrl.u64 = 0;
4824	pThis->XtPprIntrCtrl.u64 = 0;
4825	pThis->XtGALogIntrCtrl.u64 = 0;
4826
4827	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4828
4829	pThis->CmdBufHeadPtr.u64 = 0;
4830	pThis->CmdBufTailPtr.u64 = 0;
4831	pThis->EvtLogHeadPtr.u64 = 0;
4832	pThis->EvtLogTailPtr.u64 = 0;
4833
4834	pThis->Status.u64 = 0;
4835
4836	pThis->PprLogHeadPtr.u64 = 0;
4837	pThis->PprLogTailPtr.u64 = 0;
4838
4839	pThis->GALogHeadPtr.u64 = 0;
4840	pThis->GALogTailPtr.u64 = 0;
4841
4842	pThis->PprLogBHeadPtr.u64 = 0;
4843	pThis->PprLogBTailPtr.u64 = 0;
4844
4845	pThis->EvtLogBHeadPtr.u64 = 0;
4846	pThis->EvtLogBTailPtr.u64 = 0;
4847
4848	pThis->PprLogAutoResp.u64 = 0;
4849	pThis->PprLogOverflowEarly.u64 = 0;
4850	pThis->PprLogBOverflowEarly.u64 = 0;
4851
4852	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4853	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4854	}
4855
4856
4857	/**
4858	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4859	*/
4860	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4861	{
4862	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4863	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4864	LogFlowFunc(("\n"));
4865
4866	/* Close the command thread semaphore. */
4867	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4868	{
4869	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4870	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4871	}
4872	return VINF_SUCCESS;
4873	}
4874
4875
4876	/**
4877	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4878	*/
4879	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4880	{
4881	NOREF(iInstance);
4882
4883	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4884	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4885	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4886	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4887	int rc;
4888	LogFlowFunc(("\n"));
4889
4890	pThisCC->pDevInsR3 = pDevIns;
4891
4892	/*
4893	* Validate and read the configuration.
4894	*/
4895	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Device\|Function", "");
4896
4897	uint8_t uPciDevice;
4898	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Device", &uPciDevice, 0);
4899	if (RT_FAILURE(rc))
4900	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Device\""));
4901
4902	uint8_t uPciFunction;
4903	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Function", &uPciFunction, 2);
4904	if (RT_FAILURE(rc))
4905	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Function\""));
4906
4907	/*
4908	* Register the IOMMU with PDM.
4909	*/
4910	PDMIOMMUREGR3 IommuReg;
4911	RT_ZERO(IommuReg);
4912	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4913	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4914	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4915	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4916	rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4917	if (RT_FAILURE(rc))
4918	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4919	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4920	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4921	N_("IOMMU helper version mismatch; got %#x expected %#x"),
4922	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4923	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4924	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4925	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4926	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4927
4928	/*
4929	* Initialize read-only PCI configuration space.
4930	*/
4931	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4932	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4933
4934	/* Header. */
4935	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4936	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4937	PDMPciDevSetCommand(pPciDev, 0); /* Command */
4938	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
4939	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4940	PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
4941	PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
4942	PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
4943	PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
4944	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4945	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4946	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
4947	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
4948	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
4949
4950	/* Capability Header. */
4951	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4952	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4953	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
4954	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4955	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4956	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4957	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4958	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4959	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4960	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4961
4962	/* Base Address Low Register. */
4963	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
4964
4965	/* Base Address High Register. */
4966	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4967
4968	/* IOMMU Range Register. */
4969	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
4970
4971	/* Misc. Information Register 0. */
4972	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0,
4973	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
4974	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
4975	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
4976	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
4977	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
4978	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
4979
4980	/* Misc. Information Register 1. */
4981	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, 0);
4982
4983	/* MSI Capability Header register. */
4984	PDMMSIREG MsiReg;
4985	RT_ZERO(MsiReg);
4986	MsiReg.cMsiVectors = 1;
4987	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4988	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4989	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4990	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4991	AssertRCReturn(rc, rc);
4992
4993	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4994	#if 0
4995	/* MSI Address Lo. */
4996	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
4997	/* MSI Address Hi. */
4998	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
4999	/* MSI Data. */
5000	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
5001	#endif
5002
5003	#if 0
5004	/** @todo IOMMU: I don't know if we need to support this, enable later if
5005	* required. */
5006	/* MSI Mapping Capability Header register. */
5007	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
5008	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
5009	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
5010	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
5011	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
5012	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
5013	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
5014	#endif
5015
5016	/*
5017	* Register the PCI function with PDM.
5018	*/
5019	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /* fFlags */, uPciDevice, uPciFunction, "amd-iommu");
5020	AssertLogRelRCReturn(rc, rc);
5021
5022	/*
5023	* Intercept PCI config. space accesses.
5024	*/
5025	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
5026	AssertLogRelRCReturn(rc, rc);
5027
5028	/*
5029	* Create the MMIO region.
5030	* Mapping of the region is done when software configures it via PCI config space.
5031	*/
5032	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
5033	NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
5034	"AMD-IOMMU", &pThis->hMmio);
5035	AssertLogRelRCReturn(rc, rc);
5036
5037	/*
5038	* Register saved state.
5039	*/
5040	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
5041	NULL, NULL, NULL,
5042	NULL, iommuAmdR3SaveExec, NULL,
5043	NULL, iommuAmdR3LoadExec, NULL);
5044	AssertLogRelRCReturn(rc, rc);
5045
5046	/*
5047	* Register debugger info item.
5048	*/
5049	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
5050	AssertLogRelRCReturn(rc, rc);
5051
5052	/*
5053	* Create the command thread and its event semaphore.
5054	*/
5055	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5056	0 /* cbStack */, RTTHREADTYPE_IO, "AMD-IOMMU");
5057	AssertLogRelRCReturn(rc, rc);
5058
5059	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5060	AssertLogRelRCReturn(rc, rc);
5061
5062	/*
5063	* Initialize read-only registers.
5064	*/
5065	/** @todo Don't remove the =0 assignment for now. It's just there so it's easier
5066	* for me to see existing features that we might want to implement. Do it
5067	* later. */
5068	pThis->ExtFeat.u64 = 0;
5069	pThis->ExtFeat.n.u1PrefetchSup = 0;
5070	pThis->ExtFeat.n.u1PprSup = 0;
5071	pThis->ExtFeat.n.u1X2ApicSup = 0;
5072	pThis->ExtFeat.n.u1NoExecuteSup = 0;
5073	pThis->ExtFeat.n.u1GstTranslateSup = 0;
5074	pThis->ExtFeat.n.u1InvAllSup = 0;
5075	pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5076	pThis->ExtFeat.n.u1HwErrorSup = 1;
5077	pThis->ExtFeat.n.u1PerfCounterSup = 0;
5078	pThis->ExtFeat.n.u2HostAddrTranslateSize = IOMMU_MAX_HOST_PT_LEVEL;
5079	pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
5080	pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
5081	pThis->ExtFeat.n.u2SmiFilterSup = 0;
5082	pThis->ExtFeat.n.u3SmiFilterCount = 0;
5083	pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5084	pThis->ExtFeat.n.u2DualPprLogSup = 0;
5085	pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5086	pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
5087	pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5088	AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5089	pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5090	pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5091	pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5092	pThis->ExtFeat.n.u2MarcSup = 0;
5093	pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5094	pThis->ExtFeat.n.u1PerfOptSup = 0;
5095	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5096	pThis->ExtFeat.n.u1GstIoSup = 0;
5097	pThis->ExtFeat.n.u1HostAccessSup = 0;
5098	pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5099	pThis->ExtFeat.n.u1AttrForwardSup = 0;
5100	pThis->ExtFeat.n.u1HostDirtySup = 0;
5101	pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5102	pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5103	pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5104
5105	pThis->RsvdReg = 0;
5106
5107	/*
5108	* Initialize parts of the IOMMU state as it would during reset.
5109	* Must be called -after- initializing PCI config. space registers.
5110	*/
5111	iommuAmdR3Reset(pDevIns);
5112
5113	return VINF_SUCCESS;
5114	}
5115
5116	# else /* !IN_RING3 */
5117
5118	/**
5119	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5120	*/
5121	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5122	{
5123	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5124	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5125	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5126
5127	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5128
5129	/* Set up the MMIO RZ handlers. */
5130	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5131	AssertRCReturn(rc, rc);
5132
5133	/* Set up the IOMMU RZ callbacks. */
5134	PDMIOMMUREGCC IommuReg;
5135	RT_ZERO(IommuReg);
5136	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5137	IommuReg.idxIommu = pThis->idxIommu;
5138	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5139	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5140	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5141	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5142	AssertRCReturn(rc, rc);
5143
5144	return VINF_SUCCESS;
5145	}
5146
5147	# endif /* !IN_RING3 */
5148
5149	/**
5150	* The device registration structure.
5151	*/
5152	const PDMDEVREG g_DeviceIommuAmd =
5153	{
5154	/* .u32Version = */ PDM_DEVREG_VERSION,
5155	/* .uReserved0 = */ 0,
5156	/* .szName = */ "iommu-amd",
5157	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
5158	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
5159	/* .cMaxInstances = */ ~0U,
5160	/* .uSharedVersion = */ 42,
5161	/* .cbInstanceShared = */ sizeof(IOMMU),
5162	/* .cbInstanceCC = */ sizeof(IOMMUCC),
5163	/* .cbInstanceRC = */ sizeof(IOMMURC),
5164	/* .cMaxPciDevices = */ 1,
5165	/* .cMaxMsixVectors = */ 0,
5166	/* .pszDescription = */ "IOMMU (AMD)",
5167	#if defined(IN_RING3)
5168	/* .pszRCMod = */ "VBoxDDRC.rc",
5169	/* .pszR0Mod = */ "VBoxDDR0.r0",
5170	/* .pfnConstruct = */ iommuAmdR3Construct,
5171	/* .pfnDestruct = */ iommuAmdR3Destruct,
5172	/* .pfnRelocate = */ NULL,
5173	/* .pfnMemSetup = */ NULL,
5174	/* .pfnPowerOn = */ NULL,
5175	/* .pfnReset = */ iommuAmdR3Reset,
5176	/* .pfnSuspend = */ NULL,
5177	/* .pfnResume = */ NULL,
5178	/* .pfnAttach = */ NULL,
5179	/* .pfnDetach = */ NULL,
5180	/* .pfnQueryInterface = */ NULL,
5181	/* .pfnInitComplete = */ NULL,
5182	/* .pfnPowerOff = */ NULL,
5183	/* .pfnSoftReset = */ NULL,
5184	/* .pfnReserved0 = */ NULL,
5185	/* .pfnReserved1 = */ NULL,
5186	/* .pfnReserved2 = */ NULL,
5187	/* .pfnReserved3 = */ NULL,
5188	/* .pfnReserved4 = */ NULL,
5189	/* .pfnReserved5 = */ NULL,
5190	/* .pfnReserved6 = */ NULL,
5191	/* .pfnReserved7 = */ NULL,
5192	#elif defined(IN_RING0)
5193	/* .pfnEarlyConstruct = */ NULL,
5194	/* .pfnConstruct = */ iommuAmdRZConstruct,
5195	/* .pfnDestruct = */ NULL,
5196	/* .pfnFinalDestruct = */ NULL,
5197	/* .pfnRequest = */ NULL,
5198	/* .pfnReserved0 = */ NULL,
5199	/* .pfnReserved1 = */ NULL,
5200	/* .pfnReserved2 = */ NULL,
5201	/* .pfnReserved3 = */ NULL,
5202	/* .pfnReserved4 = */ NULL,
5203	/* .pfnReserved5 = */ NULL,
5204	/* .pfnReserved6 = */ NULL,
5205	/* .pfnReserved7 = */ NULL,
5206	#elif defined(IN_RC)
5207	/* .pfnConstruct = */ iommuAmdRZConstruct,
5208	/* .pfnReserved0 = */ NULL,
5209	/* .pfnReserved1 = */ NULL,
5210	/* .pfnReserved2 = */ NULL,
5211	/* .pfnReserved3 = */ NULL,
5212	/* .pfnReserved4 = */ NULL,
5213	/* .pfnReserved5 = */ NULL,
5214	/* .pfnReserved6 = */ NULL,
5215	/* .pfnReserved7 = */ NULL,
5216	#else
5217	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5218	#endif
5219	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5220	};
5221
5222	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5223

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 84170

Download in other formats: