DevIommuAmd.cpp@ 84199

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AMD IOMMU: bugref:9654 Bits.
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1	/* $Id: DevIommuAmd.cpp 84199 2020-05-08 08:23:30Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/msi.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/AssertGuest.h>
26
27	#include "VBoxDD.h"
28	#include <iprt/x86.h>
29	#include <iprt/string.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/**
36	* @name PCI configuration register offsets.
37	* In accordance with the AMD spec.
38	* @{
39	*/
40	#define IOMMU_PCI_OFF_CAP_HDR 0x40
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
42	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
43	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
44	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
45	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
46	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
47	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
48	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
49	#define IOMMU_PCI_OFF_MSI_DATA 0x70
50	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
51	/** @} */
52
53	/**
54	* @name MMIO register offsets.
55	* In accordance with the AMD spec.
56	* @{
57	*/
58	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
59	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
60	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
61	#define IOMMU_MMIO_OFF_CTRL 0x18
62	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
63	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
64	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
65
66	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
67	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
68	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
69	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
70
71	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
72	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
73
74	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
75	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
76
77	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
78	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
79
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
81	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
82	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
83	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
84	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
85	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
86	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
87	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
88	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
89
90	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
91	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
92	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
93
94	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
95	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
96	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
97	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
98	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
99	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
100	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
101
102	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
103
104	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
105	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
106	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
107
108	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
109	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
110	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
111	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
112	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
113	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
114	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
115	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
116	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
117	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
118	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
119	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
120
121	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
122
123	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
124	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
125	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
126	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
127
128	#define IOMMU_MMIO_OFF_STATUS 0x2020
129
130	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
131	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
132
133	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
134	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
135
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
137	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
138
139	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
140	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
141
142	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
143	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
144	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
145	/** @} */
146
147	/**
148	* @name MMIO register-access table offsets.
149	* Each table [first..last] (both inclusive) represents the range of registers
150	* covered by a distinct register-access table. This is done due to arbitrary large
151	* gaps in the MMIO register offsets themselves.
152	* @{
153	*/
154	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
155	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
156
157	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
158	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
159	/** @} */
160
161	/**
162	* @name Commands.
163	* In accordance with the AMD spec.
164	* @{
165	*/
166	#define IOMMU_CMD_COMPLETION_WAIT 0x01
167	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
168	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
169	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
170	#define IOMMU_CMD_INV_INTR_TABLE 0x05
171	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
172	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
173	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
174	/** @} */
175
176	/**
177	* @name Event codes.
178	* In accordance with the AMD spec.
179	* @{
180	*/
181	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
182	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
183	#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
184	#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
185	#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
186	#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
187	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
188	#define IOMMU_EVT_INVALID_DEV_REQ 0x08
189	#define IOMMU_EVT_INVALID_PPR_REQ 0x09
190	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
191	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
192	/** @} */
193
194	/**
195	* @name IOMMU Capability Header.
196	* In accordance with the AMD spec.
197	* @{
198	*/
199	/** CapId: Capability ID. */
200	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
201	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
202	/** CapPtr: Capability Pointer. */
203	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
204	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
205	/** CapType: Capability Type. */
206	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
207	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
208	/** CapRev: Capability Revision. */
209	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
210	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
211	/** IoTlbSup: IO TLB Support. */
212	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
213	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
214	/** HtTunnel: HyperTransport Tunnel translation support. */
215	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
216	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
217	/** NpCache: Not Present table entries Cached. */
218	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
219	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
220	/** EFRSup: Extended Feature Register (EFR) Supported. */
221	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
222	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
223	/** CapExt: Miscellaneous Information Register Supported . */
224	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
225	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
226	/** Bits 31:29 reserved. */
227	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
228	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
229	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
230	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
231	/** @} */
232
233	/**
234	* @name IOMMU Base Address Low Register.
235	* In accordance with the AMD spec.
236	* @{
237	*/
238	/** Enable: Enables access to the address specified in the Base Address Register. */
239	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
240	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
241	/** Bits 13:1 reserved. */
242	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
243	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
244	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
245	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
246	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
247	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
248	(ENABLE, RSVD_1_13, ADDR));
249	/** @} */
250
251	/**
252	* @name IOMMU Range Register.
253	* In accordance with the AMD spec.
254	* @{
255	*/
256	/** UnitID: HyperTransport Unit ID. */
257	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
258	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
259	/** Bits 6:5 reserved. */
260	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
261	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
262	/** RngValid: Range valid. */
263	#define IOMMU_BF_RANGE_VALID_SHIFT 7
264	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
265	/** BusNumber: Device range bus number. */
266	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
267	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
268	/** First Device. */
269	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
270	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
271	/** Last Device. */
272	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
273	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
274	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
275	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
276	/** @} */
277
278	/**
279	* @name IOMMU Miscellaneous Information Register 0.
280	* In accordance with the AMD spec.
281	* @{
282	*/
283	/** MsiNum: MSI message number. */
284	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
285	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
286	/** GvaSize: Guest Virtual Address Size. */
287	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
288	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
289	/** PaSize: Physical Address Size. */
290	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
291	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
292	/** VaSize: Virtual Address Size. */
293	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
294	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
295	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
296	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
297	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
298	/** Bits 26:23 reserved. */
299	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
300	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
301	/** MsiNumPPR: Peripheral Page Request MSI message number. */
302	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
303	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
304	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
305	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
306	/** @} */
307
308	/**
309	* @name IOMMU Miscellaneous Information Register 1.
310	* In accordance with the AMD spec.
311	* @{
312	*/
313	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
314	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
315	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
316	/** Bits 31:5 reserved. */
317	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
318	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
319	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
320	(MSI_NUM_GA, RSVD_5_31));
321	/** @} */
322
323	/**
324	* @name MSI Capability Header Register.
325	* In accordance with the AMD spec.
326	* @{
327	*/
328	/** MsiCapId: Capability ID. */
329	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
330	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
331	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
332	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
333	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
334	/** MsiEn: Message Signal Interrupt enable. */
335	#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
336	#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
337	/** MsiMultMessCap: MSI Multi-Message Capability. */
338	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
339	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
340	/** MsiMultMessEn: MSI Mult-Message Enable. */
341	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
342	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
343	/** Msi64BitEn: MSI 64-bit Enabled. */
344	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
345	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
346	/** Bits 31:24 reserved. */
347	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
348	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
349	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
350	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
351	/** @} */
352
353	/**
354	* @name MSI Mapping Capability Header Register.
355	* In accordance with the AMD spec.
356	* @{
357	*/
358	/** MsiMapCapId: Capability ID. */
359	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
360	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
361	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
362	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
363	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
364	/** MsiMapEn: MSI mapping capability enable. */
365	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
366	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
367	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
368	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
369	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
370	/** Bits 18:28 reserved. */
371	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
372	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
373	/** MsiMapCapType: MSI mapping capability. */
374	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
375	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
376	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
377	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
378	/** @} */
379
380	/**
381	* @name IOMMU Status Register Bits.
382	* In accordance with the AMD spec.
383	* @{
384	*/
385	/** EventOverflow: Event log overflow. */
386	#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
387	/** EventLogInt: Event log interrupt. */
388	#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
389	/** ComWaitInt: Completion wait interrupt. */
390	#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
391	/** EventLogRun: Event log is running. */
392	#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
393	/** CmdBufRun: Command buffer is running. */
394	#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
395	/** PprOverflow: Peripheral page request log overflow. */
396	#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
397	/** PprInt: Peripheral page request log interrupt. */
398	#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
399	/** PprLogRun: Peripheral page request log is running. */
400	#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
401	/** GALogRun: Guest virtual-APIC log is running. */
402	#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
403	/** GALOverflow: Guest virtual-APIC log overflow. */
404	#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
405	/** GAInt: Guest virtual-APIC log interrupt. */
406	#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
407	/** PprOvrflwB: PPR Log B overflow. */
408	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
409	/** PprLogActive: PPR Log B is active. */
410	#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
411	/** EvtOvrflwB: Event log B overflow. */
412	#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
413	/** EventLogActive: Event log B active. */
414	#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
415	/** PprOvrflwEarlyB: PPR log B overflow early warning. */
416	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
417	/** PprOverflowEarly: PPR log overflow early warning. */
418	#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
419	/** @} */
420
421	/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
422	* In accordance with the AMD spec.
423	*
424	* These values match the shifted values of the IR and IW field of the DTE and the
425	* PTE, PDE of the I/O page tables.
426	*
427	* @{ */
428	#define IOMMU_IO_PERM_NONE (0)
429	#define IOMMU_IO_PERM_READ RT_BIT_64(0)
430	#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
431	#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ \| IOMMU_IO_PERM_WRITE)
432	#define IOMMU_IO_PERM_SHIFT 61
433	#define IOMMU_IO_PERM_MASK 0x3
434	/** @} */
435
436	/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
437	* In accordance with the AMD spec.
438	* @{ */
439	#define SYSMGTTYPE_DMA_DENY (0)
440	#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
441	#define SYSMGTTYPE_MSG_INT_ALLOW (2)
442	#define SYSMGTTYPE_DMA_ALLOW (3)
443	/** @} */
444
445	/**
446	* @name IOMMU Control Register Bits.
447	* In accordance with the AMD spec.
448	* @{
449	*/
450	/** IommuEn: Enable the IOMMU. */
451	#define IOMMU_CTRL_IOMMU_EN RT_BIT_64(0)
452	/** HtTunEn: HyperTransport tunnel translation enable. */
453	#define IOMMU_CTRL_HT_TUNNEL_EN RT_BIT_64(1)
454	/** EventLogEn: Event log enable. */
455	#define IOMMU_CTRL_EVT_LOG_EN RT_BIT_64(2)
456	/** EventIntEn: Event interrupt enable. */
457	#define IOMMU_CTRL_EVT_INTR_EN RT_BIT_64(3)
458	/** ComWaitIntEn: Completion wait interrupt enable. */
459	#define IOMMU_CTRL_COMPLETION_WAIT_INTR_EN RT_BIT_64(4)
460	/** InvTimeout: Invalidation timeout. */
461	#define IOMMU_CTRL_INV_TIMEOUT RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7)
462	/** @todo IOMMU: the rest or remove it. */
463	/** @} */
464
465	/** @name Miscellaneous IOMMU defines.
466	* @{ */
467	/** Log prefix string. */
468	#define IOMMU_LOG_PFX "AMD_IOMMU"
469	/** The current saved state version. */
470	#define IOMMU_SAVED_STATE_VERSION 1
471	/** AMD's vendor ID. */
472	#define IOMMU_PCI_VENDOR_ID 0x1022
473	/** VirtualBox IOMMU device ID. */
474	#define IOMMU_PCI_DEVICE_ID 0xc0de
475	/** VirtualBox IOMMU device revision ID. */
476	#define IOMMU_PCI_REVISION_ID 0x01
477	/** Size of the MMIO region in bytes. */
478	#define IOMMU_MMIO_REGION_SIZE _16K
479	/** Number of device table segments supported (power of 2). */
480	#define IOMMU_MAX_DEV_TAB_SEGMENTS 3
481	/** Maximum number of host address translation levels supported. */
482	#define IOMMU_MAX_HOST_PT_LEVEL 6
483	/** The IOTLB entry magic. */
484	#define IOMMU_IOTLBE_MAGIC 0x10acce55
485	/** @} */
486
487	/**
488	* Acquires the IOMMU PDM lock or returns @a a_rcBusy if it's busy.
489	*/
490	#define IOMMU_LOCK_RET(a_pDevIns, a_pThis, a_rcBusy) \
491	do { \
492	NOREF(pThis); \
493	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), (a_rcBusy)); \
494	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
495	{ /* likely */ } \
496	else \
497	return rcLock; \
498	} while (0)
499
500	/**
501	* Releases the IOMMU PDM lock.
502	*/
503	#define IOMMU_UNLOCK(a_pDevIns, a_pThis) \
504	do { \
505	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
506	} while (0)
507
508	/**
509	* Asserts that the critsect is owned by this thread.
510	*/
511	#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
512	do { \
513	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
514	} while (0)
515
516	/**
517	* Gets the device table size given the size field.
518	*/
519	#define IOMMU_GET_DEV_TAB_SIZE(a_uSize) (((a_uSize) + 1) << X86_PAGE_4K_SHIFT)
520
521
522	/*********************************************************************************************************************************
523	* Structures and Typedefs *
524	*********************************************************************************************************************************/
525	/**
526	* The Device ID.
527	* In accordance with VirtualBox's PCI configuration.
528	*/
529	typedef union
530	{
531	struct
532	{
533	uint16_t u3Function : 3; /*< Bits 2:0 - Function. /
534	uint16_t u9Device : 9; /*< Bits 11:3 - Device. /
535	uint16_t u4Bus : 4; /*< Bits 15:12 - Bus. /
536	} n;
537	/** The unsigned integer view. */
538	uint16_t u;
539	} DEVICE_ID_T;
540	AssertCompileSize(DEVICE_ID_T, 2);
541
542	/**
543	* Device Table Entry (DTE).
544	* In accordance with the AMD spec.
545	*/
546	typedef union
547	{
548	struct
549	{
550	RT_GCC_EXTENSION uint64_t u1Valid : 1; /*< Bit 0 - V: Valid. /
551	RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
552	RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
553	RT_GCC_EXTENSION uint64_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
554	RT_GCC_EXTENSION uint64_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
555	RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /*< Bits 51:12 - Page Table Root Pointer. /
556	RT_GCC_EXTENSION uint64_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
557	RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
558	RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
559	RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
560	RT_GCC_EXTENSION uint64_t u2GstMode : 2; /*< Bits 57:56 - GLX: Guest Paging mode levels. /
561	RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). /
562	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
563	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
564	RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
565	RT_GCC_EXTENSION uint64_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
566	RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). /
567	RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /*< Bit 96 - I: IOTLB Enable. /
568	RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
569	RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
570	RT_GCC_EXTENSION uint64_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
571	RT_GCC_EXTENSION uint64_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
572	RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
573	RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
574	RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
575	RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
576	RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). /
577	RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
578	RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
579	RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
580	RT_GCC_EXTENSION uint64_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
581	RT_GCC_EXTENSION uint64_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
582	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
583	RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
584	RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
585	RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
586	RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
587	RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
588	RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 Pass-through. /
589	RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 Pass-through. /
590	RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /*< Bits 223:192 - Reserved. /
591	RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
592	RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
593	RT_GCC_EXTENSION uint64_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
594	RT_GCC_EXTENSION uint64_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
595	} n;
596	/** The 32-bit unsigned integer view. */
597	uint32_t au32[8];
598	/** The 64-bit unsigned integer view. */
599	uint64_t au64[4];
600	} DTE_T;
601	AssertCompileSize(DTE_T, 32);
602	/** Pointer to a device table entry. */
603	typedef DTE_T *PDTE_T;
604	/** Pointer to a const device table entry. */
605	typedef DTE_T const *PCDTE_T;
606
607	/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
608	* Support) feature (bits 52:53). */
609	#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
610
611	/** Mask of valid bits for GTSup (Guest Translation Support) feature (bits 55:60,
612	* bits 80:95). */
613	#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
614	#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
615
616	/* Mask of valid bits for GIoSup (Guest I/O Protection Support) feature (bit 54). */
617	#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
618
619	/* Mask of valid DTE feature bits. */
620	#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
621	\| IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
622	\| IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
623	#define IOMMU_DTE_QWORD_1_FEAT_MASK (IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
624
625	/* Mask of all valid DTE bits (including all feature bits). */
626	#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
627	#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
628	#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xf70fffffffffffff)
629	#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
630
631	/**
632	* I/O Page Translation Entry.
633	* In accordance with the AMD spec.
634	*/
635	typedef union
636	{
637	struct
638	{
639	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
640	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
641	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
642	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
643	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
644	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
645	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
646	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
647	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
648	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
649	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
650	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
651	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
652	} n;
653	/** The 64-bit unsigned integer view. */
654	uint64_t u64;
655	} IOPTE_T;
656	AssertCompileSize(IOPTE_T, 8);
657
658	/**
659	* I/O Page Directory Entry.
660	* In accordance with the AMD spec.
661	*/
662	typedef union
663	{
664	struct
665	{
666	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
667	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
668	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
669	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
670	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
671	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
672	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
673	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
674	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
675	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
676	} n;
677	/** The 64-bit unsigned integer view. */
678	uint64_t u64;
679	} IOPDE_T;
680	AssertCompileSize(IOPDE_T, 8);
681
682	/**
683	* I/O Page Table Entry/Entity.
684	* In accordance with the AMD spec.
685	*
686	* This a common subset of an DTE.au64[0], PTE and PDE.
687	* Named as an "entity" to avoid confusing it with PTE.
688	*/
689	typedef union
690	{
691	struct
692	{
693	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
694	RT_GCC_EXTENSION uint64_t u8Ign0 : 8; /*< Bits 8:1 - Ignored. /
695	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Mode / Next Level: Next page translation level. /
696	RT_GCC_EXTENSION uint64_t u40Addr : 40; /*< Bits 51:12 - Page address. /
697	RT_GCC_EXTENSION uint64_t u9Ign0 : 9; /*< Bits 60:52 - Ignored. /
698	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
699	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
700	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
701	} n;
702	/** The 64-bit unsigned integer view. */
703	uint64_t u64;
704	} IOPTENTITY_T;
705	AssertCompileSize(IOPTENTITY_T, 8);
706	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPTE_T));
707	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPDE_T));
708	/** Pointer to an IOPT_ENTITY_T struct. */
709	typedef IOPTENTITY_T *PIOPTENTITY_T;
710	/** Pointer to a const IOPT_ENTITY_T struct. */
711	typedef IOPTENTITY_T const *PCIOPTENTITY_T;
712
713	/**
714	* Interrupt Remapping Table Entry (IRTE).
715	* In accordance with the AMD spec.
716	*/
717	typedef union
718	{
719	struct
720	{
721	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
722	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
723	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
724	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
725	uint32_t u1DstMode : 1; /*< Bit 6 - DM: Destination Mode. /
726	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
727	uint32_t u8Dst : 8; /*< Bits 15:8 - Destination. /
728	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
729	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
730	} n;
731	/** The 32-bit unsigned integer view. */
732	uint32_t u32;
733	} IRTE_T;
734	AssertCompileSize(IRTE_T, 4);
735	/** Pointer to an IRTE_T struct. */
736	typedef IRTE_T *PIRTE_T;
737	/** Pointer to a const IRTE_T struct. */
738	typedef IRTE_T const *PCIRTE_T;
739
740	/**
741	* Command: Generic Command Buffer Entry.
742	* In accordance with the AMD spec.
743	*/
744	typedef union
745	{
746	struct
747	{
748	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
749	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
750	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
751	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
752	} n;
753	/** The 64-bit unsigned integer view. */
754	uint64_t au64[2];
755	} CMD_GENERIC_T;
756	AssertCompileSize(CMD_GENERIC_T, 16);
757	/** Number of bits to shift the byte offset of a command in the command buffer to
758	* get its index. */
759	#define IOMMU_CMD_GENERIC_SHIFT 4
760
761	/**
762	* Command: COMPLETION_WAIT.
763	* In accordance with the AMD spec.
764	*/
765	typedef union
766	{
767	struct
768	{
769	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
770	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
771	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
772	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
773	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
774	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
775	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
776	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
777	} n;
778	/** The 64-bit unsigned integer view. */
779	uint64_t au64[2];
780	} CMD_COMPLETION_WAIT_T;
781	AssertCompileSize(CMD_COMPLETION_WAIT_T, 16);
782
783	/**
784	* Command: INVALIDATE_DEVTAB_ENTRY.
785	* In accordance with the AMD spec.
786	*/
787	typedef union
788	{
789	struct
790	{
791	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
792	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
793	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
794	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
795	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
796	} n;
797	/** The 64-bit unsigned integer view. */
798	uint64_t au64[2];
799	} CMD_INV_DTE_T;
800	AssertCompileSize(CMD_INV_DTE_T, 16);
801
802	/**
803	* Command: INVALIDATE_IOMMU_PAGES.
804	* In accordance with the AMD spec.
805	*/
806	typedef union
807	{
808	struct
809	{
810	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
811	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
812	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
813	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
814	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
815	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
816	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
817	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
818	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
819	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
820	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
821	} n;
822	/** The 64-bit unsigned integer view. */
823	uint64_t au64[2];
824	} CMD_INV_IOMMU_PAGES_T;
825	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
826
827	/**
828	* Command: INVALIDATE_IOTLB_PAGES.
829	* In accordance with the AMD spec.
830	*/
831	typedef union
832	{
833	struct
834	{
835	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
836	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
837	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
838	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
839	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
840	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
841	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
842	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
843	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
844	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
845	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
846	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
847	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
848	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
849	} n;
850	/** The 64-bit unsigned integer view. */
851	uint64_t au64[2];
852	} CMD_INV_IOTLB_PAGES_T;
853	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
854
855	/**
856	* Command: INVALIDATE_INTR_TABLE.
857	* In accordance with the AMD spec.
858	*/
859	typedef union
860	{
861	struct
862	{
863	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
864	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
865	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
866	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
867	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
868	} u;
869	/** The 64-bit unsigned integer view. */
870	uint64_t au64[2];
871	} CMD_INV_INTR_TABLE_T;
872	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
873
874	/**
875	* Command: COMPLETE_PPR_REQ.
876	* In accordance with the AMD spec.
877	*/
878	typedef union
879	{
880	struct
881	{
882	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
883	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
884	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
885	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
886	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
887	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
888	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
889	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
890	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
891	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
892	} n;
893	/** The 64-bit unsigned integer view. */
894	uint64_t au64[2];
895	} CMD_COMPLETE_PPR_REQ_T;
896	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
897
898	/**
899	* Command: INV_IOMMU_ALL.
900	* In accordance with the AMD spec.
901	*/
902	typedef union
903	{
904	struct
905	{
906	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
907	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
908	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
909	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
910	} n;
911	/** The 64-bit unsigned integer view. */
912	uint64_t au64[2];
913	} CMD_IOMMU_ALL_T;
914	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
915
916	/**
917	* Event Log Entry: Generic.
918	* In accordance with the AMD spec.
919	*/
920	typedef union
921	{
922	struct
923	{
924	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
925	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
926	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
927	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
928	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
929	} n;
930	/** The 32-bit unsigned integer view. */
931	uint32_t au32[4];
932	} EVT_GENERIC_T;
933	AssertCompileSize(EVT_GENERIC_T, 16);
934	/** Number of bits to shift the byte offset of an event entry in the event log
935	* buffer to get its index. */
936	#define IOMMU_EVT_GENERIC_SHIFT 4
937	/** Pointer to a generic event log entry. */
938	typedef EVT_GENERIC_T *PEVT_GENERIC_T;
939	/** Pointer to a const generic event log entry. */
940	typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
941
942	/**
943	* Hardware event types.
944	* In accordance with the AMD spec.
945	*/
946	typedef enum HWEVTTYPE
947	{
948	HWEVTTYPE_RSVD = 0,
949	HWEVTTYPE_MASTER_ABORT,
950	HWEVTTYPE_TARGET_ABORT,
951	HWEVTTYPE_DATA_ERROR
952	} HWEVTTYPE;
953	AssertCompileSize(HWEVTTYPE, 4);
954
955	/**
956	* Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
957	* In accordance with the AMD spec.
958	*/
959	typedef union
960	{
961	struct
962	{
963	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
964	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
965	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
966	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
967	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
968	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
969	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
970	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
971	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
972	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
973	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
974	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
975	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
976	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
977	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
978	} n;
979	/** The 32-bit unsigned integer view. */
980	uint32_t au32[4];
981	} EVT_ILLEGAL_DTE_T;
982	AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
983	/** Pointer to an illegal device table entry event. */
984	typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
985	/** Pointer to a const illegal device table entry event. */
986	typedef EVT_ILLEGAL_DTE_T const *PCEVT_ILLEGAL_DTE_T;
987
988	/**
989	* Event Log Entry: IO_PAGE_FAULT_EVENT.
990	* In accordance with the AMD spec.
991	*/
992	typedef union
993	{
994	struct
995	{
996	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
997	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
998	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
999	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1000	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
1001	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
1002	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1003	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
1004	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1005	uint16_t u1Perm : 1; /*< Bit 54 - PE: Permission Indicator. /
1006	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1007	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1008	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
1009	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1010	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1011	} n;
1012	/** The 32-bit unsigned integer view. */
1013	uint32_t au32[4];
1014	} EVT_IO_PAGE_FAULT_T;
1015	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
1016	/** Pointer to an I/O page fault event. */
1017	typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
1018	/** Pointer to a const I/O page fault event. */
1019	typedef EVT_IO_PAGE_FAULT_T const *PCEVT_IO_PAGE_FAULT_T;
1020
1021
1022	/**
1023	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
1024	* In accordance with the AMD spec.
1025	*/
1026	typedef union
1027	{
1028	struct
1029	{
1030	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1031	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1032	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
1033	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). /
1034	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1035	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). /
1036	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
1037	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation (1=translation, 0=transaction). /
1038	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1039	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1040	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1041	uint64_t u64Addr; /*< Bits 127:64 - Address. /
1042	} n;
1043	/** The 32-bit unsigned integer view. */
1044	uint32_t au32[4];
1045	} EVT_DEV_TAB_HW_ERROR_T;
1046	AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1047	/** Pointer to a device table hardware error event. */
1048	typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1049	/** Pointer to a const device table hardware error event. */
1050	typedef EVT_DEV_TAB_HW_ERROR_T const *PCEVT_DEV_TAB_HW_ERROR_T;
1051
1052	/**
1053	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1054	* In accordance with the AMD spec.
1055	*/
1056	typedef union
1057	{
1058	struct
1059	{
1060	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1061	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1062	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1063	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1064	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1065	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1066	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1067	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1068	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
1069	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
1070	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1071	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1072	uint32_t u4EvtCode : 4; /*< Bit 63:60 - Event code. /
1073	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1074	* table 58 mentions Addr[31:4]. Looks like a typo in the figure. Use
1075	* table as it makes more sense and matches address size in
1076	* EVT_DEV_TAB_HARDWARE_ERROR. See AMD AMD IOMMU spec (3.05-PUB, Jan
1077	* 2020). */
1078	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1079	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of page table entry (Lo). /
1080	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of page table entry (Hi). /
1081	} n;
1082	/** The 32-bit unsigned integer view. */
1083	uint32_t au32[4];
1084	} EVT_PAGE_TAB_HW_ERR_T;
1085	AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1086
1087	/**
1088	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
1089	* In accordance with the AMD spec.
1090	*/
1091	typedef union
1092	{
1093	struct
1094	{
1095	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1096	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
1097	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1098	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1099	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalid command (Lo). /
1100	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalid command (Hi). /
1101	} n;
1102	/** The 32-bit unsigned integer view. */
1103	uint32_t au32[4];
1104	} EVT_ILLEGAL_CMD_ERR_T;
1105	AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1106
1107	/**
1108	* Event Log Entry: COMMAND_HARDWARE_ERROR.
1109	* In accordance with the AMD spec.
1110	*/
1111	typedef union
1112	{
1113	struct
1114	{
1115	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1116	uint32_t u4Rsvd0 : 4; /*< Bits 35:32 - Reserved. /
1117	uint32_t u28AddrLo : 28; /*< Bits 63:36 - Address: SPA of the attempted access (Lo). /
1118	uint32_t u32AddrHi; /*< Bits 95:64 - Address: SPA of the attempted access (Hi). /
1119	} n;
1120	/** The 32-bit unsigned integer view. */
1121	uint32_t au32[3];
1122	} EVT_CMD_HW_ERROR_T;
1123	AssertCompileSize(EVT_CMD_HW_ERROR_T, 12);
1124
1125	/**
1126	* Event Log Entry: IOTLB_INV_TIMEOUT.
1127	* In accordance with the AMD spec.
1128	*/
1129	typedef union
1130	{
1131	struct
1132	{
1133	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1134	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
1135	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1136	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1137	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1138	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
1139	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
1140	} n;
1141	/** The 32-bit unsigned integer view. */
1142	uint32_t au32[4];
1143	} EVT_IOTLB_INV_TIMEOUT_T;
1144	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1145
1146	/**
1147	* Event Log Entry: INVALID_DEVICE_REQUEST.
1148	* In accordance with the AMD spec.
1149	*/
1150	typedef union
1151	{
1152	struct
1153	{
1154	uint32_t u16DevId : 16; /**< Bits 15:0 - Device ID. /
1155	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1156	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
1157	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1158	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1159	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
1160	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
1161	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
1162	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
1163	uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. /
1164	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
1165	} n;
1166	/** The 32-bit unsigned integer view. */
1167	uint32_t au32[4];
1168	} EVT_INVALID_DEV_REQ_T;
1169	AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1170
1171	/**
1172	* Event Log Entry: EVENT_COUNTER_ZERO.
1173	* In accordance with the AMD spec.
1174	*/
1175	typedef union
1176	{
1177	struct
1178	{
1179	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1180	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1181	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1182	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
1183	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
1184	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
1185	} n;
1186	/** The 32-bit unsigned integer view. */
1187	uint32_t au32[4];
1188	} EVT_EVENT_COUNTER_ZERO_T;
1189	AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1190
1191	/**
1192	* IOMMU Capability Header (PCI).
1193	* In accordance with the AMD spec.
1194	*/
1195	typedef union
1196	{
1197	struct
1198	{
1199	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
1200	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
1201	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
1202	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
1203	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
1204	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
1205	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
1206	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
1207	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
1208	uint32_t u3Rsvd0 : 3; /*< Bits 31:29 - Reserved. /
1209	} n;
1210	/** The 32-bit unsigned integer view. */
1211	uint32_t u32;
1212	} IOMMU_CAP_HDR_T;
1213	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1214
1215	/**
1216	* IOMMU Base Address (Lo and Hi) Register (PCI).
1217	* In accordance with the AMD spec.
1218	*/
1219	typedef union
1220	{
1221	struct
1222	{
1223	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1224	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1225	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1226	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1227	} n;
1228	/** The 32-bit unsigned integer view. */
1229	uint32_t au32[2];
1230	/** The 64-bit unsigned integer view. */
1231	uint64_t u64;
1232	} IOMMU_BAR_T;
1233	AssertCompileSize(IOMMU_BAR_T, 8);
1234	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1235
1236	/**
1237	* IOMMU Range Register (PCI).
1238	* In accordance with the AMD spec.
1239	*/
1240	typedef union
1241	{
1242	struct
1243	{
1244	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1245	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1246	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1247	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1248	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1249	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1250	} n;
1251	/** The 32-bit unsigned integer view. */
1252	uint32_t u32;
1253	} IOMMU_RANGE_T;
1254	AssertCompileSize(IOMMU_RANGE_T, 4);
1255
1256	/**
1257	* Device Table Base Address Register (MMIO).
1258	* In accordance with the AMD spec.
1259	*/
1260	typedef union
1261	{
1262	struct
1263	{
1264	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1265	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1266	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1267	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1268	} n;
1269	/** The 64-bit unsigned integer view. */
1270	uint64_t u64;
1271	} DEV_TAB_BAR_T;
1272	AssertCompileSize(DEV_TAB_BAR_T, 8);
1273	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1274	#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1275
1276	/**
1277	* Command Buffer Base Address Register (MMIO).
1278	* In accordance with the AMD spec.
1279	*/
1280	typedef union
1281	{
1282	struct
1283	{
1284	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1285	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1286	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1287	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1288	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1289	} n;
1290	/** The 64-bit unsigned integer view. */
1291	uint64_t u64;
1292	} CMD_BUF_BAR_T;
1293	AssertCompileSize(CMD_BUF_BAR_T, 8);
1294	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1295
1296	/**
1297	* Event Log Base Address Register (MMIO).
1298	* In accordance with the AMD spec.
1299	*/
1300	typedef union
1301	{
1302	struct
1303	{
1304	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1305	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1306	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1307	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - EventLen: Event log length. /
1308	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1309	} n;
1310	/** The 64-bit unsigned integer view. */
1311	uint64_t u64;
1312	} EVT_LOG_BAR_T;
1313	AssertCompileSize(EVT_LOG_BAR_T, 8);
1314	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1315
1316	/**
1317	* IOMMU Control Register (MMIO).
1318	* In accordance with the AMD spec.
1319	*/
1320	typedef union
1321	{
1322	struct
1323	{
1324	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1325	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1326	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1327	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1328	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1329	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1330	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1331	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1332	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1333	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1334	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1335	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1336	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1337	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1338	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1339	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1340	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1341	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1342	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1343	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1344	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1345	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1346	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1347	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1348	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1349	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1350	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1351	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1352	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1353	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1354	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1355	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1356	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1357	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1358	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1359	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1360	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1361	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1362	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1363	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1364	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1365	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1366	} n;
1367	/** The 64-bit unsigned integer view. */
1368	uint64_t u64;
1369	} IOMMU_CTRL_T;
1370	AssertCompileSize(IOMMU_CTRL_T, 8);
1371	#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1372
1373	/**
1374	* IOMMU Exclusion Base Register (MMIO).
1375	* In accordance with the AMD spec.
1376	*/
1377	typedef union
1378	{
1379	struct
1380	{
1381	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1382	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1383	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1384	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1385	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1386	} n;
1387	/** The 64-bit unsigned integer view. */
1388	uint64_t u64;
1389	} IOMMU_EXCL_RANGE_BAR_T;
1390	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1391	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1392
1393	/**
1394	* IOMMU Exclusion Range Limit Register (MMIO).
1395	* In accordance with the AMD spec.
1396	*/
1397	typedef union
1398	{
1399	struct
1400	{
1401	RT_GCC_EXTENSION uint64_t u52ExclLimit : 52; /*< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). /
1402	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1403	} n;
1404	/** The 64-bit unsigned integer view. */
1405	uint64_t u64;
1406	} IOMMU_EXCL_RANGE_LIMIT_T;
1407	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1408	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1409
1410	/**
1411	* IOMMU Extended Feature Register (MMIO).
1412	* In accordance with the AMD spec.
1413	*/
1414	typedef union
1415	{
1416	struct
1417	{
1418	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1419	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1420	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1421	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1422	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations (for GVAs) Support. /
1423	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1424	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1425	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1426	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1427	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1428	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1429	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1430	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1431	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1432	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1433	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1434	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1435	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1436	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1437	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1438	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1439	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1440	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1441	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1442	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1443	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1444	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1445	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1446	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1447	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1448	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1449	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1450	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1451	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1452	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1453	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1454	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1455	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1456	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1457	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1458	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1459	} n;
1460	/** The 64-bit unsigned integer view. */
1461	uint64_t u64;
1462	} IOMMU_EXT_FEAT_T;
1463	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1464
1465	/**
1466	* Peripheral Page Request Log Base Address Register (MMIO).
1467	* In accordance with the AMD spec.
1468	*/
1469	typedef union
1470	{
1471	struct
1472	{
1473	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1474	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1475	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1476	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1477	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1478	} n;
1479	/** The 64-bit unsigned integer view. */
1480	uint64_t u64;
1481	} PPR_LOG_BAR_T;
1482	AssertCompileSize(PPR_LOG_BAR_T, 8);
1483	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1484
1485	/**
1486	* IOMMU Hardware Event Upper Register (MMIO).
1487	* In accordance with the AMD spec.
1488	*/
1489	typedef union
1490	{
1491	struct
1492	{
1493	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1494	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1495	} n;
1496	/** The 64-bit unsigned integer view. */
1497	uint64_t u64;
1498	} IOMMU_HW_EVT_HI_T;
1499	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1500
1501	/**
1502	* IOMMU Hardware Event Lower Register (MMIO).
1503	* In accordance with the AMD spec.
1504	*/
1505	typedef uint64_t IOMMU_HW_EVT_LO_T;
1506
1507	/**
1508	* IOMMU Hardware Event Status (MMIO).
1509	* In accordance with the AMD spec.
1510	*/
1511	typedef union
1512	{
1513	struct
1514	{
1515	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1516	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1517	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1518	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1519	} n;
1520	/** The 64-bit unsigned integer view. */
1521	uint64_t u64;
1522	} IOMMU_HW_EVT_STATUS_T;
1523	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1524	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1525
1526	/**
1527	* Guest Virtual-APIC Log Base Address Register (MMIO).
1528	* In accordance with the AMD spec.
1529	*/
1530	typedef union
1531	{
1532	struct
1533	{
1534	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1535	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1536	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1537	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1538	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1539	} n;
1540	/** The 64-bit unsigned integer view. */
1541	uint64_t u64;
1542	} GALOG_BAR_T;
1543	AssertCompileSize(GALOG_BAR_T, 8);
1544
1545	/**
1546	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1547	* In accordance with the AMD spec.
1548	*/
1549	typedef union
1550	{
1551	struct
1552	{
1553	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1554	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1555	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1556	} n;
1557	/** The 64-bit unsigned integer view. */
1558	uint64_t u64;
1559	} GALOG_TAIL_ADDR_T;
1560	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1561
1562	/**
1563	* PPR Log B Base Address Register (MMIO).
1564	* In accordance with the AMD spec.
1565	* Currently identical to PPR_LOG_BAR_T.
1566	*/
1567	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1568
1569	/**
1570	* Event Log B Base Address Register (MMIO).
1571	* In accordance with the AMD spec.
1572	* Currently identical to EVT_LOG_BAR_T.
1573	*/
1574	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1575
1576	/**
1577	* Device-specific Feature Extension (DSFX) Register (MMIO).
1578	* In accordance with the AMD spec.
1579	*/
1580	typedef union
1581	{
1582	struct
1583	{
1584	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1585	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1586	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1587	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1588	} n;
1589	/** The 64-bit unsigned integer view. */
1590	uint64_t u64;
1591	} DEV_SPECIFIC_FEAT_T;
1592	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1593
1594	/**
1595	* Device-specific Control Extension (DSCX) Register (MMIO).
1596	* In accordance with the AMD spec.
1597	*/
1598	typedef union
1599	{
1600	struct
1601	{
1602	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1603	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1604	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1605	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1606	} n;
1607	/** The 64-bit unsigned integer view. */
1608	uint64_t u64;
1609	} DEV_SPECIFIC_CTRL_T;
1610	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1611
1612	/**
1613	* Device-specific Status Extension (DSSX) Register (MMIO).
1614	* In accordance with the AMD spec.
1615	*/
1616	typedef union
1617	{
1618	struct
1619	{
1620	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1621	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1622	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1623	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1624	} n;
1625	/** The 64-bit unsigned integer view. */
1626	uint64_t u64;
1627	} DEV_SPECIFIC_STATUS_T;
1628	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1629
1630	/**
1631	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1632	* In accordance with the AMD spec.
1633	*/
1634	typedef union
1635	{
1636	struct
1637	{
1638	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1639	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1640	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1641	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1642	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1643	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1644	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1645	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1646	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1647	} n;
1648	/** The 32-bit unsigned integer view. */
1649	uint32_t au32[2];
1650	/** The 64-bit unsigned integer view. */
1651	uint64_t u64;
1652	} MSI_MISC_INFO_T;
1653	AssertCompileSize(MSI_MISC_INFO_T, 8);
1654	/** MSI Vector Register 0 and 1 (MMIO). */
1655	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1656
1657	/**
1658	* MSI Capability Header Register (PCI + MMIO).
1659	* In accordance with the AMD spec.
1660	*/
1661	typedef union
1662	{
1663	struct
1664	{
1665	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1666	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1667	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1668	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1669	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1670	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1671	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1672	} n;
1673	/** The 32-bit unsigned integer view. */
1674	uint32_t u32;
1675	} MSI_CAP_HDR_T;
1676	AssertCompileSize(MSI_CAP_HDR_T, 4);
1677	#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1678
1679	/**
1680	* MSI Address Register (PCI + MMIO).
1681	* In accordance with the AMD spec.
1682	*/
1683	typedef union
1684	{
1685	struct
1686	{
1687	RT_GCC_EXTENSION uint64_t u2Rsvd : 2; /*< Bits 1:0 - Reserved. /
1688	RT_GCC_EXTENSION uint64_t u62MsiAddr : 62; /*< Bits 31:2 - MsiAddr: MSI Address. /
1689	} n;
1690	/** The 32-bit unsigned integer view. */
1691	uint32_t au32[2];
1692	/** The 64-bit unsigned integer view. */
1693	uint64_t u64;
1694	} MSI_ADDR_T;
1695	AssertCompileSize(MSI_ADDR_T, 8);
1696	#define IOMMU_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc)
1697
1698	/**
1699	* MSI Data Register (PCI + MMIO).
1700	* In accordance with the AMD spec.
1701	*/
1702	typedef union
1703	{
1704	struct
1705	{
1706	uint16_t u16MsiData; /*< Bits 15:0 - MsiData: MSI Data. /
1707	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1708	} n;
1709	/** The 32-bit unsigned integer view. */
1710	uint32_t u32;
1711	} MSI_DATA_T;
1712	AssertCompileSize(MSI_DATA_T, 4);
1713	#define IOMMU_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff)
1714
1715	/**
1716	* MSI Mapping Capability Header Register (PCI + MMIO).
1717	* In accordance with the AMD spec.
1718	*/
1719	typedef union
1720	{
1721	struct
1722	{
1723	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1724	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1725	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1726	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1727	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1728	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1729	} n;
1730	/** The 32-bit unsigned integer view. */
1731	uint32_t u32;
1732	} MSI_MAP_CAP_HDR_T;
1733	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1734
1735	/**
1736	* Performance Optimization Control Register (MMIO).
1737	* In accordance with the AMD spec.
1738	*/
1739	typedef union
1740	{
1741	struct
1742	{
1743	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1744	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1745	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1746	} n;
1747	/** The 32-bit unsigned integer view. */
1748	uint32_t u32;
1749	} IOMMU_PERF_OPT_CTRL_T;
1750	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1751
1752	/**
1753	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1754	* In accordance with the AMD spec.
1755	*/
1756	typedef union
1757	{
1758	struct
1759	{
1760	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1761	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1762	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1763	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1764	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1765	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1766	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1767	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1768	} n;
1769	/** The 64-bit unsigned integer view. */
1770	uint64_t u64;
1771	} IOMMU_XT_GEN_INTR_CTRL_T;
1772	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1773
1774	/**
1775	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1776	* In accordance with the AMD spec.
1777	*/
1778	typedef union
1779	{
1780	struct
1781	{
1782	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1783	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1784	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1785	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1786	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1787	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1788	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1789	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1790	} n;
1791	/** The 64-bit unsigned integer view. */
1792	uint64_t u64;
1793	} IOMMU_XT_INTR_CTRL_T;
1794	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1795
1796	/**
1797	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1798	* In accordance with the AMD spec.
1799	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1800	*/
1801	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1802
1803	/**
1804	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1805	* In accordance with the AMD spec.
1806	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1807	*/
1808	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1809
1810	/**
1811	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1812	* In accordance with the AMD spec.
1813	*/
1814	typedef union
1815	{
1816	struct
1817	{
1818	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1819	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1820	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1821	} n;
1822	/** The 64-bit unsigned integer view. */
1823	uint64_t u64;
1824	} MARC_APER_BAR_T;
1825	AssertCompileSize(MARC_APER_BAR_T, 8);
1826
1827	/**
1828	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1829	* In accordance with the AMD spec.
1830	*/
1831	typedef union
1832	{
1833	struct
1834	{
1835	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1836	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1837	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1838	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1839	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1840	} n;
1841	/** The 64-bit unsigned integer view. */
1842	uint64_t u64;
1843	} MARC_APER_RELOC_T;
1844	AssertCompileSize(MARC_APER_RELOC_T, 8);
1845
1846	/**
1847	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1848	* In accordance with the AMD spec.
1849	*/
1850	typedef union
1851	{
1852	struct
1853	{
1854	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1855	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1856	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1857	} n;
1858	/** The 64-bit unsigned integer view. */
1859	uint64_t u64;
1860	} MARC_APER_LEN_T;
1861
1862	/**
1863	* Memory Access and Routing Control (MARC) Aperture Register.
1864	* This combines other registers to match the MMIO layout for convenient access.
1865	*/
1866	typedef struct
1867	{
1868	MARC_APER_BAR_T Base;
1869	MARC_APER_RELOC_T Reloc;
1870	MARC_APER_LEN_T Length;
1871	} MARC_APER_T;
1872	AssertCompileSize(MARC_APER_T, 24);
1873
1874	/**
1875	* IOMMU Reserved Register (MMIO).
1876	* In accordance with the AMD spec.
1877	* This register is reserved for hardware use (although RW?).
1878	*/
1879	typedef uint64_t IOMMU_RSVD_REG_T;
1880
1881	/**
1882	* Command Buffer Head Pointer Register (MMIO).
1883	* In accordance with the AMD spec.
1884	*/
1885	typedef union
1886	{
1887	struct
1888	{
1889	uint32_t off; /*< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). /
1890	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1891	} n;
1892	/** The 32-bit unsigned integer view. */
1893	uint32_t au32[2];
1894	/** The 64-bit unsigned integer view. */
1895	uint64_t u64;
1896	} CMD_BUF_HEAD_PTR_T;
1897	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1898	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1899
1900	/**
1901	* Command Buffer Tail Pointer Register (MMIO).
1902	* In accordance with the AMD spec.
1903	* Currently identical to CMD_BUF_HEAD_PTR_T.
1904	*/
1905	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1906	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1907
1908	/**
1909	* Event Log Head Pointer Register (MMIO).
1910	* In accordance with the AMD spec.
1911	* Currently identical to CMD_BUF_HEAD_PTR_T.
1912	*/
1913	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1914	#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1915
1916	/**
1917	* Event Log Tail Pointer Register (MMIO).
1918	* In accordance with the AMD spec.
1919	* Currently identical to CMD_BUF_HEAD_PTR_T.
1920	*/
1921	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1922	#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1923
1924
1925	/**
1926	* IOMMU Status Register (MMIO).
1927	* In accordance with the AMD spec.
1928	*/
1929	typedef union
1930	{
1931	struct
1932	{
1933	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
1934	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
1935	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
1936	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
1937	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
1938	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
1939	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
1940	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
1941	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
1942	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
1943	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
1944	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
1945	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
1946	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
1947	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
1948	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
1949	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
1950	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
1951	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1952	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
1953	} n;
1954	/** The 32-bit unsigned integer view. */
1955	uint32_t au32[2];
1956	/** The 64-bit unsigned integer view. */
1957	uint64_t u64;
1958	} IOMMU_STATUS_T;
1959	AssertCompileSize(IOMMU_STATUS_T, 8);
1960	#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
1961	#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
1962
1963	/**
1964	* PPR Log Head Pointer Register (MMIO).
1965	* In accordance with the AMD spec.
1966	* Currently identical to CMD_BUF_HEAD_PTR_T.
1967	*/
1968	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
1969
1970	/**
1971	* PPR Log Tail Pointer Register (MMIO).
1972	* In accordance with the AMD spec.
1973	* Currently identical to CMD_BUF_HEAD_PTR_T.
1974	*/
1975	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
1976
1977	/**
1978	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
1979	* In accordance with the AMD spec.
1980	*/
1981	typedef union
1982	{
1983	struct
1984	{
1985	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
1986	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
1987	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
1988	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1989	} n;
1990	/** The 32-bit unsigned integer view. */
1991	uint32_t au32[2];
1992	/** The 64-bit unsigned integer view. */
1993	uint64_t u64;
1994	} GALOG_HEAD_PTR_T;
1995	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
1996
1997	/**
1998	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
1999	* In accordance with the AMD spec.
2000	* Currently identical to GALOG_HEAD_PTR_T.
2001	*/
2002	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
2003
2004	/**
2005	* PPR Log B Head Pointer Register (MMIO).
2006	* In accordance with the AMD spec.
2007	* Currently identical to CMD_BUF_HEAD_PTR_T.
2008	*/
2009	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
2010
2011	/**
2012	* PPR Log B Tail Pointer Register (MMIO).
2013	* In accordance with the AMD spec.
2014	* Currently identical to CMD_BUF_HEAD_PTR_T.
2015	*/
2016	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
2017
2018	/**
2019	* Event Log B Head Pointer Register (MMIO).
2020	* In accordance with the AMD spec.
2021	* Currently identical to CMD_BUF_HEAD_PTR_T.
2022	*/
2023	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
2024
2025	/**
2026	* Event Log B Tail Pointer Register (MMIO).
2027	* In accordance with the AMD spec.
2028	* Currently identical to CMD_BUF_HEAD_PTR_T.
2029	*/
2030	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
2031
2032	/**
2033	* PPR Log Auto Response Register (MMIO).
2034	* In accordance with the AMD spec.
2035	*/
2036	typedef union
2037	{
2038	struct
2039	{
2040	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
2041	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
2042	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
2043	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
2044	} n;
2045	/** The 32-bit unsigned integer view. */
2046	uint32_t au32[2];
2047	/** The 64-bit unsigned integer view. */
2048	uint64_t u64;
2049	} PPR_LOG_AUTO_RESP_T;
2050	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
2051
2052	/**
2053	* PPR Log Overflow Early Indicator Register (MMIO).
2054	* In accordance with the AMD spec.
2055	*/
2056	typedef union
2057	{
2058	struct
2059	{
2060	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
2061	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
2062	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
2063	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
2064	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2065	} n;
2066	/** The 32-bit unsigned integer view. */
2067	uint32_t au32[2];
2068	/** The 64-bit unsigned integer view. */
2069	uint64_t u64;
2070	} PPR_LOG_OVERFLOW_EARLY_T;
2071	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2072
2073	/**
2074	* PPR Log B Overflow Early Indicator Register (MMIO).
2075	* In accordance with the AMD spec.
2076	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2077	*/
2078	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2079
2080	/**
2081	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2082	* In accordance with the AMD spec.
2083	*/
2084	typedef enum EVT_ILLEGAL_DTE_TYPE_T
2085	{
2086	kIllegalDteType_RsvdNotZero = 0,
2087	kIllegalDteType_RsvdIntTab,
2088	kIllegalDteType_RsvdIoCtl,
2089	kIllegalDteType_RsvdIntCtl
2090	} EVT_ILLEGAL_DTE_TYPE_T;
2091
2092	/**
2093	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2094	* In accordance with the AMD spec.
2095	*/
2096	typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2097	{
2098	/* Memory transaction. */
2099	kIoPageFaultType_DteRsvdPagingMode = 0,
2100	kIoPageFaultType_PteInvalidPageSize,
2101	kIoPageFaultType_PteInvalidLvlEncoding,
2102	kIoPageFaultType_InvalidSkippedPageLvl,
2103	kIoPageFaultType_PteRsvdNotZero,
2104	kIoPageFaultType_PteValidNotSet,
2105	kIoPageFaultType_DteTranslationDisabled,
2106	kIoPageFaultType_PasidInvalidRange,
2107	kIoPageFaultType_ReadProtect,
2108	kIoPageFaultType_WriteProtect,
2109	kIoPageFaultType_ExecuteProtect,
2110	kIoPageFaultType_UserSupervisor,
2111	/* Interrupt remapping */
2112	kIoPageFaultType_IrteAddrInvalid,
2113	kIoPageFaultType_IrteRsvdNotZero,
2114	kIoPageFaultType_IrteRemapEn,
2115	kIoPageFaultType_IrteRsvdIntType,
2116	kIoPageFaultType_IntrReqAborted,
2117	kIoPageFaultType_IntrWithPasid,
2118	kIoPageFaultType_SmiFilterMismatch,
2119	/* Memory transaction or interrupt remapping. */
2120	kIoPageFaultType_DevId_Invalid
2121	} EVT_IO_PAGE_FAULT_TYPE_T;
2122
2123	/**
2124	* DEV_TAB_HARDWARE_ERROR Event Types.
2125	* In accordance with the AMD spec.
2126	*/
2127	typedef enum EVT_DEV_TAB_HW_ERROR_TYPE_T
2128	{
2129	kDevTabHwErrType_MasterAbort = 0,
2130	kDevTabHwErrType_TargetAbort,
2131	kDevTabHwErrType_PoisonedData
2132	} EVT_DEV_TAB_HW_ERROR_TYPE_T;
2133
2134	/**
2135	* PAGE_TAB_HARDWARE_ERROR Even Types.
2136	* In accordance with the AMD spec.
2137	*/
2138	typedef enum EVT_PAGE_TAB_HW_ERR_TYPE_T
2139	{
2140	kPageTabHwErrType_MasterAbort = 0,
2141	kPageTabHwErrType_TargetAbort,
2142	kPageTabHwErrType_PoisonedData,
2143	} EVT_PAGE_TAB_HW_ERR_TYPE_T;
2144
2145	/**
2146	* COMMAND_HARDWARE_ERROR Event Types.
2147	* In accordance with the AMD spec.
2148	*/
2149	typedef enum EVT_CMD_HW_ERROR_TYPE_T
2150	{
2151	kCmdHwErrType_MasterAbort = 0,
2152	kCmdHwErrType_TargetAbort,
2153	kCmdHwErrType_PoisonedData
2154	} EVT_CMD_HW_ERROR_TYPE_T;
2155
2156	/**
2157	* ILLEGAL_COMMAND_ERROR Event Types.
2158	* In accordance with the AMD spec.
2159	*/
2160	typedef enum EVT_ILLEGAL_CMD_ERR_TYPE_T
2161	{
2162	kIllegalCmdErrType_RsvdNotZero = 0,
2163	kIllegalCmdErrType_CmdNotSupported,
2164	kIllegalCmdErrType_IotlbNotSupported
2165	} EVT_ILLEGAL_CMD_ERR_TYPE_T;
2166
2167	/**
2168	* IOTLB_INV_TIMEOUT Event Types.
2169	* In accordance with the AMD spec.
2170	*/
2171	typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2172	{
2173	InvTimeoutType_NoResponse = 0
2174	} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2175
2176	/**
2177	* INVALID_DEVICE_REQUEST Event Types.
2178	* In accordance with the AMD spec.
2179	*/
2180	typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2181	{
2182	/* Access. */
2183	kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2184	kInvalidDevReqType_PretranslatedTransaction,
2185	kInvalidDevReqType_PortIo,
2186	kInvalidDevReqType_SysMgt,
2187	kInvalidDevReqType_IntrRange,
2188	kInvalidDevReqType_RsvdIntrRange,
2189	kInvalidDevReqType_SysMgtAddr,
2190	/* Translation Request. */
2191	kInvalidDevReqType_TrAccessInvalid,
2192	kInvalidDevReqType_TrDisabled,
2193	kInvalidDevReqType_DevIdInvalid,
2194	} EVT_INVALID_DEV_REQ_TYPE_T;
2195
2196	/**
2197	* INVALID_PPR_REQUEST Event Types.
2198	* In accordance with the AMD spec.
2199	*/
2200	typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2201	{
2202	kInvalidPprReqType_PriNotSupported,
2203	kInvalidPprReqType_GstTranslateDisabled
2204	} EVT_INVALID_PPR_REQ_TYPE_T;
2205
2206	/**
2207	* IOMMU operations (transaction) types.
2208	*/
2209	typedef enum IOMMUOP
2210	{
2211	/** Address translation request. */
2212	IOMMUOP_TRANSLATE_REQ = 0,
2213	/** Memory read request. */
2214	IOMMUOP_MEM_READ,
2215	/** Memory write request. */
2216	IOMMUOP_MEM_WRITE,
2217	/** Interrupt request. */
2218	IOMMUOP_INTR_REQ,
2219	/** Command. */
2220	IOMMUOP_CMD
2221	} IOMMUOP;
2222	AssertCompileSize(IOMMUOP, 4);
2223
2224	/**
2225	* IOMMU I/O TLB Entry.
2226	* @note Update iommuAmdInitIotlbe() when changes are made.
2227	*/
2228	typedef struct
2229	{
2230	/** Magic (IOMMU_IOTLBE_MAGIC). */
2231	uint32_t uMagic;
2232	/** Reserved for future (eviction hints?). */
2233	uint16_t uRsvd0;
2234	/** The I/O access permissions (IOMMU_IO_PERM_XXX). */
2235	uint8_t fIoPerm;
2236	/** The number of offset bits in the system physical address. */
2237	uint8_t cShift;
2238	/** The translated system physical address (SPA) of the page. */
2239	RTGCPHYS GCPhysSpa;
2240	} IOTLBE_T;
2241	AssertCompileSizeAlignment(IOTLBE_T, 8);
2242	AssertCompileMemberAlignment(IOTLBE_T, GCPhysSpa, 8);
2243	/** Pointer to an IOMMU I/O TLB entry struct. */
2244	typedef IOTLBE_T *PIOTLBE_T;
2245	/** Pointer to a const IOMMU I/O TLB entry struct. */
2246	typedef IOTLBE_T const *PCIOTLBE_T;
2247
2248	/**
2249	* The shared IOMMU device state.
2250	*/
2251	typedef struct IOMMU
2252	{
2253	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
2254	uint32_t idxIommu;
2255	/** Alignment padding. */
2256	uint32_t uPadding0;
2257	/** The event semaphore the command thread waits on. */
2258	SUPSEMEVENT hEvtCmdThread;
2259	/** The MMIO handle. */
2260	IOMMMIOHANDLE hMmio;
2261
2262	/** @name PCI: Base capability block registers.
2263	* @{ */
2264	IOMMU_BAR_T IommuBar; /*< IOMMU base address register. /
2265	/** @} */
2266
2267	/** @name MMIO: Control and status registers.
2268	* @{ */
2269	DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /*< Device table base address registers. /
2270	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
2271	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
2272	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
2273	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
2274	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
2275	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
2276	/** @} */
2277
2278	/** @name MMIO: PPR Log registers.
2279	* @{ */
2280	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
2281	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
2282	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
2283	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
2284	/** @} */
2285
2286	/** @todo IOMMU: SMI filter. */
2287
2288	/** @name MMIO: Guest Virtual-APIC Log registers.
2289	* @{ */
2290	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
2291	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
2292	/** @} */
2293
2294	/** @name MMIO: Alternate PPR and Event Log registers.
2295	* @{ */
2296	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
2297	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
2298	/** @} */
2299
2300	/** @name MMIO: Device-specific feature registers.
2301	* @{ */
2302	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
2303	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
2304	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
2305	/** @} */
2306
2307	/** @name MMIO: MSI Capability Block registers.
2308	* @{ */
2309	MSI_MISC_INFO_T MsiMiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
2310	/** @} */
2311
2312	/** @name MMIO: Performance Optimization Control registers.
2313	* @{ */
2314	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
2315	/** @} */
2316
2317	/** @name MMIO: x2APIC Control registers.
2318	* @{ */
2319	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
2320	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
2321	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
2322	/** @} */
2323
2324	/** @name MMIO: MARC registers.
2325	* @{ */
2326	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
2327	/** @} */
2328
2329	/** @name MMIO: Reserved register.
2330	* @{ */
2331	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
2332	/** @} */
2333
2334	/** @name MMIO: Command and Event Log pointer registers.
2335	* @{ */
2336	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
2337	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
2338	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
2339	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
2340	/** @} */
2341
2342	/** @name MMIO: Command and Event Status register.
2343	* @{ */
2344	IOMMU_STATUS_T Status; /*< IOMMU status register. /
2345	/** @} */
2346
2347	/** @name MMIO: PPR Log Head and Tail pointer registers.
2348	* @{ */
2349	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
2350	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
2351	/** @} */
2352
2353	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
2354	* @{ */
2355	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
2356	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
2357	/** @} */
2358
2359	/** @name MMIO: PPR Log B Head and Tail pointer registers.
2360	* @{ */
2361	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
2362	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
2363	/** @} */
2364
2365	/** @name MMIO: Event Log B Head and Tail pointer registers.
2366	* @{ */
2367	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
2368	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
2369	/** @} */
2370
2371	/** @name MMIO: PPR Log Overflow protection registers.
2372	* @{ */
2373	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
2374	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
2375	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
2376	/** @} */
2377
2378	/** @todo IOMMU: IOMMU Event counter registers. */
2379
2380	/** @todo IOMMU: Stat counters. */
2381	} IOMMU;
2382	/** Pointer to the IOMMU device state. */
2383	typedef struct IOMMU *PIOMMU;
2384	/** Pointer to the const IOMMU device state. */
2385	typedef const struct IOMMU *PCIOMMU;
2386	AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
2387	AssertCompileMemberAlignment(IOMMU, hMmio, 8);
2388	AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
2389
2390	/**
2391	* The ring-3 IOMMU device state.
2392	*/
2393	typedef struct IOMMUR3
2394	{
2395	/** Device instance. */
2396	PPDMDEVINSR3 pDevInsR3;
2397	/** The IOMMU helpers. */
2398	PCPDMIOMMUHLPR3 pIommuHlpR3;
2399	/** The command thread handle. */
2400	R3PTRTYPE(PPDMTHREAD) pCmdThread;
2401	} IOMMUR3;
2402	/** Pointer to the ring-3 IOMMU device state. */
2403	typedef IOMMUR3 *PIOMMUR3;
2404
2405	/**
2406	* The ring-0 IOMMU device state.
2407	*/
2408	typedef struct IOMMUR0
2409	{
2410	/** Device instance. */
2411	PPDMDEVINSR0 pDevInsR0;
2412	/** The IOMMU helpers. */
2413	PCPDMIOMMUHLPR0 pIommuHlpR0;
2414	} IOMMUR0;
2415	/** Pointer to the ring-0 IOMMU device state. */
2416	typedef IOMMUR0 *PIOMMUR0;
2417
2418	/**
2419	* The raw-mode IOMMU device state.
2420	*/
2421	typedef struct IOMMURC
2422	{
2423	/** Device instance. */
2424	PPDMDEVINSR0 pDevInsRC;
2425	/** The IOMMU helpers. */
2426	PCPDMIOMMUHLPRC pIommuHlpRC;
2427	} IOMMURC;
2428	/** Pointer to the raw-mode IOMMU device state. */
2429	typedef IOMMURC *PIOMMURC;
2430
2431	/** The IOMMU device state for the current context. */
2432	typedef CTX_SUFF(IOMMU) IOMMUCC;
2433	/** Pointer to the IOMMU device state for the current context. */
2434	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
2435
2436	/**
2437	* IOMMU register access routines.
2438	*/
2439	typedef struct
2440	{
2441	const char *pszName;
2442	VBOXSTRICTRC (pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t pu64Value);
2443	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
2444	bool f64BitReg;
2445	} IOMMUREGACC;
2446
2447
2448	/*********************************************************************************************************************************
2449	* Global Variables *
2450	*********************************************************************************************************************************/
2451	/**
2452	* An array of the number of device table segments supported.
2453	* Indexed by u2DevTabSegSup.
2454	*/
2455	static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
2456
2457	/**
2458	* An array of the masks to select the device table segment index from a device ID.
2459	*/
2460	static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
2461
2462	/**
2463	* The maximum size (inclusive) of each device table segment (0 to 7).
2464	* Indexed by the device table segment index.
2465	*/
2466	static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
2467
2468
2469	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
2470	/**
2471	* Gets the maximum number of buffer entries for the given buffer length.
2472	*
2473	* @returns Number of buffer entries.
2474	* @param uEncodedLen The length (power-of-2 encoded).
2475	*/
2476	DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
2477	{
2478	Assert(uEncodedLen > 7);
2479	return 2 << (uEncodedLen - 1);
2480	}
2481
2482
2483	/**
2484	* Gets the total length of the buffer given a base register's encoded length.
2485	*
2486	* @returns The length of the buffer in bytes.
2487	* @param uEncodedLen The length (power-of-2 encoded).
2488	*/
2489	DECLINLINE(uint32_t) iommuAmdGetBufLength(uint8_t uEncodedLen)
2490	{
2491	Assert(uEncodedLen > 7);
2492	return (2 << (uEncodedLen - 1)) << 4;
2493	}
2494
2495
2496	/**
2497	* Gets the number of (unconsumed) entries in the event log.
2498	*
2499	* @returns The number of entries in the event log.
2500	* @param pThis The IOMMU device state.
2501	*/
2502	static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
2503	{
2504	uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2505	uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2506	if (idxTail >= idxHead)
2507	return idxTail - idxHead;
2508
2509	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2510	return cMaxEvts - idxHead + idxTail;
2511	}
2512
2513
2514	/**
2515	* Gets the number of (unconsumed) commands in the command buffer.
2516	*
2517	* @returns The number of commands in the command buffer.
2518	* @param pThis The IOMMU device state.
2519	*/
2520	static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
2521	{
2522	uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2523	uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2524	if (idxTail >= idxHead)
2525	return idxTail - idxHead;
2526
2527	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
2528	return cMaxEvts - idxHead + idxTail;
2529	}
2530
2531
2532	DECLINLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
2533	{
2534	IOMMU_STATUS_T Status;
2535	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
2536	return Status;
2537	}
2538
2539
2540	DECLINLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
2541	{
2542	IOMMU_CTRL_T Ctrl;
2543	Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
2544	return Ctrl;
2545	}
2546
2547
2548	/**
2549	* Returns whether MSI is enabled for the IOMMU.
2550	*
2551	* @returns Whether MSI is enabled.
2552	* @param pDevIns The IOMMU device instance.
2553	*
2554	* @note There should be a PCIDevXxx function for this.
2555	*/
2556	static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
2557	{
2558	MSI_CAP_HDR_T MsiCapHdr;
2559	MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
2560	return MsiCapHdr.n.u1MsiEnable;
2561	}
2562
2563
2564	/**
2565	* Signals a PCI target abort.
2566	*
2567	* @param pDevIns The IOMMU device instance.
2568	*/
2569	static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
2570	{
2571	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2572	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2573	PDMPciDevSetStatus(pPciDev, u16Status);
2574	}
2575
2576
2577	/**
2578	* The IOMMU command thread.
2579	*
2580	* @returns VBox status code.
2581	* @param pDevIns The IOMMU device instance.
2582	* @param pThread The command thread.
2583	*/
2584	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2585	{
2586	RT_NOREF(pDevIns, pThread);
2587	}
2588
2589
2590	/**
2591	* Unblocks the command thread so it can respond to a state change.
2592	*
2593	* @returns VBox status code.
2594	* @param pDevIns The IOMMU device instance.
2595	* @param pThread The command thread.
2596	*/
2597	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2598	{
2599	RT_NOREF(pThread);
2600	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2601	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2602	}
2603
2604
2605	/**
2606	* Writes to a read-only register.
2607	*/
2608	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2609	{
2610	RT_NOREF(pDevIns, pThis, iReg, u64Value);
2611	Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
2612	return VINF_SUCCESS;
2613	}
2614
2615
2616	/**
2617	* Writes the Device Table Base Address Register.
2618	*/
2619	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2620	{
2621	RT_NOREF(pDevIns, iReg);
2622
2623	/* Mask out all unrecognized bits. */
2624	u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2625
2626	/* Update the register. */
2627	pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2628	return VINF_SUCCESS;
2629	}
2630
2631
2632	/**
2633	* Writes the Command Buffer Base Address Register.
2634	*/
2635	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2636	{
2637	RT_NOREF(pDevIns, iReg);
2638
2639	/*
2640	* While this is not explicitly specified like the event log base address register,
2641	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2642	* Inconsistent specs :/
2643	*/
2644	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2645	if (Status.n.u1CmdBufRunning)
2646	{
2647	Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2648	return VINF_SUCCESS;
2649	}
2650
2651	/* Mask out all unrecognized bits. */
2652	CMD_BUF_BAR_T CmdBufBaseAddr;
2653	CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2654
2655	/* Validate the length. */
2656	if (CmdBufBaseAddr.n.u4Len >= 8)
2657	{
2658	/* Update the register. */
2659	pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2660
2661	/*
2662	* Writing the command buffer base address, clears the command buffer head and tail pointers.
2663	* See AMD spec. 2.4 "Commands".
2664	*/
2665	pThis->CmdBufHeadPtr.u64 = 0;
2666	pThis->CmdBufTailPtr.u64 = 0;
2667	}
2668	else
2669	Log((IOMMU_LOG_PFX ": Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2670
2671	return VINF_SUCCESS;
2672	}
2673
2674
2675	/**
2676	* Writes the Event Log Base Address Register.
2677	*/
2678	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2679	{
2680	RT_NOREF(pDevIns, iReg);
2681
2682	/*
2683	* IOMMU behavior is undefined when software writes this register when event logging is running.
2684	* In our emulation, we ignore the write entirely.
2685	* See AMD IOMMU spec. "Event Log Base Address Register".
2686	*/
2687	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2688	if (Status.n.u1EvtLogRunning)
2689	{
2690	Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2691	return VINF_SUCCESS;
2692	}
2693
2694	/* Mask out all unrecognized bits. */
2695	u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2696	EVT_LOG_BAR_T EvtLogBaseAddr;
2697	EvtLogBaseAddr.u64 = u64Value;
2698
2699	/* Validate the length. */
2700	if (EvtLogBaseAddr.n.u4Len >= 8)
2701	{
2702	/* Update the register. */
2703	pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2704
2705	/*
2706	* Writing the event log base address, clears the event log head and tail pointers.
2707	* See AMD spec. 2.5 "Event Logging".
2708	*/
2709	pThis->EvtLogHeadPtr.u64 = 0;
2710	pThis->EvtLogTailPtr.u64 = 0;
2711	}
2712	else
2713	Log((IOMMU_LOG_PFX ": Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2714
2715	return VINF_SUCCESS;
2716	}
2717
2718
2719	/**
2720	* Writes the Control Register.
2721	*/
2722	static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2723	{
2724	RT_NOREF(pDevIns, iReg);
2725
2726	/* Mask out all unrecognized bits. */
2727	u64Value &= IOMMU_CTRL_VALID_MASK;
2728
2729	IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
2730	IOMMU_CTRL_T NewCtrl;
2731	NewCtrl.u64 = u64Value;
2732
2733	/* Enable or disable event logging when the bit transitions. */
2734	if (OldCtrl.n.u1EvtLogEn != NewCtrl.n.u1EvtLogEn)
2735	{
2736	if (NewCtrl.n.u1EvtLogEn)
2737	{
2738	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2739	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2740	}
2741	else
2742	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2743	}
2744
2745	/* Update the register. */
2746	ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2747
2748	/* Enable or disable command buffer processing when the bit transitions. */
2749	if (OldCtrl.n.u1CmdBufEn != NewCtrl.n.u1CmdBufEn)
2750	{
2751	if (NewCtrl.n.u1CmdBufEn)
2752	{
2753	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2754
2755	/* If the command buffer isn't empty, kick the command thread to start processing commands. */
2756	if (pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off)
2757	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2758	}
2759	else
2760	{
2761	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2762	/* Kick the command thread to stop processing commands. */
2763	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2764	}
2765	}
2766	}
2767
2768
2769	/**
2770	* Writes to the Excluse Range Base Address Register.
2771	*/
2772	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2773	{
2774	RT_NOREF(pDevIns, iReg);
2775	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2776	return VINF_SUCCESS;
2777	}
2778
2779
2780	/**
2781	* Writes to the Excluse Range Limit Register.
2782	*/
2783	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2784	{
2785	RT_NOREF(pDevIns, iReg);
2786	u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2787	u64Value \|= UINT64_C(0xfff);
2788	pThis->ExclRangeLimit.u64 = u64Value;
2789	return VINF_SUCCESS;
2790	}
2791
2792
2793	/**
2794	* Writes the Hardware Event Register (Hi).
2795	*/
2796	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2797	{
2798	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2799	RT_NOREF(pDevIns, iReg);
2800	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2801	pThis->HwEvtHi.u64 = u64Value;
2802	return VINF_SUCCESS;
2803	}
2804
2805
2806	/**
2807	* Writes the Hardware Event Register (Lo).
2808	*/
2809	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2810	{
2811	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2812	RT_NOREF(pDevIns, iReg);
2813	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2814	pThis->HwEvtLo = u64Value;
2815	return VINF_SUCCESS;
2816	}
2817
2818
2819	/**
2820	* Writes the Hardware Event Status Register.
2821	*/
2822	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2823	{
2824	RT_NOREF(pDevIns, iReg);
2825
2826	/* Mask out all unrecognized bits. */
2827	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2828
2829	/*
2830	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2831	* If the current status bits or the bits being written are both 0, we've nothing to do.
2832	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2833	*/
2834	uint64_t HwStatus = pThis->HwEvtStatus.u64;
2835	if (!(HwStatus & RT_BIT(0)))
2836	return VINF_SUCCESS;
2837	if (u64Value & HwStatus & RT_BIT_64(0))
2838	HwStatus &= ~RT_BIT_64(0);
2839	if (u64Value & HwStatus & RT_BIT_64(1))
2840	HwStatus &= ~RT_BIT_64(1);
2841
2842	/* Update the register. */
2843	pThis->HwEvtStatus.u64 = HwStatus;
2844	return VINF_SUCCESS;
2845	}
2846
2847
2848	/**
2849	* Writes the Device Table Segment Base Address Register.
2850	*/
2851	static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2852	{
2853	RT_NOREF(pDevIns);
2854
2855	/* Figure out which segment is being written. */
2856	uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2857	uint8_t const idxSegment = offSegment + 1;
2858	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2859
2860	/* Mask out all unrecognized bits. */
2861	u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2862	DEV_TAB_BAR_T DevTabSegBar;
2863	DevTabSegBar.u64 = u64Value;
2864
2865	/* Validate the size. */
2866	uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2867	uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2868	if (uSegSize <= uMaxSegSize)
2869	{
2870	/* Update the register. */
2871	pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2872	}
2873	else
2874	Log((IOMMU_LOG_PFX ": Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2875
2876	return VINF_SUCCESS;
2877	}
2878
2879
2880	/**
2881	* Writes the MSI Capability Header Register.
2882	*/
2883	static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2884	{
2885	RT_NOREF(pThis, iReg);
2886	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2887	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2888	MSI_CAP_HDR_T MsiCapHdr;
2889	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2890	MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2891	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2892	return VINF_SUCCESS;
2893	}
2894
2895
2896	/**
2897	* Writes the MSI Address (Lo) Register (32-bit).
2898	*/
2899	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2900	{
2901	RT_NOREF(pThis, iReg);
2902	Assert(!RT_HI_U32(u64Value));
2903	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2904	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2905	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & IOMMU_MSI_ADDR_VALID_MASK);
2906	return VINF_SUCCESS;
2907	}
2908
2909
2910	/**
2911	* Writes the MSI Address (Hi) Register (32-bit).
2912	*/
2913	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2914	{
2915	RT_NOREF(pThis, iReg);
2916	Assert(!RT_HI_U32(u64Value));
2917	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2918	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2919	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
2920	return VINF_SUCCESS;
2921	}
2922
2923
2924	/**
2925	* Writes the MSI Data Register (32-bit).
2926	*/
2927	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2928	{
2929	RT_NOREF(pThis, iReg);
2930	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2931	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2932	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & IOMMU_MSI_DATA_VALID_MASK);
2933	return VINF_SUCCESS;
2934	}
2935
2936
2937	/**
2938	* Writes the Command Buffer Head Pointer Register (32-bit).
2939	*/
2940	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2941	{
2942	RT_NOREF(pDevIns, iReg);
2943
2944	/*
2945	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
2946	* In our emulation, we ignore the write entirely.
2947	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2948	*/
2949	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2950	if (Status.n.u1CmdBufRunning)
2951	{
2952	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2953	return VINF_SUCCESS;
2954	}
2955
2956	/*
2957	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2958	* In our emulation, we ignore the write entirely.
2959	*/
2960	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2961	uint32_t const cbBuf = iommuAmdGetBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2962	Assert(cbBuf <= _512K);
2963	if (offBuf >= cbBuf)
2964	{
2965	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
2966	offBuf, cbBuf));
2967	return VINF_SUCCESS;
2968	}
2969
2970	/* Update the register. */
2971	pThis->CmdBufHeadPtr.au32[0] = offBuf;
2972
2973	LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
2974	return VINF_SUCCESS;
2975	}
2976
2977
2978	/**
2979	* Writes the Command Buffer Tail Pointer Register (32-bit).
2980	*/
2981	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2982	{
2983	RT_NOREF(pDevIns, iReg);
2984
2985	/*
2986	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2987	* In our emulation, we ignore the write entirely.
2988	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2989	*/
2990	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2991	uint32_t const cbBuf = iommuAmdGetBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2992	Assert(cbBuf <= _512K);
2993	if (offBuf >= cbBuf)
2994	{
2995	Log((IOMMU_LOG_PFX ": Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
2996	offBuf, cbBuf));
2997	return VINF_SUCCESS;
2998	}
2999
3000	/*
3001	* IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
3002	* head pointer after adding one or more commands to the buffer.
3003	*
3004	* However, we cannot enforce this strictly because it's legal for software to shrink the
3005	* command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
3006	* at 0). Software might even make the queue empty by making head and tail equal which is
3007	* allowed. I don't think we can or should try too hard to prevent software shooting itself
3008	* in the foot here. As long as we make sure the offset value is within the circular buffer
3009	* bounds (which we do by masking bits above) it should be sufficient.
3010	*/
3011	pThis->CmdBufTailPtr.au32[0] = offBuf;
3012
3013	LogFlow((IOMMU_LOG_PFX ": Set CmdBufTailPtr to %#RX32\n", offBuf));
3014	return VINF_SUCCESS;
3015	}
3016
3017
3018	/**
3019	* Writes the Event Log Head Pointer Register (32-bit).
3020	*/
3021	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3022	{
3023	RT_NOREF(pDevIns, iReg);
3024
3025	/*
3026	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3027	* In our emulation, we ignore the write entirely.
3028	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3029	*/
3030	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
3031	uint32_t const cbBuf = iommuAmdGetBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3032	Assert(cbBuf <= _512K);
3033	if (offBuf >= cbBuf)
3034	{
3035	Log((IOMMU_LOG_PFX ": Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3036	offBuf, cbBuf));
3037	return VINF_SUCCESS;
3038	}
3039
3040	/* Update the register. */
3041	pThis->EvtLogHeadPtr.au32[0] = offBuf;
3042
3043	LogFlow((IOMMU_LOG_PFX ": Set EvtLogHeadPtr to %#RX32\n", offBuf));
3044	return VINF_SUCCESS;
3045	}
3046
3047
3048	/**
3049	* Writes the Event Log Tail Pointer Register (32-bit).
3050	*/
3051	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3052	{
3053	RT_NOREF(pDevIns, iReg);
3054	NOREF(pThis);
3055
3056	/*
3057	* IOMMU behavior is undefined when software writes this register when the event log is running.
3058	* In our emulation, we ignore the write entirely.
3059	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3060	*/
3061	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3062	if (Status.n.u1EvtLogRunning)
3063	{
3064	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
3065	return VINF_SUCCESS;
3066	}
3067
3068	/*
3069	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3070	* In our emulation, we ignore the write entirely.
3071	*/
3072	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
3073	uint32_t const cbBuf = iommuAmdGetBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3074	Assert(cbBuf <= _512K);
3075	if (offBuf >= cbBuf)
3076	{
3077	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3078	offBuf, cbBuf));
3079	return VINF_SUCCESS;
3080	}
3081
3082	/* Update the register. */
3083	pThis->EvtLogTailPtr.au32[0] = offBuf;
3084
3085	LogFlow((IOMMU_LOG_PFX ": Set EvtLogTailPtr to %#RX32\n", offBuf));
3086	return VINF_SUCCESS;
3087	}
3088
3089
3090	/**
3091	* Writes the Status Register (64-bit).
3092	*/
3093	static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3094	{
3095	RT_NOREF(pDevIns, iReg);
3096
3097	/* Mask out all unrecognized bits. */
3098	u64Value &= IOMMU_STATUS_VALID_MASK;
3099
3100	/*
3101	* Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
3102	* Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
3103	*/
3104	IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
3105	uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
3106	uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
3107	uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
3108
3109	uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) \| fOldRoBits;
3110
3111	/* Update the register. */
3112	ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
3113	return VINF_SUCCESS;
3114	}
3115
3116
3117	#if 0
3118	/**
3119	* Table 0: Registers-access table.
3120	*/
3121	static const IOMMUREGACC g_aTable0Regs[] =
3122	{
3123
3124	};
3125
3126	/**
3127	* Table 1: Registers-access table.
3128	*/
3129	static const IOMMUREGACC g_aTable1Regs[] =
3130	{
3131	};
3132	#endif
3133
3134
3135	/**
3136	* Writes an IOMMU register (32-bit and 64-bit).
3137	*
3138	* @returns Strict VBox status code.
3139	* @param pDevIns The IOMMU device instance.
3140	* @param off MMIO byte offset to the register.
3141	* @param cb The size of the write access.
3142	* @param uValue The value being written.
3143	*
3144	* @thread EMT.
3145	*/
3146	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
3147	{
3148	Assert(off < IOMMU_MMIO_REGION_SIZE);
3149	Assert(cb == 4 \|\| cb == 8);
3150	Assert(!(off & (cb - 1)));
3151
3152	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3153	switch (off)
3154	{
3155	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
3156	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
3157	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
3158	case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
3159	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
3160	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
3161	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3162
3163	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3164	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
3165	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
3166	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
3167
3168	case IOMMU_MMIO_OFF_GALOG_BAR:
3169	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3170
3171	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
3172	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3173
3174	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3175	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3176	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3177	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3178	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3179	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3180	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
3181
3182	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
3183	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
3184	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3185
3186	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
3187	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3188	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3189	{
3190	VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
3191	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3192	return rcStrict;
3193	uValue >>= 32;
3194	RT_FALL_THRU();
3195	}
3196	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
3197	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3198	{
3199	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
3200	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3201	return rcStrict;
3202	uValue >>= 32;
3203	RT_FALL_THRU();
3204	}
3205	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
3206	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3207
3208	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3209
3210	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
3211	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
3212	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3213
3214	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
3215	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
3216	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
3217	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
3218	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
3219	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
3220	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
3221	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
3222	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
3223	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
3224	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
3225	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3226
3227	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3228
3229	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
3230	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
3231	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
3232	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
3233
3234	case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
3235
3236	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
3237	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
3238
3239	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
3240	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
3241
3242	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
3243	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
3244
3245	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
3246	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3247
3248	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
3249	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
3250	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
3251
3252	/* Not implemented. */
3253	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3254	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3255	{
3256	Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
3257	(off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3258	return VINF_SUCCESS;
3259	}
3260
3261	/* Unknown. */
3262	default:
3263	{
3264	Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
3265	return VINF_SUCCESS;
3266	}
3267	}
3268	}
3269
3270
3271	/**
3272	* Reads an IOMMU register (64-bit) given its MMIO offset.
3273	*
3274	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
3275	* boundary include the lower half of the subsequent register.
3276	*
3277	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
3278	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
3279	* software will only perform 32-bit reads on those 32-bit registers that are
3280	* aligned on 8-byte boundaries.
3281	*
3282	* @returns Strict VBox status code.
3283	* @param pDevIns The IOMMU device instance.
3284	* @param off The MMIO offset of the register in bytes.
3285	* @param puResult Where to store the value being read.
3286	*
3287	* @thread EMT.
3288	*/
3289	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
3290	{
3291	Assert(off < IOMMU_MMIO_REGION_SIZE);
3292	Assert(!(off & 7) \|\| !(off & 3));
3293
3294	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3295	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3296	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3297
3298	/** @todo IOMMU: fine-grained locking? */
3299	uint64_t uReg;
3300	switch (off)
3301	{
3302	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
3303	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
3304	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
3305	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
3306	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
3307	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
3308	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
3309
3310	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
3311	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
3312	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
3313	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
3314
3315	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
3316	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
3317
3318	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
3319	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
3320
3321	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3322	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3323	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3324	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3325	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3326	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3327	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
3328	{
3329	uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
3330	uint8_t const idxDevTabSeg = offDevTabSeg + 1;
3331	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3332	uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
3333	break;
3334	}
3335
3336	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
3337	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
3338	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
3339
3340	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MsiMiscInfo.u64; break;
3341	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MsiMiscInfo.au32[1]; break;
3342	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3343	{
3344	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3345	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3346	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
3347	break;
3348	}
3349	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
3350	{
3351	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3352	break;
3353	}
3354	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3355	{
3356	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3357	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3358	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
3359	break;
3360	}
3361	case IOMMU_MMIO_OFF_MSI_DATA:
3362	{
3363	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3364	break;
3365	}
3366	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
3367	{
3368	/*
3369	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
3370	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
3371	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
3372	* 0 for this register.
3373	*/
3374	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
3375	break;
3376	}
3377
3378	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
3379
3380	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
3381	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
3382	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
3383
3384	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
3385	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
3386	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
3387	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
3388	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
3389	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
3390	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
3391	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
3392	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
3393	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
3394	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
3395	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
3396
3397	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
3398
3399	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
3400	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
3401	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
3402	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
3403
3404	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
3405
3406	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
3407	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
3408
3409	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
3410	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
3411
3412	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
3413	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
3414
3415	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
3416	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
3417
3418	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
3419	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
3420	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
3421
3422	/* Not implemented. */
3423	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3424	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3425	{
3426	Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3427	uReg = 0;
3428	break;
3429	}
3430
3431	/* Unknown. */
3432	default:
3433	{
3434	Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
3435	uReg = 0;
3436	return VINF_IOM_MMIO_UNUSED_00;
3437	}
3438	}
3439
3440	*puResult = uReg;
3441	return VINF_SUCCESS;
3442	}
3443
3444
3445	/**
3446	* Raises the MSI interrupt for the IOMMU device.
3447	*
3448	* @param pDevIns The IOMMU device instance.
3449	*
3450	* @thread Any.
3451	*/
3452	static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
3453	{
3454	if (iommuAmdIsMsiEnabled(pDevIns))
3455	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
3456	}
3457
3458
3459	/**
3460	* Clears the MSI interrupt for the IOMMU device.
3461	*
3462	* @param pDevIns The IOMMU device instance.
3463	*
3464	* @thread Any.
3465	*/
3466	static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
3467	{
3468	if (iommuAmdIsMsiEnabled(pDevIns))
3469	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3470	}
3471
3472
3473	/**
3474	* Writes an entry to the event log in memory.
3475	*
3476	* @returns VBox status code.
3477	* @param pDevIns The IOMMU device instance.
3478	* @param pEvent The event to log.
3479	*
3480	* @thread Any.
3481	*/
3482	static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3483	{
3484	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3485	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3486
3487	/** @todo IOMMU: Consider locking here. */
3488
3489	/* Check if event logging is active and the log has not overflowed. */
3490	if ( Status.n.u1EvtLogRunning
3491	&& !Status.n.u1EvtOverflow)
3492	{
3493	uint32_t const cbEvt = sizeof(*pEvent);
3494
3495	/* Get the offset we need to write the event to in memory (circular buffer offset). */
3496	uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3497	Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3498
3499	/* Ensure we have space in the event log. */
3500	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3501	uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3502	if (cEvts + 1 < cMaxEvts)
3503	{
3504	/* Write the event log entry to memory. */
3505	RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3506	RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3507	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3508	if (RT_FAILURE(rc))
3509	Log((IOMMU_LOG_PFX ": Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3510
3511	/* Increment the event log tail pointer. */
3512	uint32_t const cbEvtLog = iommuAmdGetBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3513	pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3514
3515	/* Indicate that an event log entry was written. */
3516	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3517
3518	/* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3519	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3520	if (Ctrl.n.u1EvtIntrEn)
3521	iommuAmdRaiseMsiInterrupt(pDevIns);
3522	}
3523	else
3524	{
3525	/* Indicate that the event log has overflowed. */
3526	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3527
3528	/* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3529	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3530	if (Ctrl.n.u1EvtIntrEn)
3531	iommuAmdRaiseMsiInterrupt(pDevIns);
3532	}
3533	}
3534	}
3535
3536
3537	/**
3538	* Sets an event in the hardware error registers.
3539	*
3540	* @param pDevIns The IOMMU device instance.
3541	* @param pEvent The event.
3542	*
3543	* @thread Any.
3544	*/
3545	static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3546	{
3547	/** @todo IOMMU: We should probably lock the device here */
3548	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3549	if (pThis->ExtFeat.n.u1HwErrorSup)
3550	{
3551	if (pThis->HwEvtStatus.n.u1Valid)
3552	pThis->HwEvtStatus.n.u1Overflow = 1;
3553	pThis->HwEvtStatus.n.u1Valid = 1;
3554	pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3555	pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3556	Assert(pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR);
3557	}
3558	}
3559
3560
3561	/**
3562	* Initializes a DEV_TAB_HARDWARE_ERROR event.
3563	*
3564	* @param uDevId The device ID.
3565	* @param GCPhysDte The system physical address of the failed device table
3566	* access.
3567	* @param enmOp The IOMMU operation being performed.
3568	* @param pEvtDevTabHwErr Where to store the initialized event.
3569	*
3570	* @thread Any.
3571	*/
3572	static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3573	PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3574	{
3575	memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3576	pEvtDevTabHwErr->n.u16DevId = uDevId;
3577	pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3578	/** @todo r=ramshankar: Any other transaction type that can set read/write bit? */
3579	pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3580	pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3581	pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3582	pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3583	pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3584	}
3585
3586
3587	/**
3588	* Raises a DEV_TAB_HARDWARE_ERROR event.
3589	*
3590	* @param pDevIns The IOMMU device instance.
3591	* @param uDevId The device ID.
3592	* @param enmOp The IOMMU operation being performed.
3593	* @param pEvtDevTabHwErr The device table hardware error event.
3594	* @param enmEvtType The device table hardware error event type.
3595	*/
3596	static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr,
3597	EVT_DEV_TAB_HW_ERROR_TYPE_T enmEvtType)
3598	{
3599	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3600	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3601	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3602	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3603	if (enmOp != IOMMUOP_CMD)
3604	iommuAmdSetPciTargetAbort(pDevIns);
3605
3606	Log((IOMMU_LOG_PFX ": Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u enmType=%u\n",
3607	pEvtDevTabHwErr->n.u16DevId, pEvtDevTabHwErr->n.u64Addr, enmOp, enmEvtType));
3608	NOREF(enmEvtType);
3609	}
3610
3611
3612	/**
3613	* Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3614	*
3615	* @param uDevId The device ID.
3616	* @param uIova The I/O virtual address.
3617	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3618	* event was caused by an invalid level encoding in the
3619	* DTE.
3620	* @param enmOp The IOMMU operation being performed.
3621	* @param pEvtIllegalDte Where to store the initialized event.
3622	*/
3623	static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3624	PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3625	{
3626	memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3627	pEvtIllegalDte->n.u16DevId = uDevId;
3628	pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3629	pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3630	pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3631	pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3632	pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3633	pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3634	/** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3635	* IOMMU spec here but not for this field for I/O page fault event. */
3636	Assert(!(uIova & UINT64_C(0x3)));
3637	}
3638
3639
3640	/**
3641	* Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3642	*
3643	* @param pDevIns The IOMMU instance data.
3644	* @param enmOp The IOMMU operation being performed.
3645	* @param pEvtIllegalDte The illegal device table entry event.
3646	* @param enmEvtType The illegal DTE event type.
3647	*/
3648	static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3649	EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3650	{
3651	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3652	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3653	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3654	if (enmOp != IOMMUOP_CMD)
3655	iommuAmdSetPciTargetAbort(pDevIns);
3656
3657	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3658	pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3659	NOREF(enmEvtType);
3660	}
3661
3662
3663	/**
3664	* Initializes an IO_PAGE_FAULT event.
3665	*
3666	* @param uDevId The device ID.
3667	* @param uDomainId The domain ID.
3668	* @param uIova The I/O virtual address being accessed.
3669	* @param fPresent Transaction to a page marked as present (including
3670	* DTE.V=1) or interrupt marked as remapped
3671	* (IRTE.RemapEn=1).
3672	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3673	* the I/O page fault was caused by invalid level
3674	* encoding.
3675	* @param enmOp The IOMMU operation being performed.
3676	* @param pEvtIoPageFault Where to store the initialized event.
3677	*/
3678	static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3679	IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3680	{
3681	memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3682	pEvtIoPageFault->n.u16DevId = uDevId;
3683	//pEvtIoPageFault->n.u4PasidHi = 0;
3684	pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
3685	//pEvtIoPageFault->n.u1GuestOrNested = 0;
3686	//pEvtIoPageFault->n.u1NoExecute = 0;
3687	//pEvtIoPageFault->n.u1User = 0;
3688	pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3689	pEvtIoPageFault->n.u1Present = fPresent;
3690	pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3691	//pEvtIoPageFault->n.u1PermIndicator = 0;
3692	pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3693	pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3694	pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3695	pEvtIoPageFault->n.u64Addr = uIova;
3696	}
3697
3698
3699	/**
3700	* Raises an IO_PAGE_FAULT event.
3701	*
3702	* @param pDevIns The IOMMU instance data.
3703	* @param pDte The device table entry. Optional, can be NULL
3704	* depending on @a enmOp.
3705	* @param pIrte The interrupt remapping table entry. Optional, can
3706	* be NULL depending on @a enmOp.
3707	* @param enmOp The IOMMU operation being performed.
3708	* @param pEvtIoPageFault The I/O page fault event.
3709	* @param enmEvtType The I/O page fault event type.
3710	*
3711	* @thread Any.
3712	*/
3713	static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3714	PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3715	{
3716	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3717	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3718
3719	bool fSuppressEvtLogging = false;
3720	if ( enmOp == IOMMUOP_MEM_READ
3721	\|\| enmOp == IOMMUOP_MEM_WRITE)
3722	{
3723	if ( pDte
3724	&& pDte->n.u1Valid)
3725	{
3726	fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
3727	/** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
3728	* suppression. Perhaps will be possible when we complete IOTLB/cache
3729	* handling. */
3730	}
3731	}
3732	else if (enmOp == IOMMUOP_INTR_REQ)
3733	{
3734	if ( pDte
3735	&& pDte->n.u1IntrMapValid)
3736	fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
3737
3738	if ( !fSuppressEvtLogging
3739	&& pIrte)
3740	fSuppressEvtLogging = pIrte->n.u1SuppressPf;
3741	}
3742	/* else: Events are never suppressed for commands. */
3743
3744	switch (enmEvtType)
3745	{
3746	case kIoPageFaultType_ReadProtect:
3747	case kIoPageFaultType_WriteProtect:
3748	case kIoPageFaultType_ExecuteProtect:
3749	{
3750	/* Cannot be triggered by a command. */
3751	Assert(enmOp != IOMMUOP_CMD);
3752	RT_FALL_THRU();
3753	}
3754	case kIoPageFaultType_DteRsvdPagingMode:
3755	case kIoPageFaultType_PteInvalidPageSize:
3756	case kIoPageFaultType_PteInvalidLvlEncoding:
3757	case kIoPageFaultType_InvalidSkippedPageLvl:
3758	case kIoPageFaultType_PteRsvdNotZero:
3759	case kIoPageFaultType_PteValidNotSet:
3760	case kIoPageFaultType_DteTranslationDisabled:
3761	case kIoPageFaultType_PasidInvalidRange:
3762	{
3763	/*
3764	* For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3765	* create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
3766	*/
3767	if (enmOp != IOMMUOP_TRANSLATE_REQ)
3768	{
3769	if (!fSuppressEvtLogging)
3770	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3771	if (enmOp != IOMMUOP_CMD)
3772	iommuAmdSetPciTargetAbort(pDevIns);
3773	}
3774	break;
3775	}
3776
3777	case kIoPageFaultType_UserSupervisor:
3778	{
3779	/* Access is blocked and only creates an event log entry. */
3780	if (!fSuppressEvtLogging)
3781	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3782	break;
3783	}
3784
3785	case kIoPageFaultType_IrteAddrInvalid:
3786	case kIoPageFaultType_IrteRsvdNotZero:
3787	case kIoPageFaultType_IrteRemapEn:
3788	case kIoPageFaultType_IrteRsvdIntType:
3789	case kIoPageFaultType_IntrReqAborted:
3790	case kIoPageFaultType_IntrWithPasid:
3791	{
3792	/* Only trigerred by interrupt requests. */
3793	Assert(enmOp == IOMMUOP_INTR_REQ);
3794	if (!fSuppressEvtLogging)
3795	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3796	iommuAmdSetPciTargetAbort(pDevIns);
3797	break;
3798	}
3799
3800	case kIoPageFaultType_SmiFilterMismatch:
3801	{
3802	/* Not supported and probably will never be, assert. */
3803	AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3804	break;
3805	}
3806
3807	case kIoPageFaultType_DevId_Invalid:
3808	{
3809	/* Cannot be triggered by a command. */
3810	Assert(enmOp != IOMMUOP_CMD);
3811	Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3812	if (!fSuppressEvtLogging)
3813	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3814	if ( enmOp == IOMMUOP_MEM_READ
3815	\|\| enmOp == IOMMUOP_MEM_WRITE)
3816	iommuAmdSetPciTargetAbort(pDevIns);
3817	break;
3818	}
3819	}
3820	}
3821
3822
3823	/**
3824	* Initializes an IOTLB entry.
3825	*
3826	* @param GCPhysSpa The translated system physical address.
3827	* @param cShift The number of offset bits in the system physical address.
3828	* @param fIoPerm The I/O access permissions (IOMMU_IO_PERM_XXX).
3829	* @param pIotlbe Where to store the initialized IOTLB entry.
3830	*/
3831	static void iommuAmdInitIotlbe(RTGCPHYS GCPhysSpa, uint8_t cShift, uint8_t fIoPerm, PIOTLBE_T pIotlbe)
3832	{
3833	pIotlbe->uMagic = IOMMU_IOTLBE_MAGIC;
3834	pIotlbe->uRsvd0 = 0;
3835	pIotlbe->fIoPerm = fIoPerm;
3836	pIotlbe->cShift = cShift;
3837	pIotlbe->GCPhysSpa = GCPhysSpa;
3838	}
3839
3840
3841	/**
3842	* Updates an IOTLB entry.
3843	*
3844	* @param GCPhysSpa The translated system physical address.
3845	* @param cShift The number of offset bits in the system physical address.
3846	* @param fIoPerm The I/O access permissions (IOMMU_IO_PERM_XXX).
3847	* @param pIotlbe The IOTLB entry to update.
3848	*/
3849	static void iommuAmdUpdateIotlbe(RTGCPHYS GCPhysSpa, uint8_t cShift, uint8_t fIoPerm, PIOTLBE_T pIotlbe)
3850	{
3851	Assert(pIotlbe->uMagic == IOMMU_IOTLBE_MAGIC);
3852	pIotlbe->fIoPerm = fIoPerm;
3853	pIotlbe->cShift = cShift;
3854	pIotlbe->GCPhysSpa = GCPhysSpa;
3855	}
3856
3857
3858	/**
3859	* Returns whether the I/O virtual address is to be excluded from translation and
3860	* permission checks.
3861	*
3862	* @returns @c true if the DVA is excluded, @c false otherwise.
3863	* @param pThis The IOMMU device state.
3864	* @param pDte The device table entry.
3865	* @param uIova The I/O virtual address.
3866	*
3867	* @remarks Ensure the exclusion range is enabled prior to calling this function.
3868	*
3869	* @thread Any.
3870	*/
3871	static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
3872	{
3873	/* Ensure the exclusion range is enabled. */
3874	Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
3875
3876	/* Check if the IOVA falls within the exclusion range. */
3877	uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
3878	uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
3879	if (uIovaExclLast - uIova >= uIovaExclFirst)
3880	{
3881	/* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
3882	if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
3883	\|\| pDte->n.u1AllowExclusion)
3884	return true;
3885	}
3886	return false;
3887	}
3888
3889
3890	/**
3891	* Reads a device table entry from guest memory given the device ID.
3892	*
3893	* @returns VBox status code.
3894	* @param pDevIns The IOMMU device instance.
3895	* @param uDevId The device ID.
3896	* @param enmOp The IOMMU operation being performed.
3897	* @param pDte Where to store the device table entry.
3898	*
3899	* @thread Any.
3900	*/
3901	static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
3902	{
3903	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3904	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3905
3906	uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
3907	Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
3908
3909	uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
3910	Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3911
3912	RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3913	uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
3914	RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3915
3916	Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3917	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3918	if (RT_FAILURE(rc))
3919	{
3920	Log((IOMMU_LOG_PFX ": Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3921
3922	EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3923	iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
3924	iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr, kDevTabHwErrType_TargetAbort);
3925	}
3926
3927	return rc;
3928	}
3929
3930
3931	/**
3932	* Walks the I/O page table(s) to translate the I/O virtual address to a system
3933	* physical address.
3934	*
3935	* @returns VBox status code.
3936	* @param pDevIns The IOMMU device instance.
3937	* @param uIova The I/O virtual address to translate.
3938	* @param uDevId The device ID.
3939	* @param cbAccess The size of the access.
3940	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
3941	* permissions for the access being made.
3942	* @param pDte The device table entry.
3943	* @param enmOp The IOMMU operation being performed.
3944	* @param pIotlbe The IOTLB entry to update with the results of the
3945	* translation.
3946	*
3947	* @thread Any.
3948	*/
3949	static int iommuAmdWalkIoPageTables(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
3950	PCDTE_T pDte, IOMMUOP enmOp, PIOTLBE_T pIotlbe)
3951	{
3952	NOREF(cbAccess);
3953	Assert(pDte->n.u1Valid);
3954
3955	/* If the translation is not valid, raise an I/O page fault. */
3956	if (pDte->n.u1TranslationValid)
3957	{ /* likely */ }
3958	else
3959	{
3960	/** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3961	* doesn't explicitly say whether an I/O page fault is raised. From other
3962	* places in the spec. it seems early page walk terminations (starting with
3963	* the DTE) return the state computed so far and raises an I/O page fault. So
3964	* returning an invalid translation rather than skipping translation. */
3965	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3966	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
3967	enmOp, &EvtIoPageFault);
3968	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3969	kIoPageFaultType_DteTranslationDisabled);
3970	iommuAmdUpdateIotlbe(NIL_RTGCPHYS, 0 /* cShift */, IOMMU_IO_PERM_NONE, pIotlbe);
3971	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3972	}
3973
3974	/* If the page table level (depth) is 0, translation is disabled and access is controlled by the permission bits. */
3975	uint8_t const uLevel = pDte->n.u3Mode;
3976	if (uLevel == 0)
3977	{
3978	uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3979	if ((fAccess & fDtePerm) != fAccess)
3980	{
3981	Log((IOMMU_LOG_PFX ": Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
3982	return VERR_IOMMU_ADDR_ACCESS_DENIED;
3983	}
3984	iommuAmdUpdateIotlbe(uIova, 0 /* cShift */, fDtePerm, pIotlbe);
3985	return VINF_SUCCESS;
3986	}
3987
3988	/* If the page table level (depth) exceeds the allowed host-address translation levels, page walk terminates. */
3989	if (uLevel > IOMMU_MAX_HOST_PT_LEVEL)
3990	{
3991	/** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3992	* raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3993	* I'm just going with I/O page fault. */
3994	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3995	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */, enmOp,
3996	&EvtIoPageFault);
3997	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,kIoPageFaultType_PteInvalidLvlEncoding);
3998
3999	iommuAmdUpdateIotlbe(NIL_RTGCPHYS, 0 /* cShift */, IOMMU_IO_PERM_NONE, pIotlbe);
4000	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4001	}
4002
4003	/* Traverse the I/O page table starting with the validated DTE. */
4004	PIOPTENTITY_T pPtEntity = (PIOPTENTITY_T)&pDte->au64[0];
4005	for (;;)
4006	{
4007	/* If the page entity isn't present or has insufficient permissions for the access being made, raise an I/O page fault. */
4008	uint8_t const fPtePerm = (pPtEntity->u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4009	if ( !pPtEntity->n.u1Present
4010	\|\| (fAccess & fPtePerm) != fAccess)
4011	{
4012	EVT_IO_PAGE_FAULT_TYPE_T const EvtIoPageFaultType = (fAccess & IOMMU_IO_PERM_WRITE) ? kIoPageFaultType_WriteProtect
4013	: kIoPageFaultType_ReadProtect;
4014	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4015	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4016	enmOp, &EvtIoPageFault);
4017	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, EvtIoPageFaultType);
4018	iommuAmdUpdateIotlbe(NIL_RTGCPHYS, 0 /* cShift */, IOMMU_IO_PERM_NONE, pIotlbe);
4019	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4020	}
4021
4022	/** @todo IOMMU: rest of page walk. */
4023	}
4024
4025	return VERR_NOT_IMPLEMENTED;
4026	}
4027
4028	/**
4029	* Looks up an I/O virtual address from the device table(s).
4030	*
4031	* @returns VBox status code.
4032	* @param pDevIns The IOMMU instance data.
4033	* @param uDevId The device ID.
4034	* @param uIova The I/O virtual address to lookup.
4035	* @param cbAccess The size of the access.
4036	* @param enmOp The IOMMU operation being performed.
4037	* @param pIotlbe The IOTLBE to update.
4038	*
4039	* @remarks Only the translated address and permission bits are updated in @a
4040	* pIotlbe when this function returns VINF_SUCCESS. Caller is expected to
4041	* know and fill in the rest already.
4042	*
4043	* @thread Any.
4044	*/
4045	static int iommuAmdLookupDeviceTables(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, IOMMUOP enmOp,
4046	PIOTLBE_T pIotlbe)
4047	{
4048	Assert(pIotlbe->uMagic == IOMMU_IOTLBE_MAGIC);
4049	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4050
4051	/* Read the device table entry from memory. */
4052	DTE_T Dte;
4053	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4054	if (RT_SUCCESS(rc))
4055	{
4056	/* If the DTE is not valid, addresses are forwarded without translation */
4057	if (Dte.n.u1Valid)
4058	{ /* likely */ }
4059	else
4060	{
4061	iommuAmdUpdateIotlbe(uIova, 0 /* cShift */, IOMMU_IO_PERM_READ_WRITE, pIotlbe);
4062	return VINF_SUCCESS;
4063	}
4064
4065	/* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4066	uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4067	uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4068	if (RT_LIKELY( !fRsvd0
4069	&& !fRsvd1))
4070	{ /* likely */ }
4071	else
4072	{
4073	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4074	EVT_ILLEGAL_DTE_T Event;
4075	iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4076	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4077	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4078	}
4079
4080	/* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
4081	if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
4082	\|\| !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
4083	{ /* likely */ }
4084	else
4085	{
4086	iommuAmdUpdateIotlbe(uIova, 0 /* cShift */, IOMMU_IO_PERM_READ_WRITE, pIotlbe);
4087	return VINF_SUCCESS;
4088	}
4089
4090	/* Walk the I/O page tables to translate and get permission bits for the IOVA access. */
4091	rc = iommuAmdWalkIoPageTables(pDevIns, uDevId, uIova, cbAccess, IOMMU_IO_PERM_READ, &Dte, enmOp, pIotlbe);
4092	if (RT_FAILURE(rc))
4093	Log((IOMMU_LOG_PFX ": I/O page table walk failed. rc=%Rrc\n"));
4094
4095	return rc;
4096	}
4097
4098	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4099	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4100	}
4101
4102
4103	/**
4104	* Memory read request from a device.
4105	*
4106	* @returns VBox status code.
4107	* @param pDevIns The IOMMU device instance.
4108	* @param uDevId The device ID (bus, device, function).
4109	* @param uIova The I/O virtual address being read.
4110	* @param cbRead The number of bytes being read.
4111	* @param pGCPhysSpa Where to store the translated system physical address.
4112	*
4113	* @thread Any.
4114	*/
4115	static int iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, PRTGCPHYS pGCPhysSpa)
4116	{
4117	Assert(pDevIns);
4118	Assert(pGCPhysSpa);
4119	Assert(cbRead > 0);
4120
4121	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4122
4123	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4124	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4125	if (Ctrl.n.u1IommuEn)
4126	{
4127	IOTLBE_T Iotlbe;
4128	iommuAmdInitIotlbe(NIL_RTGCPHYS, 0 /* cShift */, IOMMU_IO_PERM_NONE, &Iotlbe);
4129
4130	/** @todo IOMMU: IOTLB cache lookup. */
4131
4132	/* Lookup the IOVA from the device tables. */
4133	int rc = iommuAmdLookupDeviceTables(pDevIns, uDevId, uIova, cbRead, IOMMUOP_MEM_READ, &Iotlbe);
4134
4135	/** @todo IOMMU: Cache translation. */
4136
4137	*pGCPhysSpa = Iotlbe.GCPhysSpa;
4138	return rc;
4139	}
4140
4141	*pGCPhysSpa = uIova;
4142	return VINF_SUCCESS;
4143	}
4144
4145
4146	/**
4147	* Memory write request from a device.
4148	*
4149	* @returns VBox status code.
4150	* @param pDevIns The IOMMU device instance.
4151	* @param uDevId The device ID (bus, device, function).
4152	* @param uIova The I/O virtual address being written.
4153	* @param cbWrite The number of bytes being written.
4154	* @param pGCPhysSpa Where to store the translated physical address.
4155	*
4156	* @thread Any.
4157	*/
4158	static int iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite, PRTGCPHYS pGCPhysSpa)
4159	{
4160	RT_NOREF(pDevIns, uDevId, uIova, cbWrite, pGCPhysSpa);
4161	return VERR_NOT_IMPLEMENTED;
4162	}
4163
4164
4165	/**
4166	* @callback_method_impl{FNIOMMMIONEWWRITE}
4167	*/
4168	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
4169	{
4170	NOREF(pvUser);
4171	Assert(cb == 4 \|\| cb == 8);
4172	Assert(!(off & (cb - 1)));
4173
4174	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
4175	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
4176	}
4177
4178
4179	/**
4180	* @callback_method_impl{FNIOMMMIONEWREAD}
4181	*/
4182	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
4183	{
4184	NOREF(pvUser);
4185	Assert(cb == 4 \|\| cb == 8);
4186	Assert(!(off & (cb - 1)));
4187
4188	uint64_t uResult;
4189	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
4190	if (cb == 8)
4191	(uint64_t )pv = uResult;
4192	else
4193	(uint32_t )pv = (uint32_t)uResult;
4194
4195	return rcStrict;
4196	}
4197
4198
4199	# ifdef IN_RING3
4200	/**
4201	* @callback_method_impl{FNPCICONFIGREAD}
4202	*/
4203	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4204	unsigned cb, uint32_t *pu32Value)
4205	{
4206	/** @todo IOMMU: PCI config read stat counter. */
4207	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4208	Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
4209	VBOXSTRICTRC_VAL(rcStrict)));
4210	return rcStrict;
4211	}
4212
4213
4214	/**
4215	* @callback_method_impl{FNPCICONFIGWRITE}
4216	*/
4217	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4218	unsigned cb, uint32_t u32Value)
4219	{
4220	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4221
4222	/*
4223	* Discard writes to read-only registers that are specific to the IOMMU.
4224	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
4225	* See PCI spec. 6.1. "Configuration Space Organization".
4226	*/
4227	switch (uAddress)
4228	{
4229	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
4230	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
4231	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
4232	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
4233	{
4234	Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
4235	return VINF_SUCCESS;
4236	}
4237	}
4238
4239	IOMMU_LOCK_RET(pDevIns, pThis, VERR_IGNORED);
4240
4241	VBOXSTRICTRC rcStrict;
4242	switch (uAddress)
4243	{
4244	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
4245	{
4246	if (pThis->IommuBar.n.u1Enable)
4247	{
4248	rcStrict = VINF_SUCCESS;
4249	Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
4250	break;
4251	}
4252
4253	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
4254	if (pThis->IommuBar.n.u1Enable)
4255	{
4256	Assert(pThis->hMmio == NIL_IOMMMIOHANDLE);
4257	Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
4258	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
4259	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
4260	if (RT_FAILURE(rcStrict))
4261	Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
4262	}
4263	break;
4264	}
4265
4266	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
4267	{
4268	if (!pThis->IommuBar.n.u1Enable)
4269	pThis->IommuBar.au32[1] = u32Value;
4270	else
4271	{
4272	rcStrict = VINF_SUCCESS;
4273	Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
4274	}
4275	break;
4276	}
4277
4278	case IOMMU_PCI_OFF_MSI_CAP_HDR:
4279	{
4280	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
4281	RT_FALL_THRU();
4282	}
4283
4284	default:
4285	{
4286	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4287	break;
4288	}
4289	}
4290
4291	IOMMU_UNLOCK(pDevIns, pThis);
4292
4293	Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
4294	return rcStrict;
4295	}
4296
4297
4298	/**
4299	* @callback_method_impl{FNDBGFHANDLERDEV}
4300	*/
4301	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4302	{
4303	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4304	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4305	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4306
4307	LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
4308	bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
4309
4310	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
4311	/* Device Table Base Addresses (all segments). */
4312	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4313	{
4314	DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
4315	pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
4316	if (fVerbose)
4317	{
4318	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
4319	IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
4320	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
4321	}
4322	}
4323	/* Command Buffer Base Address Register. */
4324	{
4325	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
4326	uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
4327	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4328	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4329	pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
4330	if (fVerbose)
4331	{
4332	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
4333	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4334	cEntries, cbBuffer);
4335	}
4336	}
4337	/* Event Log Base Address Register. */
4338	{
4339	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
4340	uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
4341	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4342	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4343	pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
4344	if (fVerbose)
4345	{
4346	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4347	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4348	cEntries, cbBuffer);
4349	}
4350	}
4351	/* IOMMU Control Register. */
4352	{
4353	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
4354	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
4355	if (fVerbose)
4356	{
4357	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
4358	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
4359	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
4360	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4361	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4362	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
4363	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
4364	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
4365	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
4366	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
4367	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
4368	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
4369	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
4370	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
4371	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
4372	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
4373	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
4374	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
4375	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
4376	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
4377	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
4378	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
4379	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
4380	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
4381	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
4382	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
4383	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
4384	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
4385	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
4386	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
4387	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
4388	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
4389	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
4390	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
4391	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
4392	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
4393	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
4394	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
4395	}
4396	}
4397	/* Exclusion Base Address Register. */
4398	{
4399	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
4400	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
4401	if (fVerbose)
4402	{
4403	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
4404	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
4405	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
4406	ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
4407	}
4408	}
4409	/* Exclusion Range Limit Register. */
4410	{
4411	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
4412	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
4413	if (fVerbose)
4414	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
4415	}
4416	/* Extended Feature Register. */
4417	{
4418	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
4419	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
4420	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
4421	if (fVerbose)
4422	{
4423	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
4424	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
4425	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
4426	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
4427	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
4428	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
4429	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
4430	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
4431	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
4432	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
4433	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
4434	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
4435	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
4436	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
4437	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
4438	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
4439	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
4440	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
4441	pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
4442	g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
4443	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
4444	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
4445	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
4446	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
4447	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
4448	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
4449	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
4450	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
4451	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
4452	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
4453	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
4454	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
4455	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
4456	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
4457	}
4458	}
4459	/* PPR Log Base Address Register. */
4460	{
4461	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
4462	uint8_t const uEncodedLen = PprLogBar.n.u4Len;
4463	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4464	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4465	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
4466	if (fVerbose)
4467	{
4468	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4469	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4470	cEntries, cbBuffer);
4471	}
4472	}
4473	/* Hardware Event (Hi) Register. */
4474	{
4475	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4476	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4477	if (fVerbose)
4478	{
4479	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4480	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4481	}
4482	}
4483	/* Hardware Event (Lo) Register. */
4484	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4485	/* Hardware Event Status. */
4486	{
4487	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4488	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4489	if (fVerbose)
4490	{
4491	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4492	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4493	}
4494	}
4495	/* Guest Virtual-APIC Log Base Address Register. */
4496	{
4497	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4498	uint8_t const uEncodedLen = GALogBar.n.u4Len;
4499	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4500	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4501	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4502	if (fVerbose)
4503	{
4504	pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4505	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4506	cEntries, cbBuffer);
4507	}
4508	}
4509	/* Guest Virtual-APIC Log Tail Address Register. */
4510	{
4511	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4512	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4513	if (fVerbose)
4514	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4515	}
4516	/* PPR Log B Base Address Register. */
4517	{
4518	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4519	uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4520	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4521	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4522	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4523	if (fVerbose)
4524	{
4525	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4526	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4527	cEntries, cbBuffer);
4528	}
4529	}
4530	/* Event Log B Base Address Register. */
4531	{
4532	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4533	uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4534	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4535	uint32_t const cbBuffer = iommuAmdGetBufLength(uEncodedLen);
4536	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4537	if (fVerbose)
4538	{
4539	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4540	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4541	cEntries, cbBuffer);
4542	}
4543	}
4544	/* Device-Specific Feature Extension Register. */
4545	{
4546	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4547	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4548	if (fVerbose)
4549	{
4550	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4551	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4552	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4553	}
4554	}
4555	/* Device-Specific Control Extension Register. */
4556	{
4557	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4558	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4559	if (fVerbose)
4560	{
4561	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4562	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4563	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4564	}
4565	}
4566	/* Device-Specific Status Extension Register. */
4567	{
4568	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4569	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
4570	if (fVerbose)
4571	{
4572	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4573	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4574	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4575	}
4576	}
4577	/* MSI Miscellaneous Information Register (Lo and Hi). */
4578	{
4579	MSI_MISC_INFO_T const MsiMiscInfo = pThis->MsiMiscInfo;
4580	pHlp->pfnPrintf(pHlp, " MSI Misc. Info. Register = %#RX64\n", MsiMiscInfo.u64);
4581	if (fVerbose)
4582	{
4583	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumEvtLog);
4584	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MsiMiscInfo.n.u3GstVirtAddrSize);
4585	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MsiMiscInfo.n.u7PhysAddrSize);
4586	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MsiMiscInfo.n.u7VirtAddrSize);
4587	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MsiMiscInfo.n.u1HtAtsResv);
4588	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumPpr);
4589	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumGa);
4590	}
4591	}
4592	/* MSI Capability Header. */
4593	{
4594	MSI_CAP_HDR_T MsiCapHdr;
4595	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4596	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4597	if (fVerbose)
4598	{
4599	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4600	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4601	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4602	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4603	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4604	}
4605	}
4606	/* MSI Address Register (Lo and Hi). */
4607	{
4608	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4609	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4610	MSI_ADDR_T MsiAddr;
4611	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4612	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4613	if (fVerbose)
4614	pHlp->pfnPrintf(pHlp, " Address = %#RX64\n", MsiAddr.n.u62MsiAddr);
4615	}
4616	/* MSI Data. */
4617	{
4618	MSI_DATA_T MsiData;
4619	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4620	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4621	if (fVerbose)
4622	pHlp->pfnPrintf(pHlp, " Data = %#x\n", MsiData.n.u16MsiData);
4623	}
4624	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4625	{
4626	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4627	MsiMapCapHdr.u32 = 0;
4628	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4629	if (fVerbose)
4630	{
4631	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4632	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4633	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4634	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4635	}
4636	}
4637	/* Performance Optimization Control Register. */
4638	{
4639	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4640	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4641	if (fVerbose)
4642	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4643	}
4644	/* XT (x2APIC) General Interrupt Control Register. */
4645	{
4646	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4647	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4648	if (fVerbose)
4649	{
4650	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4651	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4652	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4653	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4654	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4655	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
4656	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4657	}
4658	}
4659	/* XT (x2APIC) PPR Interrupt Control Register. */
4660	{
4661	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4662	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4663	if (fVerbose)
4664	{
4665	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4666	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4667	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4668	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4669	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4670	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
4671	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4672	}
4673	}
4674	/* XT (X2APIC) GA Log Interrupt Control Register. */
4675	{
4676	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4677	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4678	if (fVerbose)
4679	{
4680	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4681	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4682	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4683	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4684	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4685	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
4686	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4687	}
4688	}
4689	/* MARC Registers. */
4690	{
4691	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4692	{
4693	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4694	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4695	pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4696
4697	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4698	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4699	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4700	MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4701
4702	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4703	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4704	}
4705	}
4706	/* Reserved Register. */
4707	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4708	/* Command Buffer Head Pointer Register. */
4709	{
4710	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4711	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
4712	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
4713	}
4714	/* Command Buffer Tail Pointer Register. */
4715	{
4716	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4717	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
4718	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
4719	}
4720	/* Event Log Head Pointer Register. */
4721	{
4722	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4723	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
4724	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
4725	}
4726	/* Event Log Tail Pointer Register. */
4727	{
4728	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4729	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
4730	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
4731	}
4732	/* Status Register. */
4733	{
4734	IOMMU_STATUS_T const Status = pThis->Status;
4735	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4736	if (fVerbose)
4737	{
4738	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4739	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4740	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4741	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4742	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4743	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4744	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4745	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4746	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4747	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4748	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4749	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4750	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4751	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4752	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4753	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4754	}
4755	}
4756	/* PPR Log Head Pointer. */
4757	{
4758	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4759	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
4760	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
4761	}
4762	/* PPR Log Tail Pointer. */
4763	{
4764	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4765	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
4766	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
4767	}
4768	/* Guest Virtual-APIC Log Head Pointer. */
4769	{
4770	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4771	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
4772	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
4773	}
4774	/* Guest Virtual-APIC Log Tail Pointer. */
4775	{
4776	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4777	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
4778	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
4779	}
4780	/* PPR Log B Head Pointer. */
4781	{
4782	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4783	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
4784	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
4785	}
4786	/* PPR Log B Tail Pointer. */
4787	{
4788	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4789	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
4790	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
4791	}
4792	/* Event Log B Head Pointer. */
4793	{
4794	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4795	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
4796	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
4797	}
4798	/* Event Log B Tail Pointer. */
4799	{
4800	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4801	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
4802	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
4803	}
4804	/* PPR Log Auto Response Register. */
4805	{
4806	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4807	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4808	if (fVerbose)
4809	{
4810	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4811	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4812	}
4813	}
4814	/* PPR Log Overflow Early Warning Indicator Register. */
4815	{
4816	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4817	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4818	if (fVerbose)
4819	{
4820	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4821	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4822	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4823	}
4824	}
4825	/* PPR Log Overflow Early Warning Indicator Register. */
4826	{
4827	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4828	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4829	if (fVerbose)
4830	{
4831	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4832	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4833	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4834	}
4835	}
4836	}
4837
4838
4839	/**
4840	* @callback_method_impl{FNSSMDEVSAVEEXEC}
4841	*/
4842	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4843	{
4844	/** @todo IOMMU: Save state. */
4845	RT_NOREF2(pDevIns, pSSM);
4846	return VERR_NOT_IMPLEMENTED;
4847	}
4848
4849
4850	/**
4851	* @callback_method_impl{FNSSMDEVLOADEXEC}
4852	*/
4853	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4854	{
4855	/** @todo IOMMU: Load state. */
4856	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4857	return VERR_NOT_IMPLEMENTED;
4858	}
4859
4860
4861	/**
4862	* @interface_method_impl{PDMDEVREG,pfnReset}
4863	*/
4864	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4865	{
4866	/*
4867	* Resets read-write portion of the IOMMU state.
4868	*
4869	* State data not initialized here is expected to be initialized during
4870	* device construction and remain read-only through the lifetime of the VM.
4871	*/
4872	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4873	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4874	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4875
4876	memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4877
4878	pThis->CmdBufBaseAddr.u64 = 0;
4879	pThis->CmdBufBaseAddr.n.u4Len = 8;
4880
4881	pThis->EvtLogBaseAddr.u64 = 0;
4882	pThis->EvtLogBaseAddr.n.u4Len = 8;
4883
4884	pThis->Ctrl.u64 = 0;
4885
4886	pThis->ExclRangeBaseAddr.u64 = 0;
4887	pThis->ExclRangeLimit.u64 = 0;
4888
4889	pThis->PprLogBaseAddr.u64 = 0;
4890	pThis->PprLogBaseAddr.n.u4Len = 8;
4891
4892	pThis->HwEvtHi.u64 = 0;
4893	pThis->HwEvtLo = 0;
4894	pThis->HwEvtStatus.u64 = 0;
4895
4896	pThis->GALogBaseAddr.u64 = 0;
4897	pThis->GALogBaseAddr.n.u4Len = 8;
4898	pThis->GALogTailAddr.u64 = 0;
4899
4900	pThis->PprLogBBaseAddr.u64 = 0;
4901	pThis->PprLogBBaseAddr.n.u4Len = 8;
4902
4903	pThis->EvtLogBBaseAddr.u64 = 0;
4904	pThis->EvtLogBBaseAddr.n.u4Len = 8;
4905
4906	pThis->DevSpecificFeat.u64 = 0;
4907	pThis->DevSpecificCtrl.u64 = 0;
4908	pThis->DevSpecificStatus.u64 = 0;
4909
4910	pThis->MsiMiscInfo.u64 = 0;
4911	pThis->PerfOptCtrl.u32 = 0;
4912
4913	pThis->XtGenIntrCtrl.u64 = 0;
4914	pThis->XtPprIntrCtrl.u64 = 0;
4915	pThis->XtGALogIntrCtrl.u64 = 0;
4916
4917	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4918
4919	pThis->CmdBufHeadPtr.u64 = 0;
4920	pThis->CmdBufTailPtr.u64 = 0;
4921	pThis->EvtLogHeadPtr.u64 = 0;
4922	pThis->EvtLogTailPtr.u64 = 0;
4923
4924	pThis->Status.u64 = 0;
4925
4926	pThis->PprLogHeadPtr.u64 = 0;
4927	pThis->PprLogTailPtr.u64 = 0;
4928
4929	pThis->GALogHeadPtr.u64 = 0;
4930	pThis->GALogTailPtr.u64 = 0;
4931
4932	pThis->PprLogBHeadPtr.u64 = 0;
4933	pThis->PprLogBTailPtr.u64 = 0;
4934
4935	pThis->EvtLogBHeadPtr.u64 = 0;
4936	pThis->EvtLogBTailPtr.u64 = 0;
4937
4938	pThis->PprLogAutoResp.u64 = 0;
4939	pThis->PprLogOverflowEarly.u64 = 0;
4940	pThis->PprLogBOverflowEarly.u64 = 0;
4941
4942	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4943	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4944	}
4945
4946
4947	/**
4948	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4949	*/
4950	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4951	{
4952	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4953	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4954	LogFlowFunc(("\n"));
4955
4956	/* Close the command thread semaphore. */
4957	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4958	{
4959	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4960	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4961	}
4962	return VINF_SUCCESS;
4963	}
4964
4965
4966	/**
4967	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4968	*/
4969	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4970	{
4971	NOREF(iInstance);
4972
4973	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4974	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4975	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4976	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4977	int rc;
4978	LogFlowFunc(("\n"));
4979
4980	pThisCC->pDevInsR3 = pDevIns;
4981
4982	/*
4983	* Validate and read the configuration.
4984	*/
4985	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Device\|Function", "");
4986
4987	uint8_t uPciDevice;
4988	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Device", &uPciDevice, 0);
4989	if (RT_FAILURE(rc))
4990	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Device\""));
4991
4992	uint8_t uPciFunction;
4993	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Function", &uPciFunction, 2);
4994	if (RT_FAILURE(rc))
4995	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Function\""));
4996
4997	/*
4998	* Register the IOMMU with PDM.
4999	*/
5000	PDMIOMMUREGR3 IommuReg;
5001	RT_ZERO(IommuReg);
5002	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5003	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5004	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5005	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5006	rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
5007	if (RT_FAILURE(rc))
5008	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
5009	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
5010	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5011	N_("IOMMU helper version mismatch; got %#x expected %#x"),
5012	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
5013	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
5014	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5015	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
5016	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
5017
5018	/*
5019	* Initialize read-only PCI configuration space.
5020	*/
5021	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5022	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5023
5024	/* Header. */
5025	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
5026	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
5027	PDMPciDevSetCommand(pPciDev, 0); /* Command */
5028	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
5029	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
5030	PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
5031	PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
5032	PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
5033	PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
5034	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
5035	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
5036	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
5037	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
5038	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
5039
5040	/* Capability Header. */
5041	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
5042	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
5043	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
5044	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
5045	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
5046	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
5047	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
5048	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
5049	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
5050	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
5051
5052	/* Base Address Low Register. */
5053	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
5054
5055	/* Base Address High Register. */
5056	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
5057
5058	/* IOMMU Range Register. */
5059	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
5060
5061	/* Misc. Information Register 0. */
5062	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0,
5063	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
5064	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
5065	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
5066	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
5067	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
5068	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
5069
5070	/* Misc. Information Register 1. */
5071	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, 0);
5072
5073	/* MSI Capability Header register. */
5074	PDMMSIREG MsiReg;
5075	RT_ZERO(MsiReg);
5076	MsiReg.cMsiVectors = 1;
5077	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
5078	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
5079	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
5080	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5081	AssertRCReturn(rc, rc);
5082
5083	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
5084	#if 0
5085	/* MSI Address Lo. */
5086	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
5087	/* MSI Address Hi. */
5088	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
5089	/* MSI Data. */
5090	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
5091	#endif
5092
5093	#if 0
5094	/** @todo IOMMU: I don't know if we need to support this, enable later if
5095	* required. */
5096	/* MSI Mapping Capability Header register. */
5097	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
5098	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
5099	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
5100	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
5101	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
5102	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
5103	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
5104	#endif
5105
5106	/*
5107	* Register the PCI function with PDM.
5108	*/
5109	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /* fFlags */, uPciDevice, uPciFunction, "amd-iommu");
5110	AssertLogRelRCReturn(rc, rc);
5111
5112	/*
5113	* Intercept PCI config. space accesses.
5114	*/
5115	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
5116	AssertLogRelRCReturn(rc, rc);
5117
5118	/*
5119	* Create the MMIO region.
5120	* Mapping of the region is done when software configures it via PCI config space.
5121	*/
5122	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
5123	NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
5124	"AMD-IOMMU", &pThis->hMmio);
5125	AssertLogRelRCReturn(rc, rc);
5126
5127	/*
5128	* Register saved state.
5129	*/
5130	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
5131	NULL, NULL, NULL,
5132	NULL, iommuAmdR3SaveExec, NULL,
5133	NULL, iommuAmdR3LoadExec, NULL);
5134	AssertLogRelRCReturn(rc, rc);
5135
5136	/*
5137	* Register debugger info item.
5138	*/
5139	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
5140	AssertLogRelRCReturn(rc, rc);
5141
5142	/*
5143	* Create the command thread and its event semaphore.
5144	*/
5145	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5146	0 /* cbStack */, RTTHREADTYPE_IO, "AMD-IOMMU");
5147	AssertLogRelRCReturn(rc, rc);
5148
5149	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5150	AssertLogRelRCReturn(rc, rc);
5151
5152	/*
5153	* Initialize read-only registers.
5154	*/
5155	/** @todo Don't remove the =0 assignment for now. It's just there so it's easier
5156	* for me to see existing features that we might want to implement. Do it
5157	* later. */
5158	pThis->ExtFeat.u64 = 0;
5159	pThis->ExtFeat.n.u1PrefetchSup = 0;
5160	pThis->ExtFeat.n.u1PprSup = 0;
5161	pThis->ExtFeat.n.u1X2ApicSup = 0;
5162	pThis->ExtFeat.n.u1NoExecuteSup = 0;
5163	pThis->ExtFeat.n.u1GstTranslateSup = 0;
5164	pThis->ExtFeat.n.u1InvAllSup = 0;
5165	pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5166	pThis->ExtFeat.n.u1HwErrorSup = 1;
5167	pThis->ExtFeat.n.u1PerfCounterSup = 0;
5168	pThis->ExtFeat.n.u2HostAddrTranslateSize = IOMMU_MAX_HOST_PT_LEVEL;
5169	pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
5170	pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
5171	pThis->ExtFeat.n.u2SmiFilterSup = 0;
5172	pThis->ExtFeat.n.u3SmiFilterCount = 0;
5173	pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5174	pThis->ExtFeat.n.u2DualPprLogSup = 0;
5175	pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5176	pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
5177	pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5178	AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5179	pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5180	pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5181	pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5182	pThis->ExtFeat.n.u2MarcSup = 0;
5183	pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5184	pThis->ExtFeat.n.u1PerfOptSup = 0;
5185	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5186	pThis->ExtFeat.n.u1GstIoSup = 0;
5187	pThis->ExtFeat.n.u1HostAccessSup = 0;
5188	pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5189	pThis->ExtFeat.n.u1AttrForwardSup = 0;
5190	pThis->ExtFeat.n.u1HostDirtySup = 0;
5191	pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5192	pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5193	pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5194
5195	pThis->RsvdReg = 0;
5196
5197	/*
5198	* Initialize parts of the IOMMU state as it would during reset.
5199	* Must be called -after- initializing PCI config. space registers.
5200	*/
5201	iommuAmdR3Reset(pDevIns);
5202
5203	return VINF_SUCCESS;
5204	}
5205
5206	# else /* !IN_RING3 */
5207
5208	/**
5209	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5210	*/
5211	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5212	{
5213	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5214	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5215	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5216
5217	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5218
5219	/* Set up the MMIO RZ handlers. */
5220	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5221	AssertRCReturn(rc, rc);
5222
5223	/* Set up the IOMMU RZ callbacks. */
5224	PDMIOMMUREGCC IommuReg;
5225	RT_ZERO(IommuReg);
5226	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5227	IommuReg.idxIommu = pThis->idxIommu;
5228	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5229	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5230	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5231	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5232	AssertRCReturn(rc, rc);
5233
5234	return VINF_SUCCESS;
5235	}
5236
5237	# endif /* !IN_RING3 */
5238
5239	/**
5240	* The device registration structure.
5241	*/
5242	const PDMDEVREG g_DeviceIommuAmd =
5243	{
5244	/* .u32Version = */ PDM_DEVREG_VERSION,
5245	/* .uReserved0 = */ 0,
5246	/* .szName = */ "iommu-amd",
5247	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
5248	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
5249	/* .cMaxInstances = */ ~0U,
5250	/* .uSharedVersion = */ 42,
5251	/* .cbInstanceShared = */ sizeof(IOMMU),
5252	/* .cbInstanceCC = */ sizeof(IOMMUCC),
5253	/* .cbInstanceRC = */ sizeof(IOMMURC),
5254	/* .cMaxPciDevices = */ 1,
5255	/* .cMaxMsixVectors = */ 0,
5256	/* .pszDescription = */ "IOMMU (AMD)",
5257	#if defined(IN_RING3)
5258	/* .pszRCMod = */ "VBoxDDRC.rc",
5259	/* .pszR0Mod = */ "VBoxDDR0.r0",
5260	/* .pfnConstruct = */ iommuAmdR3Construct,
5261	/* .pfnDestruct = */ iommuAmdR3Destruct,
5262	/* .pfnRelocate = */ NULL,
5263	/* .pfnMemSetup = */ NULL,
5264	/* .pfnPowerOn = */ NULL,
5265	/* .pfnReset = */ iommuAmdR3Reset,
5266	/* .pfnSuspend = */ NULL,
5267	/* .pfnResume = */ NULL,
5268	/* .pfnAttach = */ NULL,
5269	/* .pfnDetach = */ NULL,
5270	/* .pfnQueryInterface = */ NULL,
5271	/* .pfnInitComplete = */ NULL,
5272	/* .pfnPowerOff = */ NULL,
5273	/* .pfnSoftReset = */ NULL,
5274	/* .pfnReserved0 = */ NULL,
5275	/* .pfnReserved1 = */ NULL,
5276	/* .pfnReserved2 = */ NULL,
5277	/* .pfnReserved3 = */ NULL,
5278	/* .pfnReserved4 = */ NULL,
5279	/* .pfnReserved5 = */ NULL,
5280	/* .pfnReserved6 = */ NULL,
5281	/* .pfnReserved7 = */ NULL,
5282	#elif defined(IN_RING0)
5283	/* .pfnEarlyConstruct = */ NULL,
5284	/* .pfnConstruct = */ iommuAmdRZConstruct,
5285	/* .pfnDestruct = */ NULL,
5286	/* .pfnFinalDestruct = */ NULL,
5287	/* .pfnRequest = */ NULL,
5288	/* .pfnReserved0 = */ NULL,
5289	/* .pfnReserved1 = */ NULL,
5290	/* .pfnReserved2 = */ NULL,
5291	/* .pfnReserved3 = */ NULL,
5292	/* .pfnReserved4 = */ NULL,
5293	/* .pfnReserved5 = */ NULL,
5294	/* .pfnReserved6 = */ NULL,
5295	/* .pfnReserved7 = */ NULL,
5296	#elif defined(IN_RC)
5297	/* .pfnConstruct = */ iommuAmdRZConstruct,
5298	/* .pfnReserved0 = */ NULL,
5299	/* .pfnReserved1 = */ NULL,
5300	/* .pfnReserved2 = */ NULL,
5301	/* .pfnReserved3 = */ NULL,
5302	/* .pfnReserved4 = */ NULL,
5303	/* .pfnReserved5 = */ NULL,
5304	/* .pfnReserved6 = */ NULL,
5305	/* .pfnReserved7 = */ NULL,
5306	#else
5307	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5308	#endif
5309	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5310	};
5311
5312	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5313

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 84199

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