DevIommuAmd.cpp@ 84315

Last change on this file since 84315 was 84315, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 Bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 256.3 KB

Line
1	/* $Id: DevIommuAmd.cpp 84315 2020-05-15 06:30:29Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/msi.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/AssertGuest.h>
26
27	#include "VBoxDD.h"
28	#include <iprt/x86.h>
29	#include <iprt/string.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/**
36	* @name PCI configuration register offsets.
37	* In accordance with the AMD spec.
38	* @{
39	*/
40	#define IOMMU_PCI_OFF_CAP_HDR 0x40
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
42	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
43	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
44	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
45	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
46	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
47	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
48	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
49	#define IOMMU_PCI_OFF_MSI_DATA 0x70
50	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
51	/** @} */
52
53	/**
54	* @name MMIO register offsets.
55	* In accordance with the AMD spec.
56	* @{
57	*/
58	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
59	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
60	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
61	#define IOMMU_MMIO_OFF_CTRL 0x18
62	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
63	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
64	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
65
66	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
67	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
68	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
69	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
70
71	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
72	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
73
74	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
75	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
76
77	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
78	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
79
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
81	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
82	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
83	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
84	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
85	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
86	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
87	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
88	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
89
90	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
91	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
92	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
93
94	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
95	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
96	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
97	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
98	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
99	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
100	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
101
102	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
103
104	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
105	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
106	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
107
108	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
109	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
110	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
111	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
112	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
113	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
114	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
115	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
116	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
117	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
118	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
119	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
120
121	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
122
123	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
124	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
125	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
126	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
127
128	#define IOMMU_MMIO_OFF_STATUS 0x2020
129
130	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
131	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
132
133	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
134	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
135
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
137	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
138
139	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
140	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
141
142	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
143	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
144	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
145	/** @} */
146
147	/**
148	* @name MMIO register-access table offsets.
149	* Each table [first..last] (both inclusive) represents the range of registers
150	* covered by a distinct register-access table. This is done due to arbitrary large
151	* gaps in the MMIO register offsets themselves.
152	* @{
153	*/
154	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
155	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
156
157	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
158	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
159	/** @} */
160
161	/**
162	* @name Commands.
163	* In accordance with the AMD spec.
164	* @{
165	*/
166	#define IOMMU_CMD_COMPLETION_WAIT 0x01
167	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
168	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
169	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
170	#define IOMMU_CMD_INV_INTR_TABLE 0x05
171	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
172	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
173	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
174	/** @} */
175
176	/**
177	* @name Event codes.
178	* In accordance with the AMD spec.
179	* @{
180	*/
181	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
182	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
183	#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
184	#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
185	#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
186	#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
187	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
188	#define IOMMU_EVT_INVALID_DEV_REQ 0x08
189	#define IOMMU_EVT_INVALID_PPR_REQ 0x09
190	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
191	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
192	/** @} */
193
194	/**
195	* @name IOMMU Capability Header.
196	* In accordance with the AMD spec.
197	* @{
198	*/
199	/** CapId: Capability ID. */
200	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
201	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
202	/** CapPtr: Capability Pointer. */
203	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
204	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
205	/** CapType: Capability Type. */
206	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
207	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
208	/** CapRev: Capability Revision. */
209	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
210	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
211	/** IoTlbSup: IO TLB Support. */
212	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
213	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
214	/** HtTunnel: HyperTransport Tunnel translation support. */
215	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
216	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
217	/** NpCache: Not Present table entries Cached. */
218	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
219	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
220	/** EFRSup: Extended Feature Register (EFR) Supported. */
221	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
222	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
223	/** CapExt: Miscellaneous Information Register Supported . */
224	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
225	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
226	/** Bits 31:29 reserved. */
227	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
228	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
229	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
230	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
231	/** @} */
232
233	/**
234	* @name IOMMU Base Address Low Register.
235	* In accordance with the AMD spec.
236	* @{
237	*/
238	/** Enable: Enables access to the address specified in the Base Address Register. */
239	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
240	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
241	/** Bits 13:1 reserved. */
242	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
243	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
244	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
245	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
246	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
247	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
248	(ENABLE, RSVD_1_13, ADDR));
249	/** @} */
250
251	/**
252	* @name IOMMU Range Register.
253	* In accordance with the AMD spec.
254	* @{
255	*/
256	/** UnitID: HyperTransport Unit ID. */
257	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
258	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
259	/** Bits 6:5 reserved. */
260	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
261	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
262	/** RngValid: Range valid. */
263	#define IOMMU_BF_RANGE_VALID_SHIFT 7
264	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
265	/** BusNumber: Device range bus number. */
266	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
267	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
268	/** First Device. */
269	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
270	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
271	/** Last Device. */
272	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
273	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
274	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
275	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
276	/** @} */
277
278	/**
279	* @name IOMMU Miscellaneous Information Register 0.
280	* In accordance with the AMD spec.
281	* @{
282	*/
283	/** MsiNum: MSI message number. */
284	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
285	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
286	/** GvaSize: Guest Virtual Address Size. */
287	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
288	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
289	/** PaSize: Physical Address Size. */
290	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
291	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
292	/** VaSize: Virtual Address Size. */
293	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
294	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
295	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
296	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
297	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
298	/** Bits 26:23 reserved. */
299	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
300	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
301	/** MsiNumPPR: Peripheral Page Request MSI message number. */
302	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
303	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
304	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
305	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
306	/** @} */
307
308	/**
309	* @name IOMMU Miscellaneous Information Register 1.
310	* In accordance with the AMD spec.
311	* @{
312	*/
313	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
314	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
315	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
316	/** Bits 31:5 reserved. */
317	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
318	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
319	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
320	(MSI_NUM_GA, RSVD_5_31));
321	/** @} */
322
323	/**
324	* @name MSI Capability Header Register.
325	* In accordance with the AMD spec.
326	* @{
327	*/
328	/** MsiCapId: Capability ID. */
329	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
330	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
331	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
332	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
333	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
334	/** MsiEn: Message Signal Interrupt enable. */
335	#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
336	#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
337	/** MsiMultMessCap: MSI Multi-Message Capability. */
338	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
339	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
340	/** MsiMultMessEn: MSI Mult-Message Enable. */
341	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
342	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
343	/** Msi64BitEn: MSI 64-bit Enabled. */
344	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
345	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
346	/** Bits 31:24 reserved. */
347	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
348	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
349	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
350	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
351	/** @} */
352
353	/**
354	* @name MSI Mapping Capability Header Register.
355	* In accordance with the AMD spec.
356	* @{
357	*/
358	/** MsiMapCapId: Capability ID. */
359	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
360	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
361	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
362	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
363	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
364	/** MsiMapEn: MSI mapping capability enable. */
365	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
366	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
367	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
368	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
369	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
370	/** Bits 18:28 reserved. */
371	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
372	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
373	/** MsiMapCapType: MSI mapping capability. */
374	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
375	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
376	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
377	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
378	/** @} */
379
380	/**
381	* @name IOMMU Status Register Bits.
382	* In accordance with the AMD spec.
383	* @{
384	*/
385	/** EventOverflow: Event log overflow. */
386	#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
387	/** EventLogInt: Event log interrupt. */
388	#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
389	/** ComWaitInt: Completion wait interrupt. */
390	#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
391	/** EventLogRun: Event log is running. */
392	#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
393	/** CmdBufRun: Command buffer is running. */
394	#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
395	/** PprOverflow: Peripheral page request log overflow. */
396	#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
397	/** PprInt: Peripheral page request log interrupt. */
398	#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
399	/** PprLogRun: Peripheral page request log is running. */
400	#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
401	/** GALogRun: Guest virtual-APIC log is running. */
402	#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
403	/** GALOverflow: Guest virtual-APIC log overflow. */
404	#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
405	/** GAInt: Guest virtual-APIC log interrupt. */
406	#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
407	/** PprOvrflwB: PPR Log B overflow. */
408	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
409	/** PprLogActive: PPR Log B is active. */
410	#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
411	/** EvtOvrflwB: Event log B overflow. */
412	#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
413	/** EventLogActive: Event log B active. */
414	#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
415	/** PprOvrflwEarlyB: PPR log B overflow early warning. */
416	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
417	/** PprOverflowEarly: PPR log overflow early warning. */
418	#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
419	/** @} */
420
421	/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
422	* In accordance with the AMD spec.
423	*
424	* These values match the shifted values of the IR and IW field of the DTE and the
425	* PTE, PDE of the I/O page tables.
426	*
427	* @{ */
428	#define IOMMU_IO_PERM_NONE (0)
429	#define IOMMU_IO_PERM_READ RT_BIT_64(0)
430	#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
431	#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ \| IOMMU_IO_PERM_WRITE)
432	#define IOMMU_IO_PERM_SHIFT 61
433	#define IOMMU_IO_PERM_MASK 0x3
434	/** @} */
435
436	/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
437	* In accordance with the AMD spec.
438	* @{ */
439	#define SYSMGTTYPE_DMA_DENY (0)
440	#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
441	#define SYSMGTTYPE_MSG_INT_ALLOW (2)
442	#define SYSMGTTYPE_DMA_ALLOW (3)
443	/** @} */
444
445	/**
446	* @name IOMMU Control Register Bits.
447	* In accordance with the AMD spec.
448	* @{
449	*/
450	/** IommuEn: Enable the IOMMU. */
451	#define IOMMU_CTRL_IOMMU_EN RT_BIT_64(0)
452	/** HtTunEn: HyperTransport tunnel translation enable. */
453	#define IOMMU_CTRL_HT_TUNNEL_EN RT_BIT_64(1)
454	/** EventLogEn: Event log enable. */
455	#define IOMMU_CTRL_EVT_LOG_EN RT_BIT_64(2)
456	/** EventIntEn: Event interrupt enable. */
457	#define IOMMU_CTRL_EVT_INTR_EN RT_BIT_64(3)
458	/** ComWaitIntEn: Completion wait interrupt enable. */
459	#define IOMMU_CTRL_COMPLETION_WAIT_INTR_EN RT_BIT_64(4)
460	/** InvTimeout: Invalidation timeout. */
461	#define IOMMU_CTRL_INV_TIMEOUT RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7)
462	/** @todo IOMMU: the rest or remove it. */
463	/** @} */
464
465	/** @name Miscellaneous IOMMU defines.
466	* @{ */
467	/** Log prefix string. */
468	#define IOMMU_LOG_PFX "AMD_IOMMU"
469	/** The current saved state version. */
470	#define IOMMU_SAVED_STATE_VERSION 1
471	/** AMD's vendor ID. */
472	#define IOMMU_PCI_VENDOR_ID 0x1022
473	/** VirtualBox IOMMU device ID. */
474	#define IOMMU_PCI_DEVICE_ID 0xc0de
475	/** VirtualBox IOMMU device revision ID. */
476	#define IOMMU_PCI_REVISION_ID 0x01
477	/** Size of the MMIO region in bytes. */
478	#define IOMMU_MMIO_REGION_SIZE _16K
479	/** Number of device table segments supported (power of 2). */
480	#define IOMMU_MAX_DEV_TAB_SEGMENTS 3
481	/** Maximum host address translation level supported (inclusive). */
482	#define IOMMU_MAX_HOST_PT_LEVEL 6
483	/** The IOTLB entry magic. */
484	#define IOMMU_IOTLBE_MAGIC 0x10acce55
485	/** The device-specific feature major revision. */
486	#define IOMMU_DEVSPEC_FEAT_MAJOR_VERSION 0x1
487	/** The device-specific feature minor revision. */
488	#define IOMMU_DEVSPEC_FEAT_MINOR_VERSION 0x0
489	/** The device-specific control major revision. */
490	#define IOMMU_DEVSPEC_CTRL_MAJOR_VERSION 0x1
491	/** The device-specific control minor revision. */
492	#define IOMMU_DEVSPEC_CTRL_MINOR_VERSION 0x0
493	/** The device-specific status major revision. */
494	#define IOMMU_DEVSPEC_STATUS_MAJOR_VERSION 0x1
495	/** The device-specific status minor revision. */
496	#define IOMMU_DEVSPEC_STATUS_MINOR_VERSION 0x0
497	/** @} */
498
499	/**
500	* Acquires the IOMMU PDM lock.
501	* This will make a long jump to ring-3 to acquire the lock if necessary.
502	*/
503	#define IOMMU_LOCK(a_pDevIns) \
504	do { \
505	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
506	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
507	{ /* likely */ } \
508	else \
509	return rcLock; \
510	} while (0)
511
512	/**
513	* Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
514	* This will make a long jump to ring-3 to acquire the lock if necessary.
515	*/
516	#define IOMMU_LOCK_NORET(a_pDevIns) \
517	do { \
518	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
519	AssertRC(rcLock); \
520	} while (0)
521
522	/**
523	* Releases the IOMMU PDM lock.
524	*/
525	#define IOMMU_UNLOCK(a_pDevIns) \
526	do { \
527	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
528	} while (0)
529
530	/**
531	* Asserts that the critsect is owned by this thread.
532	*/
533	#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
534	do { \
535	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
536	} while (0)
537
538	/**
539	* Asserts that the critsect is not owned by this thread.
540	*/
541	#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
542	do { \
543	Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
544	} while (0)
545
546	/**
547	* Gets the device table size given the size field.
548	*/
549	#define IOMMU_GET_DEV_TAB_SIZE(a_uSize) (((a_uSize) + 1) << X86_PAGE_4K_SHIFT)
550
551
552	/*********************************************************************************************************************************
553	* Structures and Typedefs *
554	*********************************************************************************************************************************/
555	/**
556	* The Device ID.
557	* In accordance with VirtualBox's PCI configuration.
558	*/
559	typedef union
560	{
561	struct
562	{
563	uint16_t u3Function : 3; /*< Bits 2:0 - Function. /
564	uint16_t u9Device : 9; /*< Bits 11:3 - Device. /
565	uint16_t u4Bus : 4; /*< Bits 15:12 - Bus. /
566	} n;
567	/** The unsigned integer view. */
568	uint16_t u;
569	} DEVICE_ID_T;
570	AssertCompileSize(DEVICE_ID_T, 2);
571
572	/**
573	* Device Table Entry (DTE).
574	* In accordance with the AMD spec.
575	*/
576	typedef union
577	{
578	struct
579	{
580	RT_GCC_EXTENSION uint64_t u1Valid : 1; /*< Bit 0 - V: Valid. /
581	RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
582	RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
583	RT_GCC_EXTENSION uint64_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
584	RT_GCC_EXTENSION uint64_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
585	RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /*< Bits 51:12 - Page Table Root Pointer. /
586	RT_GCC_EXTENSION uint64_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
587	RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
588	RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
589	RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
590	RT_GCC_EXTENSION uint64_t u2GstMode : 2; /*< Bits 57:56 - GLX: Guest Paging mode levels. /
591	RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). /
592	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
593	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
594	RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
595	RT_GCC_EXTENSION uint64_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
596	RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). /
597	RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /*< Bit 96 - I: IOTLB Enable. /
598	RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
599	RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
600	RT_GCC_EXTENSION uint64_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
601	RT_GCC_EXTENSION uint64_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
602	RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
603	RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
604	RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
605	RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
606	RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). /
607	RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
608	RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
609	RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
610	RT_GCC_EXTENSION uint64_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
611	RT_GCC_EXTENSION uint64_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
612	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
613	RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
614	RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
615	RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
616	RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
617	RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
618	RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 Pass-through. /
619	RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 Pass-through. /
620	RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /*< Bits 223:192 - Reserved. /
621	RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
622	RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
623	RT_GCC_EXTENSION uint64_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
624	RT_GCC_EXTENSION uint64_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
625	} n;
626	/** The 32-bit unsigned integer view. */
627	uint32_t au32[8];
628	/** The 64-bit unsigned integer view. */
629	uint64_t au64[4];
630	} DTE_T;
631	AssertCompileSize(DTE_T, 32);
632	/** Pointer to a device table entry. */
633	typedef DTE_T *PDTE_T;
634	/** Pointer to a const device table entry. */
635	typedef DTE_T const *PCDTE_T;
636
637	/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
638	* Support) feature (bits 52:53). */
639	#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
640
641	/** Mask of valid bits for GTSup (Guest Translation Support) feature (bits 55:60,
642	* bits 80:95). */
643	#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
644	#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
645
646	/* Mask of valid bits for GIoSup (Guest I/O Protection Support) feature (bit 54). */
647	#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
648
649	/* Mask of valid DTE feature bits. */
650	#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
651	\| IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
652	\| IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
653	#define IOMMU_DTE_QWORD_1_FEAT_MASK (IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
654
655	/* Mask of all valid DTE bits (including all feature bits). */
656	#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
657	#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
658	#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xf70fffffffffffff)
659	#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
660
661	/**
662	* I/O Page Translation Entry.
663	* In accordance with the AMD spec.
664	*/
665	typedef union
666	{
667	struct
668	{
669	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
670	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
671	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
672	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
673	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
674	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
675	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
676	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
677	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
678	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
679	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
680	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
681	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
682	} n;
683	/** The 64-bit unsigned integer view. */
684	uint64_t u64;
685	} IOPTE_T;
686	AssertCompileSize(IOPTE_T, 8);
687
688	/**
689	* I/O Page Directory Entry.
690	* In accordance with the AMD spec.
691	*/
692	typedef union
693	{
694	struct
695	{
696	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
697	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
698	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
699	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
700	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
701	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
702	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
703	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
704	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
705	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
706	} n;
707	/** The 64-bit unsigned integer view. */
708	uint64_t u64;
709	} IOPDE_T;
710	AssertCompileSize(IOPDE_T, 8);
711
712	/**
713	* I/O Page Table Entry/Entity.
714	* In accordance with the AMD spec.
715	*
716	* This a common subset of an DTE.au64[0], PTE and PDE.
717	* Named as an "entity" to avoid confusing it with PTE.
718	*/
719	typedef union
720	{
721	struct
722	{
723	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
724	RT_GCC_EXTENSION uint64_t u8Ign0 : 8; /*< Bits 8:1 - Ignored. /
725	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Mode / Next Level: Next page translation level. /
726	RT_GCC_EXTENSION uint64_t u40Addr : 40; /*< Bits 51:12 - Page address. /
727	RT_GCC_EXTENSION uint64_t u9Ign0 : 9; /*< Bits 60:52 - Ignored. /
728	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
729	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
730	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
731	} n;
732	/** The 64-bit unsigned integer view. */
733	uint64_t u64;
734	} IOPTENTITY_T;
735	AssertCompileSize(IOPTENTITY_T, 8);
736	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPTE_T));
737	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPDE_T));
738	/** Pointer to an IOPT_ENTITY_T struct. */
739	typedef IOPTENTITY_T *PIOPTENTITY_T;
740	/** Pointer to a const IOPT_ENTITY_T struct. */
741	typedef IOPTENTITY_T const *PCIOPTENTITY_T;
742	/** Mask of the address field. */
743	#define IOMMU_PTENTITY_ADDR_MASK UINT64_C(0x000ffffffffff000)
744
745	/**
746	* Interrupt Remapping Table Entry (IRTE).
747	* In accordance with the AMD spec.
748	*/
749	typedef union
750	{
751	struct
752	{
753	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
754	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
755	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
756	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
757	uint32_t u1DstMode : 1; /*< Bit 6 - DM: Destination Mode. /
758	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
759	uint32_t u8Dst : 8; /*< Bits 15:8 - Destination. /
760	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
761	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
762	} n;
763	/** The 32-bit unsigned integer view. */
764	uint32_t u32;
765	} IRTE_T;
766	AssertCompileSize(IRTE_T, 4);
767	/** Pointer to an IRTE_T struct. */
768	typedef IRTE_T *PIRTE_T;
769	/** Pointer to a const IRTE_T struct. */
770	typedef IRTE_T const *PCIRTE_T;
771
772	/**
773	* Command: Generic Command Buffer Entry.
774	* In accordance with the AMD spec.
775	*/
776	typedef union
777	{
778	struct
779	{
780	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
781	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
782	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
783	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
784	} n;
785	/** The 64-bit unsigned integer view. */
786	uint64_t au64[2];
787	} CMD_GENERIC_T;
788	AssertCompileSize(CMD_GENERIC_T, 16);
789	/** Pointer to a generic command buffer entry. */
790	typedef CMD_GENERIC_T *PCMD_GENERIC_T;
791	/** Pointer to a const generic command buffer entry. */
792	typedef CMD_GENERIC_T const *PCCMD_GENERIC_T;
793
794	/** Number of bits to shift the byte offset of a command in the command buffer to
795	* get its index. */
796	#define IOMMU_CMD_GENERIC_SHIFT 4
797
798	/**
799	* Command: COMPLETION_WAIT.
800	* In accordance with the AMD spec.
801	*/
802	typedef union
803	{
804	struct
805	{
806	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
807	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
808	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
809	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
810	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
811	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
812	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
813	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
814	} n;
815	/** The 64-bit unsigned integer view. */
816	uint64_t au64[2];
817	} CMD_COMWAIT_T;
818	AssertCompileSize(CMD_COMWAIT_T, 16);
819	/** Pointer to a completion wait command. */
820	typedef CMD_COMWAIT_T *PCMD_COMWAIT_T;
821	/** Pointer to a const completion wait command. */
822	typedef CMD_COMWAIT_T const *PCCMD_COMWAIT_T;
823	#define IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK UINT64_C(0xf00fffffffffffff)
824
825	/**
826	* Command: INVALIDATE_DEVTAB_ENTRY.
827	* In accordance with the AMD spec.
828	*/
829	typedef union
830	{
831	struct
832	{
833	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
834	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
835	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
836	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
837	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
838	} n;
839	/** The 64-bit unsigned integer view. */
840	uint64_t au64[2];
841	} CMD_INV_DTE_T;
842	AssertCompileSize(CMD_INV_DTE_T, 16);
843
844	/**
845	* Command: INVALIDATE_IOMMU_PAGES.
846	* In accordance with the AMD spec.
847	*/
848	typedef union
849	{
850	struct
851	{
852	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
853	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
854	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
855	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
856	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
857	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
858	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
859	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
860	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
861	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
862	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
863	} n;
864	/** The 64-bit unsigned integer view. */
865	uint64_t au64[2];
866	} CMD_INV_IOMMU_PAGES_T;
867	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
868
869	/**
870	* Command: INVALIDATE_IOTLB_PAGES.
871	* In accordance with the AMD spec.
872	*/
873	typedef union
874	{
875	struct
876	{
877	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
878	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
879	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
880	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
881	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
882	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
883	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
884	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
885	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
886	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
887	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
888	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
889	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
890	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
891	} n;
892	/** The 64-bit unsigned integer view. */
893	uint64_t au64[2];
894	} CMD_INV_IOTLB_PAGES_T;
895	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
896
897	/**
898	* Command: INVALIDATE_INTR_TABLE.
899	* In accordance with the AMD spec.
900	*/
901	typedef union
902	{
903	struct
904	{
905	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
906	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
907	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
908	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
909	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
910	} u;
911	/** The 64-bit unsigned integer view. */
912	uint64_t au64[2];
913	} CMD_INV_INTR_TABLE_T;
914	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
915
916	/**
917	* Command: COMPLETE_PPR_REQ.
918	* In accordance with the AMD spec.
919	*/
920	typedef union
921	{
922	struct
923	{
924	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
925	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
926	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
927	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
928	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
929	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
930	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
931	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
932	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
933	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
934	} n;
935	/** The 64-bit unsigned integer view. */
936	uint64_t au64[2];
937	} CMD_COMPLETE_PPR_REQ_T;
938	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
939
940	/**
941	* Command: INV_IOMMU_ALL.
942	* In accordance with the AMD spec.
943	*/
944	typedef union
945	{
946	struct
947	{
948	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
949	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
950	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
951	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
952	} n;
953	/** The 64-bit unsigned integer view. */
954	uint64_t au64[2];
955	} CMD_IOMMU_ALL_T;
956	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
957
958	/**
959	* Event Log Entry: Generic.
960	* In accordance with the AMD spec.
961	*/
962	typedef union
963	{
964	struct
965	{
966	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
967	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
968	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
969	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
970	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
971	} n;
972	/** The 32-bit unsigned integer view. */
973	uint32_t au32[4];
974	} EVT_GENERIC_T;
975	AssertCompileSize(EVT_GENERIC_T, 16);
976	/** Number of bits to shift the byte offset of an event entry in the event log
977	* buffer to get its index. */
978	#define IOMMU_EVT_GENERIC_SHIFT 4
979	/** Pointer to a generic event log entry. */
980	typedef EVT_GENERIC_T *PEVT_GENERIC_T;
981	/** Pointer to a const generic event log entry. */
982	typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
983
984	/**
985	* Hardware event types.
986	* In accordance with the AMD spec.
987	*/
988	typedef enum HWEVTTYPE
989	{
990	HWEVTTYPE_RSVD = 0,
991	HWEVTTYPE_MASTER_ABORT,
992	HWEVTTYPE_TARGET_ABORT,
993	HWEVTTYPE_DATA_ERROR
994	} HWEVTTYPE;
995	AssertCompileSize(HWEVTTYPE, 4);
996
997	/**
998	* Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
999	* In accordance with the AMD spec.
1000	*/
1001	typedef union
1002	{
1003	struct
1004	{
1005	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1006	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1007	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
1008	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1009	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1010	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1011	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1012	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1013	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1014	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
1015	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1016	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1017	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
1018	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1019	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1020	} n;
1021	/** The 32-bit unsigned integer view. */
1022	uint32_t au32[4];
1023	/** The 64-bit unsigned integer view. */
1024	uint64_t au64[2];
1025	} EVT_ILLEGAL_DTE_T;
1026	AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
1027	/** Pointer to an illegal device table entry event. */
1028	typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
1029	/** Pointer to a const illegal device table entry event. */
1030	typedef EVT_ILLEGAL_DTE_T const *PCEVT_ILLEGAL_DTE_T;
1031
1032	/**
1033	* Event Log Entry: IO_PAGE_FAULT_EVENT.
1034	* In accordance with the AMD spec.
1035	*/
1036	typedef union
1037	{
1038	struct
1039	{
1040	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1041	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1042	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1043	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1044	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
1045	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
1046	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1047	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
1048	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1049	uint16_t u1PermDenied : 1; /*< Bit 54 - PE: Permission Indicator. /
1050	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1051	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1052	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
1053	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1054	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1055	} n;
1056	/** The 32-bit unsigned integer view. */
1057	uint32_t au32[4];
1058	/** The 64-bit unsigned integer view. */
1059	uint64_t au64[2];
1060	} EVT_IO_PAGE_FAULT_T;
1061	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
1062	/** Pointer to an I/O page fault event. */
1063	typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
1064	/** Pointer to a const I/O page fault event. */
1065	typedef EVT_IO_PAGE_FAULT_T const *PCEVT_IO_PAGE_FAULT_T;
1066
1067
1068	/**
1069	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
1070	* In accordance with the AMD spec.
1071	*/
1072	typedef union
1073	{
1074	struct
1075	{
1076	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1077	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1078	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
1079	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). /
1080	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1081	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). /
1082	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
1083	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation (1=translation, 0=transaction). /
1084	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1085	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1086	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1087	uint64_t u64Addr; /*< Bits 127:64 - Address. /
1088	} n;
1089	/** The 32-bit unsigned integer view. */
1090	uint32_t au32[4];
1091	/** The 64-bit unsigned integer view. */
1092	uint64_t au64[2];
1093	} EVT_DEV_TAB_HW_ERROR_T;
1094	AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1095	/** Pointer to a device table hardware error event. */
1096	typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1097	/** Pointer to a const device table hardware error event. */
1098	typedef EVT_DEV_TAB_HW_ERROR_T const *PCEVT_DEV_TAB_HW_ERROR_T;
1099
1100	/**
1101	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1102	* In accordance with the AMD spec.
1103	*/
1104	typedef union
1105	{
1106	struct
1107	{
1108	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1109	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1110	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1111	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1112	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1113	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1114	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1115	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1116	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
1117	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
1118	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1119	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1120	uint32_t u4EvtCode : 4; /*< Bit 63:60 - Event code. /
1121	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1122	* table 58 mentions Addr[31:4], we just use the full 64-bits. Looks like a
1123	* typo in the figure.See AMD AMD IOMMU spec (3.05-PUB, Jan 2020). */
1124	uint64_t u64Addr; /** Bits 127:64 - Address: SPA of the page table entry. */
1125	} n;
1126	/** The 32-bit unsigned integer view. */
1127	uint32_t au32[4];
1128	/** The 64-bit unsigned integer view. */
1129	uint64_t au64[2];
1130	} EVT_PAGE_TAB_HW_ERR_T;
1131	AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1132	/** Pointer to a page table hardware error event. */
1133	typedef EVT_PAGE_TAB_HW_ERR_T *PEVT_PAGE_TAB_HW_ERR_T;
1134	/** Pointer to a const page table hardware error event. */
1135	typedef EVT_PAGE_TAB_HW_ERR_T const *PCEVT_PAGE_TAB_HW_ERR_T;
1136
1137	/**
1138	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
1139	* In accordance with the AMD spec.
1140	*/
1141	typedef union
1142	{
1143	struct
1144	{
1145	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1146	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
1147	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1148	uint64_t u64Addr; /*< Bits 127:64 - Address: SPA of the invalid command. /
1149	} n;
1150	/** The 32-bit unsigned integer view. */
1151	uint32_t au32[4];
1152	/** The 64-bit unsigned integer view. */
1153	uint64_t au64[2];
1154	} EVT_ILLEGAL_CMD_ERR_T;
1155	AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1156	/** Pointer to an illegal command error event. */
1157	typedef EVT_ILLEGAL_CMD_ERR_T *PEVT_ILLEGAL_CMD_ERR_T;
1158	/** Pointer to a const illegal command error event. */
1159	typedef EVT_ILLEGAL_CMD_ERR_T const *PCEVT_ILLEGAL_CMD_ERR_T;
1160
1161	/**
1162	* Event Log Entry: COMMAND_HARDWARE_ERROR.
1163	* In accordance with the AMD spec.
1164	*/
1165	typedef union
1166	{
1167	struct
1168	{
1169	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1170	uint32_t u25Rsvd1 : 25; /*< Bits 56:32 - Reserved. /
1171	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1172	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1173	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1174	uint64_t u64Addr; /*< Bits 128:64 - Address: SPA of the attempted access. /
1175	} n;
1176	/** The 32-bit unsigned integer view. */
1177	uint32_t au32[4];
1178	/** The 64-bit unsigned integer view. */
1179	uint64_t au64[2];
1180	} EVT_CMD_HW_ERR_T;
1181	AssertCompileSize(EVT_CMD_HW_ERR_T, 16);
1182	/** Pointer to a command hardware error event. */
1183	typedef EVT_CMD_HW_ERR_T *PEVT_CMD_HW_ERR_T;
1184	/** Pointer to a const command hardware error event. */
1185	typedef EVT_CMD_HW_ERR_T const *PCEVT_CMD_HW_ERR_T;
1186
1187	/**
1188	* Event Log Entry: IOTLB_INV_TIMEOUT.
1189	* In accordance with the AMD spec.
1190	*/
1191	typedef union
1192	{
1193	struct
1194	{
1195	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1196	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
1197	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1198	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1199	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1200	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
1201	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
1202	} n;
1203	/** The 32-bit unsigned integer view. */
1204	uint32_t au32[4];
1205	} EVT_IOTLB_INV_TIMEOUT_T;
1206	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1207
1208	/**
1209	* Event Log Entry: INVALID_DEVICE_REQUEST.
1210	* In accordance with the AMD spec.
1211	*/
1212	typedef union
1213	{
1214	struct
1215	{
1216	uint32_t u16DevId : 16; /**< Bits 15:0 - Device ID. /
1217	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1218	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
1219	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1220	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1221	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
1222	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
1223	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
1224	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
1225	uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. /
1226	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
1227	} n;
1228	/** The 32-bit unsigned integer view. */
1229	uint32_t au32[4];
1230	} EVT_INVALID_DEV_REQ_T;
1231	AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1232
1233	/**
1234	* Event Log Entry: EVENT_COUNTER_ZERO.
1235	* In accordance with the AMD spec.
1236	*/
1237	typedef union
1238	{
1239	struct
1240	{
1241	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1242	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1243	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1244	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
1245	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
1246	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
1247	} n;
1248	/** The 32-bit unsigned integer view. */
1249	uint32_t au32[4];
1250	} EVT_EVENT_COUNTER_ZERO_T;
1251	AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1252
1253	/**
1254	* IOMMU Capability Header (PCI).
1255	* In accordance with the AMD spec.
1256	*/
1257	typedef union
1258	{
1259	struct
1260	{
1261	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
1262	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
1263	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
1264	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
1265	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
1266	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
1267	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
1268	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
1269	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
1270	uint32_t u3Rsvd0 : 3; /*< Bits 31:29 - Reserved. /
1271	} n;
1272	/** The 32-bit unsigned integer view. */
1273	uint32_t u32;
1274	} IOMMU_CAP_HDR_T;
1275	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1276
1277	/**
1278	* IOMMU Base Address (Lo and Hi) Register (PCI).
1279	* In accordance with the AMD spec.
1280	*/
1281	typedef union
1282	{
1283	struct
1284	{
1285	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1286	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1287	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1288	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1289	} n;
1290	/** The 32-bit unsigned integer view. */
1291	uint32_t au32[2];
1292	/** The 64-bit unsigned integer view. */
1293	uint64_t u64;
1294	} IOMMU_BAR_T;
1295	AssertCompileSize(IOMMU_BAR_T, 8);
1296	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1297
1298	/**
1299	* IOMMU Range Register (PCI).
1300	* In accordance with the AMD spec.
1301	*/
1302	typedef union
1303	{
1304	struct
1305	{
1306	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1307	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1308	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1309	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1310	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1311	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1312	} n;
1313	/** The 32-bit unsigned integer view. */
1314	uint32_t u32;
1315	} IOMMU_RANGE_T;
1316	AssertCompileSize(IOMMU_RANGE_T, 4);
1317
1318	/**
1319	* Device Table Base Address Register (MMIO).
1320	* In accordance with the AMD spec.
1321	*/
1322	typedef union
1323	{
1324	struct
1325	{
1326	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1327	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1328	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1329	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1330	} n;
1331	/** The 64-bit unsigned integer view. */
1332	uint64_t u64;
1333	} DEV_TAB_BAR_T;
1334	AssertCompileSize(DEV_TAB_BAR_T, 8);
1335	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1336	#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1337
1338	/**
1339	* Command Buffer Base Address Register (MMIO).
1340	* In accordance with the AMD spec.
1341	*/
1342	typedef union
1343	{
1344	struct
1345	{
1346	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1347	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1348	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1349	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1350	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1351	} n;
1352	/** The 64-bit unsigned integer view. */
1353	uint64_t u64;
1354	} CMD_BUF_BAR_T;
1355	AssertCompileSize(CMD_BUF_BAR_T, 8);
1356	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1357
1358	/**
1359	* Event Log Base Address Register (MMIO).
1360	* In accordance with the AMD spec.
1361	*/
1362	typedef union
1363	{
1364	struct
1365	{
1366	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1367	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1368	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1369	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - EventLen: Event log length. /
1370	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1371	} n;
1372	/** The 64-bit unsigned integer view. */
1373	uint64_t u64;
1374	} EVT_LOG_BAR_T;
1375	AssertCompileSize(EVT_LOG_BAR_T, 8);
1376	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1377
1378	/**
1379	* IOMMU Control Register (MMIO).
1380	* In accordance with the AMD spec.
1381	*/
1382	typedef union
1383	{
1384	struct
1385	{
1386	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1387	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1388	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1389	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1390	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1391	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1392	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1393	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1394	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1395	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1396	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1397	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1398	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1399	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1400	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1401	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1402	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1403	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1404	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1405	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1406	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1407	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1408	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1409	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1410	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1411	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1412	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1413	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1414	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1415	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1416	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1417	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1418	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1419	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1420	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1421	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1422	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1423	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1424	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1425	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1426	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1427	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1428	} n;
1429	/** The 64-bit unsigned integer view. */
1430	uint64_t u64;
1431	} IOMMU_CTRL_T;
1432	AssertCompileSize(IOMMU_CTRL_T, 8);
1433	#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1434	#define IOMMU_CTRL_CMD_BUF_EN_MASK UINT64_C(0x0000000000001001)
1435
1436	/**
1437	* IOMMU Exclusion Base Register (MMIO).
1438	* In accordance with the AMD spec.
1439	*/
1440	typedef union
1441	{
1442	struct
1443	{
1444	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1445	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1446	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1447	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1448	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1449	} n;
1450	/** The 64-bit unsigned integer view. */
1451	uint64_t u64;
1452	} IOMMU_EXCL_RANGE_BAR_T;
1453	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1454	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1455
1456	/**
1457	* IOMMU Exclusion Range Limit Register (MMIO).
1458	* In accordance with the AMD spec.
1459	*/
1460	typedef union
1461	{
1462	struct
1463	{
1464	RT_GCC_EXTENSION uint64_t u52ExclLimit : 52; /*< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). /
1465	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1466	} n;
1467	/** The 64-bit unsigned integer view. */
1468	uint64_t u64;
1469	} IOMMU_EXCL_RANGE_LIMIT_T;
1470	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1471	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1472
1473	/**
1474	* IOMMU Extended Feature Register (MMIO).
1475	* In accordance with the AMD spec.
1476	*/
1477	typedef union
1478	{
1479	struct
1480	{
1481	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1482	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1483	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1484	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1485	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations (for GVAs) Support. /
1486	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1487	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1488	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1489	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1490	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1491	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1492	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1493	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1494	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1495	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1496	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1497	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1498	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1499	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1500	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1501	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1502	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1503	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1504	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1505	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1506	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1507	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1508	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1509	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1510	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1511	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1512	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1513	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1514	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1515	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1516	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1517	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1518	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1519	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1520	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1521	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1522	} n;
1523	/** The 64-bit unsigned integer view. */
1524	uint64_t u64;
1525	} IOMMU_EXT_FEAT_T;
1526	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1527
1528	/**
1529	* Peripheral Page Request Log Base Address Register (MMIO).
1530	* In accordance with the AMD spec.
1531	*/
1532	typedef union
1533	{
1534	struct
1535	{
1536	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1537	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1538	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1539	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1540	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1541	} n;
1542	/** The 64-bit unsigned integer view. */
1543	uint64_t u64;
1544	} PPR_LOG_BAR_T;
1545	AssertCompileSize(PPR_LOG_BAR_T, 8);
1546	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1547
1548	/**
1549	* IOMMU Hardware Event Upper Register (MMIO).
1550	* In accordance with the AMD spec.
1551	*/
1552	typedef union
1553	{
1554	struct
1555	{
1556	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1557	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1558	} n;
1559	/** The 64-bit unsigned integer view. */
1560	uint64_t u64;
1561	} IOMMU_HW_EVT_HI_T;
1562	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1563
1564	/**
1565	* IOMMU Hardware Event Lower Register (MMIO).
1566	* In accordance with the AMD spec.
1567	*/
1568	typedef uint64_t IOMMU_HW_EVT_LO_T;
1569
1570	/**
1571	* IOMMU Hardware Event Status (MMIO).
1572	* In accordance with the AMD spec.
1573	*/
1574	typedef union
1575	{
1576	struct
1577	{
1578	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1579	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1580	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1581	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1582	} n;
1583	/** The 64-bit unsigned integer view. */
1584	uint64_t u64;
1585	} IOMMU_HW_EVT_STATUS_T;
1586	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1587	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1588
1589	/**
1590	* Guest Virtual-APIC Log Base Address Register (MMIO).
1591	* In accordance with the AMD spec.
1592	*/
1593	typedef union
1594	{
1595	struct
1596	{
1597	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1598	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1599	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1600	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1601	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1602	} n;
1603	/** The 64-bit unsigned integer view. */
1604	uint64_t u64;
1605	} GALOG_BAR_T;
1606	AssertCompileSize(GALOG_BAR_T, 8);
1607
1608	/**
1609	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1610	* In accordance with the AMD spec.
1611	*/
1612	typedef union
1613	{
1614	struct
1615	{
1616	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1617	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1618	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1619	} n;
1620	/** The 64-bit unsigned integer view. */
1621	uint64_t u64;
1622	} GALOG_TAIL_ADDR_T;
1623	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1624
1625	/**
1626	* PPR Log B Base Address Register (MMIO).
1627	* In accordance with the AMD spec.
1628	* Currently identical to PPR_LOG_BAR_T.
1629	*/
1630	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1631
1632	/**
1633	* Event Log B Base Address Register (MMIO).
1634	* In accordance with the AMD spec.
1635	* Currently identical to EVT_LOG_BAR_T.
1636	*/
1637	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1638
1639	/**
1640	* Device-specific Feature Extension (DSFX) Register (MMIO).
1641	* In accordance with the AMD spec.
1642	*/
1643	typedef union
1644	{
1645	struct
1646	{
1647	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1648	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1649	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1650	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1651	} n;
1652	/** The 64-bit unsigned integer view. */
1653	uint64_t u64;
1654	} DEV_SPECIFIC_FEAT_T;
1655	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1656
1657	/**
1658	* Device-specific Control Extension (DSCX) Register (MMIO).
1659	* In accordance with the AMD spec.
1660	*/
1661	typedef union
1662	{
1663	struct
1664	{
1665	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1666	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1667	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1668	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1669	} n;
1670	/** The 64-bit unsigned integer view. */
1671	uint64_t u64;
1672	} DEV_SPECIFIC_CTRL_T;
1673	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1674
1675	/**
1676	* Device-specific Status Extension (DSSX) Register (MMIO).
1677	* In accordance with the AMD spec.
1678	*/
1679	typedef union
1680	{
1681	struct
1682	{
1683	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1684	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1685	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1686	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1687	} n;
1688	/** The 64-bit unsigned integer view. */
1689	uint64_t u64;
1690	} DEV_SPECIFIC_STATUS_T;
1691	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1692
1693	/**
1694	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1695	* In accordance with the AMD spec.
1696	*/
1697	typedef union
1698	{
1699	struct
1700	{
1701	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1702	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1703	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1704	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1705	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1706	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1707	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1708	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1709	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1710	} n;
1711	/** The 32-bit unsigned integer view. */
1712	uint32_t au32[2];
1713	/** The 64-bit unsigned integer view. */
1714	uint64_t u64;
1715	} MSI_MISC_INFO_T;
1716	AssertCompileSize(MSI_MISC_INFO_T, 8);
1717	/** MSI Vector Register 0 and 1 (MMIO). */
1718	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1719
1720	/**
1721	* MSI Capability Header Register (PCI + MMIO).
1722	* In accordance with the AMD spec.
1723	*/
1724	typedef union
1725	{
1726	struct
1727	{
1728	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1729	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1730	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1731	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1732	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1733	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1734	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1735	} n;
1736	/** The 32-bit unsigned integer view. */
1737	uint32_t u32;
1738	} MSI_CAP_HDR_T;
1739	AssertCompileSize(MSI_CAP_HDR_T, 4);
1740	#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1741
1742	/**
1743	* MSI Address Register (PCI + MMIO).
1744	* In accordance with the AMD spec.
1745	*/
1746	typedef union
1747	{
1748	struct
1749	{
1750	RT_GCC_EXTENSION uint64_t u2Rsvd : 2; /*< Bits 1:0 - Reserved. /
1751	RT_GCC_EXTENSION uint64_t u62MsiAddr : 62; /*< Bits 31:2 - MsiAddr: MSI Address. /
1752	} n;
1753	/** The 32-bit unsigned integer view. */
1754	uint32_t au32[2];
1755	/** The 64-bit unsigned integer view. */
1756	uint64_t u64;
1757	} MSI_ADDR_T;
1758	AssertCompileSize(MSI_ADDR_T, 8);
1759	#define IOMMU_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc)
1760
1761	/**
1762	* MSI Data Register (PCI + MMIO).
1763	* In accordance with the AMD spec.
1764	*/
1765	typedef union
1766	{
1767	struct
1768	{
1769	uint16_t u16MsiData; /*< Bits 15:0 - MsiData: MSI Data. /
1770	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1771	} n;
1772	/** The 32-bit unsigned integer view. */
1773	uint32_t u32;
1774	} MSI_DATA_T;
1775	AssertCompileSize(MSI_DATA_T, 4);
1776	#define IOMMU_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff)
1777
1778	/**
1779	* MSI Mapping Capability Header Register (PCI + MMIO).
1780	* In accordance with the AMD spec.
1781	*/
1782	typedef union
1783	{
1784	struct
1785	{
1786	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1787	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1788	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1789	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1790	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1791	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1792	} n;
1793	/** The 32-bit unsigned integer view. */
1794	uint32_t u32;
1795	} MSI_MAP_CAP_HDR_T;
1796	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1797
1798	/**
1799	* Performance Optimization Control Register (MMIO).
1800	* In accordance with the AMD spec.
1801	*/
1802	typedef union
1803	{
1804	struct
1805	{
1806	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1807	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1808	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1809	} n;
1810	/** The 32-bit unsigned integer view. */
1811	uint32_t u32;
1812	} IOMMU_PERF_OPT_CTRL_T;
1813	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1814
1815	/**
1816	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1817	* In accordance with the AMD spec.
1818	*/
1819	typedef union
1820	{
1821	struct
1822	{
1823	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1824	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1825	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1826	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1827	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1828	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1829	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1830	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1831	} n;
1832	/** The 64-bit unsigned integer view. */
1833	uint64_t u64;
1834	} IOMMU_XT_GEN_INTR_CTRL_T;
1835	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1836
1837	/**
1838	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1839	* In accordance with the AMD spec.
1840	*/
1841	typedef union
1842	{
1843	struct
1844	{
1845	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1846	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1847	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1848	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1849	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1850	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1851	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1852	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1853	} n;
1854	/** The 64-bit unsigned integer view. */
1855	uint64_t u64;
1856	} IOMMU_XT_INTR_CTRL_T;
1857	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1858
1859	/**
1860	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1861	* In accordance with the AMD spec.
1862	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1863	*/
1864	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1865
1866	/**
1867	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1868	* In accordance with the AMD spec.
1869	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1870	*/
1871	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1872
1873	/**
1874	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1875	* In accordance with the AMD spec.
1876	*/
1877	typedef union
1878	{
1879	struct
1880	{
1881	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1882	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1883	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1884	} n;
1885	/** The 64-bit unsigned integer view. */
1886	uint64_t u64;
1887	} MARC_APER_BAR_T;
1888	AssertCompileSize(MARC_APER_BAR_T, 8);
1889
1890	/**
1891	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1892	* In accordance with the AMD spec.
1893	*/
1894	typedef union
1895	{
1896	struct
1897	{
1898	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1899	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1900	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1901	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1902	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1903	} n;
1904	/** The 64-bit unsigned integer view. */
1905	uint64_t u64;
1906	} MARC_APER_RELOC_T;
1907	AssertCompileSize(MARC_APER_RELOC_T, 8);
1908
1909	/**
1910	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1911	* In accordance with the AMD spec.
1912	*/
1913	typedef union
1914	{
1915	struct
1916	{
1917	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1918	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1919	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1920	} n;
1921	/** The 64-bit unsigned integer view. */
1922	uint64_t u64;
1923	} MARC_APER_LEN_T;
1924
1925	/**
1926	* Memory Access and Routing Control (MARC) Aperture Register.
1927	* This combines other registers to match the MMIO layout for convenient access.
1928	*/
1929	typedef struct
1930	{
1931	MARC_APER_BAR_T Base;
1932	MARC_APER_RELOC_T Reloc;
1933	MARC_APER_LEN_T Length;
1934	} MARC_APER_T;
1935	AssertCompileSize(MARC_APER_T, 24);
1936
1937	/**
1938	* IOMMU Reserved Register (MMIO).
1939	* In accordance with the AMD spec.
1940	* This register is reserved for hardware use (although RW?).
1941	*/
1942	typedef uint64_t IOMMU_RSVD_REG_T;
1943
1944	/**
1945	* Command Buffer Head Pointer Register (MMIO).
1946	* In accordance with the AMD spec.
1947	*/
1948	typedef union
1949	{
1950	struct
1951	{
1952	uint32_t off; /*< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). /
1953	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1954	} n;
1955	/** The 32-bit unsigned integer view. */
1956	uint32_t au32[2];
1957	/** The 64-bit unsigned integer view. */
1958	uint64_t u64;
1959	} CMD_BUF_HEAD_PTR_T;
1960	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1961	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1962
1963	/**
1964	* Command Buffer Tail Pointer Register (MMIO).
1965	* In accordance with the AMD spec.
1966	* Currently identical to CMD_BUF_HEAD_PTR_T.
1967	*/
1968	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1969	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1970
1971	/**
1972	* Event Log Head Pointer Register (MMIO).
1973	* In accordance with the AMD spec.
1974	* Currently identical to CMD_BUF_HEAD_PTR_T.
1975	*/
1976	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1977	#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1978
1979	/**
1980	* Event Log Tail Pointer Register (MMIO).
1981	* In accordance with the AMD spec.
1982	* Currently identical to CMD_BUF_HEAD_PTR_T.
1983	*/
1984	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1985	#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1986
1987
1988	/**
1989	* IOMMU Status Register (MMIO).
1990	* In accordance with the AMD spec.
1991	*/
1992	typedef union
1993	{
1994	struct
1995	{
1996	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
1997	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
1998	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
1999	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
2000	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
2001	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
2002	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
2003	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
2004	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
2005	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
2006	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
2007	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
2008	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
2009	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
2010	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
2011	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
2012	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
2013	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
2014	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
2015	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
2016	} n;
2017	/** The 32-bit unsigned integer view. */
2018	uint32_t au32[2];
2019	/** The 64-bit unsigned integer view. */
2020	uint64_t u64;
2021	} IOMMU_STATUS_T;
2022	AssertCompileSize(IOMMU_STATUS_T, 8);
2023	#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
2024	#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
2025
2026	/**
2027	* PPR Log Head Pointer Register (MMIO).
2028	* In accordance with the AMD spec.
2029	* Currently identical to CMD_BUF_HEAD_PTR_T.
2030	*/
2031	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
2032
2033	/**
2034	* PPR Log Tail Pointer Register (MMIO).
2035	* In accordance with the AMD spec.
2036	* Currently identical to CMD_BUF_HEAD_PTR_T.
2037	*/
2038	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
2039
2040	/**
2041	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
2042	* In accordance with the AMD spec.
2043	*/
2044	typedef union
2045	{
2046	struct
2047	{
2048	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
2049	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
2050	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
2051	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2052	} n;
2053	/** The 32-bit unsigned integer view. */
2054	uint32_t au32[2];
2055	/** The 64-bit unsigned integer view. */
2056	uint64_t u64;
2057	} GALOG_HEAD_PTR_T;
2058	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
2059
2060	/**
2061	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
2062	* In accordance with the AMD spec.
2063	* Currently identical to GALOG_HEAD_PTR_T.
2064	*/
2065	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
2066
2067	/**
2068	* PPR Log B Head Pointer Register (MMIO).
2069	* In accordance with the AMD spec.
2070	* Currently identical to CMD_BUF_HEAD_PTR_T.
2071	*/
2072	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
2073
2074	/**
2075	* PPR Log B Tail Pointer Register (MMIO).
2076	* In accordance with the AMD spec.
2077	* Currently identical to CMD_BUF_HEAD_PTR_T.
2078	*/
2079	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
2080
2081	/**
2082	* Event Log B Head Pointer Register (MMIO).
2083	* In accordance with the AMD spec.
2084	* Currently identical to CMD_BUF_HEAD_PTR_T.
2085	*/
2086	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
2087
2088	/**
2089	* Event Log B Tail Pointer Register (MMIO).
2090	* In accordance with the AMD spec.
2091	* Currently identical to CMD_BUF_HEAD_PTR_T.
2092	*/
2093	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
2094
2095	/**
2096	* PPR Log Auto Response Register (MMIO).
2097	* In accordance with the AMD spec.
2098	*/
2099	typedef union
2100	{
2101	struct
2102	{
2103	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
2104	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
2105	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
2106	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
2107	} n;
2108	/** The 32-bit unsigned integer view. */
2109	uint32_t au32[2];
2110	/** The 64-bit unsigned integer view. */
2111	uint64_t u64;
2112	} PPR_LOG_AUTO_RESP_T;
2113	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
2114
2115	/**
2116	* PPR Log Overflow Early Indicator Register (MMIO).
2117	* In accordance with the AMD spec.
2118	*/
2119	typedef union
2120	{
2121	struct
2122	{
2123	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
2124	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
2125	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
2126	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
2127	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2128	} n;
2129	/** The 32-bit unsigned integer view. */
2130	uint32_t au32[2];
2131	/** The 64-bit unsigned integer view. */
2132	uint64_t u64;
2133	} PPR_LOG_OVERFLOW_EARLY_T;
2134	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2135
2136	/**
2137	* PPR Log B Overflow Early Indicator Register (MMIO).
2138	* In accordance with the AMD spec.
2139	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2140	*/
2141	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2142
2143	/**
2144	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2145	* In accordance with the AMD spec.
2146	*/
2147	typedef enum EVT_ILLEGAL_DTE_TYPE_T
2148	{
2149	kIllegalDteType_RsvdNotZero = 0,
2150	kIllegalDteType_RsvdIntTab,
2151	kIllegalDteType_RsvdIoCtl,
2152	kIllegalDteType_RsvdIntCtl
2153	} EVT_ILLEGAL_DTE_TYPE_T;
2154
2155	/**
2156	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2157	* In accordance with the AMD spec.
2158	*/
2159	typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2160	{
2161	/* Memory transaction. */
2162	kIoPageFaultType_DteRsvdPagingMode = 0,
2163	kIoPageFaultType_PteInvalidPageSize,
2164	kIoPageFaultType_PteInvalidLvlEncoding,
2165	kIoPageFaultType_SkippedLevelIovaNotZero,
2166	kIoPageFaultType_PteRsvdNotZero,
2167	kIoPageFaultType_PteValidNotSet,
2168	kIoPageFaultType_DteTranslationDisabled,
2169	kIoPageFaultType_PasidInvalidRange,
2170	kIoPageFaultType_PermDenied,
2171	kIoPageFaultType_UserSupervisor,
2172	/* Interrupt remapping */
2173	kIoPageFaultType_IrteAddrInvalid,
2174	kIoPageFaultType_IrteRsvdNotZero,
2175	kIoPageFaultType_IrteRemapEn,
2176	kIoPageFaultType_IrteRsvdIntType,
2177	kIoPageFaultType_IntrReqAborted,
2178	kIoPageFaultType_IntrWithPasid,
2179	kIoPageFaultType_SmiFilterMismatch,
2180	/* Memory transaction or interrupt remapping. */
2181	kIoPageFaultType_DevId_Invalid
2182	} EVT_IO_PAGE_FAULT_TYPE_T;
2183
2184	/**
2185	* ILLEGAL_COMMAND_ERROR Event Types.
2186	* In accordance with the AMD spec.
2187	*/
2188	typedef enum EVT_ILLEGAL_CMD_ERR_TYPE_T
2189	{
2190	kIllegalCmdErrType_RsvdNotZero = 0,
2191	kIllegalCmdErrType_CmdNotSupported,
2192	kIllegalCmdErrType_IotlbNotSupported
2193	} EVT_ILLEGAL_CMD_ERR_TYPE_T;
2194	/** Pointer to an illegal command error event type. */
2195	typedef EVT_ILLEGAL_CMD_ERR_TYPE_T *PEVT_ILLEGAL_CMD_ERR_TYPE_T;
2196
2197	/**
2198	* IOTLB_INV_TIMEOUT Event Types.
2199	* In accordance with the AMD spec.
2200	*/
2201	typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2202	{
2203	InvTimeoutType_NoResponse = 0
2204	} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2205
2206	/**
2207	* INVALID_DEVICE_REQUEST Event Types.
2208	* In accordance with the AMD spec.
2209	*/
2210	typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2211	{
2212	/* Access. */
2213	kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2214	kInvalidDevReqType_PretranslatedTransaction,
2215	kInvalidDevReqType_PortIo,
2216	kInvalidDevReqType_SysMgt,
2217	kInvalidDevReqType_IntrRange,
2218	kInvalidDevReqType_RsvdIntrRange,
2219	kInvalidDevReqType_SysMgtAddr,
2220	/* Translation Request. */
2221	kInvalidDevReqType_TrAccessInvalid,
2222	kInvalidDevReqType_TrDisabled,
2223	kInvalidDevReqType_DevIdInvalid,
2224	} EVT_INVALID_DEV_REQ_TYPE_T;
2225
2226	/**
2227	* INVALID_PPR_REQUEST Event Types.
2228	* In accordance with the AMD spec.
2229	*/
2230	typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2231	{
2232	kInvalidPprReqType_PriNotSupported,
2233	kInvalidPprReqType_GstTranslateDisabled
2234	} EVT_INVALID_PPR_REQ_TYPE_T;
2235
2236	/**
2237	* IOMMU operations (transaction) types.
2238	*/
2239	typedef enum IOMMUOP
2240	{
2241	/** Address translation request. */
2242	IOMMUOP_TRANSLATE_REQ = 0,
2243	/** Memory read request. */
2244	IOMMUOP_MEM_READ,
2245	/** Memory write request. */
2246	IOMMUOP_MEM_WRITE,
2247	/** Interrupt request. */
2248	IOMMUOP_INTR_REQ,
2249	/** Command. */
2250	IOMMUOP_CMD
2251	} IOMMUOP;
2252	AssertCompileSize(IOMMUOP, 4);
2253
2254	/**
2255	* I/O page walk result.
2256	*/
2257	typedef struct
2258	{
2259	/** The translated system physical address. */
2260	RTGCPHYS GCPhysSpa;
2261	/** The number of offset bits in the system physical address. */
2262	uint8_t cShift;
2263	/** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
2264	uint8_t fIoPerm;
2265	/** Padding. */
2266	uint8_t abPadding[2];
2267	} IOWALKRESULT;
2268	/** Pointer to an I/O walk result struct. */
2269	typedef IOWALKRESULT *PIOWALKRESULT;
2270	/** Pointer to a const I/O walk result struct. */
2271	typedef IOWALKRESULT *PCIOWALKRESULT;
2272
2273	/**
2274	* IOMMU I/O TLB Entry.
2275	* @note Update iommuAmdInitIotlbe() when changes are made.
2276	*/
2277	typedef struct
2278	{
2279	/** Magic (IOMMU_IOTLBE_MAGIC). */
2280	uint32_t uMagic;
2281	/** Reserved for future (eviction hints?). */
2282	uint16_t uRsvd0;
2283	/** The I/O access permissions (IOMMU_IO_PERM_XXX). */
2284	uint8_t fIoPerm;
2285	/** The number of offset bits in the system physical address. */
2286	uint8_t cShift;
2287	/** The translated system physical address (SPA) of the page. */
2288	RTGCPHYS GCPhysSpa;
2289	} IOTLBE_T;
2290	AssertCompileSizeAlignment(IOTLBE_T, 8);
2291	AssertCompileMemberAlignment(IOTLBE_T, GCPhysSpa, 8);
2292	/** Pointer to an IOMMU I/O TLB entry struct. */
2293	typedef IOTLBE_T *PIOTLBE_T;
2294	/** Pointer to a const IOMMU I/O TLB entry struct. */
2295	typedef IOTLBE_T const *PCIOTLBE_T;
2296
2297	/**
2298	* The shared IOMMU device state.
2299	*/
2300	typedef struct IOMMU
2301	{
2302	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
2303	uint32_t idxIommu;
2304	/** Alignment padding. */
2305	uint32_t uPadding0;
2306
2307	/** Whether the command thread is sleeping. */
2308	bool volatile fCmdThreadSleeping;
2309	/** Alignment padding. */
2310	uint8_t afPadding0[3];
2311	/** Whether the command thread has been signaled for wake up. */
2312	bool volatile fCmdThreadSignaled;
2313	/** Alignment padding. */
2314	uint8_t afPadding1[3];
2315
2316	/** The event semaphore the command thread waits on. */
2317	SUPSEMEVENT hEvtCmdThread;
2318	/** The MMIO handle. */
2319	IOMMMIOHANDLE hMmio;
2320
2321	/** @name PCI: Base capability block registers.
2322	* @{ */
2323	IOMMU_BAR_T IommuBar; /*< IOMMU base address register. /
2324	/** @} */
2325
2326	/** @name MMIO: Control and status registers.
2327	* @{ */
2328	DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /*< Device table base address registers. /
2329	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
2330	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
2331	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
2332	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
2333	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
2334	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
2335	/** @} */
2336
2337	/** @name MMIO: PPR Log registers.
2338	* @{ */
2339	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
2340	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
2341	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
2342	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
2343	/** @} */
2344
2345	/** @todo IOMMU: SMI filter. */
2346
2347	/** @name MMIO: Guest Virtual-APIC Log registers.
2348	* @{ */
2349	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
2350	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
2351	/** @} */
2352
2353	/** @name MMIO: Alternate PPR and Event Log registers.
2354	* @{ */
2355	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
2356	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
2357	/** @} */
2358
2359	/** @name MMIO: Device-specific feature registers.
2360	* @{ */
2361	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
2362	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
2363	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
2364	/** @} */
2365
2366	/** @name MMIO: MSI Capability Block registers.
2367	* @{ */
2368	MSI_MISC_INFO_T MsiMiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
2369	/** @} */
2370
2371	/** @name MMIO: Performance Optimization Control registers.
2372	* @{ */
2373	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
2374	/** @} */
2375
2376	/** @name MMIO: x2APIC Control registers.
2377	* @{ */
2378	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
2379	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
2380	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
2381	/** @} */
2382
2383	/** @name MMIO: MARC registers.
2384	* @{ */
2385	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
2386	/** @} */
2387
2388	/** @name MMIO: Reserved register.
2389	* @{ */
2390	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
2391	/** @} */
2392
2393	/** @name MMIO: Command and Event Log pointer registers.
2394	* @{ */
2395	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
2396	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
2397	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
2398	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
2399	/** @} */
2400
2401	/** @name MMIO: Command and Event Status register.
2402	* @{ */
2403	IOMMU_STATUS_T Status; /*< IOMMU status register. /
2404	/** @} */
2405
2406	/** @name MMIO: PPR Log Head and Tail pointer registers.
2407	* @{ */
2408	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
2409	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
2410	/** @} */
2411
2412	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
2413	* @{ */
2414	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
2415	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
2416	/** @} */
2417
2418	/** @name MMIO: PPR Log B Head and Tail pointer registers.
2419	* @{ */
2420	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
2421	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
2422	/** @} */
2423
2424	/** @name MMIO: Event Log B Head and Tail pointer registers.
2425	* @{ */
2426	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
2427	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
2428	/** @} */
2429
2430	/** @name MMIO: PPR Log Overflow protection registers.
2431	* @{ */
2432	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
2433	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
2434	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
2435	/** @} */
2436
2437	/** @todo IOMMU: IOMMU Event counter registers. */
2438
2439	/** @todo IOMMU: Stat counters. */
2440	} IOMMU;
2441	/** Pointer to the IOMMU device state. */
2442	typedef struct IOMMU *PIOMMU;
2443	/** Pointer to the const IOMMU device state. */
2444	typedef const struct IOMMU *PCIOMMU;
2445	AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
2446	AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
2447	AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
2448	AssertCompileMemberAlignment(IOMMU, hMmio, 8);
2449	AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
2450
2451	/**
2452	* The ring-3 IOMMU device state.
2453	*/
2454	typedef struct IOMMUR3
2455	{
2456	/** Device instance. */
2457	PPDMDEVINSR3 pDevInsR3;
2458	/** The IOMMU helpers. */
2459	PCPDMIOMMUHLPR3 pIommuHlpR3;
2460	/** The command thread handle. */
2461	R3PTRTYPE(PPDMTHREAD) pCmdThread;
2462	} IOMMUR3;
2463	/** Pointer to the ring-3 IOMMU device state. */
2464	typedef IOMMUR3 *PIOMMUR3;
2465
2466	/**
2467	* The ring-0 IOMMU device state.
2468	*/
2469	typedef struct IOMMUR0
2470	{
2471	/** Device instance. */
2472	PPDMDEVINSR0 pDevInsR0;
2473	/** The IOMMU helpers. */
2474	PCPDMIOMMUHLPR0 pIommuHlpR0;
2475	} IOMMUR0;
2476	/** Pointer to the ring-0 IOMMU device state. */
2477	typedef IOMMUR0 *PIOMMUR0;
2478
2479	/**
2480	* The raw-mode IOMMU device state.
2481	*/
2482	typedef struct IOMMURC
2483	{
2484	/** Device instance. */
2485	PPDMDEVINSR0 pDevInsRC;
2486	/** The IOMMU helpers. */
2487	PCPDMIOMMUHLPRC pIommuHlpRC;
2488	} IOMMURC;
2489	/** Pointer to the raw-mode IOMMU device state. */
2490	typedef IOMMURC *PIOMMURC;
2491
2492	/** The IOMMU device state for the current context. */
2493	typedef CTX_SUFF(IOMMU) IOMMUCC;
2494	/** Pointer to the IOMMU device state for the current context. */
2495	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
2496
2497	/**
2498	* IOMMU register access routines.
2499	*/
2500	typedef struct
2501	{
2502	const char *pszName;
2503	VBOXSTRICTRC (pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t pu64Value);
2504	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
2505	bool f64BitReg;
2506	} IOMMUREGACC;
2507
2508
2509	/*********************************************************************************************************************************
2510	* Global Variables *
2511	*********************************************************************************************************************************/
2512	/**
2513	* An array of the number of device table segments supported.
2514	* Indexed by u2DevTabSegSup.
2515	*/
2516	static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
2517
2518	/**
2519	* An array of the masks to select the device table segment index from a device ID.
2520	*/
2521	static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
2522
2523	/**
2524	* The maximum size (inclusive) of each device table segment (0 to 7).
2525	* Indexed by the device table segment index.
2526	*/
2527	static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
2528
2529
2530	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
2531	/**
2532	* Gets the maximum number of buffer entries for the given buffer length.
2533	*
2534	* @returns Number of buffer entries.
2535	* @param uEncodedLen The length (power-of-2 encoded).
2536	*/
2537	DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
2538	{
2539	Assert(uEncodedLen > 7);
2540	return 2 << (uEncodedLen - 1);
2541	}
2542
2543
2544	/**
2545	* Gets the total length of the buffer given a base register's encoded length.
2546	*
2547	* @returns The length of the buffer in bytes.
2548	* @param uEncodedLen The length (power-of-2 encoded).
2549	*/
2550	DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
2551	{
2552	Assert(uEncodedLen > 7);
2553	return (2 << (uEncodedLen - 1)) << 4;
2554	}
2555
2556
2557	/**
2558	* Gets the number of (unconsumed) entries in the event log.
2559	*
2560	* @returns The number of entries in the event log.
2561	* @param pThis The IOMMU device state.
2562	*/
2563	static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
2564	{
2565	uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2566	uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2567	if (idxTail >= idxHead)
2568	return idxTail - idxHead;
2569
2570	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2571	return cMaxEvts - idxHead + idxTail;
2572	}
2573
2574
2575	/**
2576	* Gets the number of (unconsumed) commands in the command buffer.
2577	*
2578	* @returns The number of commands in the command buffer.
2579	* @param pThis The IOMMU device state.
2580	*/
2581	static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
2582	{
2583	uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2584	uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2585	if (idxTail >= idxHead)
2586	return idxTail - idxHead;
2587
2588	uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
2589	return cMaxCmds - idxHead + idxTail;
2590	}
2591
2592
2593	DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
2594	{
2595	IOMMU_STATUS_T Status;
2596	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
2597	return Status;
2598	}
2599
2600
2601	DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
2602	{
2603	IOMMU_CTRL_T Ctrl;
2604	Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
2605	return Ctrl;
2606	}
2607
2608
2609	/**
2610	* Returns whether MSI is enabled for the IOMMU.
2611	*
2612	* @returns Whether MSI is enabled.
2613	* @param pDevIns The IOMMU device instance.
2614	*
2615	* @note There should be a PCIDevXxx function for this.
2616	*/
2617	static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
2618	{
2619	MSI_CAP_HDR_T MsiCapHdr;
2620	MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
2621	return MsiCapHdr.n.u1MsiEnable;
2622	}
2623
2624
2625	/**
2626	* Signals a PCI target abort.
2627	*
2628	* @param pDevIns The IOMMU device instance.
2629	*/
2630	static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
2631	{
2632	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2633	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2634	PDMPciDevSetStatus(pPciDev, u16Status);
2635	}
2636
2637
2638	/**
2639	* Wakes up the command thread if there are commands to be processed or if
2640	* processing is requested to be stopped by software.
2641	*
2642	* @param pDevIns The IOMMU device instance.
2643	*/
2644	static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
2645	{
2646	IOMMU_ASSERT_LOCKED(pDevIns);
2647
2648	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2649	if ( !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true)
2650	&& ASMAtomicReadBool(&pThis->fCmdThreadSleeping))
2651	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2652	}
2653
2654
2655	/**
2656	* Writes to a read-only register.
2657	*/
2658	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2659	{
2660	RT_NOREF(pDevIns, pThis, iReg, u64Value);
2661	Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
2662	return VINF_SUCCESS;
2663	}
2664
2665
2666	/**
2667	* Writes the Device Table Base Address Register.
2668	*/
2669	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2670	{
2671	RT_NOREF(pDevIns, iReg);
2672
2673	/* Mask out all unrecognized bits. */
2674	u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2675
2676	/* Update the register. */
2677	pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2678	return VINF_SUCCESS;
2679	}
2680
2681
2682	/**
2683	* Writes the Command Buffer Base Address Register.
2684	*/
2685	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2686	{
2687	RT_NOREF(pDevIns, iReg);
2688
2689	/*
2690	* While this is not explicitly specified like the event log base address register,
2691	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2692	* Inconsistent specs :/
2693	*/
2694	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2695	if (Status.n.u1CmdBufRunning)
2696	{
2697	Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2698	return VINF_SUCCESS;
2699	}
2700
2701	/* Mask out all unrecognized bits. */
2702	CMD_BUF_BAR_T CmdBufBaseAddr;
2703	CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2704
2705	/* Validate the length. */
2706	if (CmdBufBaseAddr.n.u4Len >= 8)
2707	{
2708	/* Update the register. */
2709	pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2710
2711	/*
2712	* Writing the command buffer base address, clears the command buffer head and tail pointers.
2713	* See AMD spec. 2.4 "Commands".
2714	*/
2715	pThis->CmdBufHeadPtr.u64 = 0;
2716	pThis->CmdBufTailPtr.u64 = 0;
2717	}
2718	else
2719	Log((IOMMU_LOG_PFX ": Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2720
2721	return VINF_SUCCESS;
2722	}
2723
2724
2725	/**
2726	* Writes the Event Log Base Address Register.
2727	*/
2728	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2729	{
2730	RT_NOREF(pDevIns, iReg);
2731
2732	/*
2733	* IOMMU behavior is undefined when software writes this register when event logging is running.
2734	* In our emulation, we ignore the write entirely.
2735	* See AMD IOMMU spec. "Event Log Base Address Register".
2736	*/
2737	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2738	if (Status.n.u1EvtLogRunning)
2739	{
2740	Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2741	return VINF_SUCCESS;
2742	}
2743
2744	/* Mask out all unrecognized bits. */
2745	u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2746	EVT_LOG_BAR_T EvtLogBaseAddr;
2747	EvtLogBaseAddr.u64 = u64Value;
2748
2749	/* Validate the length. */
2750	if (EvtLogBaseAddr.n.u4Len >= 8)
2751	{
2752	/* Update the register. */
2753	pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2754
2755	/*
2756	* Writing the event log base address, clears the event log head and tail pointers.
2757	* See AMD spec. 2.5 "Event Logging".
2758	*/
2759	pThis->EvtLogHeadPtr.u64 = 0;
2760	pThis->EvtLogTailPtr.u64 = 0;
2761	}
2762	else
2763	Log((IOMMU_LOG_PFX ": Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2764
2765	return VINF_SUCCESS;
2766	}
2767
2768
2769	/**
2770	* Writes the Control Register.
2771	*/
2772	static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2773	{
2774	RT_NOREF(pDevIns, iReg);
2775
2776	/* Mask out all unrecognized bits. */
2777	u64Value &= IOMMU_CTRL_VALID_MASK;
2778
2779	IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
2780	IOMMU_CTRL_T NewCtrl;
2781	NewCtrl.u64 = u64Value;
2782
2783	/* Update the register. */
2784	ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2785
2786	/* Enable or disable event logging when the bit transitions. */
2787	bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2788	bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2789	bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2790	if (fOldEvtLogEn != fNewEvtLogEn)
2791	{
2792	if ( fNewIommuEn
2793	&& fNewEvtLogEn)
2794	{
2795	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2796	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2797	}
2798	else
2799	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2800	}
2801
2802	/* Enable or disable command buffer processing when the bit transitions. */
2803	bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2804	bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2805	if (fOldCmdBufEn != fNewCmdBufEn)
2806	{
2807	if ( fNewIommuEn
2808	&& fNewCmdBufEn)
2809	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2810	else
2811	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2812
2813	/* Wake up the command thread to start or stop processing commands. */
2814	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2815	}
2816	}
2817
2818
2819	/**
2820	* Writes to the Excluse Range Base Address Register.
2821	*/
2822	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2823	{
2824	RT_NOREF(pDevIns, iReg);
2825	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2826	return VINF_SUCCESS;
2827	}
2828
2829
2830	/**
2831	* Writes to the Excluse Range Limit Register.
2832	*/
2833	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2834	{
2835	RT_NOREF(pDevIns, iReg);
2836	u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2837	u64Value \|= UINT64_C(0xfff);
2838	pThis->ExclRangeLimit.u64 = u64Value;
2839	return VINF_SUCCESS;
2840	}
2841
2842
2843	/**
2844	* Writes the Hardware Event Register (Hi).
2845	*/
2846	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2847	{
2848	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2849	RT_NOREF(pDevIns, iReg);
2850	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2851	pThis->HwEvtHi.u64 = u64Value;
2852	return VINF_SUCCESS;
2853	}
2854
2855
2856	/**
2857	* Writes the Hardware Event Register (Lo).
2858	*/
2859	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2860	{
2861	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2862	RT_NOREF(pDevIns, iReg);
2863	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2864	pThis->HwEvtLo = u64Value;
2865	return VINF_SUCCESS;
2866	}
2867
2868
2869	/**
2870	* Writes the Hardware Event Status Register.
2871	*/
2872	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2873	{
2874	RT_NOREF(pDevIns, iReg);
2875
2876	/* Mask out all unrecognized bits. */
2877	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2878
2879	/*
2880	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2881	* If the current status bits or the bits being written are both 0, we've nothing to do.
2882	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2883	*/
2884	uint64_t HwStatus = pThis->HwEvtStatus.u64;
2885	if (!(HwStatus & RT_BIT(0)))
2886	return VINF_SUCCESS;
2887	if (u64Value & HwStatus & RT_BIT_64(0))
2888	HwStatus &= ~RT_BIT_64(0);
2889	if (u64Value & HwStatus & RT_BIT_64(1))
2890	HwStatus &= ~RT_BIT_64(1);
2891
2892	/* Update the register. */
2893	pThis->HwEvtStatus.u64 = HwStatus;
2894	return VINF_SUCCESS;
2895	}
2896
2897
2898	/**
2899	* Writes the Device Table Segment Base Address Register.
2900	*/
2901	static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2902	{
2903	RT_NOREF(pDevIns);
2904
2905	/* Figure out which segment is being written. */
2906	uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2907	uint8_t const idxSegment = offSegment + 1;
2908	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2909
2910	/* Mask out all unrecognized bits. */
2911	u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2912	DEV_TAB_BAR_T DevTabSegBar;
2913	DevTabSegBar.u64 = u64Value;
2914
2915	/* Validate the size. */
2916	uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2917	uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2918	if (uSegSize <= uMaxSegSize)
2919	{
2920	/* Update the register. */
2921	pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2922	}
2923	else
2924	Log((IOMMU_LOG_PFX ": Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2925
2926	return VINF_SUCCESS;
2927	}
2928
2929
2930	/**
2931	* Writes the MSI Capability Header Register.
2932	*/
2933	static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2934	{
2935	RT_NOREF(pThis, iReg);
2936	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2937	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2938	MSI_CAP_HDR_T MsiCapHdr;
2939	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2940	MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2941	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2942	return VINF_SUCCESS;
2943	}
2944
2945
2946	/**
2947	* Writes the MSI Address (Lo) Register (32-bit).
2948	*/
2949	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2950	{
2951	RT_NOREF(pThis, iReg);
2952	Assert(!RT_HI_U32(u64Value));
2953	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2954	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2955	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & IOMMU_MSI_ADDR_VALID_MASK);
2956	return VINF_SUCCESS;
2957	}
2958
2959
2960	/**
2961	* Writes the MSI Address (Hi) Register (32-bit).
2962	*/
2963	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2964	{
2965	RT_NOREF(pThis, iReg);
2966	Assert(!RT_HI_U32(u64Value));
2967	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2968	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2969	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
2970	return VINF_SUCCESS;
2971	}
2972
2973
2974	/**
2975	* Writes the MSI Data Register (32-bit).
2976	*/
2977	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2978	{
2979	RT_NOREF(pThis, iReg);
2980	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2981	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2982	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & IOMMU_MSI_DATA_VALID_MASK);
2983	return VINF_SUCCESS;
2984	}
2985
2986
2987	/**
2988	* Writes the Command Buffer Head Pointer Register (32-bit).
2989	*/
2990	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2991	{
2992	RT_NOREF(pDevIns, iReg);
2993
2994	/*
2995	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
2996	* In our emulation, we ignore the write entirely.
2997	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2998	*/
2999	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3000	if (Status.n.u1CmdBufRunning)
3001	{
3002	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
3003	return VINF_SUCCESS;
3004	}
3005
3006	/*
3007	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3008	* In our emulation, we ignore the write entirely.
3009	*/
3010	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
3011	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3012	Assert(cbBuf <= _512K);
3013	if (offBuf >= cbBuf)
3014	{
3015	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
3016	offBuf, cbBuf));
3017	return VINF_SUCCESS;
3018	}
3019
3020	/* Update the register. */
3021	pThis->CmdBufHeadPtr.au32[0] = offBuf;
3022
3023	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
3024
3025	LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
3026	return VINF_SUCCESS;
3027	}
3028
3029
3030	/**
3031	* Writes the Command Buffer Tail Pointer Register (32-bit).
3032	*/
3033	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3034	{
3035	RT_NOREF(pDevIns, iReg);
3036
3037	/*
3038	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3039	* In our emulation, we ignore the write entirely.
3040	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3041	*/
3042	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
3043	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3044	Assert(cbBuf <= _512K);
3045	if (offBuf >= cbBuf)
3046	{
3047	Log((IOMMU_LOG_PFX ": Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3048	offBuf, cbBuf));
3049	return VINF_SUCCESS;
3050	}
3051
3052	/*
3053	* IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
3054	* head pointer after adding one or more commands to the buffer.
3055	*
3056	* However, we cannot enforce this strictly because it's legal for software to shrink the
3057	* command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
3058	* at 0). Software might even make the queue empty by making head and tail equal which is
3059	* allowed. I don't think we can or should try too hard to prevent software shooting itself
3060	* in the foot here. As long as we make sure the offset value is within the circular buffer
3061	* bounds (which we do by masking bits above) it should be sufficient.
3062	*/
3063	pThis->CmdBufTailPtr.au32[0] = offBuf;
3064
3065	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
3066
3067	LogFlow((IOMMU_LOG_PFX ": Set CmdBufTailPtr to %#RX32\n", offBuf));
3068	return VINF_SUCCESS;
3069	}
3070
3071
3072	/**
3073	* Writes the Event Log Head Pointer Register (32-bit).
3074	*/
3075	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3076	{
3077	RT_NOREF(pDevIns, iReg);
3078
3079	/*
3080	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3081	* In our emulation, we ignore the write entirely.
3082	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3083	*/
3084	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
3085	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3086	Assert(cbBuf <= _512K);
3087	if (offBuf >= cbBuf)
3088	{
3089	Log((IOMMU_LOG_PFX ": Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3090	offBuf, cbBuf));
3091	return VINF_SUCCESS;
3092	}
3093
3094	/* Update the register. */
3095	pThis->EvtLogHeadPtr.au32[0] = offBuf;
3096
3097	LogFlow((IOMMU_LOG_PFX ": Set EvtLogHeadPtr to %#RX32\n", offBuf));
3098	return VINF_SUCCESS;
3099	}
3100
3101
3102	/**
3103	* Writes the Event Log Tail Pointer Register (32-bit).
3104	*/
3105	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3106	{
3107	RT_NOREF(pDevIns, iReg);
3108	NOREF(pThis);
3109
3110	/*
3111	* IOMMU behavior is undefined when software writes this register when the event log is running.
3112	* In our emulation, we ignore the write entirely.
3113	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3114	*/
3115	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3116	if (Status.n.u1EvtLogRunning)
3117	{
3118	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
3119	return VINF_SUCCESS;
3120	}
3121
3122	/*
3123	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3124	* In our emulation, we ignore the write entirely.
3125	*/
3126	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
3127	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3128	Assert(cbBuf <= _512K);
3129	if (offBuf >= cbBuf)
3130	{
3131	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3132	offBuf, cbBuf));
3133	return VINF_SUCCESS;
3134	}
3135
3136	/* Update the register. */
3137	pThis->EvtLogTailPtr.au32[0] = offBuf;
3138
3139	LogFlow((IOMMU_LOG_PFX ": Set EvtLogTailPtr to %#RX32\n", offBuf));
3140	return VINF_SUCCESS;
3141	}
3142
3143
3144	/**
3145	* Writes the Status Register (64-bit).
3146	*/
3147	static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3148	{
3149	RT_NOREF(pDevIns, iReg);
3150
3151	/* Mask out all unrecognized bits. */
3152	u64Value &= IOMMU_STATUS_VALID_MASK;
3153
3154	/*
3155	* Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
3156	* Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
3157	*/
3158	IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
3159	uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
3160	uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
3161	uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
3162
3163	uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) \| fOldRoBits;
3164
3165	/* Update the register. */
3166	ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
3167	return VINF_SUCCESS;
3168	}
3169
3170
3171	#if 0
3172	/**
3173	* Table 0: Registers-access table.
3174	*/
3175	static const IOMMUREGACC g_aTable0Regs[] =
3176	{
3177
3178	};
3179
3180	/**
3181	* Table 1: Registers-access table.
3182	*/
3183	static const IOMMUREGACC g_aTable1Regs[] =
3184	{
3185	};
3186	#endif
3187
3188
3189	/**
3190	* Writes an IOMMU register (32-bit and 64-bit).
3191	*
3192	* @returns Strict VBox status code.
3193	* @param pDevIns The IOMMU device instance.
3194	* @param off MMIO byte offset to the register.
3195	* @param cb The size of the write access.
3196	* @param uValue The value being written.
3197	*
3198	* @thread EMT.
3199	*/
3200	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
3201	{
3202	Assert(off < IOMMU_MMIO_REGION_SIZE);
3203	Assert(cb == 4 \|\| cb == 8);
3204	Assert(!(off & (cb - 1)));
3205
3206	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3207	switch (off)
3208	{
3209	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
3210	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
3211	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
3212	case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
3213	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
3214	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
3215	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3216
3217	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3218	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
3219	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
3220	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
3221
3222	case IOMMU_MMIO_OFF_GALOG_BAR:
3223	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3224
3225	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
3226	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3227
3228	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3229	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3230	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3231	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3232	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3233	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3234	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
3235
3236	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
3237	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
3238	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3239
3240	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
3241	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3242	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3243	{
3244	VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
3245	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3246	return rcStrict;
3247	uValue >>= 32;
3248	RT_FALL_THRU();
3249	}
3250	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
3251	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3252	{
3253	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
3254	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3255	return rcStrict;
3256	uValue >>= 32;
3257	RT_FALL_THRU();
3258	}
3259	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
3260	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3261
3262	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3263
3264	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
3265	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
3266	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3267
3268	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
3269	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
3270	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
3271	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
3272	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
3273	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
3274	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
3275	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
3276	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
3277	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
3278	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
3279	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3280
3281	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3282
3283	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
3284	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
3285	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
3286	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
3287
3288	case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
3289
3290	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
3291	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
3292
3293	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
3294	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
3295
3296	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
3297	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
3298
3299	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
3300	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3301
3302	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
3303	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
3304	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
3305
3306	/* Not implemented. */
3307	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3308	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3309	{
3310	Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
3311	(off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3312	return VINF_SUCCESS;
3313	}
3314
3315	/* Unknown. */
3316	default:
3317	{
3318	Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
3319	return VINF_SUCCESS;
3320	}
3321	}
3322	}
3323
3324
3325	/**
3326	* Reads an IOMMU register (64-bit) given its MMIO offset.
3327	*
3328	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
3329	* boundary include the lower half of the subsequent register.
3330	*
3331	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
3332	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
3333	* software will only perform 32-bit reads on those 32-bit registers that are
3334	* aligned on 8-byte boundaries.
3335	*
3336	* @returns Strict VBox status code.
3337	* @param pDevIns The IOMMU device instance.
3338	* @param off The MMIO offset of the register in bytes.
3339	* @param puResult Where to store the value being read.
3340	*
3341	* @thread EMT.
3342	*/
3343	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
3344	{
3345	Assert(off < IOMMU_MMIO_REGION_SIZE);
3346	Assert(!(off & 7) \|\| !(off & 3));
3347
3348	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3349	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3350	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3351
3352	/** @todo IOMMU: fine-grained locking? */
3353	uint64_t uReg;
3354	switch (off)
3355	{
3356	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
3357	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
3358	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
3359	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
3360	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
3361	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
3362	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
3363
3364	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
3365	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
3366	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
3367	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
3368
3369	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
3370	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
3371
3372	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
3373	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
3374
3375	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3376	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3377	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3378	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3379	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3380	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3381	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
3382	{
3383	uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
3384	uint8_t const idxDevTabSeg = offDevTabSeg + 1;
3385	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3386	uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
3387	break;
3388	}
3389
3390	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
3391	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
3392	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
3393
3394	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MsiMiscInfo.u64; break;
3395	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MsiMiscInfo.au32[1]; break;
3396	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3397	{
3398	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3399	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3400	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
3401	break;
3402	}
3403	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
3404	{
3405	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3406	break;
3407	}
3408	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3409	{
3410	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3411	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3412	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
3413	break;
3414	}
3415	case IOMMU_MMIO_OFF_MSI_DATA:
3416	{
3417	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3418	break;
3419	}
3420	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
3421	{
3422	/*
3423	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
3424	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
3425	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
3426	* 0 for this register.
3427	*/
3428	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
3429	break;
3430	}
3431
3432	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
3433
3434	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
3435	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
3436	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
3437
3438	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
3439	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
3440	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
3441	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
3442	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
3443	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
3444	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
3445	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
3446	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
3447	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
3448	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
3449	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
3450
3451	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
3452
3453	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
3454	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
3455	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
3456	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
3457
3458	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
3459
3460	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
3461	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
3462
3463	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
3464	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
3465
3466	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
3467	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
3468
3469	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
3470	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
3471
3472	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
3473	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
3474	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
3475
3476	/* Not implemented. */
3477	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3478	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3479	{
3480	Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3481	uReg = 0;
3482	break;
3483	}
3484
3485	/* Unknown. */
3486	default:
3487	{
3488	Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
3489	uReg = 0;
3490	return VINF_IOM_MMIO_UNUSED_00;
3491	}
3492	}
3493
3494	*puResult = uReg;
3495	return VINF_SUCCESS;
3496	}
3497
3498
3499	/**
3500	* Raises the MSI interrupt for the IOMMU device.
3501	*
3502	* @param pDevIns The IOMMU device instance.
3503	*
3504	* @thread Any.
3505	*/
3506	static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
3507	{
3508	if (iommuAmdIsMsiEnabled(pDevIns))
3509	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
3510	}
3511
3512
3513	/**
3514	* Clears the MSI interrupt for the IOMMU device.
3515	*
3516	* @param pDevIns The IOMMU device instance.
3517	*
3518	* @thread Any.
3519	*/
3520	static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
3521	{
3522	if (iommuAmdIsMsiEnabled(pDevIns))
3523	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3524	}
3525
3526
3527	/**
3528	* Writes an entry to the event log in memory.
3529	*
3530	* @returns VBox status code.
3531	* @param pDevIns The IOMMU device instance.
3532	* @param pEvent The event to log.
3533	*
3534	* @thread Any.
3535	*/
3536	static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3537	{
3538	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3539
3540	IOMMU_ASSERT_LOCKED(pDevIns);
3541
3542	/* Check if event logging is active and the log has not overflowed. */
3543	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3544	if ( Status.n.u1EvtLogRunning
3545	&& !Status.n.u1EvtOverflow)
3546	{
3547	uint32_t const cbEvt = sizeof(*pEvent);
3548
3549	/* Get the offset we need to write the event to in memory (circular buffer offset). */
3550	uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3551	Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3552
3553	/* Ensure we have space in the event log. */
3554	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3555	uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3556	if (cEvts + 1 < cMaxEvts)
3557	{
3558	/* Write the event log entry to memory. */
3559	RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3560	RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3561	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3562	if (RT_FAILURE(rc))
3563	Log((IOMMU_LOG_PFX ": Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3564
3565	/* Increment the event log tail pointer. */
3566	uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3567	pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3568
3569	/* Indicate that an event log entry was written. */
3570	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3571
3572	/* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3573	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3574	if (Ctrl.n.u1EvtIntrEn)
3575	iommuAmdRaiseMsiInterrupt(pDevIns);
3576	}
3577	else
3578	{
3579	/* Indicate that the event log has overflowed. */
3580	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3581
3582	/* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3583	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3584	if (Ctrl.n.u1EvtIntrEn)
3585	iommuAmdRaiseMsiInterrupt(pDevIns);
3586	}
3587	}
3588	}
3589
3590
3591	/**
3592	* Sets an event in the hardware error registers.
3593	*
3594	* @param pDevIns The IOMMU device instance.
3595	* @param pEvent The event.
3596	*
3597	* @thread Any.
3598	*/
3599	static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3600	{
3601	IOMMU_ASSERT_LOCKED(pDevIns);
3602
3603	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3604	if (pThis->ExtFeat.n.u1HwErrorSup)
3605	{
3606	if (pThis->HwEvtStatus.n.u1Valid)
3607	pThis->HwEvtStatus.n.u1Overflow = 1;
3608	pThis->HwEvtStatus.n.u1Valid = 1;
3609	pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3610	pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3611	Assert(pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR);
3612	}
3613	}
3614
3615
3616	/**
3617	* Initializes a PAGE_TAB_HARDWARE_ERROR event.
3618	*
3619	* @param uDevId The device ID.
3620	* @param uDomainId The domain ID.
3621	* @param GCPhysPtEntity The system physical address of the page table
3622	* entity.
3623	* @param enmOp The IOMMU operation being performed.
3624	* @param pEvtPageTabHwErr Where to store the initialized event.
3625	*/
3626	static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3627	PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3628	{
3629	memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3630	pEvtPageTabHwErr->n.u16DevId = uDevId;
3631	pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
3632	pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3633	pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3634	pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3635	pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3636	pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3637	pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3638	pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3639	}
3640
3641
3642	/**
3643	* Raises a PAGE_TAB_HARDWARE_ERROR event.
3644	*
3645	* @param pDevIns The IOMMU device instance.
3646	* @param enmOp The IOMMU operation being performed.
3647	* @param pEvtPageTabHwErr The page table hardware error event.
3648	*
3649	* @thread Any.
3650	*/
3651	static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3652	{
3653	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3654	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3655
3656	IOMMU_LOCK_NORET(pDevIns);
3657
3658	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3659	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3660	if (enmOp != IOMMUOP_CMD)
3661	iommuAmdSetPciTargetAbort(pDevIns);
3662
3663	IOMMU_UNLOCK(pDevIns);
3664
3665	Log((IOMMU_LOG_PFX ": Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3666	pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3667	pEvtPageTabHwErr->n.u2Type));
3668	}
3669
3670
3671	/**
3672	* Initializes a COMMAND_HARDWARE_ERROR event.
3673	*
3674	* @param GCPhysAddr The system physical address the IOMMU attempted to access.
3675	* @param pEvtCmdHwErr Where to store the initialized event.
3676	*/
3677	static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3678	{
3679	memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3680	pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3681	pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3682	pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3683	}
3684
3685
3686	/**
3687	* Raises a COMMAND_HARDWARE_ERROR event.
3688	*
3689	* @param pDevIns The IOMMU device instance.
3690	* @param pEvtCmdHwErr The command hardware error event.
3691	*
3692	* @thread Any.
3693	*/
3694	static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3695	{
3696	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3697	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3698	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3699
3700	IOMMU_LOCK_NORET(pDevIns);
3701
3702	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3703	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3704	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3705
3706	IOMMU_UNLOCK(pDevIns);
3707
3708	Log((IOMMU_LOG_PFX ": Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr,
3709	pEvtCmdHwErr->n.u2Type));
3710	}
3711
3712
3713	/**
3714	* Initializes a DEV_TAB_HARDWARE_ERROR event.
3715	*
3716	* @param uDevId The device ID.
3717	* @param GCPhysDte The system physical address of the failed device table
3718	* access.
3719	* @param enmOp The IOMMU operation being performed.
3720	* @param pEvtDevTabHwErr Where to store the initialized event.
3721	*/
3722	static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3723	PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3724	{
3725	memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3726	pEvtDevTabHwErr->n.u16DevId = uDevId;
3727	pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3728	/** @todo IOMMU: Any other transaction type that can set read/write bit? */
3729	pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3730	pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3731	pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3732	pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3733	pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3734	}
3735
3736
3737	/**
3738	* Raises a DEV_TAB_HARDWARE_ERROR event.
3739	*
3740	* @param pDevIns The IOMMU device instance.
3741	* @param enmOp The IOMMU operation being performed.
3742	* @param pEvtDevTabHwErr The device table hardware error event.
3743	*
3744	* @thread Any.
3745	*/
3746	static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3747	{
3748	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3749	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3750
3751	IOMMU_LOCK_NORET(pDevIns);
3752
3753	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3754	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3755	if (enmOp != IOMMUOP_CMD)
3756	iommuAmdSetPciTargetAbort(pDevIns);
3757
3758	IOMMU_UNLOCK(pDevIns);
3759
3760	Log((IOMMU_LOG_PFX ": Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n",
3761	pEvtDevTabHwErr->n.u16DevId, pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3762	}
3763
3764
3765	/**
3766	* Initializes an ILLEGAL_COMMAND_ERROR event.
3767	*
3768	* @param GCPhysCmd The system physical address of the failed command
3769	* access.
3770	* @param pEvtIllegalCmd Where to store the initialized event.
3771	*/
3772	static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3773	{
3774	Assert(!(GCPhysCmd & UINT64_C(0xf)));
3775	memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3776	pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3777	pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3778	}
3779
3780
3781	/**
3782	* Raises an ILLEGAL_COMMAND_ERROR event.
3783	*
3784	* @param pDevIns The IOMMU device instance.
3785	* @param pEvtIllegalCmd The illegal command error event.
3786	* @param enmEvtType The illegal command error event type.
3787	*/
3788	static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd,
3789	EVT_ILLEGAL_CMD_ERR_TYPE_T enmEvtType)
3790	{
3791	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3792	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3793	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3794
3795	IOMMU_LOCK_NORET(pDevIns);
3796
3797	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3798	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3799
3800	IOMMU_UNLOCK(pDevIns);
3801
3802	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_COMMAND_ERROR. GCPhysCmd=%#RGp enmType=%u\n", pEvtIllegalCmd->n.u64Addr, enmEvtType));
3803	NOREF(enmEvtType);
3804	}
3805
3806
3807	/**
3808	* Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3809	*
3810	* @param uDevId The device ID.
3811	* @param uIova The I/O virtual address.
3812	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3813	* event was caused by an invalid level encoding in the
3814	* DTE.
3815	* @param enmOp The IOMMU operation being performed.
3816	* @param pEvtIllegalDte Where to store the initialized event.
3817	*/
3818	static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3819	PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3820	{
3821	memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3822	pEvtIllegalDte->n.u16DevId = uDevId;
3823	pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3824	pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3825	pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3826	pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3827	pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3828	pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3829	/** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3830	* IOMMU spec here but not for this field for I/O page fault event. */
3831	Assert(!(uIova & UINT64_C(0x3)));
3832	}
3833
3834
3835	/**
3836	* Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3837	*
3838	* @param pDevIns The IOMMU instance data.
3839	* @param enmOp The IOMMU operation being performed.
3840	* @param pEvtIllegalDte The illegal device table entry event.
3841	* @param enmEvtType The illegal device table entry event type.
3842	*
3843	* @thread Any.
3844	*/
3845	static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3846	EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3847	{
3848	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3849	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3850
3851	IOMMU_LOCK_NORET(pDevIns);
3852
3853	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3854	if (enmOp != IOMMUOP_CMD)
3855	iommuAmdSetPciTargetAbort(pDevIns);
3856
3857	IOMMU_UNLOCK(pDevIns);
3858
3859	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3860	pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3861	NOREF(enmEvtType);
3862	}
3863
3864
3865	/**
3866	* Initializes an IO_PAGE_FAULT event.
3867	*
3868	* @param uDevId The device ID.
3869	* @param uDomainId The domain ID.
3870	* @param uIova The I/O virtual address being accessed.
3871	* @param fPresent Transaction to a page marked as present (including
3872	* DTE.V=1) or interrupt marked as remapped
3873	* (IRTE.RemapEn=1).
3874	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3875	* the I/O page fault was caused by invalid level
3876	* encoding.
3877	* @param fPermDenied Permission denied for the address being accessed.
3878	* @param enmOp The IOMMU operation being performed.
3879	* @param pEvtIoPageFault Where to store the initialized event.
3880	*/
3881	static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3882	bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3883	{
3884	Assert(!fPermDenied \|\| fPresent);
3885	memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3886	pEvtIoPageFault->n.u16DevId = uDevId;
3887	//pEvtIoPageFault->n.u4PasidHi = 0;
3888	pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
3889	//pEvtIoPageFault->n.u1GuestOrNested = 0;
3890	//pEvtIoPageFault->n.u1NoExecute = 0;
3891	//pEvtIoPageFault->n.u1User = 0;
3892	pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3893	pEvtIoPageFault->n.u1Present = fPresent;
3894	pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3895	pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3896	pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3897	pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3898	pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3899	pEvtIoPageFault->n.u64Addr = uIova;
3900	}
3901
3902
3903	/**
3904	* Raises an IO_PAGE_FAULT event.
3905	*
3906	* @param pDevIns The IOMMU instance data.
3907	* @param pDte The device table entry. Optional, can be NULL
3908	* depending on @a enmOp.
3909	* @param pIrte The interrupt remapping table entry. Optional, can
3910	* be NULL depending on @a enmOp.
3911	* @param enmOp The IOMMU operation being performed.
3912	* @param pEvtIoPageFault The I/O page fault event.
3913	* @param enmEvtType The I/O page fault event type.
3914	*
3915	* @thread Any.
3916	*/
3917	static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3918	PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3919	{
3920	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3921	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3922
3923	IOMMU_LOCK_NORET(pDevIns);
3924
3925	bool fSuppressEvtLogging = false;
3926	if ( enmOp == IOMMUOP_MEM_READ
3927	\|\| enmOp == IOMMUOP_MEM_WRITE)
3928	{
3929	if ( pDte
3930	&& pDte->n.u1Valid)
3931	{
3932	fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
3933	/** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
3934	* suppression. Perhaps will be possible when we complete IOTLB/cache
3935	* handling. */
3936	}
3937	}
3938	else if (enmOp == IOMMUOP_INTR_REQ)
3939	{
3940	if ( pDte
3941	&& pDte->n.u1IntrMapValid)
3942	fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
3943
3944	if ( !fSuppressEvtLogging
3945	&& pIrte)
3946	fSuppressEvtLogging = pIrte->n.u1SuppressPf;
3947	}
3948	/* else: Events are never suppressed for commands. */
3949
3950	switch (enmEvtType)
3951	{
3952	case kIoPageFaultType_PermDenied:
3953	{
3954	/* Cannot be triggered by a command. */
3955	Assert(enmOp != IOMMUOP_CMD);
3956	RT_FALL_THRU();
3957	}
3958	case kIoPageFaultType_DteRsvdPagingMode:
3959	case kIoPageFaultType_PteInvalidPageSize:
3960	case kIoPageFaultType_PteInvalidLvlEncoding:
3961	case kIoPageFaultType_SkippedLevelIovaNotZero:
3962	case kIoPageFaultType_PteRsvdNotZero:
3963	case kIoPageFaultType_PteValidNotSet:
3964	case kIoPageFaultType_DteTranslationDisabled:
3965	case kIoPageFaultType_PasidInvalidRange:
3966	{
3967	/*
3968	* For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3969	* create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
3970	*/
3971	if (enmOp != IOMMUOP_TRANSLATE_REQ)
3972	{
3973	if (!fSuppressEvtLogging)
3974	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3975	if (enmOp != IOMMUOP_CMD)
3976	iommuAmdSetPciTargetAbort(pDevIns);
3977	}
3978	break;
3979	}
3980
3981	case kIoPageFaultType_UserSupervisor:
3982	{
3983	/* Access is blocked and only creates an event log entry. */
3984	if (!fSuppressEvtLogging)
3985	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3986	break;
3987	}
3988
3989	case kIoPageFaultType_IrteAddrInvalid:
3990	case kIoPageFaultType_IrteRsvdNotZero:
3991	case kIoPageFaultType_IrteRemapEn:
3992	case kIoPageFaultType_IrteRsvdIntType:
3993	case kIoPageFaultType_IntrReqAborted:
3994	case kIoPageFaultType_IntrWithPasid:
3995	{
3996	/* Only trigerred by interrupt requests. */
3997	Assert(enmOp == IOMMUOP_INTR_REQ);
3998	if (!fSuppressEvtLogging)
3999	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4000	iommuAmdSetPciTargetAbort(pDevIns);
4001	break;
4002	}
4003
4004	case kIoPageFaultType_SmiFilterMismatch:
4005	{
4006	/* Not supported and probably will never be, assert. */
4007	AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
4008	break;
4009	}
4010
4011	case kIoPageFaultType_DevId_Invalid:
4012	{
4013	/* Cannot be triggered by a command. */
4014	Assert(enmOp != IOMMUOP_CMD);
4015	Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
4016	if (!fSuppressEvtLogging)
4017	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4018	if ( enmOp == IOMMUOP_MEM_READ
4019	\|\| enmOp == IOMMUOP_MEM_WRITE)
4020	iommuAmdSetPciTargetAbort(pDevIns);
4021	break;
4022	}
4023	}
4024
4025	IOMMU_UNLOCK(pDevIns);
4026	}
4027
4028
4029	/**
4030	* Initializes an IOTLB entry.
4031	*
4032	* @param GCPhysSpa The translated system physical address.
4033	* @param cShift The number of offset bits in the system physical address.
4034	* @param fIoPerm The I/O access permissions (IOMMU_IO_PERM_XXX).
4035	* @param pIotlbe Where to store the initialized IOTLB entry.
4036	*/
4037	static void iommuAmdInitIotlbe(RTGCPHYS GCPhysSpa, uint8_t cShift, uint8_t fIoPerm, PIOTLBE_T pIotlbe)
4038	{
4039	pIotlbe->uMagic = IOMMU_IOTLBE_MAGIC;
4040	pIotlbe->uRsvd0 = 0;
4041	pIotlbe->fIoPerm = fIoPerm;
4042	pIotlbe->cShift = cShift;
4043	pIotlbe->GCPhysSpa = GCPhysSpa;
4044	}
4045
4046
4047	/**
4048	* Updates an IOTLB entry.
4049	*
4050	* @param GCPhysSpa The translated system physical address.
4051	* @param cShift The number of offset bits in the system physical address.
4052	* @param fIoPerm The I/O access permissions (IOMMU_IO_PERM_XXX).
4053	* @param pIotlbe The IOTLB entry to update.
4054	*/
4055	static void iommuAmdUpdateIotlbe(RTGCPHYS GCPhysSpa, uint8_t cShift, uint8_t fIoPerm, PIOTLBE_T pIotlbe)
4056	{
4057	Assert(pIotlbe->uMagic == IOMMU_IOTLBE_MAGIC);
4058	pIotlbe->fIoPerm = fIoPerm;
4059	pIotlbe->cShift = cShift;
4060	pIotlbe->GCPhysSpa = GCPhysSpa;
4061	}
4062
4063
4064	/**
4065	* Returns whether the I/O virtual address is to be excluded from translation and
4066	* permission checks.
4067	*
4068	* @returns @c true if the DVA is excluded, @c false otherwise.
4069	* @param pThis The IOMMU device state.
4070	* @param pDte The device table entry.
4071	* @param uIova The I/O virtual address.
4072	*
4073	* @remarks Ensure the exclusion range is enabled prior to calling this function.
4074	*
4075	* @thread Any.
4076	*/
4077	static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
4078	{
4079	/* Ensure the exclusion range is enabled. */
4080	Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
4081
4082	/* Check if the IOVA falls within the exclusion range. */
4083	uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
4084	uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
4085	if (uIovaExclLast - uIova >= uIovaExclFirst)
4086	{
4087	/* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
4088	if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
4089	\|\| pDte->n.u1AllowExclusion)
4090	return true;
4091	}
4092	return false;
4093	}
4094
4095
4096	/**
4097	* Reads a device table entry from guest memory given the device ID.
4098	*
4099	* @returns VBox status code.
4100	* @param pDevIns The IOMMU device instance.
4101	* @param uDevId The device ID.
4102	* @param enmOp The IOMMU operation being performed.
4103	* @param pDte Where to store the device table entry.
4104	*
4105	* @thread Any.
4106	*/
4107	static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
4108	{
4109	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4110	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4111
4112	uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
4113	Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
4114
4115	uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
4116	Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
4117
4118	RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
4119	uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
4120	RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
4121
4122	Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
4123	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
4124	if (RT_FAILURE(rc))
4125	{
4126	Log((IOMMU_LOG_PFX ": Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
4127
4128	EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
4129	iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
4130	iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
4131	return VERR_IOMMU_IPE_1;
4132	}
4133
4134	return rc;
4135	}
4136
4137
4138	/**
4139	* Walks the I/O page table to translate the I/O virtual address to a system
4140	* physical address.
4141	*
4142	* @returns VBox status code.
4143	* @param pDevIns The IOMMU device instance.
4144	* @param uIova The I/O virtual address to translate. Must be 4K aligned.
4145	* @param uDevId The device ID.
4146	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4147	* permissions for the access being made.
4148	* @param pDte The device table entry.
4149	* @param enmOp The IOMMU operation being performed.
4150	* @param pWalkResult Where to store the results of the I/O page walk. This is
4151	* only updated when VINF_SUCCESS is returned.
4152	*
4153	* @thread Any.
4154	*/
4155	static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
4156	IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
4157	{
4158	Assert(pDte->n.u1Valid);
4159	Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
4160
4161	/* If the translation is not valid, raise an I/O page fault. */
4162	if (pDte->n.u1TranslationValid)
4163	{ /* likely */ }
4164	else
4165	{
4166	/** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
4167	* doesn't explicitly say whether an I/O page fault is raised. From other
4168	* places in the spec. it seems early page walk terminations (starting with
4169	* the DTE) return the state computed so far and raises an I/O page fault. So
4170	* returning an invalid translation rather than skipping translation. */
4171	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4172	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4173	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4174	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4175	kIoPageFaultType_DteTranslationDisabled);
4176	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4177	}
4178
4179	/* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
4180	uint8_t const uMaxLevel = pDte->n.u3Mode;
4181	if (uMaxLevel != 0)
4182	{ /* likely */ }
4183	else
4184	{
4185	uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4186	if ((fAccess & fDtePerm) != fAccess)
4187	{
4188	Log((IOMMU_LOG_PFX ": Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
4189	return VERR_IOMMU_ADDR_ACCESS_DENIED;
4190	}
4191	pWalkResult->GCPhysSpa = uIova;
4192	pWalkResult->cShift = 0;
4193	pWalkResult->fIoPerm = fDtePerm;
4194	return VINF_SUCCESS;
4195	}
4196
4197	/* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
4198	if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4199	{ /* likely */ }
4200	else
4201	{
4202	/** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
4203	* raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
4204	* I'm just going with I/O page fault. */
4205	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4206	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4207	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4208	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4209	kIoPageFaultType_PteInvalidLvlEncoding);
4210	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4211	}
4212
4213	/* Check permissions bits of the root page table. */
4214	uint8_t const fPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4215	if ((fAccess & fPtePerm) == fAccess)
4216	{ /* likely */ }
4217	else
4218	{
4219	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4220	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4221	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4222	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4223	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4224	}
4225
4226	/** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
4227	* function called iommuAmdWalkIoPageDirectory() and call it for multi-page
4228	* accesses from the 2nd page. We can avoid re-checking the DTE root-page
4229	* table entry every time. Not sure if it's worth optimizing that case now
4230	* or if at all. */
4231
4232	/* The virtual address bits indexing table. */
4233	static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
4234	static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
4235	UINT64_C(0x00000000001ff000),
4236	UINT64_C(0x000000003fe00000),
4237	UINT64_C(0x0000007fc0000000),
4238	UINT64_C(0x0000ff8000000000),
4239	UINT64_C(0x01ff000000000000),
4240	UINT64_C(0xfe00000000000000),
4241	UINT64_C(0x0000000000000000) };
4242	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
4243	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
4244
4245	/* Traverse the I/O page table starting with the page directory in the DTE. */
4246	IOPTENTITY_T PtEntity;
4247	PtEntity.u64 = pDte->au64[0];
4248	for (;;)
4249	{
4250	/* Figure out the system physical address of the page table at the current level. */
4251	uint8_t const uLevel = PtEntity.n.u3NextLevel;
4252
4253	/* Read the page table entity at the current level. */
4254	{
4255	Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
4256	Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4257	uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
4258	uint64_t const offPte = idxPte << 3;
4259	RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
4260	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
4261	if (RT_FAILURE(rc))
4262	{
4263	Log((IOMMU_LOG_PFX ": Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
4264	EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
4265	iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
4266	iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
4267	return VERR_IOMMU_IPE_2;
4268	}
4269	}
4270
4271	/* Check present bit. */
4272	if (PtEntity.n.u1Present)
4273	{ /* likely */ }
4274	else
4275	{
4276	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4277	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4278	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4279	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4280	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4281	}
4282
4283	/* Check permission bits. */
4284	uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4285	if ((fAccess & fPtePerm) == fAccess)
4286	{ /* likely */ }
4287	else
4288	{
4289	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4290	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4291	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4292	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4293	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4294	}
4295
4296	/* If this is a PTE, we're at the final level and we're done. */
4297	uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
4298	if (uNextLevel == 0)
4299	{
4300	/* The page size of the translation is the default (4K). */
4301	pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4302	pWalkResult->cShift = X86_PAGE_4K_SHIFT;
4303	pWalkResult->fIoPerm = fPtePerm;
4304	return VINF_SUCCESS;
4305	}
4306	if (uNextLevel == 7)
4307	{
4308	/* The default page size of the translation is overriden. */
4309	RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4310	uint8_t cShift = X86_PAGE_4K_SHIFT;
4311	while (GCPhysPte & RT_BIT_64(cShift++))
4312	;
4313
4314	/* The page size must be larger than the default size and lower than the default size of the higher level. */
4315	Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
4316	if ( cShift > s_acIovaLevelShifts[uLevel]
4317	&& cShift < s_acIovaLevelShifts[uLevel + 1])
4318	{
4319	pWalkResult->GCPhysSpa = GCPhysPte;
4320	pWalkResult->cShift = cShift;
4321	pWalkResult->fIoPerm = fPtePerm;
4322	return VINF_SUCCESS;
4323	}
4324
4325	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4326	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4327	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4328	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4329	kIoPageFaultType_PteInvalidPageSize);
4330	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4331	}
4332
4333	/* Validate the next level encoding of the PDE. */
4334	#if IOMMU_MAX_HOST_PT_LEVEL < 6
4335	if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4336	{ /* likely */ }
4337	else
4338	{
4339	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4340	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4341	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4342	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4343	kIoPageFaultType_PteInvalidLvlEncoding);
4344	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4345	}
4346	#else
4347	Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4348	#endif
4349
4350	/* Validate level transition. */
4351	if (uNextLevel < uLevel)
4352	{ /* likely */ }
4353	else
4354	{
4355	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4356	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4357	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4358	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4359	kIoPageFaultType_PteInvalidLvlEncoding);
4360	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4361	}
4362
4363	/* Ensure IOVA bits of skipped levels are zero. */
4364	Assert(uLevel > 0);
4365	uint64_t uIovaSkipMask = 0;
4366	for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
4367	uIovaSkipMask \|= s_auIovaLevelMasks[idxLevel];
4368	if (!(uIova & uIovaSkipMask))
4369	{ /* likely */ }
4370	else
4371	{
4372	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4373	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4374	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4375	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4376	kIoPageFaultType_SkippedLevelIovaNotZero);
4377	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4378	}
4379
4380	/* Continue with traversing the page directory at this level. */
4381	}
4382
4383	/* Shouldn't really get here. */
4384	return VERR_IOMMU_IPE_3;
4385	}
4386
4387
4388	/**
4389	* Looks up an I/O virtual address from the device table.
4390	*
4391	* @returns VBox status code.
4392	* @param pDevIns The IOMMU instance data.
4393	* @param uDevId The device ID.
4394	* @param uIova The I/O virtual address to lookup.
4395	* @param cbAccess The size of the access.
4396	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4397	* permissions for the access being made.
4398	* @param enmOp The IOMMU operation being performed.
4399	* @param pGCPhysSpa Where to store the translated system physical address. Only
4400	* valid when translation succeeds and VINF_SUCCESS is
4401	* returned!
4402	*
4403	* @thread Any.
4404	*/
4405	static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
4406	IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
4407	{
4408	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4409
4410	/* Read the device table entry from memory. */
4411	DTE_T Dte;
4412	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4413	if (RT_SUCCESS(rc))
4414	{
4415	/* If the DTE is not valid, addresses are forwarded without translation */
4416	if (Dte.n.u1Valid)
4417	{ /* likely */ }
4418	else
4419	{
4420	/** @todo IOMMU: Add to IOLTB cache. */
4421	*pGCPhysSpa = uIova;
4422	return VINF_SUCCESS;
4423	}
4424
4425	/* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4426	uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4427	uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4428	if (RT_LIKELY( !fRsvd0
4429	&& !fRsvd1))
4430	{ /* likely */ }
4431	else
4432	{
4433	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4434	EVT_ILLEGAL_DTE_T Event;
4435	iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4436	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4437	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4438	}
4439
4440	/* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
4441	if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
4442	\|\| !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
4443	{ /* likely */ }
4444	else
4445	{
4446	/** @todo IOMMU: Add to IOLTB cache. */
4447	*pGCPhysSpa = uIova;
4448	return VINF_SUCCESS;
4449	}
4450
4451	/** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
4452	* below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
4453
4454	uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
4455	uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
4456	uint64_t cbRemaining = cbAccess;
4457	for (;;)
4458	{
4459	/* Walk the I/O page tables to translate the IOVA and check permission for the access. */
4460	IOWALKRESULT WalkResult;
4461	rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
4462	if (RT_SUCCESS(rc))
4463	{
4464	/** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
4465
4466	/* Store the translated base address before continuing to check permissions for any more pages. */
4467	if (cbRemaining == cbAccess)
4468	{
4469	RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
4470	*pGCPhysSpa = WalkResult.GCPhysSpa \| offSpa;
4471	}
4472
4473	uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
4474	if (cbRemaining > cbPhysPage - offIova)
4475	{
4476	cbRemaining -= (cbPhysPage - offIova);
4477	uBaseIova += cbPhysPage;
4478	offIova = 0;
4479	}
4480	else
4481	break;
4482	}
4483	else
4484	{
4485	Log((IOMMU_LOG_PFX ": I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
4486	uBaseIova, fAccess, rc));
4487	*pGCPhysSpa = NIL_RTGCPHYS;
4488	return rc;
4489	}
4490	}
4491
4492	return rc;
4493	}
4494
4495	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4496	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4497	}
4498
4499
4500	/**
4501	* Memory read request from a device.
4502	*
4503	* @returns VBox status code.
4504	* @param pDevIns The IOMMU device instance.
4505	* @param uDevId The device ID (bus, device, function).
4506	* @param uIova The I/O virtual address being read.
4507	* @param cbRead The number of bytes being read.
4508	* @param pGCPhysSpa Where to store the translated system physical address.
4509	*
4510	* @thread Any.
4511	*/
4512	static int iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, PRTGCPHYS pGCPhysSpa)
4513	{
4514	Assert(pDevIns);
4515	Assert(pGCPhysSpa);
4516	Assert(cbRead > 0);
4517
4518	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4519
4520	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4521	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4522	if (Ctrl.n.u1IommuEn)
4523	{
4524	/** @todo IOMMU: IOTLB cache lookup. */
4525
4526	/* Lookup the IOVA from the device table. */
4527	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
4528	}
4529
4530	*pGCPhysSpa = uIova;
4531	return VINF_SUCCESS;
4532	}
4533
4534
4535	/**
4536	* Memory write request from a device.
4537	*
4538	* @returns VBox status code.
4539	* @param pDevIns The IOMMU device instance.
4540	* @param uDevId The device ID (bus, device, function).
4541	* @param uIova The I/O virtual address being written.
4542	* @param cbWrite The number of bytes being written.
4543	* @param pGCPhysSpa Where to store the translated physical address.
4544	*
4545	* @thread Any.
4546	*/
4547	static int iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite, PRTGCPHYS pGCPhysSpa)
4548	{
4549	Assert(pDevIns);
4550	Assert(pGCPhysSpa);
4551	Assert(cbWrite > 0);
4552
4553	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4554
4555	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4556	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4557	if (Ctrl.n.u1IommuEn)
4558	{
4559	/** @todo IOMMU: IOTLB cache lookup. */
4560
4561	/* Lookup the IOVA from the device table. */
4562	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
4563	}
4564
4565	*pGCPhysSpa = uIova;
4566	return VINF_SUCCESS;
4567	}
4568
4569
4570	/**
4571	* @callback_method_impl{FNIOMMMIONEWWRITE}
4572	*/
4573	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
4574	{
4575	NOREF(pvUser);
4576	Assert(cb == 4 \|\| cb == 8);
4577	Assert(!(off & (cb - 1)));
4578
4579	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
4580	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
4581	}
4582
4583
4584	/**
4585	* @callback_method_impl{FNIOMMMIONEWREAD}
4586	*/
4587	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
4588	{
4589	NOREF(pvUser);
4590	Assert(cb == 4 \|\| cb == 8);
4591	Assert(!(off & (cb - 1)));
4592
4593	uint64_t uResult;
4594	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
4595	if (cb == 8)
4596	(uint64_t )pv = uResult;
4597	else
4598	(uint32_t )pv = (uint32_t)uResult;
4599
4600	return rcStrict;
4601	}
4602
4603
4604	# ifdef IN_RING3
4605
4606	/**
4607	* Processes an IOMMU command.
4608	*
4609	* @returns VBox status code.
4610	* @param pDevIns The IOMMU device instance.
4611	* @param GCPhysCmd The system physical address of the command.
4612	* @param pCmd The command to process.
4613	*
4614	* @thread Command thread.
4615	*/
4616	static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCmd, PCCMD_GENERIC_T pCmd)
4617	{
4618	IOMMU_ASSERT_NOT_LOCKED(pDevIns);
4619
4620	EVT_ILLEGAL_CMD_ERR_T EvtIllegalCmdErr;
4621
4622	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4623	uint8_t const bCmd = pCmd->n.u4Opcode;
4624	switch (bCmd)
4625	{
4626	case IOMMU_CMD_COMPLETION_WAIT:
4627	{
4628	PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4629	AssertCompile(sizeof(pCmdComWait) == sizeof(pCmd));
4630
4631	/* Validate reserved bits in the command. */
4632	if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4633	{
4634	/* If Completion Store is requested, write the Store Data to the specified Store Address.*/
4635	if (pCmdComWait->n.u1Store)
4636	{
4637	RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4638	uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4639
4640	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4641	if (RT_FAILURE(rc))
4642	{
4643	EVT_CMD_HW_ERR_T EvtCmdHwErr;
4644	iommuAmdInitCmdHwErrorEvent(GCPhysStore, &EvtCmdHwErr);
4645	iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
4646	Log((IOMMU_LOG_PFX ": Failed to write StoreData (%#RX64) to %#RGp. rc=%Rrc\n", u64Data, GCPhysStore, rc));
4647	return rc;
4648	}
4649	}
4650
4651	/* If command completion interrupt is requested, honor it. */
4652	if (pCmdComWait->n.u1Interrupt)
4653	{
4654	IOMMU_LOCK(pDevIns);
4655	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4656	if (Ctrl.n.u1CompWaitIntrEn)
4657	{
4658	/* Indicate that this command completed. */
4659	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4660
4661	/* Check and signal an interrupt if software wants to receive one when this command completes. */
4662	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4663	if (Ctrl.n.u1CompWaitIntrEn)
4664	iommuAmdRaiseMsiInterrupt(pDevIns);
4665	}
4666	IOMMU_UNLOCK(pDevIns);
4667	}
4668	return VINF_SUCCESS;
4669	}
4670
4671	iommuAmdInitIllegalCmdEvent(GCPhysCmd, &EvtIllegalCmdErr);
4672	iommuAmdRaiseIllegalCmdEvent(pDevIns, &EvtIllegalCmdErr, kIllegalCmdErrType_RsvdNotZero);
4673	return VERR_INVALID_FUNCTION;
4674	}
4675
4676	case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4677	case IOMMU_CMD_INV_IOMMU_PAGES:
4678	case IOMMU_CMD_INV_IOTLB_PAGES:
4679	case IOMMU_CMD_INV_INTR_TABLE:
4680	{
4681	return VERR_NOT_IMPLEMENTED;
4682	}
4683
4684	case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
4685	{
4686	if (pThis->ExtFeat.n.u1PrefetchSup)
4687	{
4688	/** @todo IOMMU: Implement prefetch. */
4689	return VINF_SUCCESS;
4690	}
4691	iommuAmdInitIllegalCmdEvent(GCPhysCmd, &EvtIllegalCmdErr);
4692	iommuAmdRaiseIllegalCmdEvent(pDevIns, &EvtIllegalCmdErr, kIllegalCmdErrType_CmdNotSupported);
4693	return VERR_INVALID_FUNCTION;
4694	}
4695
4696	case IOMMU_CMD_COMPLETE_PPR_REQ:
4697	case IOMMU_CMD_INV_IOMMU_ALL:
4698	{
4699	NOREF(pThis);
4700	return VERR_NOT_IMPLEMENTED;
4701	}
4702
4703	default:
4704	break;
4705	}
4706
4707	Log((IOMMU_LOG_PFX ": Unrecognized or unsupported command opcode %u (%#x)\n", bCmd, bCmd));
4708	return VERR_NOT_SUPPORTED;
4709	}
4710
4711
4712	/**
4713	* The IOMMU command thread.
4714	*
4715	* @returns VBox status code.
4716	* @param pDevIns The IOMMU device instance.
4717	* @param pThread The command thread.
4718	*/
4719	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4720	{
4721	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4722
4723	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4724	return VINF_SUCCESS;
4725
4726	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4727	{
4728	/*
4729	* Sleep perpetually until we are woken up to process commands.
4730	*/
4731	{
4732	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
4733	bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
4734	if (!fSignaled)
4735	{
4736	Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
4737	int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
4738	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4739	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4740	break;
4741	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
4742	ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
4743	}
4744	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
4745	}
4746
4747	/*
4748	* Fetch and process IOMMU commands.
4749	*/
4750	/** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
4751	* at a time) and is expensive due to calls to PGM for fetching guest memory.
4752	* We could optimize by fetching a bunch of commands at a time reducing
4753	* number of calls to PGM. In the longer run we could lock the memory and
4754	* mappings and accessing them directly. */
4755	IOMMU_LOCK(pDevIns);
4756
4757	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
4758	if (Status.n.u1CmdBufRunning)
4759	{
4760	/* Get the offset we need to read the command from memory (circular buffer offset). */
4761	uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
4762	uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
4763	Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
4764	Assert(offHead < cbCmdBuf);
4765	while (offHead != pThis->CmdBufTailPtr.n.off)
4766	{
4767	/* Read the command from memory. */
4768	CMD_GENERIC_T Cmd;
4769	RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
4770	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
4771	if (RT_SUCCESS(rc))
4772	{
4773	/* Increment the command buffer head pointer. */
4774	offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
4775	pThis->CmdBufHeadPtr.n.off = offHead;
4776
4777	/* Process the fetched command. */
4778	IOMMU_UNLOCK(pDevIns);
4779	rc = iommuAmdR3ProcessCmd(pDevIns, GCPhysCmd, &Cmd);
4780	IOMMU_LOCK(pDevIns);
4781	if (RT_FAILURE(rc))
4782	break;
4783	}
4784	else
4785	{
4786	EVT_CMD_HW_ERR_T EvtCmdHwErr;
4787	iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
4788	iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
4789	break;
4790	}
4791	}
4792	}
4793
4794	IOMMU_UNLOCK(pDevIns);
4795	}
4796
4797	LogFlow((IOMMU_LOG_PFX ": Command thread terminating\n"));
4798	return VINF_SUCCESS;
4799	}
4800
4801
4802	/**
4803	* Wakes up the command thread so it can respond to a state change.
4804	*
4805	* @returns VBox status code.
4806	* @param pDevIns The IOMMU device instance.
4807	* @param pThread The command thread.
4808	*/
4809	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4810	{
4811	RT_NOREF(pThread);
4812
4813	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4814	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
4815	}
4816
4817
4818	/**
4819	* @callback_method_impl{FNPCICONFIGREAD}
4820	*/
4821	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4822	unsigned cb, uint32_t *pu32Value)
4823	{
4824	/** @todo IOMMU: PCI config read stat counter. */
4825	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4826	Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
4827	VBOXSTRICTRC_VAL(rcStrict)));
4828	return rcStrict;
4829	}
4830
4831
4832	/**
4833	* @callback_method_impl{FNPCICONFIGWRITE}
4834	*/
4835	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4836	unsigned cb, uint32_t u32Value)
4837	{
4838	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4839
4840	/*
4841	* Discard writes to read-only registers that are specific to the IOMMU.
4842	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
4843	* See PCI spec. 6.1. "Configuration Space Organization".
4844	*/
4845	switch (uAddress)
4846	{
4847	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
4848	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
4849	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
4850	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
4851	{
4852	Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
4853	return VINF_SUCCESS;
4854	}
4855	}
4856
4857	IOMMU_LOCK(pDevIns);
4858
4859	VBOXSTRICTRC rcStrict;
4860	switch (uAddress)
4861	{
4862	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
4863	{
4864	if (pThis->IommuBar.n.u1Enable)
4865	{
4866	rcStrict = VINF_SUCCESS;
4867	Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
4868	break;
4869	}
4870
4871	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
4872	if (pThis->IommuBar.n.u1Enable)
4873	{
4874	Assert(pThis->hMmio == NIL_IOMMMIOHANDLE);
4875	Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
4876	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
4877	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
4878	if (RT_FAILURE(rcStrict))
4879	Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
4880	}
4881	break;
4882	}
4883
4884	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
4885	{
4886	if (!pThis->IommuBar.n.u1Enable)
4887	pThis->IommuBar.au32[1] = u32Value;
4888	else
4889	{
4890	rcStrict = VINF_SUCCESS;
4891	Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
4892	}
4893	break;
4894	}
4895
4896	case IOMMU_PCI_OFF_MSI_CAP_HDR:
4897	{
4898	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
4899	RT_FALL_THRU();
4900	}
4901	default:
4902	{
4903	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4904	break;
4905	}
4906	}
4907
4908	IOMMU_UNLOCK(pDevIns);
4909
4910	Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
4911	return rcStrict;
4912	}
4913
4914
4915	/**
4916	* @callback_method_impl{FNDBGFHANDLERDEV}
4917	*/
4918	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4919	{
4920	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4921	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4922	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4923
4924	LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
4925	bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
4926
4927	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
4928	/* Device Table Base Addresses (all segments). */
4929	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4930	{
4931	DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
4932	pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
4933	if (fVerbose)
4934	{
4935	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
4936	IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
4937	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
4938	}
4939	}
4940	/* Command Buffer Base Address Register. */
4941	{
4942	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
4943	uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
4944	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4945	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4946	pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
4947	if (fVerbose)
4948	{
4949	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
4950	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4951	cEntries, cbBuffer);
4952	}
4953	}
4954	/* Event Log Base Address Register. */
4955	{
4956	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
4957	uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
4958	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4959	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4960	pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
4961	if (fVerbose)
4962	{
4963	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4964	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4965	cEntries, cbBuffer);
4966	}
4967	}
4968	/* IOMMU Control Register. */
4969	{
4970	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
4971	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
4972	if (fVerbose)
4973	{
4974	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
4975	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
4976	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
4977	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4978	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4979	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
4980	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
4981	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
4982	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
4983	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
4984	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
4985	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
4986	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
4987	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
4988	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
4989	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
4990	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
4991	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
4992	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
4993	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
4994	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
4995	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
4996	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
4997	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
4998	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
4999	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5000	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5001	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5002	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5003	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5004	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5005	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5006	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5007	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5008	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5009	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5010	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5011	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5012	}
5013	}
5014	/* Exclusion Base Address Register. */
5015	{
5016	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5017	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5018	if (fVerbose)
5019	{
5020	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5021	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5022	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5023	ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5024	}
5025	}
5026	/* Exclusion Range Limit Register. */
5027	{
5028	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5029	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5030	if (fVerbose)
5031	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
5032	}
5033	/* Extended Feature Register. */
5034	{
5035	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5036	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5037	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5038	if (fVerbose)
5039	{
5040	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5041	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5042	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5043	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5044	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5045	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5046	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5047	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5048	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5049	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5050	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5051	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5052	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5053	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5054	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5055	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5056	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5057	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5058	pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5059	g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5060	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5061	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5062	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5063	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5064	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5065	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5066	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5067	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5068	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5069	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5070	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5071	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5072	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5073	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5074	}
5075	}
5076	/* PPR Log Base Address Register. */
5077	{
5078	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5079	uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5080	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5081	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5082	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5083	if (fVerbose)
5084	{
5085	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5086	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5087	cEntries, cbBuffer);
5088	}
5089	}
5090	/* Hardware Event (Hi) Register. */
5091	{
5092	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5093	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5094	if (fVerbose)
5095	{
5096	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5097	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5098	}
5099	}
5100	/* Hardware Event (Lo) Register. */
5101	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5102	/* Hardware Event Status. */
5103	{
5104	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5105	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5106	if (fVerbose)
5107	{
5108	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5109	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5110	}
5111	}
5112	/* Guest Virtual-APIC Log Base Address Register. */
5113	{
5114	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5115	uint8_t const uEncodedLen = GALogBar.n.u4Len;
5116	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5117	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5118	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5119	if (fVerbose)
5120	{
5121	pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5122	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5123	cEntries, cbBuffer);
5124	}
5125	}
5126	/* Guest Virtual-APIC Log Tail Address Register. */
5127	{
5128	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5129	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5130	if (fVerbose)
5131	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5132	}
5133	/* PPR Log B Base Address Register. */
5134	{
5135	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5136	uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5137	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5138	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5139	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5140	if (fVerbose)
5141	{
5142	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5143	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5144	cEntries, cbBuffer);
5145	}
5146	}
5147	/* Event Log B Base Address Register. */
5148	{
5149	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5150	uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5151	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5152	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5153	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5154	if (fVerbose)
5155	{
5156	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5157	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5158	cEntries, cbBuffer);
5159	}
5160	}
5161	/* Device-Specific Feature Extension Register. */
5162	{
5163	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5164	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5165	if (fVerbose)
5166	{
5167	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5168	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5169	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5170	}
5171	}
5172	/* Device-Specific Control Extension Register. */
5173	{
5174	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5175	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5176	if (fVerbose)
5177	{
5178	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5179	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5180	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5181	}
5182	}
5183	/* Device-Specific Status Extension Register. */
5184	{
5185	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5186	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
5187	if (fVerbose)
5188	{
5189	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5190	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5191	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5192	}
5193	}
5194	/* MSI Miscellaneous Information Register (Lo and Hi). */
5195	{
5196	MSI_MISC_INFO_T const MsiMiscInfo = pThis->MsiMiscInfo;
5197	pHlp->pfnPrintf(pHlp, " MSI Misc. Info. Register = %#RX64\n", MsiMiscInfo.u64);
5198	if (fVerbose)
5199	{
5200	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumEvtLog);
5201	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MsiMiscInfo.n.u3GstVirtAddrSize);
5202	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MsiMiscInfo.n.u7PhysAddrSize);
5203	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MsiMiscInfo.n.u7VirtAddrSize);
5204	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MsiMiscInfo.n.u1HtAtsResv);
5205	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumPpr);
5206	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumGa);
5207	}
5208	}
5209	/* MSI Capability Header. */
5210	{
5211	MSI_CAP_HDR_T MsiCapHdr;
5212	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5213	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5214	if (fVerbose)
5215	{
5216	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5217	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5218	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5219	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5220	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5221	}
5222	}
5223	/* MSI Address Register (Lo and Hi). */
5224	{
5225	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5226	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5227	MSI_ADDR_T MsiAddr;
5228	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5229	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5230	if (fVerbose)
5231	pHlp->pfnPrintf(pHlp, " Address = %#RX64\n", MsiAddr.n.u62MsiAddr);
5232	}
5233	/* MSI Data. */
5234	{
5235	MSI_DATA_T MsiData;
5236	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5237	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5238	if (fVerbose)
5239	pHlp->pfnPrintf(pHlp, " Data = %#x\n", MsiData.n.u16MsiData);
5240	}
5241	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5242	{
5243	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5244	MsiMapCapHdr.u32 = 0;
5245	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5246	if (fVerbose)
5247	{
5248	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5249	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5250	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5251	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5252	}
5253	}
5254	/* Performance Optimization Control Register. */
5255	{
5256	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5257	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5258	if (fVerbose)
5259	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5260	}
5261	/* XT (x2APIC) General Interrupt Control Register. */
5262	{
5263	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5264	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5265	if (fVerbose)
5266	{
5267	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5268	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5269	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5270	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5271	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5272	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5273	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5274	}
5275	}
5276	/* XT (x2APIC) PPR Interrupt Control Register. */
5277	{
5278	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5279	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5280	if (fVerbose)
5281	{
5282	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5283	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5284	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5285	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5286	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5287	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5288	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5289	}
5290	}
5291	/* XT (X2APIC) GA Log Interrupt Control Register. */
5292	{
5293	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5294	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5295	if (fVerbose)
5296	{
5297	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5298	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5299	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5300	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5301	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5302	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5303	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5304	}
5305	}
5306	/* MARC Registers. */
5307	{
5308	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5309	{
5310	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5311	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5312	pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5313
5314	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5315	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5316	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5317	MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5318
5319	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5320	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5321	}
5322	}
5323	/* Reserved Register. */
5324	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5325	/* Command Buffer Head Pointer Register. */
5326	{
5327	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5328	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
5329	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
5330	}
5331	/* Command Buffer Tail Pointer Register. */
5332	{
5333	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5334	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
5335	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
5336	}
5337	/* Event Log Head Pointer Register. */
5338	{
5339	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5340	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
5341	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
5342	}
5343	/* Event Log Tail Pointer Register. */
5344	{
5345	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5346	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
5347	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
5348	}
5349	/* Status Register. */
5350	{
5351	IOMMU_STATUS_T const Status = pThis->Status;
5352	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5353	if (fVerbose)
5354	{
5355	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5356	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5357	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5358	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5359	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5360	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5361	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5362	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5363	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5364	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5365	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5366	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5367	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5368	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5369	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5370	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5371	}
5372	}
5373	/* PPR Log Head Pointer. */
5374	{
5375	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5376	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
5377	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
5378	}
5379	/* PPR Log Tail Pointer. */
5380	{
5381	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5382	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
5383	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
5384	}
5385	/* Guest Virtual-APIC Log Head Pointer. */
5386	{
5387	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5388	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
5389	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
5390	}
5391	/* Guest Virtual-APIC Log Tail Pointer. */
5392	{
5393	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5394	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
5395	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
5396	}
5397	/* PPR Log B Head Pointer. */
5398	{
5399	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5400	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
5401	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
5402	}
5403	/* PPR Log B Tail Pointer. */
5404	{
5405	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5406	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
5407	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
5408	}
5409	/* Event Log B Head Pointer. */
5410	{
5411	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5412	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
5413	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
5414	}
5415	/* Event Log B Tail Pointer. */
5416	{
5417	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5418	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
5419	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
5420	}
5421	/* PPR Log Auto Response Register. */
5422	{
5423	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5424	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5425	if (fVerbose)
5426	{
5427	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5428	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5429	}
5430	}
5431	/* PPR Log Overflow Early Warning Indicator Register. */
5432	{
5433	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5434	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5435	if (fVerbose)
5436	{
5437	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5438	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5439	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5440	}
5441	}
5442	/* PPR Log Overflow Early Warning Indicator Register. */
5443	{
5444	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5445	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5446	if (fVerbose)
5447	{
5448	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5449	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5450	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5451	}
5452	}
5453	}
5454
5455
5456	/**
5457	* @callback_method_impl{FNSSMDEVSAVEEXEC}
5458	*/
5459	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5460	{
5461	/** @todo IOMMU: Save state. */
5462	RT_NOREF2(pDevIns, pSSM);
5463	return VERR_NOT_IMPLEMENTED;
5464	}
5465
5466
5467	/**
5468	* @callback_method_impl{FNSSMDEVLOADEXEC}
5469	*/
5470	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5471	{
5472	/** @todo IOMMU: Load state. */
5473	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
5474	return VERR_NOT_IMPLEMENTED;
5475	}
5476
5477
5478	/**
5479	* @interface_method_impl{PDMDEVREG,pfnReset}
5480	*/
5481	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
5482	{
5483	/*
5484	* Resets read-write portion of the IOMMU state.
5485	*
5486	* State data not initialized here is expected to be initialized during
5487	* device construction and remain read-only through the lifetime of the VM.
5488	*/
5489	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5490	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5491	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5492
5493	memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
5494
5495	pThis->CmdBufBaseAddr.u64 = 0;
5496	pThis->CmdBufBaseAddr.n.u4Len = 8;
5497
5498	pThis->EvtLogBaseAddr.u64 = 0;
5499	pThis->EvtLogBaseAddr.n.u4Len = 8;
5500
5501	pThis->Ctrl.u64 = 0;
5502
5503	pThis->ExclRangeBaseAddr.u64 = 0;
5504	pThis->ExclRangeLimit.u64 = 0;
5505
5506	pThis->PprLogBaseAddr.u64 = 0;
5507	pThis->PprLogBaseAddr.n.u4Len = 8;
5508
5509	pThis->HwEvtHi.u64 = 0;
5510	pThis->HwEvtLo = 0;
5511	pThis->HwEvtStatus.u64 = 0;
5512
5513	pThis->GALogBaseAddr.u64 = 0;
5514	pThis->GALogBaseAddr.n.u4Len = 8;
5515	pThis->GALogTailAddr.u64 = 0;
5516
5517	pThis->PprLogBBaseAddr.u64 = 0;
5518	pThis->PprLogBBaseAddr.n.u4Len = 8;
5519
5520	pThis->EvtLogBBaseAddr.u64 = 0;
5521	pThis->EvtLogBBaseAddr.n.u4Len = 8;
5522
5523	pThis->MsiMiscInfo.u64 = 0;
5524	pThis->PerfOptCtrl.u32 = 0;
5525
5526	pThis->XtGenIntrCtrl.u64 = 0;
5527	pThis->XtPprIntrCtrl.u64 = 0;
5528	pThis->XtGALogIntrCtrl.u64 = 0;
5529
5530	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
5531
5532	pThis->CmdBufHeadPtr.u64 = 0;
5533	pThis->CmdBufTailPtr.u64 = 0;
5534	pThis->EvtLogHeadPtr.u64 = 0;
5535	pThis->EvtLogTailPtr.u64 = 0;
5536
5537	pThis->Status.u64 = 0;
5538
5539	pThis->PprLogHeadPtr.u64 = 0;
5540	pThis->PprLogTailPtr.u64 = 0;
5541
5542	pThis->GALogHeadPtr.u64 = 0;
5543	pThis->GALogTailPtr.u64 = 0;
5544
5545	pThis->PprLogBHeadPtr.u64 = 0;
5546	pThis->PprLogBTailPtr.u64 = 0;
5547
5548	pThis->EvtLogBHeadPtr.u64 = 0;
5549	pThis->EvtLogBTailPtr.u64 = 0;
5550
5551	pThis->PprLogAutoResp.u64 = 0;
5552	pThis->PprLogOverflowEarly.u64 = 0;
5553	pThis->PprLogBOverflowEarly.u64 = 0;
5554
5555	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
5556	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
5557	}
5558
5559
5560	/**
5561	* @interface_method_impl{PDMDEVREG,pfnDestruct}
5562	*/
5563	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
5564	{
5565	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5566	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5567	LogFlowFunc(("\n"));
5568
5569	/* Close the command thread semaphore. */
5570	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
5571	{
5572	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
5573	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
5574	}
5575	return VINF_SUCCESS;
5576	}
5577
5578
5579	/**
5580	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5581	*/
5582	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5583	{
5584	NOREF(iInstance);
5585
5586	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5587	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5588	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5589	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5590	int rc;
5591	LogFlowFunc(("\n"));
5592
5593	pThisCC->pDevInsR3 = pDevIns;
5594
5595	/*
5596	* Validate and read the configuration.
5597	*/
5598	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Device\|Function", "");
5599
5600	uint8_t uPciDevice;
5601	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Device", &uPciDevice, 0);
5602	if (RT_FAILURE(rc))
5603	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Device\""));
5604
5605	uint8_t uPciFunction;
5606	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Function", &uPciFunction, 2);
5607	if (RT_FAILURE(rc))
5608	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Function\""));
5609
5610	/*
5611	* Register the IOMMU with PDM.
5612	*/
5613	PDMIOMMUREGR3 IommuReg;
5614	RT_ZERO(IommuReg);
5615	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5616	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5617	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5618	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5619	rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
5620	if (RT_FAILURE(rc))
5621	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
5622	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
5623	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5624	N_("IOMMU helper version mismatch; got %#x expected %#x"),
5625	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
5626	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
5627	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5628	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
5629	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
5630
5631	/*
5632	* Initialize read-only PCI configuration space.
5633	*/
5634	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5635	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5636
5637	/* Header. */
5638	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
5639	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
5640	PDMPciDevSetCommand(pPciDev, 0); /* Command */
5641	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
5642	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
5643	PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
5644	PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
5645	PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
5646	PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
5647	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
5648	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
5649	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
5650	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
5651	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
5652
5653	/* Capability Header. */
5654	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
5655	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
5656	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
5657	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
5658	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
5659	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
5660	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
5661	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
5662	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
5663	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
5664
5665	/* Base Address Low Register. */
5666	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
5667
5668	/* Base Address High Register. */
5669	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
5670
5671	/* IOMMU Range Register. */
5672	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
5673
5674	/* Misc. Information Register 0. */
5675	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0,
5676	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
5677	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
5678	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
5679	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
5680	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
5681	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
5682
5683	/* Misc. Information Register 1. */
5684	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, 0);
5685
5686	/* MSI Capability Header register. */
5687	PDMMSIREG MsiReg;
5688	RT_ZERO(MsiReg);
5689	MsiReg.cMsiVectors = 1;
5690	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
5691	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
5692	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
5693	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5694	AssertRCReturn(rc, rc);
5695
5696	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
5697	#if 0
5698	/* MSI Address Lo. */
5699	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
5700	/* MSI Address Hi. */
5701	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
5702	/* MSI Data. */
5703	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
5704	#endif
5705
5706	#if 0
5707	/** @todo IOMMU: I don't know if we need to support this, enable later if
5708	* required. */
5709	/* MSI Mapping Capability Header register. */
5710	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
5711	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
5712	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
5713	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
5714	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
5715	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
5716	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
5717	#endif
5718
5719	/*
5720	* Register the PCI function with PDM.
5721	*/
5722	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /* fFlags */, uPciDevice, uPciFunction, "amd-iommu");
5723	AssertLogRelRCReturn(rc, rc);
5724
5725	/*
5726	* Intercept PCI config. space accesses.
5727	*/
5728	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
5729	AssertLogRelRCReturn(rc, rc);
5730
5731	/*
5732	* Create the MMIO region.
5733	* Mapping of the region is done when software configures it via PCI config space.
5734	*/
5735	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
5736	NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
5737	"AMD-IOMMU", &pThis->hMmio);
5738	AssertLogRelRCReturn(rc, rc);
5739
5740	/*
5741	* Register saved state.
5742	*/
5743	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
5744	NULL, NULL, NULL,
5745	NULL, iommuAmdR3SaveExec, NULL,
5746	NULL, iommuAmdR3LoadExec, NULL);
5747	AssertLogRelRCReturn(rc, rc);
5748
5749	/*
5750	* Register debugger info item.
5751	*/
5752	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
5753	AssertLogRelRCReturn(rc, rc);
5754
5755	/*
5756	* Create the command thread and its event semaphore.
5757	*/
5758	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5759	0 /* cbStack */, RTTHREADTYPE_IO, "AMD-IOMMU");
5760	AssertLogRelRCReturn(rc, rc);
5761
5762	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5763	AssertLogRelRCReturn(rc, rc);
5764
5765	/*
5766	* Initialize read-only registers.
5767	*/
5768	/** @todo Don't remove the =0 assignment for now. It's just there so it's easier
5769	* for me to see existing features that we might want to implement. Do it
5770	* later. */
5771	pThis->ExtFeat.u64 = 0;
5772	pThis->ExtFeat.n.u1PrefetchSup = 0;
5773	pThis->ExtFeat.n.u1PprSup = 0;
5774	pThis->ExtFeat.n.u1X2ApicSup = 0;
5775	pThis->ExtFeat.n.u1NoExecuteSup = 0;
5776	pThis->ExtFeat.n.u1GstTranslateSup = 0;
5777	pThis->ExtFeat.n.u1InvAllSup = 0;
5778	pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5779	pThis->ExtFeat.n.u1HwErrorSup = 1;
5780	pThis->ExtFeat.n.u1PerfCounterSup = 0;
5781	pThis->ExtFeat.n.u2HostAddrTranslateSize = IOMMU_MAX_HOST_PT_LEVEL;
5782	pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
5783	pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
5784	pThis->ExtFeat.n.u2SmiFilterSup = 0;
5785	pThis->ExtFeat.n.u3SmiFilterCount = 0;
5786	pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5787	pThis->ExtFeat.n.u2DualPprLogSup = 0;
5788	pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5789	pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
5790	pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5791	AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5792	pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5793	pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5794	pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5795	pThis->ExtFeat.n.u2MarcSup = 0;
5796	pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5797	pThis->ExtFeat.n.u1PerfOptSup = 0;
5798	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5799	pThis->ExtFeat.n.u1GstIoSup = 0;
5800	pThis->ExtFeat.n.u1HostAccessSup = 0;
5801	pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5802	pThis->ExtFeat.n.u1AttrForwardSup = 0;
5803	pThis->ExtFeat.n.u1HostDirtySup = 0;
5804	pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5805	pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5806	pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5807
5808	pThis->RsvdReg = 0;
5809
5810	pThis->DevSpecificFeat.u64 = 0;
5811	pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
5812	pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
5813
5814	pThis->DevSpecificCtrl.u64 = 0;
5815	pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
5816	pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
5817
5818	pThis->DevSpecificStatus.u64 = 0;
5819	pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
5820	pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
5821
5822	/*
5823	* Initialize parts of the IOMMU state as it would during reset.
5824	* Must be called -after- initializing PCI config. space registers.
5825	*/
5826	iommuAmdR3Reset(pDevIns);
5827
5828	return VINF_SUCCESS;
5829	}
5830
5831	# else /* !IN_RING3 */
5832
5833	/**
5834	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5835	*/
5836	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5837	{
5838	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5839	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5840	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5841
5842	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5843
5844	/* Set up the MMIO RZ handlers. */
5845	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5846	AssertRCReturn(rc, rc);
5847
5848	/* Set up the IOMMU RZ callbacks. */
5849	PDMIOMMUREGCC IommuReg;
5850	RT_ZERO(IommuReg);
5851	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5852	IommuReg.idxIommu = pThis->idxIommu;
5853	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5854	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5855	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5856	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5857	AssertRCReturn(rc, rc);
5858
5859	return VINF_SUCCESS;
5860	}
5861
5862	# endif /* !IN_RING3 */
5863
5864	/**
5865	* The device registration structure.
5866	*/
5867	const PDMDEVREG g_DeviceIommuAmd =
5868	{
5869	/* .u32Version = */ PDM_DEVREG_VERSION,
5870	/* .uReserved0 = */ 0,
5871	/* .szName = */ "iommu-amd",
5872	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
5873	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
5874	/* .cMaxInstances = */ ~0U,
5875	/* .uSharedVersion = */ 42,
5876	/* .cbInstanceShared = */ sizeof(IOMMU),
5877	/* .cbInstanceCC = */ sizeof(IOMMUCC),
5878	/* .cbInstanceRC = */ sizeof(IOMMURC),
5879	/* .cMaxPciDevices = */ 1,
5880	/* .cMaxMsixVectors = */ 0,
5881	/* .pszDescription = */ "IOMMU (AMD)",
5882	#if defined(IN_RING3)
5883	/* .pszRCMod = */ "VBoxDDRC.rc",
5884	/* .pszR0Mod = */ "VBoxDDR0.r0",
5885	/* .pfnConstruct = */ iommuAmdR3Construct,
5886	/* .pfnDestruct = */ iommuAmdR3Destruct,
5887	/* .pfnRelocate = */ NULL,
5888	/* .pfnMemSetup = */ NULL,
5889	/* .pfnPowerOn = */ NULL,
5890	/* .pfnReset = */ iommuAmdR3Reset,
5891	/* .pfnSuspend = */ NULL,
5892	/* .pfnResume = */ NULL,
5893	/* .pfnAttach = */ NULL,
5894	/* .pfnDetach = */ NULL,
5895	/* .pfnQueryInterface = */ NULL,
5896	/* .pfnInitComplete = */ NULL,
5897	/* .pfnPowerOff = */ NULL,
5898	/* .pfnSoftReset = */ NULL,
5899	/* .pfnReserved0 = */ NULL,
5900	/* .pfnReserved1 = */ NULL,
5901	/* .pfnReserved2 = */ NULL,
5902	/* .pfnReserved3 = */ NULL,
5903	/* .pfnReserved4 = */ NULL,
5904	/* .pfnReserved5 = */ NULL,
5905	/* .pfnReserved6 = */ NULL,
5906	/* .pfnReserved7 = */ NULL,
5907	#elif defined(IN_RING0)
5908	/* .pfnEarlyConstruct = */ NULL,
5909	/* .pfnConstruct = */ iommuAmdRZConstruct,
5910	/* .pfnDestruct = */ NULL,
5911	/* .pfnFinalDestruct = */ NULL,
5912	/* .pfnRequest = */ NULL,
5913	/* .pfnReserved0 = */ NULL,
5914	/* .pfnReserved1 = */ NULL,
5915	/* .pfnReserved2 = */ NULL,
5916	/* .pfnReserved3 = */ NULL,
5917	/* .pfnReserved4 = */ NULL,
5918	/* .pfnReserved5 = */ NULL,
5919	/* .pfnReserved6 = */ NULL,
5920	/* .pfnReserved7 = */ NULL,
5921	#elif defined(IN_RC)
5922	/* .pfnConstruct = */ iommuAmdRZConstruct,
5923	/* .pfnReserved0 = */ NULL,
5924	/* .pfnReserved1 = */ NULL,
5925	/* .pfnReserved2 = */ NULL,
5926	/* .pfnReserved3 = */ NULL,
5927	/* .pfnReserved4 = */ NULL,
5928	/* .pfnReserved5 = */ NULL,
5929	/* .pfnReserved6 = */ NULL,
5930	/* .pfnReserved7 = */ NULL,
5931	#else
5932	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5933	#endif
5934	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5935	};
5936
5937	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5938

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 84315

Download in other formats: