DevIommuAmd.cpp@ 84560

Last change on this file since 84560 was 84560, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 Interrupt remapping bits.
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1	/* $Id: DevIommuAmd.cpp 84560 2020-05-27 12:45:28Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/msi.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/AssertGuest.h>
26
27	#include "VBoxDD.h"
28	#include <iprt/x86.h>
29	#include <iprt/string.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/**
36	* @name PCI configuration register offsets.
37	* In accordance with the AMD spec.
38	* @{
39	*/
40	#define IOMMU_PCI_OFF_CAP_HDR 0x40
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
42	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
43	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
44	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
45	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
46	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
47	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
48	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
49	#define IOMMU_PCI_OFF_MSI_DATA 0x70
50	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
51	/** @} */
52
53	/**
54	* @name MMIO register offsets.
55	* In accordance with the AMD spec.
56	* @{
57	*/
58	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
59	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
60	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
61	#define IOMMU_MMIO_OFF_CTRL 0x18
62	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
63	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
64	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
65
66	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
67	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
68	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
69	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
70
71	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
72	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
73
74	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
75	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
76
77	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
78	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
79
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
81	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
82	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
83	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
84	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
85	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
86	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
87	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
88	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
89
90	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
91	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
92	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
93
94	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
95	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
96	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
97	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
98	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
99	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
100	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
101
102	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
103
104	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
105	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
106	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
107
108	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
109	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
110	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
111	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
112	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
113	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
114	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
115	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
116	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
117	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
118	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
119	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
120
121	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
122
123	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
124	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
125	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
126	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
127
128	#define IOMMU_MMIO_OFF_STATUS 0x2020
129
130	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
131	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
132
133	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
134	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
135
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
137	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
138
139	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
140	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
141
142	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
143	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
144	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
145	/** @} */
146
147	/**
148	* @name MMIO register-access table offsets.
149	* Each table [first..last] (both inclusive) represents the range of registers
150	* covered by a distinct register-access table. This is done due to arbitrary large
151	* gaps in the MMIO register offsets themselves.
152	* @{
153	*/
154	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
155	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
156
157	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
158	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
159	/** @} */
160
161	/**
162	* @name Commands.
163	* In accordance with the AMD spec.
164	* @{
165	*/
166	#define IOMMU_CMD_COMPLETION_WAIT 0x01
167	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
168	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
169	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
170	#define IOMMU_CMD_INV_INTR_TABLE 0x05
171	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
172	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
173	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
174	/** @} */
175
176	/**
177	* @name Event codes.
178	* In accordance with the AMD spec.
179	* @{
180	*/
181	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
182	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
183	#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
184	#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
185	#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
186	#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
187	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
188	#define IOMMU_EVT_INVALID_DEV_REQ 0x08
189	#define IOMMU_EVT_INVALID_PPR_REQ 0x09
190	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
191	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
192	/** @} */
193
194	/**
195	* @name IOMMU Capability Header.
196	* In accordance with the AMD spec.
197	* @{
198	*/
199	/** CapId: Capability ID. */
200	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
201	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
202	/** CapPtr: Capability Pointer. */
203	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
204	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
205	/** CapType: Capability Type. */
206	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
207	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
208	/** CapRev: Capability Revision. */
209	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
210	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
211	/** IoTlbSup: IO TLB Support. */
212	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
213	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
214	/** HtTunnel: HyperTransport Tunnel translation support. */
215	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
216	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
217	/** NpCache: Not Present table entries Cached. */
218	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
219	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
220	/** EFRSup: Extended Feature Register (EFR) Supported. */
221	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
222	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
223	/** CapExt: Miscellaneous Information Register Supported . */
224	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
225	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
226	/** Bits 31:29 reserved. */
227	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
228	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
229	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
230	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
231	/** @} */
232
233	/**
234	* @name IOMMU Base Address Low Register.
235	* In accordance with the AMD spec.
236	* @{
237	*/
238	/** Enable: Enables access to the address specified in the Base Address Register. */
239	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
240	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
241	/** Bits 13:1 reserved. */
242	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
243	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
244	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
245	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
246	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
247	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
248	(ENABLE, RSVD_1_13, ADDR));
249	/** @} */
250
251	/**
252	* @name IOMMU Range Register.
253	* In accordance with the AMD spec.
254	* @{
255	*/
256	/** UnitID: HyperTransport Unit ID. */
257	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
258	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
259	/** Bits 6:5 reserved. */
260	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
261	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
262	/** RngValid: Range valid. */
263	#define IOMMU_BF_RANGE_VALID_SHIFT 7
264	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
265	/** BusNumber: Device range bus number. */
266	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
267	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
268	/** First Device. */
269	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
270	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
271	/** Last Device. */
272	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
273	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
274	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
275	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
276	/** @} */
277
278	/**
279	* @name IOMMU Miscellaneous Information Register 0.
280	* In accordance with the AMD spec.
281	* @{
282	*/
283	/** MsiNum: MSI message number. */
284	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
285	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
286	/** GvaSize: Guest Virtual Address Size. */
287	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
288	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
289	/** PaSize: Physical Address Size. */
290	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
291	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
292	/** VaSize: Virtual Address Size. */
293	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
294	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
295	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
296	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
297	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
298	/** Bits 26:23 reserved. */
299	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
300	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
301	/** MsiNumPPR: Peripheral Page Request MSI message number. */
302	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
303	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
304	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
305	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
306	/** @} */
307
308	/**
309	* @name IOMMU Miscellaneous Information Register 1.
310	* In accordance with the AMD spec.
311	* @{
312	*/
313	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
314	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
315	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
316	/** Bits 31:5 reserved. */
317	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
318	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
319	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
320	(MSI_NUM_GA, RSVD_5_31));
321	/** @} */
322
323	/**
324	* @name MSI Capability Header Register.
325	* In accordance with the AMD spec.
326	* @{
327	*/
328	/** MsiCapId: Capability ID. */
329	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
330	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
331	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
332	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
333	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
334	/** MsiEn: Message Signal Interrupt enable. */
335	#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
336	#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
337	/** MsiMultMessCap: MSI Multi-Message Capability. */
338	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
339	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
340	/** MsiMultMessEn: MSI Mult-Message Enable. */
341	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
342	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
343	/** Msi64BitEn: MSI 64-bit Enabled. */
344	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
345	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
346	/** Bits 31:24 reserved. */
347	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
348	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
349	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
350	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
351	/** @} */
352
353	/**
354	* @name MSI Mapping Capability Header Register.
355	* In accordance with the AMD spec.
356	* @{
357	*/
358	/** MsiMapCapId: Capability ID. */
359	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
360	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
361	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
362	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
363	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
364	/** MsiMapEn: MSI mapping capability enable. */
365	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
366	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
367	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
368	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
369	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
370	/** Bits 18:28 reserved. */
371	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
372	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
373	/** MsiMapCapType: MSI mapping capability. */
374	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
375	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
376	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
377	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
378	/** @} */
379
380	/**
381	* @name IOMMU Status Register Bits.
382	* In accordance with the AMD spec.
383	* @{
384	*/
385	/** EventOverflow: Event log overflow. */
386	#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
387	/** EventLogInt: Event log interrupt. */
388	#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
389	/** ComWaitInt: Completion wait interrupt. */
390	#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
391	/** EventLogRun: Event log is running. */
392	#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
393	/** CmdBufRun: Command buffer is running. */
394	#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
395	/** PprOverflow: Peripheral page request log overflow. */
396	#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
397	/** PprInt: Peripheral page request log interrupt. */
398	#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
399	/** PprLogRun: Peripheral page request log is running. */
400	#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
401	/** GALogRun: Guest virtual-APIC log is running. */
402	#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
403	/** GALOverflow: Guest virtual-APIC log overflow. */
404	#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
405	/** GAInt: Guest virtual-APIC log interrupt. */
406	#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
407	/** PprOvrflwB: PPR Log B overflow. */
408	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
409	/** PprLogActive: PPR Log B is active. */
410	#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
411	/** EvtOvrflwB: Event log B overflow. */
412	#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
413	/** EventLogActive: Event log B active. */
414	#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
415	/** PprOvrflwEarlyB: PPR log B overflow early warning. */
416	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
417	/** PprOverflowEarly: PPR log overflow early warning. */
418	#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
419	/** @} */
420
421	/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
422	* In accordance with the AMD spec.
423	*
424	* These values match the shifted values of the IR and IW field of the DTE and the
425	* PTE, PDE of the I/O page tables.
426	*
427	* @{ */
428	#define IOMMU_IO_PERM_NONE (0)
429	#define IOMMU_IO_PERM_READ RT_BIT_64(0)
430	#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
431	#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ \| IOMMU_IO_PERM_WRITE)
432	#define IOMMU_IO_PERM_SHIFT 61
433	#define IOMMU_IO_PERM_MASK 0x3
434	/** @} */
435
436	/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
437	* In accordance with the AMD spec.
438	* @{ */
439	#define SYSMGTTYPE_DMA_DENY (0)
440	#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
441	#define SYSMGTTYPE_MSG_INT_ALLOW (2)
442	#define SYSMGTTYPE_DMA_ALLOW (3)
443	/** @} */
444
445	/** @name IOMMU_INTR_CTRL_XX: DTE::IntCtl field values.
446	* These are control bits for handling fixed and arbitrated interrupts.
447	* In accordance with the AMD spec.
448	* @{ */
449	#define IOMMU_INTR_CTRL_TARGET_ABORT (0)
450	#define IOMMU_INTR_CTRL_FWD_UNMAPPED (1)
451	#define IOMMU_INTR_CTRL_REMAP (2)
452	#define IOMMU_INTR_CTRL_RSVD (3)
453	/** @} */
454
455	/**
456	* @name IOMMU Control Register Bits.
457	* In accordance with the AMD spec.
458	* @{
459	*/
460	/** IommuEn: Enable the IOMMU. */
461	#define IOMMU_CTRL_IOMMU_EN RT_BIT_64(0)
462	/** HtTunEn: HyperTransport tunnel translation enable. */
463	#define IOMMU_CTRL_HT_TUNNEL_EN RT_BIT_64(1)
464	/** EventLogEn: Event log enable. */
465	#define IOMMU_CTRL_EVT_LOG_EN RT_BIT_64(2)
466	/** EventIntEn: Event interrupt enable. */
467	#define IOMMU_CTRL_EVT_INTR_EN RT_BIT_64(3)
468	/** ComWaitIntEn: Completion wait interrupt enable. */
469	#define IOMMU_CTRL_COMPLETION_WAIT_INTR_EN RT_BIT_64(4)
470	/** InvTimeout: Invalidation timeout. */
471	#define IOMMU_CTRL_INV_TIMEOUT RT_BIT_64(5) \| RT_BIT_64(6) \| RT_BIT_64(7)
472	/** @todo IOMMU: the rest or remove it. */
473	/** @} */
474
475	/** @name Miscellaneous IOMMU defines.
476	* @{ */
477	/** Log prefix string. */
478	#define IOMMU_LOG_PFX "AMD_IOMMU"
479	/** The current saved state version. */
480	#define IOMMU_SAVED_STATE_VERSION 1
481	/** AMD's vendor ID. */
482	#define IOMMU_PCI_VENDOR_ID 0x1022
483	/** VirtualBox IOMMU device ID. */
484	#define IOMMU_PCI_DEVICE_ID 0xc0de
485	/** VirtualBox IOMMU device revision ID. */
486	#define IOMMU_PCI_REVISION_ID 0x01
487	/** Size of the MMIO region in bytes. */
488	#define IOMMU_MMIO_REGION_SIZE _16K
489	/** Number of device table segments supported (power of 2). */
490	#define IOMMU_MAX_DEV_TAB_SEGMENTS 3
491	/** Maximum host address translation level supported (inclusive). */
492	#define IOMMU_MAX_HOST_PT_LEVEL 6
493	/** The IOTLB entry magic. */
494	#define IOMMU_IOTLBE_MAGIC 0x10acce55
495	/** The device-specific feature major revision. */
496	#define IOMMU_DEVSPEC_FEAT_MAJOR_VERSION 0x1
497	/** The device-specific feature minor revision. */
498	#define IOMMU_DEVSPEC_FEAT_MINOR_VERSION 0x0
499	/** The device-specific control major revision. */
500	#define IOMMU_DEVSPEC_CTRL_MAJOR_VERSION 0x1
501	/** The device-specific control minor revision. */
502	#define IOMMU_DEVSPEC_CTRL_MINOR_VERSION 0x0
503	/** The device-specific status major revision. */
504	#define IOMMU_DEVSPEC_STATUS_MAJOR_VERSION 0x1
505	/** The device-specific status minor revision. */
506	#define IOMMU_DEVSPEC_STATUS_MINOR_VERSION 0x0
507	/** @} */
508
509	/**
510	* Acquires the IOMMU PDM lock.
511	* This will make a long jump to ring-3 to acquire the lock if necessary.
512	*/
513	#define IOMMU_LOCK(a_pDevIns) \
514	do { \
515	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
516	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
517	{ /* likely */ } \
518	else \
519	return rcLock; \
520	} while (0)
521
522	/**
523	* Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
524	* This will make a long jump to ring-3 to acquire the lock if necessary.
525	*/
526	#define IOMMU_LOCK_NORET(a_pDevIns) \
527	do { \
528	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
529	AssertRC(rcLock); \
530	} while (0)
531
532	/**
533	* Releases the IOMMU PDM lock.
534	*/
535	#define IOMMU_UNLOCK(a_pDevIns) \
536	do { \
537	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
538	} while (0)
539
540	/**
541	* Asserts that the critsect is owned by this thread.
542	*/
543	#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
544	do { \
545	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
546	} while (0)
547
548	/**
549	* Asserts that the critsect is not owned by this thread.
550	*/
551	#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
552	do { \
553	Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
554	} while (0)
555
556	/**
557	* Gets the device table size given the size field.
558	*/
559	#define IOMMU_GET_DEV_TAB_SIZE(a_uSize) (((a_uSize) + 1) << X86_PAGE_4K_SHIFT)
560
561
562	/*********************************************************************************************************************************
563	* Structures and Typedefs *
564	*********************************************************************************************************************************/
565	/**
566	* The Device ID.
567	* In accordance with VirtualBox's PCI configuration.
568	*/
569	typedef union
570	{
571	struct
572	{
573	uint16_t u3Function : 3; /*< Bits 2:0 - Function. /
574	uint16_t u9Device : 9; /*< Bits 11:3 - Device. /
575	uint16_t u4Bus : 4; /*< Bits 15:12 - Bus. /
576	} n;
577	/** The unsigned integer view. */
578	uint16_t u;
579	} DEVICE_ID_T;
580	AssertCompileSize(DEVICE_ID_T, 2);
581
582	/**
583	* Device Table Entry (DTE).
584	* In accordance with the AMD spec.
585	*/
586	typedef union
587	{
588	struct
589	{
590	RT_GCC_EXTENSION uint64_t u1Valid : 1; /*< Bit 0 - V: Valid. /
591	RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
592	RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
593	RT_GCC_EXTENSION uint64_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
594	RT_GCC_EXTENSION uint64_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
595	RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /*< Bits 51:12 - Page Table Root Pointer. /
596	RT_GCC_EXTENSION uint64_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
597	RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
598	RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
599	RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
600	RT_GCC_EXTENSION uint64_t u2GstMode : 2; /*< Bits 57:56 - GLX: Guest Paging mode levels. /
601	RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). /
602	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
603	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
604	RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
605	RT_GCC_EXTENSION uint64_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
606	RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). /
607	RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /*< Bit 96 - I: IOTLB Enable. /
608	RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
609	RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
610	RT_GCC_EXTENSION uint64_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
611	RT_GCC_EXTENSION uint64_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
612	RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
613	RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
614	RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
615	RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
616	RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). /
617	RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
618	RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
619	RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
620	RT_GCC_EXTENSION uint64_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
621	RT_GCC_EXTENSION uint64_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
622	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
623	RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
624	RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
625	RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
626	RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
627	RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
628	RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 Pass-through. /
629	RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 Pass-through. /
630	RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /*< Bits 223:192 - Reserved. /
631	RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
632	RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
633	RT_GCC_EXTENSION uint64_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
634	RT_GCC_EXTENSION uint64_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
635	} n;
636	/** The 32-bit unsigned integer view. */
637	uint32_t au32[8];
638	/** The 64-bit unsigned integer view. */
639	uint64_t au64[4];
640	} DTE_T;
641	AssertCompileSize(DTE_T, 32);
642	/** Pointer to a device table entry. */
643	typedef DTE_T *PDTE_T;
644	/** Pointer to a const device table entry. */
645	typedef DTE_T const *PCDTE_T;
646
647	/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
648	* Support) feature (bits 52:53). */
649	#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
650
651	/** Mask of valid bits for GTSup (Guest Translation Support) feature (bits 55:60,
652	* bits 80:95). */
653	#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
654	#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
655
656	/* Mask of valid bits for GIoSup (Guest I/O Protection Support) feature (bit 54). */
657	#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
658
659	/* Mask of valid DTE feature bits. */
660	#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
661	\| IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
662	\| IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
663	#define IOMMU_DTE_QWORD_1_FEAT_MASK (IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
664
665	/* Mask of all valid DTE bits (including all feature bits). */
666	#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
667	#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
668	#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xf70fffffffffffff)
669	#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
670
671	/* Mask of the interrupt table root pointer. */
672	#define IOMMU_DTE_IRTE_ROOT_PTR_MASK UINT64_C(0x000fffffffffff80)
673
674	/**
675	* I/O Page Translation Entry.
676	* In accordance with the AMD spec.
677	*/
678	typedef union
679	{
680	struct
681	{
682	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
683	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
684	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
685	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
686	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
687	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
688	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
689	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
690	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
691	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
692	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
693	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
694	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
695	} n;
696	/** The 64-bit unsigned integer view. */
697	uint64_t u64;
698	} IOPTE_T;
699	AssertCompileSize(IOPTE_T, 8);
700
701	/**
702	* I/O Page Directory Entry.
703	* In accordance with the AMD spec.
704	*/
705	typedef union
706	{
707	struct
708	{
709	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
710	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
711	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
712	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
713	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
714	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
715	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
716	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
717	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
718	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
719	} n;
720	/** The 64-bit unsigned integer view. */
721	uint64_t u64;
722	} IOPDE_T;
723	AssertCompileSize(IOPDE_T, 8);
724
725	/**
726	* I/O Page Table Entity.
727	* In accordance with the AMD spec.
728	*
729	* This a common subset of an DTE.au64[0], PTE and PDE.
730	* Named as an "entity" to avoid confusing it with PTE.
731	*/
732	typedef union
733	{
734	struct
735	{
736	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
737	RT_GCC_EXTENSION uint64_t u8Ign0 : 8; /*< Bits 8:1 - Ignored. /
738	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Mode / Next Level: Next page translation level. /
739	RT_GCC_EXTENSION uint64_t u40Addr : 40; /*< Bits 51:12 - Page address. /
740	RT_GCC_EXTENSION uint64_t u9Ign0 : 9; /*< Bits 60:52 - Ignored. /
741	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
742	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
743	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
744	} n;
745	/** The 64-bit unsigned integer view. */
746	uint64_t u64;
747	} IOPTENTITY_T;
748	AssertCompileSize(IOPTENTITY_T, 8);
749	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPTE_T));
750	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPDE_T));
751	/** Pointer to an IOPT_ENTITY_T struct. */
752	typedef IOPTENTITY_T *PIOPTENTITY_T;
753	/** Pointer to a const IOPT_ENTITY_T struct. */
754	typedef IOPTENTITY_T const *PCIOPTENTITY_T;
755	/** Mask of the address field. */
756	#define IOMMU_PTENTITY_ADDR_MASK UINT64_C(0x000ffffffffff000)
757
758	/**
759	* Interrupt Remapping Table Entry (IRTE).
760	* In accordance with the AMD spec.
761	*/
762	typedef union
763	{
764	struct
765	{
766	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
767	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
768	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
769	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
770	uint32_t u1DestMode : 1; /*< Bit 6 - DM: Destination Mode. /
771	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
772	uint32_t u8Dest : 8; /*< Bits 15:8 - Destination. /
773	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
774	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
775	} n;
776	/** The 32-bit unsigned integer view. */
777	uint32_t u32;
778	} IRTE_T;
779	AssertCompileSize(IRTE_T, 4);
780	/** The number of bits to shift the IRTE offset to get the IRTE. */
781	#define IOMMU_IRTE_SIZE_SHIFT (2)
782	/** Pointer to an IRTE_T struct. */
783	typedef IRTE_T *PIRTE_T;
784	/** Pointer to a const IRTE_T struct. */
785	typedef IRTE_T const *PCIRTE_T;
786
787	/**
788	* Command: Generic Command Buffer Entry.
789	* In accordance with the AMD spec.
790	*/
791	typedef union
792	{
793	struct
794	{
795	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
796	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
797	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
798	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
799	} n;
800	/** The 64-bit unsigned integer view. */
801	uint64_t au64[2];
802	} CMD_GENERIC_T;
803	AssertCompileSize(CMD_GENERIC_T, 16);
804	/** Pointer to a generic command buffer entry. */
805	typedef CMD_GENERIC_T *PCMD_GENERIC_T;
806	/** Pointer to a const generic command buffer entry. */
807	typedef CMD_GENERIC_T const *PCCMD_GENERIC_T;
808
809	/** Number of bits to shift the byte offset of a command in the command buffer to
810	* get its index. */
811	#define IOMMU_CMD_GENERIC_SHIFT 4
812
813	/**
814	* Command: COMPLETION_WAIT.
815	* In accordance with the AMD spec.
816	*/
817	typedef union
818	{
819	struct
820	{
821	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
822	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
823	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
824	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
825	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
826	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
827	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
828	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
829	} n;
830	/** The 64-bit unsigned integer view. */
831	uint64_t au64[2];
832	} CMD_COMWAIT_T;
833	AssertCompileSize(CMD_COMWAIT_T, 16);
834	/** Pointer to a completion wait command. */
835	typedef CMD_COMWAIT_T *PCMD_COMWAIT_T;
836	/** Pointer to a const completion wait command. */
837	typedef CMD_COMWAIT_T const *PCCMD_COMWAIT_T;
838	#define IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK UINT64_C(0xf00fffffffffffff)
839
840	/**
841	* Command: INVALIDATE_DEVTAB_ENTRY.
842	* In accordance with the AMD spec.
843	*/
844	typedef union
845	{
846	struct
847	{
848	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
849	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
850	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
851	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
852	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
853	} n;
854	/** The 64-bit unsigned integer view. */
855	uint64_t au64[2];
856	} CMD_INV_DTE_T;
857	AssertCompileSize(CMD_INV_DTE_T, 16);
858
859	/**
860	* Command: INVALIDATE_IOMMU_PAGES.
861	* In accordance with the AMD spec.
862	*/
863	typedef union
864	{
865	struct
866	{
867	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
868	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
869	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
870	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
871	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
872	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
873	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
874	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
875	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
876	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
877	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
878	} n;
879	/** The 64-bit unsigned integer view. */
880	uint64_t au64[2];
881	} CMD_INV_IOMMU_PAGES_T;
882	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
883
884	/**
885	* Command: INVALIDATE_IOTLB_PAGES.
886	* In accordance with the AMD spec.
887	*/
888	typedef union
889	{
890	struct
891	{
892	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
893	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
894	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
895	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
896	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
897	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
898	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
899	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
900	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
901	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
902	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
903	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
904	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
905	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
906	} n;
907	/** The 64-bit unsigned integer view. */
908	uint64_t au64[2];
909	} CMD_INV_IOTLB_PAGES_T;
910	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
911
912	/**
913	* Command: INVALIDATE_INTR_TABLE.
914	* In accordance with the AMD spec.
915	*/
916	typedef union
917	{
918	struct
919	{
920	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
921	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
922	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
923	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
924	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
925	} u;
926	/** The 64-bit unsigned integer view. */
927	uint64_t au64[2];
928	} CMD_INV_INTR_TABLE_T;
929	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
930
931	/**
932	* Command: COMPLETE_PPR_REQ.
933	* In accordance with the AMD spec.
934	*/
935	typedef union
936	{
937	struct
938	{
939	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
940	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
941	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
942	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
943	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
944	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
945	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
946	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
947	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
948	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
949	} n;
950	/** The 64-bit unsigned integer view. */
951	uint64_t au64[2];
952	} CMD_COMPLETE_PPR_REQ_T;
953	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
954
955	/**
956	* Command: INV_IOMMU_ALL.
957	* In accordance with the AMD spec.
958	*/
959	typedef union
960	{
961	struct
962	{
963	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
964	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
965	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
966	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
967	} n;
968	/** The 64-bit unsigned integer view. */
969	uint64_t au64[2];
970	} CMD_IOMMU_ALL_T;
971	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
972
973	/**
974	* Event Log Entry: Generic.
975	* In accordance with the AMD spec.
976	*/
977	typedef union
978	{
979	struct
980	{
981	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
982	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
983	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
984	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
985	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
986	} n;
987	/** The 32-bit unsigned integer view. */
988	uint32_t au32[4];
989	} EVT_GENERIC_T;
990	AssertCompileSize(EVT_GENERIC_T, 16);
991	/** Number of bits to shift the byte offset of an event entry in the event log
992	* buffer to get its index. */
993	#define IOMMU_EVT_GENERIC_SHIFT 4
994	/** Pointer to a generic event log entry. */
995	typedef EVT_GENERIC_T *PEVT_GENERIC_T;
996	/** Pointer to a const generic event log entry. */
997	typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
998
999	/**
1000	* Hardware event types.
1001	* In accordance with the AMD spec.
1002	*/
1003	typedef enum HWEVTTYPE
1004	{
1005	HWEVTTYPE_RSVD = 0,
1006	HWEVTTYPE_MASTER_ABORT,
1007	HWEVTTYPE_TARGET_ABORT,
1008	HWEVTTYPE_DATA_ERROR
1009	} HWEVTTYPE;
1010	AssertCompileSize(HWEVTTYPE, 4);
1011
1012	/**
1013	* Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
1014	* In accordance with the AMD spec.
1015	*/
1016	typedef union
1017	{
1018	struct
1019	{
1020	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1021	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1022	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
1023	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1024	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1025	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1026	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1027	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1028	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1029	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
1030	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1031	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1032	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
1033	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1034	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1035	} n;
1036	/** The 32-bit unsigned integer view. */
1037	uint32_t au32[4];
1038	/** The 64-bit unsigned integer view. */
1039	uint64_t au64[2];
1040	} EVT_ILLEGAL_DTE_T;
1041	AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
1042	/** Pointer to an illegal device table entry event. */
1043	typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
1044	/** Pointer to a const illegal device table entry event. */
1045	typedef EVT_ILLEGAL_DTE_T const *PCEVT_ILLEGAL_DTE_T;
1046
1047	/**
1048	* Event Log Entry: IO_PAGE_FAULT_EVENT.
1049	* In accordance with the AMD spec.
1050	*/
1051	typedef union
1052	{
1053	struct
1054	{
1055	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1056	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1057	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1058	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1059	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
1060	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
1061	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1062	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
1063	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1064	uint16_t u1PermDenied : 1; /*< Bit 54 - PE: Permission Indicator. /
1065	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1066	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1067	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
1068	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1069	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1070	} n;
1071	/** The 32-bit unsigned integer view. */
1072	uint32_t au32[4];
1073	/** The 64-bit unsigned integer view. */
1074	uint64_t au64[2];
1075	} EVT_IO_PAGE_FAULT_T;
1076	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
1077	/** Pointer to an I/O page fault event. */
1078	typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
1079	/** Pointer to a const I/O page fault event. */
1080	typedef EVT_IO_PAGE_FAULT_T const *PCEVT_IO_PAGE_FAULT_T;
1081
1082
1083	/**
1084	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
1085	* In accordance with the AMD spec.
1086	*/
1087	typedef union
1088	{
1089	struct
1090	{
1091	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1092	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1093	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
1094	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). /
1095	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1096	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). /
1097	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
1098	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation (1=translation, 0=transaction). /
1099	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1100	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1101	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1102	uint64_t u64Addr; /*< Bits 127:64 - Address. /
1103	} n;
1104	/** The 32-bit unsigned integer view. */
1105	uint32_t au32[4];
1106	/** The 64-bit unsigned integer view. */
1107	uint64_t au64[2];
1108	} EVT_DEV_TAB_HW_ERROR_T;
1109	AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1110	/** Pointer to a device table hardware error event. */
1111	typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1112	/** Pointer to a const device table hardware error event. */
1113	typedef EVT_DEV_TAB_HW_ERROR_T const *PCEVT_DEV_TAB_HW_ERROR_T;
1114
1115	/**
1116	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1117	* In accordance with the AMD spec.
1118	*/
1119	typedef union
1120	{
1121	struct
1122	{
1123	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1124	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1125	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1126	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1127	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1128	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1129	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1130	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1131	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
1132	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
1133	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1134	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1135	uint32_t u4EvtCode : 4; /*< Bit 63:60 - Event code. /
1136	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1137	* table 58 mentions Addr[31:4], we just use the full 64-bits. Looks like a
1138	* typo in the figure.See AMD AMD IOMMU spec (3.05-PUB, Jan 2020). */
1139	uint64_t u64Addr; /** Bits 127:64 - Address: SPA of the page table entry. */
1140	} n;
1141	/** The 32-bit unsigned integer view. */
1142	uint32_t au32[4];
1143	/** The 64-bit unsigned integer view. */
1144	uint64_t au64[2];
1145	} EVT_PAGE_TAB_HW_ERR_T;
1146	AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1147	/** Pointer to a page table hardware error event. */
1148	typedef EVT_PAGE_TAB_HW_ERR_T *PEVT_PAGE_TAB_HW_ERR_T;
1149	/** Pointer to a const page table hardware error event. */
1150	typedef EVT_PAGE_TAB_HW_ERR_T const *PCEVT_PAGE_TAB_HW_ERR_T;
1151
1152	/**
1153	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
1154	* In accordance with the AMD spec.
1155	*/
1156	typedef union
1157	{
1158	struct
1159	{
1160	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1161	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
1162	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1163	uint64_t u64Addr; /*< Bits 127:64 - Address: SPA of the invalid command. /
1164	} n;
1165	/** The 32-bit unsigned integer view. */
1166	uint32_t au32[4];
1167	/** The 64-bit unsigned integer view. */
1168	uint64_t au64[2];
1169	} EVT_ILLEGAL_CMD_ERR_T;
1170	AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1171	/** Pointer to an illegal command error event. */
1172	typedef EVT_ILLEGAL_CMD_ERR_T *PEVT_ILLEGAL_CMD_ERR_T;
1173	/** Pointer to a const illegal command error event. */
1174	typedef EVT_ILLEGAL_CMD_ERR_T const *PCEVT_ILLEGAL_CMD_ERR_T;
1175
1176	/**
1177	* Event Log Entry: COMMAND_HARDWARE_ERROR.
1178	* In accordance with the AMD spec.
1179	*/
1180	typedef union
1181	{
1182	struct
1183	{
1184	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1185	uint32_t u25Rsvd1 : 25; /*< Bits 56:32 - Reserved. /
1186	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1187	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1188	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1189	uint64_t u64Addr; /*< Bits 128:64 - Address: SPA of the attempted access. /
1190	} n;
1191	/** The 32-bit unsigned integer view. */
1192	uint32_t au32[4];
1193	/** The 64-bit unsigned integer view. */
1194	uint64_t au64[2];
1195	} EVT_CMD_HW_ERR_T;
1196	AssertCompileSize(EVT_CMD_HW_ERR_T, 16);
1197	/** Pointer to a command hardware error event. */
1198	typedef EVT_CMD_HW_ERR_T *PEVT_CMD_HW_ERR_T;
1199	/** Pointer to a const command hardware error event. */
1200	typedef EVT_CMD_HW_ERR_T const *PCEVT_CMD_HW_ERR_T;
1201
1202	/**
1203	* Event Log Entry: IOTLB_INV_TIMEOUT.
1204	* In accordance with the AMD spec.
1205	*/
1206	typedef union
1207	{
1208	struct
1209	{
1210	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1211	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
1212	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1213	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1214	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1215	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
1216	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
1217	} n;
1218	/** The 32-bit unsigned integer view. */
1219	uint32_t au32[4];
1220	} EVT_IOTLB_INV_TIMEOUT_T;
1221	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1222
1223	/**
1224	* Event Log Entry: INVALID_DEVICE_REQUEST.
1225	* In accordance with the AMD spec.
1226	*/
1227	typedef union
1228	{
1229	struct
1230	{
1231	uint32_t u16DevId : 16; /**< Bits 15:0 - Device ID. /
1232	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1233	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
1234	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1235	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1236	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
1237	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
1238	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
1239	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
1240	uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. /
1241	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
1242	} n;
1243	/** The 32-bit unsigned integer view. */
1244	uint32_t au32[4];
1245	} EVT_INVALID_DEV_REQ_T;
1246	AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1247
1248	/**
1249	* Event Log Entry: EVENT_COUNTER_ZERO.
1250	* In accordance with the AMD spec.
1251	*/
1252	typedef union
1253	{
1254	struct
1255	{
1256	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1257	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1258	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1259	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
1260	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
1261	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
1262	} n;
1263	/** The 32-bit unsigned integer view. */
1264	uint32_t au32[4];
1265	} EVT_EVENT_COUNTER_ZERO_T;
1266	AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1267
1268	/**
1269	* IOMMU Capability Header (PCI).
1270	* In accordance with the AMD spec.
1271	*/
1272	typedef union
1273	{
1274	struct
1275	{
1276	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
1277	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
1278	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
1279	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
1280	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
1281	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
1282	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
1283	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
1284	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
1285	uint32_t u3Rsvd0 : 3; /*< Bits 31:29 - Reserved. /
1286	} n;
1287	/** The 32-bit unsigned integer view. */
1288	uint32_t u32;
1289	} IOMMU_CAP_HDR_T;
1290	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1291
1292	/**
1293	* IOMMU Base Address (Lo and Hi) Register (PCI).
1294	* In accordance with the AMD spec.
1295	*/
1296	typedef union
1297	{
1298	struct
1299	{
1300	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1301	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1302	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1303	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1304	} n;
1305	/** The 32-bit unsigned integer view. */
1306	uint32_t au32[2];
1307	/** The 64-bit unsigned integer view. */
1308	uint64_t u64;
1309	} IOMMU_BAR_T;
1310	AssertCompileSize(IOMMU_BAR_T, 8);
1311	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1312
1313	/**
1314	* IOMMU Range Register (PCI).
1315	* In accordance with the AMD spec.
1316	*/
1317	typedef union
1318	{
1319	struct
1320	{
1321	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1322	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1323	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1324	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1325	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1326	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1327	} n;
1328	/** The 32-bit unsigned integer view. */
1329	uint32_t u32;
1330	} IOMMU_RANGE_T;
1331	AssertCompileSize(IOMMU_RANGE_T, 4);
1332
1333	/**
1334	* Device Table Base Address Register (MMIO).
1335	* In accordance with the AMD spec.
1336	*/
1337	typedef union
1338	{
1339	struct
1340	{
1341	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1342	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1343	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1344	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1345	} n;
1346	/** The 64-bit unsigned integer view. */
1347	uint64_t u64;
1348	} DEV_TAB_BAR_T;
1349	AssertCompileSize(DEV_TAB_BAR_T, 8);
1350	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1351	#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1352
1353	/**
1354	* Command Buffer Base Address Register (MMIO).
1355	* In accordance with the AMD spec.
1356	*/
1357	typedef union
1358	{
1359	struct
1360	{
1361	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1362	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1363	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1364	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1365	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1366	} n;
1367	/** The 64-bit unsigned integer view. */
1368	uint64_t u64;
1369	} CMD_BUF_BAR_T;
1370	AssertCompileSize(CMD_BUF_BAR_T, 8);
1371	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1372
1373	/**
1374	* Event Log Base Address Register (MMIO).
1375	* In accordance with the AMD spec.
1376	*/
1377	typedef union
1378	{
1379	struct
1380	{
1381	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1382	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1383	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1384	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - EventLen: Event log length. /
1385	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1386	} n;
1387	/** The 64-bit unsigned integer view. */
1388	uint64_t u64;
1389	} EVT_LOG_BAR_T;
1390	AssertCompileSize(EVT_LOG_BAR_T, 8);
1391	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1392
1393	/**
1394	* IOMMU Control Register (MMIO).
1395	* In accordance with the AMD spec.
1396	*/
1397	typedef union
1398	{
1399	struct
1400	{
1401	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1402	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1403	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1404	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1405	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1406	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1407	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1408	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1409	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1410	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1411	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1412	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1413	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1414	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1415	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1416	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1417	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1418	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1419	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1420	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1421	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1422	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1423	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1424	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1425	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1426	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1427	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1428	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1429	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1430	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1431	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1432	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1433	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1434	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1435	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1436	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1437	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1438	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1439	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1440	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1441	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1442	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1443	} n;
1444	/** The 64-bit unsigned integer view. */
1445	uint64_t u64;
1446	} IOMMU_CTRL_T;
1447	AssertCompileSize(IOMMU_CTRL_T, 8);
1448	#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1449	#define IOMMU_CTRL_CMD_BUF_EN_MASK UINT64_C(0x0000000000001001)
1450
1451	/**
1452	* IOMMU Exclusion Base Register (MMIO).
1453	* In accordance with the AMD spec.
1454	*/
1455	typedef union
1456	{
1457	struct
1458	{
1459	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1460	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1461	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1462	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1463	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1464	} n;
1465	/** The 64-bit unsigned integer view. */
1466	uint64_t u64;
1467	} IOMMU_EXCL_RANGE_BAR_T;
1468	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1469	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1470
1471	/**
1472	* IOMMU Exclusion Range Limit Register (MMIO).
1473	* In accordance with the AMD spec.
1474	*/
1475	typedef union
1476	{
1477	struct
1478	{
1479	RT_GCC_EXTENSION uint64_t u52ExclLimit : 52; /*< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). /
1480	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1481	} n;
1482	/** The 64-bit unsigned integer view. */
1483	uint64_t u64;
1484	} IOMMU_EXCL_RANGE_LIMIT_T;
1485	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1486	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1487
1488	/**
1489	* IOMMU Extended Feature Register (MMIO).
1490	* In accordance with the AMD spec.
1491	*/
1492	typedef union
1493	{
1494	struct
1495	{
1496	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1497	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1498	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1499	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1500	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations (for GVAs) Support. /
1501	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1502	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1503	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1504	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1505	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1506	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1507	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1508	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1509	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1510	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1511	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1512	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1513	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1514	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1515	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1516	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1517	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1518	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1519	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1520	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1521	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1522	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1523	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1524	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1525	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1526	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1527	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1528	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1529	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1530	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1531	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1532	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1533	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1534	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1535	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1536	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1537	} n;
1538	/** The 64-bit unsigned integer view. */
1539	uint64_t u64;
1540	} IOMMU_EXT_FEAT_T;
1541	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1542
1543	/**
1544	* Peripheral Page Request Log Base Address Register (MMIO).
1545	* In accordance with the AMD spec.
1546	*/
1547	typedef union
1548	{
1549	struct
1550	{
1551	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1552	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1553	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1554	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1555	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1556	} n;
1557	/** The 64-bit unsigned integer view. */
1558	uint64_t u64;
1559	} PPR_LOG_BAR_T;
1560	AssertCompileSize(PPR_LOG_BAR_T, 8);
1561	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1562
1563	/**
1564	* IOMMU Hardware Event Upper Register (MMIO).
1565	* In accordance with the AMD spec.
1566	*/
1567	typedef union
1568	{
1569	struct
1570	{
1571	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1572	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1573	} n;
1574	/** The 64-bit unsigned integer view. */
1575	uint64_t u64;
1576	} IOMMU_HW_EVT_HI_T;
1577	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1578
1579	/**
1580	* IOMMU Hardware Event Lower Register (MMIO).
1581	* In accordance with the AMD spec.
1582	*/
1583	typedef uint64_t IOMMU_HW_EVT_LO_T;
1584
1585	/**
1586	* IOMMU Hardware Event Status (MMIO).
1587	* In accordance with the AMD spec.
1588	*/
1589	typedef union
1590	{
1591	struct
1592	{
1593	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1594	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1595	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1596	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1597	} n;
1598	/** The 64-bit unsigned integer view. */
1599	uint64_t u64;
1600	} IOMMU_HW_EVT_STATUS_T;
1601	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1602	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1603
1604	/**
1605	* Guest Virtual-APIC Log Base Address Register (MMIO).
1606	* In accordance with the AMD spec.
1607	*/
1608	typedef union
1609	{
1610	struct
1611	{
1612	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1613	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1614	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1615	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1616	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1617	} n;
1618	/** The 64-bit unsigned integer view. */
1619	uint64_t u64;
1620	} GALOG_BAR_T;
1621	AssertCompileSize(GALOG_BAR_T, 8);
1622
1623	/**
1624	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1625	* In accordance with the AMD spec.
1626	*/
1627	typedef union
1628	{
1629	struct
1630	{
1631	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1632	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1633	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1634	} n;
1635	/** The 64-bit unsigned integer view. */
1636	uint64_t u64;
1637	} GALOG_TAIL_ADDR_T;
1638	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1639
1640	/**
1641	* PPR Log B Base Address Register (MMIO).
1642	* In accordance with the AMD spec.
1643	* Currently identical to PPR_LOG_BAR_T.
1644	*/
1645	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1646
1647	/**
1648	* Event Log B Base Address Register (MMIO).
1649	* In accordance with the AMD spec.
1650	* Currently identical to EVT_LOG_BAR_T.
1651	*/
1652	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1653
1654	/**
1655	* Device-specific Feature Extension (DSFX) Register (MMIO).
1656	* In accordance with the AMD spec.
1657	*/
1658	typedef union
1659	{
1660	struct
1661	{
1662	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1663	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1664	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1665	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1666	} n;
1667	/** The 64-bit unsigned integer view. */
1668	uint64_t u64;
1669	} DEV_SPECIFIC_FEAT_T;
1670	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1671
1672	/**
1673	* Device-specific Control Extension (DSCX) Register (MMIO).
1674	* In accordance with the AMD spec.
1675	*/
1676	typedef union
1677	{
1678	struct
1679	{
1680	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1681	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1682	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1683	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1684	} n;
1685	/** The 64-bit unsigned integer view. */
1686	uint64_t u64;
1687	} DEV_SPECIFIC_CTRL_T;
1688	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1689
1690	/**
1691	* Device-specific Status Extension (DSSX) Register (MMIO).
1692	* In accordance with the AMD spec.
1693	*/
1694	typedef union
1695	{
1696	struct
1697	{
1698	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1699	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1700	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1701	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1702	} n;
1703	/** The 64-bit unsigned integer view. */
1704	uint64_t u64;
1705	} DEV_SPECIFIC_STATUS_T;
1706	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1707
1708	/**
1709	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1710	* In accordance with the AMD spec.
1711	*/
1712	typedef union
1713	{
1714	struct
1715	{
1716	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1717	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1718	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1719	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1720	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1721	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1722	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1723	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1724	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1725	} n;
1726	/** The 32-bit unsigned integer view. */
1727	uint32_t au32[2];
1728	/** The 64-bit unsigned integer view. */
1729	uint64_t u64;
1730	} MSI_MISC_INFO_T;
1731	AssertCompileSize(MSI_MISC_INFO_T, 8);
1732	/** MSI Vector Register 0 and 1 (MMIO). */
1733	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1734
1735	/**
1736	* MSI Capability Header Register (PCI + MMIO).
1737	* In accordance with the AMD spec.
1738	*/
1739	typedef union
1740	{
1741	struct
1742	{
1743	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1744	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1745	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1746	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1747	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1748	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1749	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1750	} n;
1751	/** The 32-bit unsigned integer view. */
1752	uint32_t u32;
1753	} MSI_CAP_HDR_T;
1754	AssertCompileSize(MSI_CAP_HDR_T, 4);
1755	#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1756
1757	/**
1758	* MSI Address Register (PCI + MMIO).
1759	* In accordance to the Intel spec.
1760	* See Intel spec. 10.11.1 "Message Address Register Format".
1761	*
1762	* This also conforms to the AMD IOMMU spec. which omits specifying individual
1763	* fields but specifies reserved bits.
1764	*/
1765	typedef union
1766	{
1767	struct
1768	{
1769	uint32_t u2Ign0 : 2; /*< Bits 1:0 - Ignored (read as 0, writes ignored). /
1770	uint32_t u1DestMode : 1; /*< Bit 2 - DM: Destination Mode. /
1771	uint32_t u1RedirHint : 1; /*< Bit 3 - RH: Redirection Hint. /
1772	uint32_t u8Rsvd0 : 8; /*< Bits 11:4 - Reserved. /
1773	uint32_t u8DestId : 8; /*< Bits 19:12 - Destination Id. /
1774	uint32_t u12Addr : 12; /*< Bits 31:20 - Address. /
1775	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1776	} n;
1777	/** The 32-bit unsigned integer view. */
1778	uint32_t au32[2];
1779	/** The 64-bit unsigned integer view. */
1780	uint64_t u64;
1781	} MSI_ADDR_T;
1782	AssertCompileSize(MSI_ADDR_T, 8);
1783	/** According to the AMD IOMMU spec. the top 32-bits are not reserved. From a
1784	* PCI/IOMMU standpoint this makes sense. However, when dealing with the CPU side
1785	* of things we might want to ensure the upper bits are reserved. Does x86/x64
1786	* really support a 64-bit MSI address? */
1787	#define IOMMU_MSI_ADDR_VALID_MASK UINT64_C(0xfffffffffffffffc)
1788	#define IOMMU_MSI_ADDR_ADDR_MASK UINT64_C(0x00000000fff00000)
1789	/** Pointer to an MSI address register. */
1790	typedef MSI_ADDR_T *PMSI_ADDR_T;
1791	/** Pointer to a const MSI address register. */
1792	typedef MSI_ADDR_T const *PCMSI_ADDR_T;
1793
1794	/**
1795	* MSI Data Register (PCI + MMIO).
1796	* In accordance to the Intel spec.
1797	* See Intel spec. 10.11.2 "Message Data Register Format".
1798	*
1799	* This also conforms to the AMD IOMMU spec. which omits specifying individual
1800	* fields but specifies reserved bits.
1801	*/
1802	typedef union
1803	{
1804	struct
1805	{
1806	uint32_t u8Vector : 8; /*< Bits 7:0 - Vector. /
1807	uint32_t u3DeliveryMode : 3; /*< Bits 10:8 - Delivery Mode. /
1808	uint32_t u3Rsvd0 : 3; /*< Bits 13:11 - Reserved. /
1809	uint32_t u1Level : 1; /*< Bit 14 - Level. /
1810	uint32_t u1TriggerMode : 1; /*< Bit 15 - Trigger Mode (0=edge, 1=level). /
1811	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
1812	} n;
1813	/** The 32-bit unsigned integer view. */
1814	uint32_t u32;
1815	} MSI_DATA_T;
1816	AssertCompileSize(MSI_DATA_T, 4);
1817	#define IOMMU_MSI_DATA_VALID_MASK UINT64_C(0x000000000000ffff)
1818	/** The IRTE offset corresponds directly to bits 10:0 of the originating MSI
1819	* interrupt message. See AMD IOMMU spec. 2.2.5 "Interrupt Remapping Tables". */
1820	#define IOMMU_MSI_DATA_IRTE_OFFSET_MASK UINT32_C(0x000007ff)
1821
1822	/** Pointer to an MSI data register. */
1823	typedef MSI_DATA_T *PMSI_DATA_T;
1824	/** Pointer to a const MSI data register. */
1825	typedef MSI_DATA_T const *PCMSI_DATA_T;
1826
1827	/**
1828	* MSI Mapping Capability Header Register (PCI + MMIO).
1829	* In accordance with the AMD spec.
1830	*/
1831	typedef union
1832	{
1833	struct
1834	{
1835	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1836	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1837	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1838	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1839	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1840	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1841	} n;
1842	/** The 32-bit unsigned integer view. */
1843	uint32_t u32;
1844	} MSI_MAP_CAP_HDR_T;
1845	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1846
1847	/**
1848	* Performance Optimization Control Register (MMIO).
1849	* In accordance with the AMD spec.
1850	*/
1851	typedef union
1852	{
1853	struct
1854	{
1855	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1856	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1857	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1858	} n;
1859	/** The 32-bit unsigned integer view. */
1860	uint32_t u32;
1861	} IOMMU_PERF_OPT_CTRL_T;
1862	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1863
1864	/**
1865	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1866	* In accordance with the AMD spec.
1867	*/
1868	typedef union
1869	{
1870	struct
1871	{
1872	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1873	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1874	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1875	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1876	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1877	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1878	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1879	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1880	} n;
1881	/** The 64-bit unsigned integer view. */
1882	uint64_t u64;
1883	} IOMMU_XT_GEN_INTR_CTRL_T;
1884	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1885
1886	/**
1887	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1888	* In accordance with the AMD spec.
1889	*/
1890	typedef union
1891	{
1892	struct
1893	{
1894	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1895	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1896	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1897	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1898	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1899	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1900	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1901	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1902	} n;
1903	/** The 64-bit unsigned integer view. */
1904	uint64_t u64;
1905	} IOMMU_XT_INTR_CTRL_T;
1906	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1907
1908	/**
1909	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1910	* In accordance with the AMD spec.
1911	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1912	*/
1913	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1914
1915	/**
1916	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1917	* In accordance with the AMD spec.
1918	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1919	*/
1920	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1921
1922	/**
1923	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1924	* In accordance with the AMD spec.
1925	*/
1926	typedef union
1927	{
1928	struct
1929	{
1930	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1931	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1932	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1933	} n;
1934	/** The 64-bit unsigned integer view. */
1935	uint64_t u64;
1936	} MARC_APER_BAR_T;
1937	AssertCompileSize(MARC_APER_BAR_T, 8);
1938
1939	/**
1940	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1941	* In accordance with the AMD spec.
1942	*/
1943	typedef union
1944	{
1945	struct
1946	{
1947	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1948	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1949	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1950	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1951	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1952	} n;
1953	/** The 64-bit unsigned integer view. */
1954	uint64_t u64;
1955	} MARC_APER_RELOC_T;
1956	AssertCompileSize(MARC_APER_RELOC_T, 8);
1957
1958	/**
1959	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1960	* In accordance with the AMD spec.
1961	*/
1962	typedef union
1963	{
1964	struct
1965	{
1966	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1967	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1968	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1969	} n;
1970	/** The 64-bit unsigned integer view. */
1971	uint64_t u64;
1972	} MARC_APER_LEN_T;
1973
1974	/**
1975	* Memory Access and Routing Control (MARC) Aperture Register.
1976	* This combines other registers to match the MMIO layout for convenient access.
1977	*/
1978	typedef struct
1979	{
1980	MARC_APER_BAR_T Base;
1981	MARC_APER_RELOC_T Reloc;
1982	MARC_APER_LEN_T Length;
1983	} MARC_APER_T;
1984	AssertCompileSize(MARC_APER_T, 24);
1985
1986	/**
1987	* IOMMU Reserved Register (MMIO).
1988	* In accordance with the AMD spec.
1989	* This register is reserved for hardware use (although RW?).
1990	*/
1991	typedef uint64_t IOMMU_RSVD_REG_T;
1992
1993	/**
1994	* Command Buffer Head Pointer Register (MMIO).
1995	* In accordance with the AMD spec.
1996	*/
1997	typedef union
1998	{
1999	struct
2000	{
2001	uint32_t off; /*< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). /
2002	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2003	} n;
2004	/** The 32-bit unsigned integer view. */
2005	uint32_t au32[2];
2006	/** The 64-bit unsigned integer view. */
2007	uint64_t u64;
2008	} CMD_BUF_HEAD_PTR_T;
2009	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
2010	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
2011
2012	/**
2013	* Command Buffer Tail Pointer Register (MMIO).
2014	* In accordance with the AMD spec.
2015	* Currently identical to CMD_BUF_HEAD_PTR_T.
2016	*/
2017	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
2018	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
2019
2020	/**
2021	* Event Log Head Pointer Register (MMIO).
2022	* In accordance with the AMD spec.
2023	* Currently identical to CMD_BUF_HEAD_PTR_T.
2024	*/
2025	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
2026	#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
2027
2028	/**
2029	* Event Log Tail Pointer Register (MMIO).
2030	* In accordance with the AMD spec.
2031	* Currently identical to CMD_BUF_HEAD_PTR_T.
2032	*/
2033	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
2034	#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
2035
2036
2037	/**
2038	* IOMMU Status Register (MMIO).
2039	* In accordance with the AMD spec.
2040	*/
2041	typedef union
2042	{
2043	struct
2044	{
2045	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
2046	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
2047	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
2048	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
2049	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
2050	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
2051	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
2052	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
2053	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
2054	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
2055	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
2056	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
2057	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
2058	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
2059	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
2060	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
2061	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
2062	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
2063	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
2064	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
2065	} n;
2066	/** The 32-bit unsigned integer view. */
2067	uint32_t au32[2];
2068	/** The 64-bit unsigned integer view. */
2069	uint64_t u64;
2070	} IOMMU_STATUS_T;
2071	AssertCompileSize(IOMMU_STATUS_T, 8);
2072	#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
2073	#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
2074
2075	/**
2076	* PPR Log Head Pointer Register (MMIO).
2077	* In accordance with the AMD spec.
2078	* Currently identical to CMD_BUF_HEAD_PTR_T.
2079	*/
2080	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
2081
2082	/**
2083	* PPR Log Tail Pointer Register (MMIO).
2084	* In accordance with the AMD spec.
2085	* Currently identical to CMD_BUF_HEAD_PTR_T.
2086	*/
2087	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
2088
2089	/**
2090	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
2091	* In accordance with the AMD spec.
2092	*/
2093	typedef union
2094	{
2095	struct
2096	{
2097	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
2098	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
2099	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
2100	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2101	} n;
2102	/** The 32-bit unsigned integer view. */
2103	uint32_t au32[2];
2104	/** The 64-bit unsigned integer view. */
2105	uint64_t u64;
2106	} GALOG_HEAD_PTR_T;
2107	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
2108
2109	/**
2110	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
2111	* In accordance with the AMD spec.
2112	* Currently identical to GALOG_HEAD_PTR_T.
2113	*/
2114	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
2115
2116	/**
2117	* PPR Log B Head Pointer Register (MMIO).
2118	* In accordance with the AMD spec.
2119	* Currently identical to CMD_BUF_HEAD_PTR_T.
2120	*/
2121	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
2122
2123	/**
2124	* PPR Log B Tail Pointer Register (MMIO).
2125	* In accordance with the AMD spec.
2126	* Currently identical to CMD_BUF_HEAD_PTR_T.
2127	*/
2128	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
2129
2130	/**
2131	* Event Log B Head Pointer Register (MMIO).
2132	* In accordance with the AMD spec.
2133	* Currently identical to CMD_BUF_HEAD_PTR_T.
2134	*/
2135	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
2136
2137	/**
2138	* Event Log B Tail Pointer Register (MMIO).
2139	* In accordance with the AMD spec.
2140	* Currently identical to CMD_BUF_HEAD_PTR_T.
2141	*/
2142	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
2143
2144	/**
2145	* PPR Log Auto Response Register (MMIO).
2146	* In accordance with the AMD spec.
2147	*/
2148	typedef union
2149	{
2150	struct
2151	{
2152	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
2153	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
2154	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
2155	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
2156	} n;
2157	/** The 32-bit unsigned integer view. */
2158	uint32_t au32[2];
2159	/** The 64-bit unsigned integer view. */
2160	uint64_t u64;
2161	} PPR_LOG_AUTO_RESP_T;
2162	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
2163
2164	/**
2165	* PPR Log Overflow Early Indicator Register (MMIO).
2166	* In accordance with the AMD spec.
2167	*/
2168	typedef union
2169	{
2170	struct
2171	{
2172	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
2173	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
2174	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
2175	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
2176	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2177	} n;
2178	/** The 32-bit unsigned integer view. */
2179	uint32_t au32[2];
2180	/** The 64-bit unsigned integer view. */
2181	uint64_t u64;
2182	} PPR_LOG_OVERFLOW_EARLY_T;
2183	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2184
2185	/**
2186	* PPR Log B Overflow Early Indicator Register (MMIO).
2187	* In accordance with the AMD spec.
2188	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2189	*/
2190	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2191
2192	/**
2193	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2194	* In accordance with the AMD spec.
2195	*/
2196	typedef enum EVT_ILLEGAL_DTE_TYPE_T
2197	{
2198	kIllegalDteType_RsvdNotZero = 0,
2199	kIllegalDteType_RsvdIntTabLen,
2200	kIllegalDteType_RsvdIoCtl,
2201	kIllegalDteType_RsvdIntCtl
2202	} EVT_ILLEGAL_DTE_TYPE_T;
2203
2204	/**
2205	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2206	* In accordance with the AMD spec.
2207	*/
2208	typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2209	{
2210	/* Memory transaction. */
2211	kIoPageFaultType_DteRsvdPagingMode = 0,
2212	kIoPageFaultType_PteInvalidPageSize,
2213	kIoPageFaultType_PteInvalidLvlEncoding,
2214	kIoPageFaultType_SkippedLevelIovaNotZero,
2215	kIoPageFaultType_PteRsvdNotZero,
2216	kIoPageFaultType_PteValidNotSet,
2217	kIoPageFaultType_DteTranslationDisabled,
2218	kIoPageFaultType_PasidInvalidRange,
2219	kIoPageFaultType_PermDenied,
2220	kIoPageFaultType_UserSupervisor,
2221	/* Interrupt remapping */
2222	kIoPageFaultType_IrteAddrInvalid,
2223	kIoPageFaultType_IrteRsvdNotZero,
2224	kIoPageFaultType_IrteRemapEn,
2225	kIoPageFaultType_IrteRsvdIntType,
2226	kIoPageFaultType_IntrReqAborted,
2227	kIoPageFaultType_IntrWithPasid,
2228	kIoPageFaultType_SmiFilterMismatch,
2229	/* Memory transaction or interrupt remapping. */
2230	kIoPageFaultType_DevId_Invalid
2231	} EVT_IO_PAGE_FAULT_TYPE_T;
2232
2233	/**
2234	* IOTLB_INV_TIMEOUT Event Types.
2235	* In accordance with the AMD spec.
2236	*/
2237	typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2238	{
2239	InvTimeoutType_NoResponse = 0
2240	} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2241
2242	/**
2243	* INVALID_DEVICE_REQUEST Event Types.
2244	* In accordance with the AMD spec.
2245	*/
2246	typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2247	{
2248	/* Access. */
2249	kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2250	kInvalidDevReqType_PretranslatedTransaction,
2251	kInvalidDevReqType_PortIo,
2252	kInvalidDevReqType_SysMgt,
2253	kInvalidDevReqType_IntrRange,
2254	kInvalidDevReqType_RsvdIntrRange,
2255	kInvalidDevReqType_SysMgtAddr,
2256	/* Translation Request. */
2257	kInvalidDevReqType_TrAccessInvalid,
2258	kInvalidDevReqType_TrDisabled,
2259	kInvalidDevReqType_DevIdInvalid,
2260	} EVT_INVALID_DEV_REQ_TYPE_T;
2261
2262	/**
2263	* INVALID_PPR_REQUEST Event Types.
2264	* In accordance with the AMD spec.
2265	*/
2266	typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2267	{
2268	kInvalidPprReqType_PriNotSupported,
2269	kInvalidPprReqType_GstTranslateDisabled
2270	} EVT_INVALID_PPR_REQ_TYPE_T;
2271
2272	/**
2273	* IOMMU operations (transaction) types.
2274	*/
2275	typedef enum IOMMUOP
2276	{
2277	/** Address translation request. */
2278	IOMMUOP_TRANSLATE_REQ = 0,
2279	/** Memory read request. */
2280	IOMMUOP_MEM_READ,
2281	/** Memory write request. */
2282	IOMMUOP_MEM_WRITE,
2283	/** Interrupt request. */
2284	IOMMUOP_INTR_REQ,
2285	/** Command. */
2286	IOMMUOP_CMD
2287	} IOMMUOP;
2288	AssertCompileSize(IOMMUOP, 4);
2289
2290	/**
2291	* I/O page walk result.
2292	*/
2293	typedef struct
2294	{
2295	/** The translated system physical address. */
2296	RTGCPHYS GCPhysSpa;
2297	/** The number of offset bits in the system physical address. */
2298	uint8_t cShift;
2299	/** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
2300	uint8_t fIoPerm;
2301	/** Padding. */
2302	uint8_t abPadding[2];
2303	} IOWALKRESULT;
2304	/** Pointer to an I/O walk result struct. */
2305	typedef IOWALKRESULT *PIOWALKRESULT;
2306	/** Pointer to a const I/O walk result struct. */
2307	typedef IOWALKRESULT *PCIOWALKRESULT;
2308
2309	/**
2310	* IOMMU I/O TLB Entry.
2311	* Keep this as small and aligned as possible.
2312	*/
2313	typedef struct
2314	{
2315	/** The translated system physical address (SPA) of the page. */
2316	RTGCPHYS GCPhysSpa;
2317	/** The index of the 4K page within a large page. */
2318	uint32_t idxSubPage;
2319	/** The I/O access permissions (IOMMU_IO_PERM_XXX). */
2320	uint8_t fIoPerm;
2321	/** The number of offset bits in the translation indicating page size. */
2322	uint8_t cShift;
2323	/** Alignment padding. */
2324	uint8_t afPadding[2];
2325	} IOTLBE_T;
2326	AssertCompileSize(IOTLBE_T, 16);
2327	/** Pointer to an IOMMU I/O TLB entry struct. */
2328	typedef IOTLBE_T *PIOTLBE_T;
2329	/** Pointer to a const IOMMU I/O TLB entry struct. */
2330	typedef IOTLBE_T const *PCIOTLBE_T;
2331
2332	/**
2333	* MSI Message (Address and Data Register Pair).
2334	*/
2335	typedef struct
2336	{
2337	/** The MSI Address Register. */
2338	MSI_ADDR_T MsiAddr;
2339	/** The MSI Data Register. */
2340	MSI_DATA_T MsiData;
2341	} MSI_MSG_T;
2342	/** Pointer to an MSI message struct. */
2343	typedef MSI_MSG_T *PMSI_MSG_T;
2344	/** Pointer to a const MSI message struct. */
2345	typedef MSI_MSG_T const *PCMSI_MSG_T;
2346
2347	/**
2348	* The shared IOMMU device state.
2349	*/
2350	typedef struct IOMMU
2351	{
2352	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
2353	uint32_t idxIommu;
2354	/** Alignment padding. */
2355	uint32_t uPadding0;
2356
2357	/** Whether the command thread is sleeping. */
2358	bool volatile fCmdThreadSleeping;
2359	/** Alignment padding. */
2360	uint8_t afPadding0[3];
2361	/** Whether the command thread has been signaled for wake up. */
2362	bool volatile fCmdThreadSignaled;
2363	/** Alignment padding. */
2364	uint8_t afPadding1[3];
2365
2366	/** The event semaphore the command thread waits on. */
2367	SUPSEMEVENT hEvtCmdThread;
2368	/** The MMIO handle. */
2369	IOMMMIOHANDLE hMmio;
2370
2371	/** @name PCI: Base capability block registers.
2372	* @{ */
2373	IOMMU_BAR_T IommuBar; /*< IOMMU base address register. /
2374	/** @} */
2375
2376	/** @name MMIO: Control and status registers.
2377	* @{ */
2378	DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /*< Device table base address registers. /
2379	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
2380	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
2381	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
2382	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
2383	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
2384	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
2385	/** @} */
2386
2387	/** @name MMIO: PPR Log registers.
2388	* @{ */
2389	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
2390	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
2391	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
2392	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
2393	/** @} */
2394
2395	/** @todo IOMMU: SMI filter. */
2396
2397	/** @name MMIO: Guest Virtual-APIC Log registers.
2398	* @{ */
2399	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
2400	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
2401	/** @} */
2402
2403	/** @name MMIO: Alternate PPR and Event Log registers.
2404	* @{ */
2405	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
2406	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
2407	/** @} */
2408
2409	/** @name MMIO: Device-specific feature registers.
2410	* @{ */
2411	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
2412	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
2413	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
2414	/** @} */
2415
2416	/** @name MMIO: MSI Capability Block registers.
2417	* @{ */
2418	MSI_MISC_INFO_T MsiMiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
2419	/** @} */
2420
2421	/** @name MMIO: Performance Optimization Control registers.
2422	* @{ */
2423	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
2424	/** @} */
2425
2426	/** @name MMIO: x2APIC Control registers.
2427	* @{ */
2428	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
2429	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
2430	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
2431	/** @} */
2432
2433	/** @name MMIO: MARC registers.
2434	* @{ */
2435	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
2436	/** @} */
2437
2438	/** @name MMIO: Reserved register.
2439	* @{ */
2440	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
2441	/** @} */
2442
2443	/** @name MMIO: Command and Event Log pointer registers.
2444	* @{ */
2445	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
2446	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
2447	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
2448	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
2449	/** @} */
2450
2451	/** @name MMIO: Command and Event Status register.
2452	* @{ */
2453	IOMMU_STATUS_T Status; /*< IOMMU status register. /
2454	/** @} */
2455
2456	/** @name MMIO: PPR Log Head and Tail pointer registers.
2457	* @{ */
2458	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
2459	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
2460	/** @} */
2461
2462	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
2463	* @{ */
2464	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
2465	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
2466	/** @} */
2467
2468	/** @name MMIO: PPR Log B Head and Tail pointer registers.
2469	* @{ */
2470	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
2471	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
2472	/** @} */
2473
2474	/** @name MMIO: Event Log B Head and Tail pointer registers.
2475	* @{ */
2476	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
2477	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
2478	/** @} */
2479
2480	/** @name MMIO: PPR Log Overflow protection registers.
2481	* @{ */
2482	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
2483	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
2484	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
2485	/** @} */
2486
2487	/** @todo IOMMU: IOMMU Event counter registers. */
2488
2489	/** @todo IOMMU: Stat counters. */
2490	} IOMMU;
2491	/** Pointer to the IOMMU device state. */
2492	typedef struct IOMMU *PIOMMU;
2493	/** Pointer to the const IOMMU device state. */
2494	typedef const struct IOMMU *PCIOMMU;
2495	AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
2496	AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
2497	AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
2498	AssertCompileMemberAlignment(IOMMU, hMmio, 8);
2499	AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
2500
2501	/**
2502	* The ring-3 IOMMU device state.
2503	*/
2504	typedef struct IOMMUR3
2505	{
2506	/** Device instance. */
2507	PPDMDEVINSR3 pDevInsR3;
2508	/** The IOMMU helpers. */
2509	PCPDMIOMMUHLPR3 pIommuHlpR3;
2510	/** The command thread handle. */
2511	R3PTRTYPE(PPDMTHREAD) pCmdThread;
2512	} IOMMUR3;
2513	/** Pointer to the ring-3 IOMMU device state. */
2514	typedef IOMMUR3 *PIOMMUR3;
2515
2516	/**
2517	* The ring-0 IOMMU device state.
2518	*/
2519	typedef struct IOMMUR0
2520	{
2521	/** Device instance. */
2522	PPDMDEVINSR0 pDevInsR0;
2523	/** The IOMMU helpers. */
2524	PCPDMIOMMUHLPR0 pIommuHlpR0;
2525	} IOMMUR0;
2526	/** Pointer to the ring-0 IOMMU device state. */
2527	typedef IOMMUR0 *PIOMMUR0;
2528
2529	/**
2530	* The raw-mode IOMMU device state.
2531	*/
2532	typedef struct IOMMURC
2533	{
2534	/** Device instance. */
2535	PPDMDEVINSR0 pDevInsRC;
2536	/** The IOMMU helpers. */
2537	PCPDMIOMMUHLPRC pIommuHlpRC;
2538	} IOMMURC;
2539	/** Pointer to the raw-mode IOMMU device state. */
2540	typedef IOMMURC *PIOMMURC;
2541
2542	/** The IOMMU device state for the current context. */
2543	typedef CTX_SUFF(IOMMU) IOMMUCC;
2544	/** Pointer to the IOMMU device state for the current context. */
2545	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
2546
2547	/**
2548	* IOMMU register access routines.
2549	*/
2550	typedef struct
2551	{
2552	const char *pszName;
2553	VBOXSTRICTRC (pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t pu64Value);
2554	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
2555	bool f64BitReg;
2556	} IOMMUREGACC;
2557
2558
2559	/*********************************************************************************************************************************
2560	* Global Variables *
2561	*********************************************************************************************************************************/
2562	/**
2563	* An array of the number of device table segments supported.
2564	* Indexed by u2DevTabSegSup.
2565	*/
2566	static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
2567
2568	/**
2569	* An array of the masks to select the device table segment index from a device ID.
2570	*/
2571	static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
2572
2573	/**
2574	* The maximum size (inclusive) of each device table segment (0 to 7).
2575	* Indexed by the device table segment index.
2576	*/
2577	static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
2578
2579
2580	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
2581	/**
2582	* Gets the maximum number of buffer entries for the given buffer length.
2583	*
2584	* @returns Number of buffer entries.
2585	* @param uEncodedLen The length (power-of-2 encoded).
2586	*/
2587	DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
2588	{
2589	Assert(uEncodedLen > 7);
2590	return 2 << (uEncodedLen - 1);
2591	}
2592
2593
2594	/**
2595	* Gets the total length of the buffer given a base register's encoded length.
2596	*
2597	* @returns The length of the buffer in bytes.
2598	* @param uEncodedLen The length (power-of-2 encoded).
2599	*/
2600	DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
2601	{
2602	Assert(uEncodedLen > 7);
2603	return (2 << (uEncodedLen - 1)) << 4;
2604	}
2605
2606
2607	/**
2608	* Gets the number of (unconsumed) entries in the event log.
2609	*
2610	* @returns The number of entries in the event log.
2611	* @param pThis The IOMMU device state.
2612	*/
2613	static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
2614	{
2615	uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2616	uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2617	if (idxTail >= idxHead)
2618	return idxTail - idxHead;
2619
2620	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2621	return cMaxEvts - idxHead + idxTail;
2622	}
2623
2624
2625	/**
2626	* Gets the number of (unconsumed) commands in the command buffer.
2627	*
2628	* @returns The number of commands in the command buffer.
2629	* @param pThis The IOMMU device state.
2630	*/
2631	static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
2632	{
2633	uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2634	uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2635	if (idxTail >= idxHead)
2636	return idxTail - idxHead;
2637
2638	uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
2639	return cMaxCmds - idxHead + idxTail;
2640	}
2641
2642
2643	DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
2644	{
2645	IOMMU_STATUS_T Status;
2646	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
2647	return Status;
2648	}
2649
2650
2651	DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
2652	{
2653	IOMMU_CTRL_T Ctrl;
2654	Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
2655	return Ctrl;
2656	}
2657
2658
2659	/**
2660	* Returns whether MSI is enabled for the IOMMU.
2661	*
2662	* @returns Whether MSI is enabled.
2663	* @param pDevIns The IOMMU device instance.
2664	*
2665	* @note There should be a PCIDevXxx function for this.
2666	*/
2667	static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
2668	{
2669	MSI_CAP_HDR_T MsiCapHdr;
2670	MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
2671	return MsiCapHdr.n.u1MsiEnable;
2672	}
2673
2674
2675	/**
2676	* Signals a PCI target abort.
2677	*
2678	* @param pDevIns The IOMMU device instance.
2679	*/
2680	static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
2681	{
2682	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2683	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2684	PDMPciDevSetStatus(pPciDev, u16Status);
2685	}
2686
2687
2688	/**
2689	* Wakes up the command thread if there are commands to be processed or if
2690	* processing is requested to be stopped by software.
2691	*
2692	* @param pDevIns The IOMMU device instance.
2693	*/
2694	static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
2695	{
2696	IOMMU_ASSERT_LOCKED(pDevIns);
2697
2698	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2699	if ( !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true)
2700	&& ASMAtomicReadBool(&pThis->fCmdThreadSleeping))
2701	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2702	}
2703
2704
2705	/**
2706	* Writes to a read-only register.
2707	*/
2708	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2709	{
2710	RT_NOREF(pDevIns, pThis, iReg, u64Value);
2711	Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
2712	return VINF_SUCCESS;
2713	}
2714
2715
2716	/**
2717	* Writes the Device Table Base Address Register.
2718	*/
2719	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2720	{
2721	RT_NOREF(pDevIns, iReg);
2722
2723	/* Mask out all unrecognized bits. */
2724	u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2725
2726	/* Update the register. */
2727	pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2728	return VINF_SUCCESS;
2729	}
2730
2731
2732	/**
2733	* Writes the Command Buffer Base Address Register.
2734	*/
2735	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2736	{
2737	RT_NOREF(pDevIns, iReg);
2738
2739	/*
2740	* While this is not explicitly specified like the event log base address register,
2741	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2742	* Inconsistent specs :/
2743	*/
2744	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2745	if (Status.n.u1CmdBufRunning)
2746	{
2747	Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2748	return VINF_SUCCESS;
2749	}
2750
2751	/* Mask out all unrecognized bits. */
2752	CMD_BUF_BAR_T CmdBufBaseAddr;
2753	CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2754
2755	/* Validate the length. */
2756	if (CmdBufBaseAddr.n.u4Len >= 8)
2757	{
2758	/* Update the register. */
2759	pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2760
2761	/*
2762	* Writing the command buffer base address, clears the command buffer head and tail pointers.
2763	* See AMD spec. 2.4 "Commands".
2764	*/
2765	pThis->CmdBufHeadPtr.u64 = 0;
2766	pThis->CmdBufTailPtr.u64 = 0;
2767	}
2768	else
2769	Log((IOMMU_LOG_PFX ": Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2770
2771	return VINF_SUCCESS;
2772	}
2773
2774
2775	/**
2776	* Writes the Event Log Base Address Register.
2777	*/
2778	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2779	{
2780	RT_NOREF(pDevIns, iReg);
2781
2782	/*
2783	* IOMMU behavior is undefined when software writes this register when event logging is running.
2784	* In our emulation, we ignore the write entirely.
2785	* See AMD IOMMU spec. "Event Log Base Address Register".
2786	*/
2787	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2788	if (Status.n.u1EvtLogRunning)
2789	{
2790	Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2791	return VINF_SUCCESS;
2792	}
2793
2794	/* Mask out all unrecognized bits. */
2795	u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2796	EVT_LOG_BAR_T EvtLogBaseAddr;
2797	EvtLogBaseAddr.u64 = u64Value;
2798
2799	/* Validate the length. */
2800	if (EvtLogBaseAddr.n.u4Len >= 8)
2801	{
2802	/* Update the register. */
2803	pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2804
2805	/*
2806	* Writing the event log base address, clears the event log head and tail pointers.
2807	* See AMD spec. 2.5 "Event Logging".
2808	*/
2809	pThis->EvtLogHeadPtr.u64 = 0;
2810	pThis->EvtLogTailPtr.u64 = 0;
2811	}
2812	else
2813	Log((IOMMU_LOG_PFX ": Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2814
2815	return VINF_SUCCESS;
2816	}
2817
2818
2819	/**
2820	* Writes the Control Register.
2821	*/
2822	static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2823	{
2824	RT_NOREF(pDevIns, iReg);
2825
2826	/* Mask out all unrecognized bits. */
2827	u64Value &= IOMMU_CTRL_VALID_MASK;
2828
2829	IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
2830	IOMMU_CTRL_T NewCtrl;
2831	NewCtrl.u64 = u64Value;
2832
2833	/* Update the register. */
2834	ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2835
2836	/* Enable or disable event logging when the bit transitions. */
2837	bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2838	bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2839	bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2840	if (fOldEvtLogEn != fNewEvtLogEn)
2841	{
2842	if ( fNewIommuEn
2843	&& fNewEvtLogEn)
2844	{
2845	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2846	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2847	}
2848	else
2849	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2850	}
2851
2852	/* Enable or disable command buffer processing when the bit transitions. */
2853	bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2854	bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2855	if (fOldCmdBufEn != fNewCmdBufEn)
2856	{
2857	if ( fNewIommuEn
2858	&& fNewCmdBufEn)
2859	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2860	else
2861	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2862
2863	/* Wake up the command thread to start or stop processing commands. */
2864	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2865	}
2866	}
2867
2868
2869	/**
2870	* Writes to the Excluse Range Base Address Register.
2871	*/
2872	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2873	{
2874	RT_NOREF(pDevIns, iReg);
2875	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2876	return VINF_SUCCESS;
2877	}
2878
2879
2880	/**
2881	* Writes to the Excluse Range Limit Register.
2882	*/
2883	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2884	{
2885	RT_NOREF(pDevIns, iReg);
2886	u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2887	u64Value \|= UINT64_C(0xfff);
2888	pThis->ExclRangeLimit.u64 = u64Value;
2889	return VINF_SUCCESS;
2890	}
2891
2892
2893	/**
2894	* Writes the Hardware Event Register (Hi).
2895	*/
2896	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2897	{
2898	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2899	RT_NOREF(pDevIns, iReg);
2900	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2901	pThis->HwEvtHi.u64 = u64Value;
2902	return VINF_SUCCESS;
2903	}
2904
2905
2906	/**
2907	* Writes the Hardware Event Register (Lo).
2908	*/
2909	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2910	{
2911	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2912	RT_NOREF(pDevIns, iReg);
2913	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2914	pThis->HwEvtLo = u64Value;
2915	return VINF_SUCCESS;
2916	}
2917
2918
2919	/**
2920	* Writes the Hardware Event Status Register.
2921	*/
2922	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2923	{
2924	RT_NOREF(pDevIns, iReg);
2925
2926	/* Mask out all unrecognized bits. */
2927	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2928
2929	/*
2930	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2931	* If the current status bits or the bits being written are both 0, we've nothing to do.
2932	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2933	*/
2934	uint64_t HwStatus = pThis->HwEvtStatus.u64;
2935	if (!(HwStatus & RT_BIT(0)))
2936	return VINF_SUCCESS;
2937	if (u64Value & HwStatus & RT_BIT_64(0))
2938	HwStatus &= ~RT_BIT_64(0);
2939	if (u64Value & HwStatus & RT_BIT_64(1))
2940	HwStatus &= ~RT_BIT_64(1);
2941
2942	/* Update the register. */
2943	pThis->HwEvtStatus.u64 = HwStatus;
2944	return VINF_SUCCESS;
2945	}
2946
2947
2948	/**
2949	* Writes the Device Table Segment Base Address Register.
2950	*/
2951	static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2952	{
2953	RT_NOREF(pDevIns);
2954
2955	/* Figure out which segment is being written. */
2956	uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2957	uint8_t const idxSegment = offSegment + 1;
2958	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2959
2960	/* Mask out all unrecognized bits. */
2961	u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2962	DEV_TAB_BAR_T DevTabSegBar;
2963	DevTabSegBar.u64 = u64Value;
2964
2965	/* Validate the size. */
2966	uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2967	uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2968	if (uSegSize <= uMaxSegSize)
2969	{
2970	/* Update the register. */
2971	pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2972	}
2973	else
2974	Log((IOMMU_LOG_PFX ": Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2975
2976	return VINF_SUCCESS;
2977	}
2978
2979
2980	/**
2981	* Writes the MSI Capability Header Register.
2982	*/
2983	static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2984	{
2985	RT_NOREF(pThis, iReg);
2986	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2987	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2988	MSI_CAP_HDR_T MsiCapHdr;
2989	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2990	MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2991	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2992	return VINF_SUCCESS;
2993	}
2994
2995
2996	/**
2997	* Writes the MSI Address (Lo) Register (32-bit).
2998	*/
2999	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3000	{
3001	RT_NOREF(pThis, iReg);
3002	Assert(!RT_HI_U32(u64Value));
3003	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3004	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3005	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & IOMMU_MSI_ADDR_VALID_MASK);
3006	return VINF_SUCCESS;
3007	}
3008
3009
3010	/**
3011	* Writes the MSI Address (Hi) Register (32-bit).
3012	*/
3013	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3014	{
3015	RT_NOREF(pThis, iReg);
3016	Assert(!RT_HI_U32(u64Value));
3017	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3018	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3019	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
3020	return VINF_SUCCESS;
3021	}
3022
3023
3024	/**
3025	* Writes the MSI Data Register (32-bit).
3026	*/
3027	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3028	{
3029	RT_NOREF(pThis, iReg);
3030	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3031	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3032	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & IOMMU_MSI_DATA_VALID_MASK);
3033	return VINF_SUCCESS;
3034	}
3035
3036
3037	/**
3038	* Writes the Command Buffer Head Pointer Register (32-bit).
3039	*/
3040	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3041	{
3042	RT_NOREF(pDevIns, iReg);
3043
3044	/*
3045	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
3046	* In our emulation, we ignore the write entirely.
3047	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3048	*/
3049	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3050	if (Status.n.u1CmdBufRunning)
3051	{
3052	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
3053	return VINF_SUCCESS;
3054	}
3055
3056	/*
3057	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3058	* In our emulation, we ignore the write entirely.
3059	*/
3060	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
3061	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3062	Assert(cbBuf <= _512K);
3063	if (offBuf >= cbBuf)
3064	{
3065	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
3066	offBuf, cbBuf));
3067	return VINF_SUCCESS;
3068	}
3069
3070	/* Update the register. */
3071	pThis->CmdBufHeadPtr.au32[0] = offBuf;
3072
3073	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
3074
3075	LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
3076	return VINF_SUCCESS;
3077	}
3078
3079
3080	/**
3081	* Writes the Command Buffer Tail Pointer Register (32-bit).
3082	*/
3083	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3084	{
3085	RT_NOREF(pDevIns, iReg);
3086
3087	/*
3088	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3089	* In our emulation, we ignore the write entirely.
3090	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3091	*/
3092	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
3093	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3094	Assert(cbBuf <= _512K);
3095	if (offBuf >= cbBuf)
3096	{
3097	Log((IOMMU_LOG_PFX ": Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3098	offBuf, cbBuf));
3099	return VINF_SUCCESS;
3100	}
3101
3102	/*
3103	* IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
3104	* head pointer after adding one or more commands to the buffer.
3105	*
3106	* However, we cannot enforce this strictly because it's legal for software to shrink the
3107	* command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
3108	* at 0). Software might even make the queue empty by making head and tail equal which is
3109	* allowed. I don't think we can or should try too hard to prevent software shooting itself
3110	* in the foot here. As long as we make sure the offset value is within the circular buffer
3111	* bounds (which we do by masking bits above) it should be sufficient.
3112	*/
3113	pThis->CmdBufTailPtr.au32[0] = offBuf;
3114
3115	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
3116
3117	LogFlow((IOMMU_LOG_PFX ": Set CmdBufTailPtr to %#RX32\n", offBuf));
3118	return VINF_SUCCESS;
3119	}
3120
3121
3122	/**
3123	* Writes the Event Log Head Pointer Register (32-bit).
3124	*/
3125	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3126	{
3127	RT_NOREF(pDevIns, iReg);
3128
3129	/*
3130	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3131	* In our emulation, we ignore the write entirely.
3132	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3133	*/
3134	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
3135	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3136	Assert(cbBuf <= _512K);
3137	if (offBuf >= cbBuf)
3138	{
3139	Log((IOMMU_LOG_PFX ": Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3140	offBuf, cbBuf));
3141	return VINF_SUCCESS;
3142	}
3143
3144	/* Update the register. */
3145	pThis->EvtLogHeadPtr.au32[0] = offBuf;
3146
3147	LogFlow((IOMMU_LOG_PFX ": Set EvtLogHeadPtr to %#RX32\n", offBuf));
3148	return VINF_SUCCESS;
3149	}
3150
3151
3152	/**
3153	* Writes the Event Log Tail Pointer Register (32-bit).
3154	*/
3155	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3156	{
3157	RT_NOREF(pDevIns, iReg);
3158	NOREF(pThis);
3159
3160	/*
3161	* IOMMU behavior is undefined when software writes this register when the event log is running.
3162	* In our emulation, we ignore the write entirely.
3163	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3164	*/
3165	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3166	if (Status.n.u1EvtLogRunning)
3167	{
3168	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
3169	return VINF_SUCCESS;
3170	}
3171
3172	/*
3173	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3174	* In our emulation, we ignore the write entirely.
3175	*/
3176	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
3177	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3178	Assert(cbBuf <= _512K);
3179	if (offBuf >= cbBuf)
3180	{
3181	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3182	offBuf, cbBuf));
3183	return VINF_SUCCESS;
3184	}
3185
3186	/* Update the register. */
3187	pThis->EvtLogTailPtr.au32[0] = offBuf;
3188
3189	LogFlow((IOMMU_LOG_PFX ": Set EvtLogTailPtr to %#RX32\n", offBuf));
3190	return VINF_SUCCESS;
3191	}
3192
3193
3194	/**
3195	* Writes the Status Register (64-bit).
3196	*/
3197	static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3198	{
3199	RT_NOREF(pDevIns, iReg);
3200
3201	/* Mask out all unrecognized bits. */
3202	u64Value &= IOMMU_STATUS_VALID_MASK;
3203
3204	/*
3205	* Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
3206	* Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
3207	*/
3208	IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
3209	uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
3210	uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
3211	uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
3212
3213	uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) \| fOldRoBits;
3214
3215	/* Update the register. */
3216	ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
3217	return VINF_SUCCESS;
3218	}
3219
3220
3221	#if 0
3222	/**
3223	* Table 0: Registers-access table.
3224	*/
3225	static const IOMMUREGACC g_aTable0Regs[] =
3226	{
3227
3228	};
3229
3230	/**
3231	* Table 1: Registers-access table.
3232	*/
3233	static const IOMMUREGACC g_aTable1Regs[] =
3234	{
3235	};
3236	#endif
3237
3238
3239	/**
3240	* Writes an IOMMU register (32-bit and 64-bit).
3241	*
3242	* @returns Strict VBox status code.
3243	* @param pDevIns The IOMMU device instance.
3244	* @param off MMIO byte offset to the register.
3245	* @param cb The size of the write access.
3246	* @param uValue The value being written.
3247	*
3248	* @thread EMT.
3249	*/
3250	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
3251	{
3252	Assert(off < IOMMU_MMIO_REGION_SIZE);
3253	Assert(cb == 4 \|\| cb == 8);
3254	Assert(!(off & (cb - 1)));
3255
3256	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3257	switch (off)
3258	{
3259	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
3260	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
3261	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
3262	case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
3263	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
3264	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
3265	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3266
3267	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3268	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
3269	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
3270	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
3271
3272	case IOMMU_MMIO_OFF_GALOG_BAR:
3273	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3274
3275	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
3276	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3277
3278	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3279	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3280	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3281	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3282	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3283	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3284	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
3285
3286	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
3287	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
3288	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3289
3290	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
3291	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3292	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3293	{
3294	VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
3295	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3296	return rcStrict;
3297	uValue >>= 32;
3298	RT_FALL_THRU();
3299	}
3300	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
3301	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3302	{
3303	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
3304	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3305	return rcStrict;
3306	uValue >>= 32;
3307	RT_FALL_THRU();
3308	}
3309	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
3310	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3311
3312	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3313
3314	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
3315	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
3316	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3317
3318	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
3319	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
3320	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
3321	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
3322	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
3323	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
3324	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
3325	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
3326	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
3327	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
3328	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
3329	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3330
3331	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3332
3333	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
3334	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
3335	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
3336	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
3337
3338	case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
3339
3340	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
3341	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
3342
3343	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
3344	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
3345
3346	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
3347	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
3348
3349	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
3350	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3351
3352	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
3353	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
3354	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
3355
3356	/* Not implemented. */
3357	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3358	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3359	{
3360	Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
3361	(off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3362	return VINF_SUCCESS;
3363	}
3364
3365	/* Unknown. */
3366	default:
3367	{
3368	Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
3369	return VINF_SUCCESS;
3370	}
3371	}
3372	}
3373
3374
3375	/**
3376	* Reads an IOMMU register (64-bit) given its MMIO offset.
3377	*
3378	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
3379	* boundary include the lower half of the subsequent register.
3380	*
3381	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
3382	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
3383	* software will only perform 32-bit reads on those 32-bit registers that are
3384	* aligned on 8-byte boundaries.
3385	*
3386	* @returns Strict VBox status code.
3387	* @param pDevIns The IOMMU device instance.
3388	* @param off The MMIO offset of the register in bytes.
3389	* @param puResult Where to store the value being read.
3390	*
3391	* @thread EMT.
3392	*/
3393	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
3394	{
3395	Assert(off < IOMMU_MMIO_REGION_SIZE);
3396	Assert(!(off & 7) \|\| !(off & 3));
3397
3398	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3399	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3400	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3401
3402	/** @todo IOMMU: fine-grained locking? */
3403	uint64_t uReg;
3404	switch (off)
3405	{
3406	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
3407	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
3408	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
3409	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
3410	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
3411	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
3412	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
3413
3414	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
3415	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
3416	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
3417	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
3418
3419	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
3420	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
3421
3422	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
3423	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
3424
3425	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3426	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3427	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3428	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3429	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3430	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3431	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
3432	{
3433	uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
3434	uint8_t const idxDevTabSeg = offDevTabSeg + 1;
3435	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3436	uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
3437	break;
3438	}
3439
3440	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
3441	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
3442	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
3443
3444	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MsiMiscInfo.u64; break;
3445	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MsiMiscInfo.au32[1]; break;
3446	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3447	{
3448	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3449	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3450	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
3451	break;
3452	}
3453	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
3454	{
3455	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3456	break;
3457	}
3458	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3459	{
3460	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3461	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3462	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
3463	break;
3464	}
3465	case IOMMU_MMIO_OFF_MSI_DATA:
3466	{
3467	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3468	break;
3469	}
3470	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
3471	{
3472	/*
3473	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
3474	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
3475	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
3476	* 0 for this register.
3477	*/
3478	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
3479	break;
3480	}
3481
3482	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
3483
3484	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
3485	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
3486	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
3487
3488	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
3489	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
3490	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
3491	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
3492	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
3493	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
3494	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
3495	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
3496	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
3497	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
3498	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
3499	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
3500
3501	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
3502
3503	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
3504	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
3505	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
3506	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
3507
3508	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
3509
3510	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
3511	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
3512
3513	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
3514	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
3515
3516	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
3517	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
3518
3519	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
3520	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
3521
3522	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
3523	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
3524	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
3525
3526	/* Not implemented. */
3527	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3528	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3529	{
3530	Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3531	uReg = 0;
3532	break;
3533	}
3534
3535	/* Unknown. */
3536	default:
3537	{
3538	Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
3539	uReg = 0;
3540	return VINF_IOM_MMIO_UNUSED_00;
3541	}
3542	}
3543
3544	*puResult = uReg;
3545	return VINF_SUCCESS;
3546	}
3547
3548
3549	/**
3550	* Raises the MSI interrupt for the IOMMU device.
3551	*
3552	* @param pDevIns The IOMMU device instance.
3553	*
3554	* @thread Any.
3555	*/
3556	static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
3557	{
3558	if (iommuAmdIsMsiEnabled(pDevIns))
3559	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
3560	}
3561
3562
3563	/**
3564	* Clears the MSI interrupt for the IOMMU device.
3565	*
3566	* @param pDevIns The IOMMU device instance.
3567	*
3568	* @thread Any.
3569	*/
3570	static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
3571	{
3572	if (iommuAmdIsMsiEnabled(pDevIns))
3573	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3574	}
3575
3576
3577	/**
3578	* Writes an entry to the event log in memory.
3579	*
3580	* @returns VBox status code.
3581	* @param pDevIns The IOMMU device instance.
3582	* @param pEvent The event to log.
3583	*
3584	* @thread Any.
3585	*/
3586	static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3587	{
3588	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3589
3590	IOMMU_ASSERT_LOCKED(pDevIns);
3591
3592	/* Check if event logging is active and the log has not overflowed. */
3593	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3594	if ( Status.n.u1EvtLogRunning
3595	&& !Status.n.u1EvtOverflow)
3596	{
3597	uint32_t const cbEvt = sizeof(*pEvent);
3598
3599	/* Get the offset we need to write the event to in memory (circular buffer offset). */
3600	uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3601	Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3602
3603	/* Ensure we have space in the event log. */
3604	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3605	uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3606	if (cEvts + 1 < cMaxEvts)
3607	{
3608	/* Write the event log entry to memory. */
3609	RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3610	RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3611	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3612	if (RT_FAILURE(rc))
3613	Log((IOMMU_LOG_PFX ": Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3614
3615	/* Increment the event log tail pointer. */
3616	uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3617	pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3618
3619	/* Indicate that an event log entry was written. */
3620	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3621
3622	/* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3623	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3624	if (Ctrl.n.u1EvtIntrEn)
3625	iommuAmdRaiseMsiInterrupt(pDevIns);
3626	}
3627	else
3628	{
3629	/* Indicate that the event log has overflowed. */
3630	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3631
3632	/* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3633	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3634	if (Ctrl.n.u1EvtIntrEn)
3635	iommuAmdRaiseMsiInterrupt(pDevIns);
3636	}
3637	}
3638	}
3639
3640
3641	/**
3642	* Sets an event in the hardware error registers.
3643	*
3644	* @param pDevIns The IOMMU device instance.
3645	* @param pEvent The event.
3646	*
3647	* @thread Any.
3648	*/
3649	static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3650	{
3651	IOMMU_ASSERT_LOCKED(pDevIns);
3652
3653	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3654	if (pThis->ExtFeat.n.u1HwErrorSup)
3655	{
3656	if (pThis->HwEvtStatus.n.u1Valid)
3657	pThis->HwEvtStatus.n.u1Overflow = 1;
3658	pThis->HwEvtStatus.n.u1Valid = 1;
3659	pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3660	pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3661	Assert(pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR);
3662	}
3663	}
3664
3665
3666	/**
3667	* Initializes a PAGE_TAB_HARDWARE_ERROR event.
3668	*
3669	* @param uDevId The device ID.
3670	* @param uDomainId The domain ID.
3671	* @param GCPhysPtEntity The system physical address of the page table
3672	* entity.
3673	* @param enmOp The IOMMU operation being performed.
3674	* @param pEvtPageTabHwErr Where to store the initialized event.
3675	*/
3676	static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3677	PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3678	{
3679	memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3680	pEvtPageTabHwErr->n.u16DevId = uDevId;
3681	pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
3682	pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3683	pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3684	pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3685	pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3686	pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3687	pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3688	pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3689	}
3690
3691
3692	/**
3693	* Raises a PAGE_TAB_HARDWARE_ERROR event.
3694	*
3695	* @param pDevIns The IOMMU device instance.
3696	* @param enmOp The IOMMU operation being performed.
3697	* @param pEvtPageTabHwErr The page table hardware error event.
3698	*
3699	* @thread Any.
3700	*/
3701	static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3702	{
3703	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3704	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3705
3706	IOMMU_LOCK_NORET(pDevIns);
3707
3708	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3709	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3710	if (enmOp != IOMMUOP_CMD)
3711	iommuAmdSetPciTargetAbort(pDevIns);
3712
3713	IOMMU_UNLOCK(pDevIns);
3714
3715	Log((IOMMU_LOG_PFX ": Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3716	pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3717	pEvtPageTabHwErr->n.u2Type));
3718	}
3719
3720
3721	/**
3722	* Initializes a COMMAND_HARDWARE_ERROR event.
3723	*
3724	* @param GCPhysAddr The system physical address the IOMMU attempted to access.
3725	* @param pEvtCmdHwErr Where to store the initialized event.
3726	*/
3727	static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3728	{
3729	memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3730	pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3731	pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3732	pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3733	}
3734
3735
3736	/**
3737	* Raises a COMMAND_HARDWARE_ERROR event.
3738	*
3739	* @param pDevIns The IOMMU device instance.
3740	* @param pEvtCmdHwErr The command hardware error event.
3741	*
3742	* @thread Any.
3743	*/
3744	static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3745	{
3746	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3747	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3748	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3749
3750	IOMMU_LOCK_NORET(pDevIns);
3751
3752	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3753	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3754	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3755
3756	IOMMU_UNLOCK(pDevIns);
3757
3758	Log((IOMMU_LOG_PFX ": Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr,
3759	pEvtCmdHwErr->n.u2Type));
3760	}
3761
3762
3763	/**
3764	* Initializes a DEV_TAB_HARDWARE_ERROR event.
3765	*
3766	* @param uDevId The device ID.
3767	* @param GCPhysDte The system physical address of the failed device table
3768	* access.
3769	* @param enmOp The IOMMU operation being performed.
3770	* @param pEvtDevTabHwErr Where to store the initialized event.
3771	*/
3772	static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3773	PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3774	{
3775	memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3776	pEvtDevTabHwErr->n.u16DevId = uDevId;
3777	pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3778	/** @todo IOMMU: Any other transaction type that can set read/write bit? */
3779	pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3780	pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3781	pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3782	pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3783	pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3784	}
3785
3786
3787	/**
3788	* Raises a DEV_TAB_HARDWARE_ERROR event.
3789	*
3790	* @param pDevIns The IOMMU device instance.
3791	* @param enmOp The IOMMU operation being performed.
3792	* @param pEvtDevTabHwErr The device table hardware error event.
3793	*
3794	* @thread Any.
3795	*/
3796	static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3797	{
3798	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3799	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3800
3801	IOMMU_LOCK_NORET(pDevIns);
3802
3803	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3804	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3805	if (enmOp != IOMMUOP_CMD)
3806	iommuAmdSetPciTargetAbort(pDevIns);
3807
3808	IOMMU_UNLOCK(pDevIns);
3809
3810	Log((IOMMU_LOG_PFX ": Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n",
3811	pEvtDevTabHwErr->n.u16DevId, pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3812	}
3813
3814
3815	/**
3816	* Initializes an ILLEGAL_COMMAND_ERROR event.
3817	*
3818	* @param GCPhysCmd The system physical address of the failed command
3819	* access.
3820	* @param pEvtIllegalCmd Where to store the initialized event.
3821	*/
3822	static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3823	{
3824	Assert(!(GCPhysCmd & UINT64_C(0xf)));
3825	memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3826	pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3827	pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3828	}
3829
3830
3831	/**
3832	* Raises an ILLEGAL_COMMAND_ERROR event.
3833	*
3834	* @param pDevIns The IOMMU device instance.
3835	* @param pEvtIllegalCmd The illegal command error event.
3836	*/
3837	static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3838	{
3839	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3840	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3841	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3842
3843	IOMMU_LOCK_NORET(pDevIns);
3844
3845	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3846	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3847
3848	IOMMU_UNLOCK(pDevIns);
3849
3850	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3851	}
3852
3853
3854	/**
3855	* Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3856	*
3857	* @param uDevId The device ID.
3858	* @param uIova The I/O virtual address.
3859	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3860	* event was caused by an invalid level encoding in the
3861	* DTE.
3862	* @param enmOp The IOMMU operation being performed.
3863	* @param pEvtIllegalDte Where to store the initialized event.
3864	*/
3865	static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3866	PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3867	{
3868	memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3869	pEvtIllegalDte->n.u16DevId = uDevId;
3870	pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3871	pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3872	pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3873	pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3874	pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3875	pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3876	/** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3877	* IOMMU spec here but not for this field for I/O page fault event. */
3878	Assert(!(uIova & UINT64_C(0x3)));
3879	}
3880
3881
3882	/**
3883	* Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3884	*
3885	* @param pDevIns The IOMMU instance data.
3886	* @param enmOp The IOMMU operation being performed.
3887	* @param pEvtIllegalDte The illegal device table entry event.
3888	* @param enmEvtType The illegal device table entry event type.
3889	*
3890	* @thread Any.
3891	*/
3892	static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3893	EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3894	{
3895	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3896	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3897
3898	IOMMU_LOCK_NORET(pDevIns);
3899
3900	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3901	if (enmOp != IOMMUOP_CMD)
3902	iommuAmdSetPciTargetAbort(pDevIns);
3903
3904	IOMMU_UNLOCK(pDevIns);
3905
3906	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3907	pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3908	NOREF(enmEvtType);
3909	}
3910
3911
3912	/**
3913	* Initializes an IO_PAGE_FAULT event.
3914	*
3915	* @param uDevId The device ID.
3916	* @param uDomainId The domain ID.
3917	* @param uIova The I/O virtual address being accessed.
3918	* @param fPresent Transaction to a page marked as present (including
3919	* DTE.V=1) or interrupt marked as remapped
3920	* (IRTE.RemapEn=1).
3921	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3922	* the I/O page fault was caused by invalid level
3923	* encoding.
3924	* @param fPermDenied Permission denied for the address being accessed.
3925	* @param enmOp The IOMMU operation being performed.
3926	* @param pEvtIoPageFault Where to store the initialized event.
3927	*/
3928	static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3929	bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3930	{
3931	Assert(!fPermDenied \|\| fPresent);
3932	memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3933	pEvtIoPageFault->n.u16DevId = uDevId;
3934	//pEvtIoPageFault->n.u4PasidHi = 0;
3935	pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
3936	//pEvtIoPageFault->n.u1GuestOrNested = 0;
3937	//pEvtIoPageFault->n.u1NoExecute = 0;
3938	//pEvtIoPageFault->n.u1User = 0;
3939	pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3940	pEvtIoPageFault->n.u1Present = fPresent;
3941	pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3942	pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3943	pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3944	pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3945	pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3946	pEvtIoPageFault->n.u64Addr = uIova;
3947	}
3948
3949
3950	/**
3951	* Raises an IO_PAGE_FAULT event.
3952	*
3953	* @param pDevIns The IOMMU instance data.
3954	* @param pDte The device table entry. Optional, can be NULL
3955	* depending on @a enmOp.
3956	* @param pIrte The interrupt remapping table entry. Optional, can
3957	* be NULL depending on @a enmOp.
3958	* @param enmOp The IOMMU operation being performed.
3959	* @param pEvtIoPageFault The I/O page fault event.
3960	* @param enmEvtType The I/O page fault event type.
3961	*
3962	* @thread Any.
3963	*/
3964	static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3965	PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3966	{
3967	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3968	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3969
3970	IOMMU_LOCK_NORET(pDevIns);
3971
3972	bool fSuppressEvtLogging = false;
3973	if ( enmOp == IOMMUOP_MEM_READ
3974	\|\| enmOp == IOMMUOP_MEM_WRITE)
3975	{
3976	if ( pDte
3977	&& pDte->n.u1Valid)
3978	{
3979	fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
3980	/** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
3981	* suppression. Perhaps will be possible when we complete IOTLB/cache
3982	* handling. */
3983	}
3984	}
3985	else if (enmOp == IOMMUOP_INTR_REQ)
3986	{
3987	if ( pDte
3988	&& pDte->n.u1IntrMapValid)
3989	fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
3990
3991	if ( !fSuppressEvtLogging
3992	&& pIrte)
3993	fSuppressEvtLogging = pIrte->n.u1SuppressPf;
3994	}
3995	/* else: Events are never suppressed for commands. */
3996
3997	switch (enmEvtType)
3998	{
3999	case kIoPageFaultType_PermDenied:
4000	{
4001	/* Cannot be triggered by a command. */
4002	Assert(enmOp != IOMMUOP_CMD);
4003	RT_FALL_THRU();
4004	}
4005	case kIoPageFaultType_DteRsvdPagingMode:
4006	case kIoPageFaultType_PteInvalidPageSize:
4007	case kIoPageFaultType_PteInvalidLvlEncoding:
4008	case kIoPageFaultType_SkippedLevelIovaNotZero:
4009	case kIoPageFaultType_PteRsvdNotZero:
4010	case kIoPageFaultType_PteValidNotSet:
4011	case kIoPageFaultType_DteTranslationDisabled:
4012	case kIoPageFaultType_PasidInvalidRange:
4013	{
4014	/*
4015	* For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
4016	* create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
4017	*/
4018	if (enmOp != IOMMUOP_TRANSLATE_REQ)
4019	{
4020	if (!fSuppressEvtLogging)
4021	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4022	if (enmOp != IOMMUOP_CMD)
4023	iommuAmdSetPciTargetAbort(pDevIns);
4024	}
4025	break;
4026	}
4027
4028	case kIoPageFaultType_UserSupervisor:
4029	{
4030	/* Access is blocked and only creates an event log entry. */
4031	if (!fSuppressEvtLogging)
4032	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4033	break;
4034	}
4035
4036	case kIoPageFaultType_IrteAddrInvalid:
4037	case kIoPageFaultType_IrteRsvdNotZero:
4038	case kIoPageFaultType_IrteRemapEn:
4039	case kIoPageFaultType_IrteRsvdIntType:
4040	case kIoPageFaultType_IntrReqAborted:
4041	case kIoPageFaultType_IntrWithPasid:
4042	{
4043	/* Only trigerred by interrupt requests. */
4044	Assert(enmOp == IOMMUOP_INTR_REQ);
4045	if (!fSuppressEvtLogging)
4046	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4047	iommuAmdSetPciTargetAbort(pDevIns);
4048	break;
4049	}
4050
4051	case kIoPageFaultType_SmiFilterMismatch:
4052	{
4053	/* Not supported and probably will never be, assert. */
4054	AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
4055	break;
4056	}
4057
4058	case kIoPageFaultType_DevId_Invalid:
4059	{
4060	/* Cannot be triggered by a command. */
4061	Assert(enmOp != IOMMUOP_CMD);
4062	Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
4063	if (!fSuppressEvtLogging)
4064	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
4065	if ( enmOp == IOMMUOP_MEM_READ
4066	\|\| enmOp == IOMMUOP_MEM_WRITE)
4067	iommuAmdSetPciTargetAbort(pDevIns);
4068	break;
4069	}
4070	}
4071
4072	IOMMU_UNLOCK(pDevIns);
4073	}
4074
4075
4076	/**
4077	* Returns whether the I/O virtual address is to be excluded from translation and
4078	* permission checks.
4079	*
4080	* @returns @c true if the DVA is excluded, @c false otherwise.
4081	* @param pThis The IOMMU device state.
4082	* @param pDte The device table entry.
4083	* @param uIova The I/O virtual address.
4084	*
4085	* @remarks Ensure the exclusion range is enabled prior to calling this function.
4086	*
4087	* @thread Any.
4088	*/
4089	static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
4090	{
4091	/* Ensure the exclusion range is enabled. */
4092	Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
4093
4094	/* Check if the IOVA falls within the exclusion range. */
4095	uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
4096	uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
4097	if (uIovaExclLast - uIova >= uIovaExclFirst)
4098	{
4099	/* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
4100	if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
4101	\|\| pDte->n.u1AllowExclusion)
4102	return true;
4103	}
4104	return false;
4105	}
4106
4107
4108	/**
4109	* Reads a device table entry from guest memory given the device ID.
4110	*
4111	* @returns VBox status code.
4112	* @param pDevIns The IOMMU device instance.
4113	* @param uDevId The device ID.
4114	* @param enmOp The IOMMU operation being performed.
4115	* @param pDte Where to store the device table entry.
4116	*
4117	* @thread Any.
4118	*/
4119	static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
4120	{
4121	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4122	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4123
4124	uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
4125	Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
4126
4127	uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
4128	Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
4129
4130	RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
4131	uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
4132	RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
4133
4134	Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
4135	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
4136	if (RT_FAILURE(rc))
4137	{
4138	Log((IOMMU_LOG_PFX ": Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
4139
4140	EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
4141	iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
4142	iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
4143	return VERR_IOMMU_IPE_1;
4144	}
4145
4146
4147	return rc;
4148	}
4149
4150
4151	/**
4152	* Walks the I/O page table to translate the I/O virtual address to a system
4153	* physical address.
4154	*
4155	* @returns VBox status code.
4156	* @param pDevIns The IOMMU device instance.
4157	* @param uIova The I/O virtual address to translate. Must be 4K aligned.
4158	* @param uDevId The device ID.
4159	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4160	* permissions for the access being made.
4161	* @param pDte The device table entry.
4162	* @param enmOp The IOMMU operation being performed.
4163	* @param pWalkResult Where to store the results of the I/O page walk. This is
4164	* only updated when VINF_SUCCESS is returned.
4165	*
4166	* @thread Any.
4167	*/
4168	static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
4169	IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
4170	{
4171	Assert(pDte->n.u1Valid);
4172	Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
4173
4174	/* If the translation is not valid, raise an I/O page fault. */
4175	if (pDte->n.u1TranslationValid)
4176	{ /* likely */ }
4177	else
4178	{
4179	/** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
4180	* doesn't explicitly say whether an I/O page fault is raised. From other
4181	* places in the spec. it seems early page walk terminations (starting with
4182	* the DTE) return the state computed so far and raises an I/O page fault. So
4183	* returning an invalid translation rather than skipping translation. */
4184	Log((IOMMU_LOG_PFX ": Translation valid bit not set -> IOPF"));
4185	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4186	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4187	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4188	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4189	kIoPageFaultType_DteTranslationDisabled);
4190	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4191	}
4192
4193	/* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
4194	uint8_t const uMaxLevel = pDte->n.u3Mode;
4195	if (uMaxLevel != 0)
4196	{ /* likely */ }
4197	else
4198	{
4199	uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4200	if ((fAccess & fDtePerm) != fAccess)
4201	{
4202	Log((IOMMU_LOG_PFX ": Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
4203	return VERR_IOMMU_ADDR_ACCESS_DENIED;
4204	}
4205	pWalkResult->GCPhysSpa = uIova;
4206	pWalkResult->cShift = 0;
4207	pWalkResult->fIoPerm = fDtePerm;
4208	return VINF_SUCCESS;
4209	}
4210
4211	/* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
4212	if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4213	{ /* likely */ }
4214	else
4215	{
4216	/** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
4217	* raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
4218	* I'm just going with I/O page fault. */
4219	Log((IOMMU_LOG_PFX ": Invalid root page table level %#x -> IOPF", uMaxLevel));
4220	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4221	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4222	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4223	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4224	kIoPageFaultType_PteInvalidLvlEncoding);
4225	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4226	}
4227
4228	/* Check permissions bits of the root page table. */
4229	uint8_t const fPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4230	if ((fAccess & fPtePerm) == fAccess)
4231	{ /* likely */ }
4232	else
4233	{
4234	Log((IOMMU_LOG_PFX ": Permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF", fAccess, fPtePerm));
4235	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4236	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4237	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4238	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4239	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4240	}
4241
4242	/** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
4243	* function called iommuAmdWalkIoPageDirectory() and call it for multi-page
4244	* accesses from the 2nd page. We can avoid re-checking the DTE root-page
4245	* table entry every time. Not sure if it's worth optimizing that case now
4246	* or if at all. */
4247
4248	/* The virtual address bits indexing table. */
4249	static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
4250	static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
4251	UINT64_C(0x00000000001ff000),
4252	UINT64_C(0x000000003fe00000),
4253	UINT64_C(0x0000007fc0000000),
4254	UINT64_C(0x0000ff8000000000),
4255	UINT64_C(0x01ff000000000000),
4256	UINT64_C(0xfe00000000000000),
4257	UINT64_C(0x0000000000000000) };
4258	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
4259	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
4260
4261	/* Traverse the I/O page table starting with the page directory in the DTE. */
4262	IOPTENTITY_T PtEntity;
4263	PtEntity.u64 = pDte->au64[0];
4264	for (;;)
4265	{
4266	/* Figure out the system physical address of the page table at the current level. */
4267	uint8_t const uLevel = PtEntity.n.u3NextLevel;
4268
4269	/* Read the page table entity at the current level. */
4270	{
4271	Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
4272	Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4273	uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
4274	uint64_t const offPte = idxPte << 3;
4275	RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
4276	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
4277	if (RT_FAILURE(rc))
4278	{
4279	Log((IOMMU_LOG_PFX ": Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
4280	EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
4281	iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
4282	iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
4283	return VERR_IOMMU_IPE_2;
4284	}
4285	}
4286
4287	/* Check present bit. */
4288	if (PtEntity.n.u1Present)
4289	{ /* likely */ }
4290	else
4291	{
4292	Log((IOMMU_LOG_PFX ": Page table entry not present -> IOPF", fAccess, fPtePerm));
4293	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4294	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4295	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4296	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4297	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4298	}
4299
4300	/* Check permission bits. */
4301	uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4302	if ((fAccess & fPtePerm) == fAccess)
4303	{ /* likely */ }
4304	else
4305	{
4306	Log((IOMMU_LOG_PFX ": Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF", fAccess, fPtePerm));
4307	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4308	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4309	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4310	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4311	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4312	}
4313
4314	/* If this is a PTE, we're at the final level and we're done. */
4315	uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
4316	if (uNextLevel == 0)
4317	{
4318	/* The page size of the translation is the default (4K). */
4319	pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4320	pWalkResult->cShift = X86_PAGE_4K_SHIFT;
4321	pWalkResult->fIoPerm = fPtePerm;
4322	return VINF_SUCCESS;
4323	}
4324	if (uNextLevel == 7)
4325	{
4326	/* The default page size of the translation is overriden. */
4327	RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4328	uint8_t cShift = X86_PAGE_4K_SHIFT;
4329	while (GCPhysPte & RT_BIT_64(cShift++))
4330	;
4331
4332	/* The page size must be larger than the default size and lower than the default size of the higher level. */
4333	Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
4334	if ( cShift > s_acIovaLevelShifts[uLevel]
4335	&& cShift < s_acIovaLevelShifts[uLevel + 1])
4336	{
4337	pWalkResult->GCPhysSpa = GCPhysPte;
4338	pWalkResult->cShift = cShift;
4339	pWalkResult->fIoPerm = fPtePerm;
4340	return VINF_SUCCESS;
4341	}
4342
4343	Log((IOMMU_LOG_PFX ": Page size invalid cShift=%#x -> IOPF", cShift));
4344	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4345	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4346	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4347	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4348	kIoPageFaultType_PteInvalidPageSize);
4349	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4350	}
4351
4352	/* Validate the next level encoding of the PDE. */
4353	#if IOMMU_MAX_HOST_PT_LEVEL < 6
4354	if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4355	{ /* likely */ }
4356	else
4357	{
4358	Log((IOMMU_LOG_PFX ": Next level of PDE invalid uNextLevel=%#x -> IOPF", uNextLevel));
4359	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4360	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4361	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4362	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4363	kIoPageFaultType_PteInvalidLvlEncoding);
4364	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4365	}
4366	#else
4367	Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4368	#endif
4369
4370	/* Validate level transition. */
4371	if (uNextLevel < uLevel)
4372	{ /* likely */ }
4373	else
4374	{
4375	Log((IOMMU_LOG_PFX ": Next level (%#x) must be less than the current level (%#x) -> IOPF", uNextLevel, uLevel));
4376	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4377	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4378	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4379	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4380	kIoPageFaultType_PteInvalidLvlEncoding);
4381	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4382	}
4383
4384	/* Ensure IOVA bits of skipped levels are zero. */
4385	Assert(uLevel > 0);
4386	uint64_t uIovaSkipMask = 0;
4387	for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
4388	uIovaSkipMask \|= s_auIovaLevelMasks[idxLevel];
4389	if (!(uIova & uIovaSkipMask))
4390	{ /* likely */ }
4391	else
4392	{
4393	Log((IOMMU_LOG_PFX ": IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF", uIova, uIovaSkipMask));
4394	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4395	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4396	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4397	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4398	kIoPageFaultType_SkippedLevelIovaNotZero);
4399	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4400	}
4401
4402	/* Continue with traversing the page directory at this level. */
4403	}
4404
4405	/* Shouldn't really get here. */
4406	return VERR_IOMMU_IPE_3;
4407	}
4408
4409
4410	/**
4411	* Looks up an I/O virtual address from the device table.
4412	*
4413	* @returns VBox status code.
4414	* @param pDevIns The IOMMU instance data.
4415	* @param uDevId The device ID.
4416	* @param uIova The I/O virtual address to lookup.
4417	* @param cbAccess The size of the access.
4418	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4419	* permissions for the access being made.
4420	* @param enmOp The IOMMU operation being performed.
4421	* @param pGCPhysSpa Where to store the translated system physical address. Only
4422	* valid when translation succeeds and VINF_SUCCESS is
4423	* returned!
4424	*
4425	* @thread Any.
4426	*/
4427	static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
4428	IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
4429	{
4430	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4431
4432	/* Read the device table entry from memory. */
4433	DTE_T Dte;
4434	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4435	if (RT_SUCCESS(rc))
4436	{
4437	/* If the DTE is not valid, addresses are forwarded without translation */
4438	if (Dte.n.u1Valid)
4439	{ /* likely */ }
4440	else
4441	{
4442	/** @todo IOMMU: Add to IOLTB cache. */
4443	*pGCPhysSpa = uIova;
4444	return VINF_SUCCESS;
4445	}
4446
4447	/* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4448	uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4449	uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4450	if (RT_LIKELY( !fRsvd0
4451	&& !fRsvd1))
4452	{ /* likely */ }
4453	else
4454	{
4455	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4456	EVT_ILLEGAL_DTE_T Event;
4457	iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4458	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4459	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4460	}
4461
4462	/* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
4463	if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
4464	\|\| !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
4465	{ /* likely */ }
4466	else
4467	{
4468	/** @todo IOMMU: Add to IOLTB cache. */
4469	*pGCPhysSpa = uIova;
4470	return VINF_SUCCESS;
4471	}
4472
4473	/** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
4474	* below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
4475
4476	uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
4477	uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
4478	uint64_t cbRemaining = cbAccess;
4479	for (;;)
4480	{
4481	/* Walk the I/O page tables to translate the IOVA and check permission for the access. */
4482	IOWALKRESULT WalkResult;
4483	rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
4484	if (RT_SUCCESS(rc))
4485	{
4486	/** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
4487
4488	/* Store the translated base address before continuing to check permissions for any more pages. */
4489	if (cbRemaining == cbAccess)
4490	{
4491	RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
4492	*pGCPhysSpa = WalkResult.GCPhysSpa \| offSpa;
4493	}
4494
4495	uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
4496	if (cbRemaining > cbPhysPage - offIova)
4497	{
4498	cbRemaining -= (cbPhysPage - offIova);
4499	uBaseIova += cbPhysPage;
4500	offIova = 0;
4501	}
4502	else
4503	break;
4504	}
4505	else
4506	{
4507	Log((IOMMU_LOG_PFX ": I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
4508	uBaseIova, fAccess, rc));
4509	*pGCPhysSpa = NIL_RTGCPHYS;
4510	return rc;
4511	}
4512	}
4513
4514	return rc;
4515	}
4516
4517	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4518	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4519	}
4520
4521
4522	/**
4523	* Memory read request from a device.
4524	*
4525	* @returns VBox status code.
4526	* @param pDevIns The IOMMU device instance.
4527	* @param uDevId The device ID (bus, device, function).
4528	* @param uIova The I/O virtual address being read.
4529	* @param cbRead The number of bytes being read.
4530	* @param pGCPhysSpa Where to store the translated system physical address.
4531	*
4532	* @thread Any.
4533	*/
4534	static int iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, PRTGCPHYS pGCPhysSpa)
4535	{
4536	/* Validate. */
4537	Assert(pDevIns);
4538	Assert(pGCPhysSpa);
4539	Assert(cbRead > 0);
4540
4541	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4542
4543	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4544	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4545	if (Ctrl.n.u1IommuEn)
4546	{
4547	/** @todo IOMMU: IOTLB cache lookup. */
4548
4549	/* Lookup the IOVA from the device table. */
4550	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
4551	}
4552
4553	*pGCPhysSpa = uIova;
4554	return VINF_SUCCESS;
4555	}
4556
4557
4558	/**
4559	* Memory write request from a device.
4560	*
4561	* @returns VBox status code.
4562	* @param pDevIns The IOMMU device instance.
4563	* @param uDevId The device ID (bus, device, function).
4564	* @param uIova The I/O virtual address being written.
4565	* @param cbWrite The number of bytes being written.
4566	* @param pGCPhysSpa Where to store the translated physical address.
4567	*
4568	* @thread Any.
4569	*/
4570	static int iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite, PRTGCPHYS pGCPhysSpa)
4571	{
4572	/* Validate. */
4573	Assert(pDevIns);
4574	Assert(pGCPhysSpa);
4575	Assert(cbWrite > 0);
4576
4577	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4578
4579	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4580	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4581	if (Ctrl.n.u1IommuEn)
4582	{
4583	/** @todo IOMMU: IOTLB cache lookup. */
4584
4585	/* Lookup the IOVA from the device table. */
4586	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
4587	}
4588
4589	*pGCPhysSpa = uIova;
4590	return VINF_SUCCESS;
4591	}
4592
4593
4594	/**
4595	* Reads an interrupt remapping table entry from guest memory given its DTE.
4596	*
4597	* @returns VBox status code.
4598	* @param pDevIns The IOMMU device instance.
4599	* @param uDevId The device ID.
4600	* @param pDte The device table entry.
4601	* @param GCPhysIn The source MSI address.
4602	* @param uDataIn The source MSI data.
4603	* @param enmOp The IOMMU operation being performed.
4604	* @param pIrte Where to store the interrupt remapping table entry.
4605	*
4606	* @thread Any.
4607	*/
4608	static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4609	IOMMUOP enmOp, PIRTE_T pIrte)
4610	{
4611	RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4612	uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) << IOMMU_IRTE_SIZE_SHIFT;
4613	RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4614
4615	/* Ensure the IRTE offset is within the specified table size. */
4616	Assert(pDte->n.u4IntrTableLength < 12);
4617	if (offIrte + sizeof(IRTE_T) <= (1 << pDte->n.u4IntrTableLength) << IOMMU_IRTE_SIZE_SHIFT)
4618	{ /* likely */ }
4619	else
4620	{
4621	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4622	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent /, false / fRsvdNotZero */,
4623	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4624	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4625	kIoPageFaultType_IrteAddrInvalid);
4626	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4627	}
4628
4629	/* Read the IRTE from memory. */
4630	Assert(!(GCPhysIrte & 3));
4631	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4632	if (RT_SUCCESS(rc))
4633	return VINF_SUCCESS;
4634
4635	/** @todo The IOMMU spec. does not tell what kind of error is reported in this
4636	* situation. Is it an I/O page fault or a device table hardware error?
4637	* There's no interrupt table hardware error event, but it's unclear what
4638	* we should do here. */
4639	Log((IOMMU_LOG_PFX ": Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4640	return VERR_IOMMU_IPE_4;
4641	}
4642
4643
4644	/**
4645	* Remap the interrupt using the interrupt remapping table.
4646	*
4647	* @returns VBox status code.
4648	* @param pDevIns The IOMMU instance data.
4649	* @param uDevId The device ID.
4650	* @param pDte The device table entry.
4651	* @param GCPhysIn The source MSI address.
4652	* @param uDataIn The source MSI data.
4653	* @param enmOp The IOMMU operation being performed.
4654	* @param pGCPhysOut Where to store the remapped MSI address.
4655	* @param puDataOut Where to store the remapped MSI data.
4656	*
4657	* @thread Any.
4658	*/
4659	static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4660	IOMMUOP enmOp, PRTGCPHYS pGCPhysOut, uint32_t *puDataOut)
4661	{
4662	Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4663
4664	IRTE_T Irte;
4665	int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, GCPhysIn, uDataIn, enmOp, &Irte);
4666	if (RT_SUCCESS(rc))
4667	{
4668	if (Irte.n.u1RemapEnable)
4669	{
4670	if (!Irte.n.u1GuestMode)
4671	{
4672	if (Irte.n.u3IntrType < VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4673	{
4674	MSI_ADDR_T MsiAddrIn;
4675	MsiAddrIn.u64 = GCPhysIn;
4676
4677	MSI_DATA_T MsiDataIn;
4678	MsiDataIn.u32 = uDataIn;
4679
4680	PMSI_ADDR_T pMsiAddrOut = (PMSI_ADDR_T)pGCPhysOut;
4681	PMSI_DATA_T pMsiDataOut = (PMSI_DATA_T)puDataOut;
4682
4683	/* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
4684	pMsiAddrOut->u64 = GCPhysIn;
4685	pMsiAddrOut->n.u1DestMode = Irte.n.u1DestMode;
4686	pMsiAddrOut->n.u8DestId = Irte.n.u8Dest;
4687
4688	/* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
4689	pMsiDataOut->u32 = uDataIn;
4690	pMsiDataOut->n.u8Vector = Irte.n.u8Vector;
4691	pMsiDataOut->n.u3DeliveryMode = Irte.n.u3IntrType;
4692
4693	return VINF_SUCCESS;
4694	}
4695
4696	Log((IOMMU_LOG_PFX ": Interrupt type (%#x) invalid -> IOPF", Irte.n.u3IntrType));
4697	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4698	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, Irte.n.u1RemapEnable, true /* fRsvdNotZero */,
4699	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4700	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
4701	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4702	}
4703
4704	Log((IOMMU_LOG_PFX ": Guest mode not supported -> IOPF"));
4705	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4706	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, Irte.n.u1RemapEnable, true /* fRsvdNotZero */,
4707	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4708	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4709	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4710	}
4711
4712	Log((IOMMU_LOG_PFX ": Remapping disabled -> IOPF"));
4713	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4714	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, Irte.n.u1RemapEnable, false /* fRsvdNotZero */,
4715	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4716	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4717	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4718	}
4719
4720	return rc;
4721	}
4722
4723
4724	/**
4725	* Looks up an MSI interrupt from the interrupt remapping table.
4726	*
4727	* @returns VBox status code.
4728	* @param pDevIns The IOMMU instance data.
4729	* @param uDevId The device ID.
4730	* @param GCPhysIn The source MSI address.
4731	* @param uDataIn The source MSI data.
4732	* @param enmOp The IOMMU operation being performed.
4733	* @param pGCPhysOut Where to store the remapped MSI address.
4734	* @param puDataOut Where to store the remapped MSI data.
4735	*
4736	* @thread Any.
4737	*/
4738	static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, RTGCPHYS GCPhysIn, uint32_t uDataIn, IOMMUOP enmOp,
4739	PRTGCPHYS pGCPhysOut, uint32_t *puDataOut)
4740	{
4741	/* Read the device table entry from memory. */
4742	DTE_T Dte;
4743	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4744	if (RT_SUCCESS(rc))
4745	{
4746	/* If the DTE is not valid, all interrupts are forwarded without remapping. */
4747	if (Dte.n.u1IntrMapValid)
4748	{
4749	/* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4750	uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4751	uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4752	if (RT_LIKELY( !fRsvd0
4753	&& !fRsvd1))
4754	{ /* likely */ }
4755	else
4756	{
4757	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
4758	fRsvd1));
4759	EVT_ILLEGAL_DTE_T Event;
4760	iommuAmdInitIllegalDteEvent(uDevId, GCPhysIn, true /* fRsvdNotZero */, enmOp, &Event);
4761	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4762	return VERR_IOMMU_INTR_REMAP_FAILED;
4763	}
4764
4765	/** @todo IOMMU: Figure out how we'll redirect LINT0 and LINT1 legacy PIC
4766	* interrupts here. */
4767
4768	/*
4769	* Validate the MSI source address.
4770	*
4771	* 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4772	* CPU is concerned, the MSI region is fixed and we must ensure no other device
4773	* claims the region as I/O space.
4774	*
4775	* See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4776	* See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4777	* See Intel spec. 10.11.1 "Message Address Register Format".
4778	*/
4779	MSI_ADDR_T MsiAddrIn;
4780	MsiAddrIn.u64 = GCPhysIn;
4781	if ((MsiAddrIn.u64 & IOMMU_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4782	{
4783	MSI_DATA_T MsiDataIn;
4784	MsiDataIn.u32 = uDataIn;
4785
4786	/*
4787	* The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4788	* See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4789	*/
4790	uint8_t const u8DeliveryMode = MsiDataIn.n.u3DeliveryMode;
4791	bool fPassThru = false;
4792	switch (u8DeliveryMode)
4793	{
4794	case VBOX_MSI_DELIVERY_MODE_FIXED:
4795	case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4796	{
4797	uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4798	if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4799	{
4800	Log((IOMMU_LOG_PFX ": IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
4801	iommuAmdSetPciTargetAbort(pDevIns);
4802	return VINF_SUCCESS;
4803	}
4804
4805	if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4806	{
4807	fPassThru = true;
4808	break;
4809	}
4810
4811	if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4812	{
4813	/* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4814	uint32_t const uIntTabLen = Dte.n.u4IntrTableLength;
4815	if (Dte.n.u4IntrTableLength < 12)
4816	{ /* likely */ }
4817	else
4818	{
4819	Log((IOMMU_LOG_PFX ": Invalid interrupt table length %#x -> Illegal DTE\n", uIntTabLen));
4820	EVT_ILLEGAL_DTE_T Event;
4821	iommuAmdInitIllegalDteEvent(uDevId, GCPhysIn, false /* fRsvdNotZero */, enmOp, &Event);
4822	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4823	return VERR_IOMMU_INTR_REMAP_FAILED;
4824	}
4825
4826	/*
4827	* We don't support guest interrupt remapping yet. When we do, we'll need to
4828	* check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4829	* in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4830	* already reads the control register, add that as a parameter when we eventually
4831	* support guest interrupt remapping. For now, just assert.
4832	*/
4833	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4834	Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4835	NOREF(pThis);
4836
4837	return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, GCPhysIn, uDataIn, enmOp, pGCPhysOut, puDataOut);
4838	}
4839
4840	/* Paranoia. */
4841	Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
4842
4843	Log((IOMMU_LOG_PFX ":IntCtl mode invalid %#x -> Illegal DTE", uIntrCtrl));
4844	EVT_ILLEGAL_DTE_T Event;
4845	iommuAmdInitIllegalDteEvent(uDevId, GCPhysIn, true /* fRsvdNotZero */, enmOp, &Event);
4846	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4847	return VERR_IOMMU_INTR_REMAP_FAILED;
4848	}
4849
4850	/* SMIs are passed through unmapped. We don't implement SMI filters. */
4851	case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4852	case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4853	case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4854	case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4855	default:
4856	{
4857	Log((IOMMU_LOG_PFX ":MSI data delivery mode invalid %#x -> Target abort", u8DeliveryMode));
4858	iommuAmdSetPciTargetAbort(pDevIns);
4859	return VERR_IOMMU_INTR_REMAP_FAILED;
4860	}
4861	}
4862
4863	if (fPassThru)
4864	{
4865	*pGCPhysOut = GCPhysIn;
4866	*puDataOut = uDataIn;
4867	return VINF_SUCCESS;
4868	}
4869
4870	iommuAmdSetPciTargetAbort(pDevIns);
4871	return VERR_IOMMU_INTR_REMAP_FAILED;
4872	}
4873	else
4874	{
4875	Log((IOMMU_LOG_PFX ":MSI address region invalid %#RX64.", MsiAddrIn.u64));
4876	return VERR_IOMMU_INTR_REMAP_FAILED;
4877	}
4878	}
4879	else
4880	{
4881	/** @todo IOMMU: Add to interrupt remapping cache. */
4882	*pGCPhysOut = GCPhysIn;
4883	*puDataOut = uDataIn;
4884	return VINF_SUCCESS;
4885	}
4886	}
4887
4888	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4889	return VERR_IOMMU_INTR_REMAP_FAILED;
4890	}
4891
4892
4893	/**
4894	* Interrupt remap request from a device.
4895	*
4896	* @returns VBox status code.
4897	* @param pDevIns The IOMMU device instance.
4898	* @param uDevId The device ID (bus, device, function).
4899	* @param GCPhysIn The source MSI address.
4900	* @param uDataIn The source MSI data.
4901	* @param pGCPhysOut Where to store the remapped MSI address.
4902	* @param puDataOut Where to store the remapped MSI data.
4903	*/
4904	static int iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4905	PRTGCPHYS pGCPhysOut, uint32_t *puDataOut)
4906	{
4907	/* Validate. */
4908	Assert(pDevIns);
4909	Assert(pGCPhysOut);
4910	Assert(puDataOut);
4911
4912	/* Remove later. */
4913	RT_NOREF(uDevId, GCPhysIn, uDataIn, pGCPhysOut, puDataOut);
4914
4915	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4916
4917	/* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4918	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4919	if (Ctrl.n.u1IommuEn)
4920	{
4921	/** @todo Cache? */
4922
4923	return iommuAmdLookupIntrTable(pDevIns, uDevId, GCPhysIn, uDataIn, IOMMUOP_INTR_REQ, pGCPhysOut, puDataOut);
4924	}
4925
4926	*pGCPhysOut = GCPhysIn;
4927	*puDataOut = uDataIn;
4928	return VINF_SUCCESS;
4929	}
4930
4931
4932	/**
4933	* @callback_method_impl{FNIOMMMIONEWWRITE}
4934	*/
4935	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
4936	{
4937	NOREF(pvUser);
4938	Assert(cb == 4 \|\| cb == 8);
4939	Assert(!(off & (cb - 1)));
4940
4941	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
4942	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
4943	}
4944
4945
4946	/**
4947	* @callback_method_impl{FNIOMMMIONEWREAD}
4948	*/
4949	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
4950	{
4951	NOREF(pvUser);
4952	Assert(cb == 4 \|\| cb == 8);
4953	Assert(!(off & (cb - 1)));
4954
4955	uint64_t uResult;
4956	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
4957	if (cb == 8)
4958	(uint64_t )pv = uResult;
4959	else
4960	(uint32_t )pv = (uint32_t)uResult;
4961
4962	return rcStrict;
4963	}
4964
4965	# ifdef IN_RING3
4966
4967	/**
4968	* Processes an IOMMU command.
4969	*
4970	* @returns VBox status code.
4971	* @param pDevIns The IOMMU device instance.
4972	* @param pCmd The command to process.
4973	* @param GCPhysCmd The system physical address of the command.
4974	* @param pEvtError Where to store the error event in case of failures.
4975	*
4976	* @thread Command thread.
4977	*/
4978	static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4979	{
4980	IOMMU_ASSERT_NOT_LOCKED(pDevIns);
4981
4982	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4983	uint8_t const bCmd = pCmd->n.u4Opcode;
4984	switch (bCmd)
4985	{
4986	case IOMMU_CMD_COMPLETION_WAIT:
4987	{
4988	PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4989	AssertCompile(sizeof(pCmdComWait) == sizeof(pCmd));
4990
4991	/* Validate reserved bits in the command. */
4992	if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4993	{
4994	/* If Completion Store is requested, write the StoreData to the specified address.*/
4995	if (pCmdComWait->n.u1Store)
4996	{
4997	RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4998	uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4999	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
5000	if (RT_FAILURE(rc))
5001	{
5002	Log((IOMMU_LOG_PFX ": Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
5003	GCPhysStore, rc));
5004	iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
5005	return VERR_IOMMU_CMD_HW_ERROR;
5006	}
5007	}
5008
5009	/* If command completion interrupt is requested, raise an interrupt. */
5010	if (pCmdComWait->n.u1Interrupt)
5011	{
5012	IOMMU_LOCK(pDevIns);
5013	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
5014	if (Ctrl.n.u1CompWaitIntrEn)
5015	{
5016	/* Indicate that this command completed. */
5017	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
5018
5019	/* Check and signal an interrupt if software wants to receive one when this command completes. */
5020	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
5021	if (Ctrl.n.u1CompWaitIntrEn)
5022	iommuAmdRaiseMsiInterrupt(pDevIns);
5023	}
5024	IOMMU_UNLOCK(pDevIns);
5025	}
5026	return VINF_SUCCESS;
5027	}
5028	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5029	return VERR_IOMMU_CMD_INVALID_FORMAT;
5030	}
5031
5032	case IOMMU_CMD_INV_DEV_TAB_ENTRY:
5033	{
5034	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
5035	* then. */
5036	return VINF_SUCCESS;
5037	}
5038
5039	case IOMMU_CMD_INV_IOMMU_PAGES:
5040	{
5041	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
5042	* then. */
5043	return VINF_SUCCESS;
5044	}
5045
5046	case IOMMU_CMD_INV_IOTLB_PAGES:
5047	{
5048	uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
5049	if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
5050	{
5051	/** @todo IOMMU: Implement remote IOTLB invalidation. */
5052	return VERR_NOT_IMPLEMENTED;
5053	}
5054	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5055	return VERR_IOMMU_CMD_NOT_SUPPORTED;
5056	}
5057
5058	case IOMMU_CMD_INV_INTR_TABLE:
5059	{
5060	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
5061	* then. */
5062	return VINF_SUCCESS;
5063	}
5064
5065	case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
5066	{
5067	if (pThis->ExtFeat.n.u1PrefetchSup)
5068	{
5069	/** @todo IOMMU: Implement prefetch. Pretend success until then. */
5070	return VINF_SUCCESS;
5071	}
5072	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5073	return VERR_IOMMU_CMD_NOT_SUPPORTED;
5074	}
5075
5076	case IOMMU_CMD_COMPLETE_PPR_REQ:
5077	{
5078	/* We don't support PPR requests yet. */
5079	Assert(!pThis->ExtFeat.n.u1PprSup);
5080	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5081	return VERR_IOMMU_CMD_NOT_SUPPORTED;
5082	}
5083
5084	case IOMMU_CMD_INV_IOMMU_ALL:
5085	{
5086	if (pThis->ExtFeat.n.u1InvAllSup)
5087	{
5088	/** @todo IOMMU: Invalidate all. Pretend success until then. */
5089	return VINF_SUCCESS;
5090	}
5091	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5092	return VERR_IOMMU_CMD_NOT_SUPPORTED;
5093	}
5094	}
5095
5096	Log((IOMMU_LOG_PFX ": Cmd(%#x): Unrecognized\n", bCmd));
5097	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5098	return VERR_IOMMU_CMD_NOT_SUPPORTED;
5099	}
5100
5101
5102	/**
5103	* The IOMMU command thread.
5104	*
5105	* @returns VBox status code.
5106	* @param pDevIns The IOMMU device instance.
5107	* @param pThread The command thread.
5108	*/
5109	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5110	{
5111	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5112
5113	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5114	return VINF_SUCCESS;
5115
5116	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5117	{
5118	/*
5119	* Sleep perpetually until we are woken up to process commands.
5120	*/
5121	{
5122	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
5123	bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5124	if (!fSignaled)
5125	{
5126	Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
5127	int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5128	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5129	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5130	break;
5131	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
5132	ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5133	}
5134	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
5135	}
5136
5137	/*
5138	* Fetch and process IOMMU commands.
5139	*/
5140	/** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
5141	* at a time) and is expensive due to calls to PGM for fetching guest memory.
5142	* We could optimize by fetching a bunch of commands at a time reducing
5143	* number of calls to PGM. In the longer run we could lock the memory and
5144	* mappings and accessing them directly. */
5145	IOMMU_LOCK(pDevIns);
5146
5147	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
5148	if (Status.n.u1CmdBufRunning)
5149	{
5150	/* Get the offset we need to read the command from memory (circular buffer offset). */
5151	uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5152	uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5153	Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5154	Assert(offHead < cbCmdBuf);
5155	while (offHead != pThis->CmdBufTailPtr.n.off)
5156	{
5157	/* Read the command from memory. */
5158	CMD_GENERIC_T Cmd;
5159	RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
5160	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
5161	if (RT_SUCCESS(rc))
5162	{
5163	/* Increment the command buffer head pointer. */
5164	offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5165	pThis->CmdBufHeadPtr.n.off = offHead;
5166
5167	/* Process the fetched command. */
5168	EVT_GENERIC_T EvtError;
5169	IOMMU_UNLOCK(pDevIns);
5170	rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
5171	IOMMU_LOCK(pDevIns);
5172	if (RT_FAILURE(rc))
5173	{
5174	if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5175	\|\| rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5176	{
5177	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5178	iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5179	}
5180	else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5181	{
5182	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5183	iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5184	}
5185	break;
5186	}
5187	}
5188	else
5189	{
5190	EVT_CMD_HW_ERR_T EvtCmdHwErr;
5191	iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
5192	iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
5193	break;
5194	}
5195	}
5196	}
5197
5198	IOMMU_UNLOCK(pDevIns);
5199	}
5200
5201	LogFlow((IOMMU_LOG_PFX ": Command thread terminating\n"));
5202	return VINF_SUCCESS;
5203	}
5204
5205
5206	/**
5207	* Wakes up the command thread so it can respond to a state change.
5208	*
5209	* @returns VBox status code.
5210	* @param pDevIns The IOMMU device instance.
5211	* @param pThread The command thread.
5212	*/
5213	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5214	{
5215	RT_NOREF(pThread);
5216
5217	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5218	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5219	}
5220
5221
5222	/**
5223	* @callback_method_impl{FNPCICONFIGREAD}
5224	*/
5225	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5226	unsigned cb, uint32_t *pu32Value)
5227	{
5228	/** @todo IOMMU: PCI config read stat counter. */
5229	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5230	Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
5231	VBOXSTRICTRC_VAL(rcStrict)));
5232	return rcStrict;
5233	}
5234
5235
5236	/**
5237	* @callback_method_impl{FNPCICONFIGWRITE}
5238	*/
5239	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5240	unsigned cb, uint32_t u32Value)
5241	{
5242	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5243
5244	/*
5245	* Discard writes to read-only registers that are specific to the IOMMU.
5246	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5247	* See PCI spec. 6.1. "Configuration Space Organization".
5248	*/
5249	switch (uAddress)
5250	{
5251	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5252	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5253	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5254	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5255	{
5256	Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5257	return VINF_SUCCESS;
5258	}
5259	}
5260
5261	IOMMU_LOCK(pDevIns);
5262
5263	VBOXSTRICTRC rcStrict;
5264	switch (uAddress)
5265	{
5266	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5267	{
5268	if (pThis->IommuBar.n.u1Enable)
5269	{
5270	rcStrict = VINF_SUCCESS;
5271	Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5272	break;
5273	}
5274
5275	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5276	if (pThis->IommuBar.n.u1Enable)
5277	{
5278	Assert(pThis->hMmio == NIL_IOMMMIOHANDLE);
5279	Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5280	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5281	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5282	if (RT_FAILURE(rcStrict))
5283	Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
5284	}
5285	break;
5286	}
5287
5288	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5289	{
5290	if (!pThis->IommuBar.n.u1Enable)
5291	pThis->IommuBar.au32[1] = u32Value;
5292	else
5293	{
5294	rcStrict = VINF_SUCCESS;
5295	Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5296	}
5297	break;
5298	}
5299
5300	case IOMMU_PCI_OFF_MSI_CAP_HDR:
5301	{
5302	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5303	RT_FALL_THRU();
5304	}
5305	default:
5306	{
5307	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5308	break;
5309	}
5310	}
5311
5312	IOMMU_UNLOCK(pDevIns);
5313
5314	Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
5315	return rcStrict;
5316	}
5317
5318
5319	/**
5320	* @callback_method_impl{FNDBGFHANDLERDEV}
5321	*/
5322	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5323	{
5324	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5325	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5326	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5327
5328	LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
5329	bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
5330
5331	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5332	/* Device Table Base Addresses (all segments). */
5333	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5334	{
5335	DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5336	pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
5337	if (fVerbose)
5338	{
5339	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5340	IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
5341	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5342	}
5343	}
5344	/* Command Buffer Base Address Register. */
5345	{
5346	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5347	uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5348	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5349	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5350	pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
5351	if (fVerbose)
5352	{
5353	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5354	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5355	cEntries, cbBuffer);
5356	}
5357	}
5358	/* Event Log Base Address Register. */
5359	{
5360	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5361	uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5362	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5363	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5364	pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
5365	if (fVerbose)
5366	{
5367	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5368	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5369	cEntries, cbBuffer);
5370	}
5371	}
5372	/* IOMMU Control Register. */
5373	{
5374	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5375	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5376	if (fVerbose)
5377	{
5378	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5379	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5380	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5381	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5382	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5383	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5384	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5385	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5386	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5387	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5388	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5389	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5390	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5391	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5392	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5393	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5394	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5395	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5396	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5397	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5398	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5399	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5400	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5401	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5402	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5403	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5404	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5405	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5406	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5407	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5408	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5409	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5410	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5411	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5412	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5413	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5414	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5415	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5416	}
5417	}
5418	/* Exclusion Base Address Register. */
5419	{
5420	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5421	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5422	if (fVerbose)
5423	{
5424	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5425	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5426	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5427	ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5428	}
5429	}
5430	/* Exclusion Range Limit Register. */
5431	{
5432	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5433	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5434	if (fVerbose)
5435	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
5436	}
5437	/* Extended Feature Register. */
5438	{
5439	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5440	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5441	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5442	if (fVerbose)
5443	{
5444	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5445	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5446	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5447	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5448	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5449	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5450	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5451	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5452	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5453	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5454	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5455	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5456	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5457	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5458	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5459	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5460	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5461	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5462	pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5463	g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5464	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5465	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5466	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5467	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5468	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5469	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5470	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5471	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5472	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5473	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5474	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5475	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5476	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5477	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5478	}
5479	}
5480	/* PPR Log Base Address Register. */
5481	{
5482	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5483	uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5484	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5485	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5486	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5487	if (fVerbose)
5488	{
5489	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5490	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5491	cEntries, cbBuffer);
5492	}
5493	}
5494	/* Hardware Event (Hi) Register. */
5495	{
5496	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5497	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5498	if (fVerbose)
5499	{
5500	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5501	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5502	}
5503	}
5504	/* Hardware Event (Lo) Register. */
5505	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5506	/* Hardware Event Status. */
5507	{
5508	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5509	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5510	if (fVerbose)
5511	{
5512	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5513	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5514	}
5515	}
5516	/* Guest Virtual-APIC Log Base Address Register. */
5517	{
5518	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5519	uint8_t const uEncodedLen = GALogBar.n.u4Len;
5520	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5521	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5522	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5523	if (fVerbose)
5524	{
5525	pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5526	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5527	cEntries, cbBuffer);
5528	}
5529	}
5530	/* Guest Virtual-APIC Log Tail Address Register. */
5531	{
5532	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5533	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5534	if (fVerbose)
5535	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5536	}
5537	/* PPR Log B Base Address Register. */
5538	{
5539	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5540	uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5541	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5542	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5543	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5544	if (fVerbose)
5545	{
5546	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5547	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5548	cEntries, cbBuffer);
5549	}
5550	}
5551	/* Event Log B Base Address Register. */
5552	{
5553	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5554	uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5555	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5556	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5557	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5558	if (fVerbose)
5559	{
5560	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5561	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5562	cEntries, cbBuffer);
5563	}
5564	}
5565	/* Device-Specific Feature Extension Register. */
5566	{
5567	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5568	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5569	if (fVerbose)
5570	{
5571	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5572	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5573	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5574	}
5575	}
5576	/* Device-Specific Control Extension Register. */
5577	{
5578	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5579	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5580	if (fVerbose)
5581	{
5582	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5583	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5584	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5585	}
5586	}
5587	/* Device-Specific Status Extension Register. */
5588	{
5589	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5590	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
5591	if (fVerbose)
5592	{
5593	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5594	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5595	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5596	}
5597	}
5598	/* MSI Miscellaneous Information Register (Lo and Hi). */
5599	{
5600	MSI_MISC_INFO_T const MsiMiscInfo = pThis->MsiMiscInfo;
5601	pHlp->pfnPrintf(pHlp, " MSI Misc. Info. Register = %#RX64\n", MsiMiscInfo.u64);
5602	if (fVerbose)
5603	{
5604	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumEvtLog);
5605	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MsiMiscInfo.n.u3GstVirtAddrSize);
5606	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MsiMiscInfo.n.u7PhysAddrSize);
5607	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MsiMiscInfo.n.u7VirtAddrSize);
5608	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MsiMiscInfo.n.u1HtAtsResv);
5609	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumPpr);
5610	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumGa);
5611	}
5612	}
5613	/* MSI Capability Header. */
5614	{
5615	MSI_CAP_HDR_T MsiCapHdr;
5616	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5617	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5618	if (fVerbose)
5619	{
5620	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5621	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5622	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5623	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5624	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5625	}
5626	}
5627	/* MSI Address Register (Lo and Hi). */
5628	{
5629	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5630	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5631	MSI_ADDR_T MsiAddr;
5632	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5633	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5634	if (fVerbose)
5635	{
5636	pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5637	pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5638	pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5639	pHlp->pfnPrintf(pHlp, " Address = %#Rx32\n", MsiAddr.n.u12Addr);
5640	pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#Rx32\n", MsiAddr.n.u32Rsvd0);
5641	}
5642	}
5643	/* MSI Data. */
5644	{
5645	MSI_DATA_T MsiData;
5646	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5647	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5648	if (fVerbose)
5649	{
5650	pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5651	MsiData.n.u8Vector);
5652	pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5653	pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5654	pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5655	"level" : "edge");
5656	}
5657	}
5658	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5659	{
5660	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5661	MsiMapCapHdr.u32 = 0;
5662	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5663	if (fVerbose)
5664	{
5665	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5666	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5667	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5668	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5669	}
5670	}
5671	/* Performance Optimization Control Register. */
5672	{
5673	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5674	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5675	if (fVerbose)
5676	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5677	}
5678	/* XT (x2APIC) General Interrupt Control Register. */
5679	{
5680	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5681	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5682	if (fVerbose)
5683	{
5684	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5685	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5686	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5687	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5688	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5689	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5690	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5691	}
5692	}
5693	/* XT (x2APIC) PPR Interrupt Control Register. */
5694	{
5695	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5696	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5697	if (fVerbose)
5698	{
5699	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5700	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5701	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5702	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5703	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5704	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5705	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5706	}
5707	}
5708	/* XT (X2APIC) GA Log Interrupt Control Register. */
5709	{
5710	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5711	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5712	if (fVerbose)
5713	{
5714	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5715	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5716	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5717	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5718	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5719	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5720	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5721	}
5722	}
5723	/* MARC Registers. */
5724	{
5725	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5726	{
5727	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5728	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5729	pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5730
5731	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5732	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5733	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5734	MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5735
5736	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5737	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5738	}
5739	}
5740	/* Reserved Register. */
5741	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5742	/* Command Buffer Head Pointer Register. */
5743	{
5744	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5745	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
5746	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
5747	}
5748	/* Command Buffer Tail Pointer Register. */
5749	{
5750	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5751	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
5752	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
5753	}
5754	/* Event Log Head Pointer Register. */
5755	{
5756	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5757	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
5758	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
5759	}
5760	/* Event Log Tail Pointer Register. */
5761	{
5762	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5763	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
5764	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
5765	}
5766	/* Status Register. */
5767	{
5768	IOMMU_STATUS_T const Status = pThis->Status;
5769	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5770	if (fVerbose)
5771	{
5772	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5773	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5774	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5775	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5776	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5777	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5778	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5779	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5780	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5781	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5782	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5783	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5784	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5785	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5786	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5787	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5788	}
5789	}
5790	/* PPR Log Head Pointer. */
5791	{
5792	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5793	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
5794	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
5795	}
5796	/* PPR Log Tail Pointer. */
5797	{
5798	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5799	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
5800	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
5801	}
5802	/* Guest Virtual-APIC Log Head Pointer. */
5803	{
5804	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5805	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
5806	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
5807	}
5808	/* Guest Virtual-APIC Log Tail Pointer. */
5809	{
5810	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5811	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
5812	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
5813	}
5814	/* PPR Log B Head Pointer. */
5815	{
5816	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5817	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
5818	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
5819	}
5820	/* PPR Log B Tail Pointer. */
5821	{
5822	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5823	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
5824	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
5825	}
5826	/* Event Log B Head Pointer. */
5827	{
5828	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5829	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
5830	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
5831	}
5832	/* Event Log B Tail Pointer. */
5833	{
5834	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5835	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
5836	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
5837	}
5838	/* PPR Log Auto Response Register. */
5839	{
5840	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5841	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5842	if (fVerbose)
5843	{
5844	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5845	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5846	}
5847	}
5848	/* PPR Log Overflow Early Warning Indicator Register. */
5849	{
5850	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5851	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5852	if (fVerbose)
5853	{
5854	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5855	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5856	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5857	}
5858	}
5859	/* PPR Log Overflow Early Warning Indicator Register. */
5860	{
5861	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5862	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5863	if (fVerbose)
5864	{
5865	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5866	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5867	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5868	}
5869	}
5870	}
5871
5872
5873	/**
5874	* @callback_method_impl{FNSSMDEVSAVEEXEC}
5875	*/
5876	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5877	{
5878	/** @todo IOMMU: Save state. */
5879	RT_NOREF2(pDevIns, pSSM);
5880	return VERR_NOT_IMPLEMENTED;
5881	}
5882
5883
5884	/**
5885	* @callback_method_impl{FNSSMDEVLOADEXEC}
5886	*/
5887	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5888	{
5889	/** @todo IOMMU: Load state. */
5890	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
5891	return VERR_NOT_IMPLEMENTED;
5892	}
5893
5894
5895	/**
5896	* @interface_method_impl{PDMDEVREG,pfnReset}
5897	*/
5898	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
5899	{
5900	/*
5901	* Resets read-write portion of the IOMMU state.
5902	*
5903	* State data not initialized here is expected to be initialized during
5904	* device construction and remain read-only through the lifetime of the VM.
5905	*/
5906	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5907	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5908	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5909
5910	memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
5911
5912	pThis->CmdBufBaseAddr.u64 = 0;
5913	pThis->CmdBufBaseAddr.n.u4Len = 8;
5914
5915	pThis->EvtLogBaseAddr.u64 = 0;
5916	pThis->EvtLogBaseAddr.n.u4Len = 8;
5917
5918	pThis->Ctrl.u64 = 0;
5919
5920	pThis->ExclRangeBaseAddr.u64 = 0;
5921	pThis->ExclRangeLimit.u64 = 0;
5922
5923	pThis->PprLogBaseAddr.u64 = 0;
5924	pThis->PprLogBaseAddr.n.u4Len = 8;
5925
5926	pThis->HwEvtHi.u64 = 0;
5927	pThis->HwEvtLo = 0;
5928	pThis->HwEvtStatus.u64 = 0;
5929
5930	pThis->GALogBaseAddr.u64 = 0;
5931	pThis->GALogBaseAddr.n.u4Len = 8;
5932	pThis->GALogTailAddr.u64 = 0;
5933
5934	pThis->PprLogBBaseAddr.u64 = 0;
5935	pThis->PprLogBBaseAddr.n.u4Len = 8;
5936
5937	pThis->EvtLogBBaseAddr.u64 = 0;
5938	pThis->EvtLogBBaseAddr.n.u4Len = 8;
5939
5940	pThis->MsiMiscInfo.u64 = 0;
5941	pThis->PerfOptCtrl.u32 = 0;
5942
5943	pThis->XtGenIntrCtrl.u64 = 0;
5944	pThis->XtPprIntrCtrl.u64 = 0;
5945	pThis->XtGALogIntrCtrl.u64 = 0;
5946
5947	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
5948
5949	pThis->CmdBufHeadPtr.u64 = 0;
5950	pThis->CmdBufTailPtr.u64 = 0;
5951	pThis->EvtLogHeadPtr.u64 = 0;
5952	pThis->EvtLogTailPtr.u64 = 0;
5953
5954	pThis->Status.u64 = 0;
5955
5956	pThis->PprLogHeadPtr.u64 = 0;
5957	pThis->PprLogTailPtr.u64 = 0;
5958
5959	pThis->GALogHeadPtr.u64 = 0;
5960	pThis->GALogTailPtr.u64 = 0;
5961
5962	pThis->PprLogBHeadPtr.u64 = 0;
5963	pThis->PprLogBTailPtr.u64 = 0;
5964
5965	pThis->EvtLogBHeadPtr.u64 = 0;
5966	pThis->EvtLogBTailPtr.u64 = 0;
5967
5968	pThis->PprLogAutoResp.u64 = 0;
5969	pThis->PprLogOverflowEarly.u64 = 0;
5970	pThis->PprLogBOverflowEarly.u64 = 0;
5971
5972	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
5973	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
5974	}
5975
5976
5977	/**
5978	* @interface_method_impl{PDMDEVREG,pfnDestruct}
5979	*/
5980	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
5981	{
5982	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5983	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5984	LogFlowFunc(("\n"));
5985
5986	/* Close the command thread semaphore. */
5987	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
5988	{
5989	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
5990	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
5991	}
5992	return VINF_SUCCESS;
5993	}
5994
5995
5996	/**
5997	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5998	*/
5999	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6000	{
6001	NOREF(iInstance);
6002
6003	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6004	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6005	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
6006	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6007	int rc;
6008	LogFlowFunc(("\n"));
6009
6010	pThisCC->pDevInsR3 = pDevIns;
6011
6012	/*
6013	* Validate and read the configuration.
6014	*/
6015	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Device\|Function", "");
6016
6017	uint8_t uPciDevice;
6018	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Device", &uPciDevice, 0);
6019	if (RT_FAILURE(rc))
6020	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Device\""));
6021
6022	uint8_t uPciFunction;
6023	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Function", &uPciFunction, 2);
6024	if (RT_FAILURE(rc))
6025	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Function\""));
6026
6027	/*
6028	* Register the IOMMU with PDM.
6029	*/
6030	PDMIOMMUREGR3 IommuReg;
6031	RT_ZERO(IommuReg);
6032	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6033	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
6034	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
6035	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
6036	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6037	rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6038	if (RT_FAILURE(rc))
6039	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6040	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6041	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6042	N_("IOMMU helper version mismatch; got %#x expected %#x"),
6043	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6044	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6045	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6046	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6047	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6048
6049	/*
6050	* Initialize read-only PCI configuration space.
6051	*/
6052	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6053	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6054
6055	/* Header. */
6056	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6057	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6058	PDMPciDevSetCommand(pPciDev, 0); /* Command */
6059	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
6060	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6061	PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
6062	PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
6063	PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
6064	PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
6065	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6066	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6067	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
6068	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
6069	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
6070
6071	/* Capability Header. */
6072	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6073	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6074	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
6075	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6076	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6077	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6078	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6079	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6080	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6081	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6082
6083	/* Base Address Low Register. */
6084	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
6085
6086	/* Base Address High Register. */
6087	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6088
6089	/* IOMMU Range Register. */
6090	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
6091
6092	/* Misc. Information Register 0. */
6093	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0,
6094	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
6095	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
6096	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
6097	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
6098	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
6099	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
6100
6101	/* Misc. Information Register 1. */
6102	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, 0);
6103
6104	/* MSI Capability Header register. */
6105	PDMMSIREG MsiReg;
6106	RT_ZERO(MsiReg);
6107	MsiReg.cMsiVectors = 1;
6108	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6109	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6110	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
6111	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6112	AssertRCReturn(rc, rc);
6113
6114	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6115	#if 0
6116	/* MSI Address Lo. */
6117	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
6118	/* MSI Address Hi. */
6119	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
6120	/* MSI Data. */
6121	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
6122	#endif
6123
6124	#if 0
6125	/** @todo IOMMU: I don't know if we need to support this, enable later if
6126	* required. */
6127	/* MSI Mapping Capability Header register. */
6128	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6129	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6130	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6131	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6132	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6133	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6134	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6135	#endif
6136
6137	/*
6138	* Register the PCI function with PDM.
6139	*/
6140	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /* fFlags */, uPciDevice, uPciFunction, "amd-iommu");
6141	AssertLogRelRCReturn(rc, rc);
6142
6143	/*
6144	* Intercept PCI config. space accesses.
6145	*/
6146	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6147	AssertLogRelRCReturn(rc, rc);
6148
6149	/*
6150	* Create the MMIO region.
6151	* Mapping of the region is done when software configures it via PCI config space.
6152	*/
6153	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6154	NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
6155	"AMD-IOMMU", &pThis->hMmio);
6156	AssertLogRelRCReturn(rc, rc);
6157
6158	/*
6159	* Register saved state.
6160	*/
6161	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
6162	NULL, NULL, NULL,
6163	NULL, iommuAmdR3SaveExec, NULL,
6164	NULL, iommuAmdR3LoadExec, NULL);
6165	AssertLogRelRCReturn(rc, rc);
6166
6167	/*
6168	* Register debugger info item.
6169	*/
6170	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6171	AssertLogRelRCReturn(rc, rc);
6172
6173	/*
6174	* Create the command thread and its event semaphore.
6175	*/
6176	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
6177	0 /* cbStack */, RTTHREADTYPE_IO, "AMD-IOMMU");
6178	AssertLogRelRCReturn(rc, rc);
6179
6180	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
6181	AssertLogRelRCReturn(rc, rc);
6182
6183	/*
6184	* Initialize read-only registers.
6185	*/
6186	/** @todo Don't remove the =0 assignment for now. It's just there so it's easier
6187	* for me to see existing features that we might want to implement. Do it
6188	* later. */
6189	pThis->ExtFeat.u64 = 0;
6190	pThis->ExtFeat.n.u1PrefetchSup = 0;
6191	pThis->ExtFeat.n.u1PprSup = 0;
6192	pThis->ExtFeat.n.u1X2ApicSup = 0;
6193	pThis->ExtFeat.n.u1NoExecuteSup = 0;
6194	pThis->ExtFeat.n.u1GstTranslateSup = 0;
6195	pThis->ExtFeat.n.u1InvAllSup = 0;
6196	pThis->ExtFeat.n.u1GstVirtApicSup = 0;
6197	pThis->ExtFeat.n.u1HwErrorSup = 1;
6198	pThis->ExtFeat.n.u1PerfCounterSup = 0;
6199	pThis->ExtFeat.n.u2HostAddrTranslateSize = IOMMU_MAX_HOST_PT_LEVEL;
6200	pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
6201	pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
6202	pThis->ExtFeat.n.u2SmiFilterSup = 0;
6203	pThis->ExtFeat.n.u3SmiFilterCount = 0;
6204	pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
6205	pThis->ExtFeat.n.u2DualPprLogSup = 0;
6206	pThis->ExtFeat.n.u2DualEvtLogSup = 0;
6207	pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
6208	pThis->ExtFeat.n.u1UserSupervisorSup = 0;
6209	AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
6210	pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
6211	pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
6212	pThis->ExtFeat.n.u1PprAutoRespSup = 0;
6213	pThis->ExtFeat.n.u2MarcSup = 0;
6214	pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
6215	pThis->ExtFeat.n.u1PerfOptSup = 0;
6216	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
6217	pThis->ExtFeat.n.u1GstIoSup = 0;
6218	pThis->ExtFeat.n.u1HostAccessSup = 0;
6219	pThis->ExtFeat.n.u1EnhancedPprSup = 0;
6220	pThis->ExtFeat.n.u1AttrForwardSup = 0;
6221	pThis->ExtFeat.n.u1HostDirtySup = 0;
6222	pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
6223	pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
6224	pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
6225
6226	pThis->RsvdReg = 0;
6227
6228	pThis->DevSpecificFeat.u64 = 0;
6229	pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
6230	pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
6231
6232	pThis->DevSpecificCtrl.u64 = 0;
6233	pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
6234	pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
6235
6236	pThis->DevSpecificStatus.u64 = 0;
6237	pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
6238	pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
6239
6240	/*
6241	* Initialize parts of the IOMMU state as it would during reset.
6242	* Must be called -after- initializing PCI config. space registers.
6243	*/
6244	iommuAmdR3Reset(pDevIns);
6245
6246	return VINF_SUCCESS;
6247	}
6248
6249	# else /* !IN_RING3 */
6250
6251	/**
6252	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
6253	*/
6254	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
6255	{
6256	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6257	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6258	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
6259
6260	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
6261
6262	/* Set up the MMIO RZ handlers. */
6263	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
6264	AssertRCReturn(rc, rc);
6265
6266	/* Set up the IOMMU RZ callbacks. */
6267	PDMIOMMUREGCC IommuReg;
6268	RT_ZERO(IommuReg);
6269	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6270	IommuReg.idxIommu = pThis->idxIommu;
6271	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
6272	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
6273	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
6274	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6275	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
6276	AssertRCReturn(rc, rc);
6277
6278	return VINF_SUCCESS;
6279	}
6280
6281	# endif /* !IN_RING3 */
6282
6283	/**
6284	* The device registration structure.
6285	*/
6286	const PDMDEVREG g_DeviceIommuAmd =
6287	{
6288	/* .u32Version = */ PDM_DEVREG_VERSION,
6289	/* .uReserved0 = */ 0,
6290	/* .szName = */ "iommu-amd",
6291	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
6292	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
6293	/* .cMaxInstances = */ ~0U,
6294	/* .uSharedVersion = */ 42,
6295	/* .cbInstanceShared = */ sizeof(IOMMU),
6296	/* .cbInstanceCC = */ sizeof(IOMMUCC),
6297	/* .cbInstanceRC = */ sizeof(IOMMURC),
6298	/* .cMaxPciDevices = */ 1,
6299	/* .cMaxMsixVectors = */ 0,
6300	/* .pszDescription = */ "IOMMU (AMD)",
6301	#if defined(IN_RING3)
6302	/* .pszRCMod = */ "VBoxDDRC.rc",
6303	/* .pszR0Mod = */ "VBoxDDR0.r0",
6304	/* .pfnConstruct = */ iommuAmdR3Construct,
6305	/* .pfnDestruct = */ iommuAmdR3Destruct,
6306	/* .pfnRelocate = */ NULL,
6307	/* .pfnMemSetup = */ NULL,
6308	/* .pfnPowerOn = */ NULL,
6309	/* .pfnReset = */ iommuAmdR3Reset,
6310	/* .pfnSuspend = */ NULL,
6311	/* .pfnResume = */ NULL,
6312	/* .pfnAttach = */ NULL,
6313	/* .pfnDetach = */ NULL,
6314	/* .pfnQueryInterface = */ NULL,
6315	/* .pfnInitComplete = */ NULL,
6316	/* .pfnPowerOff = */ NULL,
6317	/* .pfnSoftReset = */ NULL,
6318	/* .pfnReserved0 = */ NULL,
6319	/* .pfnReserved1 = */ NULL,
6320	/* .pfnReserved2 = */ NULL,
6321	/* .pfnReserved3 = */ NULL,
6322	/* .pfnReserved4 = */ NULL,
6323	/* .pfnReserved5 = */ NULL,
6324	/* .pfnReserved6 = */ NULL,
6325	/* .pfnReserved7 = */ NULL,
6326	#elif defined(IN_RING0)
6327	/* .pfnEarlyConstruct = */ NULL,
6328	/* .pfnConstruct = */ iommuAmdRZConstruct,
6329	/* .pfnDestruct = */ NULL,
6330	/* .pfnFinalDestruct = */ NULL,
6331	/* .pfnRequest = */ NULL,
6332	/* .pfnReserved0 = */ NULL,
6333	/* .pfnReserved1 = */ NULL,
6334	/* .pfnReserved2 = */ NULL,
6335	/* .pfnReserved3 = */ NULL,
6336	/* .pfnReserved4 = */ NULL,
6337	/* .pfnReserved5 = */ NULL,
6338	/* .pfnReserved6 = */ NULL,
6339	/* .pfnReserved7 = */ NULL,
6340	#elif defined(IN_RC)
6341	/* .pfnConstruct = */ iommuAmdRZConstruct,
6342	/* .pfnReserved0 = */ NULL,
6343	/* .pfnReserved1 = */ NULL,
6344	/* .pfnReserved2 = */ NULL,
6345	/* .pfnReserved3 = */ NULL,
6346	/* .pfnReserved4 = */ NULL,
6347	/* .pfnReserved5 = */ NULL,
6348	/* .pfnReserved6 = */ NULL,
6349	/* .pfnReserved7 = */ NULL,
6350	#else
6351	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
6352	#endif
6353	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
6354	};
6355
6356	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
6357

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 84560

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