DevIommuAmd.cpp@ 84677

Last change on this file since 84677 was 84677, checked in by vboxsync, 5 years ago
AMD IOMMU: bugref:9654 Add I/O APIC PDM helper for talking to the IOMMU for remapping MSIs and related bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 271.5 KB

Line
1	/* $Id: DevIommuAmd.cpp 84677 2020-06-04 13:12:06Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/msi.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/AssertGuest.h>
26
27	#include "VBoxDD.h"
28	#include <iprt/x86.h>
29	#include <iprt/string.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/**
36	* @name PCI configuration register offsets.
37	* In accordance with the AMD spec.
38	* @{
39	*/
40	#define IOMMU_PCI_OFF_CAP_HDR 0x40
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
42	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
43	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
44	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
45	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
46	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
47	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
48	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
49	#define IOMMU_PCI_OFF_MSI_DATA 0x70
50	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
51	/** @} */
52
53	/**
54	* @name MMIO register offsets.
55	* In accordance with the AMD spec.
56	* @{
57	*/
58	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
59	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
60	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
61	#define IOMMU_MMIO_OFF_CTRL 0x18
62	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
63	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
64	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
65
66	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
67	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
68	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
69	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
70
71	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
72	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
73
74	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
75	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
76
77	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
78	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
79
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
81	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
82	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
83	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
84	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
85	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
86	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
87	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
88	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
89
90	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
91	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
92	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
93
94	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
95	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
96	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
97	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
98	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
99	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
100	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
101
102	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
103
104	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
105	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
106	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
107
108	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
109	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
110	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
111	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
112	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
113	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
114	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
115	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
116	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
117	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
118	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
119	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
120
121	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
122
123	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
124	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
125	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
126	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
127
128	#define IOMMU_MMIO_OFF_STATUS 0x2020
129
130	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
131	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
132
133	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
134	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
135
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
137	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
138
139	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
140	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
141
142	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
143	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
144	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
145	/** @} */
146
147	/**
148	* @name MMIO register-access table offsets.
149	* Each table [first..last] (both inclusive) represents the range of registers
150	* covered by a distinct register-access table. This is done due to arbitrary large
151	* gaps in the MMIO register offsets themselves.
152	* @{
153	*/
154	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
155	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
156
157	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
158	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
159	/** @} */
160
161	/**
162	* @name Commands.
163	* In accordance with the AMD spec.
164	* @{
165	*/
166	#define IOMMU_CMD_COMPLETION_WAIT 0x01
167	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
168	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
169	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
170	#define IOMMU_CMD_INV_INTR_TABLE 0x05
171	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
172	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
173	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
174	/** @} */
175
176	/**
177	* @name Event codes.
178	* In accordance with the AMD spec.
179	* @{
180	*/
181	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
182	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
183	#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
184	#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
185	#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
186	#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
187	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
188	#define IOMMU_EVT_INVALID_DEV_REQ 0x08
189	#define IOMMU_EVT_INVALID_PPR_REQ 0x09
190	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
191	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
192	/** @} */
193
194	/**
195	* @name IOMMU Capability Header.
196	* In accordance with the AMD spec.
197	* @{
198	*/
199	/** CapId: Capability ID. */
200	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
201	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
202	/** CapPtr: Capability Pointer. */
203	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
204	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
205	/** CapType: Capability Type. */
206	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
207	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
208	/** CapRev: Capability Revision. */
209	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
210	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
211	/** IoTlbSup: IO TLB Support. */
212	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
213	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
214	/** HtTunnel: HyperTransport Tunnel translation support. */
215	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
216	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
217	/** NpCache: Not Present table entries Cached. */
218	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
219	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
220	/** EFRSup: Extended Feature Register (EFR) Supported. */
221	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
222	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
223	/** CapExt: Miscellaneous Information Register Supported . */
224	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
225	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
226	/** Bits 31:29 reserved. */
227	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
228	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
229	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
230	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
231	/** @} */
232
233	/**
234	* @name IOMMU Base Address Low Register.
235	* In accordance with the AMD spec.
236	* @{
237	*/
238	/** Enable: Enables access to the address specified in the Base Address Register. */
239	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
240	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
241	/** Bits 13:1 reserved. */
242	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
243	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
244	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
245	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
246	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
247	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
248	(ENABLE, RSVD_1_13, ADDR));
249	/** @} */
250
251	/**
252	* @name IOMMU Range Register.
253	* In accordance with the AMD spec.
254	* @{
255	*/
256	/** UnitID: HyperTransport Unit ID. */
257	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
258	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
259	/** Bits 6:5 reserved. */
260	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
261	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
262	/** RngValid: Range valid. */
263	#define IOMMU_BF_RANGE_VALID_SHIFT 7
264	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
265	/** BusNumber: Device range bus number. */
266	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
267	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
268	/** First Device. */
269	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
270	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
271	/** Last Device. */
272	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
273	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
274	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
275	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
276	/** @} */
277
278	/**
279	* @name IOMMU Miscellaneous Information Register 0.
280	* In accordance with the AMD spec.
281	* @{
282	*/
283	/** MsiNum: MSI message number. */
284	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
285	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
286	/** GvaSize: Guest Virtual Address Size. */
287	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
288	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
289	/** PaSize: Physical Address Size. */
290	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
291	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
292	/** VaSize: Virtual Address Size. */
293	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
294	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
295	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
296	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
297	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
298	/** Bits 26:23 reserved. */
299	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
300	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
301	/** MsiNumPPR: Peripheral Page Request MSI message number. */
302	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
303	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
304	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
305	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
306	/** @} */
307
308	/**
309	* @name IOMMU Miscellaneous Information Register 1.
310	* In accordance with the AMD spec.
311	* @{
312	*/
313	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
314	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
315	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
316	/** Bits 31:5 reserved. */
317	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
318	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
319	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
320	(MSI_NUM_GA, RSVD_5_31));
321	/** @} */
322
323	/**
324	* @name MSI Capability Header Register.
325	* In accordance with the AMD spec.
326	* @{
327	*/
328	/** MsiCapId: Capability ID. */
329	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
330	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
331	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
332	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
333	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
334	/** MsiEn: Message Signal Interrupt enable. */
335	#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
336	#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
337	/** MsiMultMessCap: MSI Multi-Message Capability. */
338	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
339	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
340	/** MsiMultMessEn: MSI Mult-Message Enable. */
341	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
342	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
343	/** Msi64BitEn: MSI 64-bit Enabled. */
344	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
345	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
346	/** Bits 31:24 reserved. */
347	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
348	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
349	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
350	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
351	/** @} */
352
353	/**
354	* @name MSI Mapping Capability Header Register.
355	* In accordance with the AMD spec.
356	* @{
357	*/
358	/** MsiMapCapId: Capability ID. */
359	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
360	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
361	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
362	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
363	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
364	/** MsiMapEn: MSI mapping capability enable. */
365	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
366	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
367	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
368	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
369	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
370	/** Bits 18:28 reserved. */
371	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
372	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
373	/** MsiMapCapType: MSI mapping capability. */
374	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
375	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
376	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
377	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
378	/** @} */
379
380	/**
381	* @name IOMMU Status Register Bits.
382	* In accordance with the AMD spec.
383	* @{
384	*/
385	/** EventOverflow: Event log overflow. */
386	#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
387	/** EventLogInt: Event log interrupt. */
388	#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
389	/** ComWaitInt: Completion wait interrupt. */
390	#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
391	/** EventLogRun: Event log is running. */
392	#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
393	/** CmdBufRun: Command buffer is running. */
394	#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
395	/** PprOverflow: Peripheral page request log overflow. */
396	#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
397	/** PprInt: Peripheral page request log interrupt. */
398	#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
399	/** PprLogRun: Peripheral page request log is running. */
400	#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
401	/** GALogRun: Guest virtual-APIC log is running. */
402	#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
403	/** GALOverflow: Guest virtual-APIC log overflow. */
404	#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
405	/** GAInt: Guest virtual-APIC log interrupt. */
406	#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
407	/** PprOvrflwB: PPR Log B overflow. */
408	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
409	/** PprLogActive: PPR Log B is active. */
410	#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
411	/** EvtOvrflwB: Event log B overflow. */
412	#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
413	/** EventLogActive: Event log B active. */
414	#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
415	/** PprOvrflwEarlyB: PPR log B overflow early warning. */
416	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
417	/** PprOverflowEarly: PPR log overflow early warning. */
418	#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
419	/** @} */
420
421	/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
422	* In accordance with the AMD spec.
423	*
424	* These values match the shifted values of the IR and IW field of the DTE and the
425	* PTE, PDE of the I/O page tables.
426	*
427	* @{ */
428	#define IOMMU_IO_PERM_NONE (0)
429	#define IOMMU_IO_PERM_READ RT_BIT_64(0)
430	#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
431	#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ \| IOMMU_IO_PERM_WRITE)
432	#define IOMMU_IO_PERM_SHIFT 61
433	#define IOMMU_IO_PERM_MASK 0x3
434	/** @} */
435
436	/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
437	* In accordance with the AMD spec.
438	* @{ */
439	#define SYSMGTTYPE_DMA_DENY (0)
440	#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
441	#define SYSMGTTYPE_MSG_INT_ALLOW (2)
442	#define SYSMGTTYPE_DMA_ALLOW (3)
443	/** @} */
444
445	/** @name IOMMU_INTR_CTRL_XX: DTE::IntCtl field values.
446	* These are control bits for handling fixed and arbitrated interrupts.
447	* In accordance with the AMD spec.
448	* @{ */
449	#define IOMMU_INTR_CTRL_TARGET_ABORT (0)
450	#define IOMMU_INTR_CTRL_FWD_UNMAPPED (1)
451	#define IOMMU_INTR_CTRL_REMAP (2)
452	#define IOMMU_INTR_CTRL_RSVD (3)
453	/** @} */
454
455	/** @name Miscellaneous IOMMU defines.
456	* @{ */
457	/** Log prefix string. */
458	#define IOMMU_LOG_PFX "AMD_IOMMU"
459	/** The current saved state version. */
460	#define IOMMU_SAVED_STATE_VERSION 1
461	/** AMD's vendor ID. */
462	#define IOMMU_PCI_VENDOR_ID 0x1022
463	/** VirtualBox IOMMU device ID. */
464	#define IOMMU_PCI_DEVICE_ID 0xc0de
465	/** VirtualBox IOMMU device revision ID. */
466	#define IOMMU_PCI_REVISION_ID 0x01
467	/** Size of the MMIO region in bytes. */
468	#define IOMMU_MMIO_REGION_SIZE _16K
469	/** Number of device table segments supported (power of 2). */
470	#define IOMMU_MAX_DEV_TAB_SEGMENTS 3
471	/** Maximum host address translation level supported (inclusive). */
472	#define IOMMU_MAX_HOST_PT_LEVEL 6
473	/** The IOTLB entry magic. */
474	#define IOMMU_IOTLBE_MAGIC 0x10acce55
475	/** The device-specific feature major revision. */
476	#define IOMMU_DEVSPEC_FEAT_MAJOR_VERSION 0x1
477	/** The device-specific feature minor revision. */
478	#define IOMMU_DEVSPEC_FEAT_MINOR_VERSION 0x0
479	/** The device-specific control major revision. */
480	#define IOMMU_DEVSPEC_CTRL_MAJOR_VERSION 0x1
481	/** The device-specific control minor revision. */
482	#define IOMMU_DEVSPEC_CTRL_MINOR_VERSION 0x0
483	/** The device-specific status major revision. */
484	#define IOMMU_DEVSPEC_STATUS_MAJOR_VERSION 0x1
485	/** The device-specific status minor revision. */
486	#define IOMMU_DEVSPEC_STATUS_MINOR_VERSION 0x0
487	/** @} */
488
489	/**
490	* Acquires the IOMMU PDM lock.
491	* This will make a long jump to ring-3 to acquire the lock if necessary.
492	*/
493	#define IOMMU_LOCK(a_pDevIns) \
494	do { \
495	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
496	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
497	{ /* likely */ } \
498	else \
499	return rcLock; \
500	} while (0)
501
502	/**
503	* Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
504	* This will make a long jump to ring-3 to acquire the lock if necessary.
505	*/
506	#define IOMMU_LOCK_NORET(a_pDevIns) \
507	do { \
508	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
509	AssertRC(rcLock); \
510	} while (0)
511
512	/**
513	* Releases the IOMMU PDM lock.
514	*/
515	#define IOMMU_UNLOCK(a_pDevIns) \
516	do { \
517	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
518	} while (0)
519
520	/**
521	* Asserts that the critsect is owned by this thread.
522	*/
523	#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
524	do { \
525	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
526	} while (0)
527
528	/**
529	* Asserts that the critsect is not owned by this thread.
530	*/
531	#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
532	do { \
533	Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
534	} while (0)
535
536	/**
537	* Gets the device table size given the size field.
538	*/
539	#define IOMMU_GET_DEV_TAB_SIZE(a_uSize) (((a_uSize) + 1) << X86_PAGE_4K_SHIFT)
540
541
542	/*********************************************************************************************************************************
543	* Structures and Typedefs *
544	*********************************************************************************************************************************/
545	/**
546	* The Device ID.
547	* In accordance with VirtualBox's PCI configuration.
548	*/
549	typedef union
550	{
551	struct
552	{
553	uint16_t u3Function : 3; /*< Bits 2:0 - Function. /
554	uint16_t u9Device : 9; /*< Bits 11:3 - Device. /
555	uint16_t u4Bus : 4; /*< Bits 15:12 - Bus. /
556	} n;
557	/** The unsigned integer view. */
558	uint16_t u;
559	} DEVICE_ID_T;
560	AssertCompileSize(DEVICE_ID_T, 2);
561
562	/**
563	* Device Table Entry (DTE).
564	* In accordance with the AMD spec.
565	*/
566	typedef union
567	{
568	struct
569	{
570	RT_GCC_EXTENSION uint64_t u1Valid : 1; /*< Bit 0 - V: Valid. /
571	RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
572	RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
573	RT_GCC_EXTENSION uint64_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
574	RT_GCC_EXTENSION uint64_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
575	RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /*< Bits 51:12 - Page Table Root Pointer. /
576	RT_GCC_EXTENSION uint64_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
577	RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
578	RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
579	RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
580	RT_GCC_EXTENSION uint64_t u2GstMode : 2; /*< Bits 57:56 - GLX: Guest Paging mode levels. /
581	RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). /
582	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
583	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
584	RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
585	RT_GCC_EXTENSION uint64_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
586	RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). /
587	RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /*< Bit 96 - I: IOTLB Enable. /
588	RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
589	RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
590	RT_GCC_EXTENSION uint64_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
591	RT_GCC_EXTENSION uint64_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
592	RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
593	RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
594	RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
595	RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
596	RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). /
597	RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
598	RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
599	RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
600	RT_GCC_EXTENSION uint64_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
601	RT_GCC_EXTENSION uint64_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
602	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
603	RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
604	RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
605	RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
606	RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
607	RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
608	RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 Pass-through. /
609	RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 Pass-through. /
610	RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /*< Bits 223:192 - Reserved. /
611	RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
612	RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
613	RT_GCC_EXTENSION uint64_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
614	RT_GCC_EXTENSION uint64_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
615	} n;
616	/** The 32-bit unsigned integer view. */
617	uint32_t au32[8];
618	/** The 64-bit unsigned integer view. */
619	uint64_t au64[4];
620	} DTE_T;
621	AssertCompileSize(DTE_T, 32);
622	/** Pointer to a device table entry. */
623	typedef DTE_T *PDTE_T;
624	/** Pointer to a const device table entry. */
625	typedef DTE_T const *PCDTE_T;
626
627	/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
628	* Support) feature (bits 52:53). */
629	#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
630
631	/** Mask of valid bits for GTSup (Guest Translation Support) feature (bits 55:60,
632	* bits 80:95). */
633	#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
634	#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
635
636	/* Mask of valid bits for GIoSup (Guest I/O Protection Support) feature (bit 54). */
637	#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
638
639	/* Mask of valid DTE feature bits. */
640	#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
641	\| IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
642	\| IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
643	#define IOMMU_DTE_QWORD_1_FEAT_MASK (IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
644
645	/* Mask of all valid DTE bits (including all feature bits). */
646	#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
647	#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
648	#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xf70fffffffffffff)
649	#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
650
651	/* Mask of the interrupt table root pointer. */
652	#define IOMMU_DTE_IRTE_ROOT_PTR_MASK UINT64_C(0x000fffffffffff80)
653
654	/**
655	* I/O Page Translation Entry.
656	* In accordance with the AMD spec.
657	*/
658	typedef union
659	{
660	struct
661	{
662	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
663	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
664	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
665	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
666	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
667	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
668	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
669	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
670	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
671	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
672	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
673	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
674	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
675	} n;
676	/** The 64-bit unsigned integer view. */
677	uint64_t u64;
678	} IOPTE_T;
679	AssertCompileSize(IOPTE_T, 8);
680
681	/**
682	* I/O Page Directory Entry.
683	* In accordance with the AMD spec.
684	*/
685	typedef union
686	{
687	struct
688	{
689	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
690	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
691	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
692	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
693	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
694	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
695	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
696	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
697	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
698	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
699	} n;
700	/** The 64-bit unsigned integer view. */
701	uint64_t u64;
702	} IOPDE_T;
703	AssertCompileSize(IOPDE_T, 8);
704
705	/**
706	* I/O Page Table Entity.
707	* In accordance with the AMD spec.
708	*
709	* This a common subset of an DTE.au64[0], PTE and PDE.
710	* Named as an "entity" to avoid confusing it with PTE.
711	*/
712	typedef union
713	{
714	struct
715	{
716	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
717	RT_GCC_EXTENSION uint64_t u8Ign0 : 8; /*< Bits 8:1 - Ignored. /
718	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Mode / Next Level: Next page translation level. /
719	RT_GCC_EXTENSION uint64_t u40Addr : 40; /*< Bits 51:12 - Page address. /
720	RT_GCC_EXTENSION uint64_t u9Ign0 : 9; /*< Bits 60:52 - Ignored. /
721	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
722	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
723	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
724	} n;
725	/** The 64-bit unsigned integer view. */
726	uint64_t u64;
727	} IOPTENTITY_T;
728	AssertCompileSize(IOPTENTITY_T, 8);
729	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPTE_T));
730	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPDE_T));
731	/** Pointer to an IOPT_ENTITY_T struct. */
732	typedef IOPTENTITY_T *PIOPTENTITY_T;
733	/** Pointer to a const IOPT_ENTITY_T struct. */
734	typedef IOPTENTITY_T const *PCIOPTENTITY_T;
735	/** Mask of the address field. */
736	#define IOMMU_PTENTITY_ADDR_MASK UINT64_C(0x000ffffffffff000)
737
738	/**
739	* Interrupt Remapping Table Entry (IRTE).
740	* In accordance with the AMD spec.
741	*/
742	typedef union
743	{
744	struct
745	{
746	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
747	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
748	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
749	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
750	uint32_t u1DestMode : 1; /*< Bit 6 - DM: Destination Mode. /
751	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
752	uint32_t u8Dest : 8; /*< Bits 15:8 - Destination. /
753	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
754	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
755	} n;
756	/** The 32-bit unsigned integer view. */
757	uint32_t u32;
758	} IRTE_T;
759	AssertCompileSize(IRTE_T, 4);
760	/** The number of bits to shift the IRTE offset to get the IRTE. */
761	#define IOMMU_IRTE_SIZE_SHIFT (2)
762	/** Pointer to an IRTE_T struct. */
763	typedef IRTE_T *PIRTE_T;
764	/** Pointer to a const IRTE_T struct. */
765	typedef IRTE_T const *PCIRTE_T;
766
767	/** The IRTE offset corresponds directly to bits 10:0 of the originating MSI
768	* interrupt message. See AMD IOMMU spec. 2.2.5 "Interrupt Remapping Tables". */
769	#define IOMMU_MSI_DATA_IRTE_OFFSET_MASK UINT32_C(0x000007ff)
770
771	/**
772	* Command: Generic Command Buffer Entry.
773	* In accordance with the AMD spec.
774	*/
775	typedef union
776	{
777	struct
778	{
779	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
780	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
781	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
782	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
783	} n;
784	/** The 64-bit unsigned integer view. */
785	uint64_t au64[2];
786	} CMD_GENERIC_T;
787	AssertCompileSize(CMD_GENERIC_T, 16);
788	/** Pointer to a generic command buffer entry. */
789	typedef CMD_GENERIC_T *PCMD_GENERIC_T;
790	/** Pointer to a const generic command buffer entry. */
791	typedef CMD_GENERIC_T const *PCCMD_GENERIC_T;
792
793	/** Number of bits to shift the byte offset of a command in the command buffer to
794	* get its index. */
795	#define IOMMU_CMD_GENERIC_SHIFT 4
796
797	/**
798	* Command: COMPLETION_WAIT.
799	* In accordance with the AMD spec.
800	*/
801	typedef union
802	{
803	struct
804	{
805	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
806	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
807	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
808	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
809	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
810	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
811	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
812	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
813	} n;
814	/** The 64-bit unsigned integer view. */
815	uint64_t au64[2];
816	} CMD_COMWAIT_T;
817	AssertCompileSize(CMD_COMWAIT_T, 16);
818	/** Pointer to a completion wait command. */
819	typedef CMD_COMWAIT_T *PCMD_COMWAIT_T;
820	/** Pointer to a const completion wait command. */
821	typedef CMD_COMWAIT_T const *PCCMD_COMWAIT_T;
822	#define IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK UINT64_C(0xf00fffffffffffff)
823
824	/**
825	* Command: INVALIDATE_DEVTAB_ENTRY.
826	* In accordance with the AMD spec.
827	*/
828	typedef union
829	{
830	struct
831	{
832	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
833	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
834	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
835	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
836	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
837	} n;
838	/** The 64-bit unsigned integer view. */
839	uint64_t au64[2];
840	} CMD_INV_DTE_T;
841	AssertCompileSize(CMD_INV_DTE_T, 16);
842
843	/**
844	* Command: INVALIDATE_IOMMU_PAGES.
845	* In accordance with the AMD spec.
846	*/
847	typedef union
848	{
849	struct
850	{
851	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
852	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
853	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
854	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
855	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
856	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
857	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
858	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
859	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
860	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
861	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
862	} n;
863	/** The 64-bit unsigned integer view. */
864	uint64_t au64[2];
865	} CMD_INV_IOMMU_PAGES_T;
866	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
867
868	/**
869	* Command: INVALIDATE_IOTLB_PAGES.
870	* In accordance with the AMD spec.
871	*/
872	typedef union
873	{
874	struct
875	{
876	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
877	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
878	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
879	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
880	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
881	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
882	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
883	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
884	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
885	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
886	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
887	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
888	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
889	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
890	} n;
891	/** The 64-bit unsigned integer view. */
892	uint64_t au64[2];
893	} CMD_INV_IOTLB_PAGES_T;
894	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
895
896	/**
897	* Command: INVALIDATE_INTR_TABLE.
898	* In accordance with the AMD spec.
899	*/
900	typedef union
901	{
902	struct
903	{
904	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
905	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
906	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
907	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
908	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
909	} u;
910	/** The 64-bit unsigned integer view. */
911	uint64_t au64[2];
912	} CMD_INV_INTR_TABLE_T;
913	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
914
915	/**
916	* Command: COMPLETE_PPR_REQ.
917	* In accordance with the AMD spec.
918	*/
919	typedef union
920	{
921	struct
922	{
923	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
924	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
925	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
926	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
927	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
928	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
929	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
930	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
931	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
932	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
933	} n;
934	/** The 64-bit unsigned integer view. */
935	uint64_t au64[2];
936	} CMD_COMPLETE_PPR_REQ_T;
937	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
938
939	/**
940	* Command: INV_IOMMU_ALL.
941	* In accordance with the AMD spec.
942	*/
943	typedef union
944	{
945	struct
946	{
947	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
948	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
949	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
950	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
951	} n;
952	/** The 64-bit unsigned integer view. */
953	uint64_t au64[2];
954	} CMD_IOMMU_ALL_T;
955	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
956
957	/**
958	* Event Log Entry: Generic.
959	* In accordance with the AMD spec.
960	*/
961	typedef union
962	{
963	struct
964	{
965	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
966	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
967	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
968	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
969	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
970	} n;
971	/** The 32-bit unsigned integer view. */
972	uint32_t au32[4];
973	} EVT_GENERIC_T;
974	AssertCompileSize(EVT_GENERIC_T, 16);
975	/** Number of bits to shift the byte offset of an event entry in the event log
976	* buffer to get its index. */
977	#define IOMMU_EVT_GENERIC_SHIFT 4
978	/** Pointer to a generic event log entry. */
979	typedef EVT_GENERIC_T *PEVT_GENERIC_T;
980	/** Pointer to a const generic event log entry. */
981	typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
982
983	/**
984	* Hardware event types.
985	* In accordance with the AMD spec.
986	*/
987	typedef enum HWEVTTYPE
988	{
989	HWEVTTYPE_RSVD = 0,
990	HWEVTTYPE_MASTER_ABORT,
991	HWEVTTYPE_TARGET_ABORT,
992	HWEVTTYPE_DATA_ERROR
993	} HWEVTTYPE;
994	AssertCompileSize(HWEVTTYPE, 4);
995
996	/**
997	* Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
998	* In accordance with the AMD spec.
999	*/
1000	typedef union
1001	{
1002	struct
1003	{
1004	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1005	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1006	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
1007	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1008	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1009	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1010	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1011	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1012	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1013	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
1014	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1015	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1016	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
1017	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1018	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1019	} n;
1020	/** The 32-bit unsigned integer view. */
1021	uint32_t au32[4];
1022	/** The 64-bit unsigned integer view. */
1023	uint64_t au64[2];
1024	} EVT_ILLEGAL_DTE_T;
1025	AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
1026	/** Pointer to an illegal device table entry event. */
1027	typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
1028	/** Pointer to a const illegal device table entry event. */
1029	typedef EVT_ILLEGAL_DTE_T const *PCEVT_ILLEGAL_DTE_T;
1030
1031	/**
1032	* Event Log Entry: IO_PAGE_FAULT_EVENT.
1033	* In accordance with the AMD spec.
1034	*/
1035	typedef union
1036	{
1037	struct
1038	{
1039	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1040	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1041	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1042	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1043	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
1044	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
1045	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1046	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
1047	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1048	uint16_t u1PermDenied : 1; /*< Bit 54 - PE: Permission Indicator. /
1049	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1050	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1051	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
1052	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1053	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1054	} n;
1055	/** The 32-bit unsigned integer view. */
1056	uint32_t au32[4];
1057	/** The 64-bit unsigned integer view. */
1058	uint64_t au64[2];
1059	} EVT_IO_PAGE_FAULT_T;
1060	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
1061	/** Pointer to an I/O page fault event. */
1062	typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
1063	/** Pointer to a const I/O page fault event. */
1064	typedef EVT_IO_PAGE_FAULT_T const *PCEVT_IO_PAGE_FAULT_T;
1065
1066
1067	/**
1068	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
1069	* In accordance with the AMD spec.
1070	*/
1071	typedef union
1072	{
1073	struct
1074	{
1075	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1076	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1077	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
1078	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). /
1079	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1080	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). /
1081	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
1082	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation (1=translation, 0=transaction). /
1083	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1084	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1085	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1086	uint64_t u64Addr; /*< Bits 127:64 - Address. /
1087	} n;
1088	/** The 32-bit unsigned integer view. */
1089	uint32_t au32[4];
1090	/** The 64-bit unsigned integer view. */
1091	uint64_t au64[2];
1092	} EVT_DEV_TAB_HW_ERROR_T;
1093	AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1094	/** Pointer to a device table hardware error event. */
1095	typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1096	/** Pointer to a const device table hardware error event. */
1097	typedef EVT_DEV_TAB_HW_ERROR_T const *PCEVT_DEV_TAB_HW_ERROR_T;
1098
1099	/**
1100	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1101	* In accordance with the AMD spec.
1102	*/
1103	typedef union
1104	{
1105	struct
1106	{
1107	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1108	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1109	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1110	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1111	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1112	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1113	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1114	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1115	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
1116	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
1117	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1118	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1119	uint32_t u4EvtCode : 4; /*< Bit 63:60 - Event code. /
1120	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1121	* table 58 mentions Addr[31:4], we just use the full 64-bits. Looks like a
1122	* typo in the figure.See AMD AMD IOMMU spec (3.05-PUB, Jan 2020). */
1123	uint64_t u64Addr; /** Bits 127:64 - Address: SPA of the page table entry. */
1124	} n;
1125	/** The 32-bit unsigned integer view. */
1126	uint32_t au32[4];
1127	/** The 64-bit unsigned integer view. */
1128	uint64_t au64[2];
1129	} EVT_PAGE_TAB_HW_ERR_T;
1130	AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1131	/** Pointer to a page table hardware error event. */
1132	typedef EVT_PAGE_TAB_HW_ERR_T *PEVT_PAGE_TAB_HW_ERR_T;
1133	/** Pointer to a const page table hardware error event. */
1134	typedef EVT_PAGE_TAB_HW_ERR_T const *PCEVT_PAGE_TAB_HW_ERR_T;
1135
1136	/**
1137	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
1138	* In accordance with the AMD spec.
1139	*/
1140	typedef union
1141	{
1142	struct
1143	{
1144	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1145	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
1146	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1147	uint64_t u64Addr; /*< Bits 127:64 - Address: SPA of the invalid command. /
1148	} n;
1149	/** The 32-bit unsigned integer view. */
1150	uint32_t au32[4];
1151	/** The 64-bit unsigned integer view. */
1152	uint64_t au64[2];
1153	} EVT_ILLEGAL_CMD_ERR_T;
1154	AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1155	/** Pointer to an illegal command error event. */
1156	typedef EVT_ILLEGAL_CMD_ERR_T *PEVT_ILLEGAL_CMD_ERR_T;
1157	/** Pointer to a const illegal command error event. */
1158	typedef EVT_ILLEGAL_CMD_ERR_T const *PCEVT_ILLEGAL_CMD_ERR_T;
1159
1160	/**
1161	* Event Log Entry: COMMAND_HARDWARE_ERROR.
1162	* In accordance with the AMD spec.
1163	*/
1164	typedef union
1165	{
1166	struct
1167	{
1168	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1169	uint32_t u25Rsvd1 : 25; /*< Bits 56:32 - Reserved. /
1170	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1171	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1172	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1173	uint64_t u64Addr; /*< Bits 128:64 - Address: SPA of the attempted access. /
1174	} n;
1175	/** The 32-bit unsigned integer view. */
1176	uint32_t au32[4];
1177	/** The 64-bit unsigned integer view. */
1178	uint64_t au64[2];
1179	} EVT_CMD_HW_ERR_T;
1180	AssertCompileSize(EVT_CMD_HW_ERR_T, 16);
1181	/** Pointer to a command hardware error event. */
1182	typedef EVT_CMD_HW_ERR_T *PEVT_CMD_HW_ERR_T;
1183	/** Pointer to a const command hardware error event. */
1184	typedef EVT_CMD_HW_ERR_T const *PCEVT_CMD_HW_ERR_T;
1185
1186	/**
1187	* Event Log Entry: IOTLB_INV_TIMEOUT.
1188	* In accordance with the AMD spec.
1189	*/
1190	typedef union
1191	{
1192	struct
1193	{
1194	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1195	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
1196	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1197	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1198	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1199	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
1200	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
1201	} n;
1202	/** The 32-bit unsigned integer view. */
1203	uint32_t au32[4];
1204	} EVT_IOTLB_INV_TIMEOUT_T;
1205	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1206
1207	/**
1208	* Event Log Entry: INVALID_DEVICE_REQUEST.
1209	* In accordance with the AMD spec.
1210	*/
1211	typedef union
1212	{
1213	struct
1214	{
1215	uint32_t u16DevId : 16; /**< Bits 15:0 - Device ID. /
1216	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1217	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
1218	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1219	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1220	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
1221	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
1222	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
1223	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
1224	uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. /
1225	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
1226	} n;
1227	/** The 32-bit unsigned integer view. */
1228	uint32_t au32[4];
1229	} EVT_INVALID_DEV_REQ_T;
1230	AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1231
1232	/**
1233	* Event Log Entry: EVENT_COUNTER_ZERO.
1234	* In accordance with the AMD spec.
1235	*/
1236	typedef union
1237	{
1238	struct
1239	{
1240	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1241	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1242	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1243	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
1244	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
1245	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
1246	} n;
1247	/** The 32-bit unsigned integer view. */
1248	uint32_t au32[4];
1249	} EVT_EVENT_COUNTER_ZERO_T;
1250	AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1251
1252	/**
1253	* IOMMU Capability Header (PCI).
1254	* In accordance with the AMD spec.
1255	*/
1256	typedef union
1257	{
1258	struct
1259	{
1260	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
1261	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
1262	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
1263	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
1264	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
1265	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
1266	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
1267	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
1268	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
1269	uint32_t u3Rsvd0 : 3; /*< Bits 31:29 - Reserved. /
1270	} n;
1271	/** The 32-bit unsigned integer view. */
1272	uint32_t u32;
1273	} IOMMU_CAP_HDR_T;
1274	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1275
1276	/**
1277	* IOMMU Base Address (Lo and Hi) Register (PCI).
1278	* In accordance with the AMD spec.
1279	*/
1280	typedef union
1281	{
1282	struct
1283	{
1284	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1285	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1286	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1287	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1288	} n;
1289	/** The 32-bit unsigned integer view. */
1290	uint32_t au32[2];
1291	/** The 64-bit unsigned integer view. */
1292	uint64_t u64;
1293	} IOMMU_BAR_T;
1294	AssertCompileSize(IOMMU_BAR_T, 8);
1295	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1296
1297	/**
1298	* IOMMU Range Register (PCI).
1299	* In accordance with the AMD spec.
1300	*/
1301	typedef union
1302	{
1303	struct
1304	{
1305	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1306	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1307	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1308	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1309	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1310	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1311	} n;
1312	/** The 32-bit unsigned integer view. */
1313	uint32_t u32;
1314	} IOMMU_RANGE_T;
1315	AssertCompileSize(IOMMU_RANGE_T, 4);
1316
1317	/**
1318	* Device Table Base Address Register (MMIO).
1319	* In accordance with the AMD spec.
1320	*/
1321	typedef union
1322	{
1323	struct
1324	{
1325	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1326	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1327	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1328	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1329	} n;
1330	/** The 64-bit unsigned integer view. */
1331	uint64_t u64;
1332	} DEV_TAB_BAR_T;
1333	AssertCompileSize(DEV_TAB_BAR_T, 8);
1334	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1335	#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1336
1337	/**
1338	* Command Buffer Base Address Register (MMIO).
1339	* In accordance with the AMD spec.
1340	*/
1341	typedef union
1342	{
1343	struct
1344	{
1345	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1346	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1347	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1348	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1349	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1350	} n;
1351	/** The 64-bit unsigned integer view. */
1352	uint64_t u64;
1353	} CMD_BUF_BAR_T;
1354	AssertCompileSize(CMD_BUF_BAR_T, 8);
1355	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1356
1357	/**
1358	* Event Log Base Address Register (MMIO).
1359	* In accordance with the AMD spec.
1360	*/
1361	typedef union
1362	{
1363	struct
1364	{
1365	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1366	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1367	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1368	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - EventLen: Event log length. /
1369	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1370	} n;
1371	/** The 64-bit unsigned integer view. */
1372	uint64_t u64;
1373	} EVT_LOG_BAR_T;
1374	AssertCompileSize(EVT_LOG_BAR_T, 8);
1375	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1376
1377	/**
1378	* IOMMU Control Register (MMIO).
1379	* In accordance with the AMD spec.
1380	*/
1381	typedef union
1382	{
1383	struct
1384	{
1385	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1386	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1387	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1388	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1389	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1390	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1391	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1392	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1393	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1394	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1395	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1396	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1397	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1398	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1399	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1400	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1401	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1402	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1403	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1404	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1405	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1406	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1407	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1408	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1409	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1410	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1411	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1412	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1413	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1414	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1415	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1416	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1417	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1418	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1419	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1420	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1421	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1422	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1423	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1424	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1425	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1426	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1427	} n;
1428	/** The 64-bit unsigned integer view. */
1429	uint64_t u64;
1430	} IOMMU_CTRL_T;
1431	AssertCompileSize(IOMMU_CTRL_T, 8);
1432	#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1433	#define IOMMU_CTRL_CMD_BUF_EN_MASK UINT64_C(0x0000000000001001)
1434
1435	/**
1436	* IOMMU Exclusion Base Register (MMIO).
1437	* In accordance with the AMD spec.
1438	*/
1439	typedef union
1440	{
1441	struct
1442	{
1443	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1444	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1445	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1446	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1447	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1448	} n;
1449	/** The 64-bit unsigned integer view. */
1450	uint64_t u64;
1451	} IOMMU_EXCL_RANGE_BAR_T;
1452	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1453	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1454
1455	/**
1456	* IOMMU Exclusion Range Limit Register (MMIO).
1457	* In accordance with the AMD spec.
1458	*/
1459	typedef union
1460	{
1461	struct
1462	{
1463	RT_GCC_EXTENSION uint64_t u52ExclLimit : 52; /*< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). /
1464	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1465	} n;
1466	/** The 64-bit unsigned integer view. */
1467	uint64_t u64;
1468	} IOMMU_EXCL_RANGE_LIMIT_T;
1469	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1470	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1471
1472	/**
1473	* IOMMU Extended Feature Register (MMIO).
1474	* In accordance with the AMD spec.
1475	*/
1476	typedef union
1477	{
1478	struct
1479	{
1480	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1481	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1482	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1483	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1484	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations (for GVAs) Support. /
1485	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1486	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1487	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1488	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1489	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1490	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1491	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1492	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1493	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1494	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1495	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1496	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1497	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1498	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1499	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1500	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1501	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1502	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1503	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1504	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1505	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1506	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1507	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1508	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1509	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1510	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1511	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1512	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1513	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1514	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1515	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1516	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1517	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1518	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1519	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1520	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1521	} n;
1522	/** The 64-bit unsigned integer view. */
1523	uint64_t u64;
1524	} IOMMU_EXT_FEAT_T;
1525	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1526
1527	/**
1528	* Peripheral Page Request Log Base Address Register (MMIO).
1529	* In accordance with the AMD spec.
1530	*/
1531	typedef union
1532	{
1533	struct
1534	{
1535	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1536	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1537	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1538	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1539	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1540	} n;
1541	/** The 64-bit unsigned integer view. */
1542	uint64_t u64;
1543	} PPR_LOG_BAR_T;
1544	AssertCompileSize(PPR_LOG_BAR_T, 8);
1545	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1546
1547	/**
1548	* IOMMU Hardware Event Upper Register (MMIO).
1549	* In accordance with the AMD spec.
1550	*/
1551	typedef union
1552	{
1553	struct
1554	{
1555	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1556	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1557	} n;
1558	/** The 64-bit unsigned integer view. */
1559	uint64_t u64;
1560	} IOMMU_HW_EVT_HI_T;
1561	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1562
1563	/**
1564	* IOMMU Hardware Event Lower Register (MMIO).
1565	* In accordance with the AMD spec.
1566	*/
1567	typedef uint64_t IOMMU_HW_EVT_LO_T;
1568
1569	/**
1570	* IOMMU Hardware Event Status (MMIO).
1571	* In accordance with the AMD spec.
1572	*/
1573	typedef union
1574	{
1575	struct
1576	{
1577	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1578	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1579	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1580	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1581	} n;
1582	/** The 64-bit unsigned integer view. */
1583	uint64_t u64;
1584	} IOMMU_HW_EVT_STATUS_T;
1585	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1586	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1587
1588	/**
1589	* Guest Virtual-APIC Log Base Address Register (MMIO).
1590	* In accordance with the AMD spec.
1591	*/
1592	typedef union
1593	{
1594	struct
1595	{
1596	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1597	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1598	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1599	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1600	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1601	} n;
1602	/** The 64-bit unsigned integer view. */
1603	uint64_t u64;
1604	} GALOG_BAR_T;
1605	AssertCompileSize(GALOG_BAR_T, 8);
1606
1607	/**
1608	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1609	* In accordance with the AMD spec.
1610	*/
1611	typedef union
1612	{
1613	struct
1614	{
1615	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1616	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1617	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1618	} n;
1619	/** The 64-bit unsigned integer view. */
1620	uint64_t u64;
1621	} GALOG_TAIL_ADDR_T;
1622	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1623
1624	/**
1625	* PPR Log B Base Address Register (MMIO).
1626	* In accordance with the AMD spec.
1627	* Currently identical to PPR_LOG_BAR_T.
1628	*/
1629	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1630
1631	/**
1632	* Event Log B Base Address Register (MMIO).
1633	* In accordance with the AMD spec.
1634	* Currently identical to EVT_LOG_BAR_T.
1635	*/
1636	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1637
1638	/**
1639	* Device-specific Feature Extension (DSFX) Register (MMIO).
1640	* In accordance with the AMD spec.
1641	*/
1642	typedef union
1643	{
1644	struct
1645	{
1646	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1647	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1648	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1649	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1650	} n;
1651	/** The 64-bit unsigned integer view. */
1652	uint64_t u64;
1653	} DEV_SPECIFIC_FEAT_T;
1654	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1655
1656	/**
1657	* Device-specific Control Extension (DSCX) Register (MMIO).
1658	* In accordance with the AMD spec.
1659	*/
1660	typedef union
1661	{
1662	struct
1663	{
1664	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1665	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1666	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1667	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1668	} n;
1669	/** The 64-bit unsigned integer view. */
1670	uint64_t u64;
1671	} DEV_SPECIFIC_CTRL_T;
1672	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1673
1674	/**
1675	* Device-specific Status Extension (DSSX) Register (MMIO).
1676	* In accordance with the AMD spec.
1677	*/
1678	typedef union
1679	{
1680	struct
1681	{
1682	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1683	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1684	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1685	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1686	} n;
1687	/** The 64-bit unsigned integer view. */
1688	uint64_t u64;
1689	} DEV_SPECIFIC_STATUS_T;
1690	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1691
1692	/**
1693	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1694	* In accordance with the AMD spec.
1695	*/
1696	typedef union
1697	{
1698	struct
1699	{
1700	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1701	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1702	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1703	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1704	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1705	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1706	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1707	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1708	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1709	} n;
1710	/** The 32-bit unsigned integer view. */
1711	uint32_t au32[2];
1712	/** The 64-bit unsigned integer view. */
1713	uint64_t u64;
1714	} MSI_MISC_INFO_T;
1715	AssertCompileSize(MSI_MISC_INFO_T, 8);
1716	/** MSI Vector Register 0 and 1 (MMIO). */
1717	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1718
1719	/**
1720	* MSI Capability Header Register (PCI + MMIO).
1721	* In accordance with the AMD spec.
1722	*/
1723	typedef union
1724	{
1725	struct
1726	{
1727	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1728	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1729	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1730	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1731	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1732	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1733	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1734	} n;
1735	/** The 32-bit unsigned integer view. */
1736	uint32_t u32;
1737	} MSI_CAP_HDR_T;
1738	AssertCompileSize(MSI_CAP_HDR_T, 4);
1739	#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1740
1741	/**
1742	* MSI Mapping Capability Header Register (PCI + MMIO).
1743	* In accordance with the AMD spec.
1744	*/
1745	typedef union
1746	{
1747	struct
1748	{
1749	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1750	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1751	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1752	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1753	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1754	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1755	} n;
1756	/** The 32-bit unsigned integer view. */
1757	uint32_t u32;
1758	} MSI_MAP_CAP_HDR_T;
1759	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1760
1761	/**
1762	* Performance Optimization Control Register (MMIO).
1763	* In accordance with the AMD spec.
1764	*/
1765	typedef union
1766	{
1767	struct
1768	{
1769	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1770	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1771	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1772	} n;
1773	/** The 32-bit unsigned integer view. */
1774	uint32_t u32;
1775	} IOMMU_PERF_OPT_CTRL_T;
1776	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1777
1778	/**
1779	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1780	* In accordance with the AMD spec.
1781	*/
1782	typedef union
1783	{
1784	struct
1785	{
1786	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1787	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1788	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1789	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1790	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1791	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1792	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1793	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1794	} n;
1795	/** The 64-bit unsigned integer view. */
1796	uint64_t u64;
1797	} IOMMU_XT_GEN_INTR_CTRL_T;
1798	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1799
1800	/**
1801	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1802	* In accordance with the AMD spec.
1803	*/
1804	typedef union
1805	{
1806	struct
1807	{
1808	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1809	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1810	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1811	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1812	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1813	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1814	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1815	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1816	} n;
1817	/** The 64-bit unsigned integer view. */
1818	uint64_t u64;
1819	} IOMMU_XT_INTR_CTRL_T;
1820	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1821
1822	/**
1823	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1824	* In accordance with the AMD spec.
1825	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1826	*/
1827	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1828
1829	/**
1830	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1831	* In accordance with the AMD spec.
1832	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1833	*/
1834	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1835
1836	/**
1837	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1838	* In accordance with the AMD spec.
1839	*/
1840	typedef union
1841	{
1842	struct
1843	{
1844	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1845	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1846	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1847	} n;
1848	/** The 64-bit unsigned integer view. */
1849	uint64_t u64;
1850	} MARC_APER_BAR_T;
1851	AssertCompileSize(MARC_APER_BAR_T, 8);
1852
1853	/**
1854	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1855	* In accordance with the AMD spec.
1856	*/
1857	typedef union
1858	{
1859	struct
1860	{
1861	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1862	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1863	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1864	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1865	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1866	} n;
1867	/** The 64-bit unsigned integer view. */
1868	uint64_t u64;
1869	} MARC_APER_RELOC_T;
1870	AssertCompileSize(MARC_APER_RELOC_T, 8);
1871
1872	/**
1873	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1874	* In accordance with the AMD spec.
1875	*/
1876	typedef union
1877	{
1878	struct
1879	{
1880	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1881	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1882	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1883	} n;
1884	/** The 64-bit unsigned integer view. */
1885	uint64_t u64;
1886	} MARC_APER_LEN_T;
1887
1888	/**
1889	* Memory Access and Routing Control (MARC) Aperture Register.
1890	* This combines other registers to match the MMIO layout for convenient access.
1891	*/
1892	typedef struct
1893	{
1894	MARC_APER_BAR_T Base;
1895	MARC_APER_RELOC_T Reloc;
1896	MARC_APER_LEN_T Length;
1897	} MARC_APER_T;
1898	AssertCompileSize(MARC_APER_T, 24);
1899
1900	/**
1901	* IOMMU Reserved Register (MMIO).
1902	* In accordance with the AMD spec.
1903	* This register is reserved for hardware use (although RW?).
1904	*/
1905	typedef uint64_t IOMMU_RSVD_REG_T;
1906
1907	/**
1908	* Command Buffer Head Pointer Register (MMIO).
1909	* In accordance with the AMD spec.
1910	*/
1911	typedef union
1912	{
1913	struct
1914	{
1915	uint32_t off; /*< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). /
1916	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1917	} n;
1918	/** The 32-bit unsigned integer view. */
1919	uint32_t au32[2];
1920	/** The 64-bit unsigned integer view. */
1921	uint64_t u64;
1922	} CMD_BUF_HEAD_PTR_T;
1923	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1924	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1925
1926	/**
1927	* Command Buffer Tail Pointer Register (MMIO).
1928	* In accordance with the AMD spec.
1929	* Currently identical to CMD_BUF_HEAD_PTR_T.
1930	*/
1931	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1932	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1933
1934	/**
1935	* Event Log Head Pointer Register (MMIO).
1936	* In accordance with the AMD spec.
1937	* Currently identical to CMD_BUF_HEAD_PTR_T.
1938	*/
1939	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1940	#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1941
1942	/**
1943	* Event Log Tail Pointer Register (MMIO).
1944	* In accordance with the AMD spec.
1945	* Currently identical to CMD_BUF_HEAD_PTR_T.
1946	*/
1947	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1948	#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1949
1950
1951	/**
1952	* IOMMU Status Register (MMIO).
1953	* In accordance with the AMD spec.
1954	*/
1955	typedef union
1956	{
1957	struct
1958	{
1959	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
1960	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
1961	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
1962	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
1963	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
1964	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
1965	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
1966	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
1967	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
1968	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
1969	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
1970	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
1971	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
1972	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
1973	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
1974	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
1975	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
1976	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
1977	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1978	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
1979	} n;
1980	/** The 32-bit unsigned integer view. */
1981	uint32_t au32[2];
1982	/** The 64-bit unsigned integer view. */
1983	uint64_t u64;
1984	} IOMMU_STATUS_T;
1985	AssertCompileSize(IOMMU_STATUS_T, 8);
1986	#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
1987	#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
1988
1989	/**
1990	* PPR Log Head Pointer Register (MMIO).
1991	* In accordance with the AMD spec.
1992	* Currently identical to CMD_BUF_HEAD_PTR_T.
1993	*/
1994	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
1995
1996	/**
1997	* PPR Log Tail Pointer Register (MMIO).
1998	* In accordance with the AMD spec.
1999	* Currently identical to CMD_BUF_HEAD_PTR_T.
2000	*/
2001	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
2002
2003	/**
2004	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
2005	* In accordance with the AMD spec.
2006	*/
2007	typedef union
2008	{
2009	struct
2010	{
2011	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
2012	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
2013	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
2014	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2015	} n;
2016	/** The 32-bit unsigned integer view. */
2017	uint32_t au32[2];
2018	/** The 64-bit unsigned integer view. */
2019	uint64_t u64;
2020	} GALOG_HEAD_PTR_T;
2021	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
2022
2023	/**
2024	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
2025	* In accordance with the AMD spec.
2026	* Currently identical to GALOG_HEAD_PTR_T.
2027	*/
2028	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
2029
2030	/**
2031	* PPR Log B Head Pointer Register (MMIO).
2032	* In accordance with the AMD spec.
2033	* Currently identical to CMD_BUF_HEAD_PTR_T.
2034	*/
2035	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
2036
2037	/**
2038	* PPR Log B Tail Pointer Register (MMIO).
2039	* In accordance with the AMD spec.
2040	* Currently identical to CMD_BUF_HEAD_PTR_T.
2041	*/
2042	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
2043
2044	/**
2045	* Event Log B Head Pointer Register (MMIO).
2046	* In accordance with the AMD spec.
2047	* Currently identical to CMD_BUF_HEAD_PTR_T.
2048	*/
2049	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
2050
2051	/**
2052	* Event Log B Tail Pointer Register (MMIO).
2053	* In accordance with the AMD spec.
2054	* Currently identical to CMD_BUF_HEAD_PTR_T.
2055	*/
2056	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
2057
2058	/**
2059	* PPR Log Auto Response Register (MMIO).
2060	* In accordance with the AMD spec.
2061	*/
2062	typedef union
2063	{
2064	struct
2065	{
2066	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
2067	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
2068	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
2069	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
2070	} n;
2071	/** The 32-bit unsigned integer view. */
2072	uint32_t au32[2];
2073	/** The 64-bit unsigned integer view. */
2074	uint64_t u64;
2075	} PPR_LOG_AUTO_RESP_T;
2076	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
2077
2078	/**
2079	* PPR Log Overflow Early Indicator Register (MMIO).
2080	* In accordance with the AMD spec.
2081	*/
2082	typedef union
2083	{
2084	struct
2085	{
2086	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
2087	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
2088	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
2089	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
2090	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2091	} n;
2092	/** The 32-bit unsigned integer view. */
2093	uint32_t au32[2];
2094	/** The 64-bit unsigned integer view. */
2095	uint64_t u64;
2096	} PPR_LOG_OVERFLOW_EARLY_T;
2097	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2098
2099	/**
2100	* PPR Log B Overflow Early Indicator Register (MMIO).
2101	* In accordance with the AMD spec.
2102	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2103	*/
2104	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2105
2106	/**
2107	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2108	* In accordance with the AMD spec.
2109	*/
2110	typedef enum EVT_ILLEGAL_DTE_TYPE_T
2111	{
2112	kIllegalDteType_RsvdNotZero = 0,
2113	kIllegalDteType_RsvdIntTabLen,
2114	kIllegalDteType_RsvdIoCtl,
2115	kIllegalDteType_RsvdIntCtl
2116	} EVT_ILLEGAL_DTE_TYPE_T;
2117
2118	/**
2119	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2120	* In accordance with the AMD spec.
2121	*/
2122	typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2123	{
2124	/* Memory transaction. */
2125	kIoPageFaultType_DteRsvdPagingMode = 0,
2126	kIoPageFaultType_PteInvalidPageSize,
2127	kIoPageFaultType_PteInvalidLvlEncoding,
2128	kIoPageFaultType_SkippedLevelIovaNotZero,
2129	kIoPageFaultType_PteRsvdNotZero,
2130	kIoPageFaultType_PteValidNotSet,
2131	kIoPageFaultType_DteTranslationDisabled,
2132	kIoPageFaultType_PasidInvalidRange,
2133	kIoPageFaultType_PermDenied,
2134	kIoPageFaultType_UserSupervisor,
2135	/* Interrupt remapping */
2136	kIoPageFaultType_IrteAddrInvalid,
2137	kIoPageFaultType_IrteRsvdNotZero,
2138	kIoPageFaultType_IrteRemapEn,
2139	kIoPageFaultType_IrteRsvdIntType,
2140	kIoPageFaultType_IntrReqAborted,
2141	kIoPageFaultType_IntrWithPasid,
2142	kIoPageFaultType_SmiFilterMismatch,
2143	/* Memory transaction or interrupt remapping. */
2144	kIoPageFaultType_DevId_Invalid
2145	} EVT_IO_PAGE_FAULT_TYPE_T;
2146
2147	/**
2148	* IOTLB_INV_TIMEOUT Event Types.
2149	* In accordance with the AMD spec.
2150	*/
2151	typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2152	{
2153	InvTimeoutType_NoResponse = 0
2154	} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2155
2156	/**
2157	* INVALID_DEVICE_REQUEST Event Types.
2158	* In accordance with the AMD spec.
2159	*/
2160	typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2161	{
2162	/* Access. */
2163	kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2164	kInvalidDevReqType_PretranslatedTransaction,
2165	kInvalidDevReqType_PortIo,
2166	kInvalidDevReqType_SysMgt,
2167	kInvalidDevReqType_IntrRange,
2168	kInvalidDevReqType_RsvdIntrRange,
2169	kInvalidDevReqType_SysMgtAddr,
2170	/* Translation Request. */
2171	kInvalidDevReqType_TrAccessInvalid,
2172	kInvalidDevReqType_TrDisabled,
2173	kInvalidDevReqType_DevIdInvalid,
2174	} EVT_INVALID_DEV_REQ_TYPE_T;
2175
2176	/**
2177	* INVALID_PPR_REQUEST Event Types.
2178	* In accordance with the AMD spec.
2179	*/
2180	typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2181	{
2182	kInvalidPprReqType_PriNotSupported,
2183	kInvalidPprReqType_GstTranslateDisabled
2184	} EVT_INVALID_PPR_REQ_TYPE_T;
2185
2186	/**
2187	* IOMMU operations (transaction) types.
2188	*/
2189	typedef enum IOMMUOP
2190	{
2191	/** Address translation request. */
2192	IOMMUOP_TRANSLATE_REQ = 0,
2193	/** Memory read request. */
2194	IOMMUOP_MEM_READ,
2195	/** Memory write request. */
2196	IOMMUOP_MEM_WRITE,
2197	/** Interrupt request. */
2198	IOMMUOP_INTR_REQ,
2199	/** Command. */
2200	IOMMUOP_CMD
2201	} IOMMUOP;
2202	AssertCompileSize(IOMMUOP, 4);
2203
2204	/**
2205	* I/O page walk result.
2206	*/
2207	typedef struct
2208	{
2209	/** The translated system physical address. */
2210	RTGCPHYS GCPhysSpa;
2211	/** The number of offset bits in the system physical address. */
2212	uint8_t cShift;
2213	/** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
2214	uint8_t fIoPerm;
2215	/** Padding. */
2216	uint8_t abPadding[2];
2217	} IOWALKRESULT;
2218	/** Pointer to an I/O walk result struct. */
2219	typedef IOWALKRESULT *PIOWALKRESULT;
2220	/** Pointer to a const I/O walk result struct. */
2221	typedef IOWALKRESULT *PCIOWALKRESULT;
2222
2223	/**
2224	* IOMMU I/O TLB Entry.
2225	* Keep this as small and aligned as possible.
2226	*/
2227	typedef struct
2228	{
2229	/** The translated system physical address (SPA) of the page. */
2230	RTGCPHYS GCPhysSpa;
2231	/** The index of the 4K page within a large page. */
2232	uint32_t idxSubPage;
2233	/** The I/O access permissions (IOMMU_IO_PERM_XXX). */
2234	uint8_t fIoPerm;
2235	/** The number of offset bits in the translation indicating page size. */
2236	uint8_t cShift;
2237	/** Alignment padding. */
2238	uint8_t afPadding[2];
2239	} IOTLBE_T;
2240	AssertCompileSize(IOTLBE_T, 16);
2241	/** Pointer to an IOMMU I/O TLB entry struct. */
2242	typedef IOTLBE_T *PIOTLBE_T;
2243	/** Pointer to a const IOMMU I/O TLB entry struct. */
2244	typedef IOTLBE_T const *PCIOTLBE_T;
2245
2246	/**
2247	* The shared IOMMU device state.
2248	*/
2249	typedef struct IOMMU
2250	{
2251	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
2252	uint32_t idxIommu;
2253	/** Alignment padding. */
2254	uint32_t uPadding0;
2255
2256	/** Whether the command thread is sleeping. */
2257	bool volatile fCmdThreadSleeping;
2258	/** Alignment padding. */
2259	uint8_t afPadding0[3];
2260	/** Whether the command thread has been signaled for wake up. */
2261	bool volatile fCmdThreadSignaled;
2262	/** Alignment padding. */
2263	uint8_t afPadding1[3];
2264
2265	/** The event semaphore the command thread waits on. */
2266	SUPSEMEVENT hEvtCmdThread;
2267	/** The MMIO handle. */
2268	IOMMMIOHANDLE hMmio;
2269
2270	/** @name PCI: Base capability block registers.
2271	* @{ */
2272	IOMMU_BAR_T IommuBar; /*< IOMMU base address register. /
2273	/** @} */
2274
2275	/** @name MMIO: Control and status registers.
2276	* @{ */
2277	DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /*< Device table base address registers. /
2278	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
2279	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
2280	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
2281	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
2282	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
2283	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
2284	/** @} */
2285
2286	/** @name MMIO: PPR Log registers.
2287	* @{ */
2288	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
2289	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
2290	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
2291	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
2292	/** @} */
2293
2294	/** @todo IOMMU: SMI filter. */
2295
2296	/** @name MMIO: Guest Virtual-APIC Log registers.
2297	* @{ */
2298	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
2299	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
2300	/** @} */
2301
2302	/** @name MMIO: Alternate PPR and Event Log registers.
2303	* @{ */
2304	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
2305	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
2306	/** @} */
2307
2308	/** @name MMIO: Device-specific feature registers.
2309	* @{ */
2310	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
2311	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
2312	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
2313	/** @} */
2314
2315	/** @name MMIO: MSI Capability Block registers.
2316	* @{ */
2317	MSI_MISC_INFO_T MsiMiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
2318	/** @} */
2319
2320	/** @name MMIO: Performance Optimization Control registers.
2321	* @{ */
2322	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
2323	/** @} */
2324
2325	/** @name MMIO: x2APIC Control registers.
2326	* @{ */
2327	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
2328	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
2329	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
2330	/** @} */
2331
2332	/** @name MMIO: MARC registers.
2333	* @{ */
2334	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
2335	/** @} */
2336
2337	/** @name MMIO: Reserved register.
2338	* @{ */
2339	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
2340	/** @} */
2341
2342	/** @name MMIO: Command and Event Log pointer registers.
2343	* @{ */
2344	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
2345	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
2346	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
2347	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
2348	/** @} */
2349
2350	/** @name MMIO: Command and Event Status register.
2351	* @{ */
2352	IOMMU_STATUS_T Status; /*< IOMMU status register. /
2353	/** @} */
2354
2355	/** @name MMIO: PPR Log Head and Tail pointer registers.
2356	* @{ */
2357	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
2358	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
2359	/** @} */
2360
2361	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
2362	* @{ */
2363	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
2364	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
2365	/** @} */
2366
2367	/** @name MMIO: PPR Log B Head and Tail pointer registers.
2368	* @{ */
2369	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
2370	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
2371	/** @} */
2372
2373	/** @name MMIO: Event Log B Head and Tail pointer registers.
2374	* @{ */
2375	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
2376	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
2377	/** @} */
2378
2379	/** @name MMIO: PPR Log Overflow protection registers.
2380	* @{ */
2381	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
2382	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
2383	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
2384	/** @} */
2385
2386	/** @todo IOMMU: IOMMU Event counter registers. */
2387
2388	/** @todo IOMMU: Stat counters. */
2389	} IOMMU;
2390	/** Pointer to the IOMMU device state. */
2391	typedef struct IOMMU *PIOMMU;
2392	/** Pointer to the const IOMMU device state. */
2393	typedef const struct IOMMU *PCIOMMU;
2394	AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
2395	AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
2396	AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
2397	AssertCompileMemberAlignment(IOMMU, hMmio, 8);
2398	AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
2399
2400	/**
2401	* The ring-3 IOMMU device state.
2402	*/
2403	typedef struct IOMMUR3
2404	{
2405	/** Device instance. */
2406	PPDMDEVINSR3 pDevInsR3;
2407	/** The IOMMU helpers. */
2408	PCPDMIOMMUHLPR3 pIommuHlpR3;
2409	/** The command thread handle. */
2410	R3PTRTYPE(PPDMTHREAD) pCmdThread;
2411	} IOMMUR3;
2412	/** Pointer to the ring-3 IOMMU device state. */
2413	typedef IOMMUR3 *PIOMMUR3;
2414
2415	/**
2416	* The ring-0 IOMMU device state.
2417	*/
2418	typedef struct IOMMUR0
2419	{
2420	/** Device instance. */
2421	PPDMDEVINSR0 pDevInsR0;
2422	/** The IOMMU helpers. */
2423	PCPDMIOMMUHLPR0 pIommuHlpR0;
2424	} IOMMUR0;
2425	/** Pointer to the ring-0 IOMMU device state. */
2426	typedef IOMMUR0 *PIOMMUR0;
2427
2428	/**
2429	* The raw-mode IOMMU device state.
2430	*/
2431	typedef struct IOMMURC
2432	{
2433	/** Device instance. */
2434	PPDMDEVINSR0 pDevInsRC;
2435	/** The IOMMU helpers. */
2436	PCPDMIOMMUHLPRC pIommuHlpRC;
2437	} IOMMURC;
2438	/** Pointer to the raw-mode IOMMU device state. */
2439	typedef IOMMURC *PIOMMURC;
2440
2441	/** The IOMMU device state for the current context. */
2442	typedef CTX_SUFF(IOMMU) IOMMUCC;
2443	/** Pointer to the IOMMU device state for the current context. */
2444	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
2445
2446	/**
2447	* IOMMU register access routines.
2448	*/
2449	typedef struct
2450	{
2451	const char *pszName;
2452	VBOXSTRICTRC (pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t pu64Value);
2453	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
2454	bool f64BitReg;
2455	} IOMMUREGACC;
2456
2457
2458	/*********************************************************************************************************************************
2459	* Global Variables *
2460	*********************************************************************************************************************************/
2461	/**
2462	* An array of the number of device table segments supported.
2463	* Indexed by u2DevTabSegSup.
2464	*/
2465	static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
2466
2467	/**
2468	* An array of the masks to select the device table segment index from a device ID.
2469	*/
2470	static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
2471
2472	/**
2473	* The maximum size (inclusive) of each device table segment (0 to 7).
2474	* Indexed by the device table segment index.
2475	*/
2476	static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
2477
2478
2479	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
2480	/**
2481	* Gets the maximum number of buffer entries for the given buffer length.
2482	*
2483	* @returns Number of buffer entries.
2484	* @param uEncodedLen The length (power-of-2 encoded).
2485	*/
2486	DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
2487	{
2488	Assert(uEncodedLen > 7);
2489	return 2 << (uEncodedLen - 1);
2490	}
2491
2492
2493	/**
2494	* Gets the total length of the buffer given a base register's encoded length.
2495	*
2496	* @returns The length of the buffer in bytes.
2497	* @param uEncodedLen The length (power-of-2 encoded).
2498	*/
2499	DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
2500	{
2501	Assert(uEncodedLen > 7);
2502	return (2 << (uEncodedLen - 1)) << 4;
2503	}
2504
2505
2506	/**
2507	* Gets the number of (unconsumed) entries in the event log.
2508	*
2509	* @returns The number of entries in the event log.
2510	* @param pThis The IOMMU device state.
2511	*/
2512	static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
2513	{
2514	uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2515	uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2516	if (idxTail >= idxHead)
2517	return idxTail - idxHead;
2518
2519	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2520	return cMaxEvts - idxHead + idxTail;
2521	}
2522
2523
2524	/**
2525	* Gets the number of (unconsumed) commands in the command buffer.
2526	*
2527	* @returns The number of commands in the command buffer.
2528	* @param pThis The IOMMU device state.
2529	*/
2530	static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
2531	{
2532	uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2533	uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2534	if (idxTail >= idxHead)
2535	return idxTail - idxHead;
2536
2537	uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
2538	return cMaxCmds - idxHead + idxTail;
2539	}
2540
2541
2542	DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
2543	{
2544	IOMMU_STATUS_T Status;
2545	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
2546	return Status;
2547	}
2548
2549
2550	DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
2551	{
2552	IOMMU_CTRL_T Ctrl;
2553	Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
2554	return Ctrl;
2555	}
2556
2557
2558	/**
2559	* Returns whether MSI is enabled for the IOMMU.
2560	*
2561	* @returns Whether MSI is enabled.
2562	* @param pDevIns The IOMMU device instance.
2563	*
2564	* @note There should be a PCIDevXxx function for this.
2565	*/
2566	static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
2567	{
2568	MSI_CAP_HDR_T MsiCapHdr;
2569	MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
2570	return MsiCapHdr.n.u1MsiEnable;
2571	}
2572
2573
2574	/**
2575	* Signals a PCI target abort.
2576	*
2577	* @param pDevIns The IOMMU device instance.
2578	*/
2579	static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
2580	{
2581	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2582	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2583	PDMPciDevSetStatus(pPciDev, u16Status);
2584	}
2585
2586
2587	/**
2588	* Wakes up the command thread if there are commands to be processed or if
2589	* processing is requested to be stopped by software.
2590	*
2591	* @param pDevIns The IOMMU device instance.
2592	*/
2593	static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
2594	{
2595	IOMMU_ASSERT_LOCKED(pDevIns);
2596
2597	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2598	if ( !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true)
2599	&& ASMAtomicReadBool(&pThis->fCmdThreadSleeping))
2600	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2601	}
2602
2603
2604	/**
2605	* Writes to a read-only register.
2606	*/
2607	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2608	{
2609	RT_NOREF(pDevIns, pThis, iReg, u64Value);
2610	Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
2611	return VINF_SUCCESS;
2612	}
2613
2614
2615	/**
2616	* Writes the Device Table Base Address Register.
2617	*/
2618	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2619	{
2620	RT_NOREF(pDevIns, iReg);
2621
2622	/* Mask out all unrecognized bits. */
2623	u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2624
2625	/* Update the register. */
2626	pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2627	return VINF_SUCCESS;
2628	}
2629
2630
2631	/**
2632	* Writes the Command Buffer Base Address Register.
2633	*/
2634	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2635	{
2636	RT_NOREF(pDevIns, iReg);
2637
2638	/*
2639	* While this is not explicitly specified like the event log base address register,
2640	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2641	* Inconsistent specs :/
2642	*/
2643	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2644	if (Status.n.u1CmdBufRunning)
2645	{
2646	Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2647	return VINF_SUCCESS;
2648	}
2649
2650	/* Mask out all unrecognized bits. */
2651	CMD_BUF_BAR_T CmdBufBaseAddr;
2652	CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2653
2654	/* Validate the length. */
2655	if (CmdBufBaseAddr.n.u4Len >= 8)
2656	{
2657	/* Update the register. */
2658	pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2659
2660	/*
2661	* Writing the command buffer base address, clears the command buffer head and tail pointers.
2662	* See AMD spec. 2.4 "Commands".
2663	*/
2664	pThis->CmdBufHeadPtr.u64 = 0;
2665	pThis->CmdBufTailPtr.u64 = 0;
2666	}
2667	else
2668	Log((IOMMU_LOG_PFX ": Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2669
2670	return VINF_SUCCESS;
2671	}
2672
2673
2674	/**
2675	* Writes the Event Log Base Address Register.
2676	*/
2677	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2678	{
2679	RT_NOREF(pDevIns, iReg);
2680
2681	/*
2682	* IOMMU behavior is undefined when software writes this register when event logging is running.
2683	* In our emulation, we ignore the write entirely.
2684	* See AMD IOMMU spec. "Event Log Base Address Register".
2685	*/
2686	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2687	if (Status.n.u1EvtLogRunning)
2688	{
2689	Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2690	return VINF_SUCCESS;
2691	}
2692
2693	/* Mask out all unrecognized bits. */
2694	u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2695	EVT_LOG_BAR_T EvtLogBaseAddr;
2696	EvtLogBaseAddr.u64 = u64Value;
2697
2698	/* Validate the length. */
2699	if (EvtLogBaseAddr.n.u4Len >= 8)
2700	{
2701	/* Update the register. */
2702	pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2703
2704	/*
2705	* Writing the event log base address, clears the event log head and tail pointers.
2706	* See AMD spec. 2.5 "Event Logging".
2707	*/
2708	pThis->EvtLogHeadPtr.u64 = 0;
2709	pThis->EvtLogTailPtr.u64 = 0;
2710	}
2711	else
2712	Log((IOMMU_LOG_PFX ": Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2713
2714	return VINF_SUCCESS;
2715	}
2716
2717
2718	/**
2719	* Writes the Control Register.
2720	*/
2721	static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2722	{
2723	RT_NOREF(pDevIns, iReg);
2724
2725	/* Mask out all unrecognized bits. */
2726	u64Value &= IOMMU_CTRL_VALID_MASK;
2727
2728	IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
2729	IOMMU_CTRL_T NewCtrl;
2730	NewCtrl.u64 = u64Value;
2731
2732	/* Update the register. */
2733	ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2734
2735	/* Enable or disable event logging when the bit transitions. */
2736	bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2737	bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2738	bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2739	if (fOldEvtLogEn != fNewEvtLogEn)
2740	{
2741	if ( fNewIommuEn
2742	&& fNewEvtLogEn)
2743	{
2744	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2745	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2746	}
2747	else
2748	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2749	}
2750
2751	/* Enable or disable command buffer processing when the bit transitions. */
2752	bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2753	bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2754	if (fOldCmdBufEn != fNewCmdBufEn)
2755	{
2756	if ( fNewIommuEn
2757	&& fNewCmdBufEn)
2758	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2759	else
2760	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2761
2762	/* Wake up the command thread to start or stop processing commands. */
2763	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2764	}
2765	}
2766
2767
2768	/**
2769	* Writes to the Excluse Range Base Address Register.
2770	*/
2771	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2772	{
2773	RT_NOREF(pDevIns, iReg);
2774	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2775	return VINF_SUCCESS;
2776	}
2777
2778
2779	/**
2780	* Writes to the Excluse Range Limit Register.
2781	*/
2782	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2783	{
2784	RT_NOREF(pDevIns, iReg);
2785	u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2786	u64Value \|= UINT64_C(0xfff);
2787	pThis->ExclRangeLimit.u64 = u64Value;
2788	return VINF_SUCCESS;
2789	}
2790
2791
2792	/**
2793	* Writes the Hardware Event Register (Hi).
2794	*/
2795	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2796	{
2797	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2798	RT_NOREF(pDevIns, iReg);
2799	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2800	pThis->HwEvtHi.u64 = u64Value;
2801	return VINF_SUCCESS;
2802	}
2803
2804
2805	/**
2806	* Writes the Hardware Event Register (Lo).
2807	*/
2808	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2809	{
2810	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2811	RT_NOREF(pDevIns, iReg);
2812	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2813	pThis->HwEvtLo = u64Value;
2814	return VINF_SUCCESS;
2815	}
2816
2817
2818	/**
2819	* Writes the Hardware Event Status Register.
2820	*/
2821	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2822	{
2823	RT_NOREF(pDevIns, iReg);
2824
2825	/* Mask out all unrecognized bits. */
2826	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2827
2828	/*
2829	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2830	* If the current status bits or the bits being written are both 0, we've nothing to do.
2831	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2832	*/
2833	uint64_t HwStatus = pThis->HwEvtStatus.u64;
2834	if (!(HwStatus & RT_BIT(0)))
2835	return VINF_SUCCESS;
2836	if (u64Value & HwStatus & RT_BIT_64(0))
2837	HwStatus &= ~RT_BIT_64(0);
2838	if (u64Value & HwStatus & RT_BIT_64(1))
2839	HwStatus &= ~RT_BIT_64(1);
2840
2841	/* Update the register. */
2842	pThis->HwEvtStatus.u64 = HwStatus;
2843	return VINF_SUCCESS;
2844	}
2845
2846
2847	/**
2848	* Writes the Device Table Segment Base Address Register.
2849	*/
2850	static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2851	{
2852	RT_NOREF(pDevIns);
2853
2854	/* Figure out which segment is being written. */
2855	uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2856	uint8_t const idxSegment = offSegment + 1;
2857	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2858
2859	/* Mask out all unrecognized bits. */
2860	u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2861	DEV_TAB_BAR_T DevTabSegBar;
2862	DevTabSegBar.u64 = u64Value;
2863
2864	/* Validate the size. */
2865	uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2866	uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2867	if (uSegSize <= uMaxSegSize)
2868	{
2869	/* Update the register. */
2870	pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2871	}
2872	else
2873	Log((IOMMU_LOG_PFX ": Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2874
2875	return VINF_SUCCESS;
2876	}
2877
2878
2879	/**
2880	* Writes the MSI Capability Header Register.
2881	*/
2882	static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2883	{
2884	RT_NOREF(pThis, iReg);
2885	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2886	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2887	MSI_CAP_HDR_T MsiCapHdr;
2888	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2889	MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2890	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2891	return VINF_SUCCESS;
2892	}
2893
2894
2895	/**
2896	* Writes the MSI Address (Lo) Register (32-bit).
2897	*/
2898	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2899	{
2900	RT_NOREF(pThis, iReg);
2901	Assert(!RT_HI_U32(u64Value));
2902	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2903	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2904	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
2905	return VINF_SUCCESS;
2906	}
2907
2908
2909	/**
2910	* Writes the MSI Address (Hi) Register (32-bit).
2911	*/
2912	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2913	{
2914	RT_NOREF(pThis, iReg);
2915	Assert(!RT_HI_U32(u64Value));
2916	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2917	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2918	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
2919	return VINF_SUCCESS;
2920	}
2921
2922
2923	/**
2924	* Writes the MSI Data Register (32-bit).
2925	*/
2926	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2927	{
2928	RT_NOREF(pThis, iReg);
2929	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2930	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2931	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
2932	return VINF_SUCCESS;
2933	}
2934
2935
2936	/**
2937	* Writes the Command Buffer Head Pointer Register (32-bit).
2938	*/
2939	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2940	{
2941	RT_NOREF(pDevIns, iReg);
2942
2943	/*
2944	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
2945	* In our emulation, we ignore the write entirely.
2946	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2947	*/
2948	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2949	if (Status.n.u1CmdBufRunning)
2950	{
2951	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2952	return VINF_SUCCESS;
2953	}
2954
2955	/*
2956	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2957	* In our emulation, we ignore the write entirely.
2958	*/
2959	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2960	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2961	Assert(cbBuf <= _512K);
2962	if (offBuf >= cbBuf)
2963	{
2964	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
2965	offBuf, cbBuf));
2966	return VINF_SUCCESS;
2967	}
2968
2969	/* Update the register. */
2970	pThis->CmdBufHeadPtr.au32[0] = offBuf;
2971
2972	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2973
2974	LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
2975	return VINF_SUCCESS;
2976	}
2977
2978
2979	/**
2980	* Writes the Command Buffer Tail Pointer Register (32-bit).
2981	*/
2982	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2983	{
2984	RT_NOREF(pDevIns, iReg);
2985
2986	/*
2987	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2988	* In our emulation, we ignore the write entirely.
2989	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2990	*/
2991	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2992	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2993	Assert(cbBuf <= _512K);
2994	if (offBuf >= cbBuf)
2995	{
2996	Log((IOMMU_LOG_PFX ": Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
2997	offBuf, cbBuf));
2998	return VINF_SUCCESS;
2999	}
3000
3001	/*
3002	* IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
3003	* head pointer after adding one or more commands to the buffer.
3004	*
3005	* However, we cannot enforce this strictly because it's legal for software to shrink the
3006	* command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
3007	* at 0). Software might even make the queue empty by making head and tail equal which is
3008	* allowed. I don't think we can or should try too hard to prevent software shooting itself
3009	* in the foot here. As long as we make sure the offset value is within the circular buffer
3010	* bounds (which we do by masking bits above) it should be sufficient.
3011	*/
3012	pThis->CmdBufTailPtr.au32[0] = offBuf;
3013
3014	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
3015
3016	LogFlow((IOMMU_LOG_PFX ": Set CmdBufTailPtr to %#RX32\n", offBuf));
3017	return VINF_SUCCESS;
3018	}
3019
3020
3021	/**
3022	* Writes the Event Log Head Pointer Register (32-bit).
3023	*/
3024	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3025	{
3026	RT_NOREF(pDevIns, iReg);
3027
3028	/*
3029	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3030	* In our emulation, we ignore the write entirely.
3031	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3032	*/
3033	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
3034	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3035	Assert(cbBuf <= _512K);
3036	if (offBuf >= cbBuf)
3037	{
3038	Log((IOMMU_LOG_PFX ": Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3039	offBuf, cbBuf));
3040	return VINF_SUCCESS;
3041	}
3042
3043	/* Update the register. */
3044	pThis->EvtLogHeadPtr.au32[0] = offBuf;
3045
3046	LogFlow((IOMMU_LOG_PFX ": Set EvtLogHeadPtr to %#RX32\n", offBuf));
3047	return VINF_SUCCESS;
3048	}
3049
3050
3051	/**
3052	* Writes the Event Log Tail Pointer Register (32-bit).
3053	*/
3054	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3055	{
3056	RT_NOREF(pDevIns, iReg);
3057	NOREF(pThis);
3058
3059	/*
3060	* IOMMU behavior is undefined when software writes this register when the event log is running.
3061	* In our emulation, we ignore the write entirely.
3062	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3063	*/
3064	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3065	if (Status.n.u1EvtLogRunning)
3066	{
3067	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
3068	return VINF_SUCCESS;
3069	}
3070
3071	/*
3072	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3073	* In our emulation, we ignore the write entirely.
3074	*/
3075	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
3076	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3077	Assert(cbBuf <= _512K);
3078	if (offBuf >= cbBuf)
3079	{
3080	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3081	offBuf, cbBuf));
3082	return VINF_SUCCESS;
3083	}
3084
3085	/* Update the register. */
3086	pThis->EvtLogTailPtr.au32[0] = offBuf;
3087
3088	LogFlow((IOMMU_LOG_PFX ": Set EvtLogTailPtr to %#RX32\n", offBuf));
3089	return VINF_SUCCESS;
3090	}
3091
3092
3093	/**
3094	* Writes the Status Register (64-bit).
3095	*/
3096	static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3097	{
3098	RT_NOREF(pDevIns, iReg);
3099
3100	/* Mask out all unrecognized bits. */
3101	u64Value &= IOMMU_STATUS_VALID_MASK;
3102
3103	/*
3104	* Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
3105	* Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
3106	*/
3107	IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
3108	uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
3109	uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
3110	uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
3111
3112	uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) \| fOldRoBits;
3113
3114	/* Update the register. */
3115	ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
3116	return VINF_SUCCESS;
3117	}
3118
3119
3120	#if 0
3121	/**
3122	* Table 0: Registers-access table.
3123	*/
3124	static const IOMMUREGACC g_aTable0Regs[] =
3125	{
3126
3127	};
3128
3129	/**
3130	* Table 1: Registers-access table.
3131	*/
3132	static const IOMMUREGACC g_aTable1Regs[] =
3133	{
3134	};
3135	#endif
3136
3137
3138	/**
3139	* Writes an IOMMU register (32-bit and 64-bit).
3140	*
3141	* @returns Strict VBox status code.
3142	* @param pDevIns The IOMMU device instance.
3143	* @param off MMIO byte offset to the register.
3144	* @param cb The size of the write access.
3145	* @param uValue The value being written.
3146	*
3147	* @thread EMT.
3148	*/
3149	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
3150	{
3151	Assert(off < IOMMU_MMIO_REGION_SIZE);
3152	Assert(cb == 4 \|\| cb == 8);
3153	Assert(!(off & (cb - 1)));
3154
3155	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3156	switch (off)
3157	{
3158	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
3159	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
3160	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
3161	case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
3162	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
3163	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
3164	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3165
3166	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3167	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
3168	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
3169	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
3170
3171	case IOMMU_MMIO_OFF_GALOG_BAR:
3172	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3173
3174	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
3175	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3176
3177	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3178	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3179	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3180	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3181	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3182	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3183	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
3184
3185	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
3186	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
3187	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3188
3189	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
3190	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3191	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3192	{
3193	VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
3194	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3195	return rcStrict;
3196	uValue >>= 32;
3197	RT_FALL_THRU();
3198	}
3199	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
3200	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3201	{
3202	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
3203	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3204	return rcStrict;
3205	uValue >>= 32;
3206	RT_FALL_THRU();
3207	}
3208	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
3209	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3210
3211	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3212
3213	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
3214	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
3215	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3216
3217	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
3218	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
3219	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
3220	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
3221	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
3222	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
3223	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
3224	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
3225	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
3226	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
3227	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
3228	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3229
3230	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3231
3232	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
3233	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
3234	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
3235	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
3236
3237	case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
3238
3239	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
3240	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
3241
3242	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
3243	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
3244
3245	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
3246	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
3247
3248	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
3249	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3250
3251	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
3252	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
3253	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
3254
3255	/* Not implemented. */
3256	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3257	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3258	{
3259	Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
3260	(off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3261	return VINF_SUCCESS;
3262	}
3263
3264	/* Unknown. */
3265	default:
3266	{
3267	Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
3268	return VINF_SUCCESS;
3269	}
3270	}
3271	}
3272
3273
3274	/**
3275	* Reads an IOMMU register (64-bit) given its MMIO offset.
3276	*
3277	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
3278	* boundary include the lower half of the subsequent register.
3279	*
3280	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
3281	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
3282	* software will only perform 32-bit reads on those 32-bit registers that are
3283	* aligned on 8-byte boundaries.
3284	*
3285	* @returns Strict VBox status code.
3286	* @param pDevIns The IOMMU device instance.
3287	* @param off The MMIO offset of the register in bytes.
3288	* @param puResult Where to store the value being read.
3289	*
3290	* @thread EMT.
3291	*/
3292	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
3293	{
3294	Assert(off < IOMMU_MMIO_REGION_SIZE);
3295	Assert(!(off & 7) \|\| !(off & 3));
3296
3297	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3298	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3299	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3300
3301	/** @todo IOMMU: fine-grained locking? */
3302	uint64_t uReg;
3303	switch (off)
3304	{
3305	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
3306	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
3307	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
3308	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
3309	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
3310	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
3311	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
3312
3313	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
3314	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
3315	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
3316	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
3317
3318	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
3319	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
3320
3321	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
3322	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
3323
3324	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3325	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3326	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3327	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3328	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3329	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3330	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
3331	{
3332	uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
3333	uint8_t const idxDevTabSeg = offDevTabSeg + 1;
3334	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3335	uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
3336	break;
3337	}
3338
3339	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
3340	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
3341	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
3342
3343	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MsiMiscInfo.u64; break;
3344	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MsiMiscInfo.au32[1]; break;
3345	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3346	{
3347	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3348	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3349	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
3350	break;
3351	}
3352	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
3353	{
3354	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3355	break;
3356	}
3357	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3358	{
3359	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3360	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3361	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
3362	break;
3363	}
3364	case IOMMU_MMIO_OFF_MSI_DATA:
3365	{
3366	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3367	break;
3368	}
3369	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
3370	{
3371	/*
3372	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
3373	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
3374	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
3375	* 0 for this register.
3376	*/
3377	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
3378	break;
3379	}
3380
3381	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
3382
3383	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
3384	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
3385	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
3386
3387	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
3388	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
3389	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
3390	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
3391	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
3392	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
3393	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
3394	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
3395	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
3396	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
3397	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
3398	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
3399
3400	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
3401
3402	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
3403	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
3404	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
3405	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
3406
3407	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
3408
3409	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
3410	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
3411
3412	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
3413	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
3414
3415	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
3416	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
3417
3418	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
3419	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
3420
3421	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
3422	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
3423	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
3424
3425	/* Not implemented. */
3426	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3427	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3428	{
3429	Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3430	uReg = 0;
3431	break;
3432	}
3433
3434	/* Unknown. */
3435	default:
3436	{
3437	Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
3438	uReg = 0;
3439	return VINF_IOM_MMIO_UNUSED_00;
3440	}
3441	}
3442
3443	*puResult = uReg;
3444	return VINF_SUCCESS;
3445	}
3446
3447
3448	/**
3449	* Raises the MSI interrupt for the IOMMU device.
3450	*
3451	* @param pDevIns The IOMMU device instance.
3452	*
3453	* @thread Any.
3454	*/
3455	static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
3456	{
3457	if (iommuAmdIsMsiEnabled(pDevIns))
3458	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
3459	}
3460
3461
3462	/**
3463	* Clears the MSI interrupt for the IOMMU device.
3464	*
3465	* @param pDevIns The IOMMU device instance.
3466	*
3467	* @thread Any.
3468	*/
3469	static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
3470	{
3471	if (iommuAmdIsMsiEnabled(pDevIns))
3472	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3473	}
3474
3475
3476	/**
3477	* Writes an entry to the event log in memory.
3478	*
3479	* @returns VBox status code.
3480	* @param pDevIns The IOMMU device instance.
3481	* @param pEvent The event to log.
3482	*
3483	* @thread Any.
3484	*/
3485	static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3486	{
3487	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3488
3489	IOMMU_ASSERT_LOCKED(pDevIns);
3490
3491	/* Check if event logging is active and the log has not overflowed. */
3492	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3493	if ( Status.n.u1EvtLogRunning
3494	&& !Status.n.u1EvtOverflow)
3495	{
3496	uint32_t const cbEvt = sizeof(*pEvent);
3497
3498	/* Get the offset we need to write the event to in memory (circular buffer offset). */
3499	uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3500	Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3501
3502	/* Ensure we have space in the event log. */
3503	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3504	uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3505	if (cEvts + 1 < cMaxEvts)
3506	{
3507	/* Write the event log entry to memory. */
3508	RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3509	RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3510	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3511	if (RT_FAILURE(rc))
3512	Log((IOMMU_LOG_PFX ": Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3513
3514	/* Increment the event log tail pointer. */
3515	uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3516	pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3517
3518	/* Indicate that an event log entry was written. */
3519	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3520
3521	/* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3522	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3523	if (Ctrl.n.u1EvtIntrEn)
3524	iommuAmdRaiseMsiInterrupt(pDevIns);
3525	}
3526	else
3527	{
3528	/* Indicate that the event log has overflowed. */
3529	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3530
3531	/* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3532	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3533	if (Ctrl.n.u1EvtIntrEn)
3534	iommuAmdRaiseMsiInterrupt(pDevIns);
3535	}
3536	}
3537	}
3538
3539
3540	/**
3541	* Sets an event in the hardware error registers.
3542	*
3543	* @param pDevIns The IOMMU device instance.
3544	* @param pEvent The event.
3545	*
3546	* @thread Any.
3547	*/
3548	static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3549	{
3550	IOMMU_ASSERT_LOCKED(pDevIns);
3551
3552	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3553	if (pThis->ExtFeat.n.u1HwErrorSup)
3554	{
3555	if (pThis->HwEvtStatus.n.u1Valid)
3556	pThis->HwEvtStatus.n.u1Overflow = 1;
3557	pThis->HwEvtStatus.n.u1Valid = 1;
3558	pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3559	pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3560	Assert(pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR);
3561	}
3562	}
3563
3564
3565	/**
3566	* Initializes a PAGE_TAB_HARDWARE_ERROR event.
3567	*
3568	* @param uDevId The device ID.
3569	* @param uDomainId The domain ID.
3570	* @param GCPhysPtEntity The system physical address of the page table
3571	* entity.
3572	* @param enmOp The IOMMU operation being performed.
3573	* @param pEvtPageTabHwErr Where to store the initialized event.
3574	*/
3575	static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3576	PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3577	{
3578	memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3579	pEvtPageTabHwErr->n.u16DevId = uDevId;
3580	pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
3581	pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3582	pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3583	pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3584	pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3585	pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3586	pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3587	pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3588	}
3589
3590
3591	/**
3592	* Raises a PAGE_TAB_HARDWARE_ERROR event.
3593	*
3594	* @param pDevIns The IOMMU device instance.
3595	* @param enmOp The IOMMU operation being performed.
3596	* @param pEvtPageTabHwErr The page table hardware error event.
3597	*
3598	* @thread Any.
3599	*/
3600	static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3601	{
3602	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3603	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3604
3605	IOMMU_LOCK_NORET(pDevIns);
3606
3607	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3608	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3609	if (enmOp != IOMMUOP_CMD)
3610	iommuAmdSetPciTargetAbort(pDevIns);
3611
3612	IOMMU_UNLOCK(pDevIns);
3613
3614	Log((IOMMU_LOG_PFX ": Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3615	pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3616	pEvtPageTabHwErr->n.u2Type));
3617	}
3618
3619
3620	/**
3621	* Initializes a COMMAND_HARDWARE_ERROR event.
3622	*
3623	* @param GCPhysAddr The system physical address the IOMMU attempted to access.
3624	* @param pEvtCmdHwErr Where to store the initialized event.
3625	*/
3626	static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3627	{
3628	memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3629	pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3630	pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3631	pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3632	}
3633
3634
3635	/**
3636	* Raises a COMMAND_HARDWARE_ERROR event.
3637	*
3638	* @param pDevIns The IOMMU device instance.
3639	* @param pEvtCmdHwErr The command hardware error event.
3640	*
3641	* @thread Any.
3642	*/
3643	static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3644	{
3645	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3646	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3647	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3648
3649	IOMMU_LOCK_NORET(pDevIns);
3650
3651	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3652	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3653	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3654
3655	IOMMU_UNLOCK(pDevIns);
3656
3657	Log((IOMMU_LOG_PFX ": Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr,
3658	pEvtCmdHwErr->n.u2Type));
3659	}
3660
3661
3662	/**
3663	* Initializes a DEV_TAB_HARDWARE_ERROR event.
3664	*
3665	* @param uDevId The device ID.
3666	* @param GCPhysDte The system physical address of the failed device table
3667	* access.
3668	* @param enmOp The IOMMU operation being performed.
3669	* @param pEvtDevTabHwErr Where to store the initialized event.
3670	*/
3671	static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3672	PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3673	{
3674	memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3675	pEvtDevTabHwErr->n.u16DevId = uDevId;
3676	pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3677	/** @todo IOMMU: Any other transaction type that can set read/write bit? */
3678	pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3679	pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3680	pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3681	pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3682	pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3683	}
3684
3685
3686	/**
3687	* Raises a DEV_TAB_HARDWARE_ERROR event.
3688	*
3689	* @param pDevIns The IOMMU device instance.
3690	* @param enmOp The IOMMU operation being performed.
3691	* @param pEvtDevTabHwErr The device table hardware error event.
3692	*
3693	* @thread Any.
3694	*/
3695	static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3696	{
3697	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3698	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3699
3700	IOMMU_LOCK_NORET(pDevIns);
3701
3702	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3703	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3704	if (enmOp != IOMMUOP_CMD)
3705	iommuAmdSetPciTargetAbort(pDevIns);
3706
3707	IOMMU_UNLOCK(pDevIns);
3708
3709	Log((IOMMU_LOG_PFX ": Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n",
3710	pEvtDevTabHwErr->n.u16DevId, pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3711	}
3712
3713
3714	/**
3715	* Initializes an ILLEGAL_COMMAND_ERROR event.
3716	*
3717	* @param GCPhysCmd The system physical address of the failed command
3718	* access.
3719	* @param pEvtIllegalCmd Where to store the initialized event.
3720	*/
3721	static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3722	{
3723	Assert(!(GCPhysCmd & UINT64_C(0xf)));
3724	memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3725	pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3726	pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3727	}
3728
3729
3730	/**
3731	* Raises an ILLEGAL_COMMAND_ERROR event.
3732	*
3733	* @param pDevIns The IOMMU device instance.
3734	* @param pEvtIllegalCmd The illegal command error event.
3735	*/
3736	static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3737	{
3738	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3739	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3740	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3741
3742	IOMMU_LOCK_NORET(pDevIns);
3743
3744	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3745	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3746
3747	IOMMU_UNLOCK(pDevIns);
3748
3749	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3750	}
3751
3752
3753	/**
3754	* Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3755	*
3756	* @param uDevId The device ID.
3757	* @param uIova The I/O virtual address.
3758	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3759	* event was caused by an invalid level encoding in the
3760	* DTE.
3761	* @param enmOp The IOMMU operation being performed.
3762	* @param pEvtIllegalDte Where to store the initialized event.
3763	*/
3764	static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3765	PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3766	{
3767	memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3768	pEvtIllegalDte->n.u16DevId = uDevId;
3769	pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3770	pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3771	pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3772	pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3773	pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3774	pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3775	/** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3776	* IOMMU spec here but not for this field for I/O page fault event. */
3777	Assert(!(uIova & UINT64_C(0x3)));
3778	}
3779
3780
3781	/**
3782	* Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3783	*
3784	* @param pDevIns The IOMMU instance data.
3785	* @param enmOp The IOMMU operation being performed.
3786	* @param pEvtIllegalDte The illegal device table entry event.
3787	* @param enmEvtType The illegal device table entry event type.
3788	*
3789	* @thread Any.
3790	*/
3791	static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3792	EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3793	{
3794	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3795	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3796
3797	IOMMU_LOCK_NORET(pDevIns);
3798
3799	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3800	if (enmOp != IOMMUOP_CMD)
3801	iommuAmdSetPciTargetAbort(pDevIns);
3802
3803	IOMMU_UNLOCK(pDevIns);
3804
3805	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3806	pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3807	NOREF(enmEvtType);
3808	}
3809
3810
3811	/**
3812	* Initializes an IO_PAGE_FAULT event.
3813	*
3814	* @param uDevId The device ID.
3815	* @param uDomainId The domain ID.
3816	* @param uIova The I/O virtual address being accessed.
3817	* @param fPresent Transaction to a page marked as present (including
3818	* DTE.V=1) or interrupt marked as remapped
3819	* (IRTE.RemapEn=1).
3820	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3821	* the I/O page fault was caused by invalid level
3822	* encoding.
3823	* @param fPermDenied Permission denied for the address being accessed.
3824	* @param enmOp The IOMMU operation being performed.
3825	* @param pEvtIoPageFault Where to store the initialized event.
3826	*/
3827	static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3828	bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3829	{
3830	Assert(!fPermDenied \|\| fPresent);
3831	memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3832	pEvtIoPageFault->n.u16DevId = uDevId;
3833	//pEvtIoPageFault->n.u4PasidHi = 0;
3834	pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
3835	//pEvtIoPageFault->n.u1GuestOrNested = 0;
3836	//pEvtIoPageFault->n.u1NoExecute = 0;
3837	//pEvtIoPageFault->n.u1User = 0;
3838	pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3839	pEvtIoPageFault->n.u1Present = fPresent;
3840	pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3841	pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3842	pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3843	pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3844	pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3845	pEvtIoPageFault->n.u64Addr = uIova;
3846	}
3847
3848
3849	/**
3850	* Raises an IO_PAGE_FAULT event.
3851	*
3852	* @param pDevIns The IOMMU instance data.
3853	* @param pDte The device table entry. Optional, can be NULL
3854	* depending on @a enmOp.
3855	* @param pIrte The interrupt remapping table entry. Optional, can
3856	* be NULL depending on @a enmOp.
3857	* @param enmOp The IOMMU operation being performed.
3858	* @param pEvtIoPageFault The I/O page fault event.
3859	* @param enmEvtType The I/O page fault event type.
3860	*
3861	* @thread Any.
3862	*/
3863	static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3864	PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3865	{
3866	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3867	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3868
3869	IOMMU_LOCK_NORET(pDevIns);
3870
3871	bool fSuppressEvtLogging = false;
3872	if ( enmOp == IOMMUOP_MEM_READ
3873	\|\| enmOp == IOMMUOP_MEM_WRITE)
3874	{
3875	if ( pDte
3876	&& pDte->n.u1Valid)
3877	{
3878	fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
3879	/** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
3880	* suppression. Perhaps will be possible when we complete IOTLB/cache
3881	* handling. */
3882	}
3883	}
3884	else if (enmOp == IOMMUOP_INTR_REQ)
3885	{
3886	if ( pDte
3887	&& pDte->n.u1IntrMapValid)
3888	fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
3889
3890	if ( !fSuppressEvtLogging
3891	&& pIrte)
3892	fSuppressEvtLogging = pIrte->n.u1SuppressPf;
3893	}
3894	/* else: Events are never suppressed for commands. */
3895
3896	switch (enmEvtType)
3897	{
3898	case kIoPageFaultType_PermDenied:
3899	{
3900	/* Cannot be triggered by a command. */
3901	Assert(enmOp != IOMMUOP_CMD);
3902	RT_FALL_THRU();
3903	}
3904	case kIoPageFaultType_DteRsvdPagingMode:
3905	case kIoPageFaultType_PteInvalidPageSize:
3906	case kIoPageFaultType_PteInvalidLvlEncoding:
3907	case kIoPageFaultType_SkippedLevelIovaNotZero:
3908	case kIoPageFaultType_PteRsvdNotZero:
3909	case kIoPageFaultType_PteValidNotSet:
3910	case kIoPageFaultType_DteTranslationDisabled:
3911	case kIoPageFaultType_PasidInvalidRange:
3912	{
3913	/*
3914	* For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3915	* create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
3916	*/
3917	if (enmOp != IOMMUOP_TRANSLATE_REQ)
3918	{
3919	if (!fSuppressEvtLogging)
3920	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3921	if (enmOp != IOMMUOP_CMD)
3922	iommuAmdSetPciTargetAbort(pDevIns);
3923	}
3924	break;
3925	}
3926
3927	case kIoPageFaultType_UserSupervisor:
3928	{
3929	/* Access is blocked and only creates an event log entry. */
3930	if (!fSuppressEvtLogging)
3931	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3932	break;
3933	}
3934
3935	case kIoPageFaultType_IrteAddrInvalid:
3936	case kIoPageFaultType_IrteRsvdNotZero:
3937	case kIoPageFaultType_IrteRemapEn:
3938	case kIoPageFaultType_IrteRsvdIntType:
3939	case kIoPageFaultType_IntrReqAborted:
3940	case kIoPageFaultType_IntrWithPasid:
3941	{
3942	/* Only trigerred by interrupt requests. */
3943	Assert(enmOp == IOMMUOP_INTR_REQ);
3944	if (!fSuppressEvtLogging)
3945	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3946	iommuAmdSetPciTargetAbort(pDevIns);
3947	break;
3948	}
3949
3950	case kIoPageFaultType_SmiFilterMismatch:
3951	{
3952	/* Not supported and probably will never be, assert. */
3953	AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3954	break;
3955	}
3956
3957	case kIoPageFaultType_DevId_Invalid:
3958	{
3959	/* Cannot be triggered by a command. */
3960	Assert(enmOp != IOMMUOP_CMD);
3961	Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3962	if (!fSuppressEvtLogging)
3963	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3964	if ( enmOp == IOMMUOP_MEM_READ
3965	\|\| enmOp == IOMMUOP_MEM_WRITE)
3966	iommuAmdSetPciTargetAbort(pDevIns);
3967	break;
3968	}
3969	}
3970
3971	IOMMU_UNLOCK(pDevIns);
3972	}
3973
3974
3975	/**
3976	* Returns whether the I/O virtual address is to be excluded from translation and
3977	* permission checks.
3978	*
3979	* @returns @c true if the DVA is excluded, @c false otherwise.
3980	* @param pThis The IOMMU device state.
3981	* @param pDte The device table entry.
3982	* @param uIova The I/O virtual address.
3983	*
3984	* @remarks Ensure the exclusion range is enabled prior to calling this function.
3985	*
3986	* @thread Any.
3987	*/
3988	static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
3989	{
3990	/* Ensure the exclusion range is enabled. */
3991	Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
3992
3993	/* Check if the IOVA falls within the exclusion range. */
3994	uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
3995	uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
3996	if (uIovaExclLast - uIova >= uIovaExclFirst)
3997	{
3998	/* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
3999	if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
4000	\|\| pDte->n.u1AllowExclusion)
4001	return true;
4002	}
4003	return false;
4004	}
4005
4006
4007	/**
4008	* Reads a device table entry from guest memory given the device ID.
4009	*
4010	* @returns VBox status code.
4011	* @param pDevIns The IOMMU device instance.
4012	* @param uDevId The device ID.
4013	* @param enmOp The IOMMU operation being performed.
4014	* @param pDte Where to store the device table entry.
4015	*
4016	* @thread Any.
4017	*/
4018	static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
4019	{
4020	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4021	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4022
4023	uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
4024	Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
4025
4026	uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
4027	Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
4028
4029	RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
4030	uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
4031	RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
4032
4033	Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
4034	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
4035	if (RT_FAILURE(rc))
4036	{
4037	Log((IOMMU_LOG_PFX ": Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
4038
4039	EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
4040	iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
4041	iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
4042	return VERR_IOMMU_IPE_1;
4043	}
4044
4045
4046	return rc;
4047	}
4048
4049
4050	/**
4051	* Walks the I/O page table to translate the I/O virtual address to a system
4052	* physical address.
4053	*
4054	* @returns VBox status code.
4055	* @param pDevIns The IOMMU device instance.
4056	* @param uIova The I/O virtual address to translate. Must be 4K aligned.
4057	* @param uDevId The device ID.
4058	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4059	* permissions for the access being made.
4060	* @param pDte The device table entry.
4061	* @param enmOp The IOMMU operation being performed.
4062	* @param pWalkResult Where to store the results of the I/O page walk. This is
4063	* only updated when VINF_SUCCESS is returned.
4064	*
4065	* @thread Any.
4066	*/
4067	static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
4068	IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
4069	{
4070	Assert(pDte->n.u1Valid);
4071	Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
4072
4073	/* If the translation is not valid, raise an I/O page fault. */
4074	if (pDte->n.u1TranslationValid)
4075	{ /* likely */ }
4076	else
4077	{
4078	/** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
4079	* doesn't explicitly say whether an I/O page fault is raised. From other
4080	* places in the spec. it seems early page walk terminations (starting with
4081	* the DTE) return the state computed so far and raises an I/O page fault. So
4082	* returning an invalid translation rather than skipping translation. */
4083	Log((IOMMU_LOG_PFX ": Translation valid bit not set -> IOPF"));
4084	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4085	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4086	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4087	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4088	kIoPageFaultType_DteTranslationDisabled);
4089	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4090	}
4091
4092	/* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
4093	uint8_t const uMaxLevel = pDte->n.u3Mode;
4094	if (uMaxLevel != 0)
4095	{ /* likely */ }
4096	else
4097	{
4098	uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4099	if ((fAccess & fDtePerm) != fAccess)
4100	{
4101	Log((IOMMU_LOG_PFX ": Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
4102	return VERR_IOMMU_ADDR_ACCESS_DENIED;
4103	}
4104	pWalkResult->GCPhysSpa = uIova;
4105	pWalkResult->cShift = 0;
4106	pWalkResult->fIoPerm = fDtePerm;
4107	return VINF_SUCCESS;
4108	}
4109
4110	/* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
4111	if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4112	{ /* likely */ }
4113	else
4114	{
4115	/** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
4116	* raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
4117	* I'm just going with I/O page fault. */
4118	Log((IOMMU_LOG_PFX ": Invalid root page table level %#x -> IOPF", uMaxLevel));
4119	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4120	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4121	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4122	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4123	kIoPageFaultType_PteInvalidLvlEncoding);
4124	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4125	}
4126
4127	/* Check permissions bits of the root page table. */
4128	uint8_t const fPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4129	if ((fAccess & fPtePerm) == fAccess)
4130	{ /* likely */ }
4131	else
4132	{
4133	Log((IOMMU_LOG_PFX ": Permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF", fAccess, fPtePerm));
4134	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4135	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4136	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4137	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4138	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4139	}
4140
4141	/** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
4142	* function called iommuAmdWalkIoPageDirectory() and call it for multi-page
4143	* accesses from the 2nd page. We can avoid re-checking the DTE root-page
4144	* table entry every time. Not sure if it's worth optimizing that case now
4145	* or if at all. */
4146
4147	/* The virtual address bits indexing table. */
4148	static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
4149	static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
4150	UINT64_C(0x00000000001ff000),
4151	UINT64_C(0x000000003fe00000),
4152	UINT64_C(0x0000007fc0000000),
4153	UINT64_C(0x0000ff8000000000),
4154	UINT64_C(0x01ff000000000000),
4155	UINT64_C(0xfe00000000000000),
4156	UINT64_C(0x0000000000000000) };
4157	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
4158	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
4159
4160	/* Traverse the I/O page table starting with the page directory in the DTE. */
4161	IOPTENTITY_T PtEntity;
4162	PtEntity.u64 = pDte->au64[0];
4163	for (;;)
4164	{
4165	/* Figure out the system physical address of the page table at the current level. */
4166	uint8_t const uLevel = PtEntity.n.u3NextLevel;
4167
4168	/* Read the page table entity at the current level. */
4169	{
4170	Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
4171	Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4172	uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
4173	uint64_t const offPte = idxPte << 3;
4174	RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
4175	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
4176	if (RT_FAILURE(rc))
4177	{
4178	Log((IOMMU_LOG_PFX ": Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
4179	EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
4180	iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
4181	iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
4182	return VERR_IOMMU_IPE_2;
4183	}
4184	}
4185
4186	/* Check present bit. */
4187	if (PtEntity.n.u1Present)
4188	{ /* likely */ }
4189	else
4190	{
4191	Log((IOMMU_LOG_PFX ": Page table entry not present -> IOPF", fAccess, fPtePerm));
4192	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4193	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4194	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4195	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4196	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4197	}
4198
4199	/* Check permission bits. */
4200	uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4201	if ((fAccess & fPtePerm) == fAccess)
4202	{ /* likely */ }
4203	else
4204	{
4205	Log((IOMMU_LOG_PFX ": Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF", fAccess, fPtePerm));
4206	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4207	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4208	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4209	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4210	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4211	}
4212
4213	/* If this is a PTE, we're at the final level and we're done. */
4214	uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
4215	if (uNextLevel == 0)
4216	{
4217	/* The page size of the translation is the default (4K). */
4218	pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4219	pWalkResult->cShift = X86_PAGE_4K_SHIFT;
4220	pWalkResult->fIoPerm = fPtePerm;
4221	return VINF_SUCCESS;
4222	}
4223	if (uNextLevel == 7)
4224	{
4225	/* The default page size of the translation is overriden. */
4226	RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4227	uint8_t cShift = X86_PAGE_4K_SHIFT;
4228	while (GCPhysPte & RT_BIT_64(cShift++))
4229	;
4230
4231	/* The page size must be larger than the default size and lower than the default size of the higher level. */
4232	Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
4233	if ( cShift > s_acIovaLevelShifts[uLevel]
4234	&& cShift < s_acIovaLevelShifts[uLevel + 1])
4235	{
4236	pWalkResult->GCPhysSpa = GCPhysPte;
4237	pWalkResult->cShift = cShift;
4238	pWalkResult->fIoPerm = fPtePerm;
4239	return VINF_SUCCESS;
4240	}
4241
4242	Log((IOMMU_LOG_PFX ": Page size invalid cShift=%#x -> IOPF", cShift));
4243	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4244	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4245	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4246	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4247	kIoPageFaultType_PteInvalidPageSize);
4248	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4249	}
4250
4251	/* Validate the next level encoding of the PDE. */
4252	#if IOMMU_MAX_HOST_PT_LEVEL < 6
4253	if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4254	{ /* likely */ }
4255	else
4256	{
4257	Log((IOMMU_LOG_PFX ": Next level of PDE invalid uNextLevel=%#x -> IOPF", uNextLevel));
4258	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4259	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4260	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4261	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4262	kIoPageFaultType_PteInvalidLvlEncoding);
4263	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4264	}
4265	#else
4266	Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4267	#endif
4268
4269	/* Validate level transition. */
4270	if (uNextLevel < uLevel)
4271	{ /* likely */ }
4272	else
4273	{
4274	Log((IOMMU_LOG_PFX ": Next level (%#x) must be less than the current level (%#x) -> IOPF", uNextLevel, uLevel));
4275	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4276	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4277	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4278	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4279	kIoPageFaultType_PteInvalidLvlEncoding);
4280	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4281	}
4282
4283	/* Ensure IOVA bits of skipped levels are zero. */
4284	Assert(uLevel > 0);
4285	uint64_t uIovaSkipMask = 0;
4286	for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
4287	uIovaSkipMask \|= s_auIovaLevelMasks[idxLevel];
4288	if (!(uIova & uIovaSkipMask))
4289	{ /* likely */ }
4290	else
4291	{
4292	Log((IOMMU_LOG_PFX ": IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF", uIova, uIovaSkipMask));
4293	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4294	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4295	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4296	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4297	kIoPageFaultType_SkippedLevelIovaNotZero);
4298	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4299	}
4300
4301	/* Continue with traversing the page directory at this level. */
4302	}
4303
4304	/* Shouldn't really get here. */
4305	return VERR_IOMMU_IPE_3;
4306	}
4307
4308
4309	/**
4310	* Looks up an I/O virtual address from the device table.
4311	*
4312	* @returns VBox status code.
4313	* @param pDevIns The IOMMU instance data.
4314	* @param uDevId The device ID.
4315	* @param uIova The I/O virtual address to lookup.
4316	* @param cbAccess The size of the access.
4317	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4318	* permissions for the access being made.
4319	* @param enmOp The IOMMU operation being performed.
4320	* @param pGCPhysSpa Where to store the translated system physical address. Only
4321	* valid when translation succeeds and VINF_SUCCESS is
4322	* returned!
4323	*
4324	* @thread Any.
4325	*/
4326	static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
4327	IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
4328	{
4329	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4330
4331	/* Read the device table entry from memory. */
4332	DTE_T Dte;
4333	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4334	if (RT_SUCCESS(rc))
4335	{
4336	/* If the DTE is not valid, addresses are forwarded without translation */
4337	if (Dte.n.u1Valid)
4338	{ /* likely */ }
4339	else
4340	{
4341	/** @todo IOMMU: Add to IOLTB cache. */
4342	*pGCPhysSpa = uIova;
4343	return VINF_SUCCESS;
4344	}
4345
4346	/* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4347	uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4348	uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4349	if (RT_LIKELY( !fRsvd0
4350	&& !fRsvd1))
4351	{ /* likely */ }
4352	else
4353	{
4354	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4355	EVT_ILLEGAL_DTE_T Event;
4356	iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4357	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4358	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4359	}
4360
4361	/* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
4362	if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
4363	\|\| !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
4364	{ /* likely */ }
4365	else
4366	{
4367	/** @todo IOMMU: Add to IOLTB cache. */
4368	*pGCPhysSpa = uIova;
4369	return VINF_SUCCESS;
4370	}
4371
4372	/** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
4373	* below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
4374
4375	uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
4376	uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
4377	uint64_t cbRemaining = cbAccess;
4378	for (;;)
4379	{
4380	/* Walk the I/O page tables to translate the IOVA and check permission for the access. */
4381	IOWALKRESULT WalkResult;
4382	rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
4383	if (RT_SUCCESS(rc))
4384	{
4385	/** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
4386
4387	/* Store the translated base address before continuing to check permissions for any more pages. */
4388	if (cbRemaining == cbAccess)
4389	{
4390	RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
4391	*pGCPhysSpa = WalkResult.GCPhysSpa \| offSpa;
4392	}
4393
4394	uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
4395	if (cbRemaining > cbPhysPage - offIova)
4396	{
4397	cbRemaining -= (cbPhysPage - offIova);
4398	uBaseIova += cbPhysPage;
4399	offIova = 0;
4400	}
4401	else
4402	break;
4403	}
4404	else
4405	{
4406	Log((IOMMU_LOG_PFX ": I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
4407	uBaseIova, fAccess, rc));
4408	*pGCPhysSpa = NIL_RTGCPHYS;
4409	return rc;
4410	}
4411	}
4412
4413	return rc;
4414	}
4415
4416	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4417	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4418	}
4419
4420
4421	/**
4422	* Memory read request from a device.
4423	*
4424	* @returns VBox status code.
4425	* @param pDevIns The IOMMU device instance.
4426	* @param uDevId The device ID (bus, device, function).
4427	* @param uIova The I/O virtual address being read.
4428	* @param cbRead The number of bytes being read.
4429	* @param pGCPhysSpa Where to store the translated system physical address.
4430	*
4431	* @thread Any.
4432	*/
4433	static int iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, PRTGCPHYS pGCPhysSpa)
4434	{
4435	/* Validate. */
4436	Assert(pDevIns);
4437	Assert(pGCPhysSpa);
4438	Assert(cbRead > 0);
4439
4440	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4441
4442	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4443	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4444	if (Ctrl.n.u1IommuEn)
4445	{
4446	/** @todo IOMMU: IOTLB cache lookup. */
4447
4448	/* Lookup the IOVA from the device table. */
4449	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
4450	}
4451
4452	*pGCPhysSpa = uIova;
4453	return VINF_SUCCESS;
4454	}
4455
4456
4457	/**
4458	* Memory write request from a device.
4459	*
4460	* @returns VBox status code.
4461	* @param pDevIns The IOMMU device instance.
4462	* @param uDevId The device ID (bus, device, function).
4463	* @param uIova The I/O virtual address being written.
4464	* @param cbWrite The number of bytes being written.
4465	* @param pGCPhysSpa Where to store the translated physical address.
4466	*
4467	* @thread Any.
4468	*/
4469	static int iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite, PRTGCPHYS pGCPhysSpa)
4470	{
4471	/* Validate. */
4472	Assert(pDevIns);
4473	Assert(pGCPhysSpa);
4474	Assert(cbWrite > 0);
4475
4476	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4477
4478	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4479	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4480	if (Ctrl.n.u1IommuEn)
4481	{
4482	/** @todo IOMMU: IOTLB cache lookup. */
4483
4484	/* Lookup the IOVA from the device table. */
4485	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
4486	}
4487
4488	*pGCPhysSpa = uIova;
4489	return VINF_SUCCESS;
4490	}
4491
4492
4493	/**
4494	* Reads an interrupt remapping table entry from guest memory given its DTE.
4495	*
4496	* @returns VBox status code.
4497	* @param pDevIns The IOMMU device instance.
4498	* @param uDevId The device ID.
4499	* @param pDte The device table entry.
4500	* @param GCPhysIn The source MSI address.
4501	* @param uDataIn The source MSI data.
4502	* @param enmOp The IOMMU operation being performed.
4503	* @param pIrte Where to store the interrupt remapping table entry.
4504	*
4505	* @thread Any.
4506	*/
4507	static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4508	IOMMUOP enmOp, PIRTE_T pIrte)
4509	{
4510	RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4511	uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) << IOMMU_IRTE_SIZE_SHIFT;
4512	RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4513
4514	/* Ensure the IRTE offset is within the specified table size. */
4515	Assert(pDte->n.u4IntrTableLength < 12);
4516	if (offIrte + sizeof(IRTE_T) <= (1 << pDte->n.u4IntrTableLength) << IOMMU_IRTE_SIZE_SHIFT)
4517	{ /* likely */ }
4518	else
4519	{
4520	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4521	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent /, false / fRsvdNotZero */,
4522	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4523	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4524	kIoPageFaultType_IrteAddrInvalid);
4525	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4526	}
4527
4528	/* Read the IRTE from memory. */
4529	Assert(!(GCPhysIrte & 3));
4530	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4531	if (RT_SUCCESS(rc))
4532	return VINF_SUCCESS;
4533
4534	/** @todo The IOMMU spec. does not tell what kind of error is reported in this
4535	* situation. Is it an I/O page fault or a device table hardware error?
4536	* There's no interrupt table hardware error event, but it's unclear what
4537	* we should do here. */
4538	Log((IOMMU_LOG_PFX ": Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4539	return VERR_IOMMU_IPE_4;
4540	}
4541
4542
4543	/**
4544	* Remap the interrupt using the interrupt remapping table.
4545	*
4546	* @returns VBox status code.
4547	* @param pDevIns The IOMMU instance data.
4548	* @param uDevId The device ID.
4549	* @param pDte The device table entry.
4550	* @param enmOp The IOMMU operation being performed.
4551	* @param pMsiIn The source MSI.
4552	* @param pMsiOut Where to store the remapped MSI.
4553	*
4554	* @thread Any.
4555	*/
4556	static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4557	PMSIMSG pMsiOut)
4558	{
4559	Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4560
4561	IRTE_T Irte;
4562	int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
4563	if (RT_SUCCESS(rc))
4564	{
4565	if (Irte.n.u1RemapEnable)
4566	{
4567	if (!Irte.n.u1GuestMode)
4568	{
4569	if (Irte.n.u3IntrType < VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4570	{
4571	/* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
4572	pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
4573	pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
4574	pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
4575
4576	/* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
4577	pMsiOut->Data.u32 = pMsiIn->Data.u32;
4578	pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
4579	pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
4580
4581	return VINF_SUCCESS;
4582	}
4583
4584	Log((IOMMU_LOG_PFX ": Interrupt type (%#x) invalid -> IOPF", Irte.n.u3IntrType));
4585	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4586	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4587	true /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
4588	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
4589	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4590	}
4591
4592	Log((IOMMU_LOG_PFX ": Guest mode not supported -> IOPF"));
4593	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4594	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4595	true /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
4596	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4597	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4598	}
4599
4600	Log((IOMMU_LOG_PFX ": Remapping disabled -> IOPF"));
4601	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4602	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4603	false /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
4604	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4605	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4606	}
4607
4608	return rc;
4609	}
4610
4611
4612	/**
4613	* Looks up an MSI interrupt from the interrupt remapping table.
4614	*
4615	* @returns VBox status code.
4616	* @param pDevIns The IOMMU instance data.
4617	* @param uDevId The device ID.
4618	* @param enmOp The IOMMU operation being performed.
4619	* @param pMsiIn The source MSI.
4620	* @param pMsiOut Where to store the remapped MSI.
4621	*
4622	* @thread Any.
4623	*/
4624	static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4625	{
4626	/* Read the device table entry from memory. */
4627	DTE_T Dte;
4628	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4629	if (RT_SUCCESS(rc))
4630	{
4631	/* If the DTE is not valid, all interrupts are forwarded without remapping. */
4632	if (Dte.n.u1IntrMapValid)
4633	{
4634	/* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4635	uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4636	uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4637	if (RT_LIKELY( !fRsvd0
4638	&& !fRsvd1))
4639	{ /* likely */ }
4640	else
4641	{
4642	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
4643	fRsvd1));
4644	EVT_ILLEGAL_DTE_T Event;
4645	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4646	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4647	return VERR_IOMMU_INTR_REMAP_FAILED;
4648	}
4649
4650	/*
4651	* LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4652	* that's connected through HyperTransport it might be possible; but for us, it
4653	* doesn't seem we need to specially handle these pins.
4654	*/
4655
4656	/*
4657	* Validate the MSI source address.
4658	*
4659	* 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4660	* CPU is concerned, the MSI region is fixed and we must ensure no other device
4661	* claims the region as I/O space.
4662	*
4663	* See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4664	* See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4665	* See Intel spec. 10.11.1 "Message Address Register Format".
4666	*/
4667	if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4668	{
4669	/*
4670	* The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4671	* See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4672	*/
4673	uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4674	bool fPassThru = false;
4675	switch (u8DeliveryMode)
4676	{
4677	case VBOX_MSI_DELIVERY_MODE_FIXED:
4678	case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4679	{
4680	uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4681	if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4682	{
4683	Log((IOMMU_LOG_PFX ": IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
4684	iommuAmdSetPciTargetAbort(pDevIns);
4685	return VINF_SUCCESS;
4686	}
4687
4688	if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4689	{
4690	fPassThru = true;
4691	break;
4692	}
4693
4694	if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4695	{
4696	/* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4697	uint32_t const uIntTabLen = Dte.n.u4IntrTableLength;
4698	if (Dte.n.u4IntrTableLength < 12)
4699	{
4700	/*
4701	* We don't support guest interrupt remapping yet. When we do, we'll need to
4702	* check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4703	* in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4704	* already reads the control register, add that as a parameter when we eventually
4705	* support guest interrupt remapping. For now, just assert.
4706	*/
4707	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4708	Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4709	NOREF(pThis);
4710
4711	return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
4712	}
4713
4714	Log((IOMMU_LOG_PFX ": Invalid interrupt table length %#x -> Illegal DTE\n", uIntTabLen));
4715	EVT_ILLEGAL_DTE_T Event;
4716	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4717	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4718	return VERR_IOMMU_INTR_REMAP_FAILED;
4719	}
4720
4721	/* Paranoia. */
4722	Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
4723
4724	Log((IOMMU_LOG_PFX ":IntCtl mode invalid %#x -> Illegal DTE", uIntrCtrl));
4725	EVT_ILLEGAL_DTE_T Event;
4726	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4727	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4728	return VERR_IOMMU_INTR_REMAP_FAILED;
4729	}
4730
4731	/* SMIs are passed through unmapped. We don't implement SMI filters. */
4732	case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4733	case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4734	case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4735	case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4736	default:
4737	{
4738	Log((IOMMU_LOG_PFX ":MSI data delivery mode invalid %#x -> Target abort", u8DeliveryMode));
4739	iommuAmdSetPciTargetAbort(pDevIns);
4740	return VERR_IOMMU_INTR_REMAP_FAILED;
4741	}
4742	}
4743
4744	if (fPassThru)
4745	{
4746	pMsiOut = pMsiIn;
4747	return VINF_SUCCESS;
4748	}
4749
4750	iommuAmdSetPciTargetAbort(pDevIns);
4751	return VERR_IOMMU_INTR_REMAP_FAILED;
4752	}
4753	else
4754	{
4755	Log((IOMMU_LOG_PFX ":MSI address region invalid %#RX64.", pMsiIn->Addr.u64));
4756	return VERR_IOMMU_INTR_REMAP_FAILED;
4757	}
4758	}
4759	else
4760	{
4761	/** @todo IOMMU: Add to interrupt remapping cache. */
4762	pMsiOut = pMsiIn;
4763	return VINF_SUCCESS;
4764	}
4765	}
4766
4767	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4768	return VERR_IOMMU_INTR_REMAP_FAILED;
4769	}
4770
4771
4772	/**
4773	* Interrupt remap request from a device.
4774	*
4775	* @returns VBox status code.
4776	* @param pDevIns The IOMMU device instance.
4777	* @param uDevId The device ID (bus, device, function).
4778	* @param pMsiIn The source MSI.
4779	* @param pMsiOut Where to store the remapped MSI.
4780	*/
4781	static int iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4782	{
4783	/* Validate. */
4784	Assert(pDevIns);
4785	Assert(pMsiIn);
4786	Assert(pMsiOut);
4787
4788	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4789
4790	/* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4791	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4792	if (Ctrl.n.u1IommuEn)
4793	{
4794	/** @todo Cache? */
4795
4796	return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4797	}
4798
4799	pMsiOut = pMsiIn;
4800	return VINF_SUCCESS;
4801	}
4802
4803
4804	/**
4805	* @callback_method_impl{FNIOMMMIONEWWRITE}
4806	*/
4807	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
4808	{
4809	NOREF(pvUser);
4810	Assert(cb == 4 \|\| cb == 8);
4811	Assert(!(off & (cb - 1)));
4812
4813	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
4814	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
4815	}
4816
4817
4818	/**
4819	* @callback_method_impl{FNIOMMMIONEWREAD}
4820	*/
4821	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
4822	{
4823	NOREF(pvUser);
4824	Assert(cb == 4 \|\| cb == 8);
4825	Assert(!(off & (cb - 1)));
4826
4827	uint64_t uResult;
4828	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
4829	if (cb == 8)
4830	(uint64_t )pv = uResult;
4831	else
4832	(uint32_t )pv = (uint32_t)uResult;
4833
4834	return rcStrict;
4835	}
4836
4837	# ifdef IN_RING3
4838
4839	/**
4840	* Processes an IOMMU command.
4841	*
4842	* @returns VBox status code.
4843	* @param pDevIns The IOMMU device instance.
4844	* @param pCmd The command to process.
4845	* @param GCPhysCmd The system physical address of the command.
4846	* @param pEvtError Where to store the error event in case of failures.
4847	*
4848	* @thread Command thread.
4849	*/
4850	static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4851	{
4852	IOMMU_ASSERT_NOT_LOCKED(pDevIns);
4853
4854	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4855	uint8_t const bCmd = pCmd->n.u4Opcode;
4856	switch (bCmd)
4857	{
4858	case IOMMU_CMD_COMPLETION_WAIT:
4859	{
4860	PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4861	AssertCompile(sizeof(pCmdComWait) == sizeof(pCmd));
4862
4863	/* Validate reserved bits in the command. */
4864	if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4865	{
4866	/* If Completion Store is requested, write the StoreData to the specified address.*/
4867	if (pCmdComWait->n.u1Store)
4868	{
4869	RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4870	uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4871	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4872	if (RT_FAILURE(rc))
4873	{
4874	Log((IOMMU_LOG_PFX ": Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4875	GCPhysStore, rc));
4876	iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4877	return VERR_IOMMU_CMD_HW_ERROR;
4878	}
4879	}
4880
4881	/* If command completion interrupt is requested, raise an interrupt. */
4882	if (pCmdComWait->n.u1Interrupt)
4883	{
4884	IOMMU_LOCK(pDevIns);
4885	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4886	if (Ctrl.n.u1CompWaitIntrEn)
4887	{
4888	/* Indicate that this command completed. */
4889	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4890
4891	/* Check and signal an interrupt if software wants to receive one when this command completes. */
4892	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4893	if (Ctrl.n.u1CompWaitIntrEn)
4894	iommuAmdRaiseMsiInterrupt(pDevIns);
4895	}
4896	IOMMU_UNLOCK(pDevIns);
4897	}
4898	return VINF_SUCCESS;
4899	}
4900	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4901	return VERR_IOMMU_CMD_INVALID_FORMAT;
4902	}
4903
4904	case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4905	{
4906	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4907	* then. */
4908	return VINF_SUCCESS;
4909	}
4910
4911	case IOMMU_CMD_INV_IOMMU_PAGES:
4912	{
4913	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4914	* then. */
4915	return VINF_SUCCESS;
4916	}
4917
4918	case IOMMU_CMD_INV_IOTLB_PAGES:
4919	{
4920	uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4921	if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4922	{
4923	/** @todo IOMMU: Implement remote IOTLB invalidation. */
4924	return VERR_NOT_IMPLEMENTED;
4925	}
4926	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4927	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4928	}
4929
4930	case IOMMU_CMD_INV_INTR_TABLE:
4931	{
4932	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4933	* then. */
4934	return VINF_SUCCESS;
4935	}
4936
4937	case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
4938	{
4939	if (pThis->ExtFeat.n.u1PrefetchSup)
4940	{
4941	/** @todo IOMMU: Implement prefetch. Pretend success until then. */
4942	return VINF_SUCCESS;
4943	}
4944	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4945	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4946	}
4947
4948	case IOMMU_CMD_COMPLETE_PPR_REQ:
4949	{
4950	/* We don't support PPR requests yet. */
4951	Assert(!pThis->ExtFeat.n.u1PprSup);
4952	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4953	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4954	}
4955
4956	case IOMMU_CMD_INV_IOMMU_ALL:
4957	{
4958	if (pThis->ExtFeat.n.u1InvAllSup)
4959	{
4960	/** @todo IOMMU: Invalidate all. Pretend success until then. */
4961	return VINF_SUCCESS;
4962	}
4963	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4964	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4965	}
4966	}
4967
4968	Log((IOMMU_LOG_PFX ": Cmd(%#x): Unrecognized\n", bCmd));
4969	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4970	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4971	}
4972
4973
4974	/**
4975	* The IOMMU command thread.
4976	*
4977	* @returns VBox status code.
4978	* @param pDevIns The IOMMU device instance.
4979	* @param pThread The command thread.
4980	*/
4981	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4982	{
4983	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4984
4985	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4986	return VINF_SUCCESS;
4987
4988	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4989	{
4990	/*
4991	* Sleep perpetually until we are woken up to process commands.
4992	*/
4993	{
4994	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
4995	bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
4996	if (!fSignaled)
4997	{
4998	Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
4999	int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5000	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5001	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5002	break;
5003	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
5004	ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5005	}
5006	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
5007	}
5008
5009	/*
5010	* Fetch and process IOMMU commands.
5011	*/
5012	/** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
5013	* at a time) and is expensive due to calls to PGM for fetching guest memory.
5014	* We could optimize by fetching a bunch of commands at a time reducing
5015	* number of calls to PGM. In the longer run we could lock the memory and
5016	* mappings and accessing them directly. */
5017	IOMMU_LOCK(pDevIns);
5018
5019	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
5020	if (Status.n.u1CmdBufRunning)
5021	{
5022	/* Get the offset we need to read the command from memory (circular buffer offset). */
5023	uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5024	uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5025	Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5026	Assert(offHead < cbCmdBuf);
5027	while (offHead != pThis->CmdBufTailPtr.n.off)
5028	{
5029	/* Read the command from memory. */
5030	CMD_GENERIC_T Cmd;
5031	RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
5032	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
5033	if (RT_SUCCESS(rc))
5034	{
5035	/* Increment the command buffer head pointer. */
5036	offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5037	pThis->CmdBufHeadPtr.n.off = offHead;
5038
5039	/* Process the fetched command. */
5040	EVT_GENERIC_T EvtError;
5041	IOMMU_UNLOCK(pDevIns);
5042	rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
5043	IOMMU_LOCK(pDevIns);
5044	if (RT_FAILURE(rc))
5045	{
5046	if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5047	\|\| rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5048	{
5049	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5050	iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5051	}
5052	else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5053	{
5054	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5055	iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5056	}
5057	break;
5058	}
5059	}
5060	else
5061	{
5062	EVT_CMD_HW_ERR_T EvtCmdHwErr;
5063	iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
5064	iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
5065	break;
5066	}
5067	}
5068	}
5069
5070	IOMMU_UNLOCK(pDevIns);
5071	}
5072
5073	LogFlow((IOMMU_LOG_PFX ": Command thread terminating\n"));
5074	return VINF_SUCCESS;
5075	}
5076
5077
5078	/**
5079	* Wakes up the command thread so it can respond to a state change.
5080	*
5081	* @returns VBox status code.
5082	* @param pDevIns The IOMMU device instance.
5083	* @param pThread The command thread.
5084	*/
5085	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5086	{
5087	RT_NOREF(pThread);
5088
5089	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5090	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5091	}
5092
5093
5094	/**
5095	* @callback_method_impl{FNPCICONFIGREAD}
5096	*/
5097	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5098	unsigned cb, uint32_t *pu32Value)
5099	{
5100	/** @todo IOMMU: PCI config read stat counter. */
5101	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5102	Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
5103	VBOXSTRICTRC_VAL(rcStrict)));
5104	return rcStrict;
5105	}
5106
5107
5108	/**
5109	* @callback_method_impl{FNPCICONFIGWRITE}
5110	*/
5111	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5112	unsigned cb, uint32_t u32Value)
5113	{
5114	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5115
5116	/*
5117	* Discard writes to read-only registers that are specific to the IOMMU.
5118	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5119	* See PCI spec. 6.1. "Configuration Space Organization".
5120	*/
5121	switch (uAddress)
5122	{
5123	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5124	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5125	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5126	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5127	{
5128	Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5129	return VINF_SUCCESS;
5130	}
5131	}
5132
5133	IOMMU_LOCK(pDevIns);
5134
5135	VBOXSTRICTRC rcStrict;
5136	switch (uAddress)
5137	{
5138	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5139	{
5140	if (pThis->IommuBar.n.u1Enable)
5141	{
5142	rcStrict = VINF_SUCCESS;
5143	Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5144	break;
5145	}
5146
5147	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5148	if (pThis->IommuBar.n.u1Enable)
5149	{
5150	Assert(pThis->hMmio == NIL_IOMMMIOHANDLE);
5151	Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5152	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5153	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5154	if (RT_FAILURE(rcStrict))
5155	Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
5156	}
5157	break;
5158	}
5159
5160	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5161	{
5162	if (!pThis->IommuBar.n.u1Enable)
5163	pThis->IommuBar.au32[1] = u32Value;
5164	else
5165	{
5166	rcStrict = VINF_SUCCESS;
5167	Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5168	}
5169	break;
5170	}
5171
5172	case IOMMU_PCI_OFF_MSI_CAP_HDR:
5173	{
5174	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5175	RT_FALL_THRU();
5176	}
5177	default:
5178	{
5179	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5180	break;
5181	}
5182	}
5183
5184	IOMMU_UNLOCK(pDevIns);
5185
5186	Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
5187	return rcStrict;
5188	}
5189
5190
5191	/**
5192	* @callback_method_impl{FNDBGFHANDLERDEV}
5193	*/
5194	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5195	{
5196	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5197	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5198	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5199
5200	LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
5201	bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
5202
5203	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5204	/* Device Table Base Addresses (all segments). */
5205	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5206	{
5207	DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5208	pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
5209	if (fVerbose)
5210	{
5211	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5212	IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
5213	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5214	}
5215	}
5216	/* Command Buffer Base Address Register. */
5217	{
5218	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5219	uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5220	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5221	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5222	pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
5223	if (fVerbose)
5224	{
5225	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5226	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5227	cEntries, cbBuffer);
5228	}
5229	}
5230	/* Event Log Base Address Register. */
5231	{
5232	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5233	uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5234	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5235	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5236	pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
5237	if (fVerbose)
5238	{
5239	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5240	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5241	cEntries, cbBuffer);
5242	}
5243	}
5244	/* IOMMU Control Register. */
5245	{
5246	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5247	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5248	if (fVerbose)
5249	{
5250	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5251	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5252	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5253	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5254	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5255	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5256	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5257	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5258	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5259	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5260	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5261	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5262	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5263	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5264	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5265	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5266	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5267	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5268	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5269	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5270	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5271	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5272	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5273	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5274	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5275	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5276	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5277	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5278	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5279	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5280	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5281	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5282	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5283	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5284	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5285	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5286	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5287	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5288	}
5289	}
5290	/* Exclusion Base Address Register. */
5291	{
5292	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5293	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5294	if (fVerbose)
5295	{
5296	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5297	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5298	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5299	ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5300	}
5301	}
5302	/* Exclusion Range Limit Register. */
5303	{
5304	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5305	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5306	if (fVerbose)
5307	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
5308	}
5309	/* Extended Feature Register. */
5310	{
5311	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5312	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5313	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5314	if (fVerbose)
5315	{
5316	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5317	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5318	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5319	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5320	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5321	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5322	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5323	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5324	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5325	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5326	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5327	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5328	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5329	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5330	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5331	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5332	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5333	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5334	pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5335	g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5336	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5337	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5338	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5339	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5340	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5341	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5342	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5343	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5344	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5345	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5346	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5347	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5348	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5349	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5350	}
5351	}
5352	/* PPR Log Base Address Register. */
5353	{
5354	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5355	uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5356	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5357	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5358	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5359	if (fVerbose)
5360	{
5361	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5362	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5363	cEntries, cbBuffer);
5364	}
5365	}
5366	/* Hardware Event (Hi) Register. */
5367	{
5368	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5369	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5370	if (fVerbose)
5371	{
5372	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5373	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5374	}
5375	}
5376	/* Hardware Event (Lo) Register. */
5377	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5378	/* Hardware Event Status. */
5379	{
5380	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5381	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5382	if (fVerbose)
5383	{
5384	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5385	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5386	}
5387	}
5388	/* Guest Virtual-APIC Log Base Address Register. */
5389	{
5390	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5391	uint8_t const uEncodedLen = GALogBar.n.u4Len;
5392	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5393	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5394	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5395	if (fVerbose)
5396	{
5397	pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5398	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5399	cEntries, cbBuffer);
5400	}
5401	}
5402	/* Guest Virtual-APIC Log Tail Address Register. */
5403	{
5404	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5405	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5406	if (fVerbose)
5407	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5408	}
5409	/* PPR Log B Base Address Register. */
5410	{
5411	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5412	uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5413	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5414	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5415	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5416	if (fVerbose)
5417	{
5418	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5419	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5420	cEntries, cbBuffer);
5421	}
5422	}
5423	/* Event Log B Base Address Register. */
5424	{
5425	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5426	uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5427	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5428	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5429	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5430	if (fVerbose)
5431	{
5432	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5433	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5434	cEntries, cbBuffer);
5435	}
5436	}
5437	/* Device-Specific Feature Extension Register. */
5438	{
5439	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5440	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5441	if (fVerbose)
5442	{
5443	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5444	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5445	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5446	}
5447	}
5448	/* Device-Specific Control Extension Register. */
5449	{
5450	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5451	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5452	if (fVerbose)
5453	{
5454	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5455	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5456	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5457	}
5458	}
5459	/* Device-Specific Status Extension Register. */
5460	{
5461	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5462	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
5463	if (fVerbose)
5464	{
5465	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5466	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5467	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5468	}
5469	}
5470	/* MSI Miscellaneous Information Register (Lo and Hi). */
5471	{
5472	MSI_MISC_INFO_T const MsiMiscInfo = pThis->MsiMiscInfo;
5473	pHlp->pfnPrintf(pHlp, " MSI Misc. Info. Register = %#RX64\n", MsiMiscInfo.u64);
5474	if (fVerbose)
5475	{
5476	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumEvtLog);
5477	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MsiMiscInfo.n.u3GstVirtAddrSize);
5478	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MsiMiscInfo.n.u7PhysAddrSize);
5479	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MsiMiscInfo.n.u7VirtAddrSize);
5480	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MsiMiscInfo.n.u1HtAtsResv);
5481	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumPpr);
5482	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MsiMiscInfo.n.u5MsiNumGa);
5483	}
5484	}
5485	/* MSI Capability Header. */
5486	{
5487	MSI_CAP_HDR_T MsiCapHdr;
5488	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5489	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5490	if (fVerbose)
5491	{
5492	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5493	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5494	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5495	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5496	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5497	}
5498	}
5499	/* MSI Address Register (Lo and Hi). */
5500	{
5501	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5502	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5503	MSIADDR MsiAddr;
5504	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5505	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5506	if (fVerbose)
5507	{
5508	pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5509	pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5510	pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5511	pHlp->pfnPrintf(pHlp, " Address = %#Rx32\n", MsiAddr.n.u12Addr);
5512	pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#Rx32\n", MsiAddr.n.u32Rsvd0);
5513	}
5514	}
5515	/* MSI Data. */
5516	{
5517	MSIDATA MsiData;
5518	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5519	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5520	if (fVerbose)
5521	{
5522	pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5523	MsiData.n.u8Vector);
5524	pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5525	pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5526	pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5527	"level" : "edge");
5528	}
5529	}
5530	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5531	{
5532	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5533	MsiMapCapHdr.u32 = 0;
5534	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5535	if (fVerbose)
5536	{
5537	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5538	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5539	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5540	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5541	}
5542	}
5543	/* Performance Optimization Control Register. */
5544	{
5545	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5546	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5547	if (fVerbose)
5548	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5549	}
5550	/* XT (x2APIC) General Interrupt Control Register. */
5551	{
5552	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5553	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5554	if (fVerbose)
5555	{
5556	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5557	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5558	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5559	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5560	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5561	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5562	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5563	}
5564	}
5565	/* XT (x2APIC) PPR Interrupt Control Register. */
5566	{
5567	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5568	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5569	if (fVerbose)
5570	{
5571	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5572	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5573	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5574	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5575	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5576	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5577	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5578	}
5579	}
5580	/* XT (X2APIC) GA Log Interrupt Control Register. */
5581	{
5582	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5583	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5584	if (fVerbose)
5585	{
5586	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5587	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5588	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5589	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5590	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5591	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5592	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5593	}
5594	}
5595	/* MARC Registers. */
5596	{
5597	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5598	{
5599	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5600	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5601	pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5602
5603	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5604	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5605	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5606	MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5607
5608	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5609	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5610	}
5611	}
5612	/* Reserved Register. */
5613	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5614	/* Command Buffer Head Pointer Register. */
5615	{
5616	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5617	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
5618	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
5619	}
5620	/* Command Buffer Tail Pointer Register. */
5621	{
5622	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5623	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
5624	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
5625	}
5626	/* Event Log Head Pointer Register. */
5627	{
5628	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5629	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
5630	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
5631	}
5632	/* Event Log Tail Pointer Register. */
5633	{
5634	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5635	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
5636	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
5637	}
5638	/* Status Register. */
5639	{
5640	IOMMU_STATUS_T const Status = pThis->Status;
5641	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5642	if (fVerbose)
5643	{
5644	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5645	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5646	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5647	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5648	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5649	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5650	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5651	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5652	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5653	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5654	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5655	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5656	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5657	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5658	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5659	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5660	}
5661	}
5662	/* PPR Log Head Pointer. */
5663	{
5664	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5665	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
5666	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
5667	}
5668	/* PPR Log Tail Pointer. */
5669	{
5670	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5671	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
5672	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
5673	}
5674	/* Guest Virtual-APIC Log Head Pointer. */
5675	{
5676	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5677	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
5678	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
5679	}
5680	/* Guest Virtual-APIC Log Tail Pointer. */
5681	{
5682	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5683	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
5684	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
5685	}
5686	/* PPR Log B Head Pointer. */
5687	{
5688	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5689	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
5690	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
5691	}
5692	/* PPR Log B Tail Pointer. */
5693	{
5694	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5695	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
5696	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
5697	}
5698	/* Event Log B Head Pointer. */
5699	{
5700	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5701	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
5702	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
5703	}
5704	/* Event Log B Tail Pointer. */
5705	{
5706	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5707	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
5708	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
5709	}
5710	/* PPR Log Auto Response Register. */
5711	{
5712	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5713	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5714	if (fVerbose)
5715	{
5716	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5717	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5718	}
5719	}
5720	/* PPR Log Overflow Early Warning Indicator Register. */
5721	{
5722	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5723	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5724	if (fVerbose)
5725	{
5726	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5727	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5728	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5729	}
5730	}
5731	/* PPR Log Overflow Early Warning Indicator Register. */
5732	{
5733	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5734	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5735	if (fVerbose)
5736	{
5737	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5738	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5739	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5740	}
5741	}
5742	}
5743
5744
5745	/**
5746	* @callback_method_impl{FNSSMDEVSAVEEXEC}
5747	*/
5748	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5749	{
5750	/** @todo IOMMU: Save state. */
5751	RT_NOREF2(pDevIns, pSSM);
5752	return VERR_NOT_IMPLEMENTED;
5753	}
5754
5755
5756	/**
5757	* @callback_method_impl{FNSSMDEVLOADEXEC}
5758	*/
5759	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5760	{
5761	/** @todo IOMMU: Load state. */
5762	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
5763	return VERR_NOT_IMPLEMENTED;
5764	}
5765
5766
5767	/**
5768	* @interface_method_impl{PDMDEVREG,pfnReset}
5769	*/
5770	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
5771	{
5772	/*
5773	* Resets read-write portion of the IOMMU state.
5774	*
5775	* State data not initialized here is expected to be initialized during
5776	* device construction and remain read-only through the lifetime of the VM.
5777	*/
5778	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5779	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5780	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5781
5782	memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
5783
5784	pThis->CmdBufBaseAddr.u64 = 0;
5785	pThis->CmdBufBaseAddr.n.u4Len = 8;
5786
5787	pThis->EvtLogBaseAddr.u64 = 0;
5788	pThis->EvtLogBaseAddr.n.u4Len = 8;
5789
5790	pThis->Ctrl.u64 = 0;
5791
5792	pThis->ExclRangeBaseAddr.u64 = 0;
5793	pThis->ExclRangeLimit.u64 = 0;
5794
5795	pThis->PprLogBaseAddr.u64 = 0;
5796	pThis->PprLogBaseAddr.n.u4Len = 8;
5797
5798	pThis->HwEvtHi.u64 = 0;
5799	pThis->HwEvtLo = 0;
5800	pThis->HwEvtStatus.u64 = 0;
5801
5802	pThis->GALogBaseAddr.u64 = 0;
5803	pThis->GALogBaseAddr.n.u4Len = 8;
5804	pThis->GALogTailAddr.u64 = 0;
5805
5806	pThis->PprLogBBaseAddr.u64 = 0;
5807	pThis->PprLogBBaseAddr.n.u4Len = 8;
5808
5809	pThis->EvtLogBBaseAddr.u64 = 0;
5810	pThis->EvtLogBBaseAddr.n.u4Len = 8;
5811
5812	pThis->MsiMiscInfo.u64 = 0;
5813	pThis->PerfOptCtrl.u32 = 0;
5814
5815	pThis->XtGenIntrCtrl.u64 = 0;
5816	pThis->XtPprIntrCtrl.u64 = 0;
5817	pThis->XtGALogIntrCtrl.u64 = 0;
5818
5819	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
5820
5821	pThis->CmdBufHeadPtr.u64 = 0;
5822	pThis->CmdBufTailPtr.u64 = 0;
5823	pThis->EvtLogHeadPtr.u64 = 0;
5824	pThis->EvtLogTailPtr.u64 = 0;
5825
5826	pThis->Status.u64 = 0;
5827
5828	pThis->PprLogHeadPtr.u64 = 0;
5829	pThis->PprLogTailPtr.u64 = 0;
5830
5831	pThis->GALogHeadPtr.u64 = 0;
5832	pThis->GALogTailPtr.u64 = 0;
5833
5834	pThis->PprLogBHeadPtr.u64 = 0;
5835	pThis->PprLogBTailPtr.u64 = 0;
5836
5837	pThis->EvtLogBHeadPtr.u64 = 0;
5838	pThis->EvtLogBTailPtr.u64 = 0;
5839
5840	pThis->PprLogAutoResp.u64 = 0;
5841	pThis->PprLogOverflowEarly.u64 = 0;
5842	pThis->PprLogBOverflowEarly.u64 = 0;
5843
5844	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
5845	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
5846	}
5847
5848
5849	/**
5850	* @interface_method_impl{PDMDEVREG,pfnDestruct}
5851	*/
5852	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
5853	{
5854	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5855	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5856	LogFlowFunc(("\n"));
5857
5858	/* Close the command thread semaphore. */
5859	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
5860	{
5861	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
5862	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
5863	}
5864	return VINF_SUCCESS;
5865	}
5866
5867
5868	/**
5869	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5870	*/
5871	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5872	{
5873	NOREF(iInstance);
5874
5875	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5876	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5877	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5878	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
5879	int rc;
5880	LogFlowFunc(("\n"));
5881
5882	pThisCC->pDevInsR3 = pDevIns;
5883
5884	/*
5885	* Validate and read the configuration.
5886	*/
5887	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "Device\|Function", "");
5888
5889	uint8_t uPciDevice;
5890	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Device", &uPciDevice, 0);
5891	if (RT_FAILURE(rc))
5892	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Device\""));
5893
5894	uint8_t uPciFunction;
5895	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "Function", &uPciFunction, 2);
5896	if (RT_FAILURE(rc))
5897	return PDMDEV_SET_ERROR(pDevIns, rc, N_("IOMMU: Failed to query \"Function\""));
5898
5899	/*
5900	* Register the IOMMU with PDM.
5901	*/
5902	PDMIOMMUREGR3 IommuReg;
5903	RT_ZERO(IommuReg);
5904	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5905	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5906	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5907	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5908	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5909	rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
5910	if (RT_FAILURE(rc))
5911	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
5912	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
5913	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5914	N_("IOMMU helper version mismatch; got %#x expected %#x"),
5915	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
5916	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
5917	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5918	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
5919	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
5920
5921	/*
5922	* Initialize read-only PCI configuration space.
5923	*/
5924	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5925	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5926
5927	/* Header. */
5928	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
5929	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
5930	PDMPciDevSetCommand(pPciDev, 0); /* Command */
5931	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
5932	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
5933	PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
5934	PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
5935	PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
5936	PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
5937	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
5938	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
5939	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
5940	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
5941	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
5942
5943	/* Capability Header. */
5944	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
5945	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
5946	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
5947	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
5948	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
5949	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
5950	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
5951	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
5952	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
5953	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
5954
5955	/* Base Address Low Register. */
5956	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
5957
5958	/* Base Address High Register. */
5959	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
5960
5961	/* IOMMU Range Register. */
5962	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
5963
5964	/* Misc. Information Register 0. */
5965	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0,
5966	RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0x0) /* RO - MSI number */
5967	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 0x2) /* RO - Guest Virt. Addr size (2=48 bits) */
5968	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 0x30) /* RO - Physical Addr size (48 bits) */
5969	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 0x40) /* RO - Virt. Addr size (64 bits) */
5970	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0x0) /* RW - HT ATS reserved */
5971	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0x0)); /* RW - PPR interrupt number */
5972
5973	/* Misc. Information Register 1. */
5974	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, 0);
5975
5976	/* MSI Capability Header register. */
5977	PDMMSIREG MsiReg;
5978	RT_ZERO(MsiReg);
5979	MsiReg.cMsiVectors = 1;
5980	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
5981	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
5982	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
5983	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5984	AssertRCReturn(rc, rc);
5985
5986	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
5987	#if 0
5988	/* MSI Address Lo. */
5989	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
5990	/* MSI Address Hi. */
5991	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
5992	/* MSI Data. */
5993	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
5994	#endif
5995
5996	#if 0
5997	/** @todo IOMMU: I don't know if we need to support this, enable later if
5998	* required. */
5999	/* MSI Mapping Capability Header register. */
6000	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6001	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6002	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6003	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6004	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6005	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6006	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6007	#endif
6008
6009	/*
6010	* Register the PCI function with PDM.
6011	*/
6012	rc = PDMDevHlpPCIRegisterEx(pDevIns, pPciDev, 0 /* fFlags */, uPciDevice, uPciFunction, "amd-iommu");
6013	AssertLogRelRCReturn(rc, rc);
6014
6015	/*
6016	* Intercept PCI config. space accesses.
6017	*/
6018	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6019	AssertLogRelRCReturn(rc, rc);
6020
6021	/*
6022	* Create the MMIO region.
6023	* Mapping of the region is done when software configures it via PCI config space.
6024	*/
6025	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6026	NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
6027	"AMD-IOMMU", &pThis->hMmio);
6028	AssertLogRelRCReturn(rc, rc);
6029
6030	/*
6031	* Register saved state.
6032	*/
6033	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
6034	NULL, NULL, NULL,
6035	NULL, iommuAmdR3SaveExec, NULL,
6036	NULL, iommuAmdR3LoadExec, NULL);
6037	AssertLogRelRCReturn(rc, rc);
6038
6039	/*
6040	* Register debugger info item.
6041	*/
6042	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6043	AssertLogRelRCReturn(rc, rc);
6044
6045	/*
6046	* Create the command thread and its event semaphore.
6047	*/
6048	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
6049	0 /* cbStack */, RTTHREADTYPE_IO, "AMD-IOMMU");
6050	AssertLogRelRCReturn(rc, rc);
6051
6052	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
6053	AssertLogRelRCReturn(rc, rc);
6054
6055	/*
6056	* Initialize read-only registers.
6057	*/
6058	/** @todo Don't remove the =0 assignment for now. It's just there so it's easier
6059	* for me to see existing features that we might want to implement. Do it
6060	* later. */
6061	pThis->ExtFeat.u64 = 0;
6062	pThis->ExtFeat.n.u1PrefetchSup = 0;
6063	pThis->ExtFeat.n.u1PprSup = 0;
6064	pThis->ExtFeat.n.u1X2ApicSup = 0;
6065	pThis->ExtFeat.n.u1NoExecuteSup = 0;
6066	pThis->ExtFeat.n.u1GstTranslateSup = 0;
6067	pThis->ExtFeat.n.u1InvAllSup = 0;
6068	pThis->ExtFeat.n.u1GstVirtApicSup = 0;
6069	pThis->ExtFeat.n.u1HwErrorSup = 1;
6070	pThis->ExtFeat.n.u1PerfCounterSup = 0;
6071	pThis->ExtFeat.n.u2HostAddrTranslateSize = IOMMU_MAX_HOST_PT_LEVEL;
6072	pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
6073	pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
6074	pThis->ExtFeat.n.u2SmiFilterSup = 0;
6075	pThis->ExtFeat.n.u3SmiFilterCount = 0;
6076	pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
6077	pThis->ExtFeat.n.u2DualPprLogSup = 0;
6078	pThis->ExtFeat.n.u2DualEvtLogSup = 0;
6079	pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
6080	pThis->ExtFeat.n.u1UserSupervisorSup = 0;
6081	AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
6082	pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
6083	pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
6084	pThis->ExtFeat.n.u1PprAutoRespSup = 0;
6085	pThis->ExtFeat.n.u2MarcSup = 0;
6086	pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
6087	pThis->ExtFeat.n.u1PerfOptSup = 0;
6088	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
6089	pThis->ExtFeat.n.u1GstIoSup = 0;
6090	pThis->ExtFeat.n.u1HostAccessSup = 0;
6091	pThis->ExtFeat.n.u1EnhancedPprSup = 0;
6092	pThis->ExtFeat.n.u1AttrForwardSup = 0;
6093	pThis->ExtFeat.n.u1HostDirtySup = 0;
6094	pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
6095	pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
6096	pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
6097
6098	pThis->RsvdReg = 0;
6099
6100	pThis->DevSpecificFeat.u64 = 0;
6101	pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
6102	pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
6103
6104	pThis->DevSpecificCtrl.u64 = 0;
6105	pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
6106	pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
6107
6108	pThis->DevSpecificStatus.u64 = 0;
6109	pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
6110	pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
6111
6112	/*
6113	* Initialize parts of the IOMMU state as it would during reset.
6114	* Must be called -after- initializing PCI config. space registers.
6115	*/
6116	iommuAmdR3Reset(pDevIns);
6117
6118	return VINF_SUCCESS;
6119	}
6120
6121	# else /* !IN_RING3 */
6122
6123	/**
6124	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
6125	*/
6126	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
6127	{
6128	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6129	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6130	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
6131
6132	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
6133
6134	/* Set up the MMIO RZ handlers. */
6135	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
6136	AssertRCReturn(rc, rc);
6137
6138	/* Set up the IOMMU RZ callbacks. */
6139	PDMIOMMUREGCC IommuReg;
6140	RT_ZERO(IommuReg);
6141	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6142	IommuReg.idxIommu = pThis->idxIommu;
6143	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
6144	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
6145	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
6146	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6147	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
6148	AssertRCReturn(rc, rc);
6149
6150	return VINF_SUCCESS;
6151	}
6152
6153	# endif /* !IN_RING3 */
6154
6155	/**
6156	* The device registration structure.
6157	*/
6158	const PDMDEVREG g_DeviceIommuAmd =
6159	{
6160	/* .u32Version = */ PDM_DEVREG_VERSION,
6161	/* .uReserved0 = */ 0,
6162	/* .szName = */ "iommu-amd",
6163	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
6164	/* .fClass = / PDM_DEVREG_CLASS_BUS_ISA, / Instantiate after PDM_DEVREG_CLASS_BUS_PCI */
6165	/* .cMaxInstances = */ ~0U,
6166	/* .uSharedVersion = */ 42,
6167	/* .cbInstanceShared = */ sizeof(IOMMU),
6168	/* .cbInstanceCC = */ sizeof(IOMMUCC),
6169	/* .cbInstanceRC = */ sizeof(IOMMURC),
6170	/* .cMaxPciDevices = */ 1,
6171	/* .cMaxMsixVectors = */ 0,
6172	/* .pszDescription = */ "IOMMU (AMD)",
6173	#if defined(IN_RING3)
6174	/* .pszRCMod = */ "VBoxDDRC.rc",
6175	/* .pszR0Mod = */ "VBoxDDR0.r0",
6176	/* .pfnConstruct = */ iommuAmdR3Construct,
6177	/* .pfnDestruct = */ iommuAmdR3Destruct,
6178	/* .pfnRelocate = */ NULL,
6179	/* .pfnMemSetup = */ NULL,
6180	/* .pfnPowerOn = */ NULL,
6181	/* .pfnReset = */ iommuAmdR3Reset,
6182	/* .pfnSuspend = */ NULL,
6183	/* .pfnResume = */ NULL,
6184	/* .pfnAttach = */ NULL,
6185	/* .pfnDetach = */ NULL,
6186	/* .pfnQueryInterface = */ NULL,
6187	/* .pfnInitComplete = */ NULL,
6188	/* .pfnPowerOff = */ NULL,
6189	/* .pfnSoftReset = */ NULL,
6190	/* .pfnReserved0 = */ NULL,
6191	/* .pfnReserved1 = */ NULL,
6192	/* .pfnReserved2 = */ NULL,
6193	/* .pfnReserved3 = */ NULL,
6194	/* .pfnReserved4 = */ NULL,
6195	/* .pfnReserved5 = */ NULL,
6196	/* .pfnReserved6 = */ NULL,
6197	/* .pfnReserved7 = */ NULL,
6198	#elif defined(IN_RING0)
6199	/* .pfnEarlyConstruct = */ NULL,
6200	/* .pfnConstruct = */ iommuAmdRZConstruct,
6201	/* .pfnDestruct = */ NULL,
6202	/* .pfnFinalDestruct = */ NULL,
6203	/* .pfnRequest = */ NULL,
6204	/* .pfnReserved0 = */ NULL,
6205	/* .pfnReserved1 = */ NULL,
6206	/* .pfnReserved2 = */ NULL,
6207	/* .pfnReserved3 = */ NULL,
6208	/* .pfnReserved4 = */ NULL,
6209	/* .pfnReserved5 = */ NULL,
6210	/* .pfnReserved6 = */ NULL,
6211	/* .pfnReserved7 = */ NULL,
6212	#elif defined(IN_RC)
6213	/* .pfnConstruct = */ iommuAmdRZConstruct,
6214	/* .pfnReserved0 = */ NULL,
6215	/* .pfnReserved1 = */ NULL,
6216	/* .pfnReserved2 = */ NULL,
6217	/* .pfnReserved3 = */ NULL,
6218	/* .pfnReserved4 = */ NULL,
6219	/* .pfnReserved5 = */ NULL,
6220	/* .pfnReserved6 = */ NULL,
6221	/* .pfnReserved7 = */ NULL,
6222	#else
6223	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
6224	#endif
6225	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
6226	};
6227
6228	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
6229

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 84677

Download in other formats: