DevIommuAmd.cpp@ 85726

Last change on this file since 85726 was 85640, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 Comments.
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1	/* $Id: DevIommuAmd.cpp 85640 2020-08-07 09:34:39Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/msi.h>
24	#include <VBox/vmm/pdmdev.h>
25	#include <VBox/AssertGuest.h>
26
27	#include "VBoxDD.h"
28	#include <iprt/x86.h>
29	#include <iprt/string.h>
30
31
32	/*********************************************************************************************************************************
33	* Defined Constants And Macros *
34	*********************************************************************************************************************************/
35	/**
36	* @name PCI configuration register offsets.
37	* In accordance with the AMD spec.
38	* @{
39	*/
40	#define IOMMU_PCI_OFF_CAP_HDR 0x40
41	#define IOMMU_PCI_OFF_BASE_ADDR_REG_LO 0x44
42	#define IOMMU_PCI_OFF_BASE_ADDR_REG_HI 0x48
43	#define IOMMU_PCI_OFF_RANGE_REG 0x4c
44	#define IOMMU_PCI_OFF_MISCINFO_REG_0 0x50
45	#define IOMMU_PCI_OFF_MISCINFO_REG_1 0x54
46	#define IOMMU_PCI_OFF_MSI_CAP_HDR 0x64
47	#define IOMMU_PCI_OFF_MSI_ADDR_LO 0x68
48	#define IOMMU_PCI_OFF_MSI_ADDR_HI 0x6c
49	#define IOMMU_PCI_OFF_MSI_DATA 0x70
50	#define IOMMU_PCI_OFF_MSI_MAP_CAP_HDR 0x74
51	/** @} */
52
53	/**
54	* @name MMIO register offsets.
55	* In accordance with the AMD spec.
56	* @{
57	*/
58	#define IOMMU_MMIO_OFF_DEV_TAB_BAR 0x00
59	#define IOMMU_MMIO_OFF_CMD_BUF_BAR 0x08
60	#define IOMMU_MMIO_OFF_EVT_LOG_BAR 0x10
61	#define IOMMU_MMIO_OFF_CTRL 0x18
62	#define IOMMU_MMIO_OFF_EXCL_BAR 0x20
63	#define IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT 0x28
64	#define IOMMU_MMIO_OFF_EXT_FEAT 0x30
65
66	#define IOMMU_MMIO_OFF_PPR_LOG_BAR 0x38
67	#define IOMMU_MMIO_OFF_HW_EVT_HI 0x40
68	#define IOMMU_MMIO_OFF_HW_EVT_LO 0x48
69	#define IOMMU_MMIO_OFF_HW_EVT_STATUS 0x50
70
71	#define IOMMU_MMIO_OFF_SMI_FLT_FIRST 0x60
72	#define IOMMU_MMIO_OFF_SMI_FLT_LAST 0xd8
73
74	#define IOMMU_MMIO_OFF_GALOG_BAR 0xe0
75	#define IOMMU_MMIO_OFF_GALOG_TAIL_ADDR 0xe8
76
77	#define IOMMU_MMIO_OFF_PPR_LOG_B_BAR 0xf0
78	#define IOMMU_MMIO_OFF_PPR_EVT_B_BAR 0xf8
79
80	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST 0x100
81	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_1 0x100
82	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_2 0x108
83	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_3 0x110
84	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_4 0x118
85	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_5 0x120
86	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_6 0x128
87	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_7 0x130
88	#define IOMMU_MMIO_OFF_DEV_TAB_SEG_LAST 0x130
89
90	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT 0x138
91	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL 0x140
92	#define IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS 0x148
93
94	#define IOMMU_MMIO_OFF_MSI_VECTOR_0 0x150
95	#define IOMMU_MMIO_OFF_MSI_VECTOR_1 0x154
96	#define IOMMU_MMIO_OFF_MSI_CAP_HDR 0x158
97	#define IOMMU_MMIO_OFF_MSI_ADDR_LO 0x15c
98	#define IOMMU_MMIO_OFF_MSI_ADDR_HI 0x160
99	#define IOMMU_MMIO_OFF_MSI_DATA 0x164
100	#define IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR 0x168
101
102	#define IOMMU_MMIO_OFF_PERF_OPT_CTRL 0x16c
103
104	#define IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL 0x170
105	#define IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL 0x178
106	#define IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL 0x180
107
108	#define IOMMU_MMIO_OFF_MARC_APER_BAR_0 0x200
109	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_0 0x208
110	#define IOMMU_MMIO_OFF_MARC_APER_LEN_0 0x210
111	#define IOMMU_MMIO_OFF_MARC_APER_BAR_1 0x218
112	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_1 0x220
113	#define IOMMU_MMIO_OFF_MARC_APER_LEN_1 0x228
114	#define IOMMU_MMIO_OFF_MARC_APER_BAR_2 0x230
115	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_2 0x238
116	#define IOMMU_MMIO_OFF_MARC_APER_LEN_2 0x240
117	#define IOMMU_MMIO_OFF_MARC_APER_BAR_3 0x248
118	#define IOMMU_MMIO_OFF_MARC_APER_RELOC_3 0x250
119	#define IOMMU_MMIO_OFF_MARC_APER_LEN_3 0x258
120
121	#define IOMMU_MMIO_OFF_RSVD_REG 0x1ff8
122
123	#define IOMMU_MMIO_CMD_BUF_HEAD_PTR 0x2000
124	#define IOMMU_MMIO_CMD_BUF_TAIL_PTR 0x2008
125	#define IOMMU_MMIO_EVT_LOG_HEAD_PTR 0x2010
126	#define IOMMU_MMIO_EVT_LOG_TAIL_PTR 0x2018
127
128	#define IOMMU_MMIO_OFF_STATUS 0x2020
129
130	#define IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR 0x2030
131	#define IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR 0x2038
132
133	#define IOMMU_MMIO_OFF_GALOG_HEAD_PTR 0x2040
134	#define IOMMU_MMIO_OFF_GALOG_TAIL_PTR 0x2048
135
136	#define IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR 0x2050
137	#define IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR 0x2058
138
139	#define IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR 0x2070
140	#define IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR 0x2078
141
142	#define IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP 0x2080
143	#define IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY 0x2088
144	#define IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY 0x2090
145	/** @} */
146
147	/**
148	* @name MMIO register-access table offsets.
149	* Each table [first..last] (both inclusive) represents the range of registers
150	* covered by a distinct register-access table. This is done due to arbitrary large
151	* gaps in the MMIO register offsets themselves.
152	* @{
153	*/
154	#define IOMMU_MMIO_OFF_TABLE_0_FIRST 0x00
155	#define IOMMU_MMIO_OFF_TABLE_0_LAST 0x258
156
157	#define IOMMU_MMIO_OFF_TABLE_1_FIRST 0x1ff8
158	#define IOMMU_MMIO_OFF_TABLE_1_LAST 0x2090
159	/** @} */
160
161	/**
162	* @name Commands.
163	* In accordance with the AMD spec.
164	* @{
165	*/
166	#define IOMMU_CMD_COMPLETION_WAIT 0x01
167	#define IOMMU_CMD_INV_DEV_TAB_ENTRY 0x02
168	#define IOMMU_CMD_INV_IOMMU_PAGES 0x03
169	#define IOMMU_CMD_INV_IOTLB_PAGES 0x04
170	#define IOMMU_CMD_INV_INTR_TABLE 0x05
171	#define IOMMU_CMD_PREFETCH_IOMMU_PAGES 0x06
172	#define IOMMU_CMD_COMPLETE_PPR_REQ 0x07
173	#define IOMMU_CMD_INV_IOMMU_ALL 0x08
174	/** @} */
175
176	/**
177	* @name Event codes.
178	* In accordance with the AMD spec.
179	* @{
180	*/
181	#define IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY 0x01
182	#define IOMMU_EVT_IO_PAGE_FAULT 0x02
183	#define IOMMU_EVT_DEV_TAB_HW_ERROR 0x03
184	#define IOMMU_EVT_PAGE_TAB_HW_ERROR 0x04
185	#define IOMMU_EVT_ILLEGAL_CMD_ERROR 0x05
186	#define IOMMU_EVT_COMMAND_HW_ERROR 0x06
187	#define IOMMU_EVT_IOTLB_INV_TIMEOUT 0x07
188	#define IOMMU_EVT_INVALID_DEV_REQ 0x08
189	#define IOMMU_EVT_INVALID_PPR_REQ 0x09
190	#define IOMMU_EVT_EVENT_COUNTER_ZERO 0x10
191	#define IOMMU_EVT_GUEST_EVENT_FAULT 0x11
192	/** @} */
193
194	/**
195	* @name IOMMU Capability Header.
196	* In accordance with the AMD spec.
197	* @{
198	*/
199	/** CapId: Capability ID. */
200	#define IOMMU_BF_CAPHDR_CAP_ID_SHIFT 0
201	#define IOMMU_BF_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
202	/** CapPtr: Capability Pointer. */
203	#define IOMMU_BF_CAPHDR_CAP_PTR_SHIFT 8
204	#define IOMMU_BF_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
205	/** CapType: Capability Type. */
206	#define IOMMU_BF_CAPHDR_CAP_TYPE_SHIFT 16
207	#define IOMMU_BF_CAPHDR_CAP_TYPE_MASK UINT32_C(0x00070000)
208	/** CapRev: Capability Revision. */
209	#define IOMMU_BF_CAPHDR_CAP_REV_SHIFT 19
210	#define IOMMU_BF_CAPHDR_CAP_REV_MASK UINT32_C(0x00f80000)
211	/** IoTlbSup: IO TLB Support. */
212	#define IOMMU_BF_CAPHDR_IOTLB_SUP_SHIFT 24
213	#define IOMMU_BF_CAPHDR_IOTLB_SUP_MASK UINT32_C(0x01000000)
214	/** HtTunnel: HyperTransport Tunnel translation support. */
215	#define IOMMU_BF_CAPHDR_HT_TUNNEL_SHIFT 25
216	#define IOMMU_BF_CAPHDR_HT_TUNNEL_MASK UINT32_C(0x02000000)
217	/** NpCache: Not Present table entries Cached. */
218	#define IOMMU_BF_CAPHDR_NP_CACHE_SHIFT 26
219	#define IOMMU_BF_CAPHDR_NP_CACHE_MASK UINT32_C(0x04000000)
220	/** EFRSup: Extended Feature Register (EFR) Supported. */
221	#define IOMMU_BF_CAPHDR_EFR_SUP_SHIFT 27
222	#define IOMMU_BF_CAPHDR_EFR_SUP_MASK UINT32_C(0x08000000)
223	/** CapExt: Miscellaneous Information Register Supported . */
224	#define IOMMU_BF_CAPHDR_CAP_EXT_SHIFT 28
225	#define IOMMU_BF_CAPHDR_CAP_EXT_MASK UINT32_C(0x10000000)
226	/** Bits 31:29 reserved. */
227	#define IOMMU_BF_CAPHDR_RSVD_29_31_SHIFT 29
228	#define IOMMU_BF_CAPHDR_RSVD_29_31_MASK UINT32_C(0xe0000000)
229	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_CAPHDR_, UINT32_C(0), UINT32_MAX,
230	(CAP_ID, CAP_PTR, CAP_TYPE, CAP_REV, IOTLB_SUP, HT_TUNNEL, NP_CACHE, EFR_SUP, CAP_EXT, RSVD_29_31));
231	/** @} */
232
233	/**
234	* @name IOMMU Base Address Low Register.
235	* In accordance with the AMD spec.
236	* @{
237	*/
238	/** Enable: Enables access to the address specified in the Base Address Register. */
239	#define IOMMU_BF_BASEADDR_LO_ENABLE_SHIFT 0
240	#define IOMMU_BF_BASEADDR_LO_ENABLE_MASK UINT32_C(0x00000001)
241	/** Bits 13:1 reserved. */
242	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_SHIFT 1
243	#define IOMMU_BF_BASEADDR_LO_RSVD_1_13_MASK UINT32_C(0x00003ffe)
244	/** Base Address[31:14]: Low Base address of IOMMU MMIO control registers. */
245	#define IOMMU_BF_BASEADDR_LO_ADDR_SHIFT 14
246	#define IOMMU_BF_BASEADDR_LO_ADDR_MASK UINT32_C(0xffffc000)
247	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_BASEADDR_LO_, UINT32_C(0), UINT32_MAX,
248	(ENABLE, RSVD_1_13, ADDR));
249	/** @} */
250
251	/**
252	* @name IOMMU Range Register.
253	* In accordance with the AMD spec.
254	* @{
255	*/
256	/** UnitID: HyperTransport Unit ID. */
257	#define IOMMU_BF_RANGE_UNIT_ID_SHIFT 0
258	#define IOMMU_BF_RANGE_UNIT_ID_MASK UINT32_C(0x0000001f)
259	/** Bits 6:5 reserved. */
260	#define IOMMU_BF_RANGE_RSVD_5_6_SHIFT 5
261	#define IOMMU_BF_RANGE_RSVD_5_6_MASK UINT32_C(0x00000060)
262	/** RngValid: Range valid. */
263	#define IOMMU_BF_RANGE_VALID_SHIFT 7
264	#define IOMMU_BF_RANGE_VALID_MASK UINT32_C(0x00000080)
265	/** BusNumber: Device range bus number. */
266	#define IOMMU_BF_RANGE_BUS_NUMBER_SHIFT 8
267	#define IOMMU_BF_RANGE_BUS_NUMBER_MASK UINT32_C(0x0000ff00)
268	/** First Device. */
269	#define IOMMU_BF_RANGE_FIRST_DEVICE_SHIFT 16
270	#define IOMMU_BF_RANGE_FIRST_DEVICE_MASK UINT32_C(0x00ff0000)
271	/** Last Device. */
272	#define IOMMU_BF_RANGE_LAST_DEVICE_SHIFT 24
273	#define IOMMU_BF_RANGE_LAST_DEVICE_MASK UINT32_C(0xff000000)
274	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_RANGE_, UINT32_C(0), UINT32_MAX,
275	(UNIT_ID, RSVD_5_6, VALID, BUS_NUMBER, FIRST_DEVICE, LAST_DEVICE));
276	/** @} */
277
278	/**
279	* @name IOMMU Miscellaneous Information Register 0.
280	* In accordance with the AMD spec.
281	* @{
282	*/
283	/** MsiNum: MSI message number. */
284	#define IOMMU_BF_MISCINFO_0_MSI_NUM_SHIFT 0
285	#define IOMMU_BF_MISCINFO_0_MSI_NUM_MASK UINT32_C(0x0000001f)
286	/** GvaSize: Guest Virtual Address Size. */
287	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_SHIFT 5
288	#define IOMMU_BF_MISCINFO_0_GVA_SIZE_MASK UINT32_C(0x000000e0)
289	/** PaSize: Physical Address Size. */
290	#define IOMMU_BF_MISCINFO_0_PA_SIZE_SHIFT 8
291	#define IOMMU_BF_MISCINFO_0_PA_SIZE_MASK UINT32_C(0x00007f00)
292	/** VaSize: Virtual Address Size. */
293	#define IOMMU_BF_MISCINFO_0_VA_SIZE_SHIFT 15
294	#define IOMMU_BF_MISCINFO_0_VA_SIZE_MASK UINT32_C(0x003f8000)
295	/** HtAtsResv: HyperTransport ATS Response Address range Reserved. */
296	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_SHIFT 22
297	#define IOMMU_BF_MISCINFO_0_HT_ATS_RESV_MASK UINT32_C(0x00400000)
298	/** Bits 26:23 reserved. */
299	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_SHIFT 23
300	#define IOMMU_BF_MISCINFO_0_RSVD_23_26_MASK UINT32_C(0x07800000)
301	/** MsiNumPPR: Peripheral Page Request MSI message number. */
302	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_SHIFT 27
303	#define IOMMU_BF_MISCINFO_0_MSI_NUM_PPR_MASK UINT32_C(0xf8000000)
304	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_0_, UINT32_C(0), UINT32_MAX,
305	(MSI_NUM, GVA_SIZE, PA_SIZE, VA_SIZE, HT_ATS_RESV, RSVD_23_26, MSI_NUM_PPR));
306	/** @} */
307
308	/**
309	* @name IOMMU Miscellaneous Information Register 1.
310	* In accordance with the AMD spec.
311	* @{
312	*/
313	/** MsiNumGA: MSI message number for guest virtual-APIC log. */
314	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_SHIFT 0
315	#define IOMMU_BF_MISCINFO_1_MSI_NUM_GA_MASK UINT32_C(0x0000001f)
316	/** Bits 31:5 reserved. */
317	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_SHIFT 5
318	#define IOMMU_BF_MISCINFO_1_RSVD_5_31_MASK UINT32_C(0xffffffe0)
319	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MISCINFO_1_, UINT32_C(0), UINT32_MAX,
320	(MSI_NUM_GA, RSVD_5_31));
321	/** @} */
322
323	/**
324	* @name MSI Capability Header Register.
325	* In accordance with the AMD spec.
326	* @{
327	*/
328	/** MsiCapId: Capability ID. */
329	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_SHIFT 0
330	#define IOMMU_BF_MSI_CAP_HDR_CAP_ID_MASK UINT32_C(0x000000ff)
331	/** MsiCapPtr: Pointer (PCI config offset) to the next capability. */
332	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_SHIFT 8
333	#define IOMMU_BF_MSI_CAP_HDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
334	/** MsiEn: Message Signal Interrupt enable. */
335	#define IOMMU_BF_MSI_CAP_HDR_EN_SHIFT 16
336	#define IOMMU_BF_MSI_CAP_HDR_EN_MASK UINT32_C(0x00010000)
337	/** MsiMultMessCap: MSI Multi-Message Capability. */
338	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_SHIFT 17
339	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_CAP_MASK UINT32_C(0x000e0000)
340	/** MsiMultMessEn: MSI Mult-Message Enable. */
341	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_SHIFT 20
342	#define IOMMU_BF_MSI_CAP_HDR_MULTMESS_EN_MASK UINT32_C(0x00700000)
343	/** Msi64BitEn: MSI 64-bit Enabled. */
344	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_SHIFT 23
345	#define IOMMU_BF_MSI_CAP_HDR_64BIT_EN_MASK UINT32_C(0x00800000)
346	/** Bits 31:24 reserved. */
347	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_SHIFT 24
348	#define IOMMU_BF_MSI_CAP_HDR_RSVD_24_31_MASK UINT32_C(0xff000000)
349	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_CAP_HDR_, UINT32_C(0), UINT32_MAX,
350	(CAP_ID, CAP_PTR, EN, MULTMESS_CAP, MULTMESS_EN, 64BIT_EN, RSVD_24_31));
351	/** @} */
352
353	/**
354	* @name MSI Mapping Capability Header Register.
355	* In accordance with the AMD spec.
356	* @{
357	*/
358	/** MsiMapCapId: Capability ID. */
359	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_SHIFT 0
360	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID_MASK UINT32_C(0x000000ff)
361	/** MsiMapCapPtr: Pointer (PCI config offset) to the next capability. */
362	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_SHIFT 8
363	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR_MASK UINT32_C(0x0000ff00)
364	/** MsiMapEn: MSI mapping capability enable. */
365	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_SHIFT 16
366	#define IOMMU_BF_MSI_MAP_CAPHDR_EN_MASK UINT32_C(0x00010000)
367	/** MsiMapFixd: MSI interrupt mapping range is not programmable. */
368	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_SHIFT 17
369	#define IOMMU_BF_MSI_MAP_CAPHDR_FIXED_MASK UINT32_C(0x00020000)
370	/** Bits 18:28 reserved. */
371	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_SHIFT 18
372	#define IOMMU_BF_MSI_MAP_CAPHDR_RSVD_18_28_MASK UINT32_C(0x07fc0000)
373	/** MsiMapCapType: MSI mapping capability. */
374	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_SHIFT 27
375	#define IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE_MASK UINT32_C(0xf8000000)
376	RT_BF_ASSERT_COMPILE_CHECKS(IOMMU_BF_MSI_MAP_CAPHDR_, UINT32_C(0), UINT32_MAX,
377	(CAP_ID, CAP_PTR, EN, FIXED, RSVD_18_28, CAP_TYPE));
378	/** @} */
379
380	/**
381	* @name IOMMU Status Register Bits.
382	* In accordance with the AMD spec.
383	* @{
384	*/
385	/** EventOverflow: Event log overflow. */
386	#define IOMMU_STATUS_EVT_LOG_OVERFLOW RT_BIT_64(0)
387	/** EventLogInt: Event log interrupt. */
388	#define IOMMU_STATUS_EVT_LOG_INTR RT_BIT_64(1)
389	/** ComWaitInt: Completion wait interrupt. */
390	#define IOMMU_STATUS_COMPLETION_WAIT_INTR RT_BIT_64(2)
391	/** EventLogRun: Event log is running. */
392	#define IOMMU_STATUS_EVT_LOG_RUNNING RT_BIT_64(3)
393	/** CmdBufRun: Command buffer is running. */
394	#define IOMMU_STATUS_CMD_BUF_RUNNING RT_BIT_64(4)
395	/** PprOverflow: Peripheral page request log overflow. */
396	#define IOMMU_STATUS_PPR_LOG_OVERFLOW RT_BIT_64(5)
397	/** PprInt: Peripheral page request log interrupt. */
398	#define IOMMU_STATUS_PPR_LOG_INTR RT_BIT_64(6)
399	/** PprLogRun: Peripheral page request log is running. */
400	#define IOMMU_STATUS_PPR_LOG_RUN RT_BIT_64(7)
401	/** GALogRun: Guest virtual-APIC log is running. */
402	#define IOMMU_STATUS_GA_LOG_RUN RT_BIT_64(8)
403	/** GALOverflow: Guest virtual-APIC log overflow. */
404	#define IOMMU_STATUS_GA_LOG_OVERFLOW RT_BIT_64(9)
405	/** GAInt: Guest virtual-APIC log interrupt. */
406	#define IOMMU_STATUS_GA_LOG_INTR RT_BIT_64(10)
407	/** PprOvrflwB: PPR Log B overflow. */
408	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW RT_BIT_64(11)
409	/** PprLogActive: PPR Log B is active. */
410	#define IOMMU_STATUS_PPR_LOG_B_ACTIVE RT_BIT_64(12)
411	/** EvtOvrflwB: Event log B overflow. */
412	#define IOMMU_STATUS_EVT_LOG_B_OVERFLOW RT_BIT_64(15)
413	/** EventLogActive: Event log B active. */
414	#define IOMMU_STATUS_EVT_LOG_B_ACTIVE RT_BIT_64(16)
415	/** PprOvrflwEarlyB: PPR log B overflow early warning. */
416	#define IOMMU_STATUS_PPR_LOG_B_OVERFLOW_EARLY RT_BIT_64(17)
417	/** PprOverflowEarly: PPR log overflow early warning. */
418	#define IOMMU_STATUS_PPR_LOG_OVERFLOW_EARLY RT_BIT_64(18)
419	/** @} */
420
421	/** @name IOMMU_IO_PERM_XXX: IOMMU I/O access permissions bits.
422	* In accordance with the AMD spec.
423	*
424	* These values match the shifted values of the IR and IW field of the DTE and the
425	* PTE, PDE of the I/O page tables.
426	*
427	* @{ */
428	#define IOMMU_IO_PERM_NONE (0)
429	#define IOMMU_IO_PERM_READ RT_BIT_64(0)
430	#define IOMMU_IO_PERM_WRITE RT_BIT_64(1)
431	#define IOMMU_IO_PERM_READ_WRITE (IOMMU_IO_PERM_READ \| IOMMU_IO_PERM_WRITE)
432	#define IOMMU_IO_PERM_SHIFT 61
433	#define IOMMU_IO_PERM_MASK 0x3
434	/** @} */
435
436	/** @name SYSMGT_TYPE_XXX: System Management Message Enable Types.
437	* In accordance with the AMD spec.
438	* @{ */
439	#define SYSMGTTYPE_DMA_DENY (0)
440	#define SYSMGTTYPE_MSG_ALL_ALLOW (1)
441	#define SYSMGTTYPE_MSG_INT_ALLOW (2)
442	#define SYSMGTTYPE_DMA_ALLOW (3)
443	/** @} */
444
445	/** @name IOMMU_INTR_CTRL_XX: DTE::IntCtl field values.
446	* These are control bits for handling fixed and arbitrated interrupts.
447	* In accordance with the AMD spec.
448	* @{ */
449	#define IOMMU_INTR_CTRL_TARGET_ABORT (0)
450	#define IOMMU_INTR_CTRL_FWD_UNMAPPED (1)
451	#define IOMMU_INTR_CTRL_REMAP (2)
452	#define IOMMU_INTR_CTRL_RSVD (3)
453	/** @} */
454
455	/** @name Miscellaneous IOMMU defines.
456	* @{ */
457	/** Log prefix string. */
458	#define IOMMU_LOG_PFX "AMD_IOMMU"
459	/** The current saved state version. */
460	#define IOMMU_SAVED_STATE_VERSION 1
461	/** AMD's vendor ID. */
462	#define IOMMU_PCI_VENDOR_ID 0x1022
463	/** VirtualBox IOMMU device ID. */
464	#define IOMMU_PCI_DEVICE_ID 0xc0de
465	/** VirtualBox IOMMU device revision ID. */
466	#define IOMMU_PCI_REVISION_ID 0x01
467	/** Size of the MMIO region in bytes. */
468	#define IOMMU_MMIO_REGION_SIZE _16K
469	/** Number of device table segments supported (power of 2). */
470	#define IOMMU_MAX_DEV_TAB_SEGMENTS 3
471	/** Maximum host address translation level supported (inclusive). NOTE! If you
472	* change this make sure to change the value in ACPI tables (DevACPI.cpp) */
473	#define IOMMU_MAX_HOST_PT_LEVEL 6
474	/** The IOTLB entry magic. */
475	#define IOMMU_IOTLBE_MAGIC 0x10acce55
476	/** The device-specific feature major revision. */
477	#define IOMMU_DEVSPEC_FEAT_MAJOR_VERSION 0x1
478	/** The device-specific feature minor revision. */
479	#define IOMMU_DEVSPEC_FEAT_MINOR_VERSION 0x0
480	/** The device-specific control major revision. */
481	#define IOMMU_DEVSPEC_CTRL_MAJOR_VERSION 0x1
482	/** The device-specific control minor revision. */
483	#define IOMMU_DEVSPEC_CTRL_MINOR_VERSION 0x0
484	/** The device-specific status major revision. */
485	#define IOMMU_DEVSPEC_STATUS_MAJOR_VERSION 0x1
486	/** The device-specific status minor revision. */
487	#define IOMMU_DEVSPEC_STATUS_MINOR_VERSION 0x0
488	/** @} */
489
490	/**
491	* Acquires the IOMMU PDM lock.
492	* This will make a long jump to ring-3 to acquire the lock if necessary.
493	*/
494	#define IOMMU_LOCK(a_pDevIns) \
495	do { \
496	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
497	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
498	{ /* likely */ } \
499	else \
500	return rcLock; \
501	} while (0)
502
503	/**
504	* Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
505	* This will make a long jump to ring-3 to acquire the lock if necessary.
506	*/
507	#define IOMMU_LOCK_NORET(a_pDevIns) \
508	do { \
509	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
510	AssertRC(rcLock); \
511	} while (0)
512
513	/**
514	* Releases the IOMMU PDM lock.
515	*/
516	#define IOMMU_UNLOCK(a_pDevIns) \
517	do { \
518	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
519	} while (0)
520
521	/**
522	* Asserts that the critsect is owned by this thread.
523	*/
524	#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
525	do { \
526	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
527	} while (0)
528
529	/**
530	* Asserts that the critsect is not owned by this thread.
531	*/
532	#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
533	do { \
534	Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
535	} while (0)
536
537	/**
538	* Gets the device table size given the size field.
539	*/
540	#define IOMMU_GET_DEV_TAB_SIZE(a_uSize) (((a_uSize) + 1) << X86_PAGE_4K_SHIFT)
541
542
543	/*********************************************************************************************************************************
544	* Structures and Typedefs *
545	*********************************************************************************************************************************/
546	/**
547	* The Device ID.
548	* In accordance with VirtualBox's PCI configuration.
549	*/
550	typedef union
551	{
552	struct
553	{
554	uint16_t u3Function : 3; /*< Bits 2:0 - Function. /
555	uint16_t u9Device : 9; /*< Bits 11:3 - Device. /
556	uint16_t u4Bus : 4; /*< Bits 15:12 - Bus. /
557	} n;
558	/** The unsigned integer view. */
559	uint16_t u;
560	} DEVICE_ID_T;
561	AssertCompileSize(DEVICE_ID_T, 2);
562
563	/**
564	* Device Table Entry (DTE).
565	* In accordance with the AMD spec.
566	*/
567	typedef union
568	{
569	struct
570	{
571	RT_GCC_EXTENSION uint64_t u1Valid : 1; /*< Bit 0 - V: Valid. /
572	RT_GCC_EXTENSION uint64_t u1TranslationValid : 1; /*< Bit 1 - TV: Translation information Valid. /
573	RT_GCC_EXTENSION uint64_t u5Rsvd0 : 5; /*< Bits 6:2 - Reserved. /
574	RT_GCC_EXTENSION uint64_t u2Had : 2; /*< Bits 8:7 - HAD: Host Access Dirty. /
575	RT_GCC_EXTENSION uint64_t u3Mode : 3; /*< Bits 11:9 - Mode: Paging mode. /
576	RT_GCC_EXTENSION uint64_t u40PageTableRootPtrLo : 40; /*< Bits 51:12 - Page Table Root Pointer. /
577	RT_GCC_EXTENSION uint64_t u1Ppr : 1; /*< Bit 52 - PPR: Peripheral Page Request. /
578	RT_GCC_EXTENSION uint64_t u1GstPprRespPasid : 1; /*< Bit 53 - GRPR: Guest PPR Response with PASID. /
579	RT_GCC_EXTENSION uint64_t u1GstIoValid : 1; /*< Bit 54 - GIoV: Guest I/O Protection Valid. /
580	RT_GCC_EXTENSION uint64_t u1GstTranslateValid : 1; /*< Bit 55 - GV: Guest translation Valid. /
581	RT_GCC_EXTENSION uint64_t u2GstMode : 2; /*< Bits 57:56 - GLX: Guest Paging mode levels. /
582	RT_GCC_EXTENSION uint64_t u3GstCr3TableRootPtrLo : 2; /*< Bits 60:58 - GCR3 TRP: Guest CR3 Table Root Ptr (Lo). /
583	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
584	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Write permission. /
585	RT_GCC_EXTENSION uint64_t u1Rsvd0 : 1; /*< Bit 63 - Reserved. /
586	RT_GCC_EXTENSION uint64_t u16DomainId : 1; /*< Bits 79:64 - Domain ID. /
587	RT_GCC_EXTENSION uint64_t u16GstCr3TableRootPtrMed : 16; /*< Bits 95:80 - GCR3 TRP: Guest CR3 Table Root Ptr (Mid). /
588	RT_GCC_EXTENSION uint64_t u1IoTlbEnable : 1; /*< Bit 96 - I: IOTLB Enable. /
589	RT_GCC_EXTENSION uint64_t u1SuppressPfEvents : 1; /*< Bit 97 - SE: Supress Page-fault events. /
590	RT_GCC_EXTENSION uint64_t u1SuppressAllPfEvents : 1; /*< Bit 98 - SA: Supress All Page-fault events. /
591	RT_GCC_EXTENSION uint64_t u2IoCtl : 1; /*< Bits 100:99 - IoCtl: Port I/O Control. /
592	RT_GCC_EXTENSION uint64_t u1Cache : 1; /*< Bit 101 - Cache: IOTLB Cache Hint. /
593	RT_GCC_EXTENSION uint64_t u1SnoopDisable : 1; /*< Bit 102 - SD: Snoop Disable. /
594	RT_GCC_EXTENSION uint64_t u1AllowExclusion : 1; /*< Bit 103 - EX: Allow Exclusion. /
595	RT_GCC_EXTENSION uint64_t u2SysMgt : 2; /*< Bits 105:104 - SysMgt: System Management message enable. /
596	RT_GCC_EXTENSION uint64_t u1Rsvd1 : 1; /*< Bit 106 - Reserved. /
597	RT_GCC_EXTENSION uint64_t u21GstCr3TableRootPtrHi : 21; /*< Bits 127:107 - GCR3 TRP: Guest CR3 Table Root Ptr (Hi). /
598	RT_GCC_EXTENSION uint64_t u1IntrMapValid : 1; /*< Bit 128 - IV: Interrupt map Valid. /
599	RT_GCC_EXTENSION uint64_t u4IntrTableLength : 4; /*< Bits 132:129 - IntTabLen: Interrupt Table Length. /
600	RT_GCC_EXTENSION uint64_t u1IgnoreUnmappedIntrs : 1; /*< Bits 133 - IG: Ignore unmapped interrupts. /
601	RT_GCC_EXTENSION uint64_t u26IntrTableRootPtr : 26; /*< Bits 159:134 - Interrupt Root Table Pointer (Lo). /
602	RT_GCC_EXTENSION uint64_t u20IntrTableRootPtr : 20; /*< Bits 179:160 - Interrupt Root Table Pointer (Hi). /
603	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 183:180 - Reserved. /
604	RT_GCC_EXTENSION uint64_t u1InitPassthru : 1; /*< Bits 184 - INIT Pass-through. /
605	RT_GCC_EXTENSION uint64_t u1ExtIntPassthru : 1; /*< Bits 185 - External Interrupt Pass-through. /
606	RT_GCC_EXTENSION uint64_t u1NmiPassthru : 1; /*< Bits 186 - NMI Pass-through. /
607	RT_GCC_EXTENSION uint64_t u1Rsvd2 : 1; /*< Bits 187 - Reserved. /
608	RT_GCC_EXTENSION uint64_t u2IntrCtrl : 2; /*< Bits 189:188 - IntCtl: Interrupt Control. /
609	RT_GCC_EXTENSION uint64_t u1Lint0Passthru : 1; /*< Bit 190 - Lint0Pass: LINT0 Pass-through. /
610	RT_GCC_EXTENSION uint64_t u1Lint1Passthru : 1; /*< Bit 191 - Lint1Pass: LINT1 Pass-through. /
611	RT_GCC_EXTENSION uint64_t u32Rsvd0 : 32; /*< Bits 223:192 - Reserved. /
612	RT_GCC_EXTENSION uint64_t u22Rsvd0 : 22; /*< Bits 245:224 - Reserved. /
613	RT_GCC_EXTENSION uint64_t u1AttrOverride : 1; /*< Bit 246 - AttrV: Attribute Override. /
614	RT_GCC_EXTENSION uint64_t u1Mode0FC: 1; /*< Bit 247 - Mode0FC. /
615	RT_GCC_EXTENSION uint64_t u8SnoopAttr: 1; /*< Bits 255:248 - Snoop Attribute. /
616	} n;
617	/** The 32-bit unsigned integer view. */
618	uint32_t au32[8];
619	/** The 64-bit unsigned integer view. */
620	uint64_t au64[4];
621	} DTE_T;
622	AssertCompileSize(DTE_T, 32);
623	/** Pointer to a device table entry. */
624	typedef DTE_T *PDTE_T;
625	/** Pointer to a const device table entry. */
626	typedef DTE_T const *PCDTE_T;
627
628	/** Mask of valid bits for EPHSUP (Enhanced Peripheral Page Request Handling
629	* Support) feature (bits 52:53). */
630	#define IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK UINT64_C(0x0030000000000000)
631
632	/** Mask of valid bits for GTSup (Guest Translation Support) feature (bits 55:60,
633	* bits 80:95). */
634	#define IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK UINT64_C(0x1f80000000000000)
635	#define IOMMU_DTE_QWORD_1_FEAT_GTSUP_MASK UINT64_C(0x00000000ffff0000)
636
637	/* Mask of valid bits for GIoSup (Guest I/O Protection Support) feature (bit 54). */
638	#define IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK UINT64_C(0x0040000000000000)
639
640	/* Mask of valid DTE feature bits. */
641	#define IOMMU_DTE_QWORD_0_FEAT_MASK ( IOMMU_DTE_QWORD_0_FEAT_EPHSUP_MASK \
642	\| IOMMU_DTE_QWORD_0_FEAT_GTSUP_MASK \
643	\| IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
644	#define IOMMU_DTE_QWORD_1_FEAT_MASK (IOMMU_DTE_QWORD_0_FEAT_GIOSUP_MASK)
645
646	/* Mask of all valid DTE bits (including all feature bits). */
647	#define IOMMU_DTE_QWORD_0_VALID_MASK UINT64_C(0x7fffffffffffff83)
648	#define IOMMU_DTE_QWORD_1_VALID_MASK UINT64_C(0xfffffbffffffffff)
649	#define IOMMU_DTE_QWORD_2_VALID_MASK UINT64_C(0xf70fffffffffffff)
650	#define IOMMU_DTE_QWORD_3_VALID_MASK UINT64_C(0xffc0000000000000)
651
652	/* Mask of the interrupt table root pointer. */
653	#define IOMMU_DTE_IRTE_ROOT_PTR_MASK UINT64_C(0x000fffffffffff80)
654
655	/**
656	* I/O Page Translation Entry.
657	* In accordance with the AMD spec.
658	*/
659	typedef union
660	{
661	struct
662	{
663	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
664	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
665	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
666	RT_GCC_EXTENSION uint64_t u1Dirty : 1; /*< Bit 6 - D: Dirty. /
667	RT_GCC_EXTENSION uint64_t u2Ign0 : 2; /*< Bits 8:7 - Ignored. /
668	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
669	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address. /
670	RT_GCC_EXTENSION uint64_t u7Rsvd0 : 7; /*< Bits 58:52 - Reserved. /
671	RT_GCC_EXTENSION uint64_t u1UntranslatedAccess : 1; /*< Bit 59 - U: Untranslated Access Only. /
672	RT_GCC_EXTENSION uint64_t u1ForceCoherent : 1; /*< Bit 60 - FC: Force Coherent. /
673	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
674	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
675	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
676	} n;
677	/** The 64-bit unsigned integer view. */
678	uint64_t u64;
679	} IOPTE_T;
680	AssertCompileSize(IOPTE_T, 8);
681
682	/**
683	* I/O Page Directory Entry.
684	* In accordance with the AMD spec.
685	*/
686	typedef union
687	{
688	struct
689	{
690	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
691	RT_GCC_EXTENSION uint64_t u4Ign0 : 4; /*< Bits 4:1 - Ignored. /
692	RT_GCC_EXTENSION uint64_t u1Accessed : 1; /*< Bit 5 - A: Accessed. /
693	RT_GCC_EXTENSION uint64_t u3Ign0 : 3; /*< Bits 8:6 - Ignored. /
694	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Next Level: Next page translation level. /
695	RT_GCC_EXTENSION uint64_t u40PageAddr : 40; /*< Bits 51:12 - Page address (Next Table Address). /
696	RT_GCC_EXTENSION uint64_t u9Rsvd0 : 9; /*< Bits 60:52 - Reserved. /
697	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
698	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
699	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
700	} n;
701	/** The 64-bit unsigned integer view. */
702	uint64_t u64;
703	} IOPDE_T;
704	AssertCompileSize(IOPDE_T, 8);
705
706	/**
707	* I/O Page Table Entity.
708	* In accordance with the AMD spec.
709	*
710	* This a common subset of an DTE.au64[0], PTE and PDE.
711	* Named as an "entity" to avoid confusing it with PTE.
712	*/
713	typedef union
714	{
715	struct
716	{
717	RT_GCC_EXTENSION uint64_t u1Present : 1; /*< Bit 0 - PR: Present. /
718	RT_GCC_EXTENSION uint64_t u8Ign0 : 8; /*< Bits 8:1 - Ignored. /
719	RT_GCC_EXTENSION uint64_t u3NextLevel : 3; /*< Bits 11:9 - Mode / Next Level: Next page translation level. /
720	RT_GCC_EXTENSION uint64_t u40Addr : 40; /*< Bits 51:12 - Page address. /
721	RT_GCC_EXTENSION uint64_t u9Ign0 : 9; /*< Bits 60:52 - Ignored. /
722	RT_GCC_EXTENSION uint64_t u1IoRead : 1; /*< Bit 61 - IR: I/O Read permission. /
723	RT_GCC_EXTENSION uint64_t u1IoWrite : 1; /*< Bit 62 - IW: I/O Wead permission. /
724	RT_GCC_EXTENSION uint64_t u1Ign0 : 1; /*< Bit 63 - Ignored. /
725	} n;
726	/** The 64-bit unsigned integer view. */
727	uint64_t u64;
728	} IOPTENTITY_T;
729	AssertCompileSize(IOPTENTITY_T, 8);
730	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPTE_T));
731	AssertCompile(sizeof(IOPTENTITY_T) == sizeof(IOPDE_T));
732	/** Pointer to an IOPT_ENTITY_T struct. */
733	typedef IOPTENTITY_T *PIOPTENTITY_T;
734	/** Pointer to a const IOPT_ENTITY_T struct. */
735	typedef IOPTENTITY_T const *PCIOPTENTITY_T;
736	/** Mask of the address field. */
737	#define IOMMU_PTENTITY_ADDR_MASK UINT64_C(0x000ffffffffff000)
738
739	/**
740	* Interrupt Remapping Table Entry (IRTE).
741	* In accordance with the AMD spec.
742	*/
743	typedef union
744	{
745	struct
746	{
747	uint32_t u1RemapEnable : 1; /*< Bit 0 - RemapEn: Remap Enable. /
748	uint32_t u1SuppressPf : 1; /*< Bit 1 - SupIOPF: Supress I/O Page Fault. /
749	uint32_t u3IntrType : 1; /*< Bits 4:2 - IntType: Interrupt Type. /
750	uint32_t u1ReqEoi : 1; /*< Bit 5 - RqEoi: Request EOI. /
751	uint32_t u1DestMode : 1; /*< Bit 6 - DM: Destination Mode. /
752	uint32_t u1GuestMode : 1; /*< Bit 7 - GuestMode. /
753	uint32_t u8Dest : 8; /*< Bits 15:8 - Destination. /
754	uint32_t u8Vector : 8; /*< Bits 23:16 - Vector. /
755	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
756	} n;
757	/** The 32-bit unsigned integer view. */
758	uint32_t u32;
759	} IRTE_T;
760	AssertCompileSize(IRTE_T, 4);
761	/** The number of bits to shift the IRTE offset to get the IRTE. */
762	#define IOMMU_IRTE_SIZE_SHIFT (2)
763	/** Pointer to an IRTE_T struct. */
764	typedef IRTE_T *PIRTE_T;
765	/** Pointer to a const IRTE_T struct. */
766	typedef IRTE_T const *PCIRTE_T;
767
768	/** The IRTE offset corresponds directly to bits 10:0 of the originating MSI
769	* interrupt message. See AMD IOMMU spec. 2.2.5 "Interrupt Remapping Tables". */
770	#define IOMMU_MSI_DATA_IRTE_OFFSET_MASK UINT32_C(0x000007ff)
771
772	/**
773	* Command: Generic Command Buffer Entry.
774	* In accordance with the AMD spec.
775	*/
776	typedef union
777	{
778	struct
779	{
780	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
781	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
782	uint32_t u4Opcode : 4; /*< Bits 63:60 - Op Code. /
783	uint64_t u64Operand2; /*< Bits 127:64 - Operand 2. /
784	} n;
785	/** The 64-bit unsigned integer view. */
786	uint64_t au64[2];
787	} CMD_GENERIC_T;
788	AssertCompileSize(CMD_GENERIC_T, 16);
789	/** Pointer to a generic command buffer entry. */
790	typedef CMD_GENERIC_T *PCMD_GENERIC_T;
791	/** Pointer to a const generic command buffer entry. */
792	typedef CMD_GENERIC_T const *PCCMD_GENERIC_T;
793
794	/** Number of bits to shift the byte offset of a command in the command buffer to
795	* get its index. */
796	#define IOMMU_CMD_GENERIC_SHIFT 4
797
798	/**
799	* Command: COMPLETION_WAIT.
800	* In accordance with the AMD spec.
801	*/
802	typedef union
803	{
804	struct
805	{
806	uint32_t u1Store : 1; /*< Bit 0 - S: Completion Store. /
807	uint32_t u1Interrupt : 1; /*< Bit 1 - I: Completion Interrupt. /
808	uint32_t u1Flush : 1; /*< Bit 2 - F: Flush Queue. /
809	uint32_t u29StoreAddrLo : 29; /*< Bits 31:3 - Store Address (Lo). /
810	uint32_t u20StoreAddrHi : 20; /*< Bits 51:32 - Store Address (Hi). /
811	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
812	uint32_t u4OpCode : 4; /*< Bits 63:60 - OpCode (Command). /
813	uint64_t u64StoreData; /*< Bits 127:64 - Store Data. /
814	} n;
815	/** The 64-bit unsigned integer view. */
816	uint64_t au64[2];
817	} CMD_COMWAIT_T;
818	AssertCompileSize(CMD_COMWAIT_T, 16);
819	/** Pointer to a completion wait command. */
820	typedef CMD_COMWAIT_T *PCMD_COMWAIT_T;
821	/** Pointer to a const completion wait command. */
822	typedef CMD_COMWAIT_T const *PCCMD_COMWAIT_T;
823	#define IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK UINT64_C(0xf00fffffffffffff)
824
825	/**
826	* Command: INVALIDATE_DEVTAB_ENTRY.
827	* In accordance with the AMD spec.
828	*/
829	typedef union
830	{
831	struct
832	{
833	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
834	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
835	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
836	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
837	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
838	} n;
839	/** The 64-bit unsigned integer view. */
840	uint64_t au64[2];
841	} CMD_INV_DTE_T;
842	AssertCompileSize(CMD_INV_DTE_T, 16);
843
844	/**
845	* Command: INVALIDATE_IOMMU_PAGES.
846	* In accordance with the AMD spec.
847	*/
848	typedef union
849	{
850	struct
851	{
852	uint32_t u20Pasid : 20; /*< Bits 19:0 - PASID: Process Address-Space ID. /
853	uint32_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
854	uint32_t u16DomainId : 16; /*< Bits 47:32 - Domain ID. /
855	uint32_t u12Rsvd1 : 12; /*< Bits 59:48 - Reserved. /
856	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
857	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
858	uint32_t u1PageDirEntries : 1; /*< Bit 65 - PDE: Page Directory Entries. /
859	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
860	uint32_t u9Rsvd0 : 9; /*< Bits 75:67 - Reserved. /
861	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
862	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
863	} n;
864	/** The 64-bit unsigned integer view. */
865	uint64_t au64[2];
866	} CMD_INV_IOMMU_PAGES_T;
867	AssertCompileSize(CMD_INV_IOMMU_PAGES_T, 16);
868
869	/**
870	* Command: INVALIDATE_IOTLB_PAGES.
871	* In accordance with the AMD spec.
872	*/
873	typedef union
874	{
875	struct
876	{
877	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
878	uint8_t u8PasidLo; /*< Bits 23:16 - PASID: Process Address-Space ID (Lo). /
879	uint8_t u8MaxPend; /*< Bits 31:24 - Maxpend: Maximum simultaneous in-flight transactions. /
880	uint32_t u16QueueId : 16; /*< Bits 47:32 - Queue ID. /
881	uint32_t u12PasidHi : 12; /*< Bits 59:48 - PASID: Process Address-Space ID (Hi). /
882	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
883	uint32_t u1Size : 1; /*< Bit 64 - S: Size. /
884	uint32_t u1Rsvd0: 1; /*< Bit 65 - Reserved. /
885	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
886	uint32_t u1Rsvd1 : 1; /*< Bit 67 - Reserved. /
887	uint32_t u2Type : 2; /*< Bit 69:68 - Type. /
888	uint32_t u6Rsvd0 : 6; /*< Bits 75:70 - Reserved. /
889	uint32_t u20AddrLo : 20; /*< Bits 95:76 - Address (Lo). /
890	uint32_t u32AddrHi; /*< Bits 127:96 - Address (Hi). /
891	} n;
892	/** The 64-bit unsigned integer view. */
893	uint64_t au64[2];
894	} CMD_INV_IOTLB_PAGES_T;
895	AssertCompileSize(CMD_INV_IOTLB_PAGES_T, 16);
896
897	/**
898	* Command: INVALIDATE_INTR_TABLE.
899	* In accordance with the AMD spec.
900	*/
901	typedef union
902	{
903	struct
904	{
905	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
906	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
907	uint32_t u32Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
908	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
909	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
910	} u;
911	/** The 64-bit unsigned integer view. */
912	uint64_t au64[2];
913	} CMD_INV_INTR_TABLE_T;
914	AssertCompileSize(CMD_INV_INTR_TABLE_T, 16);
915
916	/**
917	* Command: COMPLETE_PPR_REQ.
918	* In accordance with the AMD spec.
919	*/
920	typedef union
921	{
922	struct
923	{
924	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
925	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
926	uint32_t u20Pasid : 20; /*< Bits 51:32 - PASID: Process Address-Space ID. /
927	uint32_t u8Rsvd0 : 8; /*< Bits 59:52 - Reserved. /
928	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
929	uint32_t u2Rsvd0 : 2; /*< Bits 65:64 - Reserved. /
930	uint32_t u1GuestOrNested : 1; /*< Bit 66 - GN: Guest (GPA) or Nested (GVA). /
931	uint32_t u29Rsvd0 : 29; /*< Bits 95:67 - Reserved. /
932	uint32_t u16CompletionTag : 16; /*< Bits 111:96 - Completion Tag. /
933	uint32_t u16Rsvd1 : 16; /*< Bits 127:112 - Reserved. /
934	} n;
935	/** The 64-bit unsigned integer view. */
936	uint64_t au64[2];
937	} CMD_COMPLETE_PPR_REQ_T;
938	AssertCompileSize(CMD_COMPLETE_PPR_REQ_T, 16);
939
940	/**
941	* Command: INV_IOMMU_ALL.
942	* In accordance with the AMD spec.
943	*/
944	typedef union
945	{
946	struct
947	{
948	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
949	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
950	uint32_t u4OpCode : 4; /*< Bits 63:60 - Op Code (Command). /
951	uint64_t u64Rsvd0; /*< Bits 127:64 - Reserved. /
952	} n;
953	/** The 64-bit unsigned integer view. */
954	uint64_t au64[2];
955	} CMD_IOMMU_ALL_T;
956	AssertCompileSize(CMD_IOMMU_ALL_T, 16);
957
958	/**
959	* Event Log Entry: Generic.
960	* In accordance with the AMD spec.
961	*/
962	typedef union
963	{
964	struct
965	{
966	uint32_t u32Operand1Lo; /*< Bits 31:0 - Operand 1 (Lo). /
967	uint32_t u32Operand1Hi : 28; /*< Bits 59:32 - Operand 1 (Hi). /
968	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
969	uint32_t u32Operand2Lo; /*< Bits 95:64 - Operand 2 (Lo). /
970	uint32_t u32Operand2Hi; /*< Bits 127:96 - Operand 2 (Hi). /
971	} n;
972	/** The 32-bit unsigned integer view. */
973	uint32_t au32[4];
974	} EVT_GENERIC_T;
975	AssertCompileSize(EVT_GENERIC_T, 16);
976	/** Number of bits to shift the byte offset of an event entry in the event log
977	* buffer to get its index. */
978	#define IOMMU_EVT_GENERIC_SHIFT 4
979	/** Pointer to a generic event log entry. */
980	typedef EVT_GENERIC_T *PEVT_GENERIC_T;
981	/** Pointer to a const generic event log entry. */
982	typedef const EVT_GENERIC_T *PCEVT_GENERIC_T;
983
984	/**
985	* Hardware event types.
986	* In accordance with the AMD spec.
987	*/
988	typedef enum HWEVTTYPE
989	{
990	HWEVTTYPE_RSVD = 0,
991	HWEVTTYPE_MASTER_ABORT,
992	HWEVTTYPE_TARGET_ABORT,
993	HWEVTTYPE_DATA_ERROR
994	} HWEVTTYPE;
995	AssertCompileSize(HWEVTTYPE, 4);
996
997	/**
998	* Event Log Entry: ILLEGAL_DEV_TABLE_ENTRY.
999	* In accordance with the AMD spec.
1000	*/
1001	typedef union
1002	{
1003	struct
1004	{
1005	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1006	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1007	uint16_t u12Rsvd0 : 12; /*< Bits 31:20 - Reserved. /
1008	uint16_t u16PasidLo; /*< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1009	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1010	uint16_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1011	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1012	uint16_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1013	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1014	uint16_t u1Rsvd1 : 1; /*< Bit 54 - Reserved. /
1015	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1016	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1017	uint16_t u3Rsvd0 : 3; /*< Bits 59:57 - Reserved. /
1018	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1019	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1020	} n;
1021	/** The 32-bit unsigned integer view. */
1022	uint32_t au32[4];
1023	/** The 64-bit unsigned integer view. */
1024	uint64_t au64[2];
1025	} EVT_ILLEGAL_DTE_T;
1026	AssertCompileSize(EVT_ILLEGAL_DTE_T, 16);
1027	/** Pointer to an illegal device table entry event. */
1028	typedef EVT_ILLEGAL_DTE_T *PEVT_ILLEGAL_DTE_T;
1029	/** Pointer to a const illegal device table entry event. */
1030	typedef EVT_ILLEGAL_DTE_T const *PCEVT_ILLEGAL_DTE_T;
1031
1032	/**
1033	* Event Log Entry: IO_PAGE_FAULT_EVENT.
1034	* In accordance with the AMD spec.
1035	*/
1036	typedef union
1037	{
1038	struct
1039	{
1040	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1041	uint16_t u4PasidHi : 4; /*< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1042	uint16_t u16DomainOrPasidLo; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1043	uint16_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1044	uint16_t u1NoExecute : 1; /*< Bit 49 - NX: No Execute. /
1045	uint16_t u1User : 1; /*< Bit 50 - US: User/Supervisor. /
1046	uint16_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1047	uint16_t u1Present : 1; /*< Bit 52 - PR: Present. /
1048	uint16_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1049	uint16_t u1PermDenied : 1; /*< Bit 54 - PE: Permission Indicator. /
1050	uint16_t u1RsvdNotZero : 1; /*< Bit 55 - RZ: Reserved bit not Zero (0=invalid level encoding). /
1051	uint16_t u1Translation : 1; /*< Bit 56 - TN: Translation. /
1052	uint16_t u3Rsvd0 : 3; /*< Bit 59:57 - Reserved. /
1053	uint16_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1054	uint64_t u64Addr; /*< Bits 127:64 - Address: I/O Virtual Address (IOVA). /
1055	} n;
1056	/** The 32-bit unsigned integer view. */
1057	uint32_t au32[4];
1058	/** The 64-bit unsigned integer view. */
1059	uint64_t au64[2];
1060	} EVT_IO_PAGE_FAULT_T;
1061	AssertCompileSize(EVT_IO_PAGE_FAULT_T, 16);
1062	/** Pointer to an I/O page fault event. */
1063	typedef EVT_IO_PAGE_FAULT_T *PEVT_IO_PAGE_FAULT_T;
1064	/** Pointer to a const I/O page fault event. */
1065	typedef EVT_IO_PAGE_FAULT_T const *PCEVT_IO_PAGE_FAULT_T;
1066
1067
1068	/**
1069	* Event Log Entry: DEV_TAB_HARDWARE_ERROR.
1070	* In accordance with the AMD spec.
1071	*/
1072	typedef union
1073	{
1074	struct
1075	{
1076	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1077	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1078	uint32_t u19Rsvd0 : 19; /*< Bits 50:32 - Reserved. /
1079	uint32_t u1Intr : 1; /*< Bit 51 - I: Interrupt (1=interrupt request, 0=memory request). /
1080	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1081	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write transaction (only meaninful when I=0 and TR=0). /
1082	uint32_t u2Rsvd0 : 2; /*< Bits 55:54 - Reserved. /
1083	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation (1=translation, 0=transaction). /
1084	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1085	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1086	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1087	uint64_t u64Addr; /*< Bits 127:64 - Address. /
1088	} n;
1089	/** The 32-bit unsigned integer view. */
1090	uint32_t au32[4];
1091	/** The 64-bit unsigned integer view. */
1092	uint64_t au64[2];
1093	} EVT_DEV_TAB_HW_ERROR_T;
1094	AssertCompileSize(EVT_DEV_TAB_HW_ERROR_T, 16);
1095	/** Pointer to a device table hardware error event. */
1096	typedef EVT_DEV_TAB_HW_ERROR_T *PEVT_DEV_TAB_HW_ERROR_T;
1097	/** Pointer to a const device table hardware error event. */
1098	typedef EVT_DEV_TAB_HW_ERROR_T const *PCEVT_DEV_TAB_HW_ERROR_T;
1099
1100	/**
1101	* Event Log Entry: EVT_PAGE_TAB_HARDWARE_ERROR.
1102	* In accordance with the AMD spec.
1103	*/
1104	typedef union
1105	{
1106	struct
1107	{
1108	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1109	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved. /
1110	uint32_t u16DomainOrPasidLo : 16; /*< Bits 47:32 - D/P: Domain ID or Process Address-Space ID (Lo). /
1111	uint32_t u1GuestOrNested : 1; /*< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1112	uint32_t u2Rsvd0 : 2; /*< Bits 50:49 - Reserved. /
1113	uint32_t u1Interrupt : 1; /*< Bit 51 - I: Interrupt. /
1114	uint32_t u1Rsvd0 : 1; /*< Bit 52 - Reserved. /
1115	uint32_t u1ReadWrite : 1; /*< Bit 53 - RW: Read/Write. /
1116	uint32_t u2Rsvd1 : 2; /*< Bit 55:54 - Reserved. /
1117	uint32_t u1Translation : 1; /*< Bit 56 - TR: Translation. /
1118	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1119	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1120	uint32_t u4EvtCode : 4; /*< Bit 63:60 - Event code. /
1121	/** @todo r=ramshankar: Figure 55: PAGE_TAB_HARDWARE_ERROR says Addr[31:3] but
1122	* table 58 mentions Addr[31:4], we just use the full 64-bits. Looks like a
1123	* typo in the figure.See AMD AMD IOMMU spec (3.05-PUB, Jan 2020). */
1124	uint64_t u64Addr; /** Bits 127:64 - Address: SPA of the page table entry. */
1125	} n;
1126	/** The 32-bit unsigned integer view. */
1127	uint32_t au32[4];
1128	/** The 64-bit unsigned integer view. */
1129	uint64_t au64[2];
1130	} EVT_PAGE_TAB_HW_ERR_T;
1131	AssertCompileSize(EVT_PAGE_TAB_HW_ERR_T, 16);
1132	/** Pointer to a page table hardware error event. */
1133	typedef EVT_PAGE_TAB_HW_ERR_T *PEVT_PAGE_TAB_HW_ERR_T;
1134	/** Pointer to a const page table hardware error event. */
1135	typedef EVT_PAGE_TAB_HW_ERR_T const *PCEVT_PAGE_TAB_HW_ERR_T;
1136
1137	/**
1138	* Event Log Entry: ILLEGAL_COMMAND_ERROR.
1139	* In accordance with the AMD spec.
1140	*/
1141	typedef union
1142	{
1143	struct
1144	{
1145	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1146	uint32_t u28Rsvd0 : 28; /*< Bits 47:32 - Reserved. /
1147	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1148	uint64_t u64Addr; /*< Bits 127:64 - Address: SPA of the invalid command. /
1149	} n;
1150	/** The 32-bit unsigned integer view. */
1151	uint32_t au32[4];
1152	/** The 64-bit unsigned integer view. */
1153	uint64_t au64[2];
1154	} EVT_ILLEGAL_CMD_ERR_T;
1155	AssertCompileSize(EVT_ILLEGAL_CMD_ERR_T, 16);
1156	/** Pointer to an illegal command error event. */
1157	typedef EVT_ILLEGAL_CMD_ERR_T *PEVT_ILLEGAL_CMD_ERR_T;
1158	/** Pointer to a const illegal command error event. */
1159	typedef EVT_ILLEGAL_CMD_ERR_T const *PCEVT_ILLEGAL_CMD_ERR_T;
1160
1161	/**
1162	* Event Log Entry: COMMAND_HARDWARE_ERROR.
1163	* In accordance with the AMD spec.
1164	*/
1165	typedef union
1166	{
1167	struct
1168	{
1169	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1170	uint32_t u25Rsvd1 : 25; /*< Bits 56:32 - Reserved. /
1171	uint32_t u2Type : 2; /*< Bits 58:57 - Type: The type of hardware error. /
1172	uint32_t u1Rsvd1 : 1; /*< Bit 59 - Reserved. /
1173	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1174	uint64_t u64Addr; /*< Bits 128:64 - Address: SPA of the attempted access. /
1175	} n;
1176	/** The 32-bit unsigned integer view. */
1177	uint32_t au32[4];
1178	/** The 64-bit unsigned integer view. */
1179	uint64_t au64[2];
1180	} EVT_CMD_HW_ERR_T;
1181	AssertCompileSize(EVT_CMD_HW_ERR_T, 16);
1182	/** Pointer to a command hardware error event. */
1183	typedef EVT_CMD_HW_ERR_T *PEVT_CMD_HW_ERR_T;
1184	/** Pointer to a const command hardware error event. */
1185	typedef EVT_CMD_HW_ERR_T const *PCEVT_CMD_HW_ERR_T;
1186
1187	/**
1188	* Event Log Entry: IOTLB_INV_TIMEOUT.
1189	* In accordance with the AMD spec.
1190	*/
1191	typedef union
1192	{
1193	struct
1194	{
1195	uint16_t u16DevId; /*< Bits 15:0 - Device ID. /
1196	uint16_t u16Rsvd0; /*< Bits 31:16 - Reserved./
1197	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1198	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1199	uint32_t u4Rsvd0 : 4; /*< Bits 67:64 - Reserved. /
1200	uint32_t u28AddrLo : 28; /*< Bits 95:68 - Address: SPA of the invalidation command that timedout (Lo). /
1201	uint32_t u32AddrHi; /*< Bits 127:96 - Address: SPA of the invalidation command that timedout (Hi). /
1202	} n;
1203	/** The 32-bit unsigned integer view. */
1204	uint32_t au32[4];
1205	} EVT_IOTLB_INV_TIMEOUT_T;
1206	AssertCompileSize(EVT_IOTLB_INV_TIMEOUT_T, 16);
1207
1208	/**
1209	* Event Log Entry: INVALID_DEVICE_REQUEST.
1210	* In accordance with the AMD spec.
1211	*/
1212	typedef union
1213	{
1214	struct
1215	{
1216	uint32_t u16DevId : 16; /**< Bits 15:0 - Device ID. /
1217	uint32_t u4PasidHi : 4; /**< Bits 19:16 - PASID: Process Address-Space ID (Hi). /
1218	uint32_t u12Rsvd0 : 12; /**< Bits 31:20 - Reserved. /
1219	uint32_t u16PasidLo : 16; /**< Bits 47:32 - PASID: Process Address-Space ID (Lo). /
1220	uint32_t u1GuestOrNested : 1; /**< Bit 48 - GN: Guest (GPA) or Nested (GVA). /
1221	uint32_t u1User : 1; /**< Bit 49 - US: User/Supervisor. /
1222	uint32_t u6Rsvd0 : 6; /**< Bits 55:50 - Reserved. /
1223	uint32_t u1Translation: 1; /**< Bit 56 - TR: Translation. /
1224	uint32_t u3Type: 3; /**< Bits 59:57 - Type: The type of hardware error. /
1225	uint32_t u4EvtCode : 4; /**< Bits 63:60 - Event code. /
1226	uint64_t u64Addr; /**< Bits 127:64 - Address: Translation or access address. /
1227	} n;
1228	/** The 32-bit unsigned integer view. */
1229	uint32_t au32[4];
1230	} EVT_INVALID_DEV_REQ_T;
1231	AssertCompileSize(EVT_INVALID_DEV_REQ_T, 16);
1232
1233	/**
1234	* Event Log Entry: EVENT_COUNTER_ZERO.
1235	* In accordance with the AMD spec.
1236	*/
1237	typedef union
1238	{
1239	struct
1240	{
1241	uint32_t u32Rsvd0; /*< Bits 31:0 - Reserved. /
1242	uint32_t u28Rsvd0 : 28; /*< Bits 59:32 - Reserved. /
1243	uint32_t u4EvtCode : 4; /*< Bits 63:60 - Event code. /
1244	uint32_t u20CounterNoteHi : 20; /*< Bits 83:64 - CounterNote: Counter value for the event counter register (Hi). /
1245	uint32_t u12Rsvd0 : 12; /*< Bits 95:84 - Reserved. /
1246	uint32_t u32CounterNoteLo; /*< Bits 127:96 - CounterNote: Counter value for the event cuonter register (Lo). /
1247	} n;
1248	/** The 32-bit unsigned integer view. */
1249	uint32_t au32[4];
1250	} EVT_EVENT_COUNTER_ZERO_T;
1251	AssertCompileSize(EVT_EVENT_COUNTER_ZERO_T, 16);
1252
1253	/**
1254	* IOMMU Capability Header (PCI).
1255	* In accordance with the AMD spec.
1256	*/
1257	typedef union
1258	{
1259	struct
1260	{
1261	uint32_t u8CapId : 8; /*< Bits 7:0 - CapId: Capability ID. /
1262	uint32_t u8CapPtr : 8; /*< Bits 15:8 - CapPtr: Pointer (PCI config offset) to the next capability. /
1263	uint32_t u3CapType : 3; /*< Bits 18:16 - CapType: Capability Type. /
1264	uint32_t u5CapRev : 5; /*< Bits 23:19 - CapRev: Capability revision. /
1265	uint32_t u1IoTlbSup : 1; /*< Bit 24 - IotlbSup: IOTLB Support. /
1266	uint32_t u1HtTunnel : 1; /*< Bit 25 - HtTunnel: HyperTransport Tunnel translation support. /
1267	uint32_t u1NpCache : 1; /*< Bit 26 - NpCache: Not Present table entries are cached. /
1268	uint32_t u1EfrSup : 1; /*< Bit 27 - EFRSup: Extended Feature Register Support. /
1269	uint32_t u1CapExt : 1; /*< Bit 28 - CapExt: Misc. Information Register 1 Support. /
1270	uint32_t u3Rsvd0 : 3; /*< Bits 31:29 - Reserved. /
1271	} n;
1272	/** The 32-bit unsigned integer view. */
1273	uint32_t u32;
1274	} IOMMU_CAP_HDR_T;
1275	AssertCompileSize(IOMMU_CAP_HDR_T, 4);
1276
1277	/**
1278	* IOMMU Base Address (Lo and Hi) Register (PCI).
1279	* In accordance with the AMD spec.
1280	*/
1281	typedef union
1282	{
1283	struct
1284	{
1285	uint32_t u1Enable : 1; /*< Bit 1 - Enable: RW1S - Enable IOMMU MMIO region. /
1286	uint32_t u12Rsvd0 : 12; /*< Bits 13:1 - Reserved. /
1287	uint32_t u18BaseAddrLo : 18; /*< Bits 31:14 - Base address (Lo) of the MMIO region. /
1288	uint32_t u32BaseAddrHi; /*< Bits 63:32 - Base address (Hi) of the MMIO region. /
1289	} n;
1290	/** The 32-bit unsigned integer view. */
1291	uint32_t au32[2];
1292	/** The 64-bit unsigned integer view. */
1293	uint64_t u64;
1294	} IOMMU_BAR_T;
1295	AssertCompileSize(IOMMU_BAR_T, 8);
1296	#define IOMMU_BAR_VALID_MASK UINT64_C(0xffffffffffffc001)
1297
1298	/**
1299	* IOMMU Range Register (PCI).
1300	* In accordance with the AMD spec.
1301	*/
1302	typedef union
1303	{
1304	struct
1305	{
1306	uint32_t u5HtUnitId : 5; /*< Bits 4:0 - UnitID: IOMMU HyperTransport Unit ID (not used). /
1307	uint32_t u2Rsvd0 : 2; /*< Bits 6:5 - Reserved. /
1308	uint32_t u1RangeValid : 1; /*< Bit 7 - RngValid: Range Valid. /
1309	uint32_t u8Bus : 8; /*< Bits 15:8 - BusNumber: Bus number of the first and last device. /
1310	uint32_t u8FirstDevice : 8; /*< Bits 23:16 - FirstDevice: Device and function number of the first device. /
1311	uint32_t u8LastDevice: 8; /*< Bits 31:24 - LastDevice: Device and function number of the last device. /
1312	} n;
1313	/** The 32-bit unsigned integer view. */
1314	uint32_t u32;
1315	} IOMMU_RANGE_T;
1316	AssertCompileSize(IOMMU_RANGE_T, 4);
1317
1318	/**
1319	* Device Table Base Address Register (MMIO).
1320	* In accordance with the AMD spec.
1321	*/
1322	typedef union
1323	{
1324	struct
1325	{
1326	RT_GCC_EXTENSION uint64_t u9Size : 9; /*< Bits 8:0 - Size: Size of the device table. /
1327	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 11:9 - Reserved. /
1328	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - DevTabBase: Device table base address. /
1329	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1330	} n;
1331	/** The 64-bit unsigned integer view. */
1332	uint64_t u64;
1333	} DEV_TAB_BAR_T;
1334	AssertCompileSize(DEV_TAB_BAR_T, 8);
1335	#define IOMMU_DEV_TAB_BAR_VALID_MASK UINT64_C(0x000ffffffffff1ff)
1336	#define IOMMU_DEV_TAB_SEG_BAR_VALID_MASK UINT64_C(0x000ffffffffff0ff)
1337
1338	/**
1339	* Command Buffer Base Address Register (MMIO).
1340	* In accordance with the AMD spec.
1341	*/
1342	typedef union
1343	{
1344	struct
1345	{
1346	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1347	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - ComBase: Command buffer base address. /
1348	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1349	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - ComLen: Command buffer length. /
1350	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1351	} n;
1352	/** The 64-bit unsigned integer view. */
1353	uint64_t u64;
1354	} CMD_BUF_BAR_T;
1355	AssertCompileSize(CMD_BUF_BAR_T, 8);
1356	#define IOMMU_CMD_BUF_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1357
1358	/**
1359	* Event Log Base Address Register (MMIO).
1360	* In accordance with the AMD spec.
1361	*/
1362	typedef union
1363	{
1364	struct
1365	{
1366	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1367	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - EventBase: Event log base address. /
1368	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1369	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - EventLen: Event log length. /
1370	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1371	} n;
1372	/** The 64-bit unsigned integer view. */
1373	uint64_t u64;
1374	} EVT_LOG_BAR_T;
1375	AssertCompileSize(EVT_LOG_BAR_T, 8);
1376	#define IOMMU_EVT_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1377
1378	/**
1379	* IOMMU Control Register (MMIO).
1380	* In accordance with the AMD spec.
1381	*/
1382	typedef union
1383	{
1384	struct
1385	{
1386	uint32_t u1IommuEn : 1; /*< Bit 0 - IommuEn: IOMMU Enable. /
1387	uint32_t u1HtTunEn : 1; /*< Bit 1 - HtTunEn: HyperTransport Tunnel Enable. /
1388	uint32_t u1EvtLogEn : 1; /*< Bit 2 - EventLogEn: Event Log Enable. /
1389	uint32_t u1EvtIntrEn : 1; /*< Bit 3 - EventIntEn: Event Log Interrupt Enable. /
1390	uint32_t u1CompWaitIntrEn : 1; /*< Bit 4 - ComWaitIntEn: Completion Wait Interrupt Enable. /
1391	uint32_t u3InvTimeOut : 3; /*< Bits 7:5 - InvTimeOut: Invalidation Timeout. /
1392	uint32_t u1PassPW : 1; /*< Bit 8 - PassPW: Pass Posted Write. /
1393	uint32_t u1ResPassPW : 1; /*< Bit 9 - ResPassPW: Response Pass Posted Write. /
1394	uint32_t u1Coherent : 1; /*< Bit 10 - Coherent: HT read request packet Coherent bit. /
1395	uint32_t u1Isoc : 1; /*< Bit 11 - Isoc: HT read request packet Isochronous bit. /
1396	uint32_t u1CmdBufEn : 1; /*< Bit 12 - CmdBufEn: Command Buffer Enable. /
1397	uint32_t u1PprLogEn : 1; /*< Bit 13 - PprLogEn: Peripheral Page Request (PPR) Log Enable. /
1398	uint32_t u1PprIntrEn : 1; /*< Bit 14 - PprIntrEn: Peripheral Page Request Interrupt Enable. /
1399	uint32_t u1PprEn : 1; /*< Bit 15 - PprEn: Peripheral Page Request processing Enable. /
1400	uint32_t u1GstTranslateEn : 1; /*< Bit 16 - GTEn: Guest Translate Enable. /
1401	uint32_t u1GstVirtApicEn : 1; /*< Bit 17 - GAEn: Guest Virtual-APIC Enable. /
1402	uint32_t u4Crw : 1; /*< Bits 21:18 - CRW: Intended for future use (not documented). /
1403	uint32_t u1SmiFilterEn : 1; /*< Bit 22 - SmiFEn: SMI Filter Enable. /
1404	uint32_t u1SelfWriteBackDis : 1; /*< Bit 23 - SlfWBDis: Self Write-Back Disable. /
1405	uint32_t u1SmiFilterLogEn : 1; /*< Bit 24 - SmiFLogEn: SMI Filter Log Enable. /
1406	uint32_t u3GstVirtApicModeEn : 3; /*< Bits 27:25 - GAMEn: Guest Virtual-APIC Mode Enable. /
1407	uint32_t u1GstLogEn : 1; /*< Bit 28 - GALogEn: Guest Virtual-APIC GA Log Enable. /
1408	uint32_t u1GstIntrEn : 1; /*< Bit 29 - GAIntEn: Guest Virtual-APIC Interrupt Enable. /
1409	uint32_t u2DualPprLogEn : 2; /*< Bits 31:30 - DualPprLogEn: Dual Peripheral Page Request Log Enable. /
1410	uint32_t u2DualEvtLogEn : 2; /*< Bits 33:32 - DualEventLogEn: Dual Event Log Enable. /
1411	uint32_t u3DevTabSegEn : 3; /*< Bits 36:34 - DevTblSegEn: Device Table Segment Enable. /
1412	uint32_t u2PrivAbortEn : 2; /*< Bits 38:37 - PrivAbrtEn: Privilege Abort Enable. /
1413	uint32_t u1PprAutoRespEn : 1; /*< Bit 39 - PprAutoRspEn: Peripheral Page Request Auto Response Enable. /
1414	uint32_t u1MarcEn : 1; /*< Bit 40 - MarcEn: Memory Address Routing and Control Enable. /
1415	uint32_t u1BlockStopMarkEn : 1; /*< Bit 41 - BlkStopMarkEn: Block StopMark messages Enable. /
1416	uint32_t u1PprAutoRespAlwaysOnEn : 1; /*< Bit 42 - PprAutoRspAon:: PPR Auto Response - Always On Enable. /
1417	uint32_t u1DomainIDPNE : 1; /*< Bit 43 - DomainIDPE: Reserved (not documented). /
1418	uint32_t u1Rsvd0 : 1; /*< Bit 44 - Reserved. /
1419	uint32_t u1EnhancedPpr : 1; /*< Bit 45 - EPHEn: Enhanced Peripheral Page Request Handling Enable. /
1420	uint32_t u2HstAccDirtyBitUpdate : 2; /*< Bits 47:46 - HADUpdate: Access and Dirty Bit updated in host page table. /
1421	uint32_t u1GstDirtyUpdateDis : 1; /*< Bit 48 - GDUpdateDis: Disable hardare update of Dirty bit in GPT. /
1422	uint32_t u1Rsvd1 : 1; /*< Bit 49 - Reserved. /
1423	uint32_t u1X2ApicEn : 1; /*< Bit 50 - XTEn: Enable X2APIC. /
1424	uint32_t u1X2ApicIntrGenEn : 1; /*< Bit 51 - IntCapXTEn: Enable IOMMU X2APIC Interrupt generation. /
1425	uint32_t u2Rsvd0 : 2; /*< Bits 53:52 - Reserved. /
1426	uint32_t u1GstAccessUpdateDis : 1; /*< Bit 54 - GAUpdateDis: Disable hardare update of Access bit in GPT. /
1427	uint32_t u8Rsvd0 : 8; /*< Bits 63:55 - Reserved. /
1428	} n;
1429	/** The 64-bit unsigned integer view. */
1430	uint64_t u64;
1431	} IOMMU_CTRL_T;
1432	AssertCompileSize(IOMMU_CTRL_T, 8);
1433	#define IOMMU_CTRL_VALID_MASK UINT64_C(0x004defffffffffff)
1434	#define IOMMU_CTRL_CMD_BUF_EN_MASK UINT64_C(0x0000000000001001)
1435
1436	/**
1437	* IOMMU Exclusion Base Register (MMIO).
1438	* In accordance with the AMD spec.
1439	*/
1440	typedef union
1441	{
1442	struct
1443	{
1444	RT_GCC_EXTENSION uint64_t u1ExclEnable : 1; /*< Bit 0 - ExEn: Exclusion Range Enable. /
1445	RT_GCC_EXTENSION uint64_t u1AllowAll : 1; /*< Bit 1 - Allow: Allow All Devices. /
1446	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1447	RT_GCC_EXTENSION uint64_t u40ExclRangeBase : 40; /*< Bits 51:12 - Exclusion Range Base Address. /
1448	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 63:52 - Reserved. /
1449	} n;
1450	/** The 64-bit unsigned integer view. */
1451	uint64_t u64;
1452	} IOMMU_EXCL_RANGE_BAR_T;
1453	AssertCompileSize(IOMMU_EXCL_RANGE_BAR_T, 8);
1454	#define IOMMU_EXCL_RANGE_BAR_VALID_MASK UINT64_C(0x000ffffffffff003)
1455
1456	/**
1457	* IOMMU Exclusion Range Limit Register (MMIO).
1458	* In accordance with the AMD spec.
1459	*/
1460	typedef union
1461	{
1462	struct
1463	{
1464	RT_GCC_EXTENSION uint64_t u52ExclLimit : 52; /*< Bits 51:0 - Exclusion Range Limit (last 12 bits are treated as 1s). /
1465	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1466	} n;
1467	/** The 64-bit unsigned integer view. */
1468	uint64_t u64;
1469	} IOMMU_EXCL_RANGE_LIMIT_T;
1470	AssertCompileSize(IOMMU_EXCL_RANGE_LIMIT_T, 8);
1471	#define IOMMU_EXCL_RANGE_LIMIT_VALID_MASK UINT64_C(0x000fffffffffffff)
1472
1473	/**
1474	* IOMMU Extended Feature Register (MMIO).
1475	* In accordance with the AMD spec.
1476	*/
1477	typedef union
1478	{
1479	struct
1480	{
1481	uint32_t u1PrefetchSup : 1; /*< Bit 0 - PreFSup: Prefetch Support. /
1482	uint32_t u1PprSup : 1; /*< Bit 1 - PPRSup: Peripheral Page Request Support. /
1483	uint32_t u1X2ApicSup : 1; /*< Bit 2 - XTSup: x2Apic Support. /
1484	uint32_t u1NoExecuteSup : 1; /*< Bit 3 - NXSup: No-Execute and Privilege Level Support. /
1485	uint32_t u1GstTranslateSup : 1; /*< Bit 4 - GTSup: Guest Translations (for GVAs) Support. /
1486	uint32_t u1Rsvd0 : 1; /*< Bit 5 - Reserved. /
1487	uint32_t u1InvAllSup : 1; /*< Bit 6 - IASup: Invalidate-All Support. /
1488	uint32_t u1GstVirtApicSup : 1; /*< Bit 7 - GASup: Guest Virtual-APIC Support. /
1489	uint32_t u1HwErrorSup : 1; /*< Bit 8 - HESup: Hardware Error registers Support. /
1490	uint32_t u1PerfCounterSup : 1; /*< Bit 8 - PCSup: Performance Counter Support. /
1491	uint32_t u2HostAddrTranslateSize : 2; /*< Bits 11:10 - HATS: Host Address Translation Size. /
1492	uint32_t u2GstAddrTranslateSize : 2; /*< Bits 13:12 - GATS: Guest Address Translation Size. /
1493	uint32_t u2GstCr3RootTblLevel : 2; /*< Bits 15:14 - GLXSup: Guest CR3 Root Table Level (Max) Size Support. /
1494	uint32_t u2SmiFilterSup : 2; /*< Bits 17:16 - SmiFSup: SMI Filter Register Support. /
1495	uint32_t u3SmiFilterCount : 3; /*< Bits 20:18 - SmiFRC: SMI Filter Register Count. /
1496	uint32_t u3GstVirtApicModeSup : 3; /*< Bits 23:21 - GAMSup: Guest Virtual-APIC Modes Supported. /
1497	uint32_t u2DualPprLogSup : 2; /*< Bits 25:24 - DualPprLogSup: Dual Peripheral Page Request Log Support. /
1498	uint32_t u2Rsvd0 : 2; /*< Bits 27:26 - Reserved. /
1499	uint32_t u2DualEvtLogSup : 2; /*< Bits 29:28 - DualEventLogSup: Dual Event Log Support. /
1500	uint32_t u2Rsvd1 : 2; /*< Bits 31:30 - Reserved. /
1501	uint32_t u5MaxPasidSup : 5; /*< Bits 36:32 - PASMax: Maximum PASID Supported. /
1502	uint32_t u1UserSupervisorSup : 1; /*< Bit 37 - USSup: User/Supervisor Page Protection Support. /
1503	uint32_t u2DevTabSegSup : 2; /*< Bits 39:38 - DevTlbSegSup: Segmented Device Table Support. /
1504	uint32_t u1PprLogOverflowWarn : 1; /*< Bit 40 - PprOvrflwEarlySup: PPR Log Overflow Early Warning Support. /
1505	uint32_t u1PprAutoRespSup : 1; /*< Bit 41 - PprAutoRspSup: PPR Automatic Response Support. /
1506	uint32_t u2MarcSup : 2; /*< Bit 43:42 - MarcSup: Memory Access Routing and Control Support. /
1507	uint32_t u1BlockStopMarkSup : 1; /*< Bit 44 - BlkStopMarkSup: Block StopMark messages Support. /
1508	uint32_t u1PerfOptSup : 1; /*< Bit 45 - PerfOptSup: IOMMU Performance Optimization Support. /
1509	uint32_t u1MsiCapMmioSup : 1; /*< Bit 46 - MsiCapMmioSup: MSI Capability Register MMIO Access Support. /
1510	uint32_t u1Rsvd1 : 1; /*< Bit 47 - Reserved. /
1511	uint32_t u1GstIoSup : 1; /*< Bit 48 - GIoSup: Guest I/O Protection Support. /
1512	uint32_t u1HostAccessSup : 1; /*< Bit 49 - HASup: Host Access Support. /
1513	uint32_t u1EnhancedPprSup : 1; /*< Bit 50 - EPHSup: Enhanced Peripheral Page Request Handling Support. /
1514	uint32_t u1AttrForwardSup : 1; /*< Bit 51 - AttrFWSup: Attribute Forward Support. /
1515	uint32_t u1HostDirtySup : 1; /*< Bit 52 - HDSup: Host Dirty Support. /
1516	uint32_t u1Rsvd2 : 1; /*< Bit 53 - Reserved. /
1517	uint32_t u1InvIoTlbTypeSup : 1; /*< Bit 54 - InvIotlbTypeSup: Invalidate IOTLB Type Support. /
1518	uint32_t u6Rsvd0 : 6; /*< Bit 60:55 - Reserved. /
1519	uint32_t u1GstUpdateDisSup : 1; /*< Bit 61 - GAUpdateDisSup: Disable hardware update on GPT Support. /
1520	uint32_t u1ForcePhysDstSup : 1; /*< Bit 62 - ForcePhyDestSup: Force Phys. Dst. Mode for Remapped Intr. /
1521	uint32_t u1Rsvd3 : 1; /*< Bit 63 - Reserved. /
1522	} n;
1523	/** The 64-bit unsigned integer view. */
1524	uint64_t u64;
1525	} IOMMU_EXT_FEAT_T;
1526	AssertCompileSize(IOMMU_EXT_FEAT_T, 8);
1527
1528	/**
1529	* Peripheral Page Request Log Base Address Register (MMIO).
1530	* In accordance with the AMD spec.
1531	*/
1532	typedef union
1533	{
1534	struct
1535	{
1536	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1537	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - PPRLogBase: Peripheral Page Request Log Base Address. /
1538	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1539	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - PPRLogLen: Peripheral Page Request Log Length. /
1540	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1541	} n;
1542	/** The 64-bit unsigned integer view. */
1543	uint64_t u64;
1544	} PPR_LOG_BAR_T;
1545	AssertCompileSize(PPR_LOG_BAR_T, 8);
1546	#define IOMMU_PPR_LOG_BAR_VALID_MASK UINT64_C(0x0f0ffffffffff000)
1547
1548	/**
1549	* IOMMU Hardware Event Upper Register (MMIO).
1550	* In accordance with the AMD spec.
1551	*/
1552	typedef union
1553	{
1554	struct
1555	{
1556	RT_GCC_EXTENSION uint64_t u60FirstOperand : 60; /*< Bits 59:0 - First event code dependent operand. /
1557	RT_GCC_EXTENSION uint64_t u4EvtCode : 4; /*< Bits 63:60 - Event Code. /
1558	} n;
1559	/** The 64-bit unsigned integer view. */
1560	uint64_t u64;
1561	} IOMMU_HW_EVT_HI_T;
1562	AssertCompileSize(IOMMU_HW_EVT_HI_T, 8);
1563
1564	/**
1565	* IOMMU Hardware Event Lower Register (MMIO).
1566	* In accordance with the AMD spec.
1567	*/
1568	typedef uint64_t IOMMU_HW_EVT_LO_T;
1569
1570	/**
1571	* IOMMU Hardware Event Status (MMIO).
1572	* In accordance with the AMD spec.
1573	*/
1574	typedef union
1575	{
1576	struct
1577	{
1578	uint32_t u1Valid : 1; /*< Bit 0 - HEV: Hardware Event Valid. /
1579	uint32_t u1Overflow : 1; /*< Bit 1 - HEO: Hardware Event Overflow. /
1580	uint32_t u30Rsvd0 : 30; /*< Bits 31:2 - Reserved. /
1581	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1582	} n;
1583	/** The 64-bit unsigned integer view. */
1584	uint64_t u64;
1585	} IOMMU_HW_EVT_STATUS_T;
1586	AssertCompileSize(IOMMU_HW_EVT_STATUS_T, 8);
1587	#define IOMMU_HW_EVT_STATUS_VALID_MASK UINT64_C(0x0000000000000003)
1588
1589	/**
1590	* Guest Virtual-APIC Log Base Address Register (MMIO).
1591	* In accordance with the AMD spec.
1592	*/
1593	typedef union
1594	{
1595	struct
1596	{
1597	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bit 11:0 - Reserved. /
1598	RT_GCC_EXTENSION uint64_t u40Base : 40; /*< Bits 51:12 - GALogBase: Guest Virtual-APIC Log Base Address. /
1599	RT_GCC_EXTENSION uint64_t u4Rsvd0 : 4; /*< Bits 55:52 - Reserved. /
1600	RT_GCC_EXTENSION uint64_t u4Len : 4; /*< Bits 59:56 - GALogLen: Guest Virtual-APIC Log Length. /
1601	RT_GCC_EXTENSION uint64_t u4Rsvd1 : 4; /*< Bits 63:60 - Reserved. /
1602	} n;
1603	/** The 64-bit unsigned integer view. */
1604	uint64_t u64;
1605	} GALOG_BAR_T;
1606	AssertCompileSize(GALOG_BAR_T, 8);
1607
1608	/**
1609	* Guest Virtual-APIC Log Tail Address Register (MMIO).
1610	* In accordance with the AMD spec.
1611	*/
1612	typedef union
1613	{
1614	struct
1615	{
1616	RT_GCC_EXTENSION uint64_t u3Rsvd0 : 3; /*< Bits 2:0 - Reserved. /
1617	RT_GCC_EXTENSION uint64_t u40GALogTailAddr : 48; /*< Bits 51:3 - GATAddr: Guest Virtual-APIC Tail Log Address. /
1618	RT_GCC_EXTENSION uint64_t u11Rsvd1 : 11; /*< Bits 63:52 - Reserved. /
1619	} n;
1620	/** The 64-bit unsigned integer view. */
1621	uint64_t u64;
1622	} GALOG_TAIL_ADDR_T;
1623	AssertCompileSize(GALOG_TAIL_ADDR_T, 8);
1624
1625	/**
1626	* PPR Log B Base Address Register (MMIO).
1627	* In accordance with the AMD spec.
1628	* Currently identical to PPR_LOG_BAR_T.
1629	*/
1630	typedef PPR_LOG_BAR_T PPR_LOG_B_BAR_T;
1631
1632	/**
1633	* Event Log B Base Address Register (MMIO).
1634	* In accordance with the AMD spec.
1635	* Currently identical to EVT_LOG_BAR_T.
1636	*/
1637	typedef EVT_LOG_BAR_T EVT_LOG_B_BAR_T;
1638
1639	/**
1640	* Device-specific Feature Extension (DSFX) Register (MMIO).
1641	* In accordance with the AMD spec.
1642	*/
1643	typedef union
1644	{
1645	struct
1646	{
1647	uint32_t u24DevSpecFeat : 24; /*< Bits 23:0 - DevSpecificFeatSupp: Implementation specific features. /
1648	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1649	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1650	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1651	} n;
1652	/** The 64-bit unsigned integer view. */
1653	uint64_t u64;
1654	} DEV_SPECIFIC_FEAT_T;
1655	AssertCompileSize(DEV_SPECIFIC_FEAT_T, 8);
1656
1657	/**
1658	* Device-specific Control Extension (DSCX) Register (MMIO).
1659	* In accordance with the AMD spec.
1660	*/
1661	typedef union
1662	{
1663	struct
1664	{
1665	uint32_t u24DevSpecCtrl : 24; /*< Bits 23:0 - DevSpecificFeatCntrl: Implementation specific control. /
1666	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1667	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1668	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1669	} n;
1670	/** The 64-bit unsigned integer view. */
1671	uint64_t u64;
1672	} DEV_SPECIFIC_CTRL_T;
1673	AssertCompileSize(DEV_SPECIFIC_CTRL_T, 8);
1674
1675	/**
1676	* Device-specific Status Extension (DSSX) Register (MMIO).
1677	* In accordance with the AMD spec.
1678	*/
1679	typedef union
1680	{
1681	struct
1682	{
1683	uint32_t u24DevSpecStatus : 24; /*< Bits 23:0 - DevSpecificFeatStatus: Implementation specific status. /
1684	uint32_t u4RevMinor : 4; /*< Bits 27:24 - RevMinor: Minor revision identifier. /
1685	uint32_t u4RevMajor : 4; /*< Bits 31:28 - RevMajor: Major revision identifier. /
1686	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
1687	} n;
1688	/** The 64-bit unsigned integer view. */
1689	uint64_t u64;
1690	} DEV_SPECIFIC_STATUS_T;
1691	AssertCompileSize(DEV_SPECIFIC_STATUS_T, 8);
1692
1693	/**
1694	* MSI Information Register 0 and 1 (PCI) / MSI Vector Register 0 and 1 (MMIO).
1695	* In accordance with the AMD spec.
1696	*/
1697	typedef union
1698	{
1699	struct
1700	{
1701	uint32_t u5MsiNumEvtLog : 5; /*< Bits 4:0 - MsiNum: Event Log MSI message number. /
1702	uint32_t u3GstVirtAddrSize: 3; /*< Bits 7:5 - GVAsize: Guest Virtual Address Size. /
1703	uint32_t u7PhysAddrSize : 7; /*< Bits 14:8 - PAsize: Physical Address Size. /
1704	uint32_t u7VirtAddrSize : 7; /*< Bits 21:15 - VAsize: Virtual Address Size. /
1705	uint32_t u1HtAtsResv: 1; /*< Bit 22 - HtAtsResv: HyperTransport ATS Response Address range Reserved. /
1706	uint32_t u4Rsvd0 : 4; /*< Bits 26:23 - Reserved. /
1707	uint32_t u5MsiNumPpr : 5; /*< Bits 31:27 - MsiNumPPR: Peripheral Page Request MSI message number. /
1708	uint32_t u5MsiNumGa : 5; /*< Bits 36:32 - MsiNumGa: MSI message number for guest virtual-APIC log. /
1709	uint32_t u27Rsvd0: 27; /*< Bits 63:37 - Reserved. /
1710	} n;
1711	/** The 32-bit unsigned integer view. */
1712	uint32_t au32[2];
1713	/** The 64-bit unsigned integer view. */
1714	uint64_t u64;
1715	} MSI_MISC_INFO_T;
1716	AssertCompileSize(MSI_MISC_INFO_T, 8);
1717	/** MSI Vector Register 0 and 1 (MMIO). */
1718	typedef MSI_MISC_INFO_T MSI_VECTOR_T;
1719
1720	/**
1721	* MSI Capability Header Register (PCI + MMIO).
1722	* In accordance with the AMD spec.
1723	*/
1724	typedef union
1725	{
1726	struct
1727	{
1728	uint32_t u8MsiCapId : 8; /*< Bits 7:0 - MsiCapId: Capability ID. /
1729	uint32_t u8MsiCapPtr : 8; /*< Bits 15:8 - MsiCapPtr: Pointer (PCI config offset) to the next capability. /
1730	uint32_t u1MsiEnable : 1; /*< Bit 16 - MsiEn: Message Signal Interrupt Enable. /
1731	uint32_t u3MsiMultiMessCap : 3; /*< Bits 19:17 - MsiMultMessCap: MSI Multi-Message Capability. /
1732	uint32_t u3MsiMultiMessEn : 3; /*< Bits 22:20 - MsiMultMessEn: MSI Multi-Message Enable. /
1733	uint32_t u1Msi64BitEn : 1; /*< Bit 23 - Msi64BitEn: MSI 64-bit Enable. /
1734	uint32_t u8Rsvd0 : 8; /*< Bits 31:24 - Reserved. /
1735	} n;
1736	/** The 32-bit unsigned integer view. */
1737	uint32_t u32;
1738	} MSI_CAP_HDR_T;
1739	AssertCompileSize(MSI_CAP_HDR_T, 4);
1740	#define IOMMU_MSI_CAP_HDR_MSI_EN_MASK RT_BIT(16)
1741
1742	/**
1743	* MSI Mapping Capability Header Register (PCI + MMIO).
1744	* In accordance with the AMD spec.
1745	*/
1746	typedef union
1747	{
1748	struct
1749	{
1750	uint32_t u8MsiMapCapId : 8; /*< Bits 7:0 - MsiMapCapId: MSI Map capability ID. /
1751	uint32_t u8Rsvd0 : 8; /*< Bits 15:8 - Reserved. /
1752	uint32_t u1MsiMapEn : 1; /*< Bit 16 - MsiMapEn: MSI Map enable. /
1753	uint32_t u1MsiMapFixed : 1; /*< Bit 17 - MsiMapFixd: MSI Map fixed. /
1754	uint32_t u9Rsvd0 : 9; /*< Bits 26:18 - Reserved. /
1755	uint32_t u5MapCapType : 5; /*< Bits 31:27 - MsiMapCapType: MSI Mapping capability type. /
1756	} n;
1757	/** The 32-bit unsigned integer view. */
1758	uint32_t u32;
1759	} MSI_MAP_CAP_HDR_T;
1760	AssertCompileSize(MSI_MAP_CAP_HDR_T, 4);
1761
1762	/**
1763	* Performance Optimization Control Register (MMIO).
1764	* In accordance with the AMD spec.
1765	*/
1766	typedef union
1767	{
1768	struct
1769	{
1770	uint32_t u13Rsvd0 : 13; /*< Bits 12:0 - Reserved. /
1771	uint32_t u1PerfOptEn : 1; /*< Bit 13 - PerfOptEn: Performance Optimization Enable. /
1772	uint32_t u17Rsvd0 : 18; /*< Bits 31:14 - Reserved. /
1773	} n;
1774	/** The 32-bit unsigned integer view. */
1775	uint32_t u32;
1776	} IOMMU_PERF_OPT_CTRL_T;
1777	AssertCompileSize(IOMMU_PERF_OPT_CTRL_T, 4);
1778
1779	/**
1780	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1781	* In accordance with the AMD spec.
1782	*/
1783	typedef union
1784	{
1785	struct
1786	{
1787	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1788	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for general interrupt./
1789	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1790	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for general interrupt (Lo)./
1791	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for general interrupt./
1792	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for general interrupt./
1793	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1794	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for general interrupt (Hi) ./
1795	} n;
1796	/** The 64-bit unsigned integer view. */
1797	uint64_t u64;
1798	} IOMMU_XT_GEN_INTR_CTRL_T;
1799	AssertCompileSize(IOMMU_XT_GEN_INTR_CTRL_T, 8);
1800
1801	/**
1802	* XT (x2APIC) IOMMU General Interrupt Control Register (MMIO).
1803	* In accordance with the AMD spec.
1804	*/
1805	typedef union
1806	{
1807	struct
1808	{
1809	uint32_t u2Rsvd0 : 2; /*< Bits 1:0 - Reserved./
1810	uint32_t u1X2ApicIntrDstMode : 1; /*< Bit 2 - Destination Mode for the interrupt./
1811	uint32_t u4Rsvd0 : 4; /*< Bits 7:3 - Reserved./
1812	uint32_t u24X2ApicIntrDstLo : 24; /*< Bits 31:8 - Destination for the interrupt (Lo)./
1813	uint32_t u8X2ApicIntrVector : 8; /*< Bits 39:32 - Vector for the interrupt./
1814	uint32_t u1X2ApicIntrDeliveryMode : 1; /*< Bit 40 - Delivery Mode for the interrupt./
1815	uint32_t u15Rsvd0 : 15; /*< Bits 55:41 - Reserved./
1816	uint32_t u7X2ApicIntrDstHi : 7; /*< Bits 63:56 - Destination for the interrupt (Hi) ./
1817	} n;
1818	/** The 64-bit unsigned integer view. */
1819	uint64_t u64;
1820	} IOMMU_XT_INTR_CTRL_T;
1821	AssertCompileSize(IOMMU_XT_INTR_CTRL_T, 8);
1822
1823	/**
1824	* XT (x2APIC) IOMMU PPR Interrupt Control Register (MMIO).
1825	* In accordance with the AMD spec.
1826	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1827	*/
1828	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_PPR_INTR_CTRL_T;
1829
1830	/**
1831	* XT (x2APIC) IOMMU GA (Guest Address) Log Control Register (MMIO).
1832	* In accordance with the AMD spec.
1833	* Currently identical to IOMMU_XT_INTR_CTRL_T.
1834	*/
1835	typedef IOMMU_XT_INTR_CTRL_T IOMMU_XT_GALOG_INTR_CTRL_T;
1836
1837	/**
1838	* Memory Access and Routing Control (MARC) Aperture Base Register (MMIO).
1839	* In accordance with the AMD spec.
1840	*/
1841	typedef union
1842	{
1843	struct
1844	{
1845	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1846	RT_GCC_EXTENSION uint64_t u40MarcBaseAddr : 40; /*< Bits 51:12 - MarcBaseAddr: MARC Aperture Base Address. /
1847	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1848	} n;
1849	/** The 64-bit unsigned integer view. */
1850	uint64_t u64;
1851	} MARC_APER_BAR_T;
1852	AssertCompileSize(MARC_APER_BAR_T, 8);
1853
1854	/**
1855	* Memory Access and Routing Control (MARC) Relocation Register (MMIO).
1856	* In accordance with the AMD spec.
1857	*/
1858	typedef union
1859	{
1860	struct
1861	{
1862	RT_GCC_EXTENSION uint64_t u1RelocEn : 1; /*< Bit 0 - RelocEn: Relocation Enabled. /
1863	RT_GCC_EXTENSION uint64_t u1ReadOnly : 1; /*< Bit 1 - ReadOnly: Whether only read-only acceses allowed. /
1864	RT_GCC_EXTENSION uint64_t u10Rsvd0 : 10; /*< Bits 11:2 - Reserved. /
1865	RT_GCC_EXTENSION uint64_t u40MarcRelocAddr : 40; /*< Bits 51:12 - MarcRelocAddr: MARC Aperture Relocation Address. /
1866	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1867	} n;
1868	/** The 64-bit unsigned integer view. */
1869	uint64_t u64;
1870	} MARC_APER_RELOC_T;
1871	AssertCompileSize(MARC_APER_RELOC_T, 8);
1872
1873	/**
1874	* Memory Access and Routing Control (MARC) Length Register (MMIO).
1875	* In accordance with the AMD spec.
1876	*/
1877	typedef union
1878	{
1879	struct
1880	{
1881	RT_GCC_EXTENSION uint64_t u12Rsvd0 : 12; /*< Bits 11:0 - Reserved. /
1882	RT_GCC_EXTENSION uint64_t u40MarcLength : 40; /*< Bits 51:12 - MarcLength: MARC Aperture Length. /
1883	RT_GCC_EXTENSION uint64_t u12Rsvd1 : 12; /*< Bits 63:52 - Reserved. /
1884	} n;
1885	/** The 64-bit unsigned integer view. */
1886	uint64_t u64;
1887	} MARC_APER_LEN_T;
1888
1889	/**
1890	* Memory Access and Routing Control (MARC) Aperture Register.
1891	* This combines other registers to match the MMIO layout for convenient access.
1892	*/
1893	typedef struct
1894	{
1895	MARC_APER_BAR_T Base;
1896	MARC_APER_RELOC_T Reloc;
1897	MARC_APER_LEN_T Length;
1898	} MARC_APER_T;
1899	AssertCompileSize(MARC_APER_T, 24);
1900
1901	/**
1902	* IOMMU Reserved Register (MMIO).
1903	* In accordance with the AMD spec.
1904	* This register is reserved for hardware use (although RW?).
1905	*/
1906	typedef uint64_t IOMMU_RSVD_REG_T;
1907
1908	/**
1909	* Command Buffer Head Pointer Register (MMIO).
1910	* In accordance with the AMD spec.
1911	*/
1912	typedef union
1913	{
1914	struct
1915	{
1916	uint32_t off; /*< Bits 31:0 - Buffer pointer (offset; 16 byte aligned, 512 KB max). /
1917	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
1918	} n;
1919	/** The 32-bit unsigned integer view. */
1920	uint32_t au32[2];
1921	/** The 64-bit unsigned integer view. */
1922	uint64_t u64;
1923	} CMD_BUF_HEAD_PTR_T;
1924	AssertCompileSize(CMD_BUF_HEAD_PTR_T, 8);
1925	#define IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK UINT64_C(0x000000000007fff0)
1926
1927	/**
1928	* Command Buffer Tail Pointer Register (MMIO).
1929	* In accordance with the AMD spec.
1930	* Currently identical to CMD_BUF_HEAD_PTR_T.
1931	*/
1932	typedef CMD_BUF_HEAD_PTR_T CMD_BUF_TAIL_PTR_T;
1933	#define IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1934
1935	/**
1936	* Event Log Head Pointer Register (MMIO).
1937	* In accordance with the AMD spec.
1938	* Currently identical to CMD_BUF_HEAD_PTR_T.
1939	*/
1940	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_HEAD_PTR_T;
1941	#define IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1942
1943	/**
1944	* Event Log Tail Pointer Register (MMIO).
1945	* In accordance with the AMD spec.
1946	* Currently identical to CMD_BUF_HEAD_PTR_T.
1947	*/
1948	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_TAIL_PTR_T;
1949	#define IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK
1950
1951
1952	/**
1953	* IOMMU Status Register (MMIO).
1954	* In accordance with the AMD spec.
1955	*/
1956	typedef union
1957	{
1958	struct
1959	{
1960	uint32_t u1EvtOverflow : 1; /*< Bit 0 - EventOverflow: Event log overflow. /
1961	uint32_t u1EvtLogIntr : 1; /*< Bit 1 - EventLogInt: Event log interrupt. /
1962	uint32_t u1CompWaitIntr : 1; /*< Bit 2 - ComWaitInt: Completion wait interrupt . /
1963	uint32_t u1EvtLogRunning : 1; /*< Bit 3 - EventLogRun: Event logging is running. /
1964	uint32_t u1CmdBufRunning : 1; /*< Bit 4 - CmdBufRun: Command buffer is running. /
1965	uint32_t u1PprOverflow : 1; /*< Bit 5 - PprOverflow: Peripheral Page Request Log (PPR) overflow. /
1966	uint32_t u1PprIntr : 1; /*< Bit 6 - PprInt: PPR interrupt. /
1967	uint32_t u1PprLogRunning : 1; /*< Bit 7 - PprLogRun: PPR logging is running. /
1968	uint32_t u1GstLogRunning : 1; /*< Bit 8 - GALogRun: Guest virtual-APIC logging is running. /
1969	uint32_t u1GstLogOverflow : 1; /*< Bit 9 - GALOverflow: Guest virtual-APIC log overflow. /
1970	uint32_t u1GstLogIntr : 1; /*< Bit 10 - GAInt: Guest virtual-APIC log interrupt. /
1971	uint32_t u1PprOverflowB : 1; /*< Bit 11 - PprOverflowB: PPR log B overflow. /
1972	uint32_t u1PprLogActive : 1; /*< Bit 12 - PprLogActive: PPR log A is active. /
1973	uint32_t u2Rsvd0 : 2; /*< Bits 14:13 - Reserved. /
1974	uint32_t u1EvtOverflowB : 1; /*< Bit 15 - EvtOverflowB: Event log B overflow. /
1975	uint32_t u1EvtLogActive : 1; /*< Bit 16 - EvtLogActive: Event log A active. /
1976	uint32_t u1PprOverflowEarlyB : 1; /*< Bit 17 - PprOverflowEarlyB: PPR log B overflow early warning. /
1977	uint32_t u1PprOverflowEarly : 1; /*< Bit 18 - PprOverflowEarly: PPR log overflow early warning. /
1978	uint32_t u13Rsvd0 : 13; /*< Bits 31:19 - Reserved. /
1979	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved . /
1980	} n;
1981	/** The 32-bit unsigned integer view. */
1982	uint32_t au32[2];
1983	/** The 64-bit unsigned integer view. */
1984	uint64_t u64;
1985	} IOMMU_STATUS_T;
1986	AssertCompileSize(IOMMU_STATUS_T, 8);
1987	#define IOMMU_STATUS_VALID_MASK UINT64_C(0x0000000000079fff)
1988	#define IOMMU_STATUS_RW1C_MASK UINT64_C(0x0000000000068e67)
1989
1990	/**
1991	* PPR Log Head Pointer Register (MMIO).
1992	* In accordance with the AMD spec.
1993	* Currently identical to CMD_BUF_HEAD_PTR_T.
1994	*/
1995	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_HEAD_PTR_T;
1996
1997	/**
1998	* PPR Log Tail Pointer Register (MMIO).
1999	* In accordance with the AMD spec.
2000	* Currently identical to CMD_BUF_HEAD_PTR_T.
2001	*/
2002	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_TAIL_PTR_T;
2003
2004	/**
2005	* Guest Virtual-APIC Log Head Pointer Register (MMIO).
2006	* In accordance with the AMD spec.
2007	*/
2008	typedef union
2009	{
2010	struct
2011	{
2012	uint32_t u2Rsvd0 : 2; /*< Bits 2:0 - Reserved. /
2013	uint32_t u12GALogPtr : 12; /*< Bits 15:3 - Guest Virtual-APIC Log Head or Tail Pointer. /
2014	uint32_t u16Rsvd0 : 16; /*< Bits 31:16 - Reserved. /
2015	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2016	} n;
2017	/** The 32-bit unsigned integer view. */
2018	uint32_t au32[2];
2019	/** The 64-bit unsigned integer view. */
2020	uint64_t u64;
2021	} GALOG_HEAD_PTR_T;
2022	AssertCompileSize(GALOG_HEAD_PTR_T, 8);
2023
2024	/**
2025	* Guest Virtual-APIC Log Tail Pointer Register (MMIO).
2026	* In accordance with the AMD spec.
2027	* Currently identical to GALOG_HEAD_PTR_T.
2028	*/
2029	typedef GALOG_HEAD_PTR_T GALOG_TAIL_PTR_T;
2030
2031	/**
2032	* PPR Log B Head Pointer Register (MMIO).
2033	* In accordance with the AMD spec.
2034	* Currently identical to CMD_BUF_HEAD_PTR_T.
2035	*/
2036	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_HEAD_PTR_T;
2037
2038	/**
2039	* PPR Log B Tail Pointer Register (MMIO).
2040	* In accordance with the AMD spec.
2041	* Currently identical to CMD_BUF_HEAD_PTR_T.
2042	*/
2043	typedef CMD_BUF_HEAD_PTR_T PPR_LOG_B_TAIL_PTR_T;
2044
2045	/**
2046	* Event Log B Head Pointer Register (MMIO).
2047	* In accordance with the AMD spec.
2048	* Currently identical to CMD_BUF_HEAD_PTR_T.
2049	*/
2050	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_HEAD_PTR_T;
2051
2052	/**
2053	* Event Log B Tail Pointer Register (MMIO).
2054	* In accordance with the AMD spec.
2055	* Currently identical to CMD_BUF_HEAD_PTR_T.
2056	*/
2057	typedef CMD_BUF_HEAD_PTR_T EVT_LOG_B_TAIL_PTR_T;
2058
2059	/**
2060	* PPR Log Auto Response Register (MMIO).
2061	* In accordance with the AMD spec.
2062	*/
2063	typedef union
2064	{
2065	struct
2066	{
2067	uint32_t u4AutoRespCode : 4; /*< Bits 3:0 - PprAutoRespCode: PPR log Auto Response Code. /
2068	uint32_t u1AutoRespMaskGen : 1; /*< Bit 4 - PprAutoRespMaskGn: PPR log Auto Response Mask Gen. /
2069	uint32_t u27Rsvd0 : 27; /*< Bits 31:5 - Reserved. /
2070	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved./
2071	} n;
2072	/** The 32-bit unsigned integer view. */
2073	uint32_t au32[2];
2074	/** The 64-bit unsigned integer view. */
2075	uint64_t u64;
2076	} PPR_LOG_AUTO_RESP_T;
2077	AssertCompileSize(PPR_LOG_AUTO_RESP_T, 8);
2078
2079	/**
2080	* PPR Log Overflow Early Indicator Register (MMIO).
2081	* In accordance with the AMD spec.
2082	*/
2083	typedef union
2084	{
2085	struct
2086	{
2087	uint32_t u15Threshold : 15; /*< Bits 14:0 - PprOvrflwEarlyThreshold: Overflow early indicator threshold. /
2088	uint32_t u15Rsvd0 : 15; /*< Bits 29:15 - Reserved. /
2089	uint32_t u1IntrEn : 1; /*< Bit 30 - PprOvrflwEarlyIntEn: Overflow early indicator interrupt enable. /
2090	uint32_t u1Enable : 1; /*< Bit 31 - PprOvrflwEarlyEn: Overflow early indicator enable. /
2091	uint32_t u32Rsvd0; /*< Bits 63:32 - Reserved. /
2092	} n;
2093	/** The 32-bit unsigned integer view. */
2094	uint32_t au32[2];
2095	/** The 64-bit unsigned integer view. */
2096	uint64_t u64;
2097	} PPR_LOG_OVERFLOW_EARLY_T;
2098	AssertCompileSize(PPR_LOG_OVERFLOW_EARLY_T, 8);
2099
2100	/**
2101	* PPR Log B Overflow Early Indicator Register (MMIO).
2102	* In accordance with the AMD spec.
2103	* Currently identical to PPR_LOG_OVERFLOW_EARLY_T.
2104	*/
2105	typedef PPR_LOG_OVERFLOW_EARLY_T PPR_LOG_B_OVERFLOW_EARLY_T;
2106
2107	/**
2108	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2109	* In accordance with the AMD spec.
2110	*/
2111	typedef enum EVT_ILLEGAL_DTE_TYPE_T
2112	{
2113	kIllegalDteType_RsvdNotZero = 0,
2114	kIllegalDteType_RsvdIntTabLen,
2115	kIllegalDteType_RsvdIoCtl,
2116	kIllegalDteType_RsvdIntCtl
2117	} EVT_ILLEGAL_DTE_TYPE_T;
2118
2119	/**
2120	* ILLEGAL_DEV_TABLE_ENTRY Event Types.
2121	* In accordance with the AMD spec.
2122	*/
2123	typedef enum EVT_IO_PAGE_FAULT_TYPE_T
2124	{
2125	/* Memory transaction. */
2126	kIoPageFaultType_DteRsvdPagingMode = 0,
2127	kIoPageFaultType_PteInvalidPageSize,
2128	kIoPageFaultType_PteInvalidLvlEncoding,
2129	kIoPageFaultType_SkippedLevelIovaNotZero,
2130	kIoPageFaultType_PteRsvdNotZero,
2131	kIoPageFaultType_PteValidNotSet,
2132	kIoPageFaultType_DteTranslationDisabled,
2133	kIoPageFaultType_PasidInvalidRange,
2134	kIoPageFaultType_PermDenied,
2135	kIoPageFaultType_UserSupervisor,
2136	/* Interrupt remapping */
2137	kIoPageFaultType_IrteAddrInvalid,
2138	kIoPageFaultType_IrteRsvdNotZero,
2139	kIoPageFaultType_IrteRemapEn,
2140	kIoPageFaultType_IrteRsvdIntType,
2141	kIoPageFaultType_IntrReqAborted,
2142	kIoPageFaultType_IntrWithPasid,
2143	kIoPageFaultType_SmiFilterMismatch,
2144	/* Memory transaction or interrupt remapping. */
2145	kIoPageFaultType_DevId_Invalid
2146	} EVT_IO_PAGE_FAULT_TYPE_T;
2147
2148	/**
2149	* IOTLB_INV_TIMEOUT Event Types.
2150	* In accordance with the AMD spec.
2151	*/
2152	typedef enum EVT_IOTLB_INV_TIMEOUT_TYPE_T
2153	{
2154	InvTimeoutType_NoResponse = 0
2155	} EVT_IOTLB_INV_TIMEOUT_TYPE_T;
2156
2157	/**
2158	* INVALID_DEVICE_REQUEST Event Types.
2159	* In accordance with the AMD spec.
2160	*/
2161	typedef enum EVT_INVALID_DEV_REQ_TYPE_T
2162	{
2163	/* Access. */
2164	kInvalidDevReqType_ReadOrNonPostedWrite = 0,
2165	kInvalidDevReqType_PretranslatedTransaction,
2166	kInvalidDevReqType_PortIo,
2167	kInvalidDevReqType_SysMgt,
2168	kInvalidDevReqType_IntrRange,
2169	kInvalidDevReqType_RsvdIntrRange,
2170	kInvalidDevReqType_SysMgtAddr,
2171	/* Translation Request. */
2172	kInvalidDevReqType_TrAccessInvalid,
2173	kInvalidDevReqType_TrDisabled,
2174	kInvalidDevReqType_DevIdInvalid,
2175	} EVT_INVALID_DEV_REQ_TYPE_T;
2176
2177	/**
2178	* INVALID_PPR_REQUEST Event Types.
2179	* In accordance with the AMD spec.
2180	*/
2181	typedef enum EVT_INVALID_PPR_REQ_TYPE_T
2182	{
2183	kInvalidPprReqType_PriNotSupported,
2184	kInvalidPprReqType_GstTranslateDisabled
2185	} EVT_INVALID_PPR_REQ_TYPE_T;
2186
2187	/**
2188	* IOMMU operations (transaction) types.
2189	*/
2190	typedef enum IOMMUOP
2191	{
2192	/** Address translation request. */
2193	IOMMUOP_TRANSLATE_REQ = 0,
2194	/** Memory read request. */
2195	IOMMUOP_MEM_READ,
2196	/** Memory write request. */
2197	IOMMUOP_MEM_WRITE,
2198	/** Interrupt request. */
2199	IOMMUOP_INTR_REQ,
2200	/** Command. */
2201	IOMMUOP_CMD
2202	} IOMMUOP;
2203	AssertCompileSize(IOMMUOP, 4);
2204
2205	/**
2206	* I/O page walk result.
2207	*/
2208	typedef struct
2209	{
2210	/** The translated system physical address. */
2211	RTGCPHYS GCPhysSpa;
2212	/** The number of offset bits in the system physical address. */
2213	uint8_t cShift;
2214	/** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
2215	uint8_t fIoPerm;
2216	/** Padding. */
2217	uint8_t abPadding[2];
2218	} IOWALKRESULT;
2219	/** Pointer to an I/O walk result struct. */
2220	typedef IOWALKRESULT *PIOWALKRESULT;
2221	/** Pointer to a const I/O walk result struct. */
2222	typedef IOWALKRESULT *PCIOWALKRESULT;
2223
2224	/**
2225	* IOMMU I/O TLB Entry.
2226	* Keep this as small and aligned as possible.
2227	*/
2228	typedef struct
2229	{
2230	/** The translated system physical address (SPA) of the page. */
2231	RTGCPHYS GCPhysSpa;
2232	/** The index of the 4K page within a large page. */
2233	uint32_t idxSubPage;
2234	/** The I/O access permissions (IOMMU_IO_PERM_XXX). */
2235	uint8_t fIoPerm;
2236	/** The number of offset bits in the translation indicating page size. */
2237	uint8_t cShift;
2238	/** Alignment padding. */
2239	uint8_t afPadding[2];
2240	} IOTLBE_T;
2241	AssertCompileSize(IOTLBE_T, 16);
2242	/** Pointer to an IOMMU I/O TLB entry struct. */
2243	typedef IOTLBE_T *PIOTLBE_T;
2244	/** Pointer to a const IOMMU I/O TLB entry struct. */
2245	typedef IOTLBE_T const *PCIOTLBE_T;
2246
2247	/**
2248	* The shared IOMMU device state.
2249	*/
2250	typedef struct IOMMU
2251	{
2252	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
2253	uint32_t idxIommu;
2254	/** Alignment padding. */
2255	uint32_t uPadding0;
2256
2257	/** Whether the command thread is sleeping. */
2258	bool volatile fCmdThreadSleeping;
2259	/** Alignment padding. */
2260	uint8_t afPadding0[3];
2261	/** Whether the command thread has been signaled for wake up. */
2262	bool volatile fCmdThreadSignaled;
2263	/** Alignment padding. */
2264	uint8_t afPadding1[3];
2265
2266	/** The event semaphore the command thread waits on. */
2267	SUPSEMEVENT hEvtCmdThread;
2268	/** The MMIO handle. */
2269	IOMMMIOHANDLE hMmio;
2270
2271	/** @name PCI: Base capability block registers.
2272	* @{ */
2273	IOMMU_BAR_T IommuBar; /*< IOMMU base address register. /
2274	/** @} */
2275
2276	/** @name MMIO: Control and status registers.
2277	* @{ */
2278	DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /*< Device table base address registers. /
2279	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
2280	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
2281	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
2282	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
2283	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
2284	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
2285	/** @} */
2286
2287	/** @name MMIO: PPR Log registers.
2288	* @{ */
2289	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
2290	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
2291	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
2292	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
2293	/** @} */
2294
2295	/** @todo IOMMU: SMI filter. */
2296
2297	/** @name MMIO: Guest Virtual-APIC Log registers.
2298	* @{ */
2299	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
2300	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
2301	/** @} */
2302
2303	/** @name MMIO: Alternate PPR and Event Log registers.
2304	* @{ */
2305	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
2306	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
2307	/** @} */
2308
2309	/** @name MMIO: Device-specific feature registers.
2310	* @{ */
2311	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
2312	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
2313	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
2314	/** @} */
2315
2316	/** @name MMIO: MSI Capability Block registers.
2317	* @{ */
2318	MSI_MISC_INFO_T MiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
2319	/** @} */
2320
2321	/** @name MMIO: Performance Optimization Control registers.
2322	* @{ */
2323	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
2324	/** @} */
2325
2326	/** @name MMIO: x2APIC Control registers.
2327	* @{ */
2328	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
2329	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
2330	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
2331	/** @} */
2332
2333	/** @name MMIO: MARC registers.
2334	* @{ */
2335	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
2336	/** @} */
2337
2338	/** @name MMIO: Reserved register.
2339	* @{ */
2340	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
2341	/** @} */
2342
2343	/** @name MMIO: Command and Event Log pointer registers.
2344	* @{ */
2345	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
2346	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
2347	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
2348	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
2349	/** @} */
2350
2351	/** @name MMIO: Command and Event Status register.
2352	* @{ */
2353	IOMMU_STATUS_T Status; /*< IOMMU status register. /
2354	/** @} */
2355
2356	/** @name MMIO: PPR Log Head and Tail pointer registers.
2357	* @{ */
2358	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
2359	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
2360	/** @} */
2361
2362	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
2363	* @{ */
2364	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
2365	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
2366	/** @} */
2367
2368	/** @name MMIO: PPR Log B Head and Tail pointer registers.
2369	* @{ */
2370	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
2371	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
2372	/** @} */
2373
2374	/** @name MMIO: Event Log B Head and Tail pointer registers.
2375	* @{ */
2376	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
2377	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
2378	/** @} */
2379
2380	/** @name MMIO: PPR Log Overflow protection registers.
2381	* @{ */
2382	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
2383	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
2384	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
2385	/** @} */
2386
2387	/** @todo IOMMU: IOMMU Event counter registers. */
2388
2389	/** @todo IOMMU: Stat counters. */
2390	} IOMMU;
2391	/** Pointer to the IOMMU device state. */
2392	typedef struct IOMMU *PIOMMU;
2393	/** Pointer to the const IOMMU device state. */
2394	typedef const struct IOMMU *PCIOMMU;
2395	AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
2396	AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
2397	AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
2398	AssertCompileMemberAlignment(IOMMU, hMmio, 8);
2399	AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
2400
2401	/**
2402	* The ring-3 IOMMU device state.
2403	*/
2404	typedef struct IOMMUR3
2405	{
2406	/** Device instance. */
2407	PPDMDEVINSR3 pDevInsR3;
2408	/** The IOMMU helpers. */
2409	PCPDMIOMMUHLPR3 pIommuHlpR3;
2410	/** The command thread handle. */
2411	R3PTRTYPE(PPDMTHREAD) pCmdThread;
2412	} IOMMUR3;
2413	/** Pointer to the ring-3 IOMMU device state. */
2414	typedef IOMMUR3 *PIOMMUR3;
2415
2416	/**
2417	* The ring-0 IOMMU device state.
2418	*/
2419	typedef struct IOMMUR0
2420	{
2421	/** Device instance. */
2422	PPDMDEVINSR0 pDevInsR0;
2423	/** The IOMMU helpers. */
2424	PCPDMIOMMUHLPR0 pIommuHlpR0;
2425	} IOMMUR0;
2426	/** Pointer to the ring-0 IOMMU device state. */
2427	typedef IOMMUR0 *PIOMMUR0;
2428
2429	/**
2430	* The raw-mode IOMMU device state.
2431	*/
2432	typedef struct IOMMURC
2433	{
2434	/** Device instance. */
2435	PPDMDEVINSR0 pDevInsRC;
2436	/** The IOMMU helpers. */
2437	PCPDMIOMMUHLPRC pIommuHlpRC;
2438	} IOMMURC;
2439	/** Pointer to the raw-mode IOMMU device state. */
2440	typedef IOMMURC *PIOMMURC;
2441
2442	/** The IOMMU device state for the current context. */
2443	typedef CTX_SUFF(IOMMU) IOMMUCC;
2444	/** Pointer to the IOMMU device state for the current context. */
2445	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
2446
2447	/**
2448	* IOMMU register access routines.
2449	*/
2450	typedef struct
2451	{
2452	const char *pszName;
2453	VBOXSTRICTRC (pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t pu64Value);
2454	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
2455	bool f64BitReg;
2456	} IOMMUREGACC;
2457
2458
2459	/*********************************************************************************************************************************
2460	* Global Variables *
2461	*********************************************************************************************************************************/
2462	/**
2463	* An array of the number of device table segments supported.
2464	* Indexed by u2DevTabSegSup.
2465	*/
2466	static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
2467
2468	/**
2469	* An array of the masks to select the device table segment index from a device ID.
2470	*/
2471	static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
2472
2473	/**
2474	* The maximum size (inclusive) of each device table segment (0 to 7).
2475	* Indexed by the device table segment index.
2476	*/
2477	static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
2478
2479
2480	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
2481	/**
2482	* Gets the maximum number of buffer entries for the given buffer length.
2483	*
2484	* @returns Number of buffer entries.
2485	* @param uEncodedLen The length (power-of-2 encoded).
2486	*/
2487	DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
2488	{
2489	Assert(uEncodedLen > 7);
2490	return 2 << (uEncodedLen - 1);
2491	}
2492
2493
2494	/**
2495	* Gets the total length of the buffer given a base register's encoded length.
2496	*
2497	* @returns The length of the buffer in bytes.
2498	* @param uEncodedLen The length (power-of-2 encoded).
2499	*/
2500	DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
2501	{
2502	Assert(uEncodedLen > 7);
2503	return (2 << (uEncodedLen - 1)) << 4;
2504	}
2505
2506
2507	/**
2508	* Gets the number of (unconsumed) entries in the event log.
2509	*
2510	* @returns The number of entries in the event log.
2511	* @param pThis The IOMMU device state.
2512	*/
2513	static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
2514	{
2515	uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2516	uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
2517	if (idxTail >= idxHead)
2518	return idxTail - idxHead;
2519
2520	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2521	return cMaxEvts - idxHead + idxTail;
2522	}
2523
2524
2525	/**
2526	* Gets the number of (unconsumed) commands in the command buffer.
2527	*
2528	* @returns The number of commands in the command buffer.
2529	* @param pThis The IOMMU device state.
2530	*/
2531	static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
2532	{
2533	uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2534	uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
2535	if (idxTail >= idxHead)
2536	return idxTail - idxHead;
2537
2538	uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
2539	return cMaxCmds - idxHead + idxTail;
2540	}
2541
2542
2543	DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
2544	{
2545	IOMMU_STATUS_T Status;
2546	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
2547	return Status;
2548	}
2549
2550
2551	DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
2552	{
2553	IOMMU_CTRL_T Ctrl;
2554	Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
2555	return Ctrl;
2556	}
2557
2558
2559	/**
2560	* Returns whether MSI is enabled for the IOMMU.
2561	*
2562	* @returns Whether MSI is enabled.
2563	* @param pDevIns The IOMMU device instance.
2564	*
2565	* @note There should be a PCIDevXxx function for this.
2566	*/
2567	static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
2568	{
2569	MSI_CAP_HDR_T MsiCapHdr;
2570	MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
2571	return MsiCapHdr.n.u1MsiEnable;
2572	}
2573
2574
2575	/**
2576	* Signals a PCI target abort.
2577	*
2578	* @param pDevIns The IOMMU device instance.
2579	*/
2580	static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
2581	{
2582	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2583	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2584	PDMPciDevSetStatus(pPciDev, u16Status);
2585	}
2586
2587
2588	/**
2589	* Wakes up the command thread if there are commands to be processed or if
2590	* processing is requested to be stopped by software.
2591	*
2592	* @param pDevIns The IOMMU device instance.
2593	*/
2594	static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
2595	{
2596	IOMMU_ASSERT_LOCKED(pDevIns);
2597
2598	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2599	if ( !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true)
2600	&& ASMAtomicReadBool(&pThis->fCmdThreadSleeping))
2601	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
2602	}
2603
2604
2605	/**
2606	* Writes to a read-only register.
2607	*/
2608	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2609	{
2610	RT_NOREF(pDevIns, pThis, iReg, u64Value);
2611	Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
2612	return VINF_SUCCESS;
2613	}
2614
2615
2616	/**
2617	* Writes the Device Table Base Address Register.
2618	*/
2619	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2620	{
2621	RT_NOREF(pDevIns, iReg);
2622
2623	/* Mask out all unrecognized bits. */
2624	u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2625
2626	/* Update the register. */
2627	pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2628	return VINF_SUCCESS;
2629	}
2630
2631
2632	/**
2633	* Writes the Command Buffer Base Address Register.
2634	*/
2635	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2636	{
2637	RT_NOREF(pDevIns, iReg);
2638
2639	/*
2640	* While this is not explicitly specified like the event log base address register,
2641	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2642	* Inconsistent specs :/
2643	*/
2644	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2645	if (Status.n.u1CmdBufRunning)
2646	{
2647	Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2648	return VINF_SUCCESS;
2649	}
2650
2651	/* Mask out all unrecognized bits. */
2652	CMD_BUF_BAR_T CmdBufBaseAddr;
2653	CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2654
2655	/* Validate the length. */
2656	if (CmdBufBaseAddr.n.u4Len >= 8)
2657	{
2658	/* Update the register. */
2659	pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2660
2661	/*
2662	* Writing the command buffer base address, clears the command buffer head and tail pointers.
2663	* See AMD spec. 2.4 "Commands".
2664	*/
2665	pThis->CmdBufHeadPtr.u64 = 0;
2666	pThis->CmdBufTailPtr.u64 = 0;
2667	}
2668	else
2669	Log((IOMMU_LOG_PFX ": Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2670
2671	return VINF_SUCCESS;
2672	}
2673
2674
2675	/**
2676	* Writes the Event Log Base Address Register.
2677	*/
2678	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2679	{
2680	RT_NOREF(pDevIns, iReg);
2681
2682	/*
2683	* IOMMU behavior is undefined when software writes this register when event logging is running.
2684	* In our emulation, we ignore the write entirely.
2685	* See AMD IOMMU spec. "Event Log Base Address Register".
2686	*/
2687	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2688	if (Status.n.u1EvtLogRunning)
2689	{
2690	Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2691	return VINF_SUCCESS;
2692	}
2693
2694	/* Mask out all unrecognized bits. */
2695	u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2696	EVT_LOG_BAR_T EvtLogBaseAddr;
2697	EvtLogBaseAddr.u64 = u64Value;
2698
2699	/* Validate the length. */
2700	if (EvtLogBaseAddr.n.u4Len >= 8)
2701	{
2702	/* Update the register. */
2703	pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2704
2705	/*
2706	* Writing the event log base address, clears the event log head and tail pointers.
2707	* See AMD spec. 2.5 "Event Logging".
2708	*/
2709	pThis->EvtLogHeadPtr.u64 = 0;
2710	pThis->EvtLogTailPtr.u64 = 0;
2711	}
2712	else
2713	Log((IOMMU_LOG_PFX ": Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2714
2715	return VINF_SUCCESS;
2716	}
2717
2718
2719	/**
2720	* Writes the Control Register.
2721	*/
2722	static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2723	{
2724	RT_NOREF(pDevIns, iReg);
2725
2726	/* Mask out all unrecognized bits. */
2727	u64Value &= IOMMU_CTRL_VALID_MASK;
2728
2729	IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
2730	IOMMU_CTRL_T NewCtrl;
2731	NewCtrl.u64 = u64Value;
2732
2733	/* Update the register. */
2734	ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2735
2736	/* Enable or disable event logging when the bit transitions. */
2737	bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2738	bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2739	bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2740	if (fOldEvtLogEn != fNewEvtLogEn)
2741	{
2742	if ( fNewIommuEn
2743	&& fNewEvtLogEn)
2744	{
2745	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2746	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2747	}
2748	else
2749	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2750	}
2751
2752	/* Enable or disable command buffer processing when the bit transitions. */
2753	bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2754	bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2755	if (fOldCmdBufEn != fNewCmdBufEn)
2756	{
2757	if ( fNewIommuEn
2758	&& fNewCmdBufEn)
2759	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2760	else
2761	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2762
2763	/* Wake up the command thread to start or stop processing commands. */
2764	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2765	}
2766	}
2767
2768
2769	/**
2770	* Writes to the Excluse Range Base Address Register.
2771	*/
2772	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2773	{
2774	RT_NOREF(pDevIns, iReg);
2775	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2776	return VINF_SUCCESS;
2777	}
2778
2779
2780	/**
2781	* Writes to the Excluse Range Limit Register.
2782	*/
2783	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2784	{
2785	RT_NOREF(pDevIns, iReg);
2786	u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2787	u64Value \|= UINT64_C(0xfff);
2788	pThis->ExclRangeLimit.u64 = u64Value;
2789	return VINF_SUCCESS;
2790	}
2791
2792
2793	/**
2794	* Writes the Hardware Event Register (Hi).
2795	*/
2796	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2797	{
2798	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2799	RT_NOREF(pDevIns, iReg);
2800	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2801	pThis->HwEvtHi.u64 = u64Value;
2802	return VINF_SUCCESS;
2803	}
2804
2805
2806	/**
2807	* Writes the Hardware Event Register (Lo).
2808	*/
2809	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2810	{
2811	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2812	RT_NOREF(pDevIns, iReg);
2813	Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2814	pThis->HwEvtLo = u64Value;
2815	return VINF_SUCCESS;
2816	}
2817
2818
2819	/**
2820	* Writes the Hardware Event Status Register.
2821	*/
2822	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2823	{
2824	RT_NOREF(pDevIns, iReg);
2825
2826	/* Mask out all unrecognized bits. */
2827	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2828
2829	/*
2830	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2831	* If the current status bits or the bits being written are both 0, we've nothing to do.
2832	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2833	*/
2834	uint64_t HwStatus = pThis->HwEvtStatus.u64;
2835	if (!(HwStatus & RT_BIT(0)))
2836	return VINF_SUCCESS;
2837	if (u64Value & HwStatus & RT_BIT_64(0))
2838	HwStatus &= ~RT_BIT_64(0);
2839	if (u64Value & HwStatus & RT_BIT_64(1))
2840	HwStatus &= ~RT_BIT_64(1);
2841
2842	/* Update the register. */
2843	pThis->HwEvtStatus.u64 = HwStatus;
2844	return VINF_SUCCESS;
2845	}
2846
2847
2848	/**
2849	* Writes the Device Table Segment Base Address Register.
2850	*/
2851	static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2852	{
2853	RT_NOREF(pDevIns);
2854
2855	/* Figure out which segment is being written. */
2856	uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2857	uint8_t const idxSegment = offSegment + 1;
2858	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2859
2860	/* Mask out all unrecognized bits. */
2861	u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2862	DEV_TAB_BAR_T DevTabSegBar;
2863	DevTabSegBar.u64 = u64Value;
2864
2865	/* Validate the size. */
2866	uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2867	uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2868	if (uSegSize <= uMaxSegSize)
2869	{
2870	/* Update the register. */
2871	pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2872	}
2873	else
2874	Log((IOMMU_LOG_PFX ": Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2875
2876	return VINF_SUCCESS;
2877	}
2878
2879
2880	/**
2881	* Writes the MSI Capability Header Register.
2882	*/
2883	static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2884	{
2885	RT_NOREF(pThis, iReg);
2886	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2887	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2888	MSI_CAP_HDR_T MsiCapHdr;
2889	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2890	MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2891	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2892	return VINF_SUCCESS;
2893	}
2894
2895
2896	/**
2897	* Writes the MSI Address (Lo) Register (32-bit).
2898	*/
2899	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2900	{
2901	RT_NOREF(pThis, iReg);
2902	Assert(!RT_HI_U32(u64Value));
2903	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2904	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2905	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
2906	return VINF_SUCCESS;
2907	}
2908
2909
2910	/**
2911	* Writes the MSI Address (Hi) Register (32-bit).
2912	*/
2913	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2914	{
2915	RT_NOREF(pThis, iReg);
2916	Assert(!RT_HI_U32(u64Value));
2917	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2918	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2919	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
2920	return VINF_SUCCESS;
2921	}
2922
2923
2924	/**
2925	* Writes the MSI Data Register (32-bit).
2926	*/
2927	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2928	{
2929	RT_NOREF(pThis, iReg);
2930	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2931	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2932	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
2933	return VINF_SUCCESS;
2934	}
2935
2936
2937	/**
2938	* Writes the Command Buffer Head Pointer Register (32-bit).
2939	*/
2940	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2941	{
2942	RT_NOREF(pDevIns, iReg);
2943
2944	/*
2945	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
2946	* In our emulation, we ignore the write entirely.
2947	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2948	*/
2949	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2950	if (Status.n.u1CmdBufRunning)
2951	{
2952	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2953	return VINF_SUCCESS;
2954	}
2955
2956	/*
2957	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2958	* In our emulation, we ignore the write entirely.
2959	*/
2960	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2961	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2962	Assert(cbBuf <= _512K);
2963	if (offBuf >= cbBuf)
2964	{
2965	Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
2966	offBuf, cbBuf));
2967	return VINF_SUCCESS;
2968	}
2969
2970	/* Update the register. */
2971	pThis->CmdBufHeadPtr.au32[0] = offBuf;
2972
2973	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2974
2975	LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
2976	return VINF_SUCCESS;
2977	}
2978
2979
2980	/**
2981	* Writes the Command Buffer Tail Pointer Register (32-bit).
2982	*/
2983	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
2984	{
2985	RT_NOREF(pDevIns, iReg);
2986
2987	/*
2988	* IOMMU behavior is undefined when software writes a value outside the buffer length.
2989	* In our emulation, we ignore the write entirely.
2990	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2991	*/
2992	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2993	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2994	Assert(cbBuf <= _512K);
2995	if (offBuf >= cbBuf)
2996	{
2997	Log((IOMMU_LOG_PFX ": Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
2998	offBuf, cbBuf));
2999	return VINF_SUCCESS;
3000	}
3001
3002	/*
3003	* IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
3004	* head pointer after adding one or more commands to the buffer.
3005	*
3006	* However, we cannot enforce this strictly because it's legal for software to shrink the
3007	* command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
3008	* at 0). Software might even make the queue empty by making head and tail equal which is
3009	* allowed. I don't think we can or should try too hard to prevent software shooting itself
3010	* in the foot here. As long as we make sure the offset value is within the circular buffer
3011	* bounds (which we do by masking bits above) it should be sufficient.
3012	*/
3013	pThis->CmdBufTailPtr.au32[0] = offBuf;
3014
3015	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
3016
3017	LogFlow((IOMMU_LOG_PFX ": Set CmdBufTailPtr to %#RX32\n", offBuf));
3018	return VINF_SUCCESS;
3019	}
3020
3021
3022	/**
3023	* Writes the Event Log Head Pointer Register (32-bit).
3024	*/
3025	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3026	{
3027	RT_NOREF(pDevIns, iReg);
3028
3029	/*
3030	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3031	* In our emulation, we ignore the write entirely.
3032	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3033	*/
3034	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
3035	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3036	Assert(cbBuf <= _512K);
3037	if (offBuf >= cbBuf)
3038	{
3039	Log((IOMMU_LOG_PFX ": Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3040	offBuf, cbBuf));
3041	return VINF_SUCCESS;
3042	}
3043
3044	/* Update the register. */
3045	pThis->EvtLogHeadPtr.au32[0] = offBuf;
3046
3047	LogFlow((IOMMU_LOG_PFX ": Set EvtLogHeadPtr to %#RX32\n", offBuf));
3048	return VINF_SUCCESS;
3049	}
3050
3051
3052	/**
3053	* Writes the Event Log Tail Pointer Register (32-bit).
3054	*/
3055	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3056	{
3057	RT_NOREF(pDevIns, iReg);
3058	NOREF(pThis);
3059
3060	/*
3061	* IOMMU behavior is undefined when software writes this register when the event log is running.
3062	* In our emulation, we ignore the write entirely.
3063	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
3064	*/
3065	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3066	if (Status.n.u1EvtLogRunning)
3067	{
3068	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
3069	return VINF_SUCCESS;
3070	}
3071
3072	/*
3073	* IOMMU behavior is undefined when software writes a value outside the buffer length.
3074	* In our emulation, we ignore the write entirely.
3075	*/
3076	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
3077	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3078	Assert(cbBuf <= _512K);
3079	if (offBuf >= cbBuf)
3080	{
3081	Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
3082	offBuf, cbBuf));
3083	return VINF_SUCCESS;
3084	}
3085
3086	/* Update the register. */
3087	pThis->EvtLogTailPtr.au32[0] = offBuf;
3088
3089	LogFlow((IOMMU_LOG_PFX ": Set EvtLogTailPtr to %#RX32\n", offBuf));
3090	return VINF_SUCCESS;
3091	}
3092
3093
3094	/**
3095	* Writes the Status Register (64-bit).
3096	*/
3097	static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
3098	{
3099	RT_NOREF(pDevIns, iReg);
3100
3101	/* Mask out all unrecognized bits. */
3102	u64Value &= IOMMU_STATUS_VALID_MASK;
3103
3104	/*
3105	* Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
3106	* Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
3107	*/
3108	IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
3109	uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
3110	uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
3111	uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
3112
3113	uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) \| fOldRoBits;
3114
3115	/* Update the register. */
3116	ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
3117	return VINF_SUCCESS;
3118	}
3119
3120
3121	#if 0
3122	/**
3123	* Table 0: Registers-access table.
3124	*/
3125	static const IOMMUREGACC g_aTable0Regs[] =
3126	{
3127
3128	};
3129
3130	/**
3131	* Table 1: Registers-access table.
3132	*/
3133	static const IOMMUREGACC g_aTable1Regs[] =
3134	{
3135	};
3136	#endif
3137
3138
3139	/**
3140	* Writes an IOMMU register (32-bit and 64-bit).
3141	*
3142	* @returns Strict VBox status code.
3143	* @param pDevIns The IOMMU device instance.
3144	* @param off MMIO byte offset to the register.
3145	* @param cb The size of the write access.
3146	* @param uValue The value being written.
3147	*
3148	* @thread EMT.
3149	*/
3150	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
3151	{
3152	Assert(off < IOMMU_MMIO_REGION_SIZE);
3153	Assert(cb == 4 \|\| cb == 8);
3154	Assert(!(off & (cb - 1)));
3155
3156	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3157	switch (off)
3158	{
3159	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
3160	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
3161	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
3162	case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
3163	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
3164	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
3165	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3166
3167	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3168	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
3169	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
3170	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
3171
3172	case IOMMU_MMIO_OFF_GALOG_BAR:
3173	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3174
3175	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
3176	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3177
3178	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3179	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3180	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3181	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3182	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3183	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3184	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
3185
3186	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
3187	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
3188	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3189
3190	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
3191	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3192	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3193	{
3194	VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
3195	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3196	return rcStrict;
3197	uValue >>= 32;
3198	RT_FALL_THRU();
3199	}
3200	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
3201	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3202	{
3203	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
3204	if (cb == 4 \|\| RT_FAILURE(rcStrict))
3205	return rcStrict;
3206	uValue >>= 32;
3207	RT_FALL_THRU();
3208	}
3209	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
3210	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3211
3212	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3213
3214	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
3215	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
3216	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3217
3218	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
3219	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
3220	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
3221	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
3222	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
3223	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
3224	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
3225	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
3226	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
3227	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
3228	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
3229	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3230
3231	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3232
3233	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
3234	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
3235	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
3236	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
3237
3238	case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
3239
3240	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
3241	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
3242
3243	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
3244	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
3245
3246	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
3247	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
3248
3249	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
3250	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
3251
3252	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
3253	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
3254	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
3255
3256	/* Not implemented. */
3257	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3258	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3259	{
3260	Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
3261	(off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3262	return VINF_SUCCESS;
3263	}
3264
3265	/* Unknown. */
3266	default:
3267	{
3268	Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
3269	return VINF_SUCCESS;
3270	}
3271	}
3272	}
3273
3274
3275	/**
3276	* Reads an IOMMU register (64-bit) given its MMIO offset.
3277	*
3278	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
3279	* boundary include the lower half of the subsequent register.
3280	*
3281	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
3282	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
3283	* software will only perform 32-bit reads on those 32-bit registers that are
3284	* aligned on 8-byte boundaries.
3285	*
3286	* @returns Strict VBox status code.
3287	* @param pDevIns The IOMMU device instance.
3288	* @param off The MMIO offset of the register in bytes.
3289	* @param puResult Where to store the value being read.
3290	*
3291	* @thread EMT.
3292	*/
3293	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
3294	{
3295	Assert(off < IOMMU_MMIO_REGION_SIZE);
3296	Assert(!(off & 7) \|\| !(off & 3));
3297
3298	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3299	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3300	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3301
3302	/** @todo IOMMU: fine-grained locking? */
3303	uint64_t uReg;
3304	switch (off)
3305	{
3306	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
3307	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
3308	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
3309	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
3310	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
3311	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
3312	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
3313
3314	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
3315	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
3316	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
3317	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
3318
3319	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
3320	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
3321
3322	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
3323	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
3324
3325	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
3326	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
3327	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
3328	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
3329	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
3330	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
3331	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
3332	{
3333	uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
3334	uint8_t const idxDevTabSeg = offDevTabSeg + 1;
3335	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3336	uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
3337	break;
3338	}
3339
3340	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
3341	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
3342	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
3343
3344	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
3345	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
3346	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
3347	{
3348	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3349	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3350	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
3351	break;
3352	}
3353	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
3354	{
3355	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3356	break;
3357	}
3358	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
3359	{
3360	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3361	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3362	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
3363	break;
3364	}
3365	case IOMMU_MMIO_OFF_MSI_DATA:
3366	{
3367	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3368	break;
3369	}
3370	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
3371	{
3372	/*
3373	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
3374	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
3375	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
3376	* 0 for this register.
3377	*/
3378	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
3379	break;
3380	}
3381
3382	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
3383
3384	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
3385	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
3386	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
3387
3388	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
3389	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
3390	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
3391	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
3392	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
3393	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
3394	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
3395	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
3396	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
3397	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
3398	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
3399	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
3400
3401	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
3402
3403	case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
3404	case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
3405	case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
3406	case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
3407
3408	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
3409
3410	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
3411	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
3412
3413	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
3414	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
3415
3416	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
3417	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
3418
3419	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
3420	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
3421
3422	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
3423	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
3424	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
3425
3426	/* Not implemented. */
3427	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
3428	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
3429	{
3430	Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
3431	uReg = 0;
3432	break;
3433	}
3434
3435	/* Unknown. */
3436	default:
3437	{
3438	Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
3439	uReg = 0;
3440	return VINF_IOM_MMIO_UNUSED_00;
3441	}
3442	}
3443
3444	*puResult = uReg;
3445	return VINF_SUCCESS;
3446	}
3447
3448
3449	/**
3450	* Raises the MSI interrupt for the IOMMU device.
3451	*
3452	* @param pDevIns The IOMMU device instance.
3453	*
3454	* @thread Any.
3455	*/
3456	static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
3457	{
3458	if (iommuAmdIsMsiEnabled(pDevIns))
3459	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
3460	}
3461
3462
3463	/**
3464	* Clears the MSI interrupt for the IOMMU device.
3465	*
3466	* @param pDevIns The IOMMU device instance.
3467	*
3468	* @thread Any.
3469	*/
3470	static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
3471	{
3472	if (iommuAmdIsMsiEnabled(pDevIns))
3473	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
3474	}
3475
3476
3477	/**
3478	* Writes an entry to the event log in memory.
3479	*
3480	* @returns VBox status code.
3481	* @param pDevIns The IOMMU device instance.
3482	* @param pEvent The event to log.
3483	*
3484	* @thread Any.
3485	*/
3486	static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3487	{
3488	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3489
3490	IOMMU_ASSERT_LOCKED(pDevIns);
3491
3492	/* Check if event logging is active and the log has not overflowed. */
3493	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3494	if ( Status.n.u1EvtLogRunning
3495	&& !Status.n.u1EvtOverflow)
3496	{
3497	uint32_t const cbEvt = sizeof(*pEvent);
3498
3499	/* Get the offset we need to write the event to in memory (circular buffer offset). */
3500	uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
3501	Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
3502
3503	/* Ensure we have space in the event log. */
3504	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
3505	uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
3506	if (cEvts + 1 < cMaxEvts)
3507	{
3508	/* Write the event log entry to memory. */
3509	RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3510	RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
3511	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
3512	if (RT_FAILURE(rc))
3513	Log((IOMMU_LOG_PFX ": Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
3514
3515	/* Increment the event log tail pointer. */
3516	uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3517	pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3518
3519	/* Indicate that an event log entry was written. */
3520	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3521
3522	/* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3523	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3524	if (Ctrl.n.u1EvtIntrEn)
3525	iommuAmdRaiseMsiInterrupt(pDevIns);
3526	}
3527	else
3528	{
3529	/* Indicate that the event log has overflowed. */
3530	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3531
3532	/* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3533	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3534	if (Ctrl.n.u1EvtIntrEn)
3535	iommuAmdRaiseMsiInterrupt(pDevIns);
3536	}
3537	}
3538	}
3539
3540
3541	/**
3542	* Sets an event in the hardware error registers.
3543	*
3544	* @param pDevIns The IOMMU device instance.
3545	* @param pEvent The event.
3546	*
3547	* @thread Any.
3548	*/
3549	static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3550	{
3551	IOMMU_ASSERT_LOCKED(pDevIns);
3552
3553	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3554	if (pThis->ExtFeat.n.u1HwErrorSup)
3555	{
3556	if (pThis->HwEvtStatus.n.u1Valid)
3557	pThis->HwEvtStatus.n.u1Overflow = 1;
3558	pThis->HwEvtStatus.n.u1Valid = 1;
3559	pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3560	pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3561	Assert(pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR);
3562	}
3563	}
3564
3565
3566	/**
3567	* Initializes a PAGE_TAB_HARDWARE_ERROR event.
3568	*
3569	* @param uDevId The device ID.
3570	* @param uDomainId The domain ID.
3571	* @param GCPhysPtEntity The system physical address of the page table
3572	* entity.
3573	* @param enmOp The IOMMU operation being performed.
3574	* @param pEvtPageTabHwErr Where to store the initialized event.
3575	*/
3576	static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3577	PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3578	{
3579	memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3580	pEvtPageTabHwErr->n.u16DevId = uDevId;
3581	pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
3582	pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3583	pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3584	pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3585	pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3586	pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3587	pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3588	pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3589	}
3590
3591
3592	/**
3593	* Raises a PAGE_TAB_HARDWARE_ERROR event.
3594	*
3595	* @param pDevIns The IOMMU device instance.
3596	* @param enmOp The IOMMU operation being performed.
3597	* @param pEvtPageTabHwErr The page table hardware error event.
3598	*
3599	* @thread Any.
3600	*/
3601	static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3602	{
3603	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3604	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3605
3606	IOMMU_LOCK_NORET(pDevIns);
3607
3608	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3609	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3610	if (enmOp != IOMMUOP_CMD)
3611	iommuAmdSetPciTargetAbort(pDevIns);
3612
3613	IOMMU_UNLOCK(pDevIns);
3614
3615	Log((IOMMU_LOG_PFX ": Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3616	pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3617	pEvtPageTabHwErr->n.u2Type));
3618	}
3619
3620
3621	/**
3622	* Initializes a COMMAND_HARDWARE_ERROR event.
3623	*
3624	* @param GCPhysAddr The system physical address the IOMMU attempted to access.
3625	* @param pEvtCmdHwErr Where to store the initialized event.
3626	*/
3627	static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3628	{
3629	memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3630	pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3631	pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3632	pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3633	}
3634
3635
3636	/**
3637	* Raises a COMMAND_HARDWARE_ERROR event.
3638	*
3639	* @param pDevIns The IOMMU device instance.
3640	* @param pEvtCmdHwErr The command hardware error event.
3641	*
3642	* @thread Any.
3643	*/
3644	static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3645	{
3646	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3647	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3648	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3649
3650	IOMMU_LOCK_NORET(pDevIns);
3651
3652	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3653	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3654	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3655
3656	IOMMU_UNLOCK(pDevIns);
3657
3658	Log((IOMMU_LOG_PFX ": Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr,
3659	pEvtCmdHwErr->n.u2Type));
3660	}
3661
3662
3663	/**
3664	* Initializes a DEV_TAB_HARDWARE_ERROR event.
3665	*
3666	* @param uDevId The device ID.
3667	* @param GCPhysDte The system physical address of the failed device table
3668	* access.
3669	* @param enmOp The IOMMU operation being performed.
3670	* @param pEvtDevTabHwErr Where to store the initialized event.
3671	*/
3672	static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3673	PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3674	{
3675	memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3676	pEvtDevTabHwErr->n.u16DevId = uDevId;
3677	pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3678	/** @todo IOMMU: Any other transaction type that can set read/write bit? */
3679	pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3680	pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3681	pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3682	pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3683	pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3684	}
3685
3686
3687	/**
3688	* Raises a DEV_TAB_HARDWARE_ERROR event.
3689	*
3690	* @param pDevIns The IOMMU device instance.
3691	* @param enmOp The IOMMU operation being performed.
3692	* @param pEvtDevTabHwErr The device table hardware error event.
3693	*
3694	* @thread Any.
3695	*/
3696	static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3697	{
3698	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3699	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3700
3701	IOMMU_LOCK_NORET(pDevIns);
3702
3703	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
3704	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
3705	if (enmOp != IOMMUOP_CMD)
3706	iommuAmdSetPciTargetAbort(pDevIns);
3707
3708	IOMMU_UNLOCK(pDevIns);
3709
3710	Log((IOMMU_LOG_PFX ": Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n",
3711	pEvtDevTabHwErr->n.u16DevId, pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3712	}
3713
3714
3715	/**
3716	* Initializes an ILLEGAL_COMMAND_ERROR event.
3717	*
3718	* @param GCPhysCmd The system physical address of the failed command
3719	* access.
3720	* @param pEvtIllegalCmd Where to store the initialized event.
3721	*/
3722	static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3723	{
3724	Assert(!(GCPhysCmd & UINT64_C(0xf)));
3725	memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3726	pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3727	pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3728	}
3729
3730
3731	/**
3732	* Raises an ILLEGAL_COMMAND_ERROR event.
3733	*
3734	* @param pDevIns The IOMMU device instance.
3735	* @param pEvtIllegalCmd The illegal command error event.
3736	*/
3737	static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3738	{
3739	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3740	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3741	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3742
3743	IOMMU_LOCK_NORET(pDevIns);
3744
3745	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3746	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3747
3748	IOMMU_UNLOCK(pDevIns);
3749
3750	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3751	}
3752
3753
3754	/**
3755	* Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3756	*
3757	* @param uDevId The device ID.
3758	* @param uIova The I/O virtual address.
3759	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3760	* event was caused by an invalid level encoding in the
3761	* DTE.
3762	* @param enmOp The IOMMU operation being performed.
3763	* @param pEvtIllegalDte Where to store the initialized event.
3764	*/
3765	static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3766	PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3767	{
3768	memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3769	pEvtIllegalDte->n.u16DevId = uDevId;
3770	pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3771	pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3772	pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3773	pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3774	pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3775	pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3776	/** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3777	* IOMMU spec here but not for this field for I/O page fault event. */
3778	Assert(!(uIova & UINT64_C(0x3)));
3779	}
3780
3781
3782	/**
3783	* Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3784	*
3785	* @param pDevIns The IOMMU instance data.
3786	* @param enmOp The IOMMU operation being performed.
3787	* @param pEvtIllegalDte The illegal device table entry event.
3788	* @param enmEvtType The illegal device table entry event type.
3789	*
3790	* @thread Any.
3791	*/
3792	static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3793	EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3794	{
3795	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3796	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3797
3798	IOMMU_LOCK_NORET(pDevIns);
3799
3800	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3801	if (enmOp != IOMMUOP_CMD)
3802	iommuAmdSetPciTargetAbort(pDevIns);
3803
3804	IOMMU_UNLOCK(pDevIns);
3805
3806	Log((IOMMU_LOG_PFX ": Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3807	pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3808	NOREF(enmEvtType);
3809	}
3810
3811
3812	/**
3813	* Initializes an IO_PAGE_FAULT event.
3814	*
3815	* @param uDevId The device ID.
3816	* @param uDomainId The domain ID.
3817	* @param uIova The I/O virtual address being accessed.
3818	* @param fPresent Transaction to a page marked as present (including
3819	* DTE.V=1) or interrupt marked as remapped
3820	* (IRTE.RemapEn=1).
3821	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3822	* the I/O page fault was caused by invalid level
3823	* encoding.
3824	* @param fPermDenied Permission denied for the address being accessed.
3825	* @param enmOp The IOMMU operation being performed.
3826	* @param pEvtIoPageFault Where to store the initialized event.
3827	*/
3828	static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3829	bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3830	{
3831	Assert(!fPermDenied \|\| fPresent);
3832	memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3833	pEvtIoPageFault->n.u16DevId = uDevId;
3834	//pEvtIoPageFault->n.u4PasidHi = 0;
3835	pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
3836	//pEvtIoPageFault->n.u1GuestOrNested = 0;
3837	//pEvtIoPageFault->n.u1NoExecute = 0;
3838	//pEvtIoPageFault->n.u1User = 0;
3839	pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3840	pEvtIoPageFault->n.u1Present = fPresent;
3841	pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3842	pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3843	pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3844	pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3845	pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3846	pEvtIoPageFault->n.u64Addr = uIova;
3847	}
3848
3849
3850	/**
3851	* Raises an IO_PAGE_FAULT event.
3852	*
3853	* @param pDevIns The IOMMU instance data.
3854	* @param pDte The device table entry. Optional, can be NULL
3855	* depending on @a enmOp.
3856	* @param pIrte The interrupt remapping table entry. Optional, can
3857	* be NULL depending on @a enmOp.
3858	* @param enmOp The IOMMU operation being performed.
3859	* @param pEvtIoPageFault The I/O page fault event.
3860	* @param enmEvtType The I/O page fault event type.
3861	*
3862	* @thread Any.
3863	*/
3864	static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3865	PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3866	{
3867	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3868	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3869
3870	IOMMU_LOCK_NORET(pDevIns);
3871
3872	bool fSuppressEvtLogging = false;
3873	if ( enmOp == IOMMUOP_MEM_READ
3874	\|\| enmOp == IOMMUOP_MEM_WRITE)
3875	{
3876	if ( pDte
3877	&& pDte->n.u1Valid)
3878	{
3879	fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
3880	/** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
3881	* suppression. Perhaps will be possible when we complete IOTLB/cache
3882	* handling. */
3883	}
3884	}
3885	else if (enmOp == IOMMUOP_INTR_REQ)
3886	{
3887	if ( pDte
3888	&& pDte->n.u1IntrMapValid)
3889	fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
3890
3891	if ( !fSuppressEvtLogging
3892	&& pIrte)
3893	fSuppressEvtLogging = pIrte->n.u1SuppressPf;
3894	}
3895	/* else: Events are never suppressed for commands. */
3896
3897	switch (enmEvtType)
3898	{
3899	case kIoPageFaultType_PermDenied:
3900	{
3901	/* Cannot be triggered by a command. */
3902	Assert(enmOp != IOMMUOP_CMD);
3903	RT_FALL_THRU();
3904	}
3905	case kIoPageFaultType_DteRsvdPagingMode:
3906	case kIoPageFaultType_PteInvalidPageSize:
3907	case kIoPageFaultType_PteInvalidLvlEncoding:
3908	case kIoPageFaultType_SkippedLevelIovaNotZero:
3909	case kIoPageFaultType_PteRsvdNotZero:
3910	case kIoPageFaultType_PteValidNotSet:
3911	case kIoPageFaultType_DteTranslationDisabled:
3912	case kIoPageFaultType_PasidInvalidRange:
3913	{
3914	/*
3915	* For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3916	* create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
3917	*/
3918	if (enmOp != IOMMUOP_TRANSLATE_REQ)
3919	{
3920	if (!fSuppressEvtLogging)
3921	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3922	if (enmOp != IOMMUOP_CMD)
3923	iommuAmdSetPciTargetAbort(pDevIns);
3924	}
3925	break;
3926	}
3927
3928	case kIoPageFaultType_UserSupervisor:
3929	{
3930	/* Access is blocked and only creates an event log entry. */
3931	if (!fSuppressEvtLogging)
3932	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3933	break;
3934	}
3935
3936	case kIoPageFaultType_IrteAddrInvalid:
3937	case kIoPageFaultType_IrteRsvdNotZero:
3938	case kIoPageFaultType_IrteRemapEn:
3939	case kIoPageFaultType_IrteRsvdIntType:
3940	case kIoPageFaultType_IntrReqAborted:
3941	case kIoPageFaultType_IntrWithPasid:
3942	{
3943	/* Only trigerred by interrupt requests. */
3944	Assert(enmOp == IOMMUOP_INTR_REQ);
3945	if (!fSuppressEvtLogging)
3946	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3947	iommuAmdSetPciTargetAbort(pDevIns);
3948	break;
3949	}
3950
3951	case kIoPageFaultType_SmiFilterMismatch:
3952	{
3953	/* Not supported and probably will never be, assert. */
3954	AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3955	break;
3956	}
3957
3958	case kIoPageFaultType_DevId_Invalid:
3959	{
3960	/* Cannot be triggered by a command. */
3961	Assert(enmOp != IOMMUOP_CMD);
3962	Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3963	if (!fSuppressEvtLogging)
3964	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
3965	if ( enmOp == IOMMUOP_MEM_READ
3966	\|\| enmOp == IOMMUOP_MEM_WRITE)
3967	iommuAmdSetPciTargetAbort(pDevIns);
3968	break;
3969	}
3970	}
3971
3972	IOMMU_UNLOCK(pDevIns);
3973	}
3974
3975
3976	/**
3977	* Returns whether the I/O virtual address is to be excluded from translation and
3978	* permission checks.
3979	*
3980	* @returns @c true if the DVA is excluded, @c false otherwise.
3981	* @param pThis The IOMMU device state.
3982	* @param pDte The device table entry.
3983	* @param uIova The I/O virtual address.
3984	*
3985	* @remarks Ensure the exclusion range is enabled prior to calling this function.
3986	*
3987	* @thread Any.
3988	*/
3989	static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
3990	{
3991	/* Ensure the exclusion range is enabled. */
3992	Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
3993
3994	/* Check if the IOVA falls within the exclusion range. */
3995	uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
3996	uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
3997	if (uIovaExclLast - uIova >= uIovaExclFirst)
3998	{
3999	/* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
4000	if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
4001	\|\| pDte->n.u1AllowExclusion)
4002	return true;
4003	}
4004	return false;
4005	}
4006
4007
4008	/**
4009	* Reads a device table entry from guest memory given the device ID.
4010	*
4011	* @returns VBox status code.
4012	* @param pDevIns The IOMMU device instance.
4013	* @param uDevId The device ID.
4014	* @param enmOp The IOMMU operation being performed.
4015	* @param pDte Where to store the device table entry.
4016	*
4017	* @thread Any.
4018	*/
4019	static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
4020	{
4021	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4022	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4023
4024	uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
4025	Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
4026
4027	uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
4028	Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
4029
4030	RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
4031	uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
4032	RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
4033
4034	Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
4035	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
4036	if (RT_FAILURE(rc))
4037	{
4038	Log((IOMMU_LOG_PFX ": Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
4039
4040	EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
4041	iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
4042	iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
4043	return VERR_IOMMU_IPE_1;
4044	}
4045
4046
4047	return rc;
4048	}
4049
4050
4051	/**
4052	* Walks the I/O page table to translate the I/O virtual address to a system
4053	* physical address.
4054	*
4055	* @returns VBox status code.
4056	* @param pDevIns The IOMMU device instance.
4057	* @param uIova The I/O virtual address to translate. Must be 4K aligned.
4058	* @param uDevId The device ID.
4059	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4060	* permissions for the access being made.
4061	* @param pDte The device table entry.
4062	* @param enmOp The IOMMU operation being performed.
4063	* @param pWalkResult Where to store the results of the I/O page walk. This is
4064	* only updated when VINF_SUCCESS is returned.
4065	*
4066	* @thread Any.
4067	*/
4068	static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
4069	IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
4070	{
4071	Assert(pDte->n.u1Valid);
4072	Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
4073
4074	/* If the translation is not valid, raise an I/O page fault. */
4075	if (pDte->n.u1TranslationValid)
4076	{ /* likely */ }
4077	else
4078	{
4079	/** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
4080	* doesn't explicitly say whether an I/O page fault is raised. From other
4081	* places in the spec. it seems early page walk terminations (starting with
4082	* the DTE) return the state computed so far and raises an I/O page fault. So
4083	* returning an invalid translation rather than skipping translation. */
4084	Log((IOMMU_LOG_PFX ": Translation valid bit not set -> IOPF"));
4085	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4086	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4087	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4088	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4089	kIoPageFaultType_DteTranslationDisabled);
4090	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4091	}
4092
4093	/* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
4094	uint8_t const uMaxLevel = pDte->n.u3Mode;
4095	if (uMaxLevel != 0)
4096	{ /* likely */ }
4097	else
4098	{
4099	uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4100	if ((fAccess & fDtePerm) != fAccess)
4101	{
4102	Log((IOMMU_LOG_PFX ": Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
4103	return VERR_IOMMU_ADDR_ACCESS_DENIED;
4104	}
4105	pWalkResult->GCPhysSpa = uIova;
4106	pWalkResult->cShift = 0;
4107	pWalkResult->fIoPerm = fDtePerm;
4108	return VINF_SUCCESS;
4109	}
4110
4111	/* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
4112	if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4113	{ /* likely */ }
4114	else
4115	{
4116	/** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
4117	* raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
4118	* I'm just going with I/O page fault. */
4119	Log((IOMMU_LOG_PFX ": Invalid root page table level %#x -> IOPF", uMaxLevel));
4120	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4121	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4122	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4123	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4124	kIoPageFaultType_PteInvalidLvlEncoding);
4125	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4126	}
4127
4128	/* Check permissions bits of the root page table. */
4129	uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4130	if ((fAccess & fRootPtePerm) == fAccess)
4131	{ /* likely */ }
4132	else
4133	{
4134	Log((IOMMU_LOG_PFX ": Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF", fAccess, fRootPtePerm));
4135	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4136	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4137	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4138	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4139	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4140	}
4141
4142	/** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
4143	* function called iommuAmdWalkIoPageDirectory() and call it for multi-page
4144	* accesses from the 2nd page. We can avoid re-checking the DTE root-page
4145	* table entry every time. Not sure if it's worth optimizing that case now
4146	* or if at all. */
4147
4148	/* The virtual address bits indexing table. */
4149	static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
4150	static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
4151	UINT64_C(0x00000000001ff000),
4152	UINT64_C(0x000000003fe00000),
4153	UINT64_C(0x0000007fc0000000),
4154	UINT64_C(0x0000ff8000000000),
4155	UINT64_C(0x01ff000000000000),
4156	UINT64_C(0xfe00000000000000),
4157	UINT64_C(0x0000000000000000) };
4158	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
4159	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
4160
4161	/* Traverse the I/O page table starting with the page directory in the DTE. */
4162	IOPTENTITY_T PtEntity;
4163	PtEntity.u64 = pDte->au64[0];
4164	for (;;)
4165	{
4166	/* Figure out the system physical address of the page table at the current level. */
4167	uint8_t const uLevel = PtEntity.n.u3NextLevel;
4168
4169	/* Read the page table entity at the current level. */
4170	{
4171	Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
4172	Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4173	uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
4174	uint64_t const offPte = idxPte << 3;
4175	RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
4176	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
4177	if (RT_FAILURE(rc))
4178	{
4179	Log((IOMMU_LOG_PFX ": Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
4180	EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
4181	iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
4182	iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
4183	return VERR_IOMMU_IPE_2;
4184	}
4185	}
4186
4187	/* Check present bit. */
4188	if (PtEntity.n.u1Present)
4189	{ /* likely */ }
4190	else
4191	{
4192	Log((IOMMU_LOG_PFX ": Page table entry not present -> IOPF"));
4193	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4194	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
4195	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4196	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4197	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4198	}
4199
4200	/* Check permission bits. */
4201	uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
4202	if ((fAccess & fPtePerm) == fAccess)
4203	{ /* likely */ }
4204	else
4205	{
4206	Log((IOMMU_LOG_PFX ": Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF", fAccess, fPtePerm));
4207	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4208	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4209	true /* fPermDenied */, enmOp, &EvtIoPageFault);
4210	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
4211	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4212	}
4213
4214	/* If this is a PTE, we're at the final level and we're done. */
4215	uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
4216	if (uNextLevel == 0)
4217	{
4218	/* The page size of the translation is the default (4K). */
4219	pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4220	pWalkResult->cShift = X86_PAGE_4K_SHIFT;
4221	pWalkResult->fIoPerm = fPtePerm;
4222	return VINF_SUCCESS;
4223	}
4224	if (uNextLevel == 7)
4225	{
4226	/* The default page size of the translation is overridden. */
4227	RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
4228	uint8_t cShift = X86_PAGE_4K_SHIFT;
4229	while (GCPhysPte & RT_BIT_64(cShift++))
4230	;
4231
4232	/* The page size must be larger than the default size and lower than the default size of the higher level. */
4233	Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
4234	if ( cShift > s_acIovaLevelShifts[uLevel]
4235	&& cShift < s_acIovaLevelShifts[uLevel + 1])
4236	{
4237	pWalkResult->GCPhysSpa = GCPhysPte;
4238	pWalkResult->cShift = cShift;
4239	pWalkResult->fIoPerm = fPtePerm;
4240	return VINF_SUCCESS;
4241	}
4242
4243	Log((IOMMU_LOG_PFX ": Page size invalid cShift=%#x -> IOPF", cShift));
4244	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4245	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4246	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4247	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4248	kIoPageFaultType_PteInvalidPageSize);
4249	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4250	}
4251
4252	/* Validate the next level encoding of the PDE. */
4253	#if IOMMU_MAX_HOST_PT_LEVEL < 6
4254	if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
4255	{ /* likely */ }
4256	else
4257	{
4258	Log((IOMMU_LOG_PFX ": Next level of PDE invalid uNextLevel=%#x -> IOPF", uNextLevel));
4259	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4260	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4261	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4262	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4263	kIoPageFaultType_PteInvalidLvlEncoding);
4264	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4265	}
4266	#else
4267	Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
4268	#endif
4269
4270	/* Validate level transition. */
4271	if (uNextLevel < uLevel)
4272	{ /* likely */ }
4273	else
4274	{
4275	Log((IOMMU_LOG_PFX ": Next level (%#x) must be less than the current level (%#x) -> IOPF", uNextLevel, uLevel));
4276	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4277	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4278	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4279	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4280	kIoPageFaultType_PteInvalidLvlEncoding);
4281	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4282	}
4283
4284	/* Ensure IOVA bits of skipped levels are zero. */
4285	Assert(uLevel > 0);
4286	uint64_t uIovaSkipMask = 0;
4287	for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
4288	uIovaSkipMask \|= s_auIovaLevelMasks[idxLevel];
4289	if (!(uIova & uIovaSkipMask))
4290	{ /* likely */ }
4291	else
4292	{
4293	Log((IOMMU_LOG_PFX ": IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF", uIova, uIovaSkipMask));
4294	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4295	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
4296	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4297	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4298	kIoPageFaultType_SkippedLevelIovaNotZero);
4299	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4300	}
4301
4302	/* Continue with traversing the page directory at this level. */
4303	}
4304
4305	/* Shouldn't really get here. */
4306	return VERR_IOMMU_IPE_3;
4307	}
4308
4309
4310	/**
4311	* Looks up an I/O virtual address from the device table.
4312	*
4313	* @returns VBox status code.
4314	* @param pDevIns The IOMMU instance data.
4315	* @param uDevId The device ID.
4316	* @param uIova The I/O virtual address to lookup.
4317	* @param cbAccess The size of the access.
4318	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
4319	* permissions for the access being made.
4320	* @param enmOp The IOMMU operation being performed.
4321	* @param pGCPhysSpa Where to store the translated system physical address. Only
4322	* valid when translation succeeds and VINF_SUCCESS is
4323	* returned!
4324	*
4325	* @thread Any.
4326	*/
4327	static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
4328	IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
4329	{
4330	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4331
4332	/* Read the device table entry from memory. */
4333	DTE_T Dte;
4334	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4335	if (RT_SUCCESS(rc))
4336	{
4337	/* If the DTE is not valid, addresses are forwarded without translation */
4338	if (Dte.n.u1Valid)
4339	{ /* likely */ }
4340	else
4341	{
4342	/** @todo IOMMU: Add to IOLTB cache. */
4343	*pGCPhysSpa = uIova;
4344	return VINF_SUCCESS;
4345	}
4346
4347	/* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4348	uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4349	uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4350	if (RT_LIKELY( !fRsvd0
4351	&& !fRsvd1))
4352	{ /* likely */ }
4353	else
4354	{
4355	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4356	EVT_ILLEGAL_DTE_T Event;
4357	iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4358	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4359	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4360	}
4361
4362	/* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
4363	if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
4364	\|\| !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
4365	{ /* likely */ }
4366	else
4367	{
4368	/** @todo IOMMU: Add to IOLTB cache. */
4369	*pGCPhysSpa = uIova;
4370	return VINF_SUCCESS;
4371	}
4372
4373	/** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
4374	* below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
4375
4376	uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
4377	uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
4378	uint64_t cbRemaining = cbAccess;
4379	for (;;)
4380	{
4381	/* Walk the I/O page tables to translate the IOVA and check permission for the access. */
4382	IOWALKRESULT WalkResult;
4383	rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
4384	if (RT_SUCCESS(rc))
4385	{
4386	/** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
4387
4388	/* Store the translated base address before continuing to check permissions for any more pages. */
4389	if (cbRemaining == cbAccess)
4390	{
4391	RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
4392	*pGCPhysSpa = WalkResult.GCPhysSpa \| offSpa;
4393	}
4394
4395	uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
4396	if (cbRemaining > cbPhysPage - offIova)
4397	{
4398	cbRemaining -= (cbPhysPage - offIova);
4399	uBaseIova += cbPhysPage;
4400	offIova = 0;
4401	}
4402	else
4403	break;
4404	}
4405	else
4406	{
4407	Log((IOMMU_LOG_PFX ": I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
4408	uBaseIova, fAccess, rc));
4409	*pGCPhysSpa = NIL_RTGCPHYS;
4410	return rc;
4411	}
4412	}
4413
4414	return rc;
4415	}
4416
4417	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4418	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4419	}
4420
4421
4422	/**
4423	* Memory read request from a device.
4424	*
4425	* @returns VBox status code.
4426	* @param pDevIns The IOMMU device instance.
4427	* @param uDevId The device ID (bus, device, function).
4428	* @param uIova The I/O virtual address being read.
4429	* @param cbRead The number of bytes being read.
4430	* @param pGCPhysSpa Where to store the translated system physical address.
4431	*
4432	* @thread Any.
4433	*/
4434	static int iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead, PRTGCPHYS pGCPhysSpa)
4435	{
4436	/* Validate. */
4437	Assert(pDevIns);
4438	Assert(pGCPhysSpa);
4439	Assert(cbRead > 0);
4440
4441	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4442
4443	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4444	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4445	if (Ctrl.n.u1IommuEn)
4446	{
4447	/** @todo IOMMU: IOTLB cache lookup. */
4448
4449	/* Lookup the IOVA from the device table. */
4450	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
4451	}
4452
4453	*pGCPhysSpa = uIova;
4454	return VINF_SUCCESS;
4455	}
4456
4457
4458	/**
4459	* Memory write request from a device.
4460	*
4461	* @returns VBox status code.
4462	* @param pDevIns The IOMMU device instance.
4463	* @param uDevId The device ID (bus, device, function).
4464	* @param uIova The I/O virtual address being written.
4465	* @param cbWrite The number of bytes being written.
4466	* @param pGCPhysSpa Where to store the translated physical address.
4467	*
4468	* @thread Any.
4469	*/
4470	static int iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite, PRTGCPHYS pGCPhysSpa)
4471	{
4472	/* Validate. */
4473	Assert(pDevIns);
4474	Assert(pGCPhysSpa);
4475	Assert(cbWrite > 0);
4476
4477	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4478
4479	/* Addresses are forwarded without translation when the IOMMU is disabled. */
4480	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4481	if (Ctrl.n.u1IommuEn)
4482	{
4483	/** @todo IOMMU: IOTLB cache lookup. */
4484
4485	/* Lookup the IOVA from the device table. */
4486	return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
4487	}
4488
4489	*pGCPhysSpa = uIova;
4490	return VINF_SUCCESS;
4491	}
4492
4493
4494	/**
4495	* Reads an interrupt remapping table entry from guest memory given its DTE.
4496	*
4497	* @returns VBox status code.
4498	* @param pDevIns The IOMMU device instance.
4499	* @param uDevId The device ID.
4500	* @param pDte The device table entry.
4501	* @param GCPhysIn The source MSI address.
4502	* @param uDataIn The source MSI data.
4503	* @param enmOp The IOMMU operation being performed.
4504	* @param pIrte Where to store the interrupt remapping table entry.
4505	*
4506	* @thread Any.
4507	*/
4508	static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4509	IOMMUOP enmOp, PIRTE_T pIrte)
4510	{
4511	RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4512	uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) << IOMMU_IRTE_SIZE_SHIFT;
4513	RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4514
4515	/* Ensure the IRTE offset is within the specified table size. */
4516	Assert(pDte->n.u4IntrTableLength < 12);
4517	if (offIrte + sizeof(IRTE_T) <= (1U << pDte->n.u4IntrTableLength) << IOMMU_IRTE_SIZE_SHIFT)
4518	{ /* likely */ }
4519	else
4520	{
4521	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4522	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent /, false / fRsvdNotZero */,
4523	false /* fPermDenied */, enmOp, &EvtIoPageFault);
4524	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4525	kIoPageFaultType_IrteAddrInvalid);
4526	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4527	}
4528
4529	/* Read the IRTE from memory. */
4530	Assert(!(GCPhysIrte & 3));
4531	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4532	if (RT_SUCCESS(rc))
4533	return VINF_SUCCESS;
4534
4535	/** @todo The IOMMU spec. does not tell what kind of error is reported in this
4536	* situation. Is it an I/O page fault or a device table hardware error?
4537	* There's no interrupt table hardware error event, but it's unclear what
4538	* we should do here. */
4539	Log((IOMMU_LOG_PFX ": Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4540	return VERR_IOMMU_IPE_4;
4541	}
4542
4543
4544	/**
4545	* Remap the interrupt using the interrupt remapping table.
4546	*
4547	* @returns VBox status code.
4548	* @param pDevIns The IOMMU instance data.
4549	* @param uDevId The device ID.
4550	* @param pDte The device table entry.
4551	* @param enmOp The IOMMU operation being performed.
4552	* @param pMsiIn The source MSI.
4553	* @param pMsiOut Where to store the remapped MSI.
4554	*
4555	* @thread Any.
4556	*/
4557	static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4558	PMSIMSG pMsiOut)
4559	{
4560	Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4561
4562	IRTE_T Irte;
4563	int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
4564	if (RT_SUCCESS(rc))
4565	{
4566	if (Irte.n.u1RemapEnable)
4567	{
4568	if (!Irte.n.u1GuestMode)
4569	{
4570	if (Irte.n.u3IntrType < VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4571	{
4572	/* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
4573	pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
4574	pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
4575	pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
4576
4577	/* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
4578	pMsiOut->Data.u32 = pMsiIn->Data.u32;
4579	pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
4580	pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
4581
4582	return VINF_SUCCESS;
4583	}
4584
4585	Log((IOMMU_LOG_PFX ": Interrupt type (%#x) invalid -> IOPF", Irte.n.u3IntrType));
4586	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4587	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4588	true /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
4589	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
4590	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4591	}
4592
4593	Log((IOMMU_LOG_PFX ": Guest mode not supported -> IOPF"));
4594	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4595	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4596	true /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
4597	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4598	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4599	}
4600
4601	Log((IOMMU_LOG_PFX ": Remapping disabled -> IOPF"));
4602	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4603	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4604	false /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
4605	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4606	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4607	}
4608
4609	return rc;
4610	}
4611
4612
4613	/**
4614	* Looks up an MSI interrupt from the interrupt remapping table.
4615	*
4616	* @returns VBox status code.
4617	* @param pDevIns The IOMMU instance data.
4618	* @param uDevId The device ID.
4619	* @param enmOp The IOMMU operation being performed.
4620	* @param pMsiIn The source MSI.
4621	* @param pMsiOut Where to store the remapped MSI.
4622	*
4623	* @thread Any.
4624	*/
4625	static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4626	{
4627	/* Read the device table entry from memory. */
4628	DTE_T Dte;
4629	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
4630	if (RT_SUCCESS(rc))
4631	{
4632	/* If the DTE is not valid, all interrupts are forwarded without remapping. */
4633	if (Dte.n.u1IntrMapValid)
4634	{
4635	/* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4636	uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4637	uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4638	if (RT_LIKELY( !fRsvd0
4639	&& !fRsvd1))
4640	{ /* likely */ }
4641	else
4642	{
4643	Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
4644	fRsvd1));
4645	EVT_ILLEGAL_DTE_T Event;
4646	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4647	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4648	return VERR_IOMMU_INTR_REMAP_FAILED;
4649	}
4650
4651	/*
4652	* LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4653	* that's connected through HyperTransport it might be possible; but for us, it
4654	* doesn't seem we need to specially handle these pins.
4655	*/
4656
4657	/*
4658	* Validate the MSI source address.
4659	*
4660	* 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4661	* CPU is concerned, the MSI region is fixed and we must ensure no other device
4662	* claims the region as I/O space.
4663	*
4664	* See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4665	* See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4666	* See Intel spec. 10.11.1 "Message Address Register Format".
4667	*/
4668	if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4669	{
4670	/*
4671	* The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4672	* See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4673	*/
4674	uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4675	bool fPassThru = false;
4676	switch (u8DeliveryMode)
4677	{
4678	case VBOX_MSI_DELIVERY_MODE_FIXED:
4679	case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4680	{
4681	uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4682	if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4683	{
4684	Log((IOMMU_LOG_PFX ": IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
4685	iommuAmdSetPciTargetAbort(pDevIns);
4686	return VERR_IOMMU_INTR_REMAP_DENIED;
4687	}
4688
4689	if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4690	{
4691	fPassThru = true;
4692	break;
4693	}
4694
4695	if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4696	{
4697	/* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4698	uint32_t const uIntTabLen = Dte.n.u4IntrTableLength;
4699	if (Dte.n.u4IntrTableLength < 12)
4700	{
4701	/*
4702	* We don't support guest interrupt remapping yet. When we do, we'll need to
4703	* check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4704	* in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4705	* already reads the control register, add that as a parameter when we eventually
4706	* support guest interrupt remapping. For now, just assert.
4707	*/
4708	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4709	Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4710	NOREF(pThis);
4711
4712	return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
4713	}
4714
4715	Log((IOMMU_LOG_PFX ": Invalid interrupt table length %#x -> Illegal DTE\n", uIntTabLen));
4716	EVT_ILLEGAL_DTE_T Event;
4717	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4718	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4719	return VERR_IOMMU_INTR_REMAP_FAILED;
4720	}
4721
4722	/* Paranoia. */
4723	Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
4724
4725	Log((IOMMU_LOG_PFX ":IntCtl mode invalid %#x -> Illegal DTE", uIntrCtrl));
4726	EVT_ILLEGAL_DTE_T Event;
4727	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4728	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4729	return VERR_IOMMU_INTR_REMAP_FAILED;
4730	}
4731
4732	/* SMIs are passed through unmapped. We don't implement SMI filters. */
4733	case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4734	case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4735	case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4736	case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4737	default:
4738	{
4739	Log((IOMMU_LOG_PFX ":MSI data delivery mode invalid %#x -> Target abort", u8DeliveryMode));
4740	iommuAmdSetPciTargetAbort(pDevIns);
4741	return VERR_IOMMU_INTR_REMAP_FAILED;
4742	}
4743	}
4744
4745	if (fPassThru)
4746	{
4747	pMsiOut = pMsiIn;
4748	return VINF_SUCCESS;
4749	}
4750
4751	iommuAmdSetPciTargetAbort(pDevIns);
4752	return VERR_IOMMU_INTR_REMAP_DENIED;
4753	}
4754	else
4755	{
4756	Log((IOMMU_LOG_PFX ":MSI address region invalid %#RX64.", pMsiIn->Addr.u64));
4757	return VERR_IOMMU_INTR_REMAP_FAILED;
4758	}
4759	}
4760	else
4761	{
4762	/** @todo IOMMU: Add to interrupt remapping cache. */
4763	pMsiOut = pMsiIn;
4764	return VINF_SUCCESS;
4765	}
4766	}
4767
4768	Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4769	return VERR_IOMMU_INTR_REMAP_FAILED;
4770	}
4771
4772
4773	/**
4774	* Interrupt remap request from a device.
4775	*
4776	* @returns VBox status code.
4777	* @param pDevIns The IOMMU device instance.
4778	* @param uDevId The device ID (bus, device, function).
4779	* @param pMsiIn The source MSI.
4780	* @param pMsiOut Where to store the remapped MSI.
4781	*/
4782	static int iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4783	{
4784	/* Validate. */
4785	Assert(pDevIns);
4786	Assert(pMsiIn);
4787	Assert(pMsiOut);
4788
4789	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4790
4791	/* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4792	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4793	if (Ctrl.n.u1IommuEn)
4794	{
4795	/** @todo Cache? */
4796
4797	return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4798	}
4799
4800	pMsiOut = pMsiIn;
4801	return VINF_SUCCESS;
4802	}
4803
4804
4805	/**
4806	* @callback_method_impl{FNIOMMMIONEWWRITE}
4807	*/
4808	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
4809	{
4810	NOREF(pvUser);
4811	Assert(cb == 4 \|\| cb == 8);
4812	Assert(!(off & (cb - 1)));
4813
4814	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
4815	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
4816	}
4817
4818
4819	/**
4820	* @callback_method_impl{FNIOMMMIONEWREAD}
4821	*/
4822	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
4823	{
4824	NOREF(pvUser);
4825	Assert(cb == 4 \|\| cb == 8);
4826	Assert(!(off & (cb - 1)));
4827
4828	uint64_t uResult;
4829	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
4830	if (cb == 8)
4831	(uint64_t )pv = uResult;
4832	else
4833	(uint32_t )pv = (uint32_t)uResult;
4834
4835	return rcStrict;
4836	}
4837
4838	# ifdef IN_RING3
4839
4840	/**
4841	* Processes an IOMMU command.
4842	*
4843	* @returns VBox status code.
4844	* @param pDevIns The IOMMU device instance.
4845	* @param pCmd The command to process.
4846	* @param GCPhysCmd The system physical address of the command.
4847	* @param pEvtError Where to store the error event in case of failures.
4848	*
4849	* @thread Command thread.
4850	*/
4851	static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4852	{
4853	IOMMU_ASSERT_NOT_LOCKED(pDevIns);
4854
4855	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4856	uint8_t const bCmd = pCmd->n.u4Opcode;
4857	switch (bCmd)
4858	{
4859	case IOMMU_CMD_COMPLETION_WAIT:
4860	{
4861	PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4862	AssertCompile(sizeof(pCmdComWait) == sizeof(pCmd));
4863
4864	/* Validate reserved bits in the command. */
4865	if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4866	{
4867	/* If Completion Store is requested, write the StoreData to the specified address.*/
4868	if (pCmdComWait->n.u1Store)
4869	{
4870	RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4871	uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4872	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4873	if (RT_FAILURE(rc))
4874	{
4875	Log((IOMMU_LOG_PFX ": Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4876	GCPhysStore, rc));
4877	iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4878	return VERR_IOMMU_CMD_HW_ERROR;
4879	}
4880	}
4881
4882	IOMMU_LOCK(pDevIns);
4883
4884	/* Indicate that this command has completed. */
4885	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4886
4887	/* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4888	if (pCmdComWait->n.u1Interrupt)
4889	{
4890	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4891	if (Ctrl.n.u1CompWaitIntrEn)
4892	iommuAmdRaiseMsiInterrupt(pDevIns);
4893	}
4894
4895	IOMMU_UNLOCK(pDevIns);
4896	return VINF_SUCCESS;
4897	}
4898	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4899	return VERR_IOMMU_CMD_INVALID_FORMAT;
4900	}
4901
4902	case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4903	{
4904	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4905	* then. */
4906	return VINF_SUCCESS;
4907	}
4908
4909	case IOMMU_CMD_INV_IOMMU_PAGES:
4910	{
4911	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4912	* then. */
4913	return VINF_SUCCESS;
4914	}
4915
4916	case IOMMU_CMD_INV_IOTLB_PAGES:
4917	{
4918	uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4919	if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4920	{
4921	/** @todo IOMMU: Implement remote IOTLB invalidation. */
4922	return VERR_NOT_IMPLEMENTED;
4923	}
4924	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4925	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4926	}
4927
4928	case IOMMU_CMD_INV_INTR_TABLE:
4929	{
4930	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4931	* then. */
4932	return VINF_SUCCESS;
4933	}
4934
4935	case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
4936	{
4937	if (pThis->ExtFeat.n.u1PrefetchSup)
4938	{
4939	/** @todo IOMMU: Implement prefetch. Pretend success until then. */
4940	return VINF_SUCCESS;
4941	}
4942	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4943	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4944	}
4945
4946	case IOMMU_CMD_COMPLETE_PPR_REQ:
4947	{
4948	/* We don't support PPR requests yet. */
4949	Assert(!pThis->ExtFeat.n.u1PprSup);
4950	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4951	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4952	}
4953
4954	case IOMMU_CMD_INV_IOMMU_ALL:
4955	{
4956	if (pThis->ExtFeat.n.u1InvAllSup)
4957	{
4958	/** @todo IOMMU: Invalidate all. Pretend success until then. */
4959	return VINF_SUCCESS;
4960	}
4961	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4962	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4963	}
4964	}
4965
4966	Log((IOMMU_LOG_PFX ": Cmd(%#x): Unrecognized\n", bCmd));
4967	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4968	return VERR_IOMMU_CMD_NOT_SUPPORTED;
4969	}
4970
4971
4972	/**
4973	* The IOMMU command thread.
4974	*
4975	* @returns VBox status code.
4976	* @param pDevIns The IOMMU device instance.
4977	* @param pThread The command thread.
4978	*/
4979	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4980	{
4981	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4982
4983	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4984	return VINF_SUCCESS;
4985
4986	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4987	{
4988	/*
4989	* Sleep perpetually until we are woken up to process commands.
4990	*/
4991	{
4992	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
4993	bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
4994	if (!fSignaled)
4995	{
4996	Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
4997	int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
4998	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4999	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5000	break;
5001	LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
5002	ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5003	}
5004	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
5005	}
5006
5007	/*
5008	* Fetch and process IOMMU commands.
5009	*/
5010	/** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
5011	* at a time) and is expensive due to calls to PGM for fetching guest memory.
5012	* We could optimize by fetching a bunch of commands at a time reducing
5013	* number of calls to PGM. In the longer run we could lock the memory and
5014	* mappings and accessing them directly. */
5015	IOMMU_LOCK(pDevIns);
5016
5017	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
5018	if (Status.n.u1CmdBufRunning)
5019	{
5020	/* Get the offset we need to read the command from memory (circular buffer offset). */
5021	uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5022	uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5023	Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5024	Assert(offHead < cbCmdBuf);
5025	while (offHead != pThis->CmdBufTailPtr.n.off)
5026	{
5027	/* Read the command from memory. */
5028	CMD_GENERIC_T Cmd;
5029	RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
5030	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
5031	if (RT_SUCCESS(rc))
5032	{
5033	/* Increment the command buffer head pointer. */
5034	offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5035	pThis->CmdBufHeadPtr.n.off = offHead;
5036
5037	/* Process the fetched command. */
5038	EVT_GENERIC_T EvtError;
5039	IOMMU_UNLOCK(pDevIns);
5040	rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
5041	IOMMU_LOCK(pDevIns);
5042	if (RT_FAILURE(rc))
5043	{
5044	if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5045	\|\| rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5046	{
5047	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5048	iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5049	}
5050	else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5051	{
5052	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5053	iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5054	}
5055	break;
5056	}
5057	}
5058	else
5059	{
5060	EVT_CMD_HW_ERR_T EvtCmdHwErr;
5061	iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
5062	iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
5063	break;
5064	}
5065	}
5066	}
5067
5068	IOMMU_UNLOCK(pDevIns);
5069	}
5070
5071	LogFlow((IOMMU_LOG_PFX ": Command thread terminating\n"));
5072	return VINF_SUCCESS;
5073	}
5074
5075
5076	/**
5077	* Wakes up the command thread so it can respond to a state change.
5078	*
5079	* @returns VBox status code.
5080	* @param pDevIns The IOMMU device instance.
5081	* @param pThread The command thread.
5082	*/
5083	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5084	{
5085	RT_NOREF(pThread);
5086
5087	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5088	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5089	}
5090
5091
5092	/**
5093	* @callback_method_impl{FNPCICONFIGREAD}
5094	*/
5095	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5096	unsigned cb, uint32_t *pu32Value)
5097	{
5098	/** @todo IOMMU: PCI config read stat counter. */
5099	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5100	Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
5101	VBOXSTRICTRC_VAL(rcStrict)));
5102	return rcStrict;
5103	}
5104
5105
5106	/**
5107	* @callback_method_impl{FNPCICONFIGWRITE}
5108	*/
5109	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5110	unsigned cb, uint32_t u32Value)
5111	{
5112	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5113
5114	/*
5115	* Discard writes to read-only registers that are specific to the IOMMU.
5116	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5117	* See PCI spec. 6.1. "Configuration Space Organization".
5118	*/
5119	switch (uAddress)
5120	{
5121	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5122	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5123	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5124	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5125	{
5126	Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5127	return VINF_SUCCESS;
5128	}
5129	}
5130
5131	IOMMU_LOCK(pDevIns);
5132
5133	VBOXSTRICTRC rcStrict;
5134	switch (uAddress)
5135	{
5136	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5137	{
5138	if (pThis->IommuBar.n.u1Enable)
5139	{
5140	rcStrict = VINF_SUCCESS;
5141	Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5142	break;
5143	}
5144
5145	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5146	if (pThis->IommuBar.n.u1Enable)
5147	{
5148	Assert(pThis->hMmio == NIL_IOMMMIOHANDLE);
5149	Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5150	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5151	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5152	if (RT_FAILURE(rcStrict))
5153	Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
5154	}
5155	break;
5156	}
5157
5158	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5159	{
5160	if (!pThis->IommuBar.n.u1Enable)
5161	pThis->IommuBar.au32[1] = u32Value;
5162	else
5163	{
5164	rcStrict = VINF_SUCCESS;
5165	Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5166	}
5167	break;
5168	}
5169
5170	case IOMMU_PCI_OFF_MSI_CAP_HDR:
5171	{
5172	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5173	RT_FALL_THRU();
5174	}
5175	default:
5176	{
5177	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5178	break;
5179	}
5180	}
5181
5182	IOMMU_UNLOCK(pDevIns);
5183
5184	Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
5185	return rcStrict;
5186	}
5187
5188
5189	/**
5190	* @callback_method_impl{FNDBGFHANDLERDEV}
5191	*/
5192	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5193	{
5194	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5195	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5196	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5197
5198	LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
5199	bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
5200
5201	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5202	/* Device Table Base Addresses (all segments). */
5203	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5204	{
5205	DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5206	pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
5207	if (fVerbose)
5208	{
5209	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5210	IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
5211	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5212	}
5213	}
5214	/* Command Buffer Base Address Register. */
5215	{
5216	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5217	uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5218	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5219	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5220	pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
5221	if (fVerbose)
5222	{
5223	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5224	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5225	cEntries, cbBuffer);
5226	}
5227	}
5228	/* Event Log Base Address Register. */
5229	{
5230	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5231	uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5232	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5233	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5234	pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
5235	if (fVerbose)
5236	{
5237	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5238	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5239	cEntries, cbBuffer);
5240	}
5241	}
5242	/* IOMMU Control Register. */
5243	{
5244	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5245	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5246	if (fVerbose)
5247	{
5248	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5249	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5250	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5251	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5252	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5253	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5254	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5255	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5256	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5257	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5258	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5259	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5260	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5261	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5262	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5263	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5264	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5265	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5266	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5267	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5268	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5269	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5270	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5271	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5272	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5273	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5274	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5275	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5276	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5277	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5278	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5279	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5280	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5281	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5282	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5283	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5284	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5285	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5286	}
5287	}
5288	/* Exclusion Base Address Register. */
5289	{
5290	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5291	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5292	if (fVerbose)
5293	{
5294	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5295	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5296	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5297	ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5298	}
5299	}
5300	/* Exclusion Range Limit Register. */
5301	{
5302	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5303	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5304	if (fVerbose)
5305	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
5306	}
5307	/* Extended Feature Register. */
5308	{
5309	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5310	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5311	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5312	if (fVerbose)
5313	{
5314	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5315	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5316	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5317	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5318	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5319	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5320	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5321	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5322	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5323	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5324	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5325	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5326	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5327	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5328	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5329	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5330	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5331	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5332	pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5333	g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5334	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5335	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5336	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5337	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5338	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5339	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5340	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5341	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5342	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5343	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5344	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5345	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5346	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5347	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5348	}
5349	}
5350	/* PPR Log Base Address Register. */
5351	{
5352	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5353	uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5354	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5355	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5356	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5357	if (fVerbose)
5358	{
5359	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5360	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5361	cEntries, cbBuffer);
5362	}
5363	}
5364	/* Hardware Event (Hi) Register. */
5365	{
5366	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5367	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5368	if (fVerbose)
5369	{
5370	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5371	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5372	}
5373	}
5374	/* Hardware Event (Lo) Register. */
5375	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5376	/* Hardware Event Status. */
5377	{
5378	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5379	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5380	if (fVerbose)
5381	{
5382	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5383	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5384	}
5385	}
5386	/* Guest Virtual-APIC Log Base Address Register. */
5387	{
5388	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5389	uint8_t const uEncodedLen = GALogBar.n.u4Len;
5390	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5391	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5392	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5393	if (fVerbose)
5394	{
5395	pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5396	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5397	cEntries, cbBuffer);
5398	}
5399	}
5400	/* Guest Virtual-APIC Log Tail Address Register. */
5401	{
5402	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5403	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5404	if (fVerbose)
5405	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5406	}
5407	/* PPR Log B Base Address Register. */
5408	{
5409	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5410	uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5411	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5412	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5413	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5414	if (fVerbose)
5415	{
5416	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5417	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5418	cEntries, cbBuffer);
5419	}
5420	}
5421	/* Event Log B Base Address Register. */
5422	{
5423	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5424	uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5425	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5426	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5427	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5428	if (fVerbose)
5429	{
5430	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5431	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5432	cEntries, cbBuffer);
5433	}
5434	}
5435	/* Device-Specific Feature Extension Register. */
5436	{
5437	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5438	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5439	if (fVerbose)
5440	{
5441	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5442	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5443	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5444	}
5445	}
5446	/* Device-Specific Control Extension Register. */
5447	{
5448	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5449	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5450	if (fVerbose)
5451	{
5452	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5453	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5454	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5455	}
5456	}
5457	/* Device-Specific Status Extension Register. */
5458	{
5459	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5460	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
5461	if (fVerbose)
5462	{
5463	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5464	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5465	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5466	}
5467	}
5468	/* Miscellaneous Information Register (Lo and Hi). */
5469	{
5470	MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5471	pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5472	if (fVerbose)
5473	{
5474	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5475	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5476	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5477	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5478	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5479	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5480	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5481	}
5482	}
5483	/* MSI Capability Header. */
5484	{
5485	MSI_CAP_HDR_T MsiCapHdr;
5486	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5487	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5488	if (fVerbose)
5489	{
5490	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5491	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5492	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5493	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5494	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5495	}
5496	}
5497	/* MSI Address Register (Lo and Hi). */
5498	{
5499	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5500	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5501	MSIADDR MsiAddr;
5502	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5503	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5504	if (fVerbose)
5505	{
5506	pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5507	pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5508	pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5509	pHlp->pfnPrintf(pHlp, " Address = %#Rx32\n", MsiAddr.n.u12Addr);
5510	pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#Rx32\n", MsiAddr.n.u32Rsvd0);
5511	}
5512	}
5513	/* MSI Data. */
5514	{
5515	MSIDATA MsiData;
5516	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5517	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5518	if (fVerbose)
5519	{
5520	pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5521	MsiData.n.u8Vector);
5522	pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5523	pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5524	pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5525	"level" : "edge");
5526	}
5527	}
5528	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5529	{
5530	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5531	MsiMapCapHdr.u32 = 0;
5532	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5533	if (fVerbose)
5534	{
5535	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5536	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5537	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5538	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5539	}
5540	}
5541	/* Performance Optimization Control Register. */
5542	{
5543	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5544	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5545	if (fVerbose)
5546	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5547	}
5548	/* XT (x2APIC) General Interrupt Control Register. */
5549	{
5550	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5551	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5552	if (fVerbose)
5553	{
5554	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5555	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5556	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5557	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5558	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5559	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5560	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5561	}
5562	}
5563	/* XT (x2APIC) PPR Interrupt Control Register. */
5564	{
5565	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5566	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5567	if (fVerbose)
5568	{
5569	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5570	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5571	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5572	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5573	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5574	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5575	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5576	}
5577	}
5578	/* XT (X2APIC) GA Log Interrupt Control Register. */
5579	{
5580	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5581	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5582	if (fVerbose)
5583	{
5584	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5585	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5586	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5587	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5588	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5589	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
5590	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5591	}
5592	}
5593	/* MARC Registers. */
5594	{
5595	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5596	{
5597	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5598	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5599	pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5600
5601	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5602	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5603	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5604	MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5605
5606	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5607	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5608	}
5609	}
5610	/* Reserved Register. */
5611	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5612	/* Command Buffer Head Pointer Register. */
5613	{
5614	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5615	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
5616	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
5617	}
5618	/* Command Buffer Tail Pointer Register. */
5619	{
5620	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5621	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
5622	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
5623	}
5624	/* Event Log Head Pointer Register. */
5625	{
5626	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5627	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
5628	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
5629	}
5630	/* Event Log Tail Pointer Register. */
5631	{
5632	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5633	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
5634	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
5635	}
5636	/* Status Register. */
5637	{
5638	IOMMU_STATUS_T const Status = pThis->Status;
5639	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5640	if (fVerbose)
5641	{
5642	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5643	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5644	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5645	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5646	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5647	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5648	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5649	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5650	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5651	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5652	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5653	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5654	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5655	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5656	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5657	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5658	}
5659	}
5660	/* PPR Log Head Pointer. */
5661	{
5662	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5663	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
5664	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
5665	}
5666	/* PPR Log Tail Pointer. */
5667	{
5668	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5669	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
5670	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
5671	}
5672	/* Guest Virtual-APIC Log Head Pointer. */
5673	{
5674	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5675	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
5676	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
5677	}
5678	/* Guest Virtual-APIC Log Tail Pointer. */
5679	{
5680	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5681	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
5682	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
5683	}
5684	/* PPR Log B Head Pointer. */
5685	{
5686	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5687	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
5688	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
5689	}
5690	/* PPR Log B Tail Pointer. */
5691	{
5692	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5693	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
5694	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
5695	}
5696	/* Event Log B Head Pointer. */
5697	{
5698	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5699	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
5700	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
5701	}
5702	/* Event Log B Tail Pointer. */
5703	{
5704	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5705	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
5706	pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
5707	}
5708	/* PPR Log Auto Response Register. */
5709	{
5710	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5711	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5712	if (fVerbose)
5713	{
5714	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5715	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5716	}
5717	}
5718	/* PPR Log Overflow Early Warning Indicator Register. */
5719	{
5720	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5721	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5722	if (fVerbose)
5723	{
5724	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5725	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5726	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5727	}
5728	}
5729	/* PPR Log Overflow Early Warning Indicator Register. */
5730	{
5731	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5732	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5733	if (fVerbose)
5734	{
5735	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5736	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5737	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5738	}
5739	}
5740	}
5741
5742
5743	/**
5744	* @callback_method_impl{FNSSMDEVSAVEEXEC}
5745	*/
5746	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5747	{
5748	/** @todo IOMMU: Save state. */
5749	RT_NOREF2(pDevIns, pSSM);
5750	return VERR_NOT_IMPLEMENTED;
5751	}
5752
5753
5754	/**
5755	* @callback_method_impl{FNSSMDEVLOADEXEC}
5756	*/
5757	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5758	{
5759	/** @todo IOMMU: Load state. */
5760	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
5761	return VERR_NOT_IMPLEMENTED;
5762	}
5763
5764
5765	/**
5766	* @interface_method_impl{PDMDEVREG,pfnReset}
5767	*/
5768	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
5769	{
5770	/*
5771	* Resets read-write portion of the IOMMU state.
5772	*
5773	* State data not initialized here is expected to be initialized during
5774	* device construction and remain read-only through the lifetime of the VM.
5775	*/
5776	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5777	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5778	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5779
5780	memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
5781
5782	pThis->CmdBufBaseAddr.u64 = 0;
5783	pThis->CmdBufBaseAddr.n.u4Len = 8;
5784
5785	pThis->EvtLogBaseAddr.u64 = 0;
5786	pThis->EvtLogBaseAddr.n.u4Len = 8;
5787
5788	pThis->Ctrl.u64 = 0;
5789
5790	pThis->ExclRangeBaseAddr.u64 = 0;
5791	pThis->ExclRangeLimit.u64 = 0;
5792
5793	pThis->PprLogBaseAddr.u64 = 0;
5794	pThis->PprLogBaseAddr.n.u4Len = 8;
5795
5796	pThis->HwEvtHi.u64 = 0;
5797	pThis->HwEvtLo = 0;
5798	pThis->HwEvtStatus.u64 = 0;
5799
5800	pThis->GALogBaseAddr.u64 = 0;
5801	pThis->GALogBaseAddr.n.u4Len = 8;
5802	pThis->GALogTailAddr.u64 = 0;
5803
5804	pThis->PprLogBBaseAddr.u64 = 0;
5805	pThis->PprLogBBaseAddr.n.u4Len = 8;
5806
5807	pThis->EvtLogBBaseAddr.u64 = 0;
5808	pThis->EvtLogBBaseAddr.n.u4Len = 8;
5809
5810	pThis->PerfOptCtrl.u32 = 0;
5811
5812	pThis->XtGenIntrCtrl.u64 = 0;
5813	pThis->XtPprIntrCtrl.u64 = 0;
5814	pThis->XtGALogIntrCtrl.u64 = 0;
5815
5816	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
5817
5818	pThis->CmdBufHeadPtr.u64 = 0;
5819	pThis->CmdBufTailPtr.u64 = 0;
5820	pThis->EvtLogHeadPtr.u64 = 0;
5821	pThis->EvtLogTailPtr.u64 = 0;
5822
5823	pThis->Status.u64 = 0;
5824
5825	pThis->PprLogHeadPtr.u64 = 0;
5826	pThis->PprLogTailPtr.u64 = 0;
5827
5828	pThis->GALogHeadPtr.u64 = 0;
5829	pThis->GALogTailPtr.u64 = 0;
5830
5831	pThis->PprLogBHeadPtr.u64 = 0;
5832	pThis->PprLogBTailPtr.u64 = 0;
5833
5834	pThis->EvtLogBHeadPtr.u64 = 0;
5835	pThis->EvtLogBTailPtr.u64 = 0;
5836
5837	pThis->PprLogAutoResp.u64 = 0;
5838	pThis->PprLogOverflowEarly.u64 = 0;
5839	pThis->PprLogBOverflowEarly.u64 = 0;
5840
5841	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
5842	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
5843	}
5844
5845
5846	/**
5847	* @interface_method_impl{PDMDEVREG,pfnDestruct}
5848	*/
5849	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
5850	{
5851	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5852	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5853	LogFlowFunc(("\n"));
5854
5855	/* Close the command thread semaphore. */
5856	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
5857	{
5858	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
5859	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
5860	}
5861	return VINF_SUCCESS;
5862	}
5863
5864
5865	/**
5866	* @interface_method_impl{PDMDEVREG,pfnConstruct}
5867	*/
5868	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5869	{
5870	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5871	RT_NOREF2(iInstance, pCfg);
5872	LogFlowFunc(("\n"));
5873
5874	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5875	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5876	pThisCC->pDevInsR3 = pDevIns;
5877
5878	/*
5879	* Register the IOMMU with PDM.
5880	*/
5881	PDMIOMMUREGR3 IommuReg;
5882	RT_ZERO(IommuReg);
5883	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5884	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5885	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5886	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5887	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5888	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
5889	if (RT_FAILURE(rc))
5890	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
5891	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
5892	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5893	N_("IOMMU helper version mismatch; got %#x expected %#x"),
5894	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
5895	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
5896	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5897	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
5898	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
5899
5900	/*
5901	* Initialize read-only PCI configuration space.
5902	*/
5903	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5904	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5905
5906	/* Header. */
5907	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
5908	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
5909	PDMPciDevSetCommand(pPciDev, 0); /* Command */
5910	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
5911	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
5912	PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
5913	PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
5914	PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
5915	PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
5916	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
5917	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
5918	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
5919	PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
5920	PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
5921
5922	/* Capability Header. */
5923	/* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
5924	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
5925	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
5926	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
5927	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
5928	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
5929	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
5930	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
5931	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
5932	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
5933	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
5934
5935	/* Base Address Low Register. */
5936	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
5937
5938	/* Base Address High Register. */
5939	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
5940
5941	/* IOMMU Range Register. */
5942	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
5943
5944	/* Misc. Information Register. */
5945	/* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
5946	uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
5947	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
5948	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
5949	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
5950	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
5951	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
5952	uint32_t const uMiscInfoReg1 = 0;
5953	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
5954	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
5955
5956	/* MSI Capability Header register. */
5957	PDMMSIREG MsiReg;
5958	RT_ZERO(MsiReg);
5959	MsiReg.cMsiVectors = 1;
5960	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
5961	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
5962	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
5963	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5964	AssertRCReturn(rc, rc);
5965
5966	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
5967	#if 0
5968	/* MSI Address Lo. */
5969	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
5970	/* MSI Address Hi. */
5971	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
5972	/* MSI Data. */
5973	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
5974	#endif
5975
5976	#if 0
5977	/** @todo IOMMU: I don't know if we need to support this, enable later if
5978	* required. */
5979	/* MSI Mapping Capability Header register. */
5980	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
5981	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
5982	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
5983	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
5984	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
5985	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
5986	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
5987	#endif
5988
5989	/*
5990	* Register the PCI function with PDM.
5991	*/
5992	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
5993	AssertLogRelRCReturn(rc, rc);
5994
5995	/*
5996	* Intercept PCI config. space accesses.
5997	*/
5998	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
5999	AssertLogRelRCReturn(rc, rc);
6000
6001	/*
6002	* Create the MMIO region.
6003	* Mapping of the region is done when software configures it via PCI config space.
6004	*/
6005	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6006	NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
6007	"AMD-IOMMU", &pThis->hMmio);
6008	AssertLogRelRCReturn(rc, rc);
6009
6010	/*
6011	* Register saved state.
6012	*/
6013	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
6014	NULL, NULL, NULL,
6015	NULL, iommuAmdR3SaveExec, NULL,
6016	NULL, iommuAmdR3LoadExec, NULL);
6017	AssertLogRelRCReturn(rc, rc);
6018
6019	/*
6020	* Register debugger info item.
6021	*/
6022	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6023	AssertLogRelRCReturn(rc, rc);
6024
6025	/*
6026	* Create the command thread and its event semaphore.
6027	*/
6028	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
6029	0 /* cbStack */, RTTHREADTYPE_IO, "AMD-IOMMU");
6030	AssertLogRelRCReturn(rc, rc);
6031
6032	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
6033	AssertLogRelRCReturn(rc, rc);
6034
6035	/*
6036	* Initialize read-only registers.
6037	* NOTE! Fields here must match their corresponding field in the ACPI tables.
6038	*/
6039	/** @todo Don't remove the =0 assignment for now. It's just there so it's easier
6040	* for me to see existing features that we might want to implement. Do it
6041	* later. */
6042	pThis->ExtFeat.u64 = 0;
6043	pThis->ExtFeat.n.u1PrefetchSup = 0;
6044	pThis->ExtFeat.n.u1PprSup = 0;
6045	pThis->ExtFeat.n.u1X2ApicSup = 0;
6046	pThis->ExtFeat.n.u1NoExecuteSup = 0;
6047	pThis->ExtFeat.n.u1GstTranslateSup = 0;
6048	pThis->ExtFeat.n.u1InvAllSup = 0;
6049	pThis->ExtFeat.n.u1GstVirtApicSup = 0;
6050	pThis->ExtFeat.n.u1HwErrorSup = 1;
6051	pThis->ExtFeat.n.u1PerfCounterSup = 0;
6052	AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
6053	pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
6054	pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
6055	pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
6056	pThis->ExtFeat.n.u2SmiFilterSup = 0;
6057	pThis->ExtFeat.n.u3SmiFilterCount = 0;
6058	pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
6059	pThis->ExtFeat.n.u2DualPprLogSup = 0;
6060	pThis->ExtFeat.n.u2DualEvtLogSup = 0;
6061	pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
6062	pThis->ExtFeat.n.u1UserSupervisorSup = 0;
6063	AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
6064	pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
6065	pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
6066	pThis->ExtFeat.n.u1PprAutoRespSup = 0;
6067	pThis->ExtFeat.n.u2MarcSup = 0;
6068	pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
6069	pThis->ExtFeat.n.u1PerfOptSup = 0;
6070	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
6071	pThis->ExtFeat.n.u1GstIoSup = 0;
6072	pThis->ExtFeat.n.u1HostAccessSup = 0;
6073	pThis->ExtFeat.n.u1EnhancedPprSup = 0;
6074	pThis->ExtFeat.n.u1AttrForwardSup = 0;
6075	pThis->ExtFeat.n.u1HostDirtySup = 0;
6076	pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
6077	pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
6078	pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
6079
6080	pThis->RsvdReg = 0;
6081
6082	pThis->DevSpecificFeat.u64 = 0;
6083	pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
6084	pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
6085
6086	pThis->DevSpecificCtrl.u64 = 0;
6087	pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
6088	pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
6089
6090	pThis->DevSpecificStatus.u64 = 0;
6091	pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
6092	pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
6093
6094	pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
6095
6096	/*
6097	* Initialize parts of the IOMMU state as it would during reset.
6098	* Must be called -after- initializing PCI config. space registers.
6099	*/
6100	iommuAmdR3Reset(pDevIns);
6101
6102	return VINF_SUCCESS;
6103	}
6104
6105	# else /* !IN_RING3 */
6106
6107	/**
6108	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
6109	*/
6110	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
6111	{
6112	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6113	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6114	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
6115
6116	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
6117
6118	/* Set up the MMIO RZ handlers. */
6119	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
6120	AssertRCReturn(rc, rc);
6121
6122	/* Set up the IOMMU RZ callbacks. */
6123	PDMIOMMUREGCC IommuReg;
6124	RT_ZERO(IommuReg);
6125	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6126	IommuReg.idxIommu = pThis->idxIommu;
6127	IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
6128	IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
6129	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
6130	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6131	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
6132	AssertRCReturn(rc, rc);
6133
6134	return VINF_SUCCESS;
6135	}
6136
6137	# endif /* !IN_RING3 */
6138
6139	/**
6140	* The device registration structure.
6141	*/
6142	const PDMDEVREG g_DeviceIommuAmd =
6143	{
6144	/* .u32Version = */ PDM_DEVREG_VERSION,
6145	/* .uReserved0 = */ 0,
6146	/* .szName = */ "iommu-amd",
6147	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
6148	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
6149	/* .cMaxInstances = */ ~0U,
6150	/* .uSharedVersion = */ 42,
6151	/* .cbInstanceShared = */ sizeof(IOMMU),
6152	/* .cbInstanceCC = */ sizeof(IOMMUCC),
6153	/* .cbInstanceRC = */ sizeof(IOMMURC),
6154	/* .cMaxPciDevices = */ 1,
6155	/* .cMaxMsixVectors = */ 0,
6156	/* .pszDescription = */ "IOMMU (AMD)",
6157	#if defined(IN_RING3)
6158	/* .pszRCMod = */ "VBoxDDRC.rc",
6159	/* .pszR0Mod = */ "VBoxDDR0.r0",
6160	/* .pfnConstruct = */ iommuAmdR3Construct,
6161	/* .pfnDestruct = */ iommuAmdR3Destruct,
6162	/* .pfnRelocate = */ NULL,
6163	/* .pfnMemSetup = */ NULL,
6164	/* .pfnPowerOn = */ NULL,
6165	/* .pfnReset = */ iommuAmdR3Reset,
6166	/* .pfnSuspend = */ NULL,
6167	/* .pfnResume = */ NULL,
6168	/* .pfnAttach = */ NULL,
6169	/* .pfnDetach = */ NULL,
6170	/* .pfnQueryInterface = */ NULL,
6171	/* .pfnInitComplete = */ NULL,
6172	/* .pfnPowerOff = */ NULL,
6173	/* .pfnSoftReset = */ NULL,
6174	/* .pfnReserved0 = */ NULL,
6175	/* .pfnReserved1 = */ NULL,
6176	/* .pfnReserved2 = */ NULL,
6177	/* .pfnReserved3 = */ NULL,
6178	/* .pfnReserved4 = */ NULL,
6179	/* .pfnReserved5 = */ NULL,
6180	/* .pfnReserved6 = */ NULL,
6181	/* .pfnReserved7 = */ NULL,
6182	#elif defined(IN_RING0)
6183	/* .pfnEarlyConstruct = */ NULL,
6184	/* .pfnConstruct = */ iommuAmdRZConstruct,
6185	/* .pfnDestruct = */ NULL,
6186	/* .pfnFinalDestruct = */ NULL,
6187	/* .pfnRequest = */ NULL,
6188	/* .pfnReserved0 = */ NULL,
6189	/* .pfnReserved1 = */ NULL,
6190	/* .pfnReserved2 = */ NULL,
6191	/* .pfnReserved3 = */ NULL,
6192	/* .pfnReserved4 = */ NULL,
6193	/* .pfnReserved5 = */ NULL,
6194	/* .pfnReserved6 = */ NULL,
6195	/* .pfnReserved7 = */ NULL,
6196	#elif defined(IN_RC)
6197	/* .pfnConstruct = */ iommuAmdRZConstruct,
6198	/* .pfnReserved0 = */ NULL,
6199	/* .pfnReserved1 = */ NULL,
6200	/* .pfnReserved2 = */ NULL,
6201	/* .pfnReserved3 = */ NULL,
6202	/* .pfnReserved4 = */ NULL,
6203	/* .pfnReserved5 = */ NULL,
6204	/* .pfnReserved6 = */ NULL,
6205	/* .pfnReserved7 = */ NULL,
6206	#else
6207	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
6208	#endif
6209	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
6210	};
6211
6212	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
6213

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 85726

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