VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 85912

Last change on this file since 85912 was 85912, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Split IOMMU data into relevant headers to share it with other devices/VMM (ACPI, chipset, maybe Main and firmware in the future).
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1/* $Id: DevIommuAmd.cpp 85912 2020-08-28 07:17:55Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/string.h>
30
31#include "VBoxDD.h"
32#include "DevIommuAmd.h"
33
34
35/*********************************************************************************************************************************
36* Defined Constants And Macros *
37*********************************************************************************************************************************/
38/** Log prefix string. */
39#define IOMMU_LOG_PFX "IOMMU-AMD"
40/** The current saved state version. */
41#define IOMMU_SAVED_STATE_VERSION 1
42/** The IOTLB entry magic. */
43#define IOMMU_IOTLBE_MAGIC 0x10acce55
44
45
46/*********************************************************************************************************************************
47* Structures and Typedefs *
48*********************************************************************************************************************************/
49/**
50 * Acquires the IOMMU PDM lock.
51 * This will make a long jump to ring-3 to acquire the lock if necessary.
52 */
53#define IOMMU_LOCK(a_pDevIns) \
54 do { \
55 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
56 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
57 { /* likely */ } \
58 else \
59 return rcLock; \
60 } while (0)
61
62/**
63 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
64 * This will make a long jump to ring-3 to acquire the lock if necessary.
65 */
66#define IOMMU_LOCK_NORET(a_pDevIns) \
67 do { \
68 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
69 AssertRC(rcLock); \
70 } while (0)
71
72/**
73 * Releases the IOMMU PDM lock.
74 */
75#define IOMMU_UNLOCK(a_pDevIns) \
76 do { \
77 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
78 } while (0)
79
80/**
81 * Asserts that the critsect is owned by this thread.
82 */
83#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
84 do { \
85 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
86 } while (0)
87
88/**
89 * Asserts that the critsect is not owned by this thread.
90 */
91#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
92 do { \
93 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
94 } while (0)
95
96/**
97 * IOMMU operations (transaction) types.
98 */
99typedef enum IOMMUOP
100{
101 /** Address translation request. */
102 IOMMUOP_TRANSLATE_REQ = 0,
103 /** Memory read request. */
104 IOMMUOP_MEM_READ,
105 /** Memory write request. */
106 IOMMUOP_MEM_WRITE,
107 /** Interrupt request. */
108 IOMMUOP_INTR_REQ,
109 /** Command. */
110 IOMMUOP_CMD
111} IOMMUOP;
112AssertCompileSize(IOMMUOP, 4);
113
114/**
115 * I/O page walk result.
116 */
117typedef struct
118{
119 /** The translated system physical address. */
120 RTGCPHYS GCPhysSpa;
121 /** The number of offset bits in the system physical address. */
122 uint8_t cShift;
123 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
124 uint8_t fIoPerm;
125 /** Padding. */
126 uint8_t abPadding[2];
127} IOWALKRESULT;
128/** Pointer to an I/O walk result struct. */
129typedef IOWALKRESULT *PIOWALKRESULT;
130/** Pointer to a const I/O walk result struct. */
131typedef IOWALKRESULT *PCIOWALKRESULT;
132
133/**
134 * IOMMU I/O TLB Entry.
135 * Keep this as small and aligned as possible.
136 */
137typedef struct
138{
139 /** The translated system physical address (SPA) of the page. */
140 RTGCPHYS GCPhysSpa;
141 /** The index of the 4K page within a large page. */
142 uint32_t idxSubPage;
143 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
144 uint8_t fIoPerm;
145 /** The number of offset bits in the translation indicating page size. */
146 uint8_t cShift;
147 /** Alignment padding. */
148 uint8_t afPadding[2];
149} IOTLBE_T;
150AssertCompileSize(IOTLBE_T, 16);
151/** Pointer to an IOMMU I/O TLB entry struct. */
152typedef IOTLBE_T *PIOTLBE_T;
153/** Pointer to a const IOMMU I/O TLB entry struct. */
154typedef IOTLBE_T const *PCIOTLBE_T;
155
156/**
157 * The shared IOMMU device state.
158 */
159typedef struct IOMMU
160{
161 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
162 uint32_t idxIommu;
163 /** Alignment padding. */
164 uint32_t uPadding0;
165
166 /** Whether the command thread is sleeping. */
167 bool volatile fCmdThreadSleeping;
168 /** Alignment padding. */
169 uint8_t afPadding0[3];
170 /** Whether the command thread has been signaled for wake up. */
171 bool volatile fCmdThreadSignaled;
172 /** Alignment padding. */
173 uint8_t afPadding1[3];
174
175 /** The event semaphore the command thread waits on. */
176 SUPSEMEVENT hEvtCmdThread;
177 /** The MMIO handle. */
178 IOMMMIOHANDLE hMmio;
179
180 /** @name PCI: Base capability block registers.
181 * @{ */
182 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
183 /** @} */
184
185 /** @name MMIO: Control and status registers.
186 * @{ */
187 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
188 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
189 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
190 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
191 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
192 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
193 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
194 /** @} */
195
196 /** @name MMIO: PPR Log registers.
197 * @{ */
198 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
199 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
200 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
201 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
202 /** @} */
203
204 /** @todo IOMMU: SMI filter. */
205
206 /** @name MMIO: Guest Virtual-APIC Log registers.
207 * @{ */
208 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
209 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
210 /** @} */
211
212 /** @name MMIO: Alternate PPR and Event Log registers.
213 * @{ */
214 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
215 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
216 /** @} */
217
218 /** @name MMIO: Device-specific feature registers.
219 * @{ */
220 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
221 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
222 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
223 /** @} */
224
225 /** @name MMIO: MSI Capability Block registers.
226 * @{ */
227 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
228 /** @} */
229
230 /** @name MMIO: Performance Optimization Control registers.
231 * @{ */
232 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
233 /** @} */
234
235 /** @name MMIO: x2APIC Control registers.
236 * @{ */
237 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
238 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
239 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
240 /** @} */
241
242 /** @name MMIO: MARC registers.
243 * @{ */
244 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
245 /** @} */
246
247 /** @name MMIO: Reserved register.
248 * @{ */
249 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
250 /** @} */
251
252 /** @name MMIO: Command and Event Log pointer registers.
253 * @{ */
254 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
255 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
256 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
257 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
258 /** @} */
259
260 /** @name MMIO: Command and Event Status register.
261 * @{ */
262 IOMMU_STATUS_T Status; /**< IOMMU status register. */
263 /** @} */
264
265 /** @name MMIO: PPR Log Head and Tail pointer registers.
266 * @{ */
267 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
268 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
269 /** @} */
270
271 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
272 * @{ */
273 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
274 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
275 /** @} */
276
277 /** @name MMIO: PPR Log B Head and Tail pointer registers.
278 * @{ */
279 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
280 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
281 /** @} */
282
283 /** @name MMIO: Event Log B Head and Tail pointer registers.
284 * @{ */
285 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
286 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
287 /** @} */
288
289 /** @name MMIO: PPR Log Overflow protection registers.
290 * @{ */
291 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
292 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
293 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
294 /** @} */
295
296 /** @todo IOMMU: IOMMU Event counter registers. */
297
298 /** @todo IOMMU: Stat counters. */
299} IOMMU;
300/** Pointer to the IOMMU device state. */
301typedef struct IOMMU *PIOMMU;
302/** Pointer to the const IOMMU device state. */
303typedef const struct IOMMU *PCIOMMU;
304AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
305AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
306AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
307AssertCompileMemberAlignment(IOMMU, hMmio, 8);
308AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
309
310/**
311 * The ring-3 IOMMU device state.
312 */
313typedef struct IOMMUR3
314{
315 /** Device instance. */
316 PPDMDEVINSR3 pDevInsR3;
317 /** The IOMMU helpers. */
318 PCPDMIOMMUHLPR3 pIommuHlpR3;
319 /** The command thread handle. */
320 R3PTRTYPE(PPDMTHREAD) pCmdThread;
321} IOMMUR3;
322/** Pointer to the ring-3 IOMMU device state. */
323typedef IOMMUR3 *PIOMMUR3;
324
325/**
326 * The ring-0 IOMMU device state.
327 */
328typedef struct IOMMUR0
329{
330 /** Device instance. */
331 PPDMDEVINSR0 pDevInsR0;
332 /** The IOMMU helpers. */
333 PCPDMIOMMUHLPR0 pIommuHlpR0;
334} IOMMUR0;
335/** Pointer to the ring-0 IOMMU device state. */
336typedef IOMMUR0 *PIOMMUR0;
337
338/**
339 * The raw-mode IOMMU device state.
340 */
341typedef struct IOMMURC
342{
343 /** Device instance. */
344 PPDMDEVINSR0 pDevInsRC;
345 /** The IOMMU helpers. */
346 PCPDMIOMMUHLPRC pIommuHlpRC;
347} IOMMURC;
348/** Pointer to the raw-mode IOMMU device state. */
349typedef IOMMURC *PIOMMURC;
350
351/** The IOMMU device state for the current context. */
352typedef CTX_SUFF(IOMMU) IOMMUCC;
353/** Pointer to the IOMMU device state for the current context. */
354typedef CTX_SUFF(PIOMMU) PIOMMUCC;
355
356/**
357 * IOMMU register access routines.
358 */
359typedef struct
360{
361 const char *pszName;
362 VBOXSTRICTRC (*pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t *pu64Value);
363 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
364 bool f64BitReg;
365} IOMMUREGACC;
366
367
368/*********************************************************************************************************************************
369* Global Variables *
370*********************************************************************************************************************************/
371/**
372 * An array of the number of device table segments supported.
373 * Indexed by u2DevTabSegSup.
374 */
375static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
376
377/**
378 * An array of the masks to select the device table segment index from a device ID.
379 */
380static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
381
382/**
383 * The maximum size (inclusive) of each device table segment (0 to 7).
384 * Indexed by the device table segment index.
385 */
386static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
387
388
389#ifndef VBOX_DEVICE_STRUCT_TESTCASE
390/**
391 * Gets the maximum number of buffer entries for the given buffer length.
392 *
393 * @returns Number of buffer entries.
394 * @param uEncodedLen The length (power-of-2 encoded).
395 */
396DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
397{
398 Assert(uEncodedLen > 7);
399 return 2 << (uEncodedLen - 1);
400}
401
402
403/**
404 * Gets the total length of the buffer given a base register's encoded length.
405 *
406 * @returns The length of the buffer in bytes.
407 * @param uEncodedLen The length (power-of-2 encoded).
408 */
409DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
410{
411 Assert(uEncodedLen > 7);
412 return (2 << (uEncodedLen - 1)) << 4;
413}
414
415
416/**
417 * Gets the number of (unconsumed) entries in the event log.
418 *
419 * @returns The number of entries in the event log.
420 * @param pThis The IOMMU device state.
421 */
422static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
423{
424 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
425 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
426 if (idxTail >= idxHead)
427 return idxTail - idxHead;
428
429 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
430 return cMaxEvts - idxHead + idxTail;
431}
432
433
434/**
435 * Gets the number of (unconsumed) commands in the command buffer.
436 *
437 * @returns The number of commands in the command buffer.
438 * @param pThis The IOMMU device state.
439 */
440static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
441{
442 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
443 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
444 if (idxTail >= idxHead)
445 return idxTail - idxHead;
446
447 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
448 return cMaxCmds - idxHead + idxTail;
449}
450
451
452DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
453{
454 IOMMU_STATUS_T Status;
455 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
456 return Status;
457}
458
459
460DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
461{
462 IOMMU_CTRL_T Ctrl;
463 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
464 return Ctrl;
465}
466
467
468/**
469 * Returns whether MSI is enabled for the IOMMU.
470 *
471 * @returns Whether MSI is enabled.
472 * @param pDevIns The IOMMU device instance.
473 *
474 * @note There should be a PCIDevXxx function for this.
475 */
476static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
477{
478 MSI_CAP_HDR_T MsiCapHdr;
479 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
480 return MsiCapHdr.n.u1MsiEnable;
481}
482
483
484/**
485 * Signals a PCI target abort.
486 *
487 * @param pDevIns The IOMMU device instance.
488 */
489static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
490{
491 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
492 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
493 PDMPciDevSetStatus(pPciDev, u16Status);
494}
495
496
497/**
498 * Wakes up the command thread if there are commands to be processed or if
499 * processing is requested to be stopped by software.
500 *
501 * @param pDevIns The IOMMU device instance.
502 */
503static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
504{
505 IOMMU_ASSERT_LOCKED(pDevIns);
506 LogFlowFunc(("\n"));
507
508 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
509 if ( !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true)
510 && ASMAtomicReadBool(&pThis->fCmdThreadSleeping))
511 {
512 LogFlowFunc(("Signaling command thread\n"));
513 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
514 }
515}
516
517
518/**
519 * Writes to a read-only register.
520 */
521static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
522{
523 RT_NOREF(pDevIns, pThis, iReg, u64Value);
524 Log((IOMMU_LOG_PFX ": Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
525 return VINF_SUCCESS;
526}
527
528
529/**
530 * Writes the Device Table Base Address Register.
531 */
532static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
533{
534 RT_NOREF(pDevIns, iReg);
535
536 /* Mask out all unrecognized bits. */
537 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
538
539 /* Update the register. */
540 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
541 return VINF_SUCCESS;
542}
543
544
545/**
546 * Writes the Command Buffer Base Address Register.
547 */
548static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
549{
550 RT_NOREF(pDevIns, iReg);
551
552 /*
553 * While this is not explicitly specified like the event log base address register,
554 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
555 * Inconsistent specs :/
556 */
557 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
558 if (Status.n.u1CmdBufRunning)
559 {
560 Log((IOMMU_LOG_PFX ": Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
561 return VINF_SUCCESS;
562 }
563
564 /* Mask out all unrecognized bits. */
565 CMD_BUF_BAR_T CmdBufBaseAddr;
566 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
567
568 /* Validate the length. */
569 if (CmdBufBaseAddr.n.u4Len >= 8)
570 {
571 /* Update the register. */
572 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
573
574 /*
575 * Writing the command buffer base address, clears the command buffer head and tail pointers.
576 * See AMD spec. 2.4 "Commands".
577 */
578 pThis->CmdBufHeadPtr.u64 = 0;
579 pThis->CmdBufTailPtr.u64 = 0;
580 }
581 else
582 Log((IOMMU_LOG_PFX ": Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
583
584 return VINF_SUCCESS;
585}
586
587
588/**
589 * Writes the Event Log Base Address Register.
590 */
591static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
592{
593 RT_NOREF(pDevIns, iReg);
594
595 /*
596 * IOMMU behavior is undefined when software writes this register when event logging is running.
597 * In our emulation, we ignore the write entirely.
598 * See AMD IOMMU spec. "Event Log Base Address Register".
599 */
600 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
601 if (Status.n.u1EvtLogRunning)
602 {
603 Log((IOMMU_LOG_PFX ": Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
604 return VINF_SUCCESS;
605 }
606
607 /* Mask out all unrecognized bits. */
608 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
609 EVT_LOG_BAR_T EvtLogBaseAddr;
610 EvtLogBaseAddr.u64 = u64Value;
611
612 /* Validate the length. */
613 if (EvtLogBaseAddr.n.u4Len >= 8)
614 {
615 /* Update the register. */
616 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
617
618 /*
619 * Writing the event log base address, clears the event log head and tail pointers.
620 * See AMD spec. 2.5 "Event Logging".
621 */
622 pThis->EvtLogHeadPtr.u64 = 0;
623 pThis->EvtLogTailPtr.u64 = 0;
624 }
625 else
626 Log((IOMMU_LOG_PFX ": Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
627
628 return VINF_SUCCESS;
629}
630
631
632/**
633 * Writes the Control Register.
634 */
635static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
636{
637 RT_NOREF(pDevIns, iReg);
638
639 /* Mask out all unrecognized bits. */
640 u64Value &= IOMMU_CTRL_VALID_MASK;
641
642 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
643 IOMMU_CTRL_T NewCtrl;
644 NewCtrl.u64 = u64Value;
645
646 /* Update the register. */
647 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
648
649 /* Enable or disable event logging when the bit transitions. */
650 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
651 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
652 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
653 if (fOldEvtLogEn != fNewEvtLogEn)
654 {
655 if ( fNewIommuEn
656 && fNewEvtLogEn)
657 {
658 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
659 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
660 }
661 else
662 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
663 }
664
665 /* Enable or disable command buffer processing when the bit transitions. */
666 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
667 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
668 if (fOldCmdBufEn != fNewCmdBufEn)
669 {
670 if ( fNewIommuEn
671 && fNewCmdBufEn)
672 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
673 else
674 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
675
676 /* Wake up the command thread to start or stop processing commands. */
677 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
678 }
679
680 return VINF_SUCCESS;
681}
682
683
684/**
685 * Writes to the Excluse Range Base Address Register.
686 */
687static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
688{
689 RT_NOREF(pDevIns, iReg);
690 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
691 return VINF_SUCCESS;
692}
693
694
695/**
696 * Writes to the Excluse Range Limit Register.
697 */
698static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
699{
700 RT_NOREF(pDevIns, iReg);
701 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
702 u64Value |= UINT64_C(0xfff);
703 pThis->ExclRangeLimit.u64 = u64Value;
704 return VINF_SUCCESS;
705}
706
707
708/**
709 * Writes the Hardware Event Register (Hi).
710 */
711static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
712{
713 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
714 RT_NOREF(pDevIns, iReg);
715 Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
716 pThis->HwEvtHi.u64 = u64Value;
717 return VINF_SUCCESS;
718}
719
720
721/**
722 * Writes the Hardware Event Register (Lo).
723 */
724static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
725{
726 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
727 RT_NOREF(pDevIns, iReg);
728 Log((IOMMU_LOG_PFX ": Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
729 pThis->HwEvtLo = u64Value;
730 return VINF_SUCCESS;
731}
732
733
734/**
735 * Writes the Hardware Event Status Register.
736 */
737static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
738{
739 RT_NOREF(pDevIns, iReg);
740
741 /* Mask out all unrecognized bits. */
742 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
743
744 /*
745 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
746 * If the current status bits or the bits being written are both 0, we've nothing to do.
747 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
748 */
749 uint64_t HwStatus = pThis->HwEvtStatus.u64;
750 if (!(HwStatus & RT_BIT(0)))
751 return VINF_SUCCESS;
752 if (u64Value & HwStatus & RT_BIT_64(0))
753 HwStatus &= ~RT_BIT_64(0);
754 if (u64Value & HwStatus & RT_BIT_64(1))
755 HwStatus &= ~RT_BIT_64(1);
756
757 /* Update the register. */
758 pThis->HwEvtStatus.u64 = HwStatus;
759 return VINF_SUCCESS;
760}
761
762
763/**
764 * Writes the Device Table Segment Base Address Register.
765 */
766static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
767{
768 RT_NOREF(pDevIns);
769
770 /* Figure out which segment is being written. */
771 uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
772 uint8_t const idxSegment = offSegment + 1;
773 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
774
775 /* Mask out all unrecognized bits. */
776 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
777 DEV_TAB_BAR_T DevTabSegBar;
778 DevTabSegBar.u64 = u64Value;
779
780 /* Validate the size. */
781 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
782 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
783 if (uSegSize <= uMaxSegSize)
784 {
785 /* Update the register. */
786 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
787 }
788 else
789 Log((IOMMU_LOG_PFX ": Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
790
791 return VINF_SUCCESS;
792}
793
794
795/**
796 * Writes the MSI Capability Header Register.
797 */
798static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
799{
800 RT_NOREF(pThis, iReg);
801 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
802 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
803 MSI_CAP_HDR_T MsiCapHdr;
804 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
805 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
806 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
807 return VINF_SUCCESS;
808}
809
810
811/**
812 * Writes the MSI Address (Lo) Register (32-bit).
813 */
814static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
815{
816 RT_NOREF(pThis, iReg);
817 Assert(!RT_HI_U32(u64Value));
818 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
819 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
820 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
821 return VINF_SUCCESS;
822}
823
824
825/**
826 * Writes the MSI Address (Hi) Register (32-bit).
827 */
828static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
829{
830 RT_NOREF(pThis, iReg);
831 Assert(!RT_HI_U32(u64Value));
832 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
833 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
834 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
835 return VINF_SUCCESS;
836}
837
838
839/**
840 * Writes the MSI Data Register (32-bit).
841 */
842static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
843{
844 RT_NOREF(pThis, iReg);
845 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
846 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
847 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
848 return VINF_SUCCESS;
849}
850
851
852/**
853 * Writes the Command Buffer Head Pointer Register (32-bit).
854 */
855static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
856{
857 RT_NOREF(pDevIns, iReg);
858
859 /*
860 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
861 * In our emulation, we ignore the write entirely.
862 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
863 */
864 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
865 if (Status.n.u1CmdBufRunning)
866 {
867 Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
868 return VINF_SUCCESS;
869 }
870
871 /*
872 * IOMMU behavior is undefined when software writes a value outside the buffer length.
873 * In our emulation, we ignore the write entirely.
874 */
875 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
876 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
877 Assert(cbBuf <= _512K);
878 if (offBuf >= cbBuf)
879 {
880 Log((IOMMU_LOG_PFX ": Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n",
881 offBuf, cbBuf));
882 return VINF_SUCCESS;
883 }
884
885 /* Update the register. */
886 pThis->CmdBufHeadPtr.au32[0] = offBuf;
887
888 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
889
890 LogFlow((IOMMU_LOG_PFX ": Set CmdBufHeadPtr to %#RX32\n", offBuf));
891 return VINF_SUCCESS;
892}
893
894
895/**
896 * Writes the Command Buffer Tail Pointer Register (32-bit).
897 */
898static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
899{
900 RT_NOREF(pDevIns, iReg);
901
902 /*
903 * IOMMU behavior is undefined when software writes a value outside the buffer length.
904 * In our emulation, we ignore the write entirely.
905 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
906 */
907 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
908 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
909 Assert(cbBuf <= _512K);
910 if (offBuf >= cbBuf)
911 {
912 Log((IOMMU_LOG_PFX ": Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
913 offBuf, cbBuf));
914 return VINF_SUCCESS;
915 }
916
917 /*
918 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
919 * head pointer after adding one or more commands to the buffer.
920 *
921 * However, we cannot enforce this strictly because it's legal for software to shrink the
922 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
923 * at 0). Software might even make the queue empty by making head and tail equal which is
924 * allowed. I don't think we can or should try too hard to prevent software shooting itself
925 * in the foot here. As long as we make sure the offset value is within the circular buffer
926 * bounds (which we do by masking bits above) it should be sufficient.
927 */
928 pThis->CmdBufTailPtr.au32[0] = offBuf;
929
930 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
931
932 LogFlow((IOMMU_LOG_PFX ": Set CmdBufTailPtr to %#RX32\n", offBuf));
933 return VINF_SUCCESS;
934}
935
936
937/**
938 * Writes the Event Log Head Pointer Register (32-bit).
939 */
940static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
941{
942 RT_NOREF(pDevIns, iReg);
943
944 /*
945 * IOMMU behavior is undefined when software writes a value outside the buffer length.
946 * In our emulation, we ignore the write entirely.
947 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
948 */
949 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
950 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
951 Assert(cbBuf <= _512K);
952 if (offBuf >= cbBuf)
953 {
954 Log((IOMMU_LOG_PFX ": Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
955 offBuf, cbBuf));
956 return VINF_SUCCESS;
957 }
958
959 /* Update the register. */
960 pThis->EvtLogHeadPtr.au32[0] = offBuf;
961
962 LogFlow((IOMMU_LOG_PFX ": Set EvtLogHeadPtr to %#RX32\n", offBuf));
963 return VINF_SUCCESS;
964}
965
966
967/**
968 * Writes the Event Log Tail Pointer Register (32-bit).
969 */
970static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
971{
972 RT_NOREF(pDevIns, iReg);
973 NOREF(pThis);
974
975 /*
976 * IOMMU behavior is undefined when software writes this register when the event log is running.
977 * In our emulation, we ignore the write entirely.
978 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
979 */
980 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
981 if (Status.n.u1EvtLogRunning)
982 {
983 Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
984 return VINF_SUCCESS;
985 }
986
987 /*
988 * IOMMU behavior is undefined when software writes a value outside the buffer length.
989 * In our emulation, we ignore the write entirely.
990 */
991 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
992 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
993 Assert(cbBuf <= _512K);
994 if (offBuf >= cbBuf)
995 {
996 Log((IOMMU_LOG_PFX ": Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n",
997 offBuf, cbBuf));
998 return VINF_SUCCESS;
999 }
1000
1001 /* Update the register. */
1002 pThis->EvtLogTailPtr.au32[0] = offBuf;
1003
1004 LogFlow((IOMMU_LOG_PFX ": Set EvtLogTailPtr to %#RX32\n", offBuf));
1005 return VINF_SUCCESS;
1006}
1007
1008
1009/**
1010 * Writes the Status Register (64-bit).
1011 */
1012static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
1013{
1014 RT_NOREF(pDevIns, iReg);
1015
1016 /* Mask out all unrecognized bits. */
1017 u64Value &= IOMMU_STATUS_VALID_MASK;
1018
1019 /*
1020 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1021 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1022 */
1023 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1024 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1025 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1026 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1027
1028 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1029
1030 /* Update the register. */
1031 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1032 return VINF_SUCCESS;
1033}
1034
1035
1036#if 0
1037/**
1038 * Table 0: Registers-access table.
1039 */
1040static const IOMMUREGACC g_aTable0Regs[] =
1041{
1042
1043};
1044
1045/**
1046 * Table 1: Registers-access table.
1047 */
1048static const IOMMUREGACC g_aTable1Regs[] =
1049{
1050};
1051#endif
1052
1053
1054/**
1055 * Writes an IOMMU register (32-bit and 64-bit).
1056 *
1057 * @returns Strict VBox status code.
1058 * @param pDevIns The IOMMU device instance.
1059 * @param off MMIO byte offset to the register.
1060 * @param cb The size of the write access.
1061 * @param uValue The value being written.
1062 *
1063 * @thread EMT.
1064 */
1065static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1066{
1067 Assert(off < IOMMU_MMIO_REGION_SIZE);
1068 Assert(cb == 4 || cb == 8);
1069 Assert(!(off & (cb - 1)));
1070
1071 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1072 switch (off)
1073 {
1074 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1075 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1076 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1077 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1078 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1079 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1080 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1081
1082 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1083 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1084 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1085 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1086
1087 case IOMMU_MMIO_OFF_GALOG_BAR:
1088 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1089
1090 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1091 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1092
1093 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1094 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1095 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1096 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1097 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1098 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1099 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1100
1101 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1102 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1103 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1104
1105 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1106 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1107 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1108 {
1109 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1110 if (cb == 4 || RT_FAILURE(rcStrict))
1111 return rcStrict;
1112 uValue >>= 32;
1113 RT_FALL_THRU();
1114 }
1115 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1116 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1117 {
1118 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1119 if (cb == 4 || RT_FAILURE(rcStrict))
1120 return rcStrict;
1121 uValue >>= 32;
1122 RT_FALL_THRU();
1123 }
1124 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1125 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1126
1127 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1128
1129 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1130 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1131 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1132
1133 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1134 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1135 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1136 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1137 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1138 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1139 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1140 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1141 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1142 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1143 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1144 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1145
1146 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1147
1148 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1149 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1150 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1151 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1152
1153 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1154
1155 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1156 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1157
1158 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1159 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1160
1161 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1162 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1163
1164 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1165 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1166
1167 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1168 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1169 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1170
1171 /* Not implemented. */
1172 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1173 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1174 {
1175 Log((IOMMU_LOG_PFX ": Writing unsupported register: SMI filter %u -> Ignored\n",
1176 (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1177 return VINF_SUCCESS;
1178 }
1179
1180 /* Unknown. */
1181 default:
1182 {
1183 Log((IOMMU_LOG_PFX ": Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1184 return VINF_SUCCESS;
1185 }
1186 }
1187}
1188
1189
1190/**
1191 * Reads an IOMMU register (64-bit) given its MMIO offset.
1192 *
1193 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1194 * boundary include the lower half of the subsequent register.
1195 *
1196 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1197 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1198 * software will only perform 32-bit reads on those 32-bit registers that are
1199 * aligned on 8-byte boundaries.
1200 *
1201 * @returns Strict VBox status code.
1202 * @param pDevIns The IOMMU device instance.
1203 * @param off The MMIO offset of the register in bytes.
1204 * @param puResult Where to store the value being read.
1205 *
1206 * @thread EMT.
1207 */
1208static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1209{
1210 Assert(off < IOMMU_MMIO_REGION_SIZE);
1211 Assert(!(off & 7) || !(off & 3));
1212
1213 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1214 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1215 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1216
1217 /** @todo IOMMU: fine-grained locking? */
1218 uint64_t uReg;
1219 switch (off)
1220 {
1221 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1222 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1223 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1224 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1225 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1226 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1227 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1228
1229 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1230 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1231 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1232 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1233
1234 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1235 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1236
1237 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1238 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1239
1240 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1241 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1242 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1243 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1244 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1245 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1246 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1247 {
1248 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1249 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1250 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1251 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1252 break;
1253 }
1254
1255 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1256 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1257 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1258
1259 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1260 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1261 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1262 {
1263 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1264 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1265 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1266 break;
1267 }
1268 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1269 {
1270 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1271 break;
1272 }
1273 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1274 {
1275 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1276 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1277 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1278 break;
1279 }
1280 case IOMMU_MMIO_OFF_MSI_DATA:
1281 {
1282 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1283 break;
1284 }
1285 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1286 {
1287 /*
1288 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1289 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1290 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1291 * 0 for this register.
1292 */
1293 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1294 break;
1295 }
1296
1297 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1298
1299 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1300 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1301 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1302
1303 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1304 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1305 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1306 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1307 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1308 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1309 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1310 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1311 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1312 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1313 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1314 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1315
1316 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1317
1318 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1319 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1320 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1321 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1322
1323 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
1324
1325 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
1326 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
1327
1328 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
1329 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
1330
1331 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
1332 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
1333
1334 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
1335 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
1336
1337 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
1338 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
1339 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
1340
1341 /* Not implemented. */
1342 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1343 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1344 {
1345 Log((IOMMU_LOG_PFX ": Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1346 uReg = 0;
1347 break;
1348 }
1349
1350 /* Unknown. */
1351 default:
1352 {
1353 Log((IOMMU_LOG_PFX ": Reading unknown register %u (%#x) -> 0\n", off, off));
1354 uReg = 0;
1355 return VINF_IOM_MMIO_UNUSED_00;
1356 }
1357 }
1358
1359 *puResult = uReg;
1360 return VINF_SUCCESS;
1361}
1362
1363
1364/**
1365 * Raises the MSI interrupt for the IOMMU device.
1366 *
1367 * @param pDevIns The IOMMU device instance.
1368 *
1369 * @thread Any.
1370 */
1371static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
1372{
1373 if (iommuAmdIsMsiEnabled(pDevIns))
1374 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
1375}
1376
1377
1378/**
1379 * Clears the MSI interrupt for the IOMMU device.
1380 *
1381 * @param pDevIns The IOMMU device instance.
1382 *
1383 * @thread Any.
1384 */
1385static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
1386{
1387 if (iommuAmdIsMsiEnabled(pDevIns))
1388 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
1389}
1390
1391
1392/**
1393 * Writes an entry to the event log in memory.
1394 *
1395 * @returns VBox status code.
1396 * @param pDevIns The IOMMU device instance.
1397 * @param pEvent The event to log.
1398 *
1399 * @thread Any.
1400 */
1401static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1402{
1403 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1404
1405 IOMMU_ASSERT_LOCKED(pDevIns);
1406
1407 /* Check if event logging is active and the log has not overflowed. */
1408 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1409 if ( Status.n.u1EvtLogRunning
1410 && !Status.n.u1EvtOverflow)
1411 {
1412 uint32_t const cbEvt = sizeof(*pEvent);
1413
1414 /* Get the offset we need to write the event to in memory (circular buffer offset). */
1415 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
1416 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
1417
1418 /* Ensure we have space in the event log. */
1419 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
1420 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
1421 if (cEvts + 1 < cMaxEvts)
1422 {
1423 /* Write the event log entry to memory. */
1424 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
1425 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
1426 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
1427 if (RT_FAILURE(rc))
1428 Log((IOMMU_LOG_PFX ": Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
1429
1430 /* Increment the event log tail pointer. */
1431 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1432 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
1433
1434 /* Indicate that an event log entry was written. */
1435 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
1436
1437 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
1438 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1439 if (Ctrl.n.u1EvtIntrEn)
1440 iommuAmdRaiseMsiInterrupt(pDevIns);
1441 }
1442 else
1443 {
1444 /* Indicate that the event log has overflowed. */
1445 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
1446
1447 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
1448 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1449 if (Ctrl.n.u1EvtIntrEn)
1450 iommuAmdRaiseMsiInterrupt(pDevIns);
1451 }
1452 }
1453
1454 return VINF_SUCCESS;
1455}
1456
1457
1458/**
1459 * Sets an event in the hardware error registers.
1460 *
1461 * @param pDevIns The IOMMU device instance.
1462 * @param pEvent The event.
1463 *
1464 * @thread Any.
1465 */
1466static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1467{
1468 IOMMU_ASSERT_LOCKED(pDevIns);
1469
1470 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1471 if (pThis->ExtFeat.n.u1HwErrorSup)
1472 {
1473 if (pThis->HwEvtStatus.n.u1Valid)
1474 pThis->HwEvtStatus.n.u1Overflow = 1;
1475 pThis->HwEvtStatus.n.u1Valid = 1;
1476 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
1477 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
1478 Assert(pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR);
1479 }
1480}
1481
1482
1483/**
1484 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
1485 *
1486 * @param uDevId The device ID.
1487 * @param uDomainId The domain ID.
1488 * @param GCPhysPtEntity The system physical address of the page table
1489 * entity.
1490 * @param enmOp The IOMMU operation being performed.
1491 * @param pEvtPageTabHwErr Where to store the initialized event.
1492 */
1493static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
1494 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1495{
1496 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
1497 pEvtPageTabHwErr->n.u16DevId = uDevId;
1498 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
1499 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
1500 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1501 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1502 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1503 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1504 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
1505 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
1506}
1507
1508
1509/**
1510 * Raises a PAGE_TAB_HARDWARE_ERROR event.
1511 *
1512 * @param pDevIns The IOMMU device instance.
1513 * @param enmOp The IOMMU operation being performed.
1514 * @param pEvtPageTabHwErr The page table hardware error event.
1515 *
1516 * @thread Any.
1517 */
1518static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1519{
1520 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
1521 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
1522
1523 IOMMU_LOCK_NORET(pDevIns);
1524
1525 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1526 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1527 if (enmOp != IOMMUOP_CMD)
1528 iommuAmdSetPciTargetAbort(pDevIns);
1529
1530 IOMMU_UNLOCK(pDevIns);
1531
1532 Log((IOMMU_LOG_PFX ": Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
1533 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
1534 pEvtPageTabHwErr->n.u2Type));
1535}
1536
1537
1538/**
1539 * Initializes a COMMAND_HARDWARE_ERROR event.
1540 *
1541 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
1542 * @param pEvtCmdHwErr Where to store the initialized event.
1543 */
1544static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1545{
1546 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
1547 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
1548 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
1549 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
1550}
1551
1552
1553/**
1554 * Raises a COMMAND_HARDWARE_ERROR event.
1555 *
1556 * @param pDevIns The IOMMU device instance.
1557 * @param pEvtCmdHwErr The command hardware error event.
1558 *
1559 * @thread Any.
1560 */
1561static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1562{
1563 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
1564 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
1565 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1566
1567 IOMMU_LOCK_NORET(pDevIns);
1568
1569 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1570 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1571 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1572
1573 IOMMU_UNLOCK(pDevIns);
1574
1575 Log((IOMMU_LOG_PFX ": Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr,
1576 pEvtCmdHwErr->n.u2Type));
1577}
1578
1579
1580/**
1581 * Initializes a DEV_TAB_HARDWARE_ERROR event.
1582 *
1583 * @param uDevId The device ID.
1584 * @param GCPhysDte The system physical address of the failed device table
1585 * access.
1586 * @param enmOp The IOMMU operation being performed.
1587 * @param pEvtDevTabHwErr Where to store the initialized event.
1588 */
1589static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
1590 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1591{
1592 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
1593 pEvtDevTabHwErr->n.u16DevId = uDevId;
1594 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1595 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
1596 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1597 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1598 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1599 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
1600 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
1601}
1602
1603
1604/**
1605 * Raises a DEV_TAB_HARDWARE_ERROR event.
1606 *
1607 * @param pDevIns The IOMMU device instance.
1608 * @param enmOp The IOMMU operation being performed.
1609 * @param pEvtDevTabHwErr The device table hardware error event.
1610 *
1611 * @thread Any.
1612 */
1613static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1614{
1615 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
1616 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
1617
1618 IOMMU_LOCK_NORET(pDevIns);
1619
1620 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1621 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1622 if (enmOp != IOMMUOP_CMD)
1623 iommuAmdSetPciTargetAbort(pDevIns);
1624
1625 IOMMU_UNLOCK(pDevIns);
1626
1627 Log((IOMMU_LOG_PFX ": Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n",
1628 pEvtDevTabHwErr->n.u16DevId, pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
1629}
1630
1631
1632/**
1633 * Initializes an ILLEGAL_COMMAND_ERROR event.
1634 *
1635 * @param GCPhysCmd The system physical address of the failed command
1636 * access.
1637 * @param pEvtIllegalCmd Where to store the initialized event.
1638 */
1639static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
1640{
1641 Assert(!(GCPhysCmd & UINT64_C(0xf)));
1642 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
1643 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
1644 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
1645}
1646
1647
1648/**
1649 * Raises an ILLEGAL_COMMAND_ERROR event.
1650 *
1651 * @param pDevIns The IOMMU device instance.
1652 * @param pEvtIllegalCmd The illegal command error event.
1653 */
1654static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
1655{
1656 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
1657 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
1658 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1659
1660 IOMMU_LOCK_NORET(pDevIns);
1661
1662 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1663 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1664
1665 IOMMU_UNLOCK(pDevIns);
1666
1667 Log((IOMMU_LOG_PFX ": Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
1668}
1669
1670
1671/**
1672 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
1673 *
1674 * @param uDevId The device ID.
1675 * @param uIova The I/O virtual address.
1676 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
1677 * event was caused by an invalid level encoding in the
1678 * DTE.
1679 * @param enmOp The IOMMU operation being performed.
1680 * @param pEvtIllegalDte Where to store the initialized event.
1681 */
1682static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
1683 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
1684{
1685 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
1686 pEvtIllegalDte->n.u16DevId = uDevId;
1687 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1688 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1689 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
1690 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1691 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
1692 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
1693 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
1694 * IOMMU spec here but not for this field for I/O page fault event. */
1695 Assert(!(uIova & UINT64_C(0x3)));
1696}
1697
1698
1699/**
1700 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
1701 *
1702 * @param pDevIns The IOMMU instance data.
1703 * @param enmOp The IOMMU operation being performed.
1704 * @param pEvtIllegalDte The illegal device table entry event.
1705 * @param enmEvtType The illegal device table entry event type.
1706 *
1707 * @thread Any.
1708 */
1709static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
1710 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
1711{
1712 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
1713 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
1714
1715 IOMMU_LOCK_NORET(pDevIns);
1716
1717 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1718 if (enmOp != IOMMUOP_CMD)
1719 iommuAmdSetPciTargetAbort(pDevIns);
1720
1721 IOMMU_UNLOCK(pDevIns);
1722
1723 Log((IOMMU_LOG_PFX ": Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
1724 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
1725 NOREF(enmEvtType);
1726}
1727
1728
1729/**
1730 * Initializes an IO_PAGE_FAULT event.
1731 *
1732 * @param uDevId The device ID.
1733 * @param uDomainId The domain ID.
1734 * @param uIova The I/O virtual address being accessed.
1735 * @param fPresent Transaction to a page marked as present (including
1736 * DTE.V=1) or interrupt marked as remapped
1737 * (IRTE.RemapEn=1).
1738 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
1739 * the I/O page fault was caused by invalid level
1740 * encoding.
1741 * @param fPermDenied Permission denied for the address being accessed.
1742 * @param enmOp The IOMMU operation being performed.
1743 * @param pEvtIoPageFault Where to store the initialized event.
1744 */
1745static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
1746 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
1747{
1748 Assert(!fPermDenied || fPresent);
1749 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
1750 pEvtIoPageFault->n.u16DevId = uDevId;
1751 //pEvtIoPageFault->n.u4PasidHi = 0;
1752 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
1753 //pEvtIoPageFault->n.u1GuestOrNested = 0;
1754 //pEvtIoPageFault->n.u1NoExecute = 0;
1755 //pEvtIoPageFault->n.u1User = 0;
1756 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1757 pEvtIoPageFault->n.u1Present = fPresent;
1758 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1759 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
1760 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
1761 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1762 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
1763 pEvtIoPageFault->n.u64Addr = uIova;
1764}
1765
1766
1767/**
1768 * Raises an IO_PAGE_FAULT event.
1769 *
1770 * @param pDevIns The IOMMU instance data.
1771 * @param pDte The device table entry. Optional, can be NULL
1772 * depending on @a enmOp.
1773 * @param pIrte The interrupt remapping table entry. Optional, can
1774 * be NULL depending on @a enmOp.
1775 * @param enmOp The IOMMU operation being performed.
1776 * @param pEvtIoPageFault The I/O page fault event.
1777 * @param enmEvtType The I/O page fault event type.
1778 *
1779 * @thread Any.
1780 */
1781static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
1782 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
1783{
1784 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
1785 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
1786
1787 IOMMU_LOCK_NORET(pDevIns);
1788
1789 bool fSuppressEvtLogging = false;
1790 if ( enmOp == IOMMUOP_MEM_READ
1791 || enmOp == IOMMUOP_MEM_WRITE)
1792 {
1793 if ( pDte
1794 && pDte->n.u1Valid)
1795 {
1796 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
1797 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
1798 * suppression. Perhaps will be possible when we complete IOTLB/cache
1799 * handling. */
1800 }
1801 }
1802 else if (enmOp == IOMMUOP_INTR_REQ)
1803 {
1804 if ( pDte
1805 && pDte->n.u1IntrMapValid)
1806 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
1807
1808 if ( !fSuppressEvtLogging
1809 && pIrte)
1810 fSuppressEvtLogging = pIrte->n.u1SuppressPf;
1811 }
1812 /* else: Events are never suppressed for commands. */
1813
1814 switch (enmEvtType)
1815 {
1816 case kIoPageFaultType_PermDenied:
1817 {
1818 /* Cannot be triggered by a command. */
1819 Assert(enmOp != IOMMUOP_CMD);
1820 RT_FALL_THRU();
1821 }
1822 case kIoPageFaultType_DteRsvdPagingMode:
1823 case kIoPageFaultType_PteInvalidPageSize:
1824 case kIoPageFaultType_PteInvalidLvlEncoding:
1825 case kIoPageFaultType_SkippedLevelIovaNotZero:
1826 case kIoPageFaultType_PteRsvdNotZero:
1827 case kIoPageFaultType_PteValidNotSet:
1828 case kIoPageFaultType_DteTranslationDisabled:
1829 case kIoPageFaultType_PasidInvalidRange:
1830 {
1831 /*
1832 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
1833 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
1834 */
1835 if (enmOp != IOMMUOP_TRANSLATE_REQ)
1836 {
1837 if (!fSuppressEvtLogging)
1838 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1839 if (enmOp != IOMMUOP_CMD)
1840 iommuAmdSetPciTargetAbort(pDevIns);
1841 }
1842 break;
1843 }
1844
1845 case kIoPageFaultType_UserSupervisor:
1846 {
1847 /* Access is blocked and only creates an event log entry. */
1848 if (!fSuppressEvtLogging)
1849 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1850 break;
1851 }
1852
1853 case kIoPageFaultType_IrteAddrInvalid:
1854 case kIoPageFaultType_IrteRsvdNotZero:
1855 case kIoPageFaultType_IrteRemapEn:
1856 case kIoPageFaultType_IrteRsvdIntType:
1857 case kIoPageFaultType_IntrReqAborted:
1858 case kIoPageFaultType_IntrWithPasid:
1859 {
1860 /* Only trigerred by interrupt requests. */
1861 Assert(enmOp == IOMMUOP_INTR_REQ);
1862 if (!fSuppressEvtLogging)
1863 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1864 iommuAmdSetPciTargetAbort(pDevIns);
1865 break;
1866 }
1867
1868 case kIoPageFaultType_SmiFilterMismatch:
1869 {
1870 /* Not supported and probably will never be, assert. */
1871 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
1872 break;
1873 }
1874
1875 case kIoPageFaultType_DevId_Invalid:
1876 {
1877 /* Cannot be triggered by a command. */
1878 Assert(enmOp != IOMMUOP_CMD);
1879 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
1880 if (!fSuppressEvtLogging)
1881 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1882 if ( enmOp == IOMMUOP_MEM_READ
1883 || enmOp == IOMMUOP_MEM_WRITE)
1884 iommuAmdSetPciTargetAbort(pDevIns);
1885 break;
1886 }
1887 }
1888
1889 IOMMU_UNLOCK(pDevIns);
1890}
1891
1892
1893/**
1894 * Returns whether the I/O virtual address is to be excluded from translation and
1895 * permission checks.
1896 *
1897 * @returns @c true if the DVA is excluded, @c false otherwise.
1898 * @param pThis The IOMMU device state.
1899 * @param pDte The device table entry.
1900 * @param uIova The I/O virtual address.
1901 *
1902 * @remarks Ensure the exclusion range is enabled prior to calling this function.
1903 *
1904 * @thread Any.
1905 */
1906static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
1907{
1908 /* Ensure the exclusion range is enabled. */
1909 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
1910
1911 /* Check if the IOVA falls within the exclusion range. */
1912 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
1913 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
1914 if (uIovaExclLast - uIova >= uIovaExclFirst)
1915 {
1916 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
1917 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
1918 || pDte->n.u1AllowExclusion)
1919 return true;
1920 }
1921 return false;
1922}
1923
1924
1925/**
1926 * Reads a device table entry from guest memory given the device ID.
1927 *
1928 * @returns VBox status code.
1929 * @param pDevIns The IOMMU device instance.
1930 * @param uDevId The device ID.
1931 * @param enmOp The IOMMU operation being performed.
1932 * @param pDte Where to store the device table entry.
1933 *
1934 * @thread Any.
1935 */
1936static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
1937{
1938 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1939 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1940
1941 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
1942 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
1943
1944 uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
1945 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1946
1947 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
1948 uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
1949 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
1950
1951 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
1952 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
1953 if (RT_FAILURE(rc))
1954 {
1955 Log((IOMMU_LOG_PFX ": Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
1956
1957 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
1958 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
1959 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
1960 return VERR_IOMMU_IPE_1;
1961 }
1962
1963
1964 return rc;
1965}
1966
1967
1968/**
1969 * Walks the I/O page table to translate the I/O virtual address to a system
1970 * physical address.
1971 *
1972 * @returns VBox status code.
1973 * @param pDevIns The IOMMU device instance.
1974 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
1975 * @param uDevId The device ID.
1976 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
1977 * permissions for the access being made.
1978 * @param pDte The device table entry.
1979 * @param enmOp The IOMMU operation being performed.
1980 * @param pWalkResult Where to store the results of the I/O page walk. This is
1981 * only updated when VINF_SUCCESS is returned.
1982 *
1983 * @thread Any.
1984 */
1985static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
1986 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
1987{
1988 Assert(pDte->n.u1Valid);
1989 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1990
1991 /* If the translation is not valid, raise an I/O page fault. */
1992 if (pDte->n.u1TranslationValid)
1993 { /* likely */ }
1994 else
1995 {
1996 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
1997 * doesn't explicitly say whether an I/O page fault is raised. From other
1998 * places in the spec. it seems early page walk terminations (starting with
1999 * the DTE) return the state computed so far and raises an I/O page fault. So
2000 * returning an invalid translation rather than skipping translation. */
2001 Log((IOMMU_LOG_PFX ": Translation valid bit not set -> IOPF"));
2002 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2003 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2004 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2005 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2006 kIoPageFaultType_DteTranslationDisabled);
2007 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2008 }
2009
2010 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2011 uint8_t const uMaxLevel = pDte->n.u3Mode;
2012 if (uMaxLevel != 0)
2013 { /* likely */ }
2014 else
2015 {
2016 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2017 if ((fAccess & fDtePerm) != fAccess)
2018 {
2019 Log((IOMMU_LOG_PFX ": Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
2020 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2021 }
2022 pWalkResult->GCPhysSpa = uIova;
2023 pWalkResult->cShift = 0;
2024 pWalkResult->fIoPerm = fDtePerm;
2025 return VINF_SUCCESS;
2026 }
2027
2028 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2029 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2030 { /* likely */ }
2031 else
2032 {
2033 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2034 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2035 * I'm just going with I/O page fault. */
2036 Log((IOMMU_LOG_PFX ": Invalid root page table level %#x -> IOPF", uMaxLevel));
2037 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2038 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2039 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2040 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2041 kIoPageFaultType_PteInvalidLvlEncoding);
2042 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2043 }
2044
2045 /* Check permissions bits of the root page table. */
2046 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2047 if ((fAccess & fRootPtePerm) == fAccess)
2048 { /* likely */ }
2049 else
2050 {
2051 Log((IOMMU_LOG_PFX ": Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF", fAccess, fRootPtePerm));
2052 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2053 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2054 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2055 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2056 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2057 }
2058
2059 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2060 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2061 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2062 * table entry every time. Not sure if it's worth optimizing that case now
2063 * or if at all. */
2064
2065 /* The virtual address bits indexing table. */
2066 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2067 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2068 UINT64_C(0x00000000001ff000),
2069 UINT64_C(0x000000003fe00000),
2070 UINT64_C(0x0000007fc0000000),
2071 UINT64_C(0x0000ff8000000000),
2072 UINT64_C(0x01ff000000000000),
2073 UINT64_C(0xfe00000000000000),
2074 UINT64_C(0x0000000000000000) };
2075 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2076 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2077
2078 /* Traverse the I/O page table starting with the page directory in the DTE. */
2079 IOPTENTITY_T PtEntity;
2080 PtEntity.u64 = pDte->au64[0];
2081 for (;;)
2082 {
2083 /* Figure out the system physical address of the page table at the current level. */
2084 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2085
2086 /* Read the page table entity at the current level. */
2087 {
2088 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2089 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2090 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2091 uint64_t const offPte = idxPte << 3;
2092 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2093 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2094 if (RT_FAILURE(rc))
2095 {
2096 Log((IOMMU_LOG_PFX ": Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2097 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2098 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2099 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2100 return VERR_IOMMU_IPE_2;
2101 }
2102 }
2103
2104 /* Check present bit. */
2105 if (PtEntity.n.u1Present)
2106 { /* likely */ }
2107 else
2108 {
2109 Log((IOMMU_LOG_PFX ": Page table entry not present -> IOPF"));
2110 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2111 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2112 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2113 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2114 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2115 }
2116
2117 /* Check permission bits. */
2118 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2119 if ((fAccess & fPtePerm) == fAccess)
2120 { /* likely */ }
2121 else
2122 {
2123 Log((IOMMU_LOG_PFX ": Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF", fAccess, fPtePerm));
2124 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2125 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2126 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2127 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2128 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2129 }
2130
2131 /* If this is a PTE, we're at the final level and we're done. */
2132 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2133 if (uNextLevel == 0)
2134 {
2135 /* The page size of the translation is the default (4K). */
2136 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2137 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2138 pWalkResult->fIoPerm = fPtePerm;
2139 return VINF_SUCCESS;
2140 }
2141 if (uNextLevel == 7)
2142 {
2143 /* The default page size of the translation is overridden. */
2144 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2145 uint8_t cShift = X86_PAGE_4K_SHIFT;
2146 while (GCPhysPte & RT_BIT_64(cShift++))
2147 ;
2148
2149 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2150 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2151 if ( cShift > s_acIovaLevelShifts[uLevel]
2152 && cShift < s_acIovaLevelShifts[uLevel + 1])
2153 {
2154 pWalkResult->GCPhysSpa = GCPhysPte;
2155 pWalkResult->cShift = cShift;
2156 pWalkResult->fIoPerm = fPtePerm;
2157 return VINF_SUCCESS;
2158 }
2159
2160 Log((IOMMU_LOG_PFX ": Page size invalid cShift=%#x -> IOPF", cShift));
2161 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2162 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2163 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2164 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2165 kIoPageFaultType_PteInvalidPageSize);
2166 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2167 }
2168
2169 /* Validate the next level encoding of the PDE. */
2170#if IOMMU_MAX_HOST_PT_LEVEL < 6
2171 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2172 { /* likely */ }
2173 else
2174 {
2175 Log((IOMMU_LOG_PFX ": Next level of PDE invalid uNextLevel=%#x -> IOPF", uNextLevel));
2176 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2177 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2178 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2179 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2180 kIoPageFaultType_PteInvalidLvlEncoding);
2181 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2182 }
2183#else
2184 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2185#endif
2186
2187 /* Validate level transition. */
2188 if (uNextLevel < uLevel)
2189 { /* likely */ }
2190 else
2191 {
2192 Log((IOMMU_LOG_PFX ": Next level (%#x) must be less than the current level (%#x) -> IOPF", uNextLevel, uLevel));
2193 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2194 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2195 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2196 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2197 kIoPageFaultType_PteInvalidLvlEncoding);
2198 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2199 }
2200
2201 /* Ensure IOVA bits of skipped levels are zero. */
2202 Assert(uLevel > 0);
2203 uint64_t uIovaSkipMask = 0;
2204 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2205 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2206 if (!(uIova & uIovaSkipMask))
2207 { /* likely */ }
2208 else
2209 {
2210 Log((IOMMU_LOG_PFX ": IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF", uIova, uIovaSkipMask));
2211 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2212 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2213 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2214 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2215 kIoPageFaultType_SkippedLevelIovaNotZero);
2216 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2217 }
2218
2219 /* Continue with traversing the page directory at this level. */
2220 }
2221}
2222
2223
2224/**
2225 * Looks up an I/O virtual address from the device table.
2226 *
2227 * @returns VBox status code.
2228 * @param pDevIns The IOMMU instance data.
2229 * @param uDevId The device ID.
2230 * @param uIova The I/O virtual address to lookup.
2231 * @param cbAccess The size of the access.
2232 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2233 * permissions for the access being made.
2234 * @param enmOp The IOMMU operation being performed.
2235 * @param pGCPhysSpa Where to store the translated system physical address. Only
2236 * valid when translation succeeds and VINF_SUCCESS is
2237 * returned!
2238 *
2239 * @thread Any.
2240 */
2241static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2242 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2243{
2244 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2245
2246 /* Read the device table entry from memory. */
2247 DTE_T Dte;
2248 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2249 if (RT_SUCCESS(rc))
2250 {
2251 /* If the DTE is not valid, addresses are forwarded without translation */
2252 if (Dte.n.u1Valid)
2253 { /* likely */ }
2254 else
2255 {
2256 /** @todo IOMMU: Add to IOLTB cache. */
2257 *pGCPhysSpa = uIova;
2258 return VINF_SUCCESS;
2259 }
2260
2261 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2262 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2263 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2264 if (RT_LIKELY( !fRsvd0
2265 && !fRsvd1))
2266 { /* likely */ }
2267 else
2268 {
2269 Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2270 EVT_ILLEGAL_DTE_T Event;
2271 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2272 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2273 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2274 }
2275
2276 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2277 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
2278 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2279 { /* likely */ }
2280 else
2281 {
2282 /** @todo IOMMU: Add to IOLTB cache. */
2283 *pGCPhysSpa = uIova;
2284 return VINF_SUCCESS;
2285 }
2286
2287 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
2288 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
2289
2290 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
2291 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2292 uint64_t cbRemaining = cbAccess;
2293 for (;;)
2294 {
2295 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
2296 IOWALKRESULT WalkResult;
2297 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
2298 if (RT_SUCCESS(rc))
2299 {
2300 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
2301
2302 /* Store the translated base address before continuing to check permissions for any more pages. */
2303 if (cbRemaining == cbAccess)
2304 {
2305 RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2306 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2307 }
2308
2309 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
2310 if (cbRemaining > cbPhysPage - offIova)
2311 {
2312 cbRemaining -= (cbPhysPage - offIova);
2313 uBaseIova += cbPhysPage;
2314 offIova = 0;
2315 }
2316 else
2317 break;
2318 }
2319 else
2320 {
2321 Log((IOMMU_LOG_PFX ": I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
2322 uBaseIova, fAccess, rc));
2323 *pGCPhysSpa = NIL_RTGCPHYS;
2324 return rc;
2325 }
2326 }
2327
2328 return rc;
2329 }
2330
2331 Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2332 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2333}
2334
2335
2336/**
2337 * Memory read request from a device.
2338 *
2339 * @returns VBox status code.
2340 * @param pDevIns The IOMMU device instance.
2341 * @param uDevId The device ID (bus, device, function).
2342 * @param uIova The I/O virtual address being read.
2343 * @param cbRead The number of bytes being read.
2344 * @param pGCPhysSpa Where to store the translated system physical address.
2345 *
2346 * @thread Any.
2347 */
2348static DECLCALLBACK(int) iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
2349 PRTGCPHYS pGCPhysSpa)
2350{
2351 /* Validate. */
2352 Assert(pDevIns);
2353 Assert(pGCPhysSpa);
2354 Assert(cbRead > 0);
2355
2356 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2357 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
2358
2359 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2360 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2361 if (Ctrl.n.u1IommuEn)
2362 {
2363 /** @todo IOMMU: IOTLB cache lookup. */
2364
2365 /* Lookup the IOVA from the device table. */
2366 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
2367 }
2368
2369 *pGCPhysSpa = uIova;
2370 return VINF_SUCCESS;
2371}
2372
2373
2374/**
2375 * Memory write request from a device.
2376 *
2377 * @returns VBox status code.
2378 * @param pDevIns The IOMMU device instance.
2379 * @param uDevId The device ID (bus, device, function).
2380 * @param uIova The I/O virtual address being written.
2381 * @param cbWrite The number of bytes being written.
2382 * @param pGCPhysSpa Where to store the translated physical address.
2383 *
2384 * @thread Any.
2385 */
2386static DECLCALLBACK(int) iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
2387 PRTGCPHYS pGCPhysSpa)
2388{
2389 /* Validate. */
2390 Assert(pDevIns);
2391 Assert(pGCPhysSpa);
2392 Assert(cbWrite > 0);
2393
2394 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2395 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
2396
2397 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2398 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2399 if (Ctrl.n.u1IommuEn)
2400 {
2401 /** @todo IOMMU: IOTLB cache lookup. */
2402
2403 /* Lookup the IOVA from the device table. */
2404 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
2405 }
2406
2407 *pGCPhysSpa = uIova;
2408 return VINF_SUCCESS;
2409}
2410
2411
2412/**
2413 * Reads an interrupt remapping table entry from guest memory given its DTE.
2414 *
2415 * @returns VBox status code.
2416 * @param pDevIns The IOMMU device instance.
2417 * @param uDevId The device ID.
2418 * @param pDte The device table entry.
2419 * @param GCPhysIn The source MSI address.
2420 * @param uDataIn The source MSI data.
2421 * @param enmOp The IOMMU operation being performed.
2422 * @param pIrte Where to store the interrupt remapping table entry.
2423 *
2424 * @thread Any.
2425 */
2426static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
2427 IOMMUOP enmOp, PIRTE_T pIrte)
2428{
2429 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
2430 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) << IOMMU_IRTE_SIZE_SHIFT;
2431 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
2432
2433 /* Ensure the IRTE offset is within the specified table size. */
2434 Assert(pDte->n.u4IntrTableLength < 12);
2435 if (offIrte + sizeof(IRTE_T) <= (1U << pDte->n.u4IntrTableLength) << IOMMU_IRTE_SIZE_SHIFT)
2436 { /* likely */ }
2437 else
2438 {
2439 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2440 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
2441 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2442 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2443 kIoPageFaultType_IrteAddrInvalid);
2444 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2445 }
2446
2447 /* Read the IRTE from memory. */
2448 Assert(!(GCPhysIrte & 3));
2449 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
2450 if (RT_SUCCESS(rc))
2451 return VINF_SUCCESS;
2452
2453 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
2454 * situation. Is it an I/O page fault or a device table hardware error?
2455 * There's no interrupt table hardware error event, but it's unclear what
2456 * we should do here. */
2457 Log((IOMMU_LOG_PFX ": Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
2458 return VERR_IOMMU_IPE_4;
2459}
2460
2461
2462/**
2463 * Remap the interrupt using the interrupt remapping table.
2464 *
2465 * @returns VBox status code.
2466 * @param pDevIns The IOMMU instance data.
2467 * @param uDevId The device ID.
2468 * @param pDte The device table entry.
2469 * @param enmOp The IOMMU operation being performed.
2470 * @param pMsiIn The source MSI.
2471 * @param pMsiOut Where to store the remapped MSI.
2472 *
2473 * @thread Any.
2474 */
2475static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
2476 PMSIMSG pMsiOut)
2477{
2478 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
2479
2480 IRTE_T Irte;
2481 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
2482 if (RT_SUCCESS(rc))
2483 {
2484 if (Irte.n.u1RemapEnable)
2485 {
2486 if (!Irte.n.u1GuestMode)
2487 {
2488 if (Irte.n.u3IntrType < VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
2489 {
2490 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
2491 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
2492 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
2493 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
2494
2495 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
2496 pMsiOut->Data.u32 = pMsiIn->Data.u32;
2497 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
2498 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
2499
2500 return VINF_SUCCESS;
2501 }
2502
2503 Log((IOMMU_LOG_PFX ": Interrupt type (%#x) invalid -> IOPF", Irte.n.u3IntrType));
2504 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2505 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2506 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2507 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
2508 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2509 }
2510
2511 Log((IOMMU_LOG_PFX ": Guest mode not supported -> IOPF"));
2512 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2513 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2514 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2515 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
2516 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2517 }
2518
2519 Log((IOMMU_LOG_PFX ": Remapping disabled -> IOPF"));
2520 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2521 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2522 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2523 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
2524 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2525 }
2526
2527 return rc;
2528}
2529
2530
2531/**
2532 * Looks up an MSI interrupt from the interrupt remapping table.
2533 *
2534 * @returns VBox status code.
2535 * @param pDevIns The IOMMU instance data.
2536 * @param uDevId The device ID.
2537 * @param enmOp The IOMMU operation being performed.
2538 * @param pMsiIn The source MSI.
2539 * @param pMsiOut Where to store the remapped MSI.
2540 *
2541 * @thread Any.
2542 */
2543static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2544{
2545 /* Read the device table entry from memory. */
2546 DTE_T Dte;
2547 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2548 if (RT_SUCCESS(rc))
2549 {
2550 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
2551 if (Dte.n.u1IntrMapValid)
2552 {
2553 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
2554 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
2555 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
2556 if (RT_LIKELY( !fRsvd0
2557 && !fRsvd1))
2558 { /* likely */ }
2559 else
2560 {
2561 Log((IOMMU_LOG_PFX ": Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
2562 fRsvd1));
2563 EVT_ILLEGAL_DTE_T Event;
2564 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
2565 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2566 return VERR_IOMMU_INTR_REMAP_FAILED;
2567 }
2568
2569 /*
2570 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
2571 * that's connected through HyperTransport it might be possible; but for us, it
2572 * doesn't seem we need to specially handle these pins.
2573 */
2574
2575 /*
2576 * Validate the MSI source address.
2577 *
2578 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
2579 * CPU is concerned, the MSI region is fixed and we must ensure no other device
2580 * claims the region as I/O space.
2581 *
2582 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
2583 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
2584 * See Intel spec. 10.11.1 "Message Address Register Format".
2585 */
2586 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
2587 {
2588 /*
2589 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
2590 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
2591 */
2592 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
2593 bool fPassThru = false;
2594 switch (u8DeliveryMode)
2595 {
2596 case VBOX_MSI_DELIVERY_MODE_FIXED:
2597 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
2598 {
2599 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
2600 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
2601 {
2602 Log((IOMMU_LOG_PFX ": IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
2603 iommuAmdSetPciTargetAbort(pDevIns);
2604 return VERR_IOMMU_INTR_REMAP_DENIED;
2605 }
2606
2607 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
2608 {
2609 fPassThru = true;
2610 break;
2611 }
2612
2613 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
2614 {
2615 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
2616 uint32_t const uIntTabLen = Dte.n.u4IntrTableLength;
2617 if (Dte.n.u4IntrTableLength < 12)
2618 {
2619 /*
2620 * We don't support guest interrupt remapping yet. When we do, we'll need to
2621 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
2622 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
2623 * already reads the control register, add that as a parameter when we eventually
2624 * support guest interrupt remapping. For now, just assert.
2625 */
2626 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2627 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
2628 NOREF(pThis);
2629
2630 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
2631 }
2632
2633 Log((IOMMU_LOG_PFX ": Invalid interrupt table length %#x -> Illegal DTE\n", uIntTabLen));
2634 EVT_ILLEGAL_DTE_T Event;
2635 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
2636 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
2637 return VERR_IOMMU_INTR_REMAP_FAILED;
2638 }
2639
2640 /* Paranoia. */
2641 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
2642
2643 Log((IOMMU_LOG_PFX ":IntCtl mode invalid %#x -> Illegal DTE", uIntrCtrl));
2644 EVT_ILLEGAL_DTE_T Event;
2645 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
2646 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
2647 return VERR_IOMMU_INTR_REMAP_FAILED;
2648 }
2649
2650 /* SMIs are passed through unmapped. We don't implement SMI filters. */
2651 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
2652 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
2653 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
2654 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
2655 default:
2656 {
2657 Log((IOMMU_LOG_PFX ":MSI data delivery mode invalid %#x -> Target abort", u8DeliveryMode));
2658 iommuAmdSetPciTargetAbort(pDevIns);
2659 return VERR_IOMMU_INTR_REMAP_FAILED;
2660 }
2661 }
2662
2663 if (fPassThru)
2664 {
2665 *pMsiOut = *pMsiIn;
2666 return VINF_SUCCESS;
2667 }
2668
2669 iommuAmdSetPciTargetAbort(pDevIns);
2670 return VERR_IOMMU_INTR_REMAP_DENIED;
2671 }
2672 else
2673 {
2674 Log((IOMMU_LOG_PFX ":MSI address region invalid %#RX64.", pMsiIn->Addr.u64));
2675 return VERR_IOMMU_INTR_REMAP_FAILED;
2676 }
2677 }
2678 else
2679 {
2680 /** @todo IOMMU: Add to interrupt remapping cache. */
2681 *pMsiOut = *pMsiIn;
2682 return VINF_SUCCESS;
2683 }
2684 }
2685
2686 Log((IOMMU_LOG_PFX ": Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2687 return VERR_IOMMU_INTR_REMAP_FAILED;
2688}
2689
2690
2691/**
2692 * Interrupt remap request from a device.
2693 *
2694 * @returns VBox status code.
2695 * @param pDevIns The IOMMU device instance.
2696 * @param uDevId The device ID (bus, device, function).
2697 * @param pMsiIn The source MSI.
2698 * @param pMsiOut Where to store the remapped MSI.
2699 */
2700static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2701{
2702 /* Validate. */
2703 Assert(pDevIns);
2704 Assert(pMsiIn);
2705 Assert(pMsiOut);
2706
2707 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2708 LogFlowFunc(("uDevId=%#x\n", uDevId));
2709
2710 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
2711 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2712 if (Ctrl.n.u1IommuEn)
2713 {
2714 /** @todo Cache? */
2715
2716 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
2717 }
2718
2719 *pMsiOut = *pMsiIn;
2720 return VINF_SUCCESS;
2721}
2722
2723
2724/**
2725 * @callback_method_impl{FNIOMMMIONEWWRITE}
2726 */
2727static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
2728{
2729 NOREF(pvUser);
2730 Assert(cb == 4 || cb == 8);
2731 Assert(!(off & (cb - 1)));
2732
2733 LogFlowFunc(("off=%RGp cb=%u\n", off, cb));
2734
2735 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
2736 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
2737}
2738
2739
2740/**
2741 * @callback_method_impl{FNIOMMMIONEWREAD}
2742 */
2743static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
2744{
2745 NOREF(pvUser);
2746 Assert(cb == 4 || cb == 8);
2747 Assert(!(off & (cb - 1)));
2748
2749 LogFlowFunc(("off=%RGp cb=%u\n", off, cb));
2750
2751 uint64_t uResult;
2752 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
2753 if (cb == 8)
2754 *(uint64_t *)pv = uResult;
2755 else
2756 *(uint32_t *)pv = (uint32_t)uResult;
2757
2758 return rcStrict;
2759}
2760
2761# ifdef IN_RING3
2762
2763/**
2764 * Processes an IOMMU command.
2765 *
2766 * @returns VBox status code.
2767 * @param pDevIns The IOMMU device instance.
2768 * @param pCmd The command to process.
2769 * @param GCPhysCmd The system physical address of the command.
2770 * @param pEvtError Where to store the error event in case of failures.
2771 *
2772 * @thread Command thread.
2773 */
2774static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
2775{
2776 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
2777
2778 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2779 uint8_t const bCmd = pCmd->n.u4Opcode;
2780 switch (bCmd)
2781 {
2782 case IOMMU_CMD_COMPLETION_WAIT:
2783 {
2784 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
2785 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
2786
2787 /* Validate reserved bits in the command. */
2788 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
2789 {
2790 /* If Completion Store is requested, write the StoreData to the specified address.*/
2791 if (pCmdComWait->n.u1Store)
2792 {
2793 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
2794 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
2795 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
2796 if (RT_FAILURE(rc))
2797 {
2798 Log((IOMMU_LOG_PFX ": Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
2799 GCPhysStore, rc));
2800 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
2801 return VERR_IOMMU_CMD_HW_ERROR;
2802 }
2803 }
2804
2805 IOMMU_LOCK(pDevIns);
2806
2807 /* Indicate that this command has completed. */
2808 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
2809
2810 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
2811 if (pCmdComWait->n.u1Interrupt)
2812 {
2813 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2814 if (Ctrl.n.u1CompWaitIntrEn)
2815 iommuAmdRaiseMsiInterrupt(pDevIns);
2816 }
2817
2818 IOMMU_UNLOCK(pDevIns);
2819 return VINF_SUCCESS;
2820 }
2821 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2822 return VERR_IOMMU_CMD_INVALID_FORMAT;
2823 }
2824
2825 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
2826 {
2827 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2828 * then. */
2829 return VINF_SUCCESS;
2830 }
2831
2832 case IOMMU_CMD_INV_IOMMU_PAGES:
2833 {
2834 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2835 * then. */
2836 return VINF_SUCCESS;
2837 }
2838
2839 case IOMMU_CMD_INV_IOTLB_PAGES:
2840 {
2841 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
2842 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
2843 {
2844 /** @todo IOMMU: Implement remote IOTLB invalidation. */
2845 return VERR_NOT_IMPLEMENTED;
2846 }
2847 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2848 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2849 }
2850
2851 case IOMMU_CMD_INV_INTR_TABLE:
2852 {
2853 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2854 * then. */
2855 return VINF_SUCCESS;
2856 }
2857
2858 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
2859 {
2860 if (pThis->ExtFeat.n.u1PrefetchSup)
2861 {
2862 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
2863 return VINF_SUCCESS;
2864 }
2865 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2866 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2867 }
2868
2869 case IOMMU_CMD_COMPLETE_PPR_REQ:
2870 {
2871 /* We don't support PPR requests yet. */
2872 Assert(!pThis->ExtFeat.n.u1PprSup);
2873 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2874 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2875 }
2876
2877 case IOMMU_CMD_INV_IOMMU_ALL:
2878 {
2879 if (pThis->ExtFeat.n.u1InvAllSup)
2880 {
2881 /** @todo IOMMU: Invalidate all. Pretend success until then. */
2882 return VINF_SUCCESS;
2883 }
2884 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2885 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2886 }
2887 }
2888
2889 Log((IOMMU_LOG_PFX ": Cmd(%#x): Unrecognized\n", bCmd));
2890 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2891 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2892}
2893
2894
2895/**
2896 * The IOMMU command thread.
2897 *
2898 * @returns VBox status code.
2899 * @param pDevIns The IOMMU device instance.
2900 * @param pThread The command thread.
2901 */
2902static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2903{
2904 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2905
2906 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2907 return VINF_SUCCESS;
2908
2909 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2910 {
2911 /*
2912 * Sleep perpetually until we are woken up to process commands.
2913 */
2914 {
2915 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
2916 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
2917 if (!fSignaled)
2918 {
2919 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
2920 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
2921 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2922 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2923 break;
2924 LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
2925 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
2926 }
2927 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
2928 }
2929
2930 /*
2931 * Fetch and process IOMMU commands.
2932 */
2933 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
2934 * at a time) and is expensive due to calls to PGM for fetching guest memory.
2935 * We could optimize by fetching a bunch of commands at a time reducing
2936 * number of calls to PGM. In the longer run we could lock the memory and
2937 * mappings and accessing them directly. */
2938 IOMMU_LOCK(pDevIns);
2939
2940 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2941 if (Status.n.u1CmdBufRunning)
2942 {
2943 /* Get the offset we need to read the command from memory (circular buffer offset). */
2944 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2945 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
2946 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
2947 Assert(offHead < cbCmdBuf);
2948 while (offHead != pThis->CmdBufTailPtr.n.off)
2949 {
2950 /* Read the command from memory. */
2951 CMD_GENERIC_T Cmd;
2952 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
2953 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
2954 if (RT_SUCCESS(rc))
2955 {
2956 /* Increment the command buffer head pointer. */
2957 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
2958 pThis->CmdBufHeadPtr.n.off = offHead;
2959
2960 /* Process the fetched command. */
2961 EVT_GENERIC_T EvtError;
2962 IOMMU_UNLOCK(pDevIns);
2963 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
2964 IOMMU_LOCK(pDevIns);
2965 if (RT_FAILURE(rc))
2966 {
2967 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
2968 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
2969 {
2970 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
2971 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
2972 }
2973 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
2974 {
2975 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2976 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
2977 }
2978 break;
2979 }
2980 }
2981 else
2982 {
2983 EVT_CMD_HW_ERR_T EvtCmdHwErr;
2984 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
2985 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
2986 break;
2987 }
2988 }
2989 }
2990
2991 IOMMU_UNLOCK(pDevIns);
2992 }
2993
2994 LogFlow((IOMMU_LOG_PFX ": Command thread terminating\n"));
2995 return VINF_SUCCESS;
2996}
2997
2998
2999/**
3000 * Wakes up the command thread so it can respond to a state change.
3001 *
3002 * @returns VBox status code.
3003 * @param pDevIns The IOMMU device instance.
3004 * @param pThread The command thread.
3005 */
3006static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3007{
3008 RT_NOREF(pThread);
3009 LogFlowFunc(("\n"));
3010 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3011 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3012}
3013
3014
3015/**
3016 * @callback_method_impl{FNPCICONFIGREAD}
3017 */
3018static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3019 unsigned cb, uint32_t *pu32Value)
3020{
3021 LogFlowFunc(("\n"));
3022 /** @todo IOMMU: PCI config read stat counter. */
3023 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3024 Log3((IOMMU_LOG_PFX ": Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
3025 VBOXSTRICTRC_VAL(rcStrict)));
3026 return rcStrict;
3027}
3028
3029
3030/**
3031 * @callback_method_impl{FNPCICONFIGWRITE}
3032 */
3033static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3034 unsigned cb, uint32_t u32Value)
3035{
3036 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3037 LogFlowFunc(("\n"));
3038
3039 /*
3040 * Discard writes to read-only registers that are specific to the IOMMU.
3041 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3042 * See PCI spec. 6.1. "Configuration Space Organization".
3043 */
3044 switch (uAddress)
3045 {
3046 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3047 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3048 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3049 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3050 {
3051 Log((IOMMU_LOG_PFX ": PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3052 return VINF_SUCCESS;
3053 }
3054 }
3055
3056 IOMMU_LOCK(pDevIns);
3057
3058 VBOXSTRICTRC rcStrict = VERR_INVALID_FUNCTION;
3059 switch (uAddress)
3060 {
3061 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3062 {
3063 if (pThis->IommuBar.n.u1Enable)
3064 {
3065 rcStrict = VINF_SUCCESS;
3066 Log((IOMMU_LOG_PFX ": Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3067 break;
3068 }
3069
3070 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3071 if (pThis->IommuBar.n.u1Enable)
3072 {
3073 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE);
3074 Assert(PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio) == NIL_RTGCPHYS);
3075 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3076 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3077 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3078 if (RT_FAILURE(rcStrict))
3079 Log((IOMMU_LOG_PFX ": Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
3080 }
3081 break;
3082 }
3083
3084 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3085 {
3086 if (!pThis->IommuBar.n.u1Enable)
3087 pThis->IommuBar.au32[1] = u32Value;
3088 else
3089 {
3090 rcStrict = VINF_SUCCESS;
3091 Log((IOMMU_LOG_PFX ": Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3092 }
3093 break;
3094 }
3095
3096 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3097 {
3098 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3099 RT_FALL_THRU();
3100 }
3101 default:
3102 {
3103 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3104 break;
3105 }
3106 }
3107
3108 IOMMU_UNLOCK(pDevIns);
3109
3110 Log3((IOMMU_LOG_PFX ": PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
3111 return rcStrict;
3112}
3113
3114
3115/**
3116 * @callback_method_impl{FNDBGFHANDLERDEV}
3117 */
3118static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3119{
3120 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3121 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3122 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3123
3124 LogFlow((IOMMU_LOG_PFX ": iommuAmdR3DbgInfo: pThis=%p pszArgs=%s\n", pThis, pszArgs));
3125 bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
3126
3127 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3128 /* Device Table Base Addresses (all segments). */
3129 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3130 {
3131 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3132 pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
3133 if (fVerbose)
3134 {
3135 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3136 IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
3137 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3138 }
3139 }
3140 /* Command Buffer Base Address Register. */
3141 {
3142 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3143 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3144 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3145 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3146 pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
3147 if (fVerbose)
3148 {
3149 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3150 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3151 cEntries, cbBuffer);
3152 }
3153 }
3154 /* Event Log Base Address Register. */
3155 {
3156 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3157 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3158 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3159 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3160 pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
3161 if (fVerbose)
3162 {
3163 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3164 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3165 cEntries, cbBuffer);
3166 }
3167 }
3168 /* IOMMU Control Register. */
3169 {
3170 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3171 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3172 if (fVerbose)
3173 {
3174 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3175 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3176 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3177 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3178 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3179 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3180 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3181 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3182 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3183 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3184 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3185 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3186 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3187 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3188 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3189 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3190 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3191 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3192 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3193 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3194 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3195 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3196 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3197 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3198 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3199 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3200 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3201 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3202 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3203 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3204 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3205 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3206 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3207 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3208 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3209 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3210 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3211 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3212 }
3213 }
3214 /* Exclusion Base Address Register. */
3215 {
3216 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3217 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3218 if (fVerbose)
3219 {
3220 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3221 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3222 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
3223 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
3224 }
3225 }
3226 /* Exclusion Range Limit Register. */
3227 {
3228 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3229 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3230 if (fVerbose)
3231 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
3232 }
3233 /* Extended Feature Register. */
3234 {
3235 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3236 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3237 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3238 if (fVerbose)
3239 {
3240 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3241 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3242 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3243 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3244 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3245 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3246 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3247 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3248 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3249 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3250 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3251 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3252 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3253 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3254 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3255 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3256 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3257 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3258 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
3259 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
3260 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3261 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3262 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3263 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3264 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3265 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3266 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3267 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3268 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3269 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3270 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3271 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3272 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3273 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3274 }
3275 }
3276 /* PPR Log Base Address Register. */
3277 {
3278 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3279 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
3280 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3281 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3282 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3283 if (fVerbose)
3284 {
3285 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3286 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3287 cEntries, cbBuffer);
3288 }
3289 }
3290 /* Hardware Event (Hi) Register. */
3291 {
3292 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
3293 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
3294 if (fVerbose)
3295 {
3296 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
3297 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
3298 }
3299 }
3300 /* Hardware Event (Lo) Register. */
3301 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
3302 /* Hardware Event Status. */
3303 {
3304 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
3305 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
3306 if (fVerbose)
3307 {
3308 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
3309 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
3310 }
3311 }
3312 /* Guest Virtual-APIC Log Base Address Register. */
3313 {
3314 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
3315 uint8_t const uEncodedLen = GALogBar.n.u4Len;
3316 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3317 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3318 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
3319 if (fVerbose)
3320 {
3321 pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3322 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3323 cEntries, cbBuffer);
3324 }
3325 }
3326 /* Guest Virtual-APIC Log Tail Address Register. */
3327 {
3328 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
3329 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
3330 if (fVerbose)
3331 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
3332 }
3333 /* PPR Log B Base Address Register. */
3334 {
3335 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
3336 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
3337 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3338 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3339 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
3340 if (fVerbose)
3341 {
3342 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3343 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3344 cEntries, cbBuffer);
3345 }
3346 }
3347 /* Event Log B Base Address Register. */
3348 {
3349 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
3350 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
3351 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3352 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3353 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
3354 if (fVerbose)
3355 {
3356 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3357 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3358 cEntries, cbBuffer);
3359 }
3360 }
3361 /* Device-Specific Feature Extension Register. */
3362 {
3363 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
3364 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
3365 if (fVerbose)
3366 {
3367 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
3368 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
3369 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
3370 }
3371 }
3372 /* Device-Specific Control Extension Register. */
3373 {
3374 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
3375 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
3376 if (fVerbose)
3377 {
3378 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
3379 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
3380 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
3381 }
3382 }
3383 /* Device-Specific Status Extension Register. */
3384 {
3385 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
3386 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
3387 if (fVerbose)
3388 {
3389 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
3390 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
3391 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
3392 }
3393 }
3394 /* Miscellaneous Information Register (Lo and Hi). */
3395 {
3396 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
3397 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
3398 if (fVerbose)
3399 {
3400 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
3401 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
3402 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
3403 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
3404 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
3405 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
3406 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
3407 }
3408 }
3409 /* MSI Capability Header. */
3410 {
3411 MSI_CAP_HDR_T MsiCapHdr;
3412 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3413 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
3414 if (fVerbose)
3415 {
3416 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
3417 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
3418 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
3419 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
3420 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
3421 }
3422 }
3423 /* MSI Address Register (Lo and Hi). */
3424 {
3425 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3426 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3427 MSIADDR MsiAddr;
3428 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
3429 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
3430 if (fVerbose)
3431 {
3432 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
3433 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
3434 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
3435 pHlp->pfnPrintf(pHlp, " Address = %#Rx32\n", MsiAddr.n.u12Addr);
3436 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#Rx32\n", MsiAddr.n.u32Rsvd0);
3437 }
3438 }
3439 /* MSI Data. */
3440 {
3441 MSIDATA MsiData;
3442 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3443 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
3444 if (fVerbose)
3445 {
3446 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
3447 MsiData.n.u8Vector);
3448 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
3449 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
3450 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
3451 "level" : "edge");
3452 }
3453 }
3454 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
3455 {
3456 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
3457 MsiMapCapHdr.u32 = 0;
3458 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
3459 if (fVerbose)
3460 {
3461 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
3462 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
3463 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
3464 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
3465 }
3466 }
3467 /* Performance Optimization Control Register. */
3468 {
3469 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
3470 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
3471 if (fVerbose)
3472 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
3473 }
3474 /* XT (x2APIC) General Interrupt Control Register. */
3475 {
3476 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
3477 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
3478 if (fVerbose)
3479 {
3480 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3481 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3482 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3483 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
3484 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
3485 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3486 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3487 }
3488 }
3489 /* XT (x2APIC) PPR Interrupt Control Register. */
3490 {
3491 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
3492 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
3493 if (fVerbose)
3494 {
3495 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3496 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3497 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3498 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
3499 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
3500 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3501 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3502 }
3503 }
3504 /* XT (X2APIC) GA Log Interrupt Control Register. */
3505 {
3506 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
3507 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
3508 if (fVerbose)
3509 {
3510 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3511 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3512 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3513 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
3514 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
3515 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3516 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3517 }
3518 }
3519 /* MARC Registers. */
3520 {
3521 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
3522 {
3523 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
3524 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
3525 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
3526
3527 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
3528 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
3529 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
3530 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
3531
3532 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
3533 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
3534 }
3535 }
3536 /* Reserved Register. */
3537 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
3538 /* Command Buffer Head Pointer Register. */
3539 {
3540 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
3541 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
3542 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
3543 }
3544 /* Command Buffer Tail Pointer Register. */
3545 {
3546 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
3547 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
3548 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
3549 }
3550 /* Event Log Head Pointer Register. */
3551 {
3552 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
3553 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
3554 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
3555 }
3556 /* Event Log Tail Pointer Register. */
3557 {
3558 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
3559 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
3560 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
3561 }
3562 /* Status Register. */
3563 {
3564 IOMMU_STATUS_T const Status = pThis->Status;
3565 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
3566 if (fVerbose)
3567 {
3568 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
3569 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
3570 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
3571 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
3572 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
3573 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
3574 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
3575 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
3576 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
3577 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
3578 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
3579 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
3580 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
3581 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
3582 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
3583 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
3584 }
3585 }
3586 /* PPR Log Head Pointer. */
3587 {
3588 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
3589 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
3590 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
3591 }
3592 /* PPR Log Tail Pointer. */
3593 {
3594 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
3595 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
3596 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
3597 }
3598 /* Guest Virtual-APIC Log Head Pointer. */
3599 {
3600 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
3601 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
3602 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
3603 }
3604 /* Guest Virtual-APIC Log Tail Pointer. */
3605 {
3606 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
3607 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
3608 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
3609 }
3610 /* PPR Log B Head Pointer. */
3611 {
3612 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
3613 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
3614 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
3615 }
3616 /* PPR Log B Tail Pointer. */
3617 {
3618 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
3619 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
3620 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
3621 }
3622 /* Event Log B Head Pointer. */
3623 {
3624 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
3625 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
3626 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
3627 }
3628 /* Event Log B Tail Pointer. */
3629 {
3630 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
3631 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
3632 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
3633 }
3634 /* PPR Log Auto Response Register. */
3635 {
3636 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
3637 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
3638 if (fVerbose)
3639 {
3640 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
3641 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
3642 }
3643 }
3644 /* PPR Log Overflow Early Warning Indicator Register. */
3645 {
3646 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
3647 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
3648 if (fVerbose)
3649 {
3650 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
3651 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
3652 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
3653 }
3654 }
3655 /* PPR Log Overflow Early Warning Indicator Register. */
3656 {
3657 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
3658 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
3659 if (fVerbose)
3660 {
3661 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
3662 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
3663 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
3664 }
3665 }
3666}
3667
3668
3669/**
3670 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3671 */
3672static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3673{
3674 /** @todo IOMMU: Save state. */
3675 RT_NOREF2(pDevIns, pSSM);
3676 LogFlowFunc(("\n"));
3677 return VERR_NOT_IMPLEMENTED;
3678}
3679
3680
3681/**
3682 * @callback_method_impl{FNSSMDEVLOADEXEC}
3683 */
3684static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3685{
3686 /** @todo IOMMU: Load state. */
3687 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
3688 LogFlowFunc(("\n"));
3689 return VERR_NOT_IMPLEMENTED;
3690}
3691
3692
3693/**
3694 * @interface_method_impl{PDMDEVREG,pfnReset}
3695 */
3696static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
3697{
3698 /*
3699 * Resets read-write portion of the IOMMU state.
3700 *
3701 * State data not initialized here is expected to be initialized during
3702 * device construction and remain read-only through the lifetime of the VM.
3703 */
3704 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3705 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3706 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3707
3708 LogFlowFunc(("\n"));
3709
3710 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
3711
3712 pThis->CmdBufBaseAddr.u64 = 0;
3713 pThis->CmdBufBaseAddr.n.u4Len = 8;
3714
3715 pThis->EvtLogBaseAddr.u64 = 0;
3716 pThis->EvtLogBaseAddr.n.u4Len = 8;
3717
3718 pThis->Ctrl.u64 = 0;
3719
3720 pThis->ExclRangeBaseAddr.u64 = 0;
3721 pThis->ExclRangeLimit.u64 = 0;
3722
3723 pThis->PprLogBaseAddr.u64 = 0;
3724 pThis->PprLogBaseAddr.n.u4Len = 8;
3725
3726 pThis->HwEvtHi.u64 = 0;
3727 pThis->HwEvtLo = 0;
3728 pThis->HwEvtStatus.u64 = 0;
3729
3730 pThis->GALogBaseAddr.u64 = 0;
3731 pThis->GALogBaseAddr.n.u4Len = 8;
3732 pThis->GALogTailAddr.u64 = 0;
3733
3734 pThis->PprLogBBaseAddr.u64 = 0;
3735 pThis->PprLogBBaseAddr.n.u4Len = 8;
3736
3737 pThis->EvtLogBBaseAddr.u64 = 0;
3738 pThis->EvtLogBBaseAddr.n.u4Len = 8;
3739
3740 pThis->PerfOptCtrl.u32 = 0;
3741
3742 pThis->XtGenIntrCtrl.u64 = 0;
3743 pThis->XtPprIntrCtrl.u64 = 0;
3744 pThis->XtGALogIntrCtrl.u64 = 0;
3745
3746 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
3747
3748 pThis->CmdBufHeadPtr.u64 = 0;
3749 pThis->CmdBufTailPtr.u64 = 0;
3750 pThis->EvtLogHeadPtr.u64 = 0;
3751 pThis->EvtLogTailPtr.u64 = 0;
3752
3753 pThis->Status.u64 = 0;
3754
3755 pThis->PprLogHeadPtr.u64 = 0;
3756 pThis->PprLogTailPtr.u64 = 0;
3757
3758 pThis->GALogHeadPtr.u64 = 0;
3759 pThis->GALogTailPtr.u64 = 0;
3760
3761 pThis->PprLogBHeadPtr.u64 = 0;
3762 pThis->PprLogBTailPtr.u64 = 0;
3763
3764 pThis->EvtLogBHeadPtr.u64 = 0;
3765 pThis->EvtLogBTailPtr.u64 = 0;
3766
3767 pThis->PprLogAutoResp.u64 = 0;
3768 pThis->PprLogOverflowEarly.u64 = 0;
3769 pThis->PprLogBOverflowEarly.u64 = 0;
3770
3771 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
3772 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
3773
3774 /*
3775 * I ASSUME all MMIO regions mapped by a PDM device are automatically unmapped
3776 * on VM reset. If not, we need to enable the following...
3777 */
3778#if 0
3779 /* Unmap the MMIO region on reset if it has been mapped previously. */
3780 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE);
3781 if (PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio) != NIL_RTGCPHYS)
3782 PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3783#endif
3784}
3785
3786
3787/**
3788 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3789 */
3790static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
3791{
3792 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3793 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3794 LogFlowFunc(("\n"));
3795
3796 /* Close the command thread semaphore. */
3797 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
3798 {
3799 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
3800 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
3801 }
3802 return VINF_SUCCESS;
3803}
3804
3805
3806/**
3807 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3808 */
3809static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3810{
3811 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3812 RT_NOREF(pCfg);
3813
3814 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3815 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3816 pThisCC->pDevInsR3 = pDevIns;
3817
3818 LogFlowFunc(("iInstance=%d\n", iInstance));
3819
3820 /*
3821 * Register the IOMMU with PDM.
3822 */
3823 PDMIOMMUREGR3 IommuReg;
3824 RT_ZERO(IommuReg);
3825 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3826 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
3827 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
3828 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
3829 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3830 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3831 if (RT_FAILURE(rc))
3832 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3833 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3834 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3835 N_("IOMMU helper version mismatch; got %#x expected %#x"),
3836 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3837 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3838 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3839 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3840 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3841
3842 /*
3843 * Initialize read-only PCI configuration space.
3844 */
3845 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3846 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3847
3848 /* Header. */
3849 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
3850 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
3851 PDMPciDevSetCommand(pPciDev, 0); /* Command */
3852 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
3853 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3854 PDMPciDevSetClassBase(pPciDev, 0x08); /* System Base Peripheral */
3855 PDMPciDevSetClassSub(pPciDev, 0x06); /* IOMMU */
3856 PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
3857 PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
3858 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
3859 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
3860 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
3861 PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
3862 PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
3863
3864 /* Capability Header. */
3865 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
3866 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
3867 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
3868 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
3869 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
3870 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
3871 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
3872 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
3873 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
3874 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
3875 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
3876
3877 /* Base Address Low Register. */
3878 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
3879
3880 /* Base Address High Register. */
3881 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
3882
3883 /* IOMMU Range Register. */
3884 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
3885
3886 /* Misc. Information Register. */
3887 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
3888 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
3889 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
3890 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
3891 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
3892 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
3893 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
3894 uint32_t const uMiscInfoReg1 = 0;
3895 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
3896 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
3897
3898 /* MSI Capability Header register. */
3899 PDMMSIREG MsiReg;
3900 RT_ZERO(MsiReg);
3901 MsiReg.cMsiVectors = 1;
3902 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
3903 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
3904 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
3905
3906 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
3907#if 0
3908 /* MSI Address Lo. */
3909 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
3910 /* MSI Address Hi. */
3911 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
3912 /* MSI Data. */
3913 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
3914#endif
3915
3916#if 0
3917 /** @todo IOMMU: I don't know if we need to support this, enable later if
3918 * required. */
3919 /* MSI Mapping Capability Header register. */
3920 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
3921 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
3922 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
3923 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
3924 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
3925 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
3926 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
3927#endif
3928
3929 /*
3930 * Register the PCI function with PDM.
3931 */
3932 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3933 AssertLogRelRCReturn(rc, rc);
3934
3935 /*
3936 * Register MSI support for the PCI device.
3937 * This must be done -after- register it as a PCI device!
3938 */
3939 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3940 AssertRCReturn(rc, rc);
3941
3942 /*
3943 * Intercept PCI config. space accesses.
3944 */
3945 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
3946 AssertLogRelRCReturn(rc, rc);
3947
3948 /*
3949 * Create the MMIO region.
3950 * Mapping of the region is done when software configures it via PCI config space.
3951 */
3952 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
3953 NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
3954 "AMD-IOMMU", &pThis->hMmio);
3955 AssertLogRelRCReturn(rc, rc);
3956
3957 /*
3958 * Register saved state.
3959 */
3960 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
3961 NULL, NULL, NULL,
3962 NULL, iommuAmdR3SaveExec, NULL,
3963 NULL, iommuAmdR3LoadExec, NULL);
3964 AssertLogRelRCReturn(rc, rc);
3965
3966 /*
3967 * Register debugger info item.
3968 */
3969 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
3970 AssertLogRelRCReturn(rc, rc);
3971
3972 /*
3973 * Create the command thread and its event semaphore.
3974 */
3975 char szDevIommu[64];
3976 RT_ZERO(szDevIommu);
3977 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
3978 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
3979 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
3980 AssertLogRelRCReturn(rc, rc);
3981
3982 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
3983 AssertLogRelRCReturn(rc, rc);
3984
3985 /*
3986 * Initialize read-only registers.
3987 * NOTE! Fields here must match their corresponding field in the ACPI tables.
3988 */
3989 /** @todo Don't remove the =0 assignment for now. It's just there so it's easier
3990 * for me to see existing features that we might want to implement. Do it
3991 * later. */
3992 pThis->ExtFeat.u64 = 0;
3993 pThis->ExtFeat.n.u1PrefetchSup = 0;
3994 pThis->ExtFeat.n.u1PprSup = 0;
3995 pThis->ExtFeat.n.u1X2ApicSup = 0;
3996 pThis->ExtFeat.n.u1NoExecuteSup = 0;
3997 pThis->ExtFeat.n.u1GstTranslateSup = 0;
3998 pThis->ExtFeat.n.u1InvAllSup = 0;
3999 pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4000 pThis->ExtFeat.n.u1HwErrorSup = 1;
4001 pThis->ExtFeat.n.u1PerfCounterSup = 0;
4002 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4003 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4004 pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
4005 pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
4006 pThis->ExtFeat.n.u2SmiFilterSup = 0;
4007 pThis->ExtFeat.n.u3SmiFilterCount = 0;
4008 pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
4009 pThis->ExtFeat.n.u2DualPprLogSup = 0;
4010 pThis->ExtFeat.n.u2DualEvtLogSup = 0;
4011 pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
4012 pThis->ExtFeat.n.u1UserSupervisorSup = 0;
4013 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
4014 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
4015 pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
4016 pThis->ExtFeat.n.u1PprAutoRespSup = 0;
4017 pThis->ExtFeat.n.u2MarcSup = 0;
4018 pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
4019 pThis->ExtFeat.n.u1PerfOptSup = 0;
4020 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
4021 pThis->ExtFeat.n.u1GstIoSup = 0;
4022 pThis->ExtFeat.n.u1HostAccessSup = 0;
4023 pThis->ExtFeat.n.u1EnhancedPprSup = 0;
4024 pThis->ExtFeat.n.u1AttrForwardSup = 0;
4025 pThis->ExtFeat.n.u1HostDirtySup = 0;
4026 pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
4027 pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
4028 pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
4029
4030 pThis->RsvdReg = 0;
4031
4032 pThis->DevSpecificFeat.u64 = 0;
4033 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
4034 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
4035
4036 pThis->DevSpecificCtrl.u64 = 0;
4037 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
4038 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
4039
4040 pThis->DevSpecificStatus.u64 = 0;
4041 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
4042 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
4043
4044 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
4045
4046 /*
4047 * Initialize parts of the IOMMU state as it would during reset.
4048 * Must be called -after- initializing PCI config. space registers.
4049 */
4050 iommuAmdR3Reset(pDevIns);
4051
4052 return VINF_SUCCESS;
4053}
4054
4055# else /* !IN_RING3 */
4056
4057/**
4058 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4059 */
4060static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
4061{
4062 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4063 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4064 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4065
4066 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4067
4068 /* Set up the MMIO RZ handlers. */
4069 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
4070 AssertRCReturn(rc, rc);
4071
4072 /* Set up the IOMMU RZ callbacks. */
4073 PDMIOMMUREGCC IommuReg;
4074 RT_ZERO(IommuReg);
4075 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4076 IommuReg.idxIommu = pThis->idxIommu;
4077 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4078 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4079 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4080 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4081 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4082 AssertRCReturn(rc, rc);
4083
4084 return VINF_SUCCESS;
4085}
4086
4087# endif /* !IN_RING3 */
4088
4089/**
4090 * The device registration structure.
4091 */
4092const PDMDEVREG g_DeviceIommuAmd =
4093{
4094 /* .u32Version = */ PDM_DEVREG_VERSION,
4095 /* .uReserved0 = */ 0,
4096 /* .szName = */ "iommu-amd",
4097 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4098 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4099 /* .cMaxInstances = */ ~0U,
4100 /* .uSharedVersion = */ 42,
4101 /* .cbInstanceShared = */ sizeof(IOMMU),
4102 /* .cbInstanceCC = */ sizeof(IOMMUCC),
4103 /* .cbInstanceRC = */ sizeof(IOMMURC),
4104 /* .cMaxPciDevices = */ 1,
4105 /* .cMaxMsixVectors = */ 0,
4106 /* .pszDescription = */ "IOMMU (AMD)",
4107#if defined(IN_RING3)
4108 /* .pszRCMod = */ "VBoxDDRC.rc",
4109 /* .pszR0Mod = */ "VBoxDDR0.r0",
4110 /* .pfnConstruct = */ iommuAmdR3Construct,
4111 /* .pfnDestruct = */ iommuAmdR3Destruct,
4112 /* .pfnRelocate = */ NULL,
4113 /* .pfnMemSetup = */ NULL,
4114 /* .pfnPowerOn = */ NULL,
4115 /* .pfnReset = */ iommuAmdR3Reset,
4116 /* .pfnSuspend = */ NULL,
4117 /* .pfnResume = */ NULL,
4118 /* .pfnAttach = */ NULL,
4119 /* .pfnDetach = */ NULL,
4120 /* .pfnQueryInterface = */ NULL,
4121 /* .pfnInitComplete = */ NULL,
4122 /* .pfnPowerOff = */ NULL,
4123 /* .pfnSoftReset = */ NULL,
4124 /* .pfnReserved0 = */ NULL,
4125 /* .pfnReserved1 = */ NULL,
4126 /* .pfnReserved2 = */ NULL,
4127 /* .pfnReserved3 = */ NULL,
4128 /* .pfnReserved4 = */ NULL,
4129 /* .pfnReserved5 = */ NULL,
4130 /* .pfnReserved6 = */ NULL,
4131 /* .pfnReserved7 = */ NULL,
4132#elif defined(IN_RING0)
4133 /* .pfnEarlyConstruct = */ NULL,
4134 /* .pfnConstruct = */ iommuAmdRZConstruct,
4135 /* .pfnDestruct = */ NULL,
4136 /* .pfnFinalDestruct = */ NULL,
4137 /* .pfnRequest = */ NULL,
4138 /* .pfnReserved0 = */ NULL,
4139 /* .pfnReserved1 = */ NULL,
4140 /* .pfnReserved2 = */ NULL,
4141 /* .pfnReserved3 = */ NULL,
4142 /* .pfnReserved4 = */ NULL,
4143 /* .pfnReserved5 = */ NULL,
4144 /* .pfnReserved6 = */ NULL,
4145 /* .pfnReserved7 = */ NULL,
4146#elif defined(IN_RC)
4147 /* .pfnConstruct = */ iommuAmdRZConstruct,
4148 /* .pfnReserved0 = */ NULL,
4149 /* .pfnReserved1 = */ NULL,
4150 /* .pfnReserved2 = */ NULL,
4151 /* .pfnReserved3 = */ NULL,
4152 /* .pfnReserved4 = */ NULL,
4153 /* .pfnReserved5 = */ NULL,
4154 /* .pfnReserved6 = */ NULL,
4155 /* .pfnReserved7 = */ NULL,
4156#else
4157# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4158#endif
4159 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4160};
4161
4162#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4163
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