VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 85988

Last change on this file since 85988 was 85988, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Fix bit transitions to enable command-buffer and event logging in the control register. Fixed assertion.
Enable bus master bit as the virtual IOMMU writes to guest memory.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 178.5 KB
Line 
1/* $Id: DevIommuAmd.cpp 85988 2020-09-02 07:12:44Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/string.h>
30
31#include "VBoxDD.h"
32#include "DevIommuAmd.h"
33
34
35/*********************************************************************************************************************************
36* Defined Constants And Macros *
37*********************************************************************************************************************************/
38/** Release log prefix string. */
39#define IOMMU_LOG_PFX "IOMMU-AMD"
40/** The current saved state version. */
41#define IOMMU_SAVED_STATE_VERSION 1
42/** The IOTLB entry magic. */
43#define IOMMU_IOTLBE_MAGIC 0x10acce55
44
45
46/*********************************************************************************************************************************
47* Structures and Typedefs *
48*********************************************************************************************************************************/
49/**
50 * Acquires the IOMMU PDM lock.
51 * This will make a long jump to ring-3 to acquire the lock if necessary.
52 */
53#define IOMMU_LOCK(a_pDevIns) \
54 do { \
55 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
56 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
57 { /* likely */ } \
58 else \
59 return rcLock; \
60 } while (0)
61
62/**
63 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
64 * This will make a long jump to ring-3 to acquire the lock if necessary.
65 */
66#define IOMMU_LOCK_NORET(a_pDevIns) \
67 do { \
68 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
69 AssertRC(rcLock); \
70 } while (0)
71
72/**
73 * Releases the IOMMU PDM lock.
74 */
75#define IOMMU_UNLOCK(a_pDevIns) \
76 do { \
77 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
78 } while (0)
79
80/**
81 * Asserts that the critsect is owned by this thread.
82 */
83#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
84 do { \
85 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
86 } while (0)
87
88/**
89 * Asserts that the critsect is not owned by this thread.
90 */
91#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
92 do { \
93 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
94 } while (0)
95
96/**
97 * IOMMU operations (transaction) types.
98 */
99typedef enum IOMMUOP
100{
101 /** Address translation request. */
102 IOMMUOP_TRANSLATE_REQ = 0,
103 /** Memory read request. */
104 IOMMUOP_MEM_READ,
105 /** Memory write request. */
106 IOMMUOP_MEM_WRITE,
107 /** Interrupt request. */
108 IOMMUOP_INTR_REQ,
109 /** Command. */
110 IOMMUOP_CMD
111} IOMMUOP;
112AssertCompileSize(IOMMUOP, 4);
113
114/**
115 * I/O page walk result.
116 */
117typedef struct
118{
119 /** The translated system physical address. */
120 RTGCPHYS GCPhysSpa;
121 /** The number of offset bits in the system physical address. */
122 uint8_t cShift;
123 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
124 uint8_t fIoPerm;
125 /** Padding. */
126 uint8_t abPadding[2];
127} IOWALKRESULT;
128/** Pointer to an I/O walk result struct. */
129typedef IOWALKRESULT *PIOWALKRESULT;
130/** Pointer to a const I/O walk result struct. */
131typedef IOWALKRESULT *PCIOWALKRESULT;
132
133/**
134 * IOMMU I/O TLB Entry.
135 * Keep this as small and aligned as possible.
136 */
137typedef struct
138{
139 /** The translated system physical address (SPA) of the page. */
140 RTGCPHYS GCPhysSpa;
141 /** The index of the 4K page within a large page. */
142 uint32_t idxSubPage;
143 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
144 uint8_t fIoPerm;
145 /** The number of offset bits in the translation indicating page size. */
146 uint8_t cShift;
147 /** Alignment padding. */
148 uint8_t afPadding[2];
149} IOTLBE_T;
150AssertCompileSize(IOTLBE_T, 16);
151/** Pointer to an IOMMU I/O TLB entry struct. */
152typedef IOTLBE_T *PIOTLBE_T;
153/** Pointer to a const IOMMU I/O TLB entry struct. */
154typedef IOTLBE_T const *PCIOTLBE_T;
155
156/**
157 * The shared IOMMU device state.
158 */
159typedef struct IOMMU
160{
161 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
162 uint32_t idxIommu;
163 /** Alignment padding. */
164 uint32_t uPadding0;
165
166 /** Whether the command thread is sleeping. */
167 bool volatile fCmdThreadSleeping;
168 /** Alignment padding. */
169 uint8_t afPadding0[3];
170 /** Whether the command thread has been signaled for wake up. */
171 bool volatile fCmdThreadSignaled;
172 /** Alignment padding. */
173 uint8_t afPadding1[3];
174
175 /** The event semaphore the command thread waits on. */
176 SUPSEMEVENT hEvtCmdThread;
177 /** The MMIO handle. */
178 IOMMMIOHANDLE hMmio;
179
180 /** @name PCI: Base capability block registers.
181 * @{ */
182 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
183 /** @} */
184
185 /** @name MMIO: Control and status registers.
186 * @{ */
187 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
188 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
189 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
190 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
191 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
192 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
193 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
194 /** @} */
195
196 /** @name MMIO: PPR Log registers.
197 * @{ */
198 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
199 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
200 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
201 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
202 /** @} */
203
204 /** @todo IOMMU: SMI filter. */
205
206 /** @name MMIO: Guest Virtual-APIC Log registers.
207 * @{ */
208 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
209 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
210 /** @} */
211
212 /** @name MMIO: Alternate PPR and Event Log registers.
213 * @{ */
214 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
215 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
216 /** @} */
217
218 /** @name MMIO: Device-specific feature registers.
219 * @{ */
220 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
221 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
222 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
223 /** @} */
224
225 /** @name MMIO: MSI Capability Block registers.
226 * @{ */
227 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
228 /** @} */
229
230 /** @name MMIO: Performance Optimization Control registers.
231 * @{ */
232 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
233 /** @} */
234
235 /** @name MMIO: x2APIC Control registers.
236 * @{ */
237 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
238 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
239 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
240 /** @} */
241
242 /** @name MMIO: MARC registers.
243 * @{ */
244 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
245 /** @} */
246
247 /** @name MMIO: Reserved register.
248 * @{ */
249 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
250 /** @} */
251
252 /** @name MMIO: Command and Event Log pointer registers.
253 * @{ */
254 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
255 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
256 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
257 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
258 /** @} */
259
260 /** @name MMIO: Command and Event Status register.
261 * @{ */
262 IOMMU_STATUS_T Status; /**< IOMMU status register. */
263 /** @} */
264
265 /** @name MMIO: PPR Log Head and Tail pointer registers.
266 * @{ */
267 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
268 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
269 /** @} */
270
271 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
272 * @{ */
273 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
274 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
275 /** @} */
276
277 /** @name MMIO: PPR Log B Head and Tail pointer registers.
278 * @{ */
279 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
280 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
281 /** @} */
282
283 /** @name MMIO: Event Log B Head and Tail pointer registers.
284 * @{ */
285 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
286 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
287 /** @} */
288
289 /** @name MMIO: PPR Log Overflow protection registers.
290 * @{ */
291 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
292 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
293 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
294 /** @} */
295
296 /** @todo IOMMU: IOMMU Event counter registers. */
297
298 /** @todo IOMMU: Stat counters. */
299} IOMMU;
300/** Pointer to the IOMMU device state. */
301typedef struct IOMMU *PIOMMU;
302/** Pointer to the const IOMMU device state. */
303typedef const struct IOMMU *PCIOMMU;
304AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
305AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
306AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
307AssertCompileMemberAlignment(IOMMU, hMmio, 8);
308AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
309
310/**
311 * The ring-3 IOMMU device state.
312 */
313typedef struct IOMMUR3
314{
315 /** Device instance. */
316 PPDMDEVINSR3 pDevInsR3;
317 /** The IOMMU helpers. */
318 PCPDMIOMMUHLPR3 pIommuHlpR3;
319 /** The command thread handle. */
320 R3PTRTYPE(PPDMTHREAD) pCmdThread;
321} IOMMUR3;
322/** Pointer to the ring-3 IOMMU device state. */
323typedef IOMMUR3 *PIOMMUR3;
324
325/**
326 * The ring-0 IOMMU device state.
327 */
328typedef struct IOMMUR0
329{
330 /** Device instance. */
331 PPDMDEVINSR0 pDevInsR0;
332 /** The IOMMU helpers. */
333 PCPDMIOMMUHLPR0 pIommuHlpR0;
334} IOMMUR0;
335/** Pointer to the ring-0 IOMMU device state. */
336typedef IOMMUR0 *PIOMMUR0;
337
338/**
339 * The raw-mode IOMMU device state.
340 */
341typedef struct IOMMURC
342{
343 /** Device instance. */
344 PPDMDEVINSR0 pDevInsRC;
345 /** The IOMMU helpers. */
346 PCPDMIOMMUHLPRC pIommuHlpRC;
347} IOMMURC;
348/** Pointer to the raw-mode IOMMU device state. */
349typedef IOMMURC *PIOMMURC;
350
351/** The IOMMU device state for the current context. */
352typedef CTX_SUFF(IOMMU) IOMMUCC;
353/** Pointer to the IOMMU device state for the current context. */
354typedef CTX_SUFF(PIOMMU) PIOMMUCC;
355
356/**
357 * IOMMU register access routines.
358 */
359typedef struct
360{
361 const char *pszName;
362 VBOXSTRICTRC (*pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t *pu64Value);
363 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
364 bool f64BitReg;
365} IOMMUREGACC;
366
367
368/*********************************************************************************************************************************
369* Global Variables *
370*********************************************************************************************************************************/
371/**
372 * An array of the number of device table segments supported.
373 * Indexed by u2DevTabSegSup.
374 */
375static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
376
377/**
378 * An array of the masks to select the device table segment index from a device ID.
379 */
380static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
381
382/**
383 * The maximum size (inclusive) of each device table segment (0 to 7).
384 * Indexed by the device table segment index.
385 */
386static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
387
388
389#ifndef VBOX_DEVICE_STRUCT_TESTCASE
390/**
391 * Gets the maximum number of buffer entries for the given buffer length.
392 *
393 * @returns Number of buffer entries.
394 * @param uEncodedLen The length (power-of-2 encoded).
395 */
396DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
397{
398 Assert(uEncodedLen > 7);
399 return 2 << (uEncodedLen - 1);
400}
401
402
403/**
404 * Gets the total length of the buffer given a base register's encoded length.
405 *
406 * @returns The length of the buffer in bytes.
407 * @param uEncodedLen The length (power-of-2 encoded).
408 */
409DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
410{
411 Assert(uEncodedLen > 7);
412 return (2 << (uEncodedLen - 1)) << 4;
413}
414
415
416/**
417 * Gets the number of (unconsumed) entries in the event log.
418 *
419 * @returns The number of entries in the event log.
420 * @param pThis The IOMMU device state.
421 */
422static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
423{
424 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
425 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
426 if (idxTail >= idxHead)
427 return idxTail - idxHead;
428
429 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
430 return cMaxEvts - idxHead + idxTail;
431}
432
433
434/**
435 * Gets the number of (unconsumed) commands in the command buffer.
436 *
437 * @returns The number of commands in the command buffer.
438 * @param pThis The IOMMU device state.
439 */
440static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
441{
442 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
443 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
444 if (idxTail >= idxHead)
445 return idxTail - idxHead;
446
447 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
448 return cMaxCmds - idxHead + idxTail;
449}
450
451
452DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
453{
454 IOMMU_STATUS_T Status;
455 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
456 return Status;
457}
458
459
460DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
461{
462 IOMMU_CTRL_T Ctrl;
463 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
464 return Ctrl;
465}
466
467
468/**
469 * Returns whether MSI is enabled for the IOMMU.
470 *
471 * @returns Whether MSI is enabled.
472 * @param pDevIns The IOMMU device instance.
473 *
474 * @note There should be a PCIDevXxx function for this.
475 */
476static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
477{
478 MSI_CAP_HDR_T MsiCapHdr;
479 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
480 return MsiCapHdr.n.u1MsiEnable;
481}
482
483
484/**
485 * Signals a PCI target abort.
486 *
487 * @param pDevIns The IOMMU device instance.
488 */
489static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
490{
491 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
492 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
493 PDMPciDevSetStatus(pPciDev, u16Status);
494}
495
496
497/**
498 * Wakes up the command thread if there are commands to be processed or if
499 * processing is requested to be stopped by software.
500 *
501 * @param pDevIns The IOMMU device instance.
502 */
503static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
504{
505 IOMMU_ASSERT_LOCKED(pDevIns);
506 LogFlowFunc(("\n"));
507
508 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
509 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
510 if (Status.n.u1CmdBufRunning)
511 {
512 LogFlowFunc(("Signaling command thread\n"));
513 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
514 }
515}
516
517
518/**
519 * Writes to a read-only register.
520 */
521static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
522{
523 RT_NOREF(pDevIns, pThis, iReg, u64Value);
524 LogFunc(("Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
525 return VINF_SUCCESS;
526}
527
528
529/**
530 * Writes the Device Table Base Address Register.
531 */
532static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
533{
534 RT_NOREF(pDevIns, iReg);
535
536 /* Mask out all unrecognized bits. */
537 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
538
539 /* Update the register. */
540 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
541 return VINF_SUCCESS;
542}
543
544
545/**
546 * Writes the Command Buffer Base Address Register.
547 */
548static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
549{
550 RT_NOREF(pDevIns, iReg);
551
552 /*
553 * While this is not explicitly specified like the event log base address register,
554 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
555 * Inconsistent specs :/
556 */
557 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
558 if (Status.n.u1CmdBufRunning)
559 {
560 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
561 return VINF_SUCCESS;
562 }
563
564 /* Mask out all unrecognized bits. */
565 CMD_BUF_BAR_T CmdBufBaseAddr;
566 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
567
568 /* Validate the length. */
569 if (CmdBufBaseAddr.n.u4Len >= 8)
570 {
571 /* Update the register. */
572 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
573
574 /*
575 * Writing the command buffer base address, clears the command buffer head and tail pointers.
576 * See AMD spec. 2.4 "Commands".
577 */
578 pThis->CmdBufHeadPtr.u64 = 0;
579 pThis->CmdBufTailPtr.u64 = 0;
580 }
581 else
582 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
583
584 return VINF_SUCCESS;
585}
586
587
588/**
589 * Writes the Event Log Base Address Register.
590 */
591static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
592{
593 RT_NOREF(pDevIns, iReg);
594
595 /*
596 * IOMMU behavior is undefined when software writes this register when event logging is running.
597 * In our emulation, we ignore the write entirely.
598 * See AMD IOMMU spec. "Event Log Base Address Register".
599 */
600 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
601 if (Status.n.u1EvtLogRunning)
602 {
603 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
604 return VINF_SUCCESS;
605 }
606
607 /* Mask out all unrecognized bits. */
608 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
609 EVT_LOG_BAR_T EvtLogBaseAddr;
610 EvtLogBaseAddr.u64 = u64Value;
611
612 /* Validate the length. */
613 if (EvtLogBaseAddr.n.u4Len >= 8)
614 {
615 /* Update the register. */
616 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
617
618 /*
619 * Writing the event log base address, clears the event log head and tail pointers.
620 * See AMD spec. 2.5 "Event Logging".
621 */
622 pThis->EvtLogHeadPtr.u64 = 0;
623 pThis->EvtLogTailPtr.u64 = 0;
624 }
625 else
626 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
627
628 return VINF_SUCCESS;
629}
630
631
632/**
633 * Writes the Control Register.
634 */
635static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
636{
637 RT_NOREF(pDevIns, iReg);
638
639 /* Mask out all unrecognized bits. */
640 u64Value &= IOMMU_CTRL_VALID_MASK;
641
642 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
643 IOMMU_CTRL_T NewCtrl;
644 NewCtrl.u64 = u64Value;
645
646 /* Update the register. */
647 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
648
649 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
650 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
651
652 /* Enable or disable event logging when the bit transitions. */
653 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
654 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
655 if ( fOldEvtLogEn != fNewEvtLogEn
656 || fOldIommuEn != fNewIommuEn)
657 {
658 if ( fNewIommuEn
659 && fNewEvtLogEn)
660 {
661 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
662 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
663 }
664 else
665 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
666 }
667
668 /* Enable or disable command buffer processing when the bit transitions. */
669 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
670 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
671 if ( fOldCmdBufEn != fNewCmdBufEn
672 || fOldIommuEn != fNewIommuEn)
673 {
674 if ( fNewCmdBufEn
675 && fNewIommuEn)
676 {
677 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
678 LogFunc(("Command buffer enabled\n"));
679
680 /* Wake up the command thread to start processing commands. */
681 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
682 }
683 else
684 {
685 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
686 LogFunc(("Command buffer disabled\n"));
687 }
688 }
689
690 return VINF_SUCCESS;
691}
692
693
694/**
695 * Writes to the Excluse Range Base Address Register.
696 */
697static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
698{
699 RT_NOREF(pDevIns, iReg);
700 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
701 return VINF_SUCCESS;
702}
703
704
705/**
706 * Writes to the Excluse Range Limit Register.
707 */
708static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
709{
710 RT_NOREF(pDevIns, iReg);
711 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
712 u64Value |= UINT64_C(0xfff);
713 pThis->ExclRangeLimit.u64 = u64Value;
714 return VINF_SUCCESS;
715}
716
717
718/**
719 * Writes the Hardware Event Register (Hi).
720 */
721static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
722{
723 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
724 RT_NOREF(pDevIns, iReg);
725 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
726 pThis->HwEvtHi.u64 = u64Value;
727 return VINF_SUCCESS;
728}
729
730
731/**
732 * Writes the Hardware Event Register (Lo).
733 */
734static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
735{
736 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
737 RT_NOREF(pDevIns, iReg);
738 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
739 pThis->HwEvtLo = u64Value;
740 return VINF_SUCCESS;
741}
742
743
744/**
745 * Writes the Hardware Event Status Register.
746 */
747static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
748{
749 RT_NOREF(pDevIns, iReg);
750
751 /* Mask out all unrecognized bits. */
752 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
753
754 /*
755 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
756 * If the current status bits or the bits being written are both 0, we've nothing to do.
757 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
758 */
759 uint64_t HwStatus = pThis->HwEvtStatus.u64;
760 if (!(HwStatus & RT_BIT(0)))
761 return VINF_SUCCESS;
762 if (u64Value & HwStatus & RT_BIT_64(0))
763 HwStatus &= ~RT_BIT_64(0);
764 if (u64Value & HwStatus & RT_BIT_64(1))
765 HwStatus &= ~RT_BIT_64(1);
766
767 /* Update the register. */
768 pThis->HwEvtStatus.u64 = HwStatus;
769 return VINF_SUCCESS;
770}
771
772
773/**
774 * Writes the Device Table Segment Base Address Register.
775 */
776static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
777{
778 RT_NOREF(pDevIns);
779
780 /* Figure out which segment is being written. */
781 uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
782 uint8_t const idxSegment = offSegment + 1;
783 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
784
785 /* Mask out all unrecognized bits. */
786 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
787 DEV_TAB_BAR_T DevTabSegBar;
788 DevTabSegBar.u64 = u64Value;
789
790 /* Validate the size. */
791 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
792 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
793 if (uSegSize <= uMaxSegSize)
794 {
795 /* Update the register. */
796 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
797 }
798 else
799 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
800
801 return VINF_SUCCESS;
802}
803
804
805/**
806 * Writes the MSI Capability Header Register.
807 */
808static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
809{
810 RT_NOREF(pThis, iReg);
811 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
812 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
813 MSI_CAP_HDR_T MsiCapHdr;
814 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
815 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
816 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
817 return VINF_SUCCESS;
818}
819
820
821/**
822 * Writes the MSI Address (Lo) Register (32-bit).
823 */
824static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
825{
826 RT_NOREF(pThis, iReg);
827 Assert(!RT_HI_U32(u64Value));
828 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
829 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
830 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
831 return VINF_SUCCESS;
832}
833
834
835/**
836 * Writes the MSI Address (Hi) Register (32-bit).
837 */
838static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
839{
840 RT_NOREF(pThis, iReg);
841 Assert(!RT_HI_U32(u64Value));
842 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
843 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
844 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
845 return VINF_SUCCESS;
846}
847
848
849/**
850 * Writes the MSI Data Register (32-bit).
851 */
852static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
853{
854 RT_NOREF(pThis, iReg);
855 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
856 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
857 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
858 return VINF_SUCCESS;
859}
860
861
862/**
863 * Writes the Command Buffer Head Pointer Register (32-bit).
864 */
865static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
866{
867 RT_NOREF(pDevIns, iReg);
868
869 /*
870 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
871 * In our emulation, we ignore the write entirely.
872 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
873 */
874 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
875 if (Status.n.u1CmdBufRunning)
876 {
877 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
878 return VINF_SUCCESS;
879 }
880
881 /*
882 * IOMMU behavior is undefined when software writes a value outside the buffer length.
883 * In our emulation, we ignore the write entirely.
884 */
885 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
886 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
887 Assert(cbBuf <= _512K);
888 if (offBuf >= cbBuf)
889 {
890 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
891 return VINF_SUCCESS;
892 }
893
894 /* Update the register. */
895 pThis->CmdBufHeadPtr.au32[0] = offBuf;
896
897 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
898
899 LogFlowFunc(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
900 return VINF_SUCCESS;
901}
902
903
904/**
905 * Writes the Command Buffer Tail Pointer Register (32-bit).
906 */
907static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
908{
909 RT_NOREF(pDevIns, iReg);
910
911 /*
912 * IOMMU behavior is undefined when software writes a value outside the buffer length.
913 * In our emulation, we ignore the write entirely.
914 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
915 */
916 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
917 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
918 Assert(cbBuf <= _512K);
919 if (offBuf >= cbBuf)
920 {
921 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
922 return VINF_SUCCESS;
923 }
924
925 /*
926 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
927 * head pointer after adding one or more commands to the buffer.
928 *
929 * However, we cannot enforce this strictly because it's legal for software to shrink the
930 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
931 * at 0). Software might even make the queue empty by making head and tail equal which is
932 * allowed. I don't think we can or should try too hard to prevent software shooting itself
933 * in the foot here. As long as we make sure the offset value is within the circular buffer
934 * bounds (which we do by masking bits above) it should be sufficient.
935 */
936 pThis->CmdBufTailPtr.au32[0] = offBuf;
937
938 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
939
940 LogFlowFunc(("Set CmdBufTailPtr to %#RX32\n", offBuf));
941 return VINF_SUCCESS;
942}
943
944
945/**
946 * Writes the Event Log Head Pointer Register (32-bit).
947 */
948static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
949{
950 RT_NOREF(pDevIns, iReg);
951
952 /*
953 * IOMMU behavior is undefined when software writes a value outside the buffer length.
954 * In our emulation, we ignore the write entirely.
955 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
956 */
957 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
958 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
959 Assert(cbBuf <= _512K);
960 if (offBuf >= cbBuf)
961 {
962 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
963 return VINF_SUCCESS;
964 }
965
966 /* Update the register. */
967 pThis->EvtLogHeadPtr.au32[0] = offBuf;
968
969 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
970 return VINF_SUCCESS;
971}
972
973
974/**
975 * Writes the Event Log Tail Pointer Register (32-bit).
976 */
977static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
978{
979 RT_NOREF(pDevIns, iReg);
980 NOREF(pThis);
981
982 /*
983 * IOMMU behavior is undefined when software writes this register when the event log is running.
984 * In our emulation, we ignore the write entirely.
985 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
986 */
987 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
988 if (Status.n.u1EvtLogRunning)
989 {
990 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
991 return VINF_SUCCESS;
992 }
993
994 /*
995 * IOMMU behavior is undefined when software writes a value outside the buffer length.
996 * In our emulation, we ignore the write entirely.
997 */
998 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
999 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1000 Assert(cbBuf <= _512K);
1001 if (offBuf >= cbBuf)
1002 {
1003 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1004 return VINF_SUCCESS;
1005 }
1006
1007 /* Update the register. */
1008 pThis->EvtLogTailPtr.au32[0] = offBuf;
1009
1010 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1011 return VINF_SUCCESS;
1012}
1013
1014
1015/**
1016 * Writes the Status Register (64-bit).
1017 */
1018static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
1019{
1020 RT_NOREF(pDevIns, iReg);
1021
1022 /* Mask out all unrecognized bits. */
1023 u64Value &= IOMMU_STATUS_VALID_MASK;
1024
1025 /*
1026 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1027 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1028 */
1029 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1030 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1031 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1032 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1033
1034 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1035
1036 /* Update the register. */
1037 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1038 return VINF_SUCCESS;
1039}
1040
1041
1042#if 0
1043/**
1044 * Table 0: Registers-access table.
1045 */
1046static const IOMMUREGACC g_aTable0Regs[] =
1047{
1048
1049};
1050
1051/**
1052 * Table 1: Registers-access table.
1053 */
1054static const IOMMUREGACC g_aTable1Regs[] =
1055{
1056};
1057#endif
1058
1059
1060/**
1061 * Writes an IOMMU register (32-bit and 64-bit).
1062 *
1063 * @returns Strict VBox status code.
1064 * @param pDevIns The IOMMU device instance.
1065 * @param off MMIO byte offset to the register.
1066 * @param cb The size of the write access.
1067 * @param uValue The value being written.
1068 *
1069 * @thread EMT.
1070 */
1071static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1072{
1073 Assert(off < IOMMU_MMIO_REGION_SIZE);
1074 Assert(cb == 4 || cb == 8);
1075 Assert(!(off & (cb - 1)));
1076
1077 LogFlowFunc(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1078
1079 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1080 switch (off)
1081 {
1082 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1083 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1084 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1085 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1086 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1087 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1088 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1089
1090 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1091 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1092 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1093 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1094
1095 case IOMMU_MMIO_OFF_GALOG_BAR:
1096 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1097
1098 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1099 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1100
1101 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1102 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1103 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1104 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1105 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1106 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1107 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1108
1109 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1110 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1111 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1112
1113 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1114 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1115 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1116 {
1117 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1118 if (cb == 4 || RT_FAILURE(rcStrict))
1119 return rcStrict;
1120 uValue >>= 32;
1121 RT_FALL_THRU();
1122 }
1123 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1124 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1125 {
1126 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1127 if (cb == 4 || RT_FAILURE(rcStrict))
1128 return rcStrict;
1129 uValue >>= 32;
1130 RT_FALL_THRU();
1131 }
1132 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1133 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1134
1135 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1136
1137 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1138 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1139 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1140
1141 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1142 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1143 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1144 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1145 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1146 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1147 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1148 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1149 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1150 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1151 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1152 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1153
1154 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1155
1156 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1157 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1158 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1159 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1160
1161 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1162
1163 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1164 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1165
1166 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1167 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1168
1169 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1170 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1171
1172 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1173 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1174
1175 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1176 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1177 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1178
1179 /* Not implemented. */
1180 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1181 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1182 {
1183 LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1184 return VINF_SUCCESS;
1185 }
1186
1187 /* Unknown. */
1188 default:
1189 {
1190 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1191 return VINF_SUCCESS;
1192 }
1193 }
1194}
1195
1196
1197/**
1198 * Reads an IOMMU register (64-bit) given its MMIO offset.
1199 *
1200 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1201 * boundary include the lower half of the subsequent register.
1202 *
1203 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1204 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1205 * software will only perform 32-bit reads on those 32-bit registers that are
1206 * aligned on 8-byte boundaries.
1207 *
1208 * @returns Strict VBox status code.
1209 * @param pDevIns The IOMMU device instance.
1210 * @param off The MMIO offset of the register in bytes.
1211 * @param puResult Where to store the value being read.
1212 *
1213 * @thread EMT.
1214 */
1215static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1216{
1217 Assert(off < IOMMU_MMIO_REGION_SIZE);
1218 Assert(!(off & 7) || !(off & 3));
1219
1220 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1221 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1222 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1223
1224 LogFlowFunc(("off=%#x\n", off));
1225
1226 /** @todo IOMMU: fine-grained locking? */
1227 uint64_t uReg;
1228 switch (off)
1229 {
1230 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1231 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1232 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1233 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1234 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1235 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1236 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1237
1238 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1239 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1240 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1241 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1242
1243 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1244 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1245
1246 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1247 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1248
1249 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1250 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1251 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1252 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1253 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1254 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1255 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1256 {
1257 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1258 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1259 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1260 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1261 break;
1262 }
1263
1264 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1265 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1266 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1267
1268 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1269 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1270 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1271 {
1272 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1273 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1274 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1275 break;
1276 }
1277 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1278 {
1279 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1280 break;
1281 }
1282 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1283 {
1284 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1285 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1286 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1287 break;
1288 }
1289 case IOMMU_MMIO_OFF_MSI_DATA:
1290 {
1291 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1292 break;
1293 }
1294 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1295 {
1296 /*
1297 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1298 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1299 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1300 * 0 for this register.
1301 */
1302 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1303 break;
1304 }
1305
1306 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1307
1308 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1309 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1310 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1311
1312 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1313 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1314 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1315 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1316 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1317 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1318 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1319 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1320 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1321 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1322 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1323 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1324
1325 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1326
1327 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1328 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1329 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1330 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1331
1332 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
1333
1334 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
1335 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
1336
1337 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
1338 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
1339
1340 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
1341 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
1342
1343 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
1344 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
1345
1346 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
1347 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
1348 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
1349
1350 /* Not implemented. */
1351 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1352 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1353 {
1354 LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1355 uReg = 0;
1356 break;
1357 }
1358
1359 /* Unknown. */
1360 default:
1361 {
1362 LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
1363 uReg = 0;
1364 return VINF_IOM_MMIO_UNUSED_00;
1365 }
1366 }
1367
1368 *puResult = uReg;
1369 return VINF_SUCCESS;
1370}
1371
1372
1373/**
1374 * Raises the MSI interrupt for the IOMMU device.
1375 *
1376 * @param pDevIns The IOMMU device instance.
1377 *
1378 * @thread Any.
1379 */
1380static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
1381{
1382 if (iommuAmdIsMsiEnabled(pDevIns))
1383 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
1384}
1385
1386
1387/**
1388 * Clears the MSI interrupt for the IOMMU device.
1389 *
1390 * @param pDevIns The IOMMU device instance.
1391 *
1392 * @thread Any.
1393 */
1394static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
1395{
1396 if (iommuAmdIsMsiEnabled(pDevIns))
1397 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
1398}
1399
1400
1401/**
1402 * Writes an entry to the event log in memory.
1403 *
1404 * @returns VBox status code.
1405 * @param pDevIns The IOMMU device instance.
1406 * @param pEvent The event to log.
1407 *
1408 * @thread Any.
1409 */
1410static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1411{
1412 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1413
1414 IOMMU_ASSERT_LOCKED(pDevIns);
1415
1416 /* Check if event logging is active and the log has not overflowed. */
1417 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1418 if ( Status.n.u1EvtLogRunning
1419 && !Status.n.u1EvtOverflow)
1420 {
1421 uint32_t const cbEvt = sizeof(*pEvent);
1422
1423 /* Get the offset we need to write the event to in memory (circular buffer offset). */
1424 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
1425 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
1426
1427 /* Ensure we have space in the event log. */
1428 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
1429 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
1430 if (cEvts + 1 < cMaxEvts)
1431 {
1432 /* Write the event log entry to memory. */
1433 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
1434 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
1435 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
1436 if (RT_FAILURE(rc))
1437 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
1438
1439 /* Increment the event log tail pointer. */
1440 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1441 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
1442
1443 /* Indicate that an event log entry was written. */
1444 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
1445
1446 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
1447 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1448 if (Ctrl.n.u1EvtIntrEn)
1449 iommuAmdRaiseMsiInterrupt(pDevIns);
1450 }
1451 else
1452 {
1453 /* Indicate that the event log has overflowed. */
1454 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
1455
1456 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
1457 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1458 if (Ctrl.n.u1EvtIntrEn)
1459 iommuAmdRaiseMsiInterrupt(pDevIns);
1460 }
1461 }
1462
1463 return VINF_SUCCESS;
1464}
1465
1466
1467/**
1468 * Sets an event in the hardware error registers.
1469 *
1470 * @param pDevIns The IOMMU device instance.
1471 * @param pEvent The event.
1472 *
1473 * @thread Any.
1474 */
1475static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1476{
1477 IOMMU_ASSERT_LOCKED(pDevIns);
1478
1479 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1480 if (pThis->ExtFeat.n.u1HwErrorSup)
1481 {
1482 if (pThis->HwEvtStatus.n.u1Valid)
1483 pThis->HwEvtStatus.n.u1Overflow = 1;
1484 pThis->HwEvtStatus.n.u1Valid = 1;
1485 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
1486 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
1487 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
1488 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
1489 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
1490 }
1491}
1492
1493
1494/**
1495 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
1496 *
1497 * @param uDevId The device ID.
1498 * @param uDomainId The domain ID.
1499 * @param GCPhysPtEntity The system physical address of the page table
1500 * entity.
1501 * @param enmOp The IOMMU operation being performed.
1502 * @param pEvtPageTabHwErr Where to store the initialized event.
1503 */
1504static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
1505 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1506{
1507 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
1508 pEvtPageTabHwErr->n.u16DevId = uDevId;
1509 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
1510 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
1511 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1512 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1513 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1514 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1515 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
1516 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
1517}
1518
1519
1520/**
1521 * Raises a PAGE_TAB_HARDWARE_ERROR event.
1522 *
1523 * @param pDevIns The IOMMU device instance.
1524 * @param enmOp The IOMMU operation being performed.
1525 * @param pEvtPageTabHwErr The page table hardware error event.
1526 *
1527 * @thread Any.
1528 */
1529static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1530{
1531 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
1532 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
1533
1534 IOMMU_LOCK_NORET(pDevIns);
1535
1536 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1537 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1538 if (enmOp != IOMMUOP_CMD)
1539 iommuAmdSetPciTargetAbort(pDevIns);
1540
1541 IOMMU_UNLOCK(pDevIns);
1542
1543 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
1544 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
1545 pEvtPageTabHwErr->n.u2Type));
1546}
1547
1548
1549/**
1550 * Initializes a COMMAND_HARDWARE_ERROR event.
1551 *
1552 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
1553 * @param pEvtCmdHwErr Where to store the initialized event.
1554 */
1555static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1556{
1557 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
1558 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
1559 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
1560 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
1561}
1562
1563
1564/**
1565 * Raises a COMMAND_HARDWARE_ERROR event.
1566 *
1567 * @param pDevIns The IOMMU device instance.
1568 * @param pEvtCmdHwErr The command hardware error event.
1569 *
1570 * @thread Any.
1571 */
1572static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1573{
1574 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
1575 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
1576 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1577
1578 IOMMU_LOCK_NORET(pDevIns);
1579
1580 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1581 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1582 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1583
1584 IOMMU_UNLOCK(pDevIns);
1585
1586 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
1587}
1588
1589
1590/**
1591 * Initializes a DEV_TAB_HARDWARE_ERROR event.
1592 *
1593 * @param uDevId The device ID.
1594 * @param GCPhysDte The system physical address of the failed device table
1595 * access.
1596 * @param enmOp The IOMMU operation being performed.
1597 * @param pEvtDevTabHwErr Where to store the initialized event.
1598 */
1599static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
1600 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1601{
1602 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
1603 pEvtDevTabHwErr->n.u16DevId = uDevId;
1604 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1605 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
1606 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1607 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1608 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1609 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
1610 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
1611}
1612
1613
1614/**
1615 * Raises a DEV_TAB_HARDWARE_ERROR event.
1616 *
1617 * @param pDevIns The IOMMU device instance.
1618 * @param enmOp The IOMMU operation being performed.
1619 * @param pEvtDevTabHwErr The device table hardware error event.
1620 *
1621 * @thread Any.
1622 */
1623static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1624{
1625 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
1626 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
1627
1628 IOMMU_LOCK_NORET(pDevIns);
1629
1630 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1631 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1632 if (enmOp != IOMMUOP_CMD)
1633 iommuAmdSetPciTargetAbort(pDevIns);
1634
1635 IOMMU_UNLOCK(pDevIns);
1636
1637 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
1638 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
1639}
1640
1641
1642/**
1643 * Initializes an ILLEGAL_COMMAND_ERROR event.
1644 *
1645 * @param GCPhysCmd The system physical address of the failed command
1646 * access.
1647 * @param pEvtIllegalCmd Where to store the initialized event.
1648 */
1649static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
1650{
1651 Assert(!(GCPhysCmd & UINT64_C(0xf)));
1652 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
1653 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
1654 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
1655}
1656
1657
1658/**
1659 * Raises an ILLEGAL_COMMAND_ERROR event.
1660 *
1661 * @param pDevIns The IOMMU device instance.
1662 * @param pEvtIllegalCmd The illegal command error event.
1663 */
1664static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
1665{
1666 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
1667 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
1668 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1669
1670 IOMMU_LOCK_NORET(pDevIns);
1671
1672 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1673 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1674
1675 IOMMU_UNLOCK(pDevIns);
1676
1677 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
1678}
1679
1680
1681/**
1682 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
1683 *
1684 * @param uDevId The device ID.
1685 * @param uIova The I/O virtual address.
1686 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
1687 * event was caused by an invalid level encoding in the
1688 * DTE.
1689 * @param enmOp The IOMMU operation being performed.
1690 * @param pEvtIllegalDte Where to store the initialized event.
1691 */
1692static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
1693 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
1694{
1695 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
1696 pEvtIllegalDte->n.u16DevId = uDevId;
1697 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1698 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1699 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
1700 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1701 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
1702 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
1703 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
1704 * IOMMU spec here but not for this field for I/O page fault event. */
1705 Assert(!(uIova & UINT64_C(0x3)));
1706}
1707
1708
1709/**
1710 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
1711 *
1712 * @param pDevIns The IOMMU instance data.
1713 * @param enmOp The IOMMU operation being performed.
1714 * @param pEvtIllegalDte The illegal device table entry event.
1715 * @param enmEvtType The illegal device table entry event type.
1716 *
1717 * @thread Any.
1718 */
1719static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
1720 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
1721{
1722 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
1723 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
1724
1725 IOMMU_LOCK_NORET(pDevIns);
1726
1727 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1728 if (enmOp != IOMMUOP_CMD)
1729 iommuAmdSetPciTargetAbort(pDevIns);
1730
1731 IOMMU_UNLOCK(pDevIns);
1732
1733 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
1734 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
1735 NOREF(enmEvtType);
1736}
1737
1738
1739/**
1740 * Initializes an IO_PAGE_FAULT event.
1741 *
1742 * @param uDevId The device ID.
1743 * @param uDomainId The domain ID.
1744 * @param uIova The I/O virtual address being accessed.
1745 * @param fPresent Transaction to a page marked as present (including
1746 * DTE.V=1) or interrupt marked as remapped
1747 * (IRTE.RemapEn=1).
1748 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
1749 * the I/O page fault was caused by invalid level
1750 * encoding.
1751 * @param fPermDenied Permission denied for the address being accessed.
1752 * @param enmOp The IOMMU operation being performed.
1753 * @param pEvtIoPageFault Where to store the initialized event.
1754 */
1755static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
1756 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
1757{
1758 Assert(!fPermDenied || fPresent);
1759 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
1760 pEvtIoPageFault->n.u16DevId = uDevId;
1761 //pEvtIoPageFault->n.u4PasidHi = 0;
1762 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
1763 //pEvtIoPageFault->n.u1GuestOrNested = 0;
1764 //pEvtIoPageFault->n.u1NoExecute = 0;
1765 //pEvtIoPageFault->n.u1User = 0;
1766 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1767 pEvtIoPageFault->n.u1Present = fPresent;
1768 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1769 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
1770 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
1771 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1772 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
1773 pEvtIoPageFault->n.u64Addr = uIova;
1774}
1775
1776
1777/**
1778 * Raises an IO_PAGE_FAULT event.
1779 *
1780 * @param pDevIns The IOMMU instance data.
1781 * @param pDte The device table entry. Optional, can be NULL
1782 * depending on @a enmOp.
1783 * @param pIrte The interrupt remapping table entry. Optional, can
1784 * be NULL depending on @a enmOp.
1785 * @param enmOp The IOMMU operation being performed.
1786 * @param pEvtIoPageFault The I/O page fault event.
1787 * @param enmEvtType The I/O page fault event type.
1788 *
1789 * @thread Any.
1790 */
1791static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
1792 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
1793{
1794 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
1795 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
1796
1797 IOMMU_LOCK_NORET(pDevIns);
1798
1799 bool fSuppressEvtLogging = false;
1800 if ( enmOp == IOMMUOP_MEM_READ
1801 || enmOp == IOMMUOP_MEM_WRITE)
1802 {
1803 if ( pDte
1804 && pDte->n.u1Valid)
1805 {
1806 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
1807 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
1808 * suppression. Perhaps will be possible when we complete IOTLB/cache
1809 * handling. */
1810 }
1811 }
1812 else if (enmOp == IOMMUOP_INTR_REQ)
1813 {
1814 if ( pDte
1815 && pDte->n.u1IntrMapValid)
1816 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
1817
1818 if ( !fSuppressEvtLogging
1819 && pIrte)
1820 fSuppressEvtLogging = pIrte->n.u1SuppressPf;
1821 }
1822 /* else: Events are never suppressed for commands. */
1823
1824 switch (enmEvtType)
1825 {
1826 case kIoPageFaultType_PermDenied:
1827 {
1828 /* Cannot be triggered by a command. */
1829 Assert(enmOp != IOMMUOP_CMD);
1830 RT_FALL_THRU();
1831 }
1832 case kIoPageFaultType_DteRsvdPagingMode:
1833 case kIoPageFaultType_PteInvalidPageSize:
1834 case kIoPageFaultType_PteInvalidLvlEncoding:
1835 case kIoPageFaultType_SkippedLevelIovaNotZero:
1836 case kIoPageFaultType_PteRsvdNotZero:
1837 case kIoPageFaultType_PteValidNotSet:
1838 case kIoPageFaultType_DteTranslationDisabled:
1839 case kIoPageFaultType_PasidInvalidRange:
1840 {
1841 /*
1842 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
1843 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
1844 */
1845 if (enmOp != IOMMUOP_TRANSLATE_REQ)
1846 {
1847 if (!fSuppressEvtLogging)
1848 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1849 if (enmOp != IOMMUOP_CMD)
1850 iommuAmdSetPciTargetAbort(pDevIns);
1851 }
1852 break;
1853 }
1854
1855 case kIoPageFaultType_UserSupervisor:
1856 {
1857 /* Access is blocked and only creates an event log entry. */
1858 if (!fSuppressEvtLogging)
1859 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1860 break;
1861 }
1862
1863 case kIoPageFaultType_IrteAddrInvalid:
1864 case kIoPageFaultType_IrteRsvdNotZero:
1865 case kIoPageFaultType_IrteRemapEn:
1866 case kIoPageFaultType_IrteRsvdIntType:
1867 case kIoPageFaultType_IntrReqAborted:
1868 case kIoPageFaultType_IntrWithPasid:
1869 {
1870 /* Only trigerred by interrupt requests. */
1871 Assert(enmOp == IOMMUOP_INTR_REQ);
1872 if (!fSuppressEvtLogging)
1873 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1874 iommuAmdSetPciTargetAbort(pDevIns);
1875 break;
1876 }
1877
1878 case kIoPageFaultType_SmiFilterMismatch:
1879 {
1880 /* Not supported and probably will never be, assert. */
1881 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
1882 break;
1883 }
1884
1885 case kIoPageFaultType_DevId_Invalid:
1886 {
1887 /* Cannot be triggered by a command. */
1888 Assert(enmOp != IOMMUOP_CMD);
1889 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
1890 if (!fSuppressEvtLogging)
1891 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1892 if ( enmOp == IOMMUOP_MEM_READ
1893 || enmOp == IOMMUOP_MEM_WRITE)
1894 iommuAmdSetPciTargetAbort(pDevIns);
1895 break;
1896 }
1897 }
1898
1899 IOMMU_UNLOCK(pDevIns);
1900}
1901
1902
1903/**
1904 * Returns whether the I/O virtual address is to be excluded from translation and
1905 * permission checks.
1906 *
1907 * @returns @c true if the DVA is excluded, @c false otherwise.
1908 * @param pThis The IOMMU device state.
1909 * @param pDte The device table entry.
1910 * @param uIova The I/O virtual address.
1911 *
1912 * @remarks Ensure the exclusion range is enabled prior to calling this function.
1913 *
1914 * @thread Any.
1915 */
1916static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
1917{
1918 /* Ensure the exclusion range is enabled. */
1919 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
1920
1921 /* Check if the IOVA falls within the exclusion range. */
1922 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
1923 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
1924 if (uIovaExclLast - uIova >= uIovaExclFirst)
1925 {
1926 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
1927 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
1928 || pDte->n.u1AllowExclusion)
1929 return true;
1930 }
1931 return false;
1932}
1933
1934
1935/**
1936 * Reads a device table entry from guest memory given the device ID.
1937 *
1938 * @returns VBox status code.
1939 * @param pDevIns The IOMMU device instance.
1940 * @param uDevId The device ID.
1941 * @param enmOp The IOMMU operation being performed.
1942 * @param pDte Where to store the device table entry.
1943 *
1944 * @thread Any.
1945 */
1946static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
1947{
1948 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1949 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1950
1951 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
1952 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
1953
1954 uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
1955 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1956
1957 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
1958 uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
1959 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
1960
1961 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
1962 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
1963 if (RT_FAILURE(rc))
1964 {
1965 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
1966
1967 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
1968 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
1969 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
1970 return VERR_IOMMU_IPE_1;
1971 }
1972
1973
1974 return rc;
1975}
1976
1977
1978/**
1979 * Walks the I/O page table to translate the I/O virtual address to a system
1980 * physical address.
1981 *
1982 * @returns VBox status code.
1983 * @param pDevIns The IOMMU device instance.
1984 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
1985 * @param uDevId The device ID.
1986 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
1987 * permissions for the access being made.
1988 * @param pDte The device table entry.
1989 * @param enmOp The IOMMU operation being performed.
1990 * @param pWalkResult Where to store the results of the I/O page walk. This is
1991 * only updated when VINF_SUCCESS is returned.
1992 *
1993 * @thread Any.
1994 */
1995static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
1996 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
1997{
1998 Assert(pDte->n.u1Valid);
1999 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2000
2001 /* If the translation is not valid, raise an I/O page fault. */
2002 if (pDte->n.u1TranslationValid)
2003 { /* likely */ }
2004 else
2005 {
2006 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2007 * doesn't explicitly say whether an I/O page fault is raised. From other
2008 * places in the spec. it seems early page walk terminations (starting with
2009 * the DTE) return the state computed so far and raises an I/O page fault. So
2010 * returning an invalid translation rather than skipping translation. */
2011 LogFunc(("Translation valid bit not set -> IOPF"));
2012 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2013 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2014 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2015 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2016 kIoPageFaultType_DteTranslationDisabled);
2017 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2018 }
2019
2020 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2021 uint8_t const uMaxLevel = pDte->n.u3Mode;
2022 if (uMaxLevel != 0)
2023 { /* likely */ }
2024 else
2025 {
2026 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2027 if ((fAccess & fDtePerm) != fAccess)
2028 {
2029 LogFunc(("Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
2030 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2031 }
2032 pWalkResult->GCPhysSpa = uIova;
2033 pWalkResult->cShift = 0;
2034 pWalkResult->fIoPerm = fDtePerm;
2035 return VINF_SUCCESS;
2036 }
2037
2038 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2039 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2040 { /* likely */ }
2041 else
2042 {
2043 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2044 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2045 * I'm just going with I/O page fault. */
2046 LogFunc(("Invalid root page table level %#x -> IOPF", uMaxLevel));
2047 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2048 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2049 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2050 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2051 kIoPageFaultType_PteInvalidLvlEncoding);
2052 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2053 }
2054
2055 /* Check permissions bits of the root page table. */
2056 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2057 if ((fAccess & fRootPtePerm) == fAccess)
2058 { /* likely */ }
2059 else
2060 {
2061 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF", fAccess, fRootPtePerm));
2062 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2063 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2064 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2065 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2066 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2067 }
2068
2069 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2070 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2071 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2072 * table entry every time. Not sure if it's worth optimizing that case now
2073 * or if at all. */
2074
2075 /* The virtual address bits indexing table. */
2076 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2077 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2078 UINT64_C(0x00000000001ff000),
2079 UINT64_C(0x000000003fe00000),
2080 UINT64_C(0x0000007fc0000000),
2081 UINT64_C(0x0000ff8000000000),
2082 UINT64_C(0x01ff000000000000),
2083 UINT64_C(0xfe00000000000000),
2084 UINT64_C(0x0000000000000000) };
2085 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2086 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2087
2088 /* Traverse the I/O page table starting with the page directory in the DTE. */
2089 IOPTENTITY_T PtEntity;
2090 PtEntity.u64 = pDte->au64[0];
2091 for (;;)
2092 {
2093 /* Figure out the system physical address of the page table at the current level. */
2094 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2095
2096 /* Read the page table entity at the current level. */
2097 {
2098 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2099 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2100 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2101 uint64_t const offPte = idxPte << 3;
2102 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2103 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2104 if (RT_FAILURE(rc))
2105 {
2106 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2107 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2108 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2109 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2110 return VERR_IOMMU_IPE_2;
2111 }
2112 }
2113
2114 /* Check present bit. */
2115 if (PtEntity.n.u1Present)
2116 { /* likely */ }
2117 else
2118 {
2119 LogFunc(("Page table entry not present -> IOPF"));
2120 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2121 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2122 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2123 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2124 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2125 }
2126
2127 /* Check permission bits. */
2128 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2129 if ((fAccess & fPtePerm) == fAccess)
2130 { /* likely */ }
2131 else
2132 {
2133 LogFunc(("Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF", fAccess, fPtePerm));
2134 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2135 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2136 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2137 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2138 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2139 }
2140
2141 /* If this is a PTE, we're at the final level and we're done. */
2142 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2143 if (uNextLevel == 0)
2144 {
2145 /* The page size of the translation is the default (4K). */
2146 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2147 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2148 pWalkResult->fIoPerm = fPtePerm;
2149 return VINF_SUCCESS;
2150 }
2151 if (uNextLevel == 7)
2152 {
2153 /* The default page size of the translation is overridden. */
2154 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2155 uint8_t cShift = X86_PAGE_4K_SHIFT;
2156 while (GCPhysPte & RT_BIT_64(cShift++))
2157 ;
2158
2159 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2160 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2161 if ( cShift > s_acIovaLevelShifts[uLevel]
2162 && cShift < s_acIovaLevelShifts[uLevel + 1])
2163 {
2164 pWalkResult->GCPhysSpa = GCPhysPte;
2165 pWalkResult->cShift = cShift;
2166 pWalkResult->fIoPerm = fPtePerm;
2167 return VINF_SUCCESS;
2168 }
2169
2170 LogFunc(("Page size invalid cShift=%#x -> IOPF", cShift));
2171 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2172 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2173 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2174 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2175 kIoPageFaultType_PteInvalidPageSize);
2176 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2177 }
2178
2179 /* Validate the next level encoding of the PDE. */
2180#if IOMMU_MAX_HOST_PT_LEVEL < 6
2181 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2182 { /* likely */ }
2183 else
2184 {
2185 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF", uNextLevel));
2186 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2187 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2188 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2189 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2190 kIoPageFaultType_PteInvalidLvlEncoding);
2191 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2192 }
2193#else
2194 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2195#endif
2196
2197 /* Validate level transition. */
2198 if (uNextLevel < uLevel)
2199 { /* likely */ }
2200 else
2201 {
2202 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF", uNextLevel, uLevel));
2203 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2204 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2205 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2206 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2207 kIoPageFaultType_PteInvalidLvlEncoding);
2208 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2209 }
2210
2211 /* Ensure IOVA bits of skipped levels are zero. */
2212 Assert(uLevel > 0);
2213 uint64_t uIovaSkipMask = 0;
2214 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2215 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2216 if (!(uIova & uIovaSkipMask))
2217 { /* likely */ }
2218 else
2219 {
2220 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF", uIova, uIovaSkipMask));
2221 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2222 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2223 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2224 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2225 kIoPageFaultType_SkippedLevelIovaNotZero);
2226 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2227 }
2228
2229 /* Continue with traversing the page directory at this level. */
2230 }
2231}
2232
2233
2234/**
2235 * Looks up an I/O virtual address from the device table.
2236 *
2237 * @returns VBox status code.
2238 * @param pDevIns The IOMMU instance data.
2239 * @param uDevId The device ID.
2240 * @param uIova The I/O virtual address to lookup.
2241 * @param cbAccess The size of the access.
2242 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2243 * permissions for the access being made.
2244 * @param enmOp The IOMMU operation being performed.
2245 * @param pGCPhysSpa Where to store the translated system physical address. Only
2246 * valid when translation succeeds and VINF_SUCCESS is
2247 * returned!
2248 *
2249 * @thread Any.
2250 */
2251static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2252 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2253{
2254 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2255
2256 /* Read the device table entry from memory. */
2257 DTE_T Dte;
2258 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2259 if (RT_SUCCESS(rc))
2260 {
2261 /* If the DTE is not valid, addresses are forwarded without translation */
2262 if (Dte.n.u1Valid)
2263 { /* likely */ }
2264 else
2265 {
2266 /** @todo IOMMU: Add to IOLTB cache. */
2267 *pGCPhysSpa = uIova;
2268 return VINF_SUCCESS;
2269 }
2270
2271 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2272 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2273 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2274 if (RT_LIKELY( !fRsvd0
2275 && !fRsvd1))
2276 { /* likely */ }
2277 else
2278 {
2279 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2280 EVT_ILLEGAL_DTE_T Event;
2281 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2282 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2283 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2284 }
2285
2286 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2287 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
2288 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2289 { /* likely */ }
2290 else
2291 {
2292 /** @todo IOMMU: Add to IOLTB cache. */
2293 *pGCPhysSpa = uIova;
2294 return VINF_SUCCESS;
2295 }
2296
2297 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
2298 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
2299
2300 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
2301 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2302 uint64_t cbRemaining = cbAccess;
2303 for (;;)
2304 {
2305 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
2306 IOWALKRESULT WalkResult;
2307 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
2308 if (RT_SUCCESS(rc))
2309 {
2310 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
2311
2312 /* Store the translated base address before continuing to check permissions for any more pages. */
2313 if (cbRemaining == cbAccess)
2314 {
2315 RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2316 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2317 }
2318
2319 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
2320 if (cbRemaining > cbPhysPage - offIova)
2321 {
2322 cbRemaining -= (cbPhysPage - offIova);
2323 uBaseIova += cbPhysPage;
2324 offIova = 0;
2325 }
2326 else
2327 break;
2328 }
2329 else
2330 {
2331 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
2332 uBaseIova, fAccess, rc));
2333 *pGCPhysSpa = NIL_RTGCPHYS;
2334 return rc;
2335 }
2336 }
2337
2338 return rc;
2339 }
2340
2341 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2342 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2343}
2344
2345
2346/**
2347 * Memory read request from a device.
2348 *
2349 * @returns VBox status code.
2350 * @param pDevIns The IOMMU device instance.
2351 * @param uDevId The device ID (bus, device, function).
2352 * @param uIova The I/O virtual address being read.
2353 * @param cbRead The number of bytes being read.
2354 * @param pGCPhysSpa Where to store the translated system physical address.
2355 *
2356 * @thread Any.
2357 */
2358static DECLCALLBACK(int) iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
2359 PRTGCPHYS pGCPhysSpa)
2360{
2361 /* Validate. */
2362 Assert(pDevIns);
2363 Assert(pGCPhysSpa);
2364 Assert(cbRead > 0);
2365
2366 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2367 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
2368
2369 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2370 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2371 if (Ctrl.n.u1IommuEn)
2372 {
2373 /** @todo IOMMU: IOTLB cache lookup. */
2374
2375 /* Lookup the IOVA from the device table. */
2376 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
2377 }
2378
2379 *pGCPhysSpa = uIova;
2380 return VINF_SUCCESS;
2381}
2382
2383
2384/**
2385 * Memory write request from a device.
2386 *
2387 * @returns VBox status code.
2388 * @param pDevIns The IOMMU device instance.
2389 * @param uDevId The device ID (bus, device, function).
2390 * @param uIova The I/O virtual address being written.
2391 * @param cbWrite The number of bytes being written.
2392 * @param pGCPhysSpa Where to store the translated physical address.
2393 *
2394 * @thread Any.
2395 */
2396static DECLCALLBACK(int) iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
2397 PRTGCPHYS pGCPhysSpa)
2398{
2399 /* Validate. */
2400 Assert(pDevIns);
2401 Assert(pGCPhysSpa);
2402 Assert(cbWrite > 0);
2403
2404 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2405 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
2406
2407 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2408 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2409 if (Ctrl.n.u1IommuEn)
2410 {
2411 /** @todo IOMMU: IOTLB cache lookup. */
2412
2413 /* Lookup the IOVA from the device table. */
2414 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
2415 }
2416
2417 *pGCPhysSpa = uIova;
2418 return VINF_SUCCESS;
2419}
2420
2421
2422/**
2423 * Reads an interrupt remapping table entry from guest memory given its DTE.
2424 *
2425 * @returns VBox status code.
2426 * @param pDevIns The IOMMU device instance.
2427 * @param uDevId The device ID.
2428 * @param pDte The device table entry.
2429 * @param GCPhysIn The source MSI address.
2430 * @param uDataIn The source MSI data.
2431 * @param enmOp The IOMMU operation being performed.
2432 * @param pIrte Where to store the interrupt remapping table entry.
2433 *
2434 * @thread Any.
2435 */
2436static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
2437 IOMMUOP enmOp, PIRTE_T pIrte)
2438{
2439 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
2440 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) << IOMMU_IRTE_SIZE_SHIFT;
2441 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
2442
2443 /* Ensure the IRTE offset is within the specified table size. */
2444 Assert(pDte->n.u4IntrTableLength < 12);
2445 if (offIrte + sizeof(IRTE_T) <= (1U << pDte->n.u4IntrTableLength) << IOMMU_IRTE_SIZE_SHIFT)
2446 { /* likely */ }
2447 else
2448 {
2449 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2450 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
2451 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2452 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2453 kIoPageFaultType_IrteAddrInvalid);
2454 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2455 }
2456
2457 /* Read the IRTE from memory. */
2458 Assert(!(GCPhysIrte & 3));
2459 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
2460 if (RT_SUCCESS(rc))
2461 return VINF_SUCCESS;
2462
2463 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
2464 * situation. Is it an I/O page fault or a device table hardware error?
2465 * There's no interrupt table hardware error event, but it's unclear what
2466 * we should do here. */
2467 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
2468 return VERR_IOMMU_IPE_4;
2469}
2470
2471
2472/**
2473 * Remap the interrupt using the interrupt remapping table.
2474 *
2475 * @returns VBox status code.
2476 * @param pDevIns The IOMMU instance data.
2477 * @param uDevId The device ID.
2478 * @param pDte The device table entry.
2479 * @param enmOp The IOMMU operation being performed.
2480 * @param pMsiIn The source MSI.
2481 * @param pMsiOut Where to store the remapped MSI.
2482 *
2483 * @thread Any.
2484 */
2485static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
2486 PMSIMSG pMsiOut)
2487{
2488 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
2489
2490 IRTE_T Irte;
2491 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
2492 if (RT_SUCCESS(rc))
2493 {
2494 if (Irte.n.u1RemapEnable)
2495 {
2496 if (!Irte.n.u1GuestMode)
2497 {
2498 if (Irte.n.u3IntrType < VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
2499 {
2500 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
2501 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
2502 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
2503 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
2504
2505 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
2506 pMsiOut->Data.u32 = pMsiIn->Data.u32;
2507 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
2508 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
2509
2510 return VINF_SUCCESS;
2511 }
2512
2513 LogFunc(("Interrupt type (%#x) invalid -> IOPF", Irte.n.u3IntrType));
2514 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2515 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2516 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2517 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
2518 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2519 }
2520
2521 LogFunc(("Guest mode not supported -> IOPF"));
2522 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2523 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2524 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2525 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
2526 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2527 }
2528
2529 LogFunc(("Remapping disabled -> IOPF"));
2530 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2531 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2532 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2533 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
2534 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2535 }
2536
2537 return rc;
2538}
2539
2540
2541/**
2542 * Looks up an MSI interrupt from the interrupt remapping table.
2543 *
2544 * @returns VBox status code.
2545 * @param pDevIns The IOMMU instance data.
2546 * @param uDevId The device ID.
2547 * @param enmOp The IOMMU operation being performed.
2548 * @param pMsiIn The source MSI.
2549 * @param pMsiOut Where to store the remapped MSI.
2550 *
2551 * @thread Any.
2552 */
2553static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2554{
2555 /* Read the device table entry from memory. */
2556 DTE_T Dte;
2557 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2558 if (RT_SUCCESS(rc))
2559 {
2560 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
2561 if (Dte.n.u1IntrMapValid)
2562 {
2563 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
2564 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
2565 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
2566 if (RT_LIKELY( !fRsvd0
2567 && !fRsvd1))
2568 { /* likely */ }
2569 else
2570 {
2571 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
2572 fRsvd1));
2573 EVT_ILLEGAL_DTE_T Event;
2574 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
2575 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2576 return VERR_IOMMU_INTR_REMAP_FAILED;
2577 }
2578
2579 /*
2580 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
2581 * that's connected through HyperTransport it might be possible; but for us, it
2582 * doesn't seem we need to specially handle these pins.
2583 */
2584
2585 /*
2586 * Validate the MSI source address.
2587 *
2588 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
2589 * CPU is concerned, the MSI region is fixed and we must ensure no other device
2590 * claims the region as I/O space.
2591 *
2592 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
2593 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
2594 * See Intel spec. 10.11.1 "Message Address Register Format".
2595 */
2596 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
2597 {
2598 /*
2599 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
2600 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
2601 */
2602 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
2603 bool fPassThru = false;
2604 switch (u8DeliveryMode)
2605 {
2606 case VBOX_MSI_DELIVERY_MODE_FIXED:
2607 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
2608 {
2609 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
2610 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
2611 {
2612 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
2613 iommuAmdSetPciTargetAbort(pDevIns);
2614 return VERR_IOMMU_INTR_REMAP_DENIED;
2615 }
2616
2617 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
2618 {
2619 fPassThru = true;
2620 break;
2621 }
2622
2623 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
2624 {
2625 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
2626 uint32_t const uIntTabLen = Dte.n.u4IntrTableLength;
2627 if (Dte.n.u4IntrTableLength < 12)
2628 {
2629 /*
2630 * We don't support guest interrupt remapping yet. When we do, we'll need to
2631 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
2632 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
2633 * already reads the control register, add that as a parameter when we eventually
2634 * support guest interrupt remapping. For now, just assert.
2635 */
2636 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2637 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
2638 NOREF(pThis);
2639
2640 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
2641 }
2642
2643 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntTabLen));
2644 EVT_ILLEGAL_DTE_T Event;
2645 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
2646 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
2647 return VERR_IOMMU_INTR_REMAP_FAILED;
2648 }
2649
2650 /* Paranoia. */
2651 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
2652
2653 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE", uIntrCtrl));
2654
2655 EVT_ILLEGAL_DTE_T Event;
2656 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
2657 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
2658 return VERR_IOMMU_INTR_REMAP_FAILED;
2659 }
2660
2661 /* SMIs are passed through unmapped. We don't implement SMI filters. */
2662 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
2663 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
2664 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
2665 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
2666 default:
2667 {
2668 LogFunc(("MSI data delivery mode invalid %#x -> Target abort", u8DeliveryMode));
2669 iommuAmdSetPciTargetAbort(pDevIns);
2670 return VERR_IOMMU_INTR_REMAP_FAILED;
2671 }
2672 }
2673
2674 if (fPassThru)
2675 {
2676 *pMsiOut = *pMsiIn;
2677 return VINF_SUCCESS;
2678 }
2679
2680 iommuAmdSetPciTargetAbort(pDevIns);
2681 return VERR_IOMMU_INTR_REMAP_DENIED;
2682 }
2683 else
2684 {
2685 LogFunc(("MSI address region invalid %#RX64.", pMsiIn->Addr.u64));
2686 return VERR_IOMMU_INTR_REMAP_FAILED;
2687 }
2688 }
2689 else
2690 {
2691 /** @todo IOMMU: Add to interrupt remapping cache. */
2692 *pMsiOut = *pMsiIn;
2693 return VINF_SUCCESS;
2694 }
2695 }
2696
2697 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2698 return VERR_IOMMU_INTR_REMAP_FAILED;
2699}
2700
2701
2702/**
2703 * Interrupt remap request from a device.
2704 *
2705 * @returns VBox status code.
2706 * @param pDevIns The IOMMU device instance.
2707 * @param uDevId The device ID (bus, device, function).
2708 * @param pMsiIn The source MSI.
2709 * @param pMsiOut Where to store the remapped MSI.
2710 */
2711static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2712{
2713 /* Validate. */
2714 Assert(pDevIns);
2715 Assert(pMsiIn);
2716 Assert(pMsiOut);
2717
2718 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2719 LogFlowFunc(("uDevId=%#x\n", uDevId));
2720
2721 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
2722 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2723 if (Ctrl.n.u1IommuEn)
2724 {
2725 /** @todo Cache? */
2726
2727 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
2728 }
2729
2730 *pMsiOut = *pMsiIn;
2731 return VINF_SUCCESS;
2732}
2733
2734
2735/**
2736 * @callback_method_impl{FNIOMMMIONEWWRITE}
2737 */
2738static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
2739{
2740 NOREF(pvUser);
2741 Assert(cb == 4 || cb == 8);
2742 Assert(!(off & (cb - 1)));
2743
2744 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
2745 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
2746}
2747
2748
2749/**
2750 * @callback_method_impl{FNIOMMMIONEWREAD}
2751 */
2752static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
2753{
2754 NOREF(pvUser);
2755 Assert(cb == 4 || cb == 8);
2756 Assert(!(off & (cb - 1)));
2757
2758 uint64_t uResult;
2759 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
2760 if (cb == 8)
2761 *(uint64_t *)pv = uResult;
2762 else
2763 *(uint32_t *)pv = (uint32_t)uResult;
2764
2765 return rcStrict;
2766}
2767
2768# ifdef IN_RING3
2769
2770/**
2771 * Processes an IOMMU command.
2772 *
2773 * @returns VBox status code.
2774 * @param pDevIns The IOMMU device instance.
2775 * @param pCmd The command to process.
2776 * @param GCPhysCmd The system physical address of the command.
2777 * @param pEvtError Where to store the error event in case of failures.
2778 *
2779 * @thread Command thread.
2780 */
2781static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
2782{
2783 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
2784
2785 LogFlowFunc(("\n"));
2786
2787 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2788 uint8_t const bCmd = pCmd->n.u4Opcode;
2789 switch (bCmd)
2790 {
2791 case IOMMU_CMD_COMPLETION_WAIT:
2792 {
2793 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
2794 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
2795
2796 /* Validate reserved bits in the command. */
2797 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
2798 {
2799 /* If Completion Store is requested, write the StoreData to the specified address.*/
2800 if (pCmdComWait->n.u1Store)
2801 {
2802 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
2803 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
2804 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
2805 if (RT_FAILURE(rc))
2806 {
2807 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
2808 GCPhysStore, rc));
2809 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
2810 return VERR_IOMMU_CMD_HW_ERROR;
2811 }
2812 }
2813
2814 IOMMU_LOCK(pDevIns);
2815
2816 /* Indicate that this command has completed. */
2817 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
2818
2819 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
2820 if (pCmdComWait->n.u1Interrupt)
2821 {
2822 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2823 if (Ctrl.n.u1CompWaitIntrEn)
2824 iommuAmdRaiseMsiInterrupt(pDevIns);
2825 }
2826
2827 IOMMU_UNLOCK(pDevIns);
2828 return VINF_SUCCESS;
2829 }
2830 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2831 return VERR_IOMMU_CMD_INVALID_FORMAT;
2832 }
2833
2834 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
2835 {
2836 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2837 * then. */
2838 return VINF_SUCCESS;
2839 }
2840
2841 case IOMMU_CMD_INV_IOMMU_PAGES:
2842 {
2843 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2844 * then. */
2845 return VINF_SUCCESS;
2846 }
2847
2848 case IOMMU_CMD_INV_IOTLB_PAGES:
2849 {
2850 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
2851 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
2852 {
2853 /** @todo IOMMU: Implement remote IOTLB invalidation. */
2854 return VERR_NOT_IMPLEMENTED;
2855 }
2856 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2857 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2858 }
2859
2860 case IOMMU_CMD_INV_INTR_TABLE:
2861 {
2862 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2863 * then. */
2864 return VINF_SUCCESS;
2865 }
2866
2867 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
2868 {
2869 if (pThis->ExtFeat.n.u1PrefetchSup)
2870 {
2871 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
2872 return VINF_SUCCESS;
2873 }
2874 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2875 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2876 }
2877
2878 case IOMMU_CMD_COMPLETE_PPR_REQ:
2879 {
2880 /* We don't support PPR requests yet. */
2881 Assert(!pThis->ExtFeat.n.u1PprSup);
2882 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2883 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2884 }
2885
2886 case IOMMU_CMD_INV_IOMMU_ALL:
2887 {
2888 if (pThis->ExtFeat.n.u1InvAllSup)
2889 {
2890 /** @todo IOMMU: Invalidate all. Pretend success until then. */
2891 return VINF_SUCCESS;
2892 }
2893 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2894 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2895 }
2896 }
2897
2898 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
2899 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2900 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2901}
2902
2903
2904/**
2905 * The IOMMU command thread.
2906 *
2907 * @returns VBox status code.
2908 * @param pDevIns The IOMMU device instance.
2909 * @param pThread The command thread.
2910 */
2911static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2912{
2913 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2914
2915 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2916 return VINF_SUCCESS;
2917
2918 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2919 {
2920 /*
2921 * Sleep perpetually until we are woken up to process commands.
2922 */
2923 {
2924 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
2925 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
2926 if (!fSignaled)
2927 {
2928 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
2929 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
2930 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2931 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2932 break;
2933 LogFlowFunc(("Woken up with rc=%Rrc\n", rc));
2934 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
2935 }
2936 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
2937 }
2938
2939 /*
2940 * Fetch and process IOMMU commands.
2941 */
2942 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
2943 * at a time) and is expensive due to calls to PGM for fetching guest memory.
2944 * We could optimize by fetching a bunch of commands at a time reducing
2945 * number of calls to PGM. In the longer run we could lock the memory and
2946 * mappings and accessing them directly. */
2947 IOMMU_LOCK(pDevIns);
2948
2949 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2950 if (Status.n.u1CmdBufRunning)
2951 {
2952 LogFlowFunc(("Command buffer running\n"));
2953
2954 /* Get the offset we need to read the command from memory (circular buffer offset). */
2955 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2956 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
2957 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
2958 Assert(offHead < cbCmdBuf);
2959 while (offHead != pThis->CmdBufTailPtr.n.off)
2960 {
2961 /* Read the command from memory. */
2962 CMD_GENERIC_T Cmd;
2963 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
2964 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
2965 if (RT_SUCCESS(rc))
2966 {
2967 /* Increment the command buffer head pointer. */
2968 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
2969 pThis->CmdBufHeadPtr.n.off = offHead;
2970
2971 /* Process the fetched command. */
2972 EVT_GENERIC_T EvtError;
2973 IOMMU_UNLOCK(pDevIns);
2974 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
2975 IOMMU_LOCK(pDevIns);
2976 if (RT_FAILURE(rc))
2977 {
2978 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
2979 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
2980 {
2981 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
2982 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
2983 }
2984 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
2985 {
2986 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2987 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
2988 }
2989 break;
2990 }
2991 }
2992 else
2993 {
2994 EVT_CMD_HW_ERR_T EvtCmdHwErr;
2995 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
2996 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
2997 break;
2998 }
2999 }
3000 }
3001
3002 IOMMU_UNLOCK(pDevIns);
3003 }
3004
3005 LogFlowFunc(("Command thread terminating\n"));
3006 return VINF_SUCCESS;
3007}
3008
3009
3010/**
3011 * Wakes up the command thread so it can respond to a state change.
3012 *
3013 * @returns VBox status code.
3014 * @param pDevIns The IOMMU device instance.
3015 * @param pThread The command thread.
3016 */
3017static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3018{
3019 RT_NOREF(pThread);
3020 LogFlowFunc(("\n"));
3021 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3022 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3023}
3024
3025
3026/**
3027 * @callback_method_impl{FNPCICONFIGREAD}
3028 */
3029static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3030 unsigned cb, uint32_t *pu32Value)
3031{
3032 /** @todo IOMMU: PCI config read stat counter. */
3033 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3034 Log3Func(("Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
3035 VBOXSTRICTRC_VAL(rcStrict)));
3036 return rcStrict;
3037}
3038
3039
3040/**
3041 * @callback_method_impl{FNPCICONFIGWRITE}
3042 */
3043static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3044 unsigned cb, uint32_t u32Value)
3045{
3046 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3047
3048 /*
3049 * Discard writes to read-only registers that are specific to the IOMMU.
3050 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3051 * See PCI spec. 6.1. "Configuration Space Organization".
3052 */
3053 switch (uAddress)
3054 {
3055 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3056 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3057 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3058 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3059 {
3060 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3061 return VINF_SUCCESS;
3062 }
3063 }
3064
3065 IOMMU_LOCK(pDevIns);
3066
3067 VBOXSTRICTRC rcStrict = VERR_INVALID_FUNCTION;
3068 switch (uAddress)
3069 {
3070 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3071 {
3072 if (pThis->IommuBar.n.u1Enable)
3073 {
3074 rcStrict = VINF_SUCCESS;
3075 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3076 break;
3077 }
3078
3079 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3080 if (pThis->IommuBar.n.u1Enable)
3081 {
3082 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE);
3083 Assert(PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio) == NIL_RTGCPHYS);
3084 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3085 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3086 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3087 if (RT_FAILURE(rcStrict))
3088 LogFunc(("Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
3089 }
3090 break;
3091 }
3092
3093 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3094 {
3095 if (!pThis->IommuBar.n.u1Enable)
3096 pThis->IommuBar.au32[1] = u32Value;
3097 else
3098 {
3099 rcStrict = VINF_SUCCESS;
3100 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3101 }
3102 break;
3103 }
3104
3105 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3106 {
3107 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3108 RT_FALL_THRU();
3109 }
3110 default:
3111 {
3112 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3113 break;
3114 }
3115 }
3116
3117 IOMMU_UNLOCK(pDevIns);
3118
3119 Log3Func(("PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
3120 return rcStrict;
3121}
3122
3123
3124/**
3125 * @callback_method_impl{FNDBGFHANDLERDEV}
3126 */
3127static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3128{
3129 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3130 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3131 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3132
3133 LogFlowFunc(("pThis=%p pszArgs=%s\n", pThis, pszArgs));
3134 bool const fVerbose = !strncmp(pszArgs, RT_STR_TUPLE("verbose")) ? true : false;
3135
3136 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3137 /* Device Table Base Addresses (all segments). */
3138 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3139 {
3140 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3141 pHlp->pfnPrintf(pHlp, " Device Table BAR [%u] = %#RX64\n", i, DevTabBar.u64);
3142 if (fVerbose)
3143 {
3144 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3145 IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
3146 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3147 }
3148 }
3149 /* Command Buffer Base Address Register. */
3150 {
3151 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3152 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3153 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3154 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3155 pHlp->pfnPrintf(pHlp, " Command buffer BAR = %#RX64\n", CmdBufBar.u64);
3156 if (fVerbose)
3157 {
3158 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3159 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3160 cEntries, cbBuffer);
3161 }
3162 }
3163 /* Event Log Base Address Register. */
3164 {
3165 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3166 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3167 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3168 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3169 pHlp->pfnPrintf(pHlp, " Event log BAR = %#RX64\n", EvtLogBar.u64);
3170 if (fVerbose)
3171 {
3172 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3173 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3174 cEntries, cbBuffer);
3175 }
3176 }
3177 /* IOMMU Control Register. */
3178 {
3179 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3180 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3181 if (fVerbose)
3182 {
3183 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3184 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3185 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3186 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3187 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3188 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3189 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3190 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3191 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3192 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3193 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3194 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3195 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3196 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3197 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3198 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3199 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3200 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3201 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3202 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3203 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3204 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3205 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3206 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3207 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3208 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3209 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3210 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3211 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3212 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3213 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3214 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3215 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3216 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3217 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3218 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3219 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3220 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3221 }
3222 }
3223 /* Exclusion Base Address Register. */
3224 {
3225 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3226 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3227 if (fVerbose)
3228 {
3229 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3230 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3231 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
3232 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
3233 }
3234 }
3235 /* Exclusion Range Limit Register. */
3236 {
3237 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3238 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3239 if (fVerbose)
3240 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
3241 }
3242 /* Extended Feature Register. */
3243 {
3244 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3245 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3246 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3247 if (fVerbose)
3248 {
3249 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3250 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3251 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3252 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3253 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3254 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3255 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3256 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3257 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3258 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3259 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3260 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3261 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3262 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3263 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3264 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3265 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3266 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3267 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
3268 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
3269 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3270 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3271 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3272 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3273 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3274 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3275 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3276 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3277 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3278 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3279 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3280 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3281 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3282 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3283 }
3284 }
3285 /* PPR Log Base Address Register. */
3286 {
3287 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3288 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
3289 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3290 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3291 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3292 if (fVerbose)
3293 {
3294 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3295 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3296 cEntries, cbBuffer);
3297 }
3298 }
3299 /* Hardware Event (Hi) Register. */
3300 {
3301 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
3302 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
3303 if (fVerbose)
3304 {
3305 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
3306 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
3307 }
3308 }
3309 /* Hardware Event (Lo) Register. */
3310 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
3311 /* Hardware Event Status. */
3312 {
3313 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
3314 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
3315 if (fVerbose)
3316 {
3317 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
3318 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
3319 }
3320 }
3321 /* Guest Virtual-APIC Log Base Address Register. */
3322 {
3323 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
3324 uint8_t const uEncodedLen = GALogBar.n.u4Len;
3325 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3326 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3327 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
3328 if (fVerbose)
3329 {
3330 pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3331 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3332 cEntries, cbBuffer);
3333 }
3334 }
3335 /* Guest Virtual-APIC Log Tail Address Register. */
3336 {
3337 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
3338 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
3339 if (fVerbose)
3340 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
3341 }
3342 /* PPR Log B Base Address Register. */
3343 {
3344 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
3345 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
3346 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3347 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3348 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
3349 if (fVerbose)
3350 {
3351 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3352 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3353 cEntries, cbBuffer);
3354 }
3355 }
3356 /* Event Log B Base Address Register. */
3357 {
3358 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
3359 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
3360 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3361 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3362 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
3363 if (fVerbose)
3364 {
3365 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3366 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3367 cEntries, cbBuffer);
3368 }
3369 }
3370 /* Device-Specific Feature Extension Register. */
3371 {
3372 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
3373 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
3374 if (fVerbose)
3375 {
3376 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
3377 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
3378 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
3379 }
3380 }
3381 /* Device-Specific Control Extension Register. */
3382 {
3383 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
3384 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
3385 if (fVerbose)
3386 {
3387 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
3388 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
3389 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
3390 }
3391 }
3392 /* Device-Specific Status Extension Register. */
3393 {
3394 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
3395 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificStatus.u64);
3396 if (fVerbose)
3397 {
3398 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
3399 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
3400 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
3401 }
3402 }
3403 /* Miscellaneous Information Register (Lo and Hi). */
3404 {
3405 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
3406 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
3407 if (fVerbose)
3408 {
3409 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
3410 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
3411 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
3412 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
3413 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
3414 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
3415 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
3416 }
3417 }
3418 /* MSI Capability Header. */
3419 {
3420 MSI_CAP_HDR_T MsiCapHdr;
3421 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3422 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
3423 if (fVerbose)
3424 {
3425 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
3426 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
3427 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
3428 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
3429 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
3430 }
3431 }
3432 /* MSI Address Register (Lo and Hi). */
3433 {
3434 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3435 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3436 MSIADDR MsiAddr;
3437 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
3438 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
3439 if (fVerbose)
3440 {
3441 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
3442 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
3443 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
3444 pHlp->pfnPrintf(pHlp, " Address = %#Rx32\n", MsiAddr.n.u12Addr);
3445 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#Rx32\n", MsiAddr.n.u32Rsvd0);
3446 }
3447 }
3448 /* MSI Data. */
3449 {
3450 MSIDATA MsiData;
3451 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3452 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
3453 if (fVerbose)
3454 {
3455 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
3456 MsiData.n.u8Vector);
3457 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
3458 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
3459 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
3460 "level" : "edge");
3461 }
3462 }
3463 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
3464 {
3465 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
3466 MsiMapCapHdr.u32 = 0;
3467 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
3468 if (fVerbose)
3469 {
3470 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
3471 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
3472 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
3473 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
3474 }
3475 }
3476 /* Performance Optimization Control Register. */
3477 {
3478 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
3479 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
3480 if (fVerbose)
3481 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
3482 }
3483 /* XT (x2APIC) General Interrupt Control Register. */
3484 {
3485 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
3486 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
3487 if (fVerbose)
3488 {
3489 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3490 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3491 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3492 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
3493 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
3494 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3495 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3496 }
3497 }
3498 /* XT (x2APIC) PPR Interrupt Control Register. */
3499 {
3500 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
3501 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
3502 if (fVerbose)
3503 {
3504 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3505 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3506 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3507 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
3508 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
3509 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3510 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3511 }
3512 }
3513 /* XT (X2APIC) GA Log Interrupt Control Register. */
3514 {
3515 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
3516 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
3517 if (fVerbose)
3518 {
3519 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3520 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3521 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3522 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
3523 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
3524 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %#x\n",
3525 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3526 }
3527 }
3528 /* MARC Registers. */
3529 {
3530 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
3531 {
3532 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
3533 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
3534 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
3535
3536 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
3537 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
3538 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
3539 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
3540
3541 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
3542 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
3543 }
3544 }
3545 /* Reserved Register. */
3546 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
3547 /* Command Buffer Head Pointer Register. */
3548 {
3549 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
3550 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64\n", CmdBufHeadPtr.u64);
3551 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufHeadPtr.n.off);
3552 }
3553 /* Command Buffer Tail Pointer Register. */
3554 {
3555 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
3556 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64\n", CmdBufTailPtr.u64);
3557 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", CmdBufTailPtr.n.off);
3558 }
3559 /* Event Log Head Pointer Register. */
3560 {
3561 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
3562 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogHeadPtr.u64);
3563 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogHeadPtr.n.off);
3564 }
3565 /* Event Log Tail Pointer Register. */
3566 {
3567 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
3568 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64\n", EvtLogTailPtr.u64);
3569 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogTailPtr.n.off);
3570 }
3571 /* Status Register. */
3572 {
3573 IOMMU_STATUS_T const Status = pThis->Status;
3574 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
3575 if (fVerbose)
3576 {
3577 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
3578 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
3579 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
3580 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
3581 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
3582 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
3583 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
3584 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
3585 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
3586 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
3587 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
3588 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
3589 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
3590 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
3591 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
3592 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
3593 }
3594 }
3595 /* PPR Log Head Pointer. */
3596 {
3597 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
3598 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64\n", PprLogHeadPtr.u64);
3599 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogHeadPtr.n.off);
3600 }
3601 /* PPR Log Tail Pointer. */
3602 {
3603 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
3604 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64\n", PprLogTailPtr.u64);
3605 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogTailPtr.n.off);
3606 }
3607 /* Guest Virtual-APIC Log Head Pointer. */
3608 {
3609 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
3610 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64\n", GALogHeadPtr.u64);
3611 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogHeadPtr.n.u12GALogPtr);
3612 }
3613 /* Guest Virtual-APIC Log Tail Pointer. */
3614 {
3615 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
3616 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64\n", GALogTailPtr.u64);
3617 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", GALogTailPtr.n.u12GALogPtr);
3618 }
3619 /* PPR Log B Head Pointer. */
3620 {
3621 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
3622 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64\n", PprLogBHeadPtr.u64);
3623 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBHeadPtr.n.off);
3624 }
3625 /* PPR Log B Tail Pointer. */
3626 {
3627 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
3628 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64\n", PprLogBTailPtr.u64);
3629 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", PprLogBTailPtr.n.off);
3630 }
3631 /* Event Log B Head Pointer. */
3632 {
3633 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
3634 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64\n", EvtLogBHeadPtr.u64);
3635 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBHeadPtr.n.off);
3636 }
3637 /* Event Log B Tail Pointer. */
3638 {
3639 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
3640 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64\n", EvtLogBTailPtr.u64);
3641 pHlp->pfnPrintf(pHlp, " Pointer = %#x\n", EvtLogBTailPtr.n.off);
3642 }
3643 /* PPR Log Auto Response Register. */
3644 {
3645 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
3646 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
3647 if (fVerbose)
3648 {
3649 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
3650 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
3651 }
3652 }
3653 /* PPR Log Overflow Early Warning Indicator Register. */
3654 {
3655 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
3656 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
3657 if (fVerbose)
3658 {
3659 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
3660 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
3661 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
3662 }
3663 }
3664 /* PPR Log Overflow Early Warning Indicator Register. */
3665 {
3666 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
3667 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
3668 if (fVerbose)
3669 {
3670 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
3671 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
3672 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
3673 }
3674 }
3675}
3676
3677
3678/**
3679 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3680 */
3681static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3682{
3683 /** @todo IOMMU: Save state. */
3684 RT_NOREF2(pDevIns, pSSM);
3685 LogFlowFunc(("\n"));
3686 return VERR_NOT_IMPLEMENTED;
3687}
3688
3689
3690/**
3691 * @callback_method_impl{FNSSMDEVLOADEXEC}
3692 */
3693static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3694{
3695 /** @todo IOMMU: Load state. */
3696 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
3697 LogFlowFunc(("\n"));
3698 return VERR_NOT_IMPLEMENTED;
3699}
3700
3701
3702/**
3703 * @interface_method_impl{PDMDEVREG,pfnReset}
3704 */
3705static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
3706{
3707 /*
3708 * Resets read-write portion of the IOMMU state.
3709 *
3710 * State data not initialized here is expected to be initialized during
3711 * device construction and remain read-only through the lifetime of the VM.
3712 */
3713 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3714 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3715 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3716
3717 LogFlowFunc(("\n"));
3718
3719 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
3720
3721 pThis->CmdBufBaseAddr.u64 = 0;
3722 pThis->CmdBufBaseAddr.n.u4Len = 8;
3723
3724 pThis->EvtLogBaseAddr.u64 = 0;
3725 pThis->EvtLogBaseAddr.n.u4Len = 8;
3726
3727 pThis->Ctrl.u64 = 0;
3728 pThis->Ctrl.n.u1Coherent = 1;
3729 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
3730
3731 pThis->ExclRangeBaseAddr.u64 = 0;
3732 pThis->ExclRangeLimit.u64 = 0;
3733
3734 pThis->PprLogBaseAddr.u64 = 0;
3735 pThis->PprLogBaseAddr.n.u4Len = 8;
3736
3737 pThis->HwEvtHi.u64 = 0;
3738 pThis->HwEvtLo = 0;
3739 pThis->HwEvtStatus.u64 = 0;
3740
3741 pThis->GALogBaseAddr.u64 = 0;
3742 pThis->GALogBaseAddr.n.u4Len = 8;
3743 pThis->GALogTailAddr.u64 = 0;
3744
3745 pThis->PprLogBBaseAddr.u64 = 0;
3746 pThis->PprLogBBaseAddr.n.u4Len = 8;
3747
3748 pThis->EvtLogBBaseAddr.u64 = 0;
3749 pThis->EvtLogBBaseAddr.n.u4Len = 8;
3750
3751 pThis->PerfOptCtrl.u32 = 0;
3752
3753 pThis->XtGenIntrCtrl.u64 = 0;
3754 pThis->XtPprIntrCtrl.u64 = 0;
3755 pThis->XtGALogIntrCtrl.u64 = 0;
3756
3757 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
3758
3759 pThis->CmdBufHeadPtr.u64 = 0;
3760 pThis->CmdBufTailPtr.u64 = 0;
3761 pThis->EvtLogHeadPtr.u64 = 0;
3762 pThis->EvtLogTailPtr.u64 = 0;
3763
3764 pThis->Status.u64 = 0;
3765
3766 pThis->PprLogHeadPtr.u64 = 0;
3767 pThis->PprLogTailPtr.u64 = 0;
3768
3769 pThis->GALogHeadPtr.u64 = 0;
3770 pThis->GALogTailPtr.u64 = 0;
3771
3772 pThis->PprLogBHeadPtr.u64 = 0;
3773 pThis->PprLogBTailPtr.u64 = 0;
3774
3775 pThis->EvtLogBHeadPtr.u64 = 0;
3776 pThis->EvtLogBTailPtr.u64 = 0;
3777
3778 pThis->PprLogAutoResp.u64 = 0;
3779 pThis->PprLogOverflowEarly.u64 = 0;
3780 pThis->PprLogBOverflowEarly.u64 = 0;
3781
3782 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
3783 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
3784
3785 /*
3786 * I ASSUME all MMIO regions mapped by a PDM device are automatically unmapped
3787 * on VM reset. If not, we need to enable the following...
3788 */
3789#if 0
3790 /* Unmap the MMIO region on reset if it has been mapped previously. */
3791 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE);
3792 if (PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio) != NIL_RTGCPHYS)
3793 PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3794#endif
3795}
3796
3797
3798/**
3799 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3800 */
3801static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
3802{
3803 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3804 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3805 LogFlowFunc(("\n"));
3806
3807 /* Close the command thread semaphore. */
3808 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
3809 {
3810 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
3811 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
3812 }
3813 return VINF_SUCCESS;
3814}
3815
3816
3817/**
3818 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3819 */
3820static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3821{
3822 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3823 RT_NOREF(pCfg);
3824
3825 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3826 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3827 pThisCC->pDevInsR3 = pDevIns;
3828
3829 LogFlowFunc(("iInstance=%d\n", iInstance));
3830
3831 /*
3832 * Register the IOMMU with PDM.
3833 */
3834 PDMIOMMUREGR3 IommuReg;
3835 RT_ZERO(IommuReg);
3836 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3837 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
3838 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
3839 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
3840 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3841 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3842 if (RT_FAILURE(rc))
3843 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3844 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3845 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3846 N_("IOMMU helper version mismatch; got %#x expected %#x"),
3847 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3848 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3849 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3850 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3851 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3852
3853 /*
3854 * Initialize read-only PCI configuration space.
3855 */
3856 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3857 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3858
3859 /* Header. */
3860 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
3861 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
3862 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we write to main memory). */
3863 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Status - CapList supported */
3864 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3865 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
3866 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
3867 PDMPciDevSetClassProg(pPciDev, 0x00); /* IOMMU Programming interface */
3868 PDMPciDevSetHeaderType(pPciDev, 0x00); /* Single function, type 0. */
3869 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
3870 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
3871 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers. */
3872 PDMPciDevSetInterruptPin(pPciDev, 0x01); /* INTA#. */
3873 PDMPciDevSetInterruptLine(pPciDev, 0x00); /* For software compatibility; no effect on hardware. */
3874
3875 /* Capability Header. */
3876 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
3877 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
3878 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
3879 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
3880 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
3881 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
3882 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
3883 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
3884 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
3885 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
3886 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
3887
3888 /* Base Address Low Register. */
3889 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit. */
3890
3891 /* Base Address High Register. */
3892 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
3893
3894 /* IOMMU Range Register. */
3895 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us). */
3896
3897 /* Misc. Information Register. */
3898 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
3899 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
3900 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
3901 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
3902 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
3903 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
3904 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
3905 uint32_t const uMiscInfoReg1 = 0;
3906 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
3907 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
3908
3909 /* MSI Capability Header register. */
3910 PDMMSIREG MsiReg;
3911 RT_ZERO(MsiReg);
3912 MsiReg.cMsiVectors = 1;
3913 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
3914 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
3915 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
3916
3917 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
3918#if 0
3919 /* MSI Address Lo. */
3920 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo). */
3921 /* MSI Address Hi. */
3922 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi). */
3923 /* MSI Data. */
3924 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data. */
3925#endif
3926
3927#if 0
3928 /** @todo IOMMU: I don't know if we need to support this, enable later if
3929 * required. */
3930 /* MSI Mapping Capability Header register. */
3931 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
3932 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
3933 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
3934 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
3935 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
3936 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
3937 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
3938#endif
3939
3940 /*
3941 * Register the PCI function with PDM.
3942 */
3943 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3944 AssertLogRelRCReturn(rc, rc);
3945
3946 /*
3947 * Register MSI support for the PCI device.
3948 * This must be done -after- register it as a PCI device!
3949 */
3950 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3951 AssertRCReturn(rc, rc);
3952
3953 /*
3954 * Intercept PCI config. space accesses.
3955 */
3956 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
3957 AssertLogRelRCReturn(rc, rc);
3958
3959 /*
3960 * Create the MMIO region.
3961 * Mapping of the region is done when software configures it via PCI config space.
3962 */
3963 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
3964 NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
3965 "AMD-IOMMU", &pThis->hMmio);
3966 AssertLogRelRCReturn(rc, rc);
3967
3968 /*
3969 * Register saved state.
3970 */
3971 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
3972 NULL, NULL, NULL,
3973 NULL, iommuAmdR3SaveExec, NULL,
3974 NULL, iommuAmdR3LoadExec, NULL);
3975 AssertLogRelRCReturn(rc, rc);
3976
3977 /*
3978 * Register debugger info item.
3979 */
3980 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
3981 AssertLogRelRCReturn(rc, rc);
3982
3983 /*
3984 * Create the command thread and its event semaphore.
3985 */
3986 char szDevIommu[64];
3987 RT_ZERO(szDevIommu);
3988 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
3989 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
3990 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
3991 AssertLogRelRCReturn(rc, rc);
3992
3993 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
3994 AssertLogRelRCReturn(rc, rc);
3995
3996 /*
3997 * Initialize read-only registers.
3998 * NOTE! Fields here must match their corresponding field in the ACPI tables.
3999 */
4000 /** @todo Don't remove the =0 assignment for now. It's just there so it's easier
4001 * for me to see existing features that we might want to implement. Do it
4002 * later. */
4003 pThis->ExtFeat.u64 = 0;
4004 pThis->ExtFeat.n.u1PrefetchSup = 0;
4005 pThis->ExtFeat.n.u1PprSup = 0;
4006 pThis->ExtFeat.n.u1X2ApicSup = 0;
4007 pThis->ExtFeat.n.u1NoExecuteSup = 0;
4008 pThis->ExtFeat.n.u1GstTranslateSup = 0;
4009 pThis->ExtFeat.n.u1InvAllSup = 0;
4010 pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4011 pThis->ExtFeat.n.u1HwErrorSup = 1;
4012 pThis->ExtFeat.n.u1PerfCounterSup = 0;
4013 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4014 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4015 pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup. */
4016 pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup. */
4017 pThis->ExtFeat.n.u2SmiFilterSup = 0;
4018 pThis->ExtFeat.n.u3SmiFilterCount = 0;
4019 pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
4020 pThis->ExtFeat.n.u2DualPprLogSup = 0;
4021 pThis->ExtFeat.n.u2DualEvtLogSup = 0;
4022 pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup. */
4023 pThis->ExtFeat.n.u1UserSupervisorSup = 0;
4024 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
4025 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
4026 pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
4027 pThis->ExtFeat.n.u1PprAutoRespSup = 0;
4028 pThis->ExtFeat.n.u2MarcSup = 0;
4029 pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
4030 pThis->ExtFeat.n.u1PerfOptSup = 0;
4031 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
4032 pThis->ExtFeat.n.u1GstIoSup = 0;
4033 pThis->ExtFeat.n.u1HostAccessSup = 0;
4034 pThis->ExtFeat.n.u1EnhancedPprSup = 0;
4035 pThis->ExtFeat.n.u1AttrForwardSup = 0;
4036 pThis->ExtFeat.n.u1HostDirtySup = 0;
4037 pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
4038 pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
4039 pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
4040
4041 pThis->RsvdReg = 0;
4042
4043 pThis->DevSpecificFeat.u64 = 0;
4044 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
4045 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
4046
4047 pThis->DevSpecificCtrl.u64 = 0;
4048 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
4049 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
4050
4051 pThis->DevSpecificStatus.u64 = 0;
4052 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
4053 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
4054
4055 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
4056
4057 /*
4058 * Initialize parts of the IOMMU state as it would during reset.
4059 * Must be called -after- initializing PCI config. space registers.
4060 */
4061 iommuAmdR3Reset(pDevIns);
4062
4063 return VINF_SUCCESS;
4064}
4065
4066# else /* !IN_RING3 */
4067
4068/**
4069 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4070 */
4071static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
4072{
4073 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4074 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4075 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4076
4077 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4078
4079 /* Set up the MMIO RZ handlers. */
4080 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
4081 AssertRCReturn(rc, rc);
4082
4083 /* Set up the IOMMU RZ callbacks. */
4084 PDMIOMMUREGCC IommuReg;
4085 RT_ZERO(IommuReg);
4086 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4087 IommuReg.idxIommu = pThis->idxIommu;
4088 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4089 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4090 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4091 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4092 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4093 AssertRCReturn(rc, rc);
4094
4095 return VINF_SUCCESS;
4096}
4097
4098# endif /* !IN_RING3 */
4099
4100/**
4101 * The device registration structure.
4102 */
4103const PDMDEVREG g_DeviceIommuAmd =
4104{
4105 /* .u32Version = */ PDM_DEVREG_VERSION,
4106 /* .uReserved0 = */ 0,
4107 /* .szName = */ "iommu-amd",
4108 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4109 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4110 /* .cMaxInstances = */ ~0U,
4111 /* .uSharedVersion = */ 42,
4112 /* .cbInstanceShared = */ sizeof(IOMMU),
4113 /* .cbInstanceCC = */ sizeof(IOMMUCC),
4114 /* .cbInstanceRC = */ sizeof(IOMMURC),
4115 /* .cMaxPciDevices = */ 1,
4116 /* .cMaxMsixVectors = */ 0,
4117 /* .pszDescription = */ "IOMMU (AMD)",
4118#if defined(IN_RING3)
4119 /* .pszRCMod = */ "VBoxDDRC.rc",
4120 /* .pszR0Mod = */ "VBoxDDR0.r0",
4121 /* .pfnConstruct = */ iommuAmdR3Construct,
4122 /* .pfnDestruct = */ iommuAmdR3Destruct,
4123 /* .pfnRelocate = */ NULL,
4124 /* .pfnMemSetup = */ NULL,
4125 /* .pfnPowerOn = */ NULL,
4126 /* .pfnReset = */ iommuAmdR3Reset,
4127 /* .pfnSuspend = */ NULL,
4128 /* .pfnResume = */ NULL,
4129 /* .pfnAttach = */ NULL,
4130 /* .pfnDetach = */ NULL,
4131 /* .pfnQueryInterface = */ NULL,
4132 /* .pfnInitComplete = */ NULL,
4133 /* .pfnPowerOff = */ NULL,
4134 /* .pfnSoftReset = */ NULL,
4135 /* .pfnReserved0 = */ NULL,
4136 /* .pfnReserved1 = */ NULL,
4137 /* .pfnReserved2 = */ NULL,
4138 /* .pfnReserved3 = */ NULL,
4139 /* .pfnReserved4 = */ NULL,
4140 /* .pfnReserved5 = */ NULL,
4141 /* .pfnReserved6 = */ NULL,
4142 /* .pfnReserved7 = */ NULL,
4143#elif defined(IN_RING0)
4144 /* .pfnEarlyConstruct = */ NULL,
4145 /* .pfnConstruct = */ iommuAmdRZConstruct,
4146 /* .pfnDestruct = */ NULL,
4147 /* .pfnFinalDestruct = */ NULL,
4148 /* .pfnRequest = */ NULL,
4149 /* .pfnReserved0 = */ NULL,
4150 /* .pfnReserved1 = */ NULL,
4151 /* .pfnReserved2 = */ NULL,
4152 /* .pfnReserved3 = */ NULL,
4153 /* .pfnReserved4 = */ NULL,
4154 /* .pfnReserved5 = */ NULL,
4155 /* .pfnReserved6 = */ NULL,
4156 /* .pfnReserved7 = */ NULL,
4157#elif defined(IN_RC)
4158 /* .pfnConstruct = */ iommuAmdRZConstruct,
4159 /* .pfnReserved0 = */ NULL,
4160 /* .pfnReserved1 = */ NULL,
4161 /* .pfnReserved2 = */ NULL,
4162 /* .pfnReserved3 = */ NULL,
4163 /* .pfnReserved4 = */ NULL,
4164 /* .pfnReserved5 = */ NULL,
4165 /* .pfnReserved6 = */ NULL,
4166 /* .pfnReserved7 = */ NULL,
4167#else
4168# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4169#endif
4170 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4171};
4172
4173#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4174
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette