VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86075

Last change on this file since 86075 was 86075, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Set the ComWaitInt bit in the Status register only when the COMPLETION_WAIT command requests it explicitly.
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1/* $Id: DevIommuAmd.cpp 86075 2020-09-09 15:23:22Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/string.h>
30
31#include "VBoxDD.h"
32#include "DevIommuAmd.h"
33
34
35/*********************************************************************************************************************************
36* Defined Constants And Macros *
37*********************************************************************************************************************************/
38/** Release log prefix string. */
39#define IOMMU_LOG_PFX "IOMMU-AMD"
40/** The current saved state version. */
41#define IOMMU_SAVED_STATE_VERSION 1
42/** The IOTLB entry magic. */
43#define IOMMU_IOTLBE_MAGIC 0x10acce55
44
45
46/*********************************************************************************************************************************
47* Structures and Typedefs *
48*********************************************************************************************************************************/
49/**
50 * Acquires the IOMMU PDM lock.
51 * This will make a long jump to ring-3 to acquire the lock if necessary.
52 */
53#define IOMMU_LOCK(a_pDevIns) \
54 do { \
55 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
56 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
57 { /* likely */ } \
58 else \
59 return rcLock; \
60 } while (0)
61
62/**
63 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
64 * This will make a long jump to ring-3 to acquire the lock if necessary.
65 */
66#define IOMMU_LOCK_NORET(a_pDevIns) \
67 do { \
68 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
69 AssertRC(rcLock); \
70 } while (0)
71
72/**
73 * Releases the IOMMU PDM lock.
74 */
75#define IOMMU_UNLOCK(a_pDevIns) \
76 do { \
77 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
78 } while (0)
79
80/**
81 * Asserts that the critsect is owned by this thread.
82 */
83#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
84 do { \
85 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
86 } while (0)
87
88/**
89 * Asserts that the critsect is not owned by this thread.
90 */
91#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
92 do { \
93 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
94 } while (0)
95
96/**
97 * IOMMU operations (transaction) types.
98 */
99typedef enum IOMMUOP
100{
101 /** Address translation request. */
102 IOMMUOP_TRANSLATE_REQ = 0,
103 /** Memory read request. */
104 IOMMUOP_MEM_READ,
105 /** Memory write request. */
106 IOMMUOP_MEM_WRITE,
107 /** Interrupt request. */
108 IOMMUOP_INTR_REQ,
109 /** Command. */
110 IOMMUOP_CMD
111} IOMMUOP;
112AssertCompileSize(IOMMUOP, 4);
113
114/**
115 * I/O page walk result.
116 */
117typedef struct
118{
119 /** The translated system physical address. */
120 RTGCPHYS GCPhysSpa;
121 /** The number of offset bits in the system physical address. */
122 uint8_t cShift;
123 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
124 uint8_t fIoPerm;
125 /** Padding. */
126 uint8_t abPadding[2];
127} IOWALKRESULT;
128/** Pointer to an I/O walk result struct. */
129typedef IOWALKRESULT *PIOWALKRESULT;
130/** Pointer to a const I/O walk result struct. */
131typedef IOWALKRESULT *PCIOWALKRESULT;
132
133/**
134 * IOMMU I/O TLB Entry.
135 * Keep this as small and aligned as possible.
136 */
137typedef struct
138{
139 /** The translated system physical address (SPA) of the page. */
140 RTGCPHYS GCPhysSpa;
141 /** The index of the 4K page within a large page. */
142 uint32_t idxSubPage;
143 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
144 uint8_t fIoPerm;
145 /** The number of offset bits in the translation indicating page size. */
146 uint8_t cShift;
147 /** Alignment padding. */
148 uint8_t afPadding[2];
149} IOTLBE_T;
150AssertCompileSize(IOTLBE_T, 16);
151/** Pointer to an IOMMU I/O TLB entry struct. */
152typedef IOTLBE_T *PIOTLBE_T;
153/** Pointer to a const IOMMU I/O TLB entry struct. */
154typedef IOTLBE_T const *PCIOTLBE_T;
155
156/**
157 * The shared IOMMU device state.
158 */
159typedef struct IOMMU
160{
161 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
162 uint32_t idxIommu;
163 /** Alignment padding. */
164 uint32_t uPadding0;
165
166 /** Whether the command thread is sleeping. */
167 bool volatile fCmdThreadSleeping;
168 /** Alignment padding. */
169 uint8_t afPadding0[3];
170 /** Whether the command thread has been signaled for wake up. */
171 bool volatile fCmdThreadSignaled;
172 /** Alignment padding. */
173 uint8_t afPadding1[3];
174
175 /** The event semaphore the command thread waits on. */
176 SUPSEMEVENT hEvtCmdThread;
177 /** The MMIO handle. */
178 IOMMMIOHANDLE hMmio;
179
180 /** @name PCI: Base capability block registers.
181 * @{ */
182 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
183 /** @} */
184
185 /** @name MMIO: Control and status registers.
186 * @{ */
187 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
188 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
189 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
190 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
191 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
192 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
193 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
194 /** @} */
195
196 /** @name MMIO: PPR Log registers.
197 * @{ */
198 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
199 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
200 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
201 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
202 /** @} */
203
204 /** @todo IOMMU: SMI filter. */
205
206 /** @name MMIO: Guest Virtual-APIC Log registers.
207 * @{ */
208 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
209 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
210 /** @} */
211
212 /** @name MMIO: Alternate PPR and Event Log registers.
213 * @{ */
214 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
215 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
216 /** @} */
217
218 /** @name MMIO: Device-specific feature registers.
219 * @{ */
220 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
221 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
222 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
223 /** @} */
224
225 /** @name MMIO: MSI Capability Block registers.
226 * @{ */
227 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
228 /** @} */
229
230 /** @name MMIO: Performance Optimization Control registers.
231 * @{ */
232 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
233 /** @} */
234
235 /** @name MMIO: x2APIC Control registers.
236 * @{ */
237 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
238 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
239 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
240 /** @} */
241
242 /** @name MMIO: MARC registers.
243 * @{ */
244 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
245 /** @} */
246
247 /** @name MMIO: Reserved register.
248 * @{ */
249 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
250 /** @} */
251
252 /** @name MMIO: Command and Event Log pointer registers.
253 * @{ */
254 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
255 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
256 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
257 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
258 /** @} */
259
260 /** @name MMIO: Command and Event Status register.
261 * @{ */
262 IOMMU_STATUS_T Status; /**< IOMMU status register. */
263 /** @} */
264
265 /** @name MMIO: PPR Log Head and Tail pointer registers.
266 * @{ */
267 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
268 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
269 /** @} */
270
271 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
272 * @{ */
273 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
274 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
275 /** @} */
276
277 /** @name MMIO: PPR Log B Head and Tail pointer registers.
278 * @{ */
279 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
280 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
281 /** @} */
282
283 /** @name MMIO: Event Log B Head and Tail pointer registers.
284 * @{ */
285 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
286 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
287 /** @} */
288
289 /** @name MMIO: PPR Log Overflow protection registers.
290 * @{ */
291 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
292 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
293 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
294 /** @} */
295
296 /** @todo IOMMU: IOMMU Event counter registers. */
297
298#ifdef VBOX_WITH_STATISTICS
299 /** @name IOMMU: Stat counters.
300 * @{ */
301 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
302 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
303
304 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
305 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
306
307 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
308 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
309
310 STAMCOUNTER StatCmd; /**< Number of commands processed. */
311 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
312 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
313 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
314 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
315 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
316 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
317 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
318 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
319 /** @} */
320#endif
321} IOMMU;
322/** Pointer to the IOMMU device state. */
323typedef struct IOMMU *PIOMMU;
324/** Pointer to the const IOMMU device state. */
325typedef const struct IOMMU *PCIOMMU;
326AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
327AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
328AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
329AssertCompileMemberAlignment(IOMMU, hMmio, 8);
330AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
331
332/**
333 * The ring-3 IOMMU device state.
334 */
335typedef struct IOMMUR3
336{
337 /** Device instance. */
338 PPDMDEVINSR3 pDevInsR3;
339 /** The IOMMU helpers. */
340 PCPDMIOMMUHLPR3 pIommuHlpR3;
341 /** The command thread handle. */
342 R3PTRTYPE(PPDMTHREAD) pCmdThread;
343} IOMMUR3;
344/** Pointer to the ring-3 IOMMU device state. */
345typedef IOMMUR3 *PIOMMUR3;
346
347/**
348 * The ring-0 IOMMU device state.
349 */
350typedef struct IOMMUR0
351{
352 /** Device instance. */
353 PPDMDEVINSR0 pDevInsR0;
354 /** The IOMMU helpers. */
355 PCPDMIOMMUHLPR0 pIommuHlpR0;
356} IOMMUR0;
357/** Pointer to the ring-0 IOMMU device state. */
358typedef IOMMUR0 *PIOMMUR0;
359
360/**
361 * The raw-mode IOMMU device state.
362 */
363typedef struct IOMMURC
364{
365 /** Device instance. */
366 PPDMDEVINSR0 pDevInsRC;
367 /** The IOMMU helpers. */
368 PCPDMIOMMUHLPRC pIommuHlpRC;
369} IOMMURC;
370/** Pointer to the raw-mode IOMMU device state. */
371typedef IOMMURC *PIOMMURC;
372
373/** The IOMMU device state for the current context. */
374typedef CTX_SUFF(IOMMU) IOMMUCC;
375/** Pointer to the IOMMU device state for the current context. */
376typedef CTX_SUFF(PIOMMU) PIOMMUCC;
377
378/**
379 * IOMMU register access routines.
380 */
381typedef struct
382{
383 const char *pszName;
384 VBOXSTRICTRC (*pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t *pu64Value);
385 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
386 bool f64BitReg;
387} IOMMUREGACC;
388
389
390/*********************************************************************************************************************************
391* Global Variables *
392*********************************************************************************************************************************/
393/**
394 * An array of the number of device table segments supported.
395 * Indexed by u2DevTabSegSup.
396 */
397static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
398
399/**
400 * An array of the masks to select the device table segment index from a device ID.
401 */
402static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
403
404/**
405 * The maximum size (inclusive) of each device table segment (0 to 7).
406 * Indexed by the device table segment index.
407 */
408static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
409
410
411#ifndef VBOX_DEVICE_STRUCT_TESTCASE
412/**
413 * Gets the maximum number of buffer entries for the given buffer length.
414 *
415 * @returns Number of buffer entries.
416 * @param uEncodedLen The length (power-of-2 encoded).
417 */
418DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
419{
420 Assert(uEncodedLen > 7);
421 return 2 << (uEncodedLen - 1);
422}
423
424
425/**
426 * Gets the total length of the buffer given a base register's encoded length.
427 *
428 * @returns The length of the buffer in bytes.
429 * @param uEncodedLen The length (power-of-2 encoded).
430 */
431DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
432{
433 Assert(uEncodedLen > 7);
434 return (2 << (uEncodedLen - 1)) << 4;
435}
436
437
438/**
439 * Gets the number of (unconsumed) entries in the event log.
440 *
441 * @returns The number of entries in the event log.
442 * @param pThis The IOMMU device state.
443 */
444static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
445{
446 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
447 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
448 if (idxTail >= idxHead)
449 return idxTail - idxHead;
450
451 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
452 return cMaxEvts - idxHead + idxTail;
453}
454
455
456/**
457 * Gets the number of (unconsumed) commands in the command buffer.
458 *
459 * @returns The number of commands in the command buffer.
460 * @param pThis The IOMMU device state.
461 */
462static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
463{
464 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
465 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
466 if (idxTail >= idxHead)
467 return idxTail - idxHead;
468
469 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
470 return cMaxCmds - idxHead + idxTail;
471}
472
473
474DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
475{
476 IOMMU_STATUS_T Status;
477 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
478 return Status;
479}
480
481
482DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
483{
484 IOMMU_CTRL_T Ctrl;
485 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
486 return Ctrl;
487}
488
489
490/**
491 * Returns whether MSI is enabled for the IOMMU.
492 *
493 * @returns Whether MSI is enabled.
494 * @param pDevIns The IOMMU device instance.
495 *
496 * @note There should be a PCIDevXxx function for this.
497 */
498static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
499{
500 MSI_CAP_HDR_T MsiCapHdr;
501 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
502 return MsiCapHdr.n.u1MsiEnable;
503}
504
505
506/**
507 * Signals a PCI target abort.
508 *
509 * @param pDevIns The IOMMU device instance.
510 */
511static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
512{
513 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
514 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
515 PDMPciDevSetStatus(pPciDev, u16Status);
516}
517
518
519/**
520 * Wakes up the command thread if there are commands to be processed or if
521 * processing is requested to be stopped by software.
522 *
523 * @param pDevIns The IOMMU device instance.
524 */
525static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
526{
527 IOMMU_ASSERT_LOCKED(pDevIns);
528 Log5Func(("\n"));
529
530 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
531 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
532 if (Status.n.u1CmdBufRunning)
533 {
534 Log5Func(("Signaling command thread\n"));
535 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
536 }
537}
538
539
540/**
541 * Writes to a read-only register.
542 */
543static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
544{
545 RT_NOREF(pDevIns, pThis, iReg, u64Value);
546 LogFunc(("Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
547 return VINF_SUCCESS;
548}
549
550
551/**
552 * Writes the Device Table Base Address Register.
553 */
554static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
555{
556 RT_NOREF(pDevIns, iReg);
557
558 /* Mask out all unrecognized bits. */
559 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
560
561 /* Update the register. */
562 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
563 return VINF_SUCCESS;
564}
565
566
567/**
568 * Writes the Command Buffer Base Address Register.
569 */
570static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
571{
572 RT_NOREF(pDevIns, iReg);
573
574 /*
575 * While this is not explicitly specified like the event log base address register,
576 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
577 * Inconsistent specs :/
578 */
579 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
580 if (Status.n.u1CmdBufRunning)
581 {
582 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
583 return VINF_SUCCESS;
584 }
585
586 /* Mask out all unrecognized bits. */
587 CMD_BUF_BAR_T CmdBufBaseAddr;
588 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
589
590 /* Validate the length. */
591 if (CmdBufBaseAddr.n.u4Len >= 8)
592 {
593 /* Update the register. */
594 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
595
596 /*
597 * Writing the command buffer base address, clears the command buffer head and tail pointers.
598 * See AMD spec. 2.4 "Commands".
599 */
600 pThis->CmdBufHeadPtr.u64 = 0;
601 pThis->CmdBufTailPtr.u64 = 0;
602 }
603 else
604 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
605
606 return VINF_SUCCESS;
607}
608
609
610/**
611 * Writes the Event Log Base Address Register.
612 */
613static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
614{
615 RT_NOREF(pDevIns, iReg);
616
617 /*
618 * IOMMU behavior is undefined when software writes this register when event logging is running.
619 * In our emulation, we ignore the write entirely.
620 * See AMD IOMMU spec. "Event Log Base Address Register".
621 */
622 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
623 if (Status.n.u1EvtLogRunning)
624 {
625 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
626 return VINF_SUCCESS;
627 }
628
629 /* Mask out all unrecognized bits. */
630 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
631 EVT_LOG_BAR_T EvtLogBaseAddr;
632 EvtLogBaseAddr.u64 = u64Value;
633
634 /* Validate the length. */
635 if (EvtLogBaseAddr.n.u4Len >= 8)
636 {
637 /* Update the register. */
638 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
639
640 /*
641 * Writing the event log base address, clears the event log head and tail pointers.
642 * See AMD spec. 2.5 "Event Logging".
643 */
644 pThis->EvtLogHeadPtr.u64 = 0;
645 pThis->EvtLogTailPtr.u64 = 0;
646 }
647 else
648 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
649
650 return VINF_SUCCESS;
651}
652
653
654/**
655 * Writes the Control Register.
656 */
657static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
658{
659 RT_NOREF(pDevIns, iReg);
660
661 /* Mask out all unrecognized bits. */
662 u64Value &= IOMMU_CTRL_VALID_MASK;
663
664 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
665 IOMMU_CTRL_T NewCtrl;
666 NewCtrl.u64 = u64Value;
667
668 /* Update the register. */
669 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
670
671 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
672 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
673
674 /* Enable or disable event logging when the bit transitions. */
675 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
676 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
677 if ( fOldEvtLogEn != fNewEvtLogEn
678 || fOldIommuEn != fNewIommuEn)
679 {
680 if ( fNewIommuEn
681 && fNewEvtLogEn)
682 {
683 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
684 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
685 }
686 else
687 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
688 }
689
690 /* Enable or disable command buffer processing when the bit transitions. */
691 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
692 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
693 if ( fOldCmdBufEn != fNewCmdBufEn
694 || fOldIommuEn != fNewIommuEn)
695 {
696 if ( fNewCmdBufEn
697 && fNewIommuEn)
698 {
699 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
700 LogFunc(("Command buffer enabled\n"));
701
702 /* Wake up the command thread to start processing commands. */
703 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
704 }
705 else
706 {
707 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
708 LogFunc(("Command buffer disabled\n"));
709 }
710 }
711
712 return VINF_SUCCESS;
713}
714
715
716/**
717 * Writes to the Excluse Range Base Address Register.
718 */
719static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
720{
721 RT_NOREF(pDevIns, iReg);
722 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
723 return VINF_SUCCESS;
724}
725
726
727/**
728 * Writes to the Excluse Range Limit Register.
729 */
730static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
731{
732 RT_NOREF(pDevIns, iReg);
733 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
734 u64Value |= UINT64_C(0xfff);
735 pThis->ExclRangeLimit.u64 = u64Value;
736 return VINF_SUCCESS;
737}
738
739
740/**
741 * Writes the Hardware Event Register (Hi).
742 */
743static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
744{
745 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
746 RT_NOREF(pDevIns, iReg);
747 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
748 pThis->HwEvtHi.u64 = u64Value;
749 return VINF_SUCCESS;
750}
751
752
753/**
754 * Writes the Hardware Event Register (Lo).
755 */
756static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
757{
758 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
759 RT_NOREF(pDevIns, iReg);
760 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
761 pThis->HwEvtLo = u64Value;
762 return VINF_SUCCESS;
763}
764
765
766/**
767 * Writes the Hardware Event Status Register.
768 */
769static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
770{
771 RT_NOREF(pDevIns, iReg);
772
773 /* Mask out all unrecognized bits. */
774 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
775
776 /*
777 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
778 * If the current status bits or the bits being written are both 0, we've nothing to do.
779 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
780 */
781 uint64_t HwStatus = pThis->HwEvtStatus.u64;
782 if (!(HwStatus & RT_BIT(0)))
783 return VINF_SUCCESS;
784 if (u64Value & HwStatus & RT_BIT_64(0))
785 HwStatus &= ~RT_BIT_64(0);
786 if (u64Value & HwStatus & RT_BIT_64(1))
787 HwStatus &= ~RT_BIT_64(1);
788
789 /* Update the register. */
790 pThis->HwEvtStatus.u64 = HwStatus;
791 return VINF_SUCCESS;
792}
793
794
795/**
796 * Writes the Device Table Segment Base Address Register.
797 */
798static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
799{
800 RT_NOREF(pDevIns);
801
802 /* Figure out which segment is being written. */
803 uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
804 uint8_t const idxSegment = offSegment + 1;
805 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
806
807 /* Mask out all unrecognized bits. */
808 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
809 DEV_TAB_BAR_T DevTabSegBar;
810 DevTabSegBar.u64 = u64Value;
811
812 /* Validate the size. */
813 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
814 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
815 if (uSegSize <= uMaxSegSize)
816 {
817 /* Update the register. */
818 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
819 }
820 else
821 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
822
823 return VINF_SUCCESS;
824}
825
826
827/**
828 * Writes the MSI Capability Header Register.
829 */
830static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
831{
832 RT_NOREF(pThis, iReg);
833 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
834 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
835 MSI_CAP_HDR_T MsiCapHdr;
836 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
837 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
838 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
839 return VINF_SUCCESS;
840}
841
842
843/**
844 * Writes the MSI Address (Lo) Register (32-bit).
845 */
846static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
847{
848 RT_NOREF(pThis, iReg);
849 Assert(!RT_HI_U32(u64Value));
850 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
851 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
852 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
853 return VINF_SUCCESS;
854}
855
856
857/**
858 * Writes the MSI Address (Hi) Register (32-bit).
859 */
860static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
861{
862 RT_NOREF(pThis, iReg);
863 Assert(!RT_HI_U32(u64Value));
864 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
865 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
866 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
867 return VINF_SUCCESS;
868}
869
870
871/**
872 * Writes the MSI Data Register (32-bit).
873 */
874static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
875{
876 RT_NOREF(pThis, iReg);
877 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
878 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
879 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
880 return VINF_SUCCESS;
881}
882
883
884/**
885 * Writes the Command Buffer Head Pointer Register (32-bit).
886 */
887static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
888{
889 RT_NOREF(pDevIns, iReg);
890
891 /*
892 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
893 * In our emulation, we ignore the write entirely.
894 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
895 */
896 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
897 if (Status.n.u1CmdBufRunning)
898 {
899 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
900 return VINF_SUCCESS;
901 }
902
903 /*
904 * IOMMU behavior is undefined when software writes a value outside the buffer length.
905 * In our emulation, we ignore the write entirely.
906 */
907 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
908 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
909 Assert(cbBuf <= _512K);
910 if (offBuf >= cbBuf)
911 {
912 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
913 return VINF_SUCCESS;
914 }
915
916 /* Update the register. */
917 pThis->CmdBufHeadPtr.au32[0] = offBuf;
918
919 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
920
921 LogFlowFunc(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
922 return VINF_SUCCESS;
923}
924
925
926/**
927 * Writes the Command Buffer Tail Pointer Register (32-bit).
928 */
929static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
930{
931 RT_NOREF(pDevIns, iReg);
932
933 /*
934 * IOMMU behavior is undefined when software writes a value outside the buffer length.
935 * In our emulation, we ignore the write entirely.
936 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
937 */
938 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
939 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
940 Assert(cbBuf <= _512K);
941 if (offBuf >= cbBuf)
942 {
943 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
944 return VINF_SUCCESS;
945 }
946
947 /*
948 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
949 * head pointer after adding one or more commands to the buffer.
950 *
951 * However, we cannot enforce this strictly because it's legal for software to shrink the
952 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
953 * at 0). Software might even make the queue empty by making head and tail equal which is
954 * allowed. I don't think we can or should try too hard to prevent software shooting itself
955 * in the foot here. As long as we make sure the offset value is within the circular buffer
956 * bounds (which we do by masking bits above) it should be sufficient.
957 */
958 pThis->CmdBufTailPtr.au32[0] = offBuf;
959
960 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
961
962 LogFlowFunc(("Set CmdBufTailPtr to %#RX32\n", offBuf));
963 return VINF_SUCCESS;
964}
965
966
967/**
968 * Writes the Event Log Head Pointer Register (32-bit).
969 */
970static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
971{
972 RT_NOREF(pDevIns, iReg);
973
974 /*
975 * IOMMU behavior is undefined when software writes a value outside the buffer length.
976 * In our emulation, we ignore the write entirely.
977 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
978 */
979 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
980 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
981 Assert(cbBuf <= _512K);
982 if (offBuf >= cbBuf)
983 {
984 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
985 return VINF_SUCCESS;
986 }
987
988 /* Update the register. */
989 pThis->EvtLogHeadPtr.au32[0] = offBuf;
990
991 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
992 return VINF_SUCCESS;
993}
994
995
996/**
997 * Writes the Event Log Tail Pointer Register (32-bit).
998 */
999static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
1000{
1001 RT_NOREF(pDevIns, iReg);
1002 NOREF(pThis);
1003
1004 /*
1005 * IOMMU behavior is undefined when software writes this register when the event log is running.
1006 * In our emulation, we ignore the write entirely.
1007 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1008 */
1009 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1010 if (Status.n.u1EvtLogRunning)
1011 {
1012 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1013 return VINF_SUCCESS;
1014 }
1015
1016 /*
1017 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1018 * In our emulation, we ignore the write entirely.
1019 */
1020 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1021 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1022 Assert(cbBuf <= _512K);
1023 if (offBuf >= cbBuf)
1024 {
1025 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1026 return VINF_SUCCESS;
1027 }
1028
1029 /* Update the register. */
1030 pThis->EvtLogTailPtr.au32[0] = offBuf;
1031
1032 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1033 return VINF_SUCCESS;
1034}
1035
1036
1037/**
1038 * Writes the Status Register (64-bit).
1039 */
1040static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
1041{
1042 RT_NOREF(pDevIns, iReg);
1043
1044 /* Mask out all unrecognized bits. */
1045 u64Value &= IOMMU_STATUS_VALID_MASK;
1046
1047 /*
1048 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1049 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1050 */
1051 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1052 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1053 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1054 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1055
1056 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1057
1058 /* Update the register. */
1059 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1060 return VINF_SUCCESS;
1061}
1062
1063
1064#if 0
1065/**
1066 * Table 0: Registers-access table.
1067 */
1068static const IOMMUREGACC g_aTable0Regs[] =
1069{
1070
1071};
1072
1073/**
1074 * Table 1: Registers-access table.
1075 */
1076static const IOMMUREGACC g_aTable1Regs[] =
1077{
1078};
1079#endif
1080
1081
1082/**
1083 * Writes an IOMMU register (32-bit and 64-bit).
1084 *
1085 * @returns Strict VBox status code.
1086 * @param pDevIns The IOMMU device instance.
1087 * @param off MMIO byte offset to the register.
1088 * @param cb The size of the write access.
1089 * @param uValue The value being written.
1090 *
1091 * @thread EMT.
1092 */
1093static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1094{
1095 Assert(off < IOMMU_MMIO_REGION_SIZE);
1096 Assert(cb == 4 || cb == 8);
1097 Assert(!(off & (cb - 1)));
1098
1099 LogFlowFunc(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1100
1101 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1102 switch (off)
1103 {
1104 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1105 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1106 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1107 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1108 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1109 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1110 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1111
1112 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1113 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1114 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1115 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1116
1117 case IOMMU_MMIO_OFF_GALOG_BAR:
1118 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1119
1120 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1121 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1122
1123 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1124 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1125 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1126 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1127 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1128 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1129 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1130
1131 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1132 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1133 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1134
1135 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1136 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1137 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1138 {
1139 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1140 if (cb == 4 || RT_FAILURE(rcStrict))
1141 return rcStrict;
1142 uValue >>= 32;
1143 RT_FALL_THRU();
1144 }
1145 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1146 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1147 {
1148 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1149 if (cb == 4 || RT_FAILURE(rcStrict))
1150 return rcStrict;
1151 uValue >>= 32;
1152 RT_FALL_THRU();
1153 }
1154 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1155 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1156
1157 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1158
1159 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1160 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1161 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1162
1163 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1164 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1165 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1166 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1167 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1168 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1169 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1170 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1171 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1172 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1173 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1174 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1175
1176 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1177
1178 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1179 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1180 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1181 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1182
1183 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1184
1185 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1186 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1187
1188 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1189 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1190
1191 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1192 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1193
1194 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1195 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1196
1197 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1198 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1199 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1200
1201 /* Not implemented. */
1202 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1203 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1204 {
1205 LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1206 return VINF_SUCCESS;
1207 }
1208
1209 /* Unknown. */
1210 default:
1211 {
1212 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1213 return VINF_SUCCESS;
1214 }
1215 }
1216}
1217
1218
1219/**
1220 * Reads an IOMMU register (64-bit) given its MMIO offset.
1221 *
1222 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1223 * boundary include the lower half of the subsequent register.
1224 *
1225 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1226 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1227 * software will only perform 32-bit reads on those 32-bit registers that are
1228 * aligned on 8-byte boundaries.
1229 *
1230 * @returns Strict VBox status code.
1231 * @param pDevIns The IOMMU device instance.
1232 * @param off The MMIO offset of the register in bytes.
1233 * @param puResult Where to store the value being read.
1234 *
1235 * @thread EMT.
1236 */
1237static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1238{
1239 Assert(off < IOMMU_MMIO_REGION_SIZE);
1240 Assert(!(off & 7) || !(off & 3));
1241
1242 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1243 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1244 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1245
1246 LogFlowFunc(("off=%#x\n", off));
1247
1248 /** @todo IOMMU: fine-grained locking? */
1249 uint64_t uReg;
1250 switch (off)
1251 {
1252 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1253 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1254 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1255 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1256 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1257 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1258 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1259
1260 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1261 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1262 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1263 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1264
1265 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1266 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1267
1268 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1269 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1270
1271 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1272 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1273 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1274 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1275 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1276 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1277 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1278 {
1279 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1280 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1281 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1282 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1283 break;
1284 }
1285
1286 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1287 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1288 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1289
1290 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1291 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1292 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1293 {
1294 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1295 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1296 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1297 break;
1298 }
1299 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1300 {
1301 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1302 break;
1303 }
1304 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1305 {
1306 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1307 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1308 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1309 break;
1310 }
1311 case IOMMU_MMIO_OFF_MSI_DATA:
1312 {
1313 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1314 break;
1315 }
1316 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1317 {
1318 /*
1319 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1320 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1321 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1322 * 0 for this register.
1323 */
1324 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1325 break;
1326 }
1327
1328 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1329
1330 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1331 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1332 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1333
1334 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1335 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1336 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1337 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1338 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1339 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1340 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1341 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1342 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1343 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1344 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1345 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1346
1347 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1348
1349 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1350 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1351 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1352 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1353
1354 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
1355
1356 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
1357 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
1358
1359 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
1360 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
1361
1362 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
1363 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
1364
1365 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
1366 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
1367
1368 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
1369 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
1370 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
1371
1372 /* Not implemented. */
1373 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1374 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1375 {
1376 LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1377 uReg = 0;
1378 break;
1379 }
1380
1381 /* Unknown. */
1382 default:
1383 {
1384 LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
1385 uReg = 0;
1386 return VINF_IOM_MMIO_UNUSED_00;
1387 }
1388 }
1389
1390 *puResult = uReg;
1391 return VINF_SUCCESS;
1392}
1393
1394
1395/**
1396 * Raises the MSI interrupt for the IOMMU device.
1397 *
1398 * @param pDevIns The IOMMU device instance.
1399 *
1400 * @thread Any.
1401 */
1402static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
1403{
1404 if (iommuAmdIsMsiEnabled(pDevIns))
1405 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
1406}
1407
1408
1409/**
1410 * Clears the MSI interrupt for the IOMMU device.
1411 *
1412 * @param pDevIns The IOMMU device instance.
1413 *
1414 * @thread Any.
1415 */
1416static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
1417{
1418 if (iommuAmdIsMsiEnabled(pDevIns))
1419 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
1420}
1421
1422
1423/**
1424 * Writes an entry to the event log in memory.
1425 *
1426 * @returns VBox status code.
1427 * @param pDevIns The IOMMU device instance.
1428 * @param pEvent The event to log.
1429 *
1430 * @thread Any.
1431 */
1432static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1433{
1434 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1435
1436 IOMMU_ASSERT_LOCKED(pDevIns);
1437
1438 /* Check if event logging is active and the log has not overflowed. */
1439 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1440 if ( Status.n.u1EvtLogRunning
1441 && !Status.n.u1EvtOverflow)
1442 {
1443 uint32_t const cbEvt = sizeof(*pEvent);
1444
1445 /* Get the offset we need to write the event to in memory (circular buffer offset). */
1446 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
1447 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
1448
1449 /* Ensure we have space in the event log. */
1450 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
1451 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
1452 if (cEvts + 1 < cMaxEvts)
1453 {
1454 /* Write the event log entry to memory. */
1455 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
1456 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
1457 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
1458 if (RT_FAILURE(rc))
1459 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
1460
1461 /* Increment the event log tail pointer. */
1462 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1463 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
1464
1465 /* Indicate that an event log entry was written. */
1466 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
1467
1468 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
1469 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1470 if (Ctrl.n.u1EvtIntrEn)
1471 iommuAmdRaiseMsiInterrupt(pDevIns);
1472 }
1473 else
1474 {
1475 /* Indicate that the event log has overflowed. */
1476 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
1477
1478 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
1479 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1480 if (Ctrl.n.u1EvtIntrEn)
1481 iommuAmdRaiseMsiInterrupt(pDevIns);
1482 }
1483 }
1484
1485 return VINF_SUCCESS;
1486}
1487
1488
1489/**
1490 * Sets an event in the hardware error registers.
1491 *
1492 * @param pDevIns The IOMMU device instance.
1493 * @param pEvent The event.
1494 *
1495 * @thread Any.
1496 */
1497static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1498{
1499 IOMMU_ASSERT_LOCKED(pDevIns);
1500
1501 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1502 if (pThis->ExtFeat.n.u1HwErrorSup)
1503 {
1504 if (pThis->HwEvtStatus.n.u1Valid)
1505 pThis->HwEvtStatus.n.u1Overflow = 1;
1506 pThis->HwEvtStatus.n.u1Valid = 1;
1507 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
1508 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
1509 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
1510 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
1511 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
1512 }
1513}
1514
1515
1516/**
1517 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
1518 *
1519 * @param uDevId The device ID.
1520 * @param uDomainId The domain ID.
1521 * @param GCPhysPtEntity The system physical address of the page table
1522 * entity.
1523 * @param enmOp The IOMMU operation being performed.
1524 * @param pEvtPageTabHwErr Where to store the initialized event.
1525 */
1526static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
1527 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1528{
1529 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
1530 pEvtPageTabHwErr->n.u16DevId = uDevId;
1531 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
1532 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
1533 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1534 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1535 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1536 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1537 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
1538 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
1539}
1540
1541
1542/**
1543 * Raises a PAGE_TAB_HARDWARE_ERROR event.
1544 *
1545 * @param pDevIns The IOMMU device instance.
1546 * @param enmOp The IOMMU operation being performed.
1547 * @param pEvtPageTabHwErr The page table hardware error event.
1548 *
1549 * @thread Any.
1550 */
1551static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1552{
1553 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
1554 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
1555
1556 IOMMU_LOCK_NORET(pDevIns);
1557
1558 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1559 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1560 if (enmOp != IOMMUOP_CMD)
1561 iommuAmdSetPciTargetAbort(pDevIns);
1562
1563 IOMMU_UNLOCK(pDevIns);
1564
1565 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
1566 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
1567 pEvtPageTabHwErr->n.u2Type));
1568}
1569
1570
1571/**
1572 * Initializes a COMMAND_HARDWARE_ERROR event.
1573 *
1574 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
1575 * @param pEvtCmdHwErr Where to store the initialized event.
1576 */
1577static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1578{
1579 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
1580 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
1581 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
1582 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
1583}
1584
1585
1586/**
1587 * Raises a COMMAND_HARDWARE_ERROR event.
1588 *
1589 * @param pDevIns The IOMMU device instance.
1590 * @param pEvtCmdHwErr The command hardware error event.
1591 *
1592 * @thread Any.
1593 */
1594static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1595{
1596 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
1597 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
1598 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1599
1600 IOMMU_LOCK_NORET(pDevIns);
1601
1602 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1603 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1604 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1605
1606 IOMMU_UNLOCK(pDevIns);
1607
1608 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
1609}
1610
1611
1612/**
1613 * Initializes a DEV_TAB_HARDWARE_ERROR event.
1614 *
1615 * @param uDevId The device ID.
1616 * @param GCPhysDte The system physical address of the failed device table
1617 * access.
1618 * @param enmOp The IOMMU operation being performed.
1619 * @param pEvtDevTabHwErr Where to store the initialized event.
1620 */
1621static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
1622 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1623{
1624 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
1625 pEvtDevTabHwErr->n.u16DevId = uDevId;
1626 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1627 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
1628 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1629 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1630 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1631 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
1632 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
1633}
1634
1635
1636/**
1637 * Raises a DEV_TAB_HARDWARE_ERROR event.
1638 *
1639 * @param pDevIns The IOMMU device instance.
1640 * @param enmOp The IOMMU operation being performed.
1641 * @param pEvtDevTabHwErr The device table hardware error event.
1642 *
1643 * @thread Any.
1644 */
1645static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1646{
1647 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
1648 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
1649
1650 IOMMU_LOCK_NORET(pDevIns);
1651
1652 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1653 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1654 if (enmOp != IOMMUOP_CMD)
1655 iommuAmdSetPciTargetAbort(pDevIns);
1656
1657 IOMMU_UNLOCK(pDevIns);
1658
1659 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
1660 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
1661}
1662
1663
1664/**
1665 * Initializes an ILLEGAL_COMMAND_ERROR event.
1666 *
1667 * @param GCPhysCmd The system physical address of the failed command
1668 * access.
1669 * @param pEvtIllegalCmd Where to store the initialized event.
1670 */
1671static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
1672{
1673 Assert(!(GCPhysCmd & UINT64_C(0xf)));
1674 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
1675 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
1676 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
1677}
1678
1679
1680/**
1681 * Raises an ILLEGAL_COMMAND_ERROR event.
1682 *
1683 * @param pDevIns The IOMMU device instance.
1684 * @param pEvtIllegalCmd The illegal command error event.
1685 */
1686static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
1687{
1688 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
1689 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
1690 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1691
1692 IOMMU_LOCK_NORET(pDevIns);
1693
1694 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1695 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1696
1697 IOMMU_UNLOCK(pDevIns);
1698
1699 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
1700}
1701
1702
1703/**
1704 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
1705 *
1706 * @param uDevId The device ID.
1707 * @param uIova The I/O virtual address.
1708 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
1709 * event was caused by an invalid level encoding in the
1710 * DTE.
1711 * @param enmOp The IOMMU operation being performed.
1712 * @param pEvtIllegalDte Where to store the initialized event.
1713 */
1714static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
1715 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
1716{
1717 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
1718 pEvtIllegalDte->n.u16DevId = uDevId;
1719 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1720 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1721 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
1722 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1723 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
1724 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
1725 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
1726 * IOMMU spec here but not for this field for I/O page fault event. */
1727 Assert(!(uIova & UINT64_C(0x3)));
1728}
1729
1730
1731/**
1732 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
1733 *
1734 * @param pDevIns The IOMMU instance data.
1735 * @param enmOp The IOMMU operation being performed.
1736 * @param pEvtIllegalDte The illegal device table entry event.
1737 * @param enmEvtType The illegal device table entry event type.
1738 *
1739 * @thread Any.
1740 */
1741static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
1742 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
1743{
1744 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
1745 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
1746
1747 IOMMU_LOCK_NORET(pDevIns);
1748
1749 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1750 if (enmOp != IOMMUOP_CMD)
1751 iommuAmdSetPciTargetAbort(pDevIns);
1752
1753 IOMMU_UNLOCK(pDevIns);
1754
1755 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
1756 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
1757 NOREF(enmEvtType);
1758}
1759
1760
1761/**
1762 * Initializes an IO_PAGE_FAULT event.
1763 *
1764 * @param uDevId The device ID.
1765 * @param uDomainId The domain ID.
1766 * @param uIova The I/O virtual address being accessed.
1767 * @param fPresent Transaction to a page marked as present (including
1768 * DTE.V=1) or interrupt marked as remapped
1769 * (IRTE.RemapEn=1).
1770 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
1771 * the I/O page fault was caused by invalid level
1772 * encoding.
1773 * @param fPermDenied Permission denied for the address being accessed.
1774 * @param enmOp The IOMMU operation being performed.
1775 * @param pEvtIoPageFault Where to store the initialized event.
1776 */
1777static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
1778 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
1779{
1780 Assert(!fPermDenied || fPresent);
1781 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
1782 pEvtIoPageFault->n.u16DevId = uDevId;
1783 //pEvtIoPageFault->n.u4PasidHi = 0;
1784 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
1785 //pEvtIoPageFault->n.u1GuestOrNested = 0;
1786 //pEvtIoPageFault->n.u1NoExecute = 0;
1787 //pEvtIoPageFault->n.u1User = 0;
1788 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1789 pEvtIoPageFault->n.u1Present = fPresent;
1790 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1791 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
1792 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
1793 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1794 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
1795 pEvtIoPageFault->n.u64Addr = uIova;
1796}
1797
1798
1799/**
1800 * Raises an IO_PAGE_FAULT event.
1801 *
1802 * @param pDevIns The IOMMU instance data.
1803 * @param pDte The device table entry. Optional, can be NULL
1804 * depending on @a enmOp.
1805 * @param pIrte The interrupt remapping table entry. Optional, can
1806 * be NULL depending on @a enmOp.
1807 * @param enmOp The IOMMU operation being performed.
1808 * @param pEvtIoPageFault The I/O page fault event.
1809 * @param enmEvtType The I/O page fault event type.
1810 *
1811 * @thread Any.
1812 */
1813static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
1814 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
1815{
1816 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
1817 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
1818
1819 IOMMU_LOCK_NORET(pDevIns);
1820
1821 bool fSuppressEvtLogging = false;
1822 if ( enmOp == IOMMUOP_MEM_READ
1823 || enmOp == IOMMUOP_MEM_WRITE)
1824 {
1825 if ( pDte
1826 && pDte->n.u1Valid)
1827 {
1828 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
1829 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
1830 * suppression. Perhaps will be possible when we complete IOTLB/cache
1831 * handling. */
1832 }
1833 }
1834 else if (enmOp == IOMMUOP_INTR_REQ)
1835 {
1836 if ( pDte
1837 && pDte->n.u1IntrMapValid)
1838 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
1839
1840 if ( !fSuppressEvtLogging
1841 && pIrte)
1842 fSuppressEvtLogging = pIrte->n.u1SuppressPf;
1843 }
1844 /* else: Events are never suppressed for commands. */
1845
1846 switch (enmEvtType)
1847 {
1848 case kIoPageFaultType_PermDenied:
1849 {
1850 /* Cannot be triggered by a command. */
1851 Assert(enmOp != IOMMUOP_CMD);
1852 RT_FALL_THRU();
1853 }
1854 case kIoPageFaultType_DteRsvdPagingMode:
1855 case kIoPageFaultType_PteInvalidPageSize:
1856 case kIoPageFaultType_PteInvalidLvlEncoding:
1857 case kIoPageFaultType_SkippedLevelIovaNotZero:
1858 case kIoPageFaultType_PteRsvdNotZero:
1859 case kIoPageFaultType_PteValidNotSet:
1860 case kIoPageFaultType_DteTranslationDisabled:
1861 case kIoPageFaultType_PasidInvalidRange:
1862 {
1863 /*
1864 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
1865 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
1866 */
1867 if (enmOp != IOMMUOP_TRANSLATE_REQ)
1868 {
1869 if (!fSuppressEvtLogging)
1870 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1871 if (enmOp != IOMMUOP_CMD)
1872 iommuAmdSetPciTargetAbort(pDevIns);
1873 }
1874 break;
1875 }
1876
1877 case kIoPageFaultType_UserSupervisor:
1878 {
1879 /* Access is blocked and only creates an event log entry. */
1880 if (!fSuppressEvtLogging)
1881 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1882 break;
1883 }
1884
1885 case kIoPageFaultType_IrteAddrInvalid:
1886 case kIoPageFaultType_IrteRsvdNotZero:
1887 case kIoPageFaultType_IrteRemapEn:
1888 case kIoPageFaultType_IrteRsvdIntType:
1889 case kIoPageFaultType_IntrReqAborted:
1890 case kIoPageFaultType_IntrWithPasid:
1891 {
1892 /* Only trigerred by interrupt requests. */
1893 Assert(enmOp == IOMMUOP_INTR_REQ);
1894 if (!fSuppressEvtLogging)
1895 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1896 iommuAmdSetPciTargetAbort(pDevIns);
1897 break;
1898 }
1899
1900 case kIoPageFaultType_SmiFilterMismatch:
1901 {
1902 /* Not supported and probably will never be, assert. */
1903 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
1904 break;
1905 }
1906
1907 case kIoPageFaultType_DevId_Invalid:
1908 {
1909 /* Cannot be triggered by a command. */
1910 Assert(enmOp != IOMMUOP_CMD);
1911 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
1912 if (!fSuppressEvtLogging)
1913 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1914 if ( enmOp == IOMMUOP_MEM_READ
1915 || enmOp == IOMMUOP_MEM_WRITE)
1916 iommuAmdSetPciTargetAbort(pDevIns);
1917 break;
1918 }
1919 }
1920
1921 IOMMU_UNLOCK(pDevIns);
1922}
1923
1924
1925/**
1926 * Returns whether the I/O virtual address is to be excluded from translation and
1927 * permission checks.
1928 *
1929 * @returns @c true if the DVA is excluded, @c false otherwise.
1930 * @param pThis The IOMMU device state.
1931 * @param pDte The device table entry.
1932 * @param uIova The I/O virtual address.
1933 *
1934 * @remarks Ensure the exclusion range is enabled prior to calling this function.
1935 *
1936 * @thread Any.
1937 */
1938static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
1939{
1940 /* Ensure the exclusion range is enabled. */
1941 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
1942
1943 /* Check if the IOVA falls within the exclusion range. */
1944 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
1945 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
1946 if (uIovaExclLast - uIova >= uIovaExclFirst)
1947 {
1948 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
1949 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
1950 || pDte->n.u1AllowExclusion)
1951 return true;
1952 }
1953 return false;
1954}
1955
1956
1957/**
1958 * Reads a device table entry from guest memory given the device ID.
1959 *
1960 * @returns VBox status code.
1961 * @param pDevIns The IOMMU device instance.
1962 * @param uDevId The device ID.
1963 * @param enmOp The IOMMU operation being performed.
1964 * @param pDte Where to store the device table entry.
1965 *
1966 * @thread Any.
1967 */
1968static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
1969{
1970 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1971 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1972
1973 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
1974 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
1975
1976 uint8_t const idxSeg = uDevId & g_auDevTabSegMasks[idxSegsEn] >> 13;
1977 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1978
1979 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
1980 uint16_t const offDte = uDevId & ~g_auDevTabSegMasks[idxSegsEn];
1981 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
1982
1983 LogFlowFunc(("idxSegsEn=%#x GCPhysDevTab=%#RGp offDte=%#x GCPhysDte=%#RGp\n", idxSegsEn, GCPhysDevTab, offDte, GCPhysDte));
1984
1985 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
1986 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
1987 if (RT_FAILURE(rc))
1988 {
1989 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
1990
1991 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
1992 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
1993 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
1994 return VERR_IOMMU_IPE_1;
1995 }
1996
1997
1998 return rc;
1999}
2000
2001
2002/**
2003 * Walks the I/O page table to translate the I/O virtual address to a system
2004 * physical address.
2005 *
2006 * @returns VBox status code.
2007 * @param pDevIns The IOMMU device instance.
2008 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2009 * @param uDevId The device ID.
2010 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2011 * permissions for the access being made.
2012 * @param pDte The device table entry.
2013 * @param enmOp The IOMMU operation being performed.
2014 * @param pWalkResult Where to store the results of the I/O page walk. This is
2015 * only updated when VINF_SUCCESS is returned.
2016 *
2017 * @thread Any.
2018 */
2019static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2020 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2021{
2022 Assert(pDte->n.u1Valid);
2023 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2024
2025 /* If the translation is not valid, raise an I/O page fault. */
2026 if (pDte->n.u1TranslationValid)
2027 { /* likely */ }
2028 else
2029 {
2030 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2031 * doesn't explicitly say whether an I/O page fault is raised. From other
2032 * places in the spec. it seems early page walk terminations (starting with
2033 * the DTE) return the state computed so far and raises an I/O page fault. So
2034 * returning an invalid translation rather than skipping translation. */
2035 LogFunc(("Translation valid bit not set -> IOPF"));
2036 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2037 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2038 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2039 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2040 kIoPageFaultType_DteTranslationDisabled);
2041 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2042 }
2043
2044 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2045 uint8_t const uMaxLevel = pDte->n.u3Mode;
2046 if (uMaxLevel != 0)
2047 { /* likely */ }
2048 else
2049 {
2050 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2051 if ((fAccess & fDtePerm) != fAccess)
2052 {
2053 LogFunc(("Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
2054 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2055 }
2056 pWalkResult->GCPhysSpa = uIova;
2057 pWalkResult->cShift = 0;
2058 pWalkResult->fIoPerm = fDtePerm;
2059 return VINF_SUCCESS;
2060 }
2061
2062 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2063 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2064 { /* likely */ }
2065 else
2066 {
2067 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2068 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2069 * I'm just going with I/O page fault. */
2070 LogFunc(("Invalid root page table level %#x -> IOPF\n", uMaxLevel));
2071 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2072 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2073 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2074 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2075 kIoPageFaultType_PteInvalidLvlEncoding);
2076 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2077 }
2078
2079 /* Check permissions bits of the root page table. */
2080 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2081 if ((fAccess & fRootPtePerm) == fAccess)
2082 { /* likely */ }
2083 else
2084 {
2085 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2086 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2087 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2088 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2089 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2090 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2091 }
2092
2093 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2094 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2095 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2096 * table entry every time. Not sure if it's worth optimizing that case now
2097 * or if at all. */
2098
2099 /* The virtual address bits indexing table. */
2100 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2101 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2102 UINT64_C(0x00000000001ff000),
2103 UINT64_C(0x000000003fe00000),
2104 UINT64_C(0x0000007fc0000000),
2105 UINT64_C(0x0000ff8000000000),
2106 UINT64_C(0x01ff000000000000),
2107 UINT64_C(0xfe00000000000000),
2108 UINT64_C(0x0000000000000000) };
2109 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2110 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2111
2112 /* Traverse the I/O page table starting with the page directory in the DTE. */
2113 IOPTENTITY_T PtEntity;
2114 PtEntity.u64 = pDte->au64[0];
2115 for (;;)
2116 {
2117 /* Figure out the system physical address of the page table at the current level. */
2118 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2119
2120 /* Read the page table entity at the current level. */
2121 {
2122 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2123 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2124 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2125 uint64_t const offPte = idxPte << 3;
2126 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2127 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2128 if (RT_FAILURE(rc))
2129 {
2130 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2131 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2132 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2133 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2134 return VERR_IOMMU_IPE_2;
2135 }
2136 }
2137
2138 /* Check present bit. */
2139 if (PtEntity.n.u1Present)
2140 { /* likely */ }
2141 else
2142 {
2143 LogFunc(("Page table entry not present -> IOPF"));
2144 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2145 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2146 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2147 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2148 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2149 }
2150
2151 /* Check permission bits. */
2152 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2153 if ((fAccess & fPtePerm) == fAccess)
2154 { /* likely */ }
2155 else
2156 {
2157 LogFunc(("Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF\n", fAccess, fPtePerm));
2158 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2159 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2160 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2161 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2162 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2163 }
2164
2165 /* If this is a PTE, we're at the final level and we're done. */
2166 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2167 if (uNextLevel == 0)
2168 {
2169 /* The page size of the translation is the default (4K). */
2170 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2171 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2172 pWalkResult->fIoPerm = fPtePerm;
2173 return VINF_SUCCESS;
2174 }
2175 if (uNextLevel == 7)
2176 {
2177 /* The default page size of the translation is overridden. */
2178 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2179 uint8_t cShift = X86_PAGE_4K_SHIFT;
2180 while (GCPhysPte & RT_BIT_64(cShift++))
2181 ;
2182
2183 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2184 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2185 if ( cShift > s_acIovaLevelShifts[uLevel]
2186 && cShift < s_acIovaLevelShifts[uLevel + 1])
2187 {
2188 pWalkResult->GCPhysSpa = GCPhysPte;
2189 pWalkResult->cShift = cShift;
2190 pWalkResult->fIoPerm = fPtePerm;
2191 return VINF_SUCCESS;
2192 }
2193
2194 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2195 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2196 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2197 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2198 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2199 kIoPageFaultType_PteInvalidPageSize);
2200 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2201 }
2202
2203 /* Validate the next level encoding of the PDE. */
2204#if IOMMU_MAX_HOST_PT_LEVEL < 6
2205 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2206 { /* likely */ }
2207 else
2208 {
2209 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2210 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2211 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2212 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2213 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2214 kIoPageFaultType_PteInvalidLvlEncoding);
2215 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2216 }
2217#else
2218 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2219#endif
2220
2221 /* Validate level transition. */
2222 if (uNextLevel < uLevel)
2223 { /* likely */ }
2224 else
2225 {
2226 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2227 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2228 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2229 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2230 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2231 kIoPageFaultType_PteInvalidLvlEncoding);
2232 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2233 }
2234
2235 /* Ensure IOVA bits of skipped levels are zero. */
2236 Assert(uLevel > 0);
2237 uint64_t uIovaSkipMask = 0;
2238 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2239 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2240 if (!(uIova & uIovaSkipMask))
2241 { /* likely */ }
2242 else
2243 {
2244 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2245 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2246 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2247 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2248 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2249 kIoPageFaultType_SkippedLevelIovaNotZero);
2250 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2251 }
2252
2253 /* Continue with traversing the page directory at this level. */
2254 }
2255}
2256
2257
2258/**
2259 * Looks up an I/O virtual address from the device table.
2260 *
2261 * @returns VBox status code.
2262 * @param pDevIns The IOMMU instance data.
2263 * @param uDevId The device ID.
2264 * @param uIova The I/O virtual address to lookup.
2265 * @param cbAccess The size of the access.
2266 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2267 * permissions for the access being made.
2268 * @param enmOp The IOMMU operation being performed.
2269 * @param pGCPhysSpa Where to store the translated system physical address. Only
2270 * valid when translation succeeds and VINF_SUCCESS is
2271 * returned!
2272 *
2273 * @thread Any.
2274 */
2275static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2276 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2277{
2278 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2279
2280 /* Read the device table entry from memory. */
2281 DTE_T Dte;
2282 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2283 if (RT_SUCCESS(rc))
2284 {
2285 /* If the DTE is not valid, addresses are forwarded without translation */
2286 if (Dte.n.u1Valid)
2287 { /* likely */ }
2288 else
2289 {
2290 /** @todo IOMMU: Add to IOLTB cache. */
2291 *pGCPhysSpa = uIova;
2292 return VINF_SUCCESS;
2293 }
2294
2295 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2296 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2297 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2298 if (RT_LIKELY( !fRsvd0
2299 && !fRsvd1))
2300 { /* likely */ }
2301 else
2302 {
2303 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2304 EVT_ILLEGAL_DTE_T Event;
2305 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2306 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2307 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2308 }
2309
2310 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2311 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
2312 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2313 { /* likely */ }
2314 else
2315 {
2316 /** @todo IOMMU: Add to IOLTB cache. */
2317 *pGCPhysSpa = uIova;
2318 return VINF_SUCCESS;
2319 }
2320
2321 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
2322 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
2323
2324 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
2325 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2326 uint64_t cbRemaining = cbAccess;
2327 for (;;)
2328 {
2329 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
2330 IOWALKRESULT WalkResult;
2331 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
2332 if (RT_SUCCESS(rc))
2333 {
2334 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
2335
2336 /* Store the translated base address before continuing to check permissions for any more pages. */
2337 if (cbRemaining == cbAccess)
2338 {
2339 RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2340 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2341 }
2342
2343 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
2344 if (cbRemaining > cbPhysPage - offIova)
2345 {
2346 cbRemaining -= (cbPhysPage - offIova);
2347 uBaseIova += cbPhysPage;
2348 offIova = 0;
2349 }
2350 else
2351 break;
2352 }
2353 else
2354 {
2355 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
2356 uBaseIova, fAccess, rc));
2357 *pGCPhysSpa = NIL_RTGCPHYS;
2358 return rc;
2359 }
2360 }
2361
2362 return rc;
2363 }
2364
2365 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2366 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2367}
2368
2369
2370/**
2371 * Memory read request from a device.
2372 *
2373 * @returns VBox status code.
2374 * @param pDevIns The IOMMU device instance.
2375 * @param uDevId The device ID (bus, device, function).
2376 * @param uIova The I/O virtual address being read.
2377 * @param cbRead The number of bytes being read.
2378 * @param pGCPhysSpa Where to store the translated system physical address.
2379 *
2380 * @thread Any.
2381 */
2382static DECLCALLBACK(int) iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
2383 PRTGCPHYS pGCPhysSpa)
2384{
2385 /* Validate. */
2386 Assert(pDevIns);
2387 Assert(pGCPhysSpa);
2388 Assert(cbRead > 0);
2389
2390 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2391 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
2392
2393 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2394 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2395 if (Ctrl.n.u1IommuEn)
2396 {
2397 /** @todo IOMMU: IOTLB cache lookup. */
2398
2399 /* Lookup the IOVA from the device table. */
2400 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
2401 }
2402
2403 *pGCPhysSpa = uIova;
2404 return VINF_SUCCESS;
2405}
2406
2407
2408/**
2409 * Memory write request from a device.
2410 *
2411 * @returns VBox status code.
2412 * @param pDevIns The IOMMU device instance.
2413 * @param uDevId The device ID (bus, device, function).
2414 * @param uIova The I/O virtual address being written.
2415 * @param cbWrite The number of bytes being written.
2416 * @param pGCPhysSpa Where to store the translated physical address.
2417 *
2418 * @thread Any.
2419 */
2420static DECLCALLBACK(int) iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
2421 PRTGCPHYS pGCPhysSpa)
2422{
2423 /* Validate. */
2424 Assert(pDevIns);
2425 Assert(pGCPhysSpa);
2426 Assert(cbWrite > 0);
2427
2428 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2429 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
2430
2431 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2432 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2433 if (Ctrl.n.u1IommuEn)
2434 {
2435 /** @todo IOMMU: IOTLB cache lookup. */
2436
2437 /* Lookup the IOVA from the device table. */
2438 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
2439 }
2440
2441 *pGCPhysSpa = uIova;
2442 return VINF_SUCCESS;
2443}
2444
2445
2446/**
2447 * Reads an interrupt remapping table entry from guest memory given its DTE.
2448 *
2449 * @returns VBox status code.
2450 * @param pDevIns The IOMMU device instance.
2451 * @param uDevId The device ID.
2452 * @param pDte The device table entry.
2453 * @param GCPhysIn The source MSI address.
2454 * @param uDataIn The source MSI data.
2455 * @param enmOp The IOMMU operation being performed.
2456 * @param pIrte Where to store the interrupt remapping table entry.
2457 *
2458 * @thread Any.
2459 */
2460static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
2461 IOMMUOP enmOp, PIRTE_T pIrte)
2462{
2463 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
2464 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) << IOMMU_IRTE_SIZE_SHIFT;
2465 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
2466
2467 /* Ensure the IRTE offset is within the specified table size. */
2468 Assert(pDte->n.u4IntrTableLength < 12);
2469 if (offIrte + sizeof(IRTE_T) <= (1U << pDte->n.u4IntrTableLength) << IOMMU_IRTE_SIZE_SHIFT)
2470 { /* likely */ }
2471 else
2472 {
2473 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2474 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
2475 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2476 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2477 kIoPageFaultType_IrteAddrInvalid);
2478 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2479 }
2480
2481 /* Read the IRTE from memory. */
2482 Assert(!(GCPhysIrte & 3));
2483 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
2484 if (RT_SUCCESS(rc))
2485 return VINF_SUCCESS;
2486
2487 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
2488 * situation. Is it an I/O page fault or a device table hardware error?
2489 * There's no interrupt table hardware error event, but it's unclear what
2490 * we should do here. */
2491 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
2492 return VERR_IOMMU_IPE_4;
2493}
2494
2495
2496/**
2497 * Remap the interrupt using the interrupt remapping table.
2498 *
2499 * @returns VBox status code.
2500 * @param pDevIns The IOMMU instance data.
2501 * @param uDevId The device ID.
2502 * @param pDte The device table entry.
2503 * @param enmOp The IOMMU operation being performed.
2504 * @param pMsiIn The source MSI.
2505 * @param pMsiOut Where to store the remapped MSI.
2506 *
2507 * @thread Any.
2508 */
2509static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
2510 PMSIMSG pMsiOut)
2511{
2512 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
2513
2514 IRTE_T Irte;
2515 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
2516 if (RT_SUCCESS(rc))
2517 {
2518 if (Irte.n.u1RemapEnable)
2519 {
2520 if (!Irte.n.u1GuestMode)
2521 {
2522 if (Irte.n.u3IntrType < VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
2523 {
2524 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
2525 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
2526 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
2527 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
2528
2529 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
2530 pMsiOut->Data.u32 = pMsiIn->Data.u32;
2531 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
2532 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
2533
2534 return VINF_SUCCESS;
2535 }
2536
2537 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
2538 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2539 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2540 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2541 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
2542 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2543 }
2544
2545 LogFunc(("Guest mode not supported -> IOPF\n"));
2546 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2547 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2548 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2549 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
2550 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2551 }
2552
2553 LogFunc(("Remapping disabled -> IOPF\n"));
2554 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2555 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2556 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2557 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
2558 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2559 }
2560
2561 return rc;
2562}
2563
2564
2565/**
2566 * Looks up an MSI interrupt from the interrupt remapping table.
2567 *
2568 * @returns VBox status code.
2569 * @param pDevIns The IOMMU instance data.
2570 * @param uDevId The device ID.
2571 * @param enmOp The IOMMU operation being performed.
2572 * @param pMsiIn The source MSI.
2573 * @param pMsiOut Where to store the remapped MSI.
2574 *
2575 * @thread Any.
2576 */
2577static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2578{
2579 /* Read the device table entry from memory. */
2580 LogFlowFunc(("uDevId=%#x enmOp=%u\n", uDevId, enmOp));
2581
2582 DTE_T Dte;
2583 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2584 if (RT_SUCCESS(rc))
2585 {
2586 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
2587 if (Dte.n.u1IntrMapValid)
2588 {
2589 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
2590 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
2591 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
2592 if (RT_LIKELY( !fRsvd0
2593 && !fRsvd1))
2594 { /* likely */ }
2595 else
2596 {
2597 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
2598 fRsvd1));
2599 EVT_ILLEGAL_DTE_T Event;
2600 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
2601 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2602 return VERR_IOMMU_INTR_REMAP_FAILED;
2603 }
2604
2605 /*
2606 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
2607 * that's connected through HyperTransport it might be possible; but for us, it
2608 * doesn't seem we need to specially handle these pins.
2609 */
2610
2611 /*
2612 * Validate the MSI source address.
2613 *
2614 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
2615 * CPU is concerned, the MSI region is fixed and we must ensure no other device
2616 * claims the region as I/O space.
2617 *
2618 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
2619 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
2620 * See Intel spec. 10.11.1 "Message Address Register Format".
2621 */
2622 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
2623 {
2624 /*
2625 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
2626 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
2627 */
2628 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
2629 bool fPassThru = false;
2630 switch (u8DeliveryMode)
2631 {
2632 case VBOX_MSI_DELIVERY_MODE_FIXED:
2633 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
2634 {
2635 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
2636 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
2637 {
2638 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
2639 iommuAmdSetPciTargetAbort(pDevIns);
2640 return VERR_IOMMU_INTR_REMAP_DENIED;
2641 }
2642
2643 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
2644 {
2645 fPassThru = true;
2646 break;
2647 }
2648
2649 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
2650 {
2651 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
2652 uint32_t const uIntTabLen = Dte.n.u4IntrTableLength;
2653 if (Dte.n.u4IntrTableLength < 12)
2654 {
2655 /*
2656 * We don't support guest interrupt remapping yet. When we do, we'll need to
2657 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
2658 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
2659 * already reads the control register, add that as a parameter when we eventually
2660 * support guest interrupt remapping. For now, just assert.
2661 */
2662 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2663 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
2664 NOREF(pThis);
2665
2666 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
2667 }
2668
2669 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntTabLen));
2670 EVT_ILLEGAL_DTE_T Event;
2671 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
2672 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
2673 return VERR_IOMMU_INTR_REMAP_FAILED;
2674 }
2675
2676 /* Paranoia. */
2677 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
2678
2679 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
2680
2681 EVT_ILLEGAL_DTE_T Event;
2682 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
2683 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
2684 return VERR_IOMMU_INTR_REMAP_FAILED;
2685 }
2686
2687 /* SMIs are passed through unmapped. We don't implement SMI filters. */
2688 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
2689 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
2690 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
2691 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
2692 default:
2693 {
2694 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
2695 iommuAmdSetPciTargetAbort(pDevIns);
2696 return VERR_IOMMU_INTR_REMAP_FAILED;
2697 }
2698 }
2699
2700 if (fPassThru)
2701 {
2702 *pMsiOut = *pMsiIn;
2703 return VINF_SUCCESS;
2704 }
2705
2706 iommuAmdSetPciTargetAbort(pDevIns);
2707 return VERR_IOMMU_INTR_REMAP_DENIED;
2708 }
2709 else
2710 {
2711 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
2712 return VERR_IOMMU_INTR_REMAP_FAILED;
2713 }
2714 }
2715 else
2716 {
2717 /** @todo IOMMU: Add to interrupt remapping cache. */
2718 LogFlowFunc(("DTE interrupt map not valid\n"));
2719 *pMsiOut = *pMsiIn;
2720 return VINF_SUCCESS;
2721 }
2722 }
2723
2724 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2725 return VERR_IOMMU_INTR_REMAP_FAILED;
2726}
2727
2728
2729/**
2730 * Interrupt remap request from a device.
2731 *
2732 * @returns VBox status code.
2733 * @param pDevIns The IOMMU device instance.
2734 * @param uDevId The device ID (bus, device, function).
2735 * @param pMsiIn The source MSI.
2736 * @param pMsiOut Where to store the remapped MSI.
2737 */
2738static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2739{
2740 /* Validate. */
2741 Assert(pDevIns);
2742 Assert(pMsiIn);
2743 Assert(pMsiOut);
2744
2745 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2746 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
2747
2748 LogFlowFunc(("uDevId=%#x\n", uDevId));
2749
2750 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
2751 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2752 if (Ctrl.n.u1IommuEn)
2753 {
2754 /** @todo Cache? */
2755
2756 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
2757 }
2758
2759 *pMsiOut = *pMsiIn;
2760 return VINF_SUCCESS;
2761}
2762
2763
2764/**
2765 * @callback_method_impl{FNIOMMMIONEWWRITE}
2766 */
2767static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
2768{
2769 NOREF(pvUser);
2770 Assert(cb == 4 || cb == 8);
2771 Assert(!(off & (cb - 1)));
2772
2773 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2774 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
2775
2776 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
2777 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
2778}
2779
2780
2781/**
2782 * @callback_method_impl{FNIOMMMIONEWREAD}
2783 */
2784static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
2785{
2786 NOREF(pvUser);
2787 Assert(cb == 4 || cb == 8);
2788 Assert(!(off & (cb - 1)));
2789
2790 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2791 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
2792
2793 uint64_t uResult;
2794 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
2795 if (cb == 8)
2796 *(uint64_t *)pv = uResult;
2797 else
2798 *(uint32_t *)pv = (uint32_t)uResult;
2799
2800 return rcStrict;
2801}
2802
2803# ifdef IN_RING3
2804
2805/**
2806 * Processes an IOMMU command.
2807 *
2808 * @returns VBox status code.
2809 * @param pDevIns The IOMMU device instance.
2810 * @param pCmd The command to process.
2811 * @param GCPhysCmd The system physical address of the command.
2812 * @param pEvtError Where to store the error event in case of failures.
2813 *
2814 * @thread Command thread.
2815 */
2816static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
2817{
2818 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
2819
2820 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2821 STAM_COUNTER_INC(&pThis->StatCmd);
2822
2823 uint8_t const bCmd = pCmd->n.u4Opcode;
2824 switch (bCmd)
2825 {
2826 case IOMMU_CMD_COMPLETION_WAIT:
2827 {
2828 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
2829
2830 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
2831 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
2832
2833 /* Validate reserved bits in the command. */
2834 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
2835 {
2836 /* If Completion Store is requested, write the StoreData to the specified address. */
2837 if (pCmdComWait->n.u1Store)
2838 {
2839 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
2840 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
2841 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
2842 if (RT_FAILURE(rc))
2843 {
2844 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
2845 GCPhysStore, rc));
2846 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
2847 return VERR_IOMMU_CMD_HW_ERROR;
2848 }
2849 }
2850
2851 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
2852 if (pCmdComWait->n.u1Interrupt)
2853 {
2854 IOMMU_LOCK(pDevIns);
2855 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
2856 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2857 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
2858 IOMMU_UNLOCK(pDevIns);
2859
2860 if (fRaiseInt)
2861 iommuAmdRaiseMsiInterrupt(pDevIns);
2862 }
2863
2864 return VINF_SUCCESS;
2865 }
2866 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2867 return VERR_IOMMU_CMD_INVALID_FORMAT;
2868 }
2869
2870 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
2871 {
2872 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2873 * then. */
2874 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
2875 return VINF_SUCCESS;
2876 }
2877
2878 case IOMMU_CMD_INV_IOMMU_PAGES:
2879 {
2880 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2881 * then. */
2882 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
2883 return VINF_SUCCESS;
2884 }
2885
2886 case IOMMU_CMD_INV_IOTLB_PAGES:
2887 {
2888 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
2889
2890 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
2891 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
2892 {
2893 /** @todo IOMMU: Implement remote IOTLB invalidation. */
2894 return VERR_NOT_IMPLEMENTED;
2895 }
2896 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2897 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2898 }
2899
2900 case IOMMU_CMD_INV_INTR_TABLE:
2901 {
2902 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2903 * then. */
2904 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
2905 return VINF_SUCCESS;
2906 }
2907
2908 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
2909 {
2910 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
2911 if (pThis->ExtFeat.n.u1PrefetchSup)
2912 {
2913 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
2914 return VINF_SUCCESS;
2915 }
2916 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2917 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2918 }
2919
2920 case IOMMU_CMD_COMPLETE_PPR_REQ:
2921 {
2922 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
2923
2924 /* We don't support PPR requests yet. */
2925 Assert(!pThis->ExtFeat.n.u1PprSup);
2926 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2927 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2928 }
2929
2930 case IOMMU_CMD_INV_IOMMU_ALL:
2931 {
2932 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
2933
2934 if (pThis->ExtFeat.n.u1InvAllSup)
2935 {
2936 /** @todo IOMMU: Invalidate all. Pretend success until then. */
2937 return VINF_SUCCESS;
2938 }
2939 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2940 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2941 }
2942 }
2943
2944 STAM_COUNTER_DEC(&pThis->StatCmd);
2945 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
2946 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2947 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2948}
2949
2950
2951/**
2952 * The IOMMU command thread.
2953 *
2954 * @returns VBox status code.
2955 * @param pDevIns The IOMMU device instance.
2956 * @param pThread The command thread.
2957 */
2958static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2959{
2960 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2961
2962 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2963 return VINF_SUCCESS;
2964
2965 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2966 {
2967 /*
2968 * Sleep perpetually until we are woken up to process commands.
2969 */
2970 {
2971 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
2972 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
2973 if (!fSignaled)
2974 {
2975 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
2976 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
2977 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2978 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2979 break;
2980 Log5Func(("Woken up with rc=%Rrc\n", rc));
2981 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
2982 }
2983 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
2984 }
2985
2986 /*
2987 * Fetch and process IOMMU commands.
2988 */
2989 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
2990 * at a time) and is expensive due to calls to PGM for fetching guest memory.
2991 * We could optimize by fetching a bunch of commands at a time reducing
2992 * number of calls to PGM. In the longer run we could lock the memory and
2993 * mappings and accessing them directly. */
2994 IOMMU_LOCK(pDevIns);
2995
2996 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2997 if (Status.n.u1CmdBufRunning)
2998 {
2999 /* Get the offset we need to read the command from memory (circular buffer offset). */
3000 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3001 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3002 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3003 Assert(offHead < cbCmdBuf);
3004 while (offHead != pThis->CmdBufTailPtr.n.off)
3005 {
3006 /* Read the command from memory. */
3007 CMD_GENERIC_T Cmd;
3008 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3009 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3010 if (RT_SUCCESS(rc))
3011 {
3012 /* Increment the command buffer head pointer. */
3013 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3014 pThis->CmdBufHeadPtr.n.off = offHead;
3015
3016 /* Process the fetched command. */
3017 EVT_GENERIC_T EvtError;
3018 IOMMU_UNLOCK(pDevIns);
3019 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3020 IOMMU_LOCK(pDevIns);
3021 if (RT_FAILURE(rc))
3022 {
3023 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3024 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3025 {
3026 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3027 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3028 }
3029 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3030 {
3031 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3032 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3033 }
3034 break;
3035 }
3036 }
3037 else
3038 {
3039 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3040 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3041 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3042 break;
3043 }
3044 }
3045 }
3046
3047 IOMMU_UNLOCK(pDevIns);
3048 }
3049
3050 LogFlowFunc(("Command thread terminating\n"));
3051 return VINF_SUCCESS;
3052}
3053
3054
3055/**
3056 * Wakes up the command thread so it can respond to a state change.
3057 *
3058 * @returns VBox status code.
3059 * @param pDevIns The IOMMU device instance.
3060 * @param pThread The command thread.
3061 */
3062static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3063{
3064 RT_NOREF(pThread);
3065 LogFlowFunc(("\n"));
3066 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3067 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3068}
3069
3070
3071/**
3072 * @callback_method_impl{FNPCICONFIGREAD}
3073 */
3074static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3075 unsigned cb, uint32_t *pu32Value)
3076{
3077 /** @todo IOMMU: PCI config read stat counter. */
3078 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3079 Log3Func(("Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
3080 VBOXSTRICTRC_VAL(rcStrict)));
3081 return rcStrict;
3082}
3083
3084
3085/**
3086 * @callback_method_impl{FNPCICONFIGWRITE}
3087 */
3088static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3089 unsigned cb, uint32_t u32Value)
3090{
3091 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3092
3093 /*
3094 * Discard writes to read-only registers that are specific to the IOMMU.
3095 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3096 * See PCI spec. 6.1. "Configuration Space Organization".
3097 */
3098 switch (uAddress)
3099 {
3100 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3101 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3102 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3103 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3104 {
3105 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3106 return VINF_SUCCESS;
3107 }
3108 }
3109
3110 IOMMU_LOCK(pDevIns);
3111
3112 VBOXSTRICTRC rcStrict = VERR_INVALID_FUNCTION;
3113 switch (uAddress)
3114 {
3115 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3116 {
3117 if (pThis->IommuBar.n.u1Enable)
3118 {
3119 rcStrict = VINF_SUCCESS;
3120 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3121 break;
3122 }
3123
3124 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3125 if (pThis->IommuBar.n.u1Enable)
3126 {
3127 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE);
3128 Assert(PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio) == NIL_RTGCPHYS);
3129 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3130 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3131 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3132 if (RT_FAILURE(rcStrict))
3133 LogFunc(("Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
3134 }
3135 break;
3136 }
3137
3138 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3139 {
3140 if (!pThis->IommuBar.n.u1Enable)
3141 pThis->IommuBar.au32[1] = u32Value;
3142 else
3143 {
3144 rcStrict = VINF_SUCCESS;
3145 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3146 }
3147 break;
3148 }
3149
3150 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3151 {
3152 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3153 RT_FALL_THRU();
3154 }
3155 default:
3156 {
3157 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3158 break;
3159 }
3160 }
3161
3162 IOMMU_UNLOCK(pDevIns);
3163
3164 Log3Func(("PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
3165 return rcStrict;
3166}
3167
3168
3169/**
3170 * @callback_method_impl{FNDBGFHANDLERDEV}
3171 */
3172static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3173{
3174 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3175 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3176 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3177
3178 LogFlowFunc(("pThis=%p pszArgs=%s\n", pThis, pszArgs));
3179 bool fVerbose;
3180 if ( pszArgs
3181 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3182 fVerbose = true;
3183 else
3184 fVerbose = false;
3185
3186 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3187 /* Device Table Base Addresses (all segments). */
3188 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3189 {
3190 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3191 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3192 if (fVerbose)
3193 {
3194 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3195 IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
3196 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3197 }
3198 }
3199 /* Command Buffer Base Address Register. */
3200 {
3201 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3202 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3203 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3204 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3205 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
3206 if (fVerbose)
3207 {
3208 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3209 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3210 cEntries, cbBuffer);
3211 }
3212 }
3213 /* Event Log Base Address Register. */
3214 {
3215 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3216 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3217 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3218 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3219 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
3220 if (fVerbose)
3221 {
3222 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3223 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3224 cEntries, cbBuffer);
3225 }
3226 }
3227 /* IOMMU Control Register. */
3228 {
3229 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3230 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3231 if (fVerbose)
3232 {
3233 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3234 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3235 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3236 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3237 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3238 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3239 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3240 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3241 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3242 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3243 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3244 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3245 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3246 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3247 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3248 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3249 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3250 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3251 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3252 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3253 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3254 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3255 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3256 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3257 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3258 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3259 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3260 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3261 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3262 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3263 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3264 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3265 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3266 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3267 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3268 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3269 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3270 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3271 }
3272 }
3273 /* Exclusion Base Address Register. */
3274 {
3275 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3276 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3277 if (fVerbose)
3278 {
3279 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3280 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3281 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
3282 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
3283 }
3284 }
3285 /* Exclusion Range Limit Register. */
3286 {
3287 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3288 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3289 if (fVerbose)
3290 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
3291 }
3292 /* Extended Feature Register. */
3293 {
3294 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3295 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3296 if (fVerbose)
3297 {
3298 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3299 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3300 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3301 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3302 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3303 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3304 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3305 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3306 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3307 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3308 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3309 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3310 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3311 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3312 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3313 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3314 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3315 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3316 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3317 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
3318 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
3319 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3320 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3321 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3322 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3323 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3324 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3325 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3326 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3327 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3328 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3329 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3330 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3331 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3332 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3333 }
3334 }
3335 /* PPR Log Base Address Register. */
3336 {
3337 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3338 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
3339 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3340 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3341 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3342 if (fVerbose)
3343 {
3344 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3345 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3346 cEntries, cbBuffer);
3347 }
3348 }
3349 /* Hardware Event (Hi) Register. */
3350 {
3351 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
3352 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
3353 if (fVerbose)
3354 {
3355 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
3356 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
3357 }
3358 }
3359 /* Hardware Event (Lo) Register. */
3360 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
3361 /* Hardware Event Status. */
3362 {
3363 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
3364 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
3365 if (fVerbose)
3366 {
3367 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
3368 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
3369 }
3370 }
3371 /* Guest Virtual-APIC Log Base Address Register. */
3372 {
3373 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
3374 uint8_t const uEncodedLen = GALogBar.n.u4Len;
3375 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3376 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3377 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
3378 if (fVerbose)
3379 {
3380 pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3381 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3382 cEntries, cbBuffer);
3383 }
3384 }
3385 /* Guest Virtual-APIC Log Tail Address Register. */
3386 {
3387 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
3388 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
3389 if (fVerbose)
3390 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
3391 }
3392 /* PPR Log B Base Address Register. */
3393 {
3394 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
3395 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
3396 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3397 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3398 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
3399 if (fVerbose)
3400 {
3401 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3402 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3403 cEntries, cbBuffer);
3404 }
3405 }
3406 /* Event Log B Base Address Register. */
3407 {
3408 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
3409 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
3410 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3411 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3412 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
3413 if (fVerbose)
3414 {
3415 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3416 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3417 cEntries, cbBuffer);
3418 }
3419 }
3420 /* Device-Specific Feature Extension Register. */
3421 {
3422 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
3423 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
3424 if (fVerbose)
3425 {
3426 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
3427 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
3428 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
3429 }
3430 }
3431 /* Device-Specific Control Extension Register. */
3432 {
3433 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
3434 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
3435 if (fVerbose)
3436 {
3437 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
3438 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
3439 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
3440 }
3441 }
3442 /* Device-Specific Status Extension Register. */
3443 {
3444 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
3445 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
3446 if (fVerbose)
3447 {
3448 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
3449 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
3450 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
3451 }
3452 }
3453 /* Miscellaneous Information Register (Lo and Hi). */
3454 {
3455 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
3456 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
3457 if (fVerbose)
3458 {
3459 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
3460 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
3461 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
3462 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
3463 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
3464 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
3465 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
3466 }
3467 }
3468 /* MSI Capability Header. */
3469 {
3470 MSI_CAP_HDR_T MsiCapHdr;
3471 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3472 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
3473 if (fVerbose)
3474 {
3475 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
3476 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
3477 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
3478 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
3479 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
3480 }
3481 }
3482 /* MSI Address Register (Lo and Hi). */
3483 {
3484 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3485 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3486 MSIADDR MsiAddr;
3487 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
3488 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
3489 if (fVerbose)
3490 {
3491 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
3492 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
3493 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
3494 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
3495 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
3496 }
3497 }
3498 /* MSI Data. */
3499 {
3500 MSIDATA MsiData;
3501 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3502 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
3503 if (fVerbose)
3504 {
3505 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
3506 MsiData.n.u8Vector);
3507 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
3508 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
3509 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
3510 "level" : "edge");
3511 }
3512 }
3513 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
3514 {
3515 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
3516 MsiMapCapHdr.u32 = 0;
3517 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
3518 if (fVerbose)
3519 {
3520 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
3521 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
3522 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
3523 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
3524 }
3525 }
3526 /* Performance Optimization Control Register. */
3527 {
3528 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
3529 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
3530 if (fVerbose)
3531 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
3532 }
3533 /* XT (x2APIC) General Interrupt Control Register. */
3534 {
3535 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
3536 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
3537 if (fVerbose)
3538 {
3539 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3540 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3541 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3542 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
3543 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
3544 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
3545 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3546 }
3547 }
3548 /* XT (x2APIC) PPR Interrupt Control Register. */
3549 {
3550 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
3551 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
3552 if (fVerbose)
3553 {
3554 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3555 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3556 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3557 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
3558 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
3559 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
3560 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3561 }
3562 }
3563 /* XT (X2APIC) GA Log Interrupt Control Register. */
3564 {
3565 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
3566 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
3567 if (fVerbose)
3568 {
3569 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3570 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3571 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3572 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
3573 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
3574 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
3575 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3576 }
3577 }
3578 /* MARC Registers. */
3579 {
3580 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
3581 {
3582 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
3583 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
3584 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
3585
3586 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
3587 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
3588 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
3589 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
3590
3591 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
3592 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
3593 }
3594 }
3595 /* Reserved Register. */
3596 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
3597 /* Command Buffer Head Pointer Register. */
3598 {
3599 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
3600 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
3601 CmdBufHeadPtr.n.off);
3602 }
3603 /* Command Buffer Tail Pointer Register. */
3604 {
3605 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
3606 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
3607 CmdBufTailPtr.n.off);
3608 }
3609 /* Event Log Head Pointer Register. */
3610 {
3611 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
3612 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
3613 EvtLogHeadPtr.n.off);
3614 }
3615 /* Event Log Tail Pointer Register. */
3616 {
3617 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
3618 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
3619 EvtLogTailPtr.n.off);
3620 }
3621 /* Status Register. */
3622 {
3623 IOMMU_STATUS_T const Status = pThis->Status;
3624 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
3625 if (fVerbose)
3626 {
3627 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
3628 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
3629 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
3630 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
3631 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
3632 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
3633 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
3634 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
3635 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
3636 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
3637 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
3638 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
3639 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
3640 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
3641 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
3642 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
3643 }
3644 }
3645 /* PPR Log Head Pointer. */
3646 {
3647 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
3648 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
3649 PprLogHeadPtr.n.off);
3650 }
3651 /* PPR Log Tail Pointer. */
3652 {
3653 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
3654 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
3655 PprLogTailPtr.n.off);
3656 }
3657 /* Guest Virtual-APIC Log Head Pointer. */
3658 {
3659 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
3660 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
3661 GALogHeadPtr.n.u12GALogPtr);
3662 }
3663 /* Guest Virtual-APIC Log Tail Pointer. */
3664 {
3665 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
3666 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
3667 GALogTailPtr.n.u12GALogPtr);
3668 }
3669 /* PPR Log B Head Pointer. */
3670 {
3671 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
3672 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
3673 PprLogBHeadPtr.n.off);
3674 }
3675 /* PPR Log B Tail Pointer. */
3676 {
3677 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
3678 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
3679 PprLogBTailPtr.n.off);
3680 }
3681 /* Event Log B Head Pointer. */
3682 {
3683 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
3684 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
3685 EvtLogBHeadPtr.n.off);
3686 }
3687 /* Event Log B Tail Pointer. */
3688 {
3689 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
3690 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
3691 EvtLogBTailPtr.n.off);
3692 }
3693 /* PPR Log Auto Response Register. */
3694 {
3695 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
3696 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
3697 if (fVerbose)
3698 {
3699 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
3700 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
3701 }
3702 }
3703 /* PPR Log Overflow Early Warning Indicator Register. */
3704 {
3705 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
3706 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
3707 if (fVerbose)
3708 {
3709 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
3710 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
3711 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
3712 }
3713 }
3714 /* PPR Log Overflow Early Warning Indicator Register. */
3715 {
3716 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
3717 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
3718 if (fVerbose)
3719 {
3720 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
3721 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
3722 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
3723 }
3724 }
3725}
3726
3727
3728/**
3729 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3730 */
3731static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3732{
3733 /** @todo IOMMU: Save state. */
3734 RT_NOREF2(pDevIns, pSSM);
3735 LogFlowFunc(("\n"));
3736 return VERR_NOT_IMPLEMENTED;
3737}
3738
3739
3740/**
3741 * @callback_method_impl{FNSSMDEVLOADEXEC}
3742 */
3743static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3744{
3745 /** @todo IOMMU: Load state. */
3746 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
3747 LogFlowFunc(("\n"));
3748 return VERR_NOT_IMPLEMENTED;
3749}
3750
3751
3752/**
3753 * @interface_method_impl{PDMDEVREG,pfnReset}
3754 */
3755static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
3756{
3757 /*
3758 * Resets read-write portion of the IOMMU state.
3759 *
3760 * State data not initialized here is expected to be initialized during
3761 * device construction and remain read-only through the lifetime of the VM.
3762 */
3763 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3764 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3765 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3766
3767 LogFlowFunc(("\n"));
3768
3769 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
3770
3771 pThis->CmdBufBaseAddr.u64 = 0;
3772 pThis->CmdBufBaseAddr.n.u4Len = 8;
3773
3774 pThis->EvtLogBaseAddr.u64 = 0;
3775 pThis->EvtLogBaseAddr.n.u4Len = 8;
3776
3777 pThis->Ctrl.u64 = 0;
3778 pThis->Ctrl.n.u1Coherent = 1;
3779 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
3780
3781 pThis->ExclRangeBaseAddr.u64 = 0;
3782 pThis->ExclRangeLimit.u64 = 0;
3783
3784 pThis->PprLogBaseAddr.u64 = 0;
3785 pThis->PprLogBaseAddr.n.u4Len = 8;
3786
3787 pThis->HwEvtHi.u64 = 0;
3788 pThis->HwEvtLo = 0;
3789 pThis->HwEvtStatus.u64 = 0;
3790
3791 pThis->GALogBaseAddr.u64 = 0;
3792 pThis->GALogBaseAddr.n.u4Len = 8;
3793 pThis->GALogTailAddr.u64 = 0;
3794
3795 pThis->PprLogBBaseAddr.u64 = 0;
3796 pThis->PprLogBBaseAddr.n.u4Len = 8;
3797
3798 pThis->EvtLogBBaseAddr.u64 = 0;
3799 pThis->EvtLogBBaseAddr.n.u4Len = 8;
3800
3801 pThis->PerfOptCtrl.u32 = 0;
3802
3803 pThis->XtGenIntrCtrl.u64 = 0;
3804 pThis->XtPprIntrCtrl.u64 = 0;
3805 pThis->XtGALogIntrCtrl.u64 = 0;
3806
3807 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
3808
3809 pThis->CmdBufHeadPtr.u64 = 0;
3810 pThis->CmdBufTailPtr.u64 = 0;
3811 pThis->EvtLogHeadPtr.u64 = 0;
3812 pThis->EvtLogTailPtr.u64 = 0;
3813
3814 pThis->Status.u64 = 0;
3815
3816 pThis->PprLogHeadPtr.u64 = 0;
3817 pThis->PprLogTailPtr.u64 = 0;
3818
3819 pThis->GALogHeadPtr.u64 = 0;
3820 pThis->GALogTailPtr.u64 = 0;
3821
3822 pThis->PprLogBHeadPtr.u64 = 0;
3823 pThis->PprLogBTailPtr.u64 = 0;
3824
3825 pThis->EvtLogBHeadPtr.u64 = 0;
3826 pThis->EvtLogBTailPtr.u64 = 0;
3827
3828 pThis->PprLogAutoResp.u64 = 0;
3829 pThis->PprLogOverflowEarly.u64 = 0;
3830 pThis->PprLogBOverflowEarly.u64 = 0;
3831
3832 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
3833 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
3834
3835 /*
3836 * I ASSUME all MMIO regions mapped by a PDM device are automatically unmapped
3837 * on VM reset. If not, we need to enable the following...
3838 */
3839#if 0
3840 /* Unmap the MMIO region on reset if it has been mapped previously. */
3841 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE);
3842 if (PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio) != NIL_RTGCPHYS)
3843 PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3844#endif
3845}
3846
3847
3848/**
3849 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3850 */
3851static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
3852{
3853 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3854 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3855 LogFlowFunc(("\n"));
3856
3857 /* Close the command thread semaphore. */
3858 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
3859 {
3860 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
3861 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
3862 }
3863 return VINF_SUCCESS;
3864}
3865
3866
3867/**
3868 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3869 */
3870static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3871{
3872 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3873 RT_NOREF(pCfg);
3874
3875 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3876 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3877 pThisCC->pDevInsR3 = pDevIns;
3878
3879 LogFlowFunc(("iInstance=%d\n", iInstance));
3880
3881 /*
3882 * Register the IOMMU with PDM.
3883 */
3884 PDMIOMMUREGR3 IommuReg;
3885 RT_ZERO(IommuReg);
3886 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3887 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
3888 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
3889 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
3890 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3891 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3892 if (RT_FAILURE(rc))
3893 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3894 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3895 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3896 N_("IOMMU helper version mismatch; got %#x expected %#x"),
3897 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3898 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3899 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3900 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3901 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3902
3903 /*
3904 * Initialize read-only PCI configuration space.
3905 */
3906 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3907 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3908
3909 /* Header. */
3910 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
3911 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
3912 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we write to main memory) */
3913 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
3914 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3915 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
3916 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
3917 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
3918 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
3919 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
3920 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
3921 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
3922 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
3923 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
3924
3925 /* Capability Header. */
3926 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
3927 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
3928 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
3929 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
3930 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
3931 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
3932 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
3933 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
3934 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
3935 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
3936 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
3937
3938 /* Base Address Register. */
3939 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
3940 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
3941
3942 /* IOMMU Range Register. */
3943 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
3944
3945 /* Misc. Information Register. */
3946 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
3947 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
3948 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
3949 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
3950 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
3951 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
3952 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
3953 uint32_t const uMiscInfoReg1 = 0;
3954 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
3955 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
3956
3957 /* MSI Capability Header register. */
3958 PDMMSIREG MsiReg;
3959 RT_ZERO(MsiReg);
3960 MsiReg.cMsiVectors = 1;
3961 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
3962 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
3963 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
3964
3965 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
3966#if 0
3967 /* MSI Address Lo. */
3968 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
3969 /* MSI Address Hi. */
3970 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
3971 /* MSI Data. */
3972 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
3973#endif
3974
3975#if 0
3976 /** @todo IOMMU: I don't know if we need to support this, enable later if
3977 * required. */
3978 /* MSI Mapping Capability Header register. */
3979 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
3980 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
3981 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
3982 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
3983 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
3984 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
3985 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
3986#endif
3987
3988 /*
3989 * Register the PCI function with PDM.
3990 */
3991 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3992 AssertLogRelRCReturn(rc, rc);
3993
3994 /*
3995 * Register MSI support for the PCI device.
3996 * This must be done -after- register it as a PCI device!
3997 */
3998 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
3999 AssertRCReturn(rc, rc);
4000
4001 /*
4002 * Intercept PCI config. space accesses.
4003 */
4004 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4005 AssertLogRelRCReturn(rc, rc);
4006
4007 /*
4008 * Create the MMIO region.
4009 * Mapping of the region is done when software configures it via PCI config space.
4010 */
4011 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4012 NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
4013 "AMD-IOMMU", &pThis->hMmio);
4014 AssertLogRelRCReturn(rc, rc);
4015
4016 /*
4017 * Register saved state.
4018 */
4019 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4020 NULL, NULL, NULL,
4021 NULL, iommuAmdR3SaveExec, NULL,
4022 NULL, iommuAmdR3LoadExec, NULL);
4023 AssertLogRelRCReturn(rc, rc);
4024
4025 /*
4026 * Register debugger info item.
4027 */
4028 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
4029 AssertLogRelRCReturn(rc, rc);
4030
4031# ifdef VBOX_WITH_STATISTICS
4032 /*
4033 * Statistics.
4034 */
4035 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4036 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4037
4038 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4039 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4040
4041 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemapR3", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
4042 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRZ", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
4043
4044 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
4045 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
4046 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
4047 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
4048 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
4049 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
4050 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
4051 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
4052 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
4053# endif
4054
4055 /*
4056 * Create the command thread and its event semaphore.
4057 */
4058 char szDevIommu[64];
4059 RT_ZERO(szDevIommu);
4060 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
4061 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
4062 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
4063 AssertLogRelRCReturn(rc, rc);
4064
4065 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
4066 AssertLogRelRCReturn(rc, rc);
4067
4068 /*
4069 * Initialize read-only registers.
4070 * NOTE! Fields here must match their corresponding field in the ACPI tables.
4071 */
4072 /** @todo Don't remove the =0 assignment for now. It's just there so it's easier
4073 * for me to see existing features that we might want to implement. Do it
4074 * later. */
4075 pThis->ExtFeat.u64 = 0;
4076 pThis->ExtFeat.n.u1PrefetchSup = 0;
4077 pThis->ExtFeat.n.u1PprSup = 0;
4078 pThis->ExtFeat.n.u1X2ApicSup = 0;
4079 pThis->ExtFeat.n.u1NoExecuteSup = 0;
4080 pThis->ExtFeat.n.u1GstTranslateSup = 0;
4081 pThis->ExtFeat.n.u1InvAllSup = 0;
4082 pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4083 pThis->ExtFeat.n.u1HwErrorSup = 1;
4084 pThis->ExtFeat.n.u1PerfCounterSup = 0;
4085 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4086 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4087 pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
4088 pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
4089 pThis->ExtFeat.n.u2SmiFilterSup = 0;
4090 pThis->ExtFeat.n.u3SmiFilterCount = 0;
4091 pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
4092 pThis->ExtFeat.n.u2DualPprLogSup = 0;
4093 pThis->ExtFeat.n.u2DualEvtLogSup = 0;
4094 pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
4095 pThis->ExtFeat.n.u1UserSupervisorSup = 0;
4096 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
4097 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
4098 pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
4099 pThis->ExtFeat.n.u1PprAutoRespSup = 0;
4100 pThis->ExtFeat.n.u2MarcSup = 0;
4101 pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
4102 pThis->ExtFeat.n.u1PerfOptSup = 0;
4103 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
4104 pThis->ExtFeat.n.u1GstIoSup = 0;
4105 pThis->ExtFeat.n.u1HostAccessSup = 0;
4106 pThis->ExtFeat.n.u1EnhancedPprSup = 0;
4107 pThis->ExtFeat.n.u1AttrForwardSup = 0;
4108 pThis->ExtFeat.n.u1HostDirtySup = 0;
4109 pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
4110 pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
4111 pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
4112
4113 pThis->RsvdReg = 0;
4114
4115 pThis->DevSpecificFeat.u64 = 0;
4116 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
4117 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
4118
4119 pThis->DevSpecificCtrl.u64 = 0;
4120 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
4121 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
4122
4123 pThis->DevSpecificStatus.u64 = 0;
4124 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
4125 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
4126
4127 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
4128
4129 /*
4130 * Initialize parts of the IOMMU state as it would during reset.
4131 * Must be called -after- initializing PCI config. space registers.
4132 */
4133 iommuAmdR3Reset(pDevIns);
4134
4135 return VINF_SUCCESS;
4136}
4137
4138# else /* !IN_RING3 */
4139
4140/**
4141 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4142 */
4143static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
4144{
4145 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4146 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4147 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4148
4149 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4150
4151 /* Set up the MMIO RZ handlers. */
4152 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
4153 AssertRCReturn(rc, rc);
4154
4155 /* Set up the IOMMU RZ callbacks. */
4156 PDMIOMMUREGCC IommuReg;
4157 RT_ZERO(IommuReg);
4158 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4159 IommuReg.idxIommu = pThis->idxIommu;
4160 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4161 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4162 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4163 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4164 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4165 AssertRCReturn(rc, rc);
4166
4167 return VINF_SUCCESS;
4168}
4169
4170# endif /* !IN_RING3 */
4171
4172/**
4173 * The device registration structure.
4174 */
4175const PDMDEVREG g_DeviceIommuAmd =
4176{
4177 /* .u32Version = */ PDM_DEVREG_VERSION,
4178 /* .uReserved0 = */ 0,
4179 /* .szName = */ "iommu-amd",
4180 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4181 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4182 /* .cMaxInstances = */ ~0U,
4183 /* .uSharedVersion = */ 42,
4184 /* .cbInstanceShared = */ sizeof(IOMMU),
4185 /* .cbInstanceCC = */ sizeof(IOMMUCC),
4186 /* .cbInstanceRC = */ sizeof(IOMMURC),
4187 /* .cMaxPciDevices = */ 1,
4188 /* .cMaxMsixVectors = */ 0,
4189 /* .pszDescription = */ "IOMMU (AMD)",
4190#if defined(IN_RING3)
4191 /* .pszRCMod = */ "VBoxDDRC.rc",
4192 /* .pszR0Mod = */ "VBoxDDR0.r0",
4193 /* .pfnConstruct = */ iommuAmdR3Construct,
4194 /* .pfnDestruct = */ iommuAmdR3Destruct,
4195 /* .pfnRelocate = */ NULL,
4196 /* .pfnMemSetup = */ NULL,
4197 /* .pfnPowerOn = */ NULL,
4198 /* .pfnReset = */ iommuAmdR3Reset,
4199 /* .pfnSuspend = */ NULL,
4200 /* .pfnResume = */ NULL,
4201 /* .pfnAttach = */ NULL,
4202 /* .pfnDetach = */ NULL,
4203 /* .pfnQueryInterface = */ NULL,
4204 /* .pfnInitComplete = */ NULL,
4205 /* .pfnPowerOff = */ NULL,
4206 /* .pfnSoftReset = */ NULL,
4207 /* .pfnReserved0 = */ NULL,
4208 /* .pfnReserved1 = */ NULL,
4209 /* .pfnReserved2 = */ NULL,
4210 /* .pfnReserved3 = */ NULL,
4211 /* .pfnReserved4 = */ NULL,
4212 /* .pfnReserved5 = */ NULL,
4213 /* .pfnReserved6 = */ NULL,
4214 /* .pfnReserved7 = */ NULL,
4215#elif defined(IN_RING0)
4216 /* .pfnEarlyConstruct = */ NULL,
4217 /* .pfnConstruct = */ iommuAmdRZConstruct,
4218 /* .pfnDestruct = */ NULL,
4219 /* .pfnFinalDestruct = */ NULL,
4220 /* .pfnRequest = */ NULL,
4221 /* .pfnReserved0 = */ NULL,
4222 /* .pfnReserved1 = */ NULL,
4223 /* .pfnReserved2 = */ NULL,
4224 /* .pfnReserved3 = */ NULL,
4225 /* .pfnReserved4 = */ NULL,
4226 /* .pfnReserved5 = */ NULL,
4227 /* .pfnReserved6 = */ NULL,
4228 /* .pfnReserved7 = */ NULL,
4229#elif defined(IN_RC)
4230 /* .pfnConstruct = */ iommuAmdRZConstruct,
4231 /* .pfnReserved0 = */ NULL,
4232 /* .pfnReserved1 = */ NULL,
4233 /* .pfnReserved2 = */ NULL,
4234 /* .pfnReserved3 = */ NULL,
4235 /* .pfnReserved4 = */ NULL,
4236 /* .pfnReserved5 = */ NULL,
4237 /* .pfnReserved6 = */ NULL,
4238 /* .pfnReserved7 = */ NULL,
4239#else
4240# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4241#endif
4242 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4243};
4244
4245#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4246
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