VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86087

Last change on this file since 86087 was 86087, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Dump device tables. Needs re-work, dumping 2M of data in the debugger overwhelms it.
Maybe change to dump specific DTEs given the Device ID later.
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File size: 186.5 KB
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1/* $Id: DevIommuAmd.cpp 86087 2020-09-10 17:52:45Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31
32#include "VBoxDD.h"
33#include "DevIommuAmd.h"
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** Release log prefix string. */
40#define IOMMU_LOG_PFX "IOMMU-AMD"
41/** The current saved state version. */
42#define IOMMU_SAVED_STATE_VERSION 1
43/** The IOTLB entry magic. */
44#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46
47/*********************************************************************************************************************************
48* Structures and Typedefs *
49*********************************************************************************************************************************/
50/**
51 * Acquires the IOMMU PDM lock.
52 * This will make a long jump to ring-3 to acquire the lock if necessary.
53 */
54#define IOMMU_LOCK(a_pDevIns) \
55 do { \
56 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
57 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
58 { /* likely */ } \
59 else \
60 return rcLock; \
61 } while (0)
62
63/**
64 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
65 * This will make a long jump to ring-3 to acquire the lock if necessary.
66 */
67#define IOMMU_LOCK_NORET(a_pDevIns) \
68 do { \
69 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
70 AssertRC(rcLock); \
71 } while (0)
72
73/**
74 * Releases the IOMMU PDM lock.
75 */
76#define IOMMU_UNLOCK(a_pDevIns) \
77 do { \
78 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
79 } while (0)
80
81/**
82 * Asserts that the critsect is owned by this thread.
83 */
84#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
85 do { \
86 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
87 } while (0)
88
89/**
90 * Asserts that the critsect is not owned by this thread.
91 */
92#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
93 do { \
94 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95 } while (0)
96
97/**
98 * IOMMU operations (transaction) types.
99 */
100typedef enum IOMMUOP
101{
102 /** Address translation request. */
103 IOMMUOP_TRANSLATE_REQ = 0,
104 /** Memory read request. */
105 IOMMUOP_MEM_READ,
106 /** Memory write request. */
107 IOMMUOP_MEM_WRITE,
108 /** Interrupt request. */
109 IOMMUOP_INTR_REQ,
110 /** Command. */
111 IOMMUOP_CMD
112} IOMMUOP;
113AssertCompileSize(IOMMUOP, 4);
114
115/**
116 * I/O page walk result.
117 */
118typedef struct
119{
120 /** The translated system physical address. */
121 RTGCPHYS GCPhysSpa;
122 /** The number of offset bits in the system physical address. */
123 uint8_t cShift;
124 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
125 uint8_t fIoPerm;
126 /** Padding. */
127 uint8_t abPadding[2];
128} IOWALKRESULT;
129/** Pointer to an I/O walk result struct. */
130typedef IOWALKRESULT *PIOWALKRESULT;
131/** Pointer to a const I/O walk result struct. */
132typedef IOWALKRESULT *PCIOWALKRESULT;
133
134/**
135 * IOMMU I/O TLB Entry.
136 * Keep this as small and aligned as possible.
137 */
138typedef struct
139{
140 /** The translated system physical address (SPA) of the page. */
141 RTGCPHYS GCPhysSpa;
142 /** The index of the 4K page within a large page. */
143 uint32_t idxSubPage;
144 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
145 uint8_t fIoPerm;
146 /** The number of offset bits in the translation indicating page size. */
147 uint8_t cShift;
148 /** Alignment padding. */
149 uint8_t afPadding[2];
150} IOTLBE_T;
151AssertCompileSize(IOTLBE_T, 16);
152/** Pointer to an IOMMU I/O TLB entry struct. */
153typedef IOTLBE_T *PIOTLBE_T;
154/** Pointer to a const IOMMU I/O TLB entry struct. */
155typedef IOTLBE_T const *PCIOTLBE_T;
156
157/**
158 * The shared IOMMU device state.
159 */
160typedef struct IOMMU
161{
162 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
163 uint32_t idxIommu;
164 /** Alignment padding. */
165 uint32_t uPadding0;
166
167 /** Whether the command thread is sleeping. */
168 bool volatile fCmdThreadSleeping;
169 /** Alignment padding. */
170 uint8_t afPadding0[3];
171 /** Whether the command thread has been signaled for wake up. */
172 bool volatile fCmdThreadSignaled;
173 /** Alignment padding. */
174 uint8_t afPadding1[3];
175
176 /** The event semaphore the command thread waits on. */
177 SUPSEMEVENT hEvtCmdThread;
178 /** The MMIO handle. */
179 IOMMMIOHANDLE hMmio;
180
181 /** @name PCI: Base capability block registers.
182 * @{ */
183 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
184 /** @} */
185
186 /** @name MMIO: Control and status registers.
187 * @{ */
188 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
189 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
190 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
191 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
192 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
193 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
194 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
195 /** @} */
196
197 /** @name MMIO: PPR Log registers.
198 * @{ */
199 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
200 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
201 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
202 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
203 /** @} */
204
205 /** @todo IOMMU: SMI filter. */
206
207 /** @name MMIO: Guest Virtual-APIC Log registers.
208 * @{ */
209 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
210 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
211 /** @} */
212
213 /** @name MMIO: Alternate PPR and Event Log registers.
214 * @{ */
215 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
216 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
217 /** @} */
218
219 /** @name MMIO: Device-specific feature registers.
220 * @{ */
221 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
222 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
223 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
224 /** @} */
225
226 /** @name MMIO: MSI Capability Block registers.
227 * @{ */
228 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
229 /** @} */
230
231 /** @name MMIO: Performance Optimization Control registers.
232 * @{ */
233 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
234 /** @} */
235
236 /** @name MMIO: x2APIC Control registers.
237 * @{ */
238 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
239 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
240 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
241 /** @} */
242
243 /** @name MMIO: MARC registers.
244 * @{ */
245 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
246 /** @} */
247
248 /** @name MMIO: Reserved register.
249 * @{ */
250 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
251 /** @} */
252
253 /** @name MMIO: Command and Event Log pointer registers.
254 * @{ */
255 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
256 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
257 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
258 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
259 /** @} */
260
261 /** @name MMIO: Command and Event Status register.
262 * @{ */
263 IOMMU_STATUS_T Status; /**< IOMMU status register. */
264 /** @} */
265
266 /** @name MMIO: PPR Log Head and Tail pointer registers.
267 * @{ */
268 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
269 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
270 /** @} */
271
272 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
273 * @{ */
274 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
275 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
276 /** @} */
277
278 /** @name MMIO: PPR Log B Head and Tail pointer registers.
279 * @{ */
280 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
281 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
282 /** @} */
283
284 /** @name MMIO: Event Log B Head and Tail pointer registers.
285 * @{ */
286 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
287 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
288 /** @} */
289
290 /** @name MMIO: PPR Log Overflow protection registers.
291 * @{ */
292 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
293 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
294 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
295 /** @} */
296
297 /** @todo IOMMU: IOMMU Event counter registers. */
298
299#ifdef VBOX_WITH_STATISTICS
300 /** @name IOMMU: Stat counters.
301 * @{ */
302 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
303 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
304
305 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
306 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
307
308 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
309 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
310
311 STAMCOUNTER StatCmd; /**< Number of commands processed. */
312 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
313 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
314 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
315 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
316 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
317 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
318 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
319 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
320 /** @} */
321#endif
322} IOMMU;
323/** Pointer to the IOMMU device state. */
324typedef struct IOMMU *PIOMMU;
325/** Pointer to the const IOMMU device state. */
326typedef const struct IOMMU *PCIOMMU;
327AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
328AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
329AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
330AssertCompileMemberAlignment(IOMMU, hMmio, 8);
331AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
332
333/**
334 * The ring-3 IOMMU device state.
335 */
336typedef struct IOMMUR3
337{
338 /** Device instance. */
339 PPDMDEVINSR3 pDevInsR3;
340 /** The IOMMU helpers. */
341 PCPDMIOMMUHLPR3 pIommuHlpR3;
342 /** The command thread handle. */
343 R3PTRTYPE(PPDMTHREAD) pCmdThread;
344} IOMMUR3;
345/** Pointer to the ring-3 IOMMU device state. */
346typedef IOMMUR3 *PIOMMUR3;
347
348/**
349 * The ring-0 IOMMU device state.
350 */
351typedef struct IOMMUR0
352{
353 /** Device instance. */
354 PPDMDEVINSR0 pDevInsR0;
355 /** The IOMMU helpers. */
356 PCPDMIOMMUHLPR0 pIommuHlpR0;
357} IOMMUR0;
358/** Pointer to the ring-0 IOMMU device state. */
359typedef IOMMUR0 *PIOMMUR0;
360
361/**
362 * The raw-mode IOMMU device state.
363 */
364typedef struct IOMMURC
365{
366 /** Device instance. */
367 PPDMDEVINSR0 pDevInsRC;
368 /** The IOMMU helpers. */
369 PCPDMIOMMUHLPRC pIommuHlpRC;
370} IOMMURC;
371/** Pointer to the raw-mode IOMMU device state. */
372typedef IOMMURC *PIOMMURC;
373
374/** The IOMMU device state for the current context. */
375typedef CTX_SUFF(IOMMU) IOMMUCC;
376/** Pointer to the IOMMU device state for the current context. */
377typedef CTX_SUFF(PIOMMU) PIOMMUCC;
378
379/**
380 * IOMMU register access routines.
381 */
382typedef struct
383{
384 const char *pszName;
385 VBOXSTRICTRC (*pfnRead )(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t *pu64Value);
386 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value);
387 bool f64BitReg;
388} IOMMUREGACC;
389
390
391/*********************************************************************************************************************************
392* Global Variables *
393*********************************************************************************************************************************/
394/**
395 * An array of the number of device table segments supported.
396 * Indexed by u2DevTabSegSup.
397 */
398static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
399
400/**
401 * An array of the masks to select the device table segment index from a device ID.
402 */
403static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
404
405/**
406 * An array of the shift values to select the device table segment index from a
407 * device ID.
408 */
409static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
410
411/**
412 * The maximum size (inclusive) of each device table segment (0 to 7).
413 * Indexed by the device table segment index.
414 */
415static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
416
417
418#ifndef VBOX_DEVICE_STRUCT_TESTCASE
419/**
420 * Gets the maximum number of buffer entries for the given buffer length.
421 *
422 * @returns Number of buffer entries.
423 * @param uEncodedLen The length (power-of-2 encoded).
424 */
425DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
426{
427 Assert(uEncodedLen > 7);
428 return 2 << (uEncodedLen - 1);
429}
430
431
432/**
433 * Gets the total length of the buffer given a base register's encoded length.
434 *
435 * @returns The length of the buffer in bytes.
436 * @param uEncodedLen The length (power-of-2 encoded).
437 */
438DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
439{
440 Assert(uEncodedLen > 7);
441 return (2 << (uEncodedLen - 1)) << 4;
442}
443
444
445/**
446 * Gets the number of (unconsumed) entries in the event log.
447 *
448 * @returns The number of entries in the event log.
449 * @param pThis The IOMMU device state.
450 */
451static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
452{
453 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
454 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
455 if (idxTail >= idxHead)
456 return idxTail - idxHead;
457
458 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
459 return cMaxEvts - idxHead + idxTail;
460}
461
462
463/**
464 * Gets the number of (unconsumed) commands in the command buffer.
465 *
466 * @returns The number of commands in the command buffer.
467 * @param pThis The IOMMU device state.
468 */
469static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
470{
471 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
472 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
473 if (idxTail >= idxHead)
474 return idxTail - idxHead;
475
476 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
477 return cMaxCmds - idxHead + idxTail;
478}
479
480
481DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
482{
483 IOMMU_STATUS_T Status;
484 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
485 return Status;
486}
487
488
489DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
490{
491 IOMMU_CTRL_T Ctrl;
492 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
493 return Ctrl;
494}
495
496
497/**
498 * Returns whether MSI is enabled for the IOMMU.
499 *
500 * @returns Whether MSI is enabled.
501 * @param pDevIns The IOMMU device instance.
502 *
503 * @note There should be a PCIDevXxx function for this.
504 */
505static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
506{
507 MSI_CAP_HDR_T MsiCapHdr;
508 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
509 return MsiCapHdr.n.u1MsiEnable;
510}
511
512
513/**
514 * Signals a PCI target abort.
515 *
516 * @param pDevIns The IOMMU device instance.
517 */
518static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
519{
520 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
521 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
522 PDMPciDevSetStatus(pPciDev, u16Status);
523}
524
525
526/**
527 * Wakes up the command thread if there are commands to be processed or if
528 * processing is requested to be stopped by software.
529 *
530 * @param pDevIns The IOMMU device instance.
531 */
532static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
533{
534 IOMMU_ASSERT_LOCKED(pDevIns);
535 Log5Func(("\n"));
536
537 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
538 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
539 if (Status.n.u1CmdBufRunning)
540 {
541 Log5Func(("Signaling command thread\n"));
542 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
543 }
544}
545
546
547/**
548 * Writes to a read-only register.
549 */
550static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
551{
552 RT_NOREF(pDevIns, pThis, iReg, u64Value);
553 LogFunc(("Write to read-only register (%#x) with value %#RX64 ignored\n", iReg, u64Value));
554 return VINF_SUCCESS;
555}
556
557
558/**
559 * Writes the Device Table Base Address Register.
560 */
561static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
562{
563 RT_NOREF(pDevIns, iReg);
564
565 /* Mask out all unrecognized bits. */
566 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
567
568 /* Update the register. */
569 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
570 return VINF_SUCCESS;
571}
572
573
574/**
575 * Writes the Command Buffer Base Address Register.
576 */
577static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
578{
579 RT_NOREF(pDevIns, iReg);
580
581 /*
582 * While this is not explicitly specified like the event log base address register,
583 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
584 * Inconsistent specs :/
585 */
586 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
587 if (Status.n.u1CmdBufRunning)
588 {
589 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
590 return VINF_SUCCESS;
591 }
592
593 /* Mask out all unrecognized bits. */
594 CMD_BUF_BAR_T CmdBufBaseAddr;
595 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
596
597 /* Validate the length. */
598 if (CmdBufBaseAddr.n.u4Len >= 8)
599 {
600 /* Update the register. */
601 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
602
603 /*
604 * Writing the command buffer base address, clears the command buffer head and tail pointers.
605 * See AMD spec. 2.4 "Commands".
606 */
607 pThis->CmdBufHeadPtr.u64 = 0;
608 pThis->CmdBufTailPtr.u64 = 0;
609 }
610 else
611 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
612
613 return VINF_SUCCESS;
614}
615
616
617/**
618 * Writes the Event Log Base Address Register.
619 */
620static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
621{
622 RT_NOREF(pDevIns, iReg);
623
624 /*
625 * IOMMU behavior is undefined when software writes this register when event logging is running.
626 * In our emulation, we ignore the write entirely.
627 * See AMD IOMMU spec. "Event Log Base Address Register".
628 */
629 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
630 if (Status.n.u1EvtLogRunning)
631 {
632 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
633 return VINF_SUCCESS;
634 }
635
636 /* Mask out all unrecognized bits. */
637 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
638 EVT_LOG_BAR_T EvtLogBaseAddr;
639 EvtLogBaseAddr.u64 = u64Value;
640
641 /* Validate the length. */
642 if (EvtLogBaseAddr.n.u4Len >= 8)
643 {
644 /* Update the register. */
645 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
646
647 /*
648 * Writing the event log base address, clears the event log head and tail pointers.
649 * See AMD spec. 2.5 "Event Logging".
650 */
651 pThis->EvtLogHeadPtr.u64 = 0;
652 pThis->EvtLogTailPtr.u64 = 0;
653 }
654 else
655 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
656
657 return VINF_SUCCESS;
658}
659
660
661/**
662 * Writes the Control Register.
663 */
664static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
665{
666 RT_NOREF(pDevIns, iReg);
667
668 /* Mask out all unrecognized bits. */
669 u64Value &= IOMMU_CTRL_VALID_MASK;
670
671 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
672 IOMMU_CTRL_T NewCtrl;
673 NewCtrl.u64 = u64Value;
674
675 /* Update the register. */
676 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
677
678 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
679 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
680
681 /* Enable or disable event logging when the bit transitions. */
682 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
683 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
684 if ( fOldEvtLogEn != fNewEvtLogEn
685 || fOldIommuEn != fNewIommuEn)
686 {
687 if ( fNewIommuEn
688 && fNewEvtLogEn)
689 {
690 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
691 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
692 }
693 else
694 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
695 }
696
697 /* Enable or disable command buffer processing when the bit transitions. */
698 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
699 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
700 if ( fOldCmdBufEn != fNewCmdBufEn
701 || fOldIommuEn != fNewIommuEn)
702 {
703 if ( fNewCmdBufEn
704 && fNewIommuEn)
705 {
706 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
707 LogFunc(("Command buffer enabled\n"));
708
709 /* Wake up the command thread to start processing commands. */
710 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
711 }
712 else
713 {
714 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
715 LogFunc(("Command buffer disabled\n"));
716 }
717 }
718
719 return VINF_SUCCESS;
720}
721
722
723/**
724 * Writes to the Excluse Range Base Address Register.
725 */
726static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
727{
728 RT_NOREF(pDevIns, iReg);
729 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
730 return VINF_SUCCESS;
731}
732
733
734/**
735 * Writes to the Excluse Range Limit Register.
736 */
737static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
738{
739 RT_NOREF(pDevIns, iReg);
740 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
741 u64Value |= UINT64_C(0xfff);
742 pThis->ExclRangeLimit.u64 = u64Value;
743 return VINF_SUCCESS;
744}
745
746
747/**
748 * Writes the Hardware Event Register (Hi).
749 */
750static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
751{
752 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
753 RT_NOREF(pDevIns, iReg);
754 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
755 pThis->HwEvtHi.u64 = u64Value;
756 return VINF_SUCCESS;
757}
758
759
760/**
761 * Writes the Hardware Event Register (Lo).
762 */
763static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
764{
765 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
766 RT_NOREF(pDevIns, iReg);
767 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
768 pThis->HwEvtLo = u64Value;
769 return VINF_SUCCESS;
770}
771
772
773/**
774 * Writes the Hardware Event Status Register.
775 */
776static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
777{
778 RT_NOREF(pDevIns, iReg);
779
780 /* Mask out all unrecognized bits. */
781 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
782
783 /*
784 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
785 * If the current status bits or the bits being written are both 0, we've nothing to do.
786 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
787 */
788 uint64_t HwStatus = pThis->HwEvtStatus.u64;
789 if (!(HwStatus & RT_BIT(0)))
790 return VINF_SUCCESS;
791 if (u64Value & HwStatus & RT_BIT_64(0))
792 HwStatus &= ~RT_BIT_64(0);
793 if (u64Value & HwStatus & RT_BIT_64(1))
794 HwStatus &= ~RT_BIT_64(1);
795
796 /* Update the register. */
797 pThis->HwEvtStatus.u64 = HwStatus;
798 return VINF_SUCCESS;
799}
800
801
802/**
803 * Writes the Device Table Segment Base Address Register.
804 */
805static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
806{
807 RT_NOREF(pDevIns);
808
809 /* Figure out which segment is being written. */
810 uint8_t const offSegment = (iReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
811 uint8_t const idxSegment = offSegment + 1;
812 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
813
814 /* Mask out all unrecognized bits. */
815 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
816 DEV_TAB_BAR_T DevTabSegBar;
817 DevTabSegBar.u64 = u64Value;
818
819 /* Validate the size. */
820 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
821 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
822 if (uSegSize <= uMaxSegSize)
823 {
824 /* Update the register. */
825 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
826 }
827 else
828 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
829
830 return VINF_SUCCESS;
831}
832
833
834/**
835 * Writes the MSI Capability Header Register.
836 */
837static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
838{
839 RT_NOREF(pThis, iReg);
840 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
841 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
842 MSI_CAP_HDR_T MsiCapHdr;
843 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
844 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
845 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
846 return VINF_SUCCESS;
847}
848
849
850/**
851 * Writes the MSI Address (Lo) Register (32-bit).
852 */
853static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
854{
855 RT_NOREF(pThis, iReg);
856 Assert(!RT_HI_U32(u64Value));
857 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
858 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
859 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
860 return VINF_SUCCESS;
861}
862
863
864/**
865 * Writes the MSI Address (Hi) Register (32-bit).
866 */
867static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
868{
869 RT_NOREF(pThis, iReg);
870 Assert(!RT_HI_U32(u64Value));
871 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
872 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
873 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
874 return VINF_SUCCESS;
875}
876
877
878/**
879 * Writes the MSI Data Register (32-bit).
880 */
881static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
882{
883 RT_NOREF(pThis, iReg);
884 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
885 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
886 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
887 return VINF_SUCCESS;
888}
889
890
891/**
892 * Writes the Command Buffer Head Pointer Register (32-bit).
893 */
894static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
895{
896 RT_NOREF(pDevIns, iReg);
897
898 /*
899 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
900 * In our emulation, we ignore the write entirely.
901 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
902 */
903 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
904 if (Status.n.u1CmdBufRunning)
905 {
906 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
907 return VINF_SUCCESS;
908 }
909
910 /*
911 * IOMMU behavior is undefined when software writes a value outside the buffer length.
912 * In our emulation, we ignore the write entirely.
913 */
914 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
915 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
916 Assert(cbBuf <= _512K);
917 if (offBuf >= cbBuf)
918 {
919 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
920 return VINF_SUCCESS;
921 }
922
923 /* Update the register. */
924 pThis->CmdBufHeadPtr.au32[0] = offBuf;
925
926 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
927
928 LogFlowFunc(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
929 return VINF_SUCCESS;
930}
931
932
933/**
934 * Writes the Command Buffer Tail Pointer Register (32-bit).
935 */
936static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
937{
938 RT_NOREF(pDevIns, iReg);
939
940 /*
941 * IOMMU behavior is undefined when software writes a value outside the buffer length.
942 * In our emulation, we ignore the write entirely.
943 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
944 */
945 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
946 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
947 Assert(cbBuf <= _512K);
948 if (offBuf >= cbBuf)
949 {
950 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
951 return VINF_SUCCESS;
952 }
953
954 /*
955 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
956 * head pointer after adding one or more commands to the buffer.
957 *
958 * However, we cannot enforce this strictly because it's legal for software to shrink the
959 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
960 * at 0). Software might even make the queue empty by making head and tail equal which is
961 * allowed. I don't think we can or should try too hard to prevent software shooting itself
962 * in the foot here. As long as we make sure the offset value is within the circular buffer
963 * bounds (which we do by masking bits above) it should be sufficient.
964 */
965 pThis->CmdBufTailPtr.au32[0] = offBuf;
966
967 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
968
969 LogFlowFunc(("Set CmdBufTailPtr to %#RX32\n", offBuf));
970 return VINF_SUCCESS;
971}
972
973
974/**
975 * Writes the Event Log Head Pointer Register (32-bit).
976 */
977static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
978{
979 RT_NOREF(pDevIns, iReg);
980
981 /*
982 * IOMMU behavior is undefined when software writes a value outside the buffer length.
983 * In our emulation, we ignore the write entirely.
984 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
985 */
986 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
987 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
988 Assert(cbBuf <= _512K);
989 if (offBuf >= cbBuf)
990 {
991 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
992 return VINF_SUCCESS;
993 }
994
995 /* Update the register. */
996 pThis->EvtLogHeadPtr.au32[0] = offBuf;
997
998 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
999 return VINF_SUCCESS;
1000}
1001
1002
1003/**
1004 * Writes the Event Log Tail Pointer Register (32-bit).
1005 */
1006static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
1007{
1008 RT_NOREF(pDevIns, iReg);
1009 NOREF(pThis);
1010
1011 /*
1012 * IOMMU behavior is undefined when software writes this register when the event log is running.
1013 * In our emulation, we ignore the write entirely.
1014 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1015 */
1016 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1017 if (Status.n.u1EvtLogRunning)
1018 {
1019 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1020 return VINF_SUCCESS;
1021 }
1022
1023 /*
1024 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1025 * In our emulation, we ignore the write entirely.
1026 */
1027 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1028 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1029 Assert(cbBuf <= _512K);
1030 if (offBuf >= cbBuf)
1031 {
1032 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1033 return VINF_SUCCESS;
1034 }
1035
1036 /* Update the register. */
1037 pThis->EvtLogTailPtr.au32[0] = offBuf;
1038
1039 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1040 return VINF_SUCCESS;
1041}
1042
1043
1044/**
1045 * Writes the Status Register (64-bit).
1046 */
1047static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t iReg, uint64_t u64Value)
1048{
1049 RT_NOREF(pDevIns, iReg);
1050
1051 /* Mask out all unrecognized bits. */
1052 u64Value &= IOMMU_STATUS_VALID_MASK;
1053
1054 /*
1055 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1056 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1057 */
1058 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1059 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1060 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1061 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1062
1063 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1064
1065 /* Update the register. */
1066 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1067 return VINF_SUCCESS;
1068}
1069
1070
1071#if 0
1072/**
1073 * Table 0: Registers-access table.
1074 */
1075static const IOMMUREGACC g_aTable0Regs[] =
1076{
1077
1078};
1079
1080/**
1081 * Table 1: Registers-access table.
1082 */
1083static const IOMMUREGACC g_aTable1Regs[] =
1084{
1085};
1086#endif
1087
1088
1089/**
1090 * Writes an IOMMU register (32-bit and 64-bit).
1091 *
1092 * @returns Strict VBox status code.
1093 * @param pDevIns The IOMMU device instance.
1094 * @param off MMIO byte offset to the register.
1095 * @param cb The size of the write access.
1096 * @param uValue The value being written.
1097 *
1098 * @thread EMT.
1099 */
1100static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1101{
1102 Assert(off < IOMMU_MMIO_REGION_SIZE);
1103 Assert(cb == 4 || cb == 8);
1104 Assert(!(off & (cb - 1)));
1105
1106 LogFlowFunc(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1107
1108 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1109 switch (off)
1110 {
1111 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1112 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1113 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1114 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1115 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1116 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1117 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1118
1119 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1120 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1121 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1122 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1123
1124 case IOMMU_MMIO_OFF_GALOG_BAR:
1125 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1126
1127 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1128 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1129
1130 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1131 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1132 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1133 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1134 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1135 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1136 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1137
1138 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1139 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1140 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1141
1142 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1143 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1144 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1145 {
1146 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1147 if (cb == 4 || RT_FAILURE(rcStrict))
1148 return rcStrict;
1149 uValue >>= 32;
1150 RT_FALL_THRU();
1151 }
1152 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1153 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1154 {
1155 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1156 if (cb == 4 || RT_FAILURE(rcStrict))
1157 return rcStrict;
1158 uValue >>= 32;
1159 RT_FALL_THRU();
1160 }
1161 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1162 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1163
1164 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1165
1166 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1167 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1168 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1169
1170 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1171 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1172 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1173 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1174 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1175 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1176 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1177 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1178 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1179 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1180 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1181 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1182
1183 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1184
1185 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1186 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1187 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1188 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1189
1190 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1191
1192 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1193 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1194
1195 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1196 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1197
1198 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1199 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1200
1201 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1202 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1203
1204 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1205 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1206 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1207
1208 /* Not implemented. */
1209 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1210 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1211 {
1212 LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1213 return VINF_SUCCESS;
1214 }
1215
1216 /* Unknown. */
1217 default:
1218 {
1219 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1220 return VINF_SUCCESS;
1221 }
1222 }
1223}
1224
1225
1226/**
1227 * Reads an IOMMU register (64-bit) given its MMIO offset.
1228 *
1229 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1230 * boundary include the lower half of the subsequent register.
1231 *
1232 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1233 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1234 * software will only perform 32-bit reads on those 32-bit registers that are
1235 * aligned on 8-byte boundaries.
1236 *
1237 * @returns Strict VBox status code.
1238 * @param pDevIns The IOMMU device instance.
1239 * @param off The MMIO offset of the register in bytes.
1240 * @param puResult Where to store the value being read.
1241 *
1242 * @thread EMT.
1243 */
1244static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1245{
1246 Assert(off < IOMMU_MMIO_REGION_SIZE);
1247 Assert(!(off & 7) || !(off & 3));
1248
1249 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1250 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1251 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1252
1253 LogFlowFunc(("off=%#x\n", off));
1254
1255 /** @todo IOMMU: fine-grained locking? */
1256 uint64_t uReg;
1257 switch (off)
1258 {
1259 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1260 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1261 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1262 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1263 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1264 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1265 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1266
1267 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1268 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1269 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1270 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1271
1272 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1273 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1274
1275 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1276 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1277
1278 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1279 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1280 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1281 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1282 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1283 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1284 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1285 {
1286 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1287 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1288 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1289 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1290 break;
1291 }
1292
1293 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1294 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1295 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1296
1297 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1298 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1299 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1300 {
1301 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1302 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1303 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1304 break;
1305 }
1306 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1307 {
1308 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1309 break;
1310 }
1311 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1312 {
1313 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1314 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1315 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1316 break;
1317 }
1318 case IOMMU_MMIO_OFF_MSI_DATA:
1319 {
1320 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1321 break;
1322 }
1323 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1324 {
1325 /*
1326 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1327 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1328 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1329 * 0 for this register.
1330 */
1331 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1332 break;
1333 }
1334
1335 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1336
1337 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1338 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1339 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1340
1341 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1342 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1343 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1344 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1345 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1346 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1347 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1348 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1349 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1350 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1351 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1352 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1353
1354 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1355
1356 case IOMMU_MMIO_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1357 case IOMMU_MMIO_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1358 case IOMMU_MMIO_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1359 case IOMMU_MMIO_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1360
1361 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
1362
1363 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
1364 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
1365
1366 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
1367 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
1368
1369 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
1370 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
1371
1372 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
1373 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
1374
1375 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
1376 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
1377 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
1378
1379 /* Not implemented. */
1380 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1381 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1382 {
1383 LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1384 uReg = 0;
1385 break;
1386 }
1387
1388 /* Unknown. */
1389 default:
1390 {
1391 LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
1392 uReg = 0;
1393 return VINF_IOM_MMIO_UNUSED_00;
1394 }
1395 }
1396
1397 *puResult = uReg;
1398 return VINF_SUCCESS;
1399}
1400
1401
1402/**
1403 * Raises the MSI interrupt for the IOMMU device.
1404 *
1405 * @param pDevIns The IOMMU device instance.
1406 *
1407 * @thread Any.
1408 * @remarks The IOMMU lock may or may not be held.
1409 */
1410static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
1411{
1412 if (iommuAmdIsMsiEnabled(pDevIns))
1413 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
1414}
1415
1416
1417/**
1418 * Clears the MSI interrupt for the IOMMU device.
1419 *
1420 * @param pDevIns The IOMMU device instance.
1421 *
1422 * @thread Any.
1423 * @remarks The IOMMU lock may or may not be held.
1424 */
1425static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
1426{
1427 if (iommuAmdIsMsiEnabled(pDevIns))
1428 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
1429}
1430
1431
1432/**
1433 * Writes an entry to the event log in memory.
1434 *
1435 * @returns VBox status code.
1436 * @param pDevIns The IOMMU device instance.
1437 * @param pEvent The event to log.
1438 *
1439 * @thread Any.
1440 */
1441static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1442{
1443 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1444
1445 IOMMU_ASSERT_LOCKED(pDevIns);
1446
1447 /* Check if event logging is active and the log has not overflowed. */
1448 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1449 if ( Status.n.u1EvtLogRunning
1450 && !Status.n.u1EvtOverflow)
1451 {
1452 uint32_t const cbEvt = sizeof(*pEvent);
1453
1454 /* Get the offset we need to write the event to in memory (circular buffer offset). */
1455 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
1456 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
1457
1458 /* Ensure we have space in the event log. */
1459 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
1460 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
1461 if (cEvts + 1 < cMaxEvts)
1462 {
1463 /* Write the event log entry to memory. */
1464 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
1465 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
1466 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
1467 if (RT_FAILURE(rc))
1468 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
1469
1470 /* Increment the event log tail pointer. */
1471 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1472 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
1473
1474 /* Indicate that an event log entry was written. */
1475 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
1476
1477 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
1478 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1479 if (Ctrl.n.u1EvtIntrEn)
1480 iommuAmdRaiseMsiInterrupt(pDevIns);
1481 }
1482 else
1483 {
1484 /* Indicate that the event log has overflowed. */
1485 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
1486
1487 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
1488 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1489 if (Ctrl.n.u1EvtIntrEn)
1490 iommuAmdRaiseMsiInterrupt(pDevIns);
1491 }
1492 }
1493
1494 return VINF_SUCCESS;
1495}
1496
1497
1498/**
1499 * Sets an event in the hardware error registers.
1500 *
1501 * @param pDevIns The IOMMU device instance.
1502 * @param pEvent The event.
1503 *
1504 * @thread Any.
1505 */
1506static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1507{
1508 IOMMU_ASSERT_LOCKED(pDevIns);
1509
1510 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1511 if (pThis->ExtFeat.n.u1HwErrorSup)
1512 {
1513 if (pThis->HwEvtStatus.n.u1Valid)
1514 pThis->HwEvtStatus.n.u1Overflow = 1;
1515 pThis->HwEvtStatus.n.u1Valid = 1;
1516 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
1517 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
1518 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
1519 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
1520 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
1521 }
1522}
1523
1524
1525/**
1526 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
1527 *
1528 * @param uDevId The device ID.
1529 * @param uDomainId The domain ID.
1530 * @param GCPhysPtEntity The system physical address of the page table
1531 * entity.
1532 * @param enmOp The IOMMU operation being performed.
1533 * @param pEvtPageTabHwErr Where to store the initialized event.
1534 */
1535static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
1536 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1537{
1538 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
1539 pEvtPageTabHwErr->n.u16DevId = uDevId;
1540 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
1541 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
1542 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1543 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1544 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1545 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1546 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
1547 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
1548}
1549
1550
1551/**
1552 * Raises a PAGE_TAB_HARDWARE_ERROR event.
1553 *
1554 * @param pDevIns The IOMMU device instance.
1555 * @param enmOp The IOMMU operation being performed.
1556 * @param pEvtPageTabHwErr The page table hardware error event.
1557 *
1558 * @thread Any.
1559 */
1560static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1561{
1562 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
1563 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
1564
1565 IOMMU_LOCK_NORET(pDevIns);
1566
1567 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1568 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1569 if (enmOp != IOMMUOP_CMD)
1570 iommuAmdSetPciTargetAbort(pDevIns);
1571
1572 IOMMU_UNLOCK(pDevIns);
1573
1574 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
1575 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
1576 pEvtPageTabHwErr->n.u2Type));
1577}
1578
1579
1580/**
1581 * Initializes a COMMAND_HARDWARE_ERROR event.
1582 *
1583 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
1584 * @param pEvtCmdHwErr Where to store the initialized event.
1585 */
1586static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1587{
1588 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
1589 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
1590 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
1591 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
1592}
1593
1594
1595/**
1596 * Raises a COMMAND_HARDWARE_ERROR event.
1597 *
1598 * @param pDevIns The IOMMU device instance.
1599 * @param pEvtCmdHwErr The command hardware error event.
1600 *
1601 * @thread Any.
1602 */
1603static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1604{
1605 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
1606 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
1607 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1608
1609 IOMMU_LOCK_NORET(pDevIns);
1610
1611 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1612 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1613 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1614
1615 IOMMU_UNLOCK(pDevIns);
1616
1617 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
1618}
1619
1620
1621/**
1622 * Initializes a DEV_TAB_HARDWARE_ERROR event.
1623 *
1624 * @param uDevId The device ID.
1625 * @param GCPhysDte The system physical address of the failed device table
1626 * access.
1627 * @param enmOp The IOMMU operation being performed.
1628 * @param pEvtDevTabHwErr Where to store the initialized event.
1629 */
1630static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
1631 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1632{
1633 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
1634 pEvtDevTabHwErr->n.u16DevId = uDevId;
1635 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1636 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
1637 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1638 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1639 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1640 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
1641 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
1642}
1643
1644
1645/**
1646 * Raises a DEV_TAB_HARDWARE_ERROR event.
1647 *
1648 * @param pDevIns The IOMMU device instance.
1649 * @param enmOp The IOMMU operation being performed.
1650 * @param pEvtDevTabHwErr The device table hardware error event.
1651 *
1652 * @thread Any.
1653 */
1654static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1655{
1656 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
1657 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
1658
1659 IOMMU_LOCK_NORET(pDevIns);
1660
1661 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1662 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1663 if (enmOp != IOMMUOP_CMD)
1664 iommuAmdSetPciTargetAbort(pDevIns);
1665
1666 IOMMU_UNLOCK(pDevIns);
1667
1668 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
1669 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
1670}
1671
1672
1673/**
1674 * Initializes an ILLEGAL_COMMAND_ERROR event.
1675 *
1676 * @param GCPhysCmd The system physical address of the failed command
1677 * access.
1678 * @param pEvtIllegalCmd Where to store the initialized event.
1679 */
1680static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
1681{
1682 Assert(!(GCPhysCmd & UINT64_C(0xf)));
1683 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
1684 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
1685 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
1686}
1687
1688
1689/**
1690 * Raises an ILLEGAL_COMMAND_ERROR event.
1691 *
1692 * @param pDevIns The IOMMU device instance.
1693 * @param pEvtIllegalCmd The illegal command error event.
1694 */
1695static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
1696{
1697 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
1698 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
1699 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1700
1701 IOMMU_LOCK_NORET(pDevIns);
1702
1703 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1704 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1705
1706 IOMMU_UNLOCK(pDevIns);
1707
1708 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
1709}
1710
1711
1712/**
1713 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
1714 *
1715 * @param uDevId The device ID.
1716 * @param uIova The I/O virtual address.
1717 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
1718 * event was caused by an invalid level encoding in the
1719 * DTE.
1720 * @param enmOp The IOMMU operation being performed.
1721 * @param pEvtIllegalDte Where to store the initialized event.
1722 */
1723static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
1724 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
1725{
1726 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
1727 pEvtIllegalDte->n.u16DevId = uDevId;
1728 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1729 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1730 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
1731 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1732 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
1733 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
1734 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
1735 * IOMMU spec here but not for this field for I/O page fault event. */
1736 Assert(!(uIova & UINT64_C(0x3)));
1737}
1738
1739
1740/**
1741 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
1742 *
1743 * @param pDevIns The IOMMU instance data.
1744 * @param enmOp The IOMMU operation being performed.
1745 * @param pEvtIllegalDte The illegal device table entry event.
1746 * @param enmEvtType The illegal device table entry event type.
1747 *
1748 * @thread Any.
1749 */
1750static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
1751 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
1752{
1753 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
1754 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
1755
1756 IOMMU_LOCK_NORET(pDevIns);
1757
1758 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1759 if (enmOp != IOMMUOP_CMD)
1760 iommuAmdSetPciTargetAbort(pDevIns);
1761
1762 IOMMU_UNLOCK(pDevIns);
1763
1764 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
1765 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
1766 NOREF(enmEvtType);
1767}
1768
1769
1770/**
1771 * Initializes an IO_PAGE_FAULT event.
1772 *
1773 * @param uDevId The device ID.
1774 * @param uDomainId The domain ID.
1775 * @param uIova The I/O virtual address being accessed.
1776 * @param fPresent Transaction to a page marked as present (including
1777 * DTE.V=1) or interrupt marked as remapped
1778 * (IRTE.RemapEn=1).
1779 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
1780 * the I/O page fault was caused by invalid level
1781 * encoding.
1782 * @param fPermDenied Permission denied for the address being accessed.
1783 * @param enmOp The IOMMU operation being performed.
1784 * @param pEvtIoPageFault Where to store the initialized event.
1785 */
1786static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
1787 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
1788{
1789 Assert(!fPermDenied || fPresent);
1790 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
1791 pEvtIoPageFault->n.u16DevId = uDevId;
1792 //pEvtIoPageFault->n.u4PasidHi = 0;
1793 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
1794 //pEvtIoPageFault->n.u1GuestOrNested = 0;
1795 //pEvtIoPageFault->n.u1NoExecute = 0;
1796 //pEvtIoPageFault->n.u1User = 0;
1797 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1798 pEvtIoPageFault->n.u1Present = fPresent;
1799 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1800 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
1801 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
1802 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1803 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
1804 pEvtIoPageFault->n.u64Addr = uIova;
1805}
1806
1807
1808/**
1809 * Raises an IO_PAGE_FAULT event.
1810 *
1811 * @param pDevIns The IOMMU instance data.
1812 * @param pDte The device table entry. Optional, can be NULL
1813 * depending on @a enmOp.
1814 * @param pIrte The interrupt remapping table entry. Optional, can
1815 * be NULL depending on @a enmOp.
1816 * @param enmOp The IOMMU operation being performed.
1817 * @param pEvtIoPageFault The I/O page fault event.
1818 * @param enmEvtType The I/O page fault event type.
1819 *
1820 * @thread Any.
1821 */
1822static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
1823 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
1824{
1825 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
1826 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
1827
1828 IOMMU_LOCK_NORET(pDevIns);
1829
1830 bool fSuppressEvtLogging = false;
1831 if ( enmOp == IOMMUOP_MEM_READ
1832 || enmOp == IOMMUOP_MEM_WRITE)
1833 {
1834 if ( pDte
1835 && pDte->n.u1Valid)
1836 {
1837 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
1838 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
1839 * suppression. Perhaps will be possible when we complete IOTLB/cache
1840 * handling. */
1841 }
1842 }
1843 else if (enmOp == IOMMUOP_INTR_REQ)
1844 {
1845 if ( pDte
1846 && pDte->n.u1IntrMapValid)
1847 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
1848
1849 if ( !fSuppressEvtLogging
1850 && pIrte)
1851 fSuppressEvtLogging = pIrte->n.u1SuppressPf;
1852 }
1853 /* else: Events are never suppressed for commands. */
1854
1855 switch (enmEvtType)
1856 {
1857 case kIoPageFaultType_PermDenied:
1858 {
1859 /* Cannot be triggered by a command. */
1860 Assert(enmOp != IOMMUOP_CMD);
1861 RT_FALL_THRU();
1862 }
1863 case kIoPageFaultType_DteRsvdPagingMode:
1864 case kIoPageFaultType_PteInvalidPageSize:
1865 case kIoPageFaultType_PteInvalidLvlEncoding:
1866 case kIoPageFaultType_SkippedLevelIovaNotZero:
1867 case kIoPageFaultType_PteRsvdNotZero:
1868 case kIoPageFaultType_PteValidNotSet:
1869 case kIoPageFaultType_DteTranslationDisabled:
1870 case kIoPageFaultType_PasidInvalidRange:
1871 {
1872 /*
1873 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
1874 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
1875 */
1876 if (enmOp != IOMMUOP_TRANSLATE_REQ)
1877 {
1878 if (!fSuppressEvtLogging)
1879 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1880 if (enmOp != IOMMUOP_CMD)
1881 iommuAmdSetPciTargetAbort(pDevIns);
1882 }
1883 break;
1884 }
1885
1886 case kIoPageFaultType_UserSupervisor:
1887 {
1888 /* Access is blocked and only creates an event log entry. */
1889 if (!fSuppressEvtLogging)
1890 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1891 break;
1892 }
1893
1894 case kIoPageFaultType_IrteAddrInvalid:
1895 case kIoPageFaultType_IrteRsvdNotZero:
1896 case kIoPageFaultType_IrteRemapEn:
1897 case kIoPageFaultType_IrteRsvdIntType:
1898 case kIoPageFaultType_IntrReqAborted:
1899 case kIoPageFaultType_IntrWithPasid:
1900 {
1901 /* Only trigerred by interrupt requests. */
1902 Assert(enmOp == IOMMUOP_INTR_REQ);
1903 if (!fSuppressEvtLogging)
1904 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1905 iommuAmdSetPciTargetAbort(pDevIns);
1906 break;
1907 }
1908
1909 case kIoPageFaultType_SmiFilterMismatch:
1910 {
1911 /* Not supported and probably will never be, assert. */
1912 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
1913 break;
1914 }
1915
1916 case kIoPageFaultType_DevId_Invalid:
1917 {
1918 /* Cannot be triggered by a command. */
1919 Assert(enmOp != IOMMUOP_CMD);
1920 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
1921 if (!fSuppressEvtLogging)
1922 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
1923 if ( enmOp == IOMMUOP_MEM_READ
1924 || enmOp == IOMMUOP_MEM_WRITE)
1925 iommuAmdSetPciTargetAbort(pDevIns);
1926 break;
1927 }
1928 }
1929
1930 IOMMU_UNLOCK(pDevIns);
1931}
1932
1933
1934/**
1935 * Returns whether the I/O virtual address is to be excluded from translation and
1936 * permission checks.
1937 *
1938 * @returns @c true if the DVA is excluded, @c false otherwise.
1939 * @param pThis The IOMMU device state.
1940 * @param pDte The device table entry.
1941 * @param uIova The I/O virtual address.
1942 *
1943 * @remarks Ensure the exclusion range is enabled prior to calling this function.
1944 *
1945 * @thread Any.
1946 */
1947static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
1948{
1949 /* Ensure the exclusion range is enabled. */
1950 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
1951
1952 /* Check if the IOVA falls within the exclusion range. */
1953 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
1954 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
1955 if (uIovaExclLast - uIova >= uIovaExclFirst)
1956 {
1957 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
1958 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
1959 || pDte->n.u1AllowExclusion)
1960 return true;
1961 }
1962 return false;
1963}
1964
1965
1966/**
1967 * Reads a device table entry from guest memory given the device ID.
1968 *
1969 * @returns VBox status code.
1970 * @param pDevIns The IOMMU device instance.
1971 * @param uDevId The device ID.
1972 * @param enmOp The IOMMU operation being performed.
1973 * @param pDte Where to store the device table entry.
1974 *
1975 * @thread Any.
1976 */
1977static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
1978{
1979 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1980 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1981
1982 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
1983 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
1984 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
1985
1986 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
1987 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1988
1989 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
1990 uint16_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
1991 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
1992
1993 LogFlowFunc(("idxSegsEn=%#x GCPhysDevTab=%#RGp offDte=%#x GCPhysDte=%#RGp\n", idxSegsEn, GCPhysDevTab, offDte, GCPhysDte));
1994
1995 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
1996 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
1997 if (RT_FAILURE(rc))
1998 {
1999 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2000
2001 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2002 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2003 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2004 return VERR_IOMMU_IPE_1;
2005 }
2006
2007
2008 return rc;
2009}
2010
2011
2012/**
2013 * Walks the I/O page table to translate the I/O virtual address to a system
2014 * physical address.
2015 *
2016 * @returns VBox status code.
2017 * @param pDevIns The IOMMU device instance.
2018 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2019 * @param uDevId The device ID.
2020 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2021 * permissions for the access being made.
2022 * @param pDte The device table entry.
2023 * @param enmOp The IOMMU operation being performed.
2024 * @param pWalkResult Where to store the results of the I/O page walk. This is
2025 * only updated when VINF_SUCCESS is returned.
2026 *
2027 * @thread Any.
2028 */
2029static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2030 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2031{
2032 Assert(pDte->n.u1Valid);
2033 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2034
2035 /* If the translation is not valid, raise an I/O page fault. */
2036 if (pDte->n.u1TranslationValid)
2037 { /* likely */ }
2038 else
2039 {
2040 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2041 * doesn't explicitly say whether an I/O page fault is raised. From other
2042 * places in the spec. it seems early page walk terminations (starting with
2043 * the DTE) return the state computed so far and raises an I/O page fault. So
2044 * returning an invalid translation rather than skipping translation. */
2045 LogFunc(("Translation valid bit not set -> IOPF"));
2046 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2047 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2048 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2049 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2050 kIoPageFaultType_DteTranslationDisabled);
2051 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2052 }
2053
2054 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2055 uint8_t const uMaxLevel = pDte->n.u3Mode;
2056 if (uMaxLevel != 0)
2057 { /* likely */ }
2058 else
2059 {
2060 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2061 if ((fAccess & fDtePerm) != fAccess)
2062 {
2063 LogFunc(("Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
2064 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2065 }
2066 pWalkResult->GCPhysSpa = uIova;
2067 pWalkResult->cShift = 0;
2068 pWalkResult->fIoPerm = fDtePerm;
2069 return VINF_SUCCESS;
2070 }
2071
2072 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2073 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2074 { /* likely */ }
2075 else
2076 {
2077 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2078 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2079 * I'm just going with I/O page fault. */
2080 LogFunc(("Invalid root page table level %#x -> IOPF\n", uMaxLevel));
2081 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2082 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2083 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2084 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2085 kIoPageFaultType_PteInvalidLvlEncoding);
2086 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2087 }
2088
2089 /* Check permissions bits of the root page table. */
2090 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2091 if ((fAccess & fRootPtePerm) == fAccess)
2092 { /* likely */ }
2093 else
2094 {
2095 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2096 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2097 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2098 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2099 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2100 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2101 }
2102
2103 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2104 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2105 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2106 * table entry every time. Not sure if it's worth optimizing that case now
2107 * or if at all. */
2108
2109 /* The virtual address bits indexing table. */
2110 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2111 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2112 UINT64_C(0x00000000001ff000),
2113 UINT64_C(0x000000003fe00000),
2114 UINT64_C(0x0000007fc0000000),
2115 UINT64_C(0x0000ff8000000000),
2116 UINT64_C(0x01ff000000000000),
2117 UINT64_C(0xfe00000000000000),
2118 UINT64_C(0x0000000000000000) };
2119 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2120 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2121
2122 /* Traverse the I/O page table starting with the page directory in the DTE. */
2123 IOPTENTITY_T PtEntity;
2124 PtEntity.u64 = pDte->au64[0];
2125 for (;;)
2126 {
2127 /* Figure out the system physical address of the page table at the current level. */
2128 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2129
2130 /* Read the page table entity at the current level. */
2131 {
2132 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2133 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2134 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2135 uint64_t const offPte = idxPte << 3;
2136 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2137 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2138 if (RT_FAILURE(rc))
2139 {
2140 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2141 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2142 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2143 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2144 return VERR_IOMMU_IPE_2;
2145 }
2146 }
2147
2148 /* Check present bit. */
2149 if (PtEntity.n.u1Present)
2150 { /* likely */ }
2151 else
2152 {
2153 LogFunc(("Page table entry not present -> IOPF"));
2154 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2155 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2156 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2157 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2158 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2159 }
2160
2161 /* Check permission bits. */
2162 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2163 if ((fAccess & fPtePerm) == fAccess)
2164 { /* likely */ }
2165 else
2166 {
2167 LogFunc(("Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF\n", fAccess, fPtePerm));
2168 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2169 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2170 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2171 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2172 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2173 }
2174
2175 /* If this is a PTE, we're at the final level and we're done. */
2176 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2177 if (uNextLevel == 0)
2178 {
2179 /* The page size of the translation is the default (4K). */
2180 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2181 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2182 pWalkResult->fIoPerm = fPtePerm;
2183 return VINF_SUCCESS;
2184 }
2185 if (uNextLevel == 7)
2186 {
2187 /* The default page size of the translation is overridden. */
2188 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2189 uint8_t cShift = X86_PAGE_4K_SHIFT;
2190 while (GCPhysPte & RT_BIT_64(cShift++))
2191 ;
2192
2193 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2194 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2195 if ( cShift > s_acIovaLevelShifts[uLevel]
2196 && cShift < s_acIovaLevelShifts[uLevel + 1])
2197 {
2198 pWalkResult->GCPhysSpa = GCPhysPte;
2199 pWalkResult->cShift = cShift;
2200 pWalkResult->fIoPerm = fPtePerm;
2201 return VINF_SUCCESS;
2202 }
2203
2204 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2205 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2206 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2207 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2208 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2209 kIoPageFaultType_PteInvalidPageSize);
2210 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2211 }
2212
2213 /* Validate the next level encoding of the PDE. */
2214#if IOMMU_MAX_HOST_PT_LEVEL < 6
2215 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2216 { /* likely */ }
2217 else
2218 {
2219 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2220 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2221 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2222 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2223 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2224 kIoPageFaultType_PteInvalidLvlEncoding);
2225 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2226 }
2227#else
2228 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2229#endif
2230
2231 /* Validate level transition. */
2232 if (uNextLevel < uLevel)
2233 { /* likely */ }
2234 else
2235 {
2236 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2237 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2238 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2239 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2240 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2241 kIoPageFaultType_PteInvalidLvlEncoding);
2242 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2243 }
2244
2245 /* Ensure IOVA bits of skipped levels are zero. */
2246 Assert(uLevel > 0);
2247 uint64_t uIovaSkipMask = 0;
2248 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2249 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2250 if (!(uIova & uIovaSkipMask))
2251 { /* likely */ }
2252 else
2253 {
2254 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2255 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2256 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2257 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2258 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2259 kIoPageFaultType_SkippedLevelIovaNotZero);
2260 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2261 }
2262
2263 /* Continue with traversing the page directory at this level. */
2264 }
2265}
2266
2267
2268/**
2269 * Looks up an I/O virtual address from the device table.
2270 *
2271 * @returns VBox status code.
2272 * @param pDevIns The IOMMU instance data.
2273 * @param uDevId The device ID.
2274 * @param uIova The I/O virtual address to lookup.
2275 * @param cbAccess The size of the access.
2276 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2277 * permissions for the access being made.
2278 * @param enmOp The IOMMU operation being performed.
2279 * @param pGCPhysSpa Where to store the translated system physical address. Only
2280 * valid when translation succeeds and VINF_SUCCESS is
2281 * returned!
2282 *
2283 * @thread Any.
2284 */
2285static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2286 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2287{
2288 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2289
2290 /* Read the device table entry from memory. */
2291 DTE_T Dte;
2292 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2293 if (RT_SUCCESS(rc))
2294 {
2295 /* If the DTE is not valid, addresses are forwarded without translation */
2296 if (Dte.n.u1Valid)
2297 { /* likely */ }
2298 else
2299 {
2300 /** @todo IOMMU: Add to IOLTB cache. */
2301 *pGCPhysSpa = uIova;
2302 return VINF_SUCCESS;
2303 }
2304
2305 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2306 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2307 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2308 if (RT_LIKELY( !fRsvd0
2309 && !fRsvd1))
2310 { /* likely */ }
2311 else
2312 {
2313 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2314 EVT_ILLEGAL_DTE_T Event;
2315 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2316 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2317 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2318 }
2319
2320 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2321 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
2322 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2323 { /* likely */ }
2324 else
2325 {
2326 /** @todo IOMMU: Add to IOLTB cache. */
2327 *pGCPhysSpa = uIova;
2328 return VINF_SUCCESS;
2329 }
2330
2331 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
2332 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
2333
2334 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
2335 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2336 uint64_t cbRemaining = cbAccess;
2337 for (;;)
2338 {
2339 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
2340 IOWALKRESULT WalkResult;
2341 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
2342 if (RT_SUCCESS(rc))
2343 {
2344 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
2345
2346 /* Store the translated base address before continuing to check permissions for any more pages. */
2347 if (cbRemaining == cbAccess)
2348 {
2349 RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2350 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2351 }
2352
2353 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
2354 if (cbRemaining > cbPhysPage - offIova)
2355 {
2356 cbRemaining -= (cbPhysPage - offIova);
2357 uBaseIova += cbPhysPage;
2358 offIova = 0;
2359 }
2360 else
2361 break;
2362 }
2363 else
2364 {
2365 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
2366 uBaseIova, fAccess, rc));
2367 *pGCPhysSpa = NIL_RTGCPHYS;
2368 return rc;
2369 }
2370 }
2371
2372 return rc;
2373 }
2374
2375 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2376 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2377}
2378
2379
2380/**
2381 * Memory read request from a device.
2382 *
2383 * @returns VBox status code.
2384 * @param pDevIns The IOMMU device instance.
2385 * @param uDevId The device ID (bus, device, function).
2386 * @param uIova The I/O virtual address being read.
2387 * @param cbRead The number of bytes being read.
2388 * @param pGCPhysSpa Where to store the translated system physical address.
2389 *
2390 * @thread Any.
2391 */
2392static DECLCALLBACK(int) iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
2393 PRTGCPHYS pGCPhysSpa)
2394{
2395 /* Validate. */
2396 Assert(pDevIns);
2397 Assert(pGCPhysSpa);
2398 Assert(cbRead > 0);
2399
2400 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2401 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
2402
2403 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2404 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2405 if (Ctrl.n.u1IommuEn)
2406 {
2407 /** @todo IOMMU: IOTLB cache lookup. */
2408
2409 /* Lookup the IOVA from the device table. */
2410 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
2411 }
2412
2413 *pGCPhysSpa = uIova;
2414 return VINF_SUCCESS;
2415}
2416
2417
2418/**
2419 * Memory write request from a device.
2420 *
2421 * @returns VBox status code.
2422 * @param pDevIns The IOMMU device instance.
2423 * @param uDevId The device ID (bus, device, function).
2424 * @param uIova The I/O virtual address being written.
2425 * @param cbWrite The number of bytes being written.
2426 * @param pGCPhysSpa Where to store the translated physical address.
2427 *
2428 * @thread Any.
2429 */
2430static DECLCALLBACK(int) iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
2431 PRTGCPHYS pGCPhysSpa)
2432{
2433 /* Validate. */
2434 Assert(pDevIns);
2435 Assert(pGCPhysSpa);
2436 Assert(cbWrite > 0);
2437
2438 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2439 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
2440
2441 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2442 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2443 if (Ctrl.n.u1IommuEn)
2444 {
2445 /** @todo IOMMU: IOTLB cache lookup. */
2446
2447 /* Lookup the IOVA from the device table. */
2448 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
2449 }
2450
2451 *pGCPhysSpa = uIova;
2452 return VINF_SUCCESS;
2453}
2454
2455
2456/**
2457 * Reads an interrupt remapping table entry from guest memory given its DTE.
2458 *
2459 * @returns VBox status code.
2460 * @param pDevIns The IOMMU device instance.
2461 * @param uDevId The device ID.
2462 * @param pDte The device table entry.
2463 * @param GCPhysIn The source MSI address.
2464 * @param uDataIn The source MSI data.
2465 * @param enmOp The IOMMU operation being performed.
2466 * @param pIrte Where to store the interrupt remapping table entry.
2467 *
2468 * @thread Any.
2469 */
2470static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
2471 IOMMUOP enmOp, PIRTE_T pIrte)
2472{
2473 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
2474 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) << IOMMU_IRTE_SIZE_SHIFT;
2475 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
2476
2477 /* Ensure the IRTE offset is within the specified table size. */
2478 Assert(pDte->n.u4IntrTableLength < 12);
2479 if (offIrte + sizeof(IRTE_T) <= (1U << pDte->n.u4IntrTableLength) << IOMMU_IRTE_SIZE_SHIFT)
2480 { /* likely */ }
2481 else
2482 {
2483 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2484 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
2485 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2486 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2487 kIoPageFaultType_IrteAddrInvalid);
2488 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2489 }
2490
2491 /* Read the IRTE from memory. */
2492 Assert(!(GCPhysIrte & 3));
2493 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
2494 if (RT_SUCCESS(rc))
2495 return VINF_SUCCESS;
2496
2497 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
2498 * situation. Is it an I/O page fault or a device table hardware error?
2499 * There's no interrupt table hardware error event, but it's unclear what
2500 * we should do here. */
2501 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
2502 return VERR_IOMMU_IPE_4;
2503}
2504
2505
2506/**
2507 * Remap the interrupt using the interrupt remapping table.
2508 *
2509 * @returns VBox status code.
2510 * @param pDevIns The IOMMU instance data.
2511 * @param uDevId The device ID.
2512 * @param pDte The device table entry.
2513 * @param enmOp The IOMMU operation being performed.
2514 * @param pMsiIn The source MSI.
2515 * @param pMsiOut Where to store the remapped MSI.
2516 *
2517 * @thread Any.
2518 */
2519static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
2520 PMSIMSG pMsiOut)
2521{
2522 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
2523
2524 IRTE_T Irte;
2525 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
2526 if (RT_SUCCESS(rc))
2527 {
2528 if (Irte.n.u1RemapEnable)
2529 {
2530 if (!Irte.n.u1GuestMode)
2531 {
2532 if (Irte.n.u3IntrType < VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
2533 {
2534 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
2535 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
2536 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
2537 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
2538
2539 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
2540 pMsiOut->Data.u32 = pMsiIn->Data.u32;
2541 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
2542 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
2543
2544 return VINF_SUCCESS;
2545 }
2546
2547 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
2548 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2549 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2550 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2551 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
2552 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2553 }
2554
2555 LogFunc(("Guest mode not supported -> IOPF\n"));
2556 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2557 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2558 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2559 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
2560 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2561 }
2562
2563 LogFunc(("Remapping disabled -> IOPF\n"));
2564 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2565 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2566 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2567 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
2568 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2569 }
2570
2571 return rc;
2572}
2573
2574
2575/**
2576 * Looks up an MSI interrupt from the interrupt remapping table.
2577 *
2578 * @returns VBox status code.
2579 * @param pDevIns The IOMMU instance data.
2580 * @param uDevId The device ID.
2581 * @param enmOp The IOMMU operation being performed.
2582 * @param pMsiIn The source MSI.
2583 * @param pMsiOut Where to store the remapped MSI.
2584 *
2585 * @thread Any.
2586 */
2587static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2588{
2589 /* Read the device table entry from memory. */
2590 LogFlowFunc(("uDevId=%#x enmOp=%u\n", uDevId, enmOp));
2591
2592 DTE_T Dte;
2593 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2594 if (RT_SUCCESS(rc))
2595 {
2596 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
2597 if (Dte.n.u1IntrMapValid)
2598 {
2599 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
2600 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
2601 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
2602 if (RT_LIKELY( !fRsvd0
2603 && !fRsvd1))
2604 { /* likely */ }
2605 else
2606 {
2607 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
2608 fRsvd1));
2609 EVT_ILLEGAL_DTE_T Event;
2610 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
2611 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2612 return VERR_IOMMU_INTR_REMAP_FAILED;
2613 }
2614
2615 /*
2616 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
2617 * that's connected through HyperTransport it might be possible; but for us, it
2618 * doesn't seem we need to specially handle these pins.
2619 */
2620
2621 /*
2622 * Validate the MSI source address.
2623 *
2624 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
2625 * CPU is concerned, the MSI region is fixed and we must ensure no other device
2626 * claims the region as I/O space.
2627 *
2628 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
2629 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
2630 * See Intel spec. 10.11.1 "Message Address Register Format".
2631 */
2632 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
2633 {
2634 /*
2635 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
2636 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
2637 */
2638 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
2639 bool fPassThru = false;
2640 switch (u8DeliveryMode)
2641 {
2642 case VBOX_MSI_DELIVERY_MODE_FIXED:
2643 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
2644 {
2645 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
2646 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
2647 {
2648 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
2649 iommuAmdSetPciTargetAbort(pDevIns);
2650 return VERR_IOMMU_INTR_REMAP_DENIED;
2651 }
2652
2653 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
2654 {
2655 fPassThru = true;
2656 break;
2657 }
2658
2659 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
2660 {
2661 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
2662 uint32_t const uIntTabLen = Dte.n.u4IntrTableLength;
2663 if (Dte.n.u4IntrTableLength < 12)
2664 {
2665 /*
2666 * We don't support guest interrupt remapping yet. When we do, we'll need to
2667 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
2668 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
2669 * already reads the control register, add that as a parameter when we eventually
2670 * support guest interrupt remapping. For now, just assert.
2671 */
2672 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2673 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
2674 NOREF(pThis);
2675
2676 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
2677 }
2678
2679 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntTabLen));
2680 EVT_ILLEGAL_DTE_T Event;
2681 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
2682 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
2683 return VERR_IOMMU_INTR_REMAP_FAILED;
2684 }
2685
2686 /* Paranoia. */
2687 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
2688
2689 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
2690
2691 EVT_ILLEGAL_DTE_T Event;
2692 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
2693 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
2694 return VERR_IOMMU_INTR_REMAP_FAILED;
2695 }
2696
2697 /* SMIs are passed through unmapped. We don't implement SMI filters. */
2698 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
2699 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
2700 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
2701 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
2702 default:
2703 {
2704 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
2705 iommuAmdSetPciTargetAbort(pDevIns);
2706 return VERR_IOMMU_INTR_REMAP_FAILED;
2707 }
2708 }
2709
2710 if (fPassThru)
2711 {
2712 *pMsiOut = *pMsiIn;
2713 return VINF_SUCCESS;
2714 }
2715
2716 iommuAmdSetPciTargetAbort(pDevIns);
2717 return VERR_IOMMU_INTR_REMAP_DENIED;
2718 }
2719 else
2720 {
2721 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
2722 return VERR_IOMMU_INTR_REMAP_FAILED;
2723 }
2724 }
2725 else
2726 {
2727 /** @todo IOMMU: Add to interrupt remapping cache. */
2728 LogFlowFunc(("DTE interrupt map not valid\n"));
2729 *pMsiOut = *pMsiIn;
2730 return VINF_SUCCESS;
2731 }
2732 }
2733
2734 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2735 return VERR_IOMMU_INTR_REMAP_FAILED;
2736}
2737
2738
2739/**
2740 * Interrupt remap request from a device.
2741 *
2742 * @returns VBox status code.
2743 * @param pDevIns The IOMMU device instance.
2744 * @param uDevId The device ID (bus, device, function).
2745 * @param pMsiIn The source MSI.
2746 * @param pMsiOut Where to store the remapped MSI.
2747 */
2748static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2749{
2750 /* Validate. */
2751 Assert(pDevIns);
2752 Assert(pMsiIn);
2753 Assert(pMsiOut);
2754
2755 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2756 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
2757
2758 LogFlowFunc(("uDevId=%#x\n", uDevId));
2759
2760 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
2761 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2762 if (Ctrl.n.u1IommuEn)
2763 {
2764 /** @todo Cache? */
2765
2766 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
2767 }
2768
2769 *pMsiOut = *pMsiIn;
2770 return VINF_SUCCESS;
2771}
2772
2773
2774/**
2775 * @callback_method_impl{FNIOMMMIONEWWRITE}
2776 */
2777static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
2778{
2779 NOREF(pvUser);
2780 Assert(cb == 4 || cb == 8);
2781 Assert(!(off & (cb - 1)));
2782
2783 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2784 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
2785
2786 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
2787 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
2788}
2789
2790
2791/**
2792 * @callback_method_impl{FNIOMMMIONEWREAD}
2793 */
2794static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
2795{
2796 NOREF(pvUser);
2797 Assert(cb == 4 || cb == 8);
2798 Assert(!(off & (cb - 1)));
2799
2800 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2801 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
2802
2803 uint64_t uResult;
2804 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
2805 if (cb == 8)
2806 *(uint64_t *)pv = uResult;
2807 else
2808 *(uint32_t *)pv = (uint32_t)uResult;
2809
2810 return rcStrict;
2811}
2812
2813# ifdef IN_RING3
2814
2815/**
2816 * Processes an IOMMU command.
2817 *
2818 * @returns VBox status code.
2819 * @param pDevIns The IOMMU device instance.
2820 * @param pCmd The command to process.
2821 * @param GCPhysCmd The system physical address of the command.
2822 * @param pEvtError Where to store the error event in case of failures.
2823 *
2824 * @thread Command thread.
2825 */
2826static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
2827{
2828 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
2829
2830 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2831 STAM_COUNTER_INC(&pThis->StatCmd);
2832
2833 uint8_t const bCmd = pCmd->n.u4Opcode;
2834 switch (bCmd)
2835 {
2836 case IOMMU_CMD_COMPLETION_WAIT:
2837 {
2838 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
2839
2840 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
2841 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
2842
2843 /* Validate reserved bits in the command. */
2844 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
2845 {
2846 /* If Completion Store is requested, write the StoreData to the specified address. */
2847 if (pCmdComWait->n.u1Store)
2848 {
2849 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
2850 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
2851 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
2852 if (RT_FAILURE(rc))
2853 {
2854 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
2855 GCPhysStore, rc));
2856 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
2857 return VERR_IOMMU_CMD_HW_ERROR;
2858 }
2859 }
2860
2861 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
2862 if (pCmdComWait->n.u1Interrupt)
2863 {
2864 IOMMU_LOCK(pDevIns);
2865 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
2866 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2867 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
2868 IOMMU_UNLOCK(pDevIns);
2869
2870 if (fRaiseInt)
2871 iommuAmdRaiseMsiInterrupt(pDevIns);
2872 }
2873 return VINF_SUCCESS;
2874 }
2875 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2876 return VERR_IOMMU_CMD_INVALID_FORMAT;
2877 }
2878
2879 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
2880 {
2881 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2882 * then. */
2883 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
2884 return VINF_SUCCESS;
2885 }
2886
2887 case IOMMU_CMD_INV_IOMMU_PAGES:
2888 {
2889 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2890 * then. */
2891 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
2892 return VINF_SUCCESS;
2893 }
2894
2895 case IOMMU_CMD_INV_IOTLB_PAGES:
2896 {
2897 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
2898
2899 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
2900 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
2901 {
2902 /** @todo IOMMU: Implement remote IOTLB invalidation. */
2903 return VERR_NOT_IMPLEMENTED;
2904 }
2905 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2906 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2907 }
2908
2909 case IOMMU_CMD_INV_INTR_TABLE:
2910 {
2911 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
2912 * then. */
2913 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
2914 return VINF_SUCCESS;
2915 }
2916
2917 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
2918 {
2919 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
2920 if (pThis->ExtFeat.n.u1PrefetchSup)
2921 {
2922 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
2923 return VINF_SUCCESS;
2924 }
2925 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2926 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2927 }
2928
2929 case IOMMU_CMD_COMPLETE_PPR_REQ:
2930 {
2931 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
2932
2933 /* We don't support PPR requests yet. */
2934 Assert(!pThis->ExtFeat.n.u1PprSup);
2935 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2936 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2937 }
2938
2939 case IOMMU_CMD_INV_IOMMU_ALL:
2940 {
2941 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
2942
2943 if (pThis->ExtFeat.n.u1InvAllSup)
2944 {
2945 /** @todo IOMMU: Invalidate all. Pretend success until then. */
2946 return VINF_SUCCESS;
2947 }
2948 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2949 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2950 }
2951 }
2952
2953 STAM_COUNTER_DEC(&pThis->StatCmd);
2954 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
2955 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
2956 return VERR_IOMMU_CMD_NOT_SUPPORTED;
2957}
2958
2959
2960/**
2961 * The IOMMU command thread.
2962 *
2963 * @returns VBox status code.
2964 * @param pDevIns The IOMMU device instance.
2965 * @param pThread The command thread.
2966 */
2967static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2968{
2969 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2970
2971 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2972 return VINF_SUCCESS;
2973
2974 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2975 {
2976 /*
2977 * Sleep perpetually until we are woken up to process commands.
2978 */
2979 {
2980 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
2981 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
2982 if (!fSignaled)
2983 {
2984 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
2985 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
2986 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2987 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2988 break;
2989 Log5Func(("Woken up with rc=%Rrc\n", rc));
2990 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
2991 }
2992 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
2993 }
2994
2995 /*
2996 * Fetch and process IOMMU commands.
2997 */
2998 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
2999 * at a time) and is expensive due to calls to PGM for fetching guest memory.
3000 * We could optimize by fetching a bunch of commands at a time reducing
3001 * number of calls to PGM. In the longer run we could lock the memory and
3002 * mappings and accessing them directly. */
3003 IOMMU_LOCK(pDevIns);
3004
3005 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3006 if (Status.n.u1CmdBufRunning)
3007 {
3008 /* Get the offset we need to read the command from memory (circular buffer offset). */
3009 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3010 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3011 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3012 Assert(offHead < cbCmdBuf);
3013 while (offHead != pThis->CmdBufTailPtr.n.off)
3014 {
3015 /* Read the command from memory. */
3016 CMD_GENERIC_T Cmd;
3017 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3018 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3019 if (RT_SUCCESS(rc))
3020 {
3021 /* Increment the command buffer head pointer. */
3022 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3023 pThis->CmdBufHeadPtr.n.off = offHead;
3024
3025 /* Process the fetched command. */
3026 EVT_GENERIC_T EvtError;
3027 IOMMU_UNLOCK(pDevIns);
3028 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3029 IOMMU_LOCK(pDevIns);
3030 if (RT_FAILURE(rc))
3031 {
3032 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3033 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3034 {
3035 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3036 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3037 }
3038 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3039 {
3040 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3041 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3042 }
3043 break;
3044 }
3045 }
3046 else
3047 {
3048 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3049 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3050 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3051 break;
3052 }
3053 }
3054 }
3055
3056 IOMMU_UNLOCK(pDevIns);
3057 }
3058
3059 LogFlowFunc(("Command thread terminating\n"));
3060 return VINF_SUCCESS;
3061}
3062
3063
3064/**
3065 * Wakes up the command thread so it can respond to a state change.
3066 *
3067 * @returns VBox status code.
3068 * @param pDevIns The IOMMU device instance.
3069 * @param pThread The command thread.
3070 */
3071static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3072{
3073 RT_NOREF(pThread);
3074 LogFlowFunc(("\n"));
3075 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3076 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3077}
3078
3079
3080/**
3081 * @callback_method_impl{FNPCICONFIGREAD}
3082 */
3083static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3084 unsigned cb, uint32_t *pu32Value)
3085{
3086 /** @todo IOMMU: PCI config read stat counter. */
3087 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3088 Log3Func(("Reading PCI config register %#x (cb=%u) -> %#x %Rrc\n", uAddress, cb, *pu32Value,
3089 VBOXSTRICTRC_VAL(rcStrict)));
3090 return rcStrict;
3091}
3092
3093
3094/**
3095 * @callback_method_impl{FNPCICONFIGWRITE}
3096 */
3097static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3098 unsigned cb, uint32_t u32Value)
3099{
3100 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3101
3102 /*
3103 * Discard writes to read-only registers that are specific to the IOMMU.
3104 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3105 * See PCI spec. 6.1. "Configuration Space Organization".
3106 */
3107 switch (uAddress)
3108 {
3109 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3110 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3111 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3112 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3113 {
3114 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3115 return VINF_SUCCESS;
3116 }
3117 }
3118
3119 IOMMU_LOCK(pDevIns);
3120
3121 VBOXSTRICTRC rcStrict = VERR_INVALID_FUNCTION;
3122 switch (uAddress)
3123 {
3124 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3125 {
3126 if (pThis->IommuBar.n.u1Enable)
3127 {
3128 rcStrict = VINF_SUCCESS;
3129 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3130 break;
3131 }
3132
3133 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3134 if (pThis->IommuBar.n.u1Enable)
3135 {
3136 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE);
3137 Assert(PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio) == NIL_RTGCPHYS);
3138 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3139 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3140 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3141 if (RT_FAILURE(rcStrict))
3142 LogFunc(("Failed to map IOMMU MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rcStrict));
3143 }
3144 break;
3145 }
3146
3147 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3148 {
3149 if (!pThis->IommuBar.n.u1Enable)
3150 pThis->IommuBar.au32[1] = u32Value;
3151 else
3152 {
3153 rcStrict = VINF_SUCCESS;
3154 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3155 }
3156 break;
3157 }
3158
3159 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3160 {
3161 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3162 RT_FALL_THRU();
3163 }
3164 default:
3165 {
3166 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3167 break;
3168 }
3169 }
3170
3171 IOMMU_UNLOCK(pDevIns);
3172
3173 Log3Func(("PCI config write: %#x -> To %#x (%u) %Rrc\n", u32Value, uAddress, cb, VBOXSTRICTRC_VAL(rcStrict)));
3174 return rcStrict;
3175}
3176
3177
3178/**
3179 * @callback_method_impl{FNDBGFHANDLERDEV}
3180 */
3181static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3182{
3183 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3184 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3185 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3186
3187 bool fVerbose;
3188 if ( pszArgs
3189 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3190 fVerbose = true;
3191 else
3192 fVerbose = false;
3193
3194 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3195 /* Device Table Base Addresses (all segments). */
3196 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3197 {
3198 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3199 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3200 if (fVerbose)
3201 {
3202 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3203 IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size));
3204 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3205 }
3206 }
3207 /* Command Buffer Base Address Register. */
3208 {
3209 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3210 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3211 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3212 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3213 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
3214 if (fVerbose)
3215 {
3216 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3217 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3218 cEntries, cbBuffer);
3219 }
3220 }
3221 /* Event Log Base Address Register. */
3222 {
3223 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3224 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3225 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3226 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3227 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
3228 if (fVerbose)
3229 {
3230 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3231 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3232 cEntries, cbBuffer);
3233 }
3234 }
3235 /* IOMMU Control Register. */
3236 {
3237 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3238 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3239 if (fVerbose)
3240 {
3241 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3242 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3243 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3244 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3245 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3246 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3247 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3248 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3249 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3250 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3251 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3252 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3253 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3254 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3255 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3256 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3257 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3258 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3259 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3260 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3261 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3262 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3263 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3264 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3265 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3266 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3267 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3268 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3269 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3270 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3271 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3272 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3273 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3274 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3275 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3276 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3277 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3278 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3279 }
3280 }
3281 /* Exclusion Base Address Register. */
3282 {
3283 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3284 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3285 if (fVerbose)
3286 {
3287 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3288 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3289 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
3290 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
3291 }
3292 }
3293 /* Exclusion Range Limit Register. */
3294 {
3295 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3296 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3297 if (fVerbose)
3298 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
3299 }
3300 /* Extended Feature Register. */
3301 {
3302 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3303 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3304 if (fVerbose)
3305 {
3306 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3307 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3308 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3309 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3310 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3311 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3312 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3313 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3314 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3315 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3316 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3317 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3318 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3319 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3320 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3321 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3322 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3323 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3324 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3325 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
3326 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
3327 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3328 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3329 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3330 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3331 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3332 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3333 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3334 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3335 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3336 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3337 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3338 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3339 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3340 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3341 }
3342 }
3343 /* PPR Log Base Address Register. */
3344 {
3345 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3346 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
3347 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3348 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3349 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3350 if (fVerbose)
3351 {
3352 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3353 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3354 cEntries, cbBuffer);
3355 }
3356 }
3357 /* Hardware Event (Hi) Register. */
3358 {
3359 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
3360 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
3361 if (fVerbose)
3362 {
3363 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
3364 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
3365 }
3366 }
3367 /* Hardware Event (Lo) Register. */
3368 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
3369 /* Hardware Event Status. */
3370 {
3371 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
3372 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
3373 if (fVerbose)
3374 {
3375 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
3376 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
3377 }
3378 }
3379 /* Guest Virtual-APIC Log Base Address Register. */
3380 {
3381 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
3382 uint8_t const uEncodedLen = GALogBar.n.u4Len;
3383 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3384 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3385 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
3386 if (fVerbose)
3387 {
3388 pHlp->pfnPrintf(pHlp, " Base address = %RTbool\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3389 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3390 cEntries, cbBuffer);
3391 }
3392 }
3393 /* Guest Virtual-APIC Log Tail Address Register. */
3394 {
3395 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
3396 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
3397 if (fVerbose)
3398 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
3399 }
3400 /* PPR Log B Base Address Register. */
3401 {
3402 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
3403 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
3404 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3405 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3406 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
3407 if (fVerbose)
3408 {
3409 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3410 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3411 cEntries, cbBuffer);
3412 }
3413 }
3414 /* Event Log B Base Address Register. */
3415 {
3416 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
3417 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
3418 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3419 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3420 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
3421 if (fVerbose)
3422 {
3423 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3424 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3425 cEntries, cbBuffer);
3426 }
3427 }
3428 /* Device-Specific Feature Extension Register. */
3429 {
3430 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
3431 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
3432 if (fVerbose)
3433 {
3434 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
3435 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
3436 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
3437 }
3438 }
3439 /* Device-Specific Control Extension Register. */
3440 {
3441 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
3442 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
3443 if (fVerbose)
3444 {
3445 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
3446 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
3447 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
3448 }
3449 }
3450 /* Device-Specific Status Extension Register. */
3451 {
3452 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
3453 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
3454 if (fVerbose)
3455 {
3456 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
3457 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
3458 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
3459 }
3460 }
3461 /* Miscellaneous Information Register (Lo and Hi). */
3462 {
3463 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
3464 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
3465 if (fVerbose)
3466 {
3467 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
3468 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
3469 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
3470 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
3471 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
3472 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
3473 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
3474 }
3475 }
3476 /* MSI Capability Header. */
3477 {
3478 MSI_CAP_HDR_T MsiCapHdr;
3479 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3480 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
3481 if (fVerbose)
3482 {
3483 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
3484 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
3485 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
3486 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
3487 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
3488 }
3489 }
3490 /* MSI Address Register (Lo and Hi). */
3491 {
3492 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3493 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3494 MSIADDR MsiAddr;
3495 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
3496 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
3497 if (fVerbose)
3498 {
3499 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
3500 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
3501 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
3502 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
3503 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
3504 }
3505 }
3506 /* MSI Data. */
3507 {
3508 MSIDATA MsiData;
3509 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3510 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
3511 if (fVerbose)
3512 {
3513 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
3514 MsiData.n.u8Vector);
3515 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
3516 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
3517 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
3518 "level" : "edge");
3519 }
3520 }
3521 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
3522 {
3523 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
3524 MsiMapCapHdr.u32 = 0;
3525 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
3526 if (fVerbose)
3527 {
3528 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
3529 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
3530 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
3531 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
3532 }
3533 }
3534 /* Performance Optimization Control Register. */
3535 {
3536 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
3537 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
3538 if (fVerbose)
3539 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
3540 }
3541 /* XT (x2APIC) General Interrupt Control Register. */
3542 {
3543 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
3544 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
3545 if (fVerbose)
3546 {
3547 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3548 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3549 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3550 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
3551 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
3552 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
3553 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3554 }
3555 }
3556 /* XT (x2APIC) PPR Interrupt Control Register. */
3557 {
3558 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
3559 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
3560 if (fVerbose)
3561 {
3562 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3563 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3564 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3565 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
3566 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
3567 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
3568 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3569 }
3570 }
3571 /* XT (X2APIC) GA Log Interrupt Control Register. */
3572 {
3573 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
3574 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
3575 if (fVerbose)
3576 {
3577 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
3578 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
3579 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
3580 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
3581 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
3582 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
3583 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
3584 }
3585 }
3586 /* MARC Registers. */
3587 {
3588 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
3589 {
3590 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
3591 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
3592 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
3593
3594 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
3595 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
3596 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
3597 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
3598
3599 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
3600 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
3601 }
3602 }
3603 /* Reserved Register. */
3604 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
3605 /* Command Buffer Head Pointer Register. */
3606 {
3607 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
3608 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
3609 CmdBufHeadPtr.n.off);
3610 }
3611 /* Command Buffer Tail Pointer Register. */
3612 {
3613 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
3614 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
3615 CmdBufTailPtr.n.off);
3616 }
3617 /* Event Log Head Pointer Register. */
3618 {
3619 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
3620 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
3621 EvtLogHeadPtr.n.off);
3622 }
3623 /* Event Log Tail Pointer Register. */
3624 {
3625 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
3626 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
3627 EvtLogTailPtr.n.off);
3628 }
3629 /* Status Register. */
3630 {
3631 IOMMU_STATUS_T const Status = pThis->Status;
3632 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
3633 if (fVerbose)
3634 {
3635 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
3636 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
3637 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
3638 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
3639 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
3640 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
3641 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
3642 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
3643 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
3644 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
3645 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
3646 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
3647 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
3648 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
3649 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
3650 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
3651 }
3652 }
3653 /* PPR Log Head Pointer. */
3654 {
3655 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
3656 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
3657 PprLogHeadPtr.n.off);
3658 }
3659 /* PPR Log Tail Pointer. */
3660 {
3661 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
3662 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
3663 PprLogTailPtr.n.off);
3664 }
3665 /* Guest Virtual-APIC Log Head Pointer. */
3666 {
3667 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
3668 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
3669 GALogHeadPtr.n.u12GALogPtr);
3670 }
3671 /* Guest Virtual-APIC Log Tail Pointer. */
3672 {
3673 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
3674 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
3675 GALogTailPtr.n.u12GALogPtr);
3676 }
3677 /* PPR Log B Head Pointer. */
3678 {
3679 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
3680 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
3681 PprLogBHeadPtr.n.off);
3682 }
3683 /* PPR Log B Tail Pointer. */
3684 {
3685 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
3686 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
3687 PprLogBTailPtr.n.off);
3688 }
3689 /* Event Log B Head Pointer. */
3690 {
3691 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
3692 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
3693 EvtLogBHeadPtr.n.off);
3694 }
3695 /* Event Log B Tail Pointer. */
3696 {
3697 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
3698 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
3699 EvtLogBTailPtr.n.off);
3700 }
3701 /* PPR Log Auto Response Register. */
3702 {
3703 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
3704 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
3705 if (fVerbose)
3706 {
3707 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
3708 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
3709 }
3710 }
3711 /* PPR Log Overflow Early Warning Indicator Register. */
3712 {
3713 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
3714 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
3715 if (fVerbose)
3716 {
3717 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
3718 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
3719 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
3720 }
3721 }
3722 /* PPR Log Overflow Early Warning Indicator Register. */
3723 {
3724 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
3725 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
3726 if (fVerbose)
3727 {
3728 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
3729 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
3730 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
3731 }
3732 }
3733}
3734
3735
3736static void iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
3737{
3738 RT_NOREF(pDevIns);
3739 pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
3740 pHlp->pfnPrintf(pHlp, " %sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
3741}
3742
3743
3744/**
3745 * @callback_method_impl{FNDBGFHANDLERDEV}
3746 */
3747static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3748{
3749 RT_NOREF(pszArgs);
3750
3751 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3752 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3753 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3754
3755 uint8_t cTables = 0;
3756 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3757 {
3758 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
3759 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
3760 if (GCPhysDevTab)
3761 ++cTables;
3762 }
3763
3764 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
3765 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
3766 if (!cTables)
3767 return;
3768
3769 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3770 {
3771 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
3772 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
3773 if (GCPhysDevTab)
3774 {
3775 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_SIZE(DevTabBar.n.u9Size);
3776 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
3777 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
3778
3779 void *pvDevTab = RTMemAllocZ(cbDevTab);
3780 if (RT_LIKELY(pvDevTab))
3781 {
3782 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
3783 if (RT_SUCCESS(rc))
3784 {
3785 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
3786 {
3787 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
3788 if ( pDte->n.u1Valid
3789 || pDte->n.u1IntrMapValid)
3790 {
3791 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
3792 iommuAmdR3DbgInfoDte(pDevIns, pHlp, pDte, " ");
3793 }
3794 }
3795 pHlp->pfnPrintf(pHlp, "\n");
3796 }
3797 else
3798 {
3799 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
3800 cbDevTab, rc);
3801 }
3802
3803 RTMemFree(pvDevTab);
3804 }
3805 else
3806 {
3807 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
3808 return;
3809 }
3810 }
3811 }
3812
3813}
3814
3815
3816/**
3817 * @callback_method_impl{FNSSMDEVSAVEEXEC}
3818 */
3819static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3820{
3821 /** @todo IOMMU: Save state. */
3822 RT_NOREF2(pDevIns, pSSM);
3823 LogFlowFunc(("\n"));
3824 return VERR_NOT_IMPLEMENTED;
3825}
3826
3827
3828/**
3829 * @callback_method_impl{FNSSMDEVLOADEXEC}
3830 */
3831static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3832{
3833 /** @todo IOMMU: Load state. */
3834 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
3835 LogFlowFunc(("\n"));
3836 return VERR_NOT_IMPLEMENTED;
3837}
3838
3839
3840/**
3841 * @interface_method_impl{PDMDEVREG,pfnReset}
3842 */
3843static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
3844{
3845 /*
3846 * Resets read-write portion of the IOMMU state.
3847 *
3848 * State data not initialized here is expected to be initialized during
3849 * device construction and remain read-only through the lifetime of the VM.
3850 */
3851 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3852 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3853 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3854
3855 LogFlowFunc(("\n"));
3856
3857 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
3858
3859 pThis->CmdBufBaseAddr.u64 = 0;
3860 pThis->CmdBufBaseAddr.n.u4Len = 8;
3861
3862 pThis->EvtLogBaseAddr.u64 = 0;
3863 pThis->EvtLogBaseAddr.n.u4Len = 8;
3864
3865 pThis->Ctrl.u64 = 0;
3866 pThis->Ctrl.n.u1Coherent = 1;
3867 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
3868
3869 pThis->ExclRangeBaseAddr.u64 = 0;
3870 pThis->ExclRangeLimit.u64 = 0;
3871
3872 pThis->PprLogBaseAddr.u64 = 0;
3873 pThis->PprLogBaseAddr.n.u4Len = 8;
3874
3875 pThis->HwEvtHi.u64 = 0;
3876 pThis->HwEvtLo = 0;
3877 pThis->HwEvtStatus.u64 = 0;
3878
3879 pThis->GALogBaseAddr.u64 = 0;
3880 pThis->GALogBaseAddr.n.u4Len = 8;
3881 pThis->GALogTailAddr.u64 = 0;
3882
3883 pThis->PprLogBBaseAddr.u64 = 0;
3884 pThis->PprLogBBaseAddr.n.u4Len = 8;
3885
3886 pThis->EvtLogBBaseAddr.u64 = 0;
3887 pThis->EvtLogBBaseAddr.n.u4Len = 8;
3888
3889 pThis->PerfOptCtrl.u32 = 0;
3890
3891 pThis->XtGenIntrCtrl.u64 = 0;
3892 pThis->XtPprIntrCtrl.u64 = 0;
3893 pThis->XtGALogIntrCtrl.u64 = 0;
3894
3895 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
3896
3897 pThis->CmdBufHeadPtr.u64 = 0;
3898 pThis->CmdBufTailPtr.u64 = 0;
3899 pThis->EvtLogHeadPtr.u64 = 0;
3900 pThis->EvtLogTailPtr.u64 = 0;
3901
3902 pThis->Status.u64 = 0;
3903
3904 pThis->PprLogHeadPtr.u64 = 0;
3905 pThis->PprLogTailPtr.u64 = 0;
3906
3907 pThis->GALogHeadPtr.u64 = 0;
3908 pThis->GALogTailPtr.u64 = 0;
3909
3910 pThis->PprLogBHeadPtr.u64 = 0;
3911 pThis->PprLogBTailPtr.u64 = 0;
3912
3913 pThis->EvtLogBHeadPtr.u64 = 0;
3914 pThis->EvtLogBTailPtr.u64 = 0;
3915
3916 pThis->PprLogAutoResp.u64 = 0;
3917 pThis->PprLogOverflowEarly.u64 = 0;
3918 pThis->PprLogBOverflowEarly.u64 = 0;
3919
3920 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
3921 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
3922
3923 /*
3924 * I ASSUME all MMIO regions mapped by a PDM device are automatically unmapped
3925 * on VM reset. If not, we need to enable the following...
3926 */
3927#if 0
3928 /* Unmap the MMIO region on reset if it has been mapped previously. */
3929 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE);
3930 if (PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio) != NIL_RTGCPHYS)
3931 PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3932#endif
3933}
3934
3935
3936/**
3937 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3938 */
3939static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
3940{
3941 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
3942 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3943 LogFlowFunc(("\n"));
3944
3945 /* Close the command thread semaphore. */
3946 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
3947 {
3948 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
3949 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
3950 }
3951 return VINF_SUCCESS;
3952}
3953
3954
3955/**
3956 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3957 */
3958static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3959{
3960 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3961 RT_NOREF(pCfg);
3962
3963 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3964 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3965 pThisCC->pDevInsR3 = pDevIns;
3966
3967 LogFlowFunc(("iInstance=%d\n", iInstance));
3968
3969 /*
3970 * Register the IOMMU with PDM.
3971 */
3972 PDMIOMMUREGR3 IommuReg;
3973 RT_ZERO(IommuReg);
3974 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3975 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
3976 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
3977 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
3978 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3979 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3980 if (RT_FAILURE(rc))
3981 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3982 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3983 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3984 N_("IOMMU helper version mismatch; got %#x expected %#x"),
3985 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3986 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3987 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3988 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3989 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3990
3991 /*
3992 * Initialize read-only PCI configuration space.
3993 */
3994 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3995 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3996
3997 /* Header. */
3998 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
3999 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4000 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we write to main memory) */
4001 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4002 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4003 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4004 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4005 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4006 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4007 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4008 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4009 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4010 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4011 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4012
4013 /* Capability Header. */
4014 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4015 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4016 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4017 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
4018 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4019 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4020 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4021 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4022 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4023 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4024 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4025
4026 /* Base Address Register. */
4027 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4028 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4029
4030 /* IOMMU Range Register. */
4031 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4032
4033 /* Misc. Information Register. */
4034 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4035 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4036 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4037 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4038 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4039 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4040 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4041 uint32_t const uMiscInfoReg1 = 0;
4042 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4043 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4044
4045 /* MSI Capability Header register. */
4046 PDMMSIREG MsiReg;
4047 RT_ZERO(MsiReg);
4048 MsiReg.cMsiVectors = 1;
4049 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4050 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4051 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4052
4053 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4054#if 0
4055 /* MSI Address Lo. */
4056 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4057 /* MSI Address Hi. */
4058 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4059 /* MSI Data. */
4060 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4061#endif
4062
4063#if 0
4064 /** @todo IOMMU: I don't know if we need to support this, enable later if
4065 * required. */
4066 /* MSI Mapping Capability Header register. */
4067 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4068 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4069 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4070 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4071 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4072 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4073 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4074#endif
4075
4076 /*
4077 * Register the PCI function with PDM.
4078 */
4079 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4080 AssertLogRelRCReturn(rc, rc);
4081
4082 /*
4083 * Register MSI support for the PCI device.
4084 * This must be done -after- register it as a PCI device!
4085 */
4086 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4087 AssertRCReturn(rc, rc);
4088
4089 /*
4090 * Intercept PCI config. space accesses.
4091 */
4092 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4093 AssertLogRelRCReturn(rc, rc);
4094
4095 /*
4096 * Create the MMIO region.
4097 * Mapping of the region is done when software configures it via PCI config space.
4098 */
4099 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4100 NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
4101 "AMD-IOMMU", &pThis->hMmio);
4102 AssertLogRelRCReturn(rc, rc);
4103
4104 /*
4105 * Register saved state.
4106 */
4107 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4108 NULL, NULL, NULL,
4109 NULL, iommuAmdR3SaveExec, NULL,
4110 NULL, iommuAmdR3LoadExec, NULL);
4111 AssertLogRelRCReturn(rc, rc);
4112
4113 /*
4114 * Register debugger info items.
4115 */
4116 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
4117 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
4118
4119# ifdef VBOX_WITH_STATISTICS
4120 /*
4121 * Statistics.
4122 */
4123 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4124 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4125
4126 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4127 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4128
4129 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemapR3", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
4130 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRZ", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
4131
4132 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
4133 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
4134 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
4135 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
4136 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
4137 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
4138 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
4139 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
4140 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
4141# endif
4142
4143 /*
4144 * Create the command thread and its event semaphore.
4145 */
4146 char szDevIommu[64];
4147 RT_ZERO(szDevIommu);
4148 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
4149 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
4150 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
4151 AssertLogRelRCReturn(rc, rc);
4152
4153 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
4154 AssertLogRelRCReturn(rc, rc);
4155
4156 /*
4157 * Initialize read-only registers.
4158 * NOTE! Fields here must match their corresponding field in the ACPI tables.
4159 */
4160 /** @todo Don't remove the =0 assignment for now. It's just there so it's easier
4161 * for me to see existing features that we might want to implement. Do it
4162 * later. */
4163 pThis->ExtFeat.u64 = 0;
4164 pThis->ExtFeat.n.u1PrefetchSup = 0;
4165 pThis->ExtFeat.n.u1PprSup = 0;
4166 pThis->ExtFeat.n.u1X2ApicSup = 0;
4167 pThis->ExtFeat.n.u1NoExecuteSup = 0;
4168 pThis->ExtFeat.n.u1GstTranslateSup = 0;
4169 pThis->ExtFeat.n.u1InvAllSup = 1;
4170 pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4171 pThis->ExtFeat.n.u1HwErrorSup = 1;
4172 pThis->ExtFeat.n.u1PerfCounterSup = 0;
4173 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4174 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4175 pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
4176 pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
4177 pThis->ExtFeat.n.u2SmiFilterSup = 0;
4178 pThis->ExtFeat.n.u3SmiFilterCount = 0;
4179 pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
4180 pThis->ExtFeat.n.u2DualPprLogSup = 0;
4181 pThis->ExtFeat.n.u2DualEvtLogSup = 0;
4182 pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
4183 pThis->ExtFeat.n.u1UserSupervisorSup = 0;
4184 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
4185 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
4186 pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
4187 pThis->ExtFeat.n.u1PprAutoRespSup = 0;
4188 pThis->ExtFeat.n.u2MarcSup = 0;
4189 pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
4190 pThis->ExtFeat.n.u1PerfOptSup = 0;
4191 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
4192 pThis->ExtFeat.n.u1GstIoSup = 0;
4193 pThis->ExtFeat.n.u1HostAccessSup = 0;
4194 pThis->ExtFeat.n.u1EnhancedPprSup = 0;
4195 pThis->ExtFeat.n.u1AttrForwardSup = 0;
4196 pThis->ExtFeat.n.u1HostDirtySup = 0;
4197 pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
4198 pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
4199 pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
4200
4201 pThis->RsvdReg = 0;
4202
4203 pThis->DevSpecificFeat.u64 = 0;
4204 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
4205 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
4206
4207 pThis->DevSpecificCtrl.u64 = 0;
4208 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
4209 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
4210
4211 pThis->DevSpecificStatus.u64 = 0;
4212 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
4213 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
4214
4215 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
4216
4217 /*
4218 * Initialize parts of the IOMMU state as it would during reset.
4219 * Must be called -after- initializing PCI config. space registers.
4220 */
4221 iommuAmdR3Reset(pDevIns);
4222
4223 return VINF_SUCCESS;
4224}
4225
4226# else /* !IN_RING3 */
4227
4228/**
4229 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4230 */
4231static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
4232{
4233 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4234 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4235 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4236
4237 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4238
4239 /* Set up the MMIO RZ handlers. */
4240 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
4241 AssertRCReturn(rc, rc);
4242
4243 /* Set up the IOMMU RZ callbacks. */
4244 PDMIOMMUREGCC IommuReg;
4245 RT_ZERO(IommuReg);
4246 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4247 IommuReg.idxIommu = pThis->idxIommu;
4248 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4249 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4250 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4251 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4252 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4253 AssertRCReturn(rc, rc);
4254
4255 return VINF_SUCCESS;
4256}
4257
4258# endif /* !IN_RING3 */
4259
4260/**
4261 * The device registration structure.
4262 */
4263const PDMDEVREG g_DeviceIommuAmd =
4264{
4265 /* .u32Version = */ PDM_DEVREG_VERSION,
4266 /* .uReserved0 = */ 0,
4267 /* .szName = */ "iommu-amd",
4268 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4269 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4270 /* .cMaxInstances = */ ~0U,
4271 /* .uSharedVersion = */ 42,
4272 /* .cbInstanceShared = */ sizeof(IOMMU),
4273 /* .cbInstanceCC = */ sizeof(IOMMUCC),
4274 /* .cbInstanceRC = */ sizeof(IOMMURC),
4275 /* .cMaxPciDevices = */ 1,
4276 /* .cMaxMsixVectors = */ 0,
4277 /* .pszDescription = */ "IOMMU (AMD)",
4278#if defined(IN_RING3)
4279 /* .pszRCMod = */ "VBoxDDRC.rc",
4280 /* .pszR0Mod = */ "VBoxDDR0.r0",
4281 /* .pfnConstruct = */ iommuAmdR3Construct,
4282 /* .pfnDestruct = */ iommuAmdR3Destruct,
4283 /* .pfnRelocate = */ NULL,
4284 /* .pfnMemSetup = */ NULL,
4285 /* .pfnPowerOn = */ NULL,
4286 /* .pfnReset = */ iommuAmdR3Reset,
4287 /* .pfnSuspend = */ NULL,
4288 /* .pfnResume = */ NULL,
4289 /* .pfnAttach = */ NULL,
4290 /* .pfnDetach = */ NULL,
4291 /* .pfnQueryInterface = */ NULL,
4292 /* .pfnInitComplete = */ NULL,
4293 /* .pfnPowerOff = */ NULL,
4294 /* .pfnSoftReset = */ NULL,
4295 /* .pfnReserved0 = */ NULL,
4296 /* .pfnReserved1 = */ NULL,
4297 /* .pfnReserved2 = */ NULL,
4298 /* .pfnReserved3 = */ NULL,
4299 /* .pfnReserved4 = */ NULL,
4300 /* .pfnReserved5 = */ NULL,
4301 /* .pfnReserved6 = */ NULL,
4302 /* .pfnReserved7 = */ NULL,
4303#elif defined(IN_RING0)
4304 /* .pfnEarlyConstruct = */ NULL,
4305 /* .pfnConstruct = */ iommuAmdRZConstruct,
4306 /* .pfnDestruct = */ NULL,
4307 /* .pfnFinalDestruct = */ NULL,
4308 /* .pfnRequest = */ NULL,
4309 /* .pfnReserved0 = */ NULL,
4310 /* .pfnReserved1 = */ NULL,
4311 /* .pfnReserved2 = */ NULL,
4312 /* .pfnReserved3 = */ NULL,
4313 /* .pfnReserved4 = */ NULL,
4314 /* .pfnReserved5 = */ NULL,
4315 /* .pfnReserved6 = */ NULL,
4316 /* .pfnReserved7 = */ NULL,
4317#elif defined(IN_RC)
4318 /* .pfnConstruct = */ iommuAmdRZConstruct,
4319 /* .pfnReserved0 = */ NULL,
4320 /* .pfnReserved1 = */ NULL,
4321 /* .pfnReserved2 = */ NULL,
4322 /* .pfnReserved3 = */ NULL,
4323 /* .pfnReserved4 = */ NULL,
4324 /* .pfnReserved5 = */ NULL,
4325 /* .pfnReserved6 = */ NULL,
4326 /* .pfnReserved7 = */ NULL,
4327#else
4328# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4329#endif
4330 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4331};
4332
4333#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4334
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