VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86209

Last change on this file since 86209 was 86209, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Nits.
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1/* $Id: DevIommuAmd.cpp 86209 2020-09-22 06:56:14Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31
32#include "VBoxDD.h"
33#include "DevIommuAmd.h"
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** Release log prefix string. */
40#define IOMMU_LOG_PFX "IOMMU-AMD"
41/** The current saved state version. */
42#define IOMMU_SAVED_STATE_VERSION 1
43/** The IOTLB entry magic. */
44#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46#ifndef DEBUG_ramshankar
47/** Temporary, make permanent later (get rid of define entirely and remove old
48 * code). This allow ssub-qword accesses to qword registers. Write accesses
49 * seems to work (needs testing one sub-path of the code), Read accesses not yet
50 * converted. */
51# define IOMMU_NEW_REGISTER_ACCESS
52#endif
53
54
55/*********************************************************************************************************************************
56* Structures and Typedefs *
57*********************************************************************************************************************************/
58/**
59 * Acquires the IOMMU PDM lock.
60 * This will make a long jump to ring-3 to acquire the lock if necessary.
61 */
62#define IOMMU_LOCK(a_pDevIns) \
63 do { \
64 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
65 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
66 { /* likely */ } \
67 else \
68 return rcLock; \
69 } while (0)
70
71/**
72 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
73 * This will make a long jump to ring-3 to acquire the lock if necessary.
74 */
75#define IOMMU_LOCK_NORET(a_pDevIns) \
76 do { \
77 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
78 AssertRC(rcLock); \
79 } while (0)
80
81/**
82 * Releases the IOMMU PDM lock.
83 */
84#define IOMMU_UNLOCK(a_pDevIns) \
85 do { \
86 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
87 } while (0)
88
89/**
90 * Asserts that the critsect is owned by this thread.
91 */
92#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
93 do { \
94 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95 } while (0)
96
97/**
98 * Asserts that the critsect is not owned by this thread.
99 */
100#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
101 do { \
102 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
103 } while (0)
104
105/**
106 * IOMMU operations (transaction) types.
107 */
108typedef enum IOMMUOP
109{
110 /** Address translation request. */
111 IOMMUOP_TRANSLATE_REQ = 0,
112 /** Memory read request. */
113 IOMMUOP_MEM_READ,
114 /** Memory write request. */
115 IOMMUOP_MEM_WRITE,
116 /** Interrupt request. */
117 IOMMUOP_INTR_REQ,
118 /** Command. */
119 IOMMUOP_CMD
120} IOMMUOP;
121AssertCompileSize(IOMMUOP, 4);
122
123/**
124 * I/O page walk result.
125 */
126typedef struct
127{
128 /** The translated system physical address. */
129 RTGCPHYS GCPhysSpa;
130 /** The number of offset bits in the system physical address. */
131 uint8_t cShift;
132 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
133 uint8_t fIoPerm;
134 /** Padding. */
135 uint8_t abPadding[2];
136} IOWALKRESULT;
137/** Pointer to an I/O walk result struct. */
138typedef IOWALKRESULT *PIOWALKRESULT;
139/** Pointer to a const I/O walk result struct. */
140typedef IOWALKRESULT *PCIOWALKRESULT;
141
142/**
143 * IOMMU I/O TLB Entry.
144 * Keep this as small and aligned as possible.
145 */
146typedef struct
147{
148 /** The translated system physical address (SPA) of the page. */
149 RTGCPHYS GCPhysSpa;
150 /** The index of the 4K page within a large page. */
151 uint32_t idxSubPage;
152 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
153 uint8_t fIoPerm;
154 /** The number of offset bits in the translation indicating page size. */
155 uint8_t cShift;
156 /** Alignment padding. */
157 uint8_t afPadding[2];
158} IOTLBE_T;
159AssertCompileSize(IOTLBE_T, 16);
160/** Pointer to an IOMMU I/O TLB entry struct. */
161typedef IOTLBE_T *PIOTLBE_T;
162/** Pointer to a const IOMMU I/O TLB entry struct. */
163typedef IOTLBE_T const *PCIOTLBE_T;
164
165/**
166 * The shared IOMMU device state.
167 */
168typedef struct IOMMU
169{
170 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
171 uint32_t idxIommu;
172 /** Alignment padding. */
173 uint32_t uPadding0;
174
175 /** Whether the command thread is sleeping. */
176 bool volatile fCmdThreadSleeping;
177 /** Alignment padding. */
178 uint8_t afPadding0[3];
179 /** Whether the command thread has been signaled for wake up. */
180 bool volatile fCmdThreadSignaled;
181 /** Alignment padding. */
182 uint8_t afPadding1[3];
183
184 /** The event semaphore the command thread waits on. */
185 SUPSEMEVENT hEvtCmdThread;
186 /** The MMIO handle. */
187 IOMMMIOHANDLE hMmio;
188
189 /** @name PCI: Base capability block registers.
190 * @{ */
191 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
192 /** @} */
193
194 /** @name MMIO: Control and status registers.
195 * @{ */
196 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
197 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
198 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
199 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
200 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
201 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
202 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
203 /** @} */
204
205 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
206 * @{ */
207 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
208 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
209 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
210 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
211 /** @} */
212
213 /** @todo IOMMU: SMI filter. */
214
215 /** @name MMIO: Guest Virtual-APIC Log registers.
216 * @{ */
217 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
218 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
219 /** @} */
220
221 /** @name MMIO: Alternate PPR and Event Log registers.
222 * @{ */
223 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
224 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
225 /** @} */
226
227 /** @name MMIO: Device-specific feature registers.
228 * @{ */
229 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
230 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
231 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
232 /** @} */
233
234 /** @name MMIO: MSI Capability Block registers.
235 * @{ */
236 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
237 /** @} */
238
239 /** @name MMIO: Performance Optimization Control registers.
240 * @{ */
241 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
242 /** @} */
243
244 /** @name MMIO: x2APIC Control registers.
245 * @{ */
246 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
247 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
248 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
249 /** @} */
250
251 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
252 * @{ */
253 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
254 /** @} */
255
256 /** @name MMIO: Reserved register.
257 * @{ */
258 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
259 /** @} */
260
261 /** @name MMIO: Command and Event Log pointer registers.
262 * @{ */
263 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
264 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
265 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
266 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
267 /** @} */
268
269 /** @name MMIO: Command and Event Status register.
270 * @{ */
271 IOMMU_STATUS_T Status; /**< IOMMU status register. */
272 /** @} */
273
274 /** @name MMIO: PPR Log Head and Tail pointer registers.
275 * @{ */
276 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
277 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
278 /** @} */
279
280 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
281 * @{ */
282 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
283 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
284 /** @} */
285
286 /** @name MMIO: PPR Log B Head and Tail pointer registers.
287 * @{ */
288 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
289 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
290 /** @} */
291
292 /** @name MMIO: Event Log B Head and Tail pointer registers.
293 * @{ */
294 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
295 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
296 /** @} */
297
298 /** @name MMIO: PPR Log Overflow protection registers.
299 * @{ */
300 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
301 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
302 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
303 /** @} */
304
305 /** @todo IOMMU: IOMMU Event counter registers. */
306
307#ifdef VBOX_WITH_STATISTICS
308 /** @name IOMMU: Stat counters.
309 * @{ */
310 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
311 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
312
313 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
314 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
315
316 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
317 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
318
319 STAMCOUNTER StatCmd; /**< Number of commands processed. */
320 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
321 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
322 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
323 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
324 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
325 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
326 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
327 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
328 /** @} */
329#endif
330} IOMMU;
331/** Pointer to the IOMMU device state. */
332typedef struct IOMMU *PIOMMU;
333/** Pointer to the const IOMMU device state. */
334typedef const struct IOMMU *PCIOMMU;
335AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
336AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
337AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
338AssertCompileMemberAlignment(IOMMU, hMmio, 8);
339AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
340
341/**
342 * The ring-3 IOMMU device state.
343 */
344typedef struct IOMMUR3
345{
346 /** Device instance. */
347 PPDMDEVINSR3 pDevInsR3;
348 /** The IOMMU helpers. */
349 PCPDMIOMMUHLPR3 pIommuHlpR3;
350 /** The command thread handle. */
351 R3PTRTYPE(PPDMTHREAD) pCmdThread;
352} IOMMUR3;
353/** Pointer to the ring-3 IOMMU device state. */
354typedef IOMMUR3 *PIOMMUR3;
355
356/**
357 * The ring-0 IOMMU device state.
358 */
359typedef struct IOMMUR0
360{
361 /** Device instance. */
362 PPDMDEVINSR0 pDevInsR0;
363 /** The IOMMU helpers. */
364 PCPDMIOMMUHLPR0 pIommuHlpR0;
365} IOMMUR0;
366/** Pointer to the ring-0 IOMMU device state. */
367typedef IOMMUR0 *PIOMMUR0;
368
369/**
370 * The raw-mode IOMMU device state.
371 */
372typedef struct IOMMURC
373{
374 /** Device instance. */
375 PPDMDEVINSR0 pDevInsRC;
376 /** The IOMMU helpers. */
377 PCPDMIOMMUHLPRC pIommuHlpRC;
378} IOMMURC;
379/** Pointer to the raw-mode IOMMU device state. */
380typedef IOMMURC *PIOMMURC;
381
382/** The IOMMU device state for the current context. */
383typedef CTX_SUFF(IOMMU) IOMMUCC;
384/** Pointer to the IOMMU device state for the current context. */
385typedef CTX_SUFF(PIOMMU) PIOMMUCC;
386
387/**
388 * IOMMU register access.
389 */
390typedef struct IOMMUREGACC
391{
392 const char *pszName;
393 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
394 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
395 uint8_t cb;
396} IOMMUREGACC;
397/** Pointer to an IOMMU register access. */
398typedef IOMMUREGACC *PIOMMUREGACC;
399/** Pointer to a const IOMMU register access. */
400typedef IOMMUREGACC const *PCIOMMUREGACC;
401
402
403/*********************************************************************************************************************************
404* Global Variables *
405*********************************************************************************************************************************/
406/**
407 * An array of the number of device table segments supported.
408 * Indexed by u2DevTabSegSup.
409 */
410static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
411
412/**
413 * An array of the masks to select the device table segment index from a device ID.
414 */
415static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
416
417/**
418 * An array of the shift values to select the device table segment index from a
419 * device ID.
420 */
421static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
422
423/**
424 * The maximum size (inclusive) of each device table segment (0 to 7).
425 * Indexed by the device table segment index.
426 */
427static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
428
429
430#ifndef VBOX_DEVICE_STRUCT_TESTCASE
431/**
432 * Gets the maximum number of buffer entries for the given buffer length.
433 *
434 * @returns Number of buffer entries.
435 * @param uEncodedLen The length (power-of-2 encoded).
436 */
437DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
438{
439 Assert(uEncodedLen > 7);
440 return 2 << (uEncodedLen - 1);
441}
442
443
444/**
445 * Gets the total length of the buffer given a base register's encoded length.
446 *
447 * @returns The length of the buffer in bytes.
448 * @param uEncodedLen The length (power-of-2 encoded).
449 */
450DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
451{
452 Assert(uEncodedLen > 7);
453 return (2 << (uEncodedLen - 1)) << 4;
454}
455
456
457/**
458 * Gets the number of (unconsumed) entries in the event log.
459 *
460 * @returns The number of entries in the event log.
461 * @param pThis The IOMMU device state.
462 */
463static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
464{
465 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
466 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
467 if (idxTail >= idxHead)
468 return idxTail - idxHead;
469
470 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
471 return cMaxEvts - idxHead + idxTail;
472}
473
474
475/**
476 * Gets the number of (unconsumed) commands in the command buffer.
477 *
478 * @returns The number of commands in the command buffer.
479 * @param pThis The IOMMU device state.
480 */
481static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
482{
483 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
484 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
485 if (idxTail >= idxHead)
486 return idxTail - idxHead;
487
488 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
489 return cMaxCmds - idxHead + idxTail;
490}
491
492
493DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
494{
495 IOMMU_STATUS_T Status;
496 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
497 return Status;
498}
499
500
501DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
502{
503 IOMMU_CTRL_T Ctrl;
504 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
505 return Ctrl;
506}
507
508
509/**
510 * Returns whether MSI is enabled for the IOMMU.
511 *
512 * @returns Whether MSI is enabled.
513 * @param pDevIns The IOMMU device instance.
514 *
515 * @note There should be a PCIDevXxx function for this.
516 */
517static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
518{
519 MSI_CAP_HDR_T MsiCapHdr;
520 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
521 return MsiCapHdr.n.u1MsiEnable;
522}
523
524
525/**
526 * Signals a PCI target abort.
527 *
528 * @param pDevIns The IOMMU device instance.
529 */
530static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
531{
532 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
533 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
534 PDMPciDevSetStatus(pPciDev, u16Status);
535}
536
537
538/**
539 * Wakes up the command thread if there are commands to be processed or if
540 * processing is requested to be stopped by software.
541 *
542 * @param pDevIns The IOMMU device instance.
543 */
544static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
545{
546 IOMMU_ASSERT_LOCKED(pDevIns);
547 Log5Func(("\n"));
548
549 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
550 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
551 if (Status.n.u1CmdBufRunning)
552 {
553 Log5Func(("Signaling command thread\n"));
554 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
555 }
556}
557
558
559/**
560 * Reads the Device Table Base Address Register.
561 */
562static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
563{
564 RT_NOREF(pDevIns, offReg);
565 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
566 return VINF_SUCCESS;
567}
568
569
570/**
571 * Reads the Command Buffer Base Address Register.
572 */
573static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
574{
575 RT_NOREF(pDevIns, offReg);
576 *pu64Value = pThis->CmdBufBaseAddr.u64;
577 return VINF_SUCCESS;
578}
579
580
581/**
582 * Reads the Event Log Base Address Register.
583 */
584static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
585{
586 RT_NOREF(pDevIns, offReg);
587 *pu64Value = pThis->EvtLogBaseAddr.u64;
588 return VINF_SUCCESS;
589}
590
591
592/**
593 * Reads the Control Register.
594 */
595static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
596{
597 RT_NOREF(pDevIns, offReg);
598 *pu64Value = pThis->Ctrl.u64;
599 return VINF_SUCCESS;
600}
601
602
603/**
604 * Reads the Exclusion Range Base Address Register.
605 */
606static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
607{
608 RT_NOREF(pDevIns, offReg);
609 *pu64Value = pThis->ExclRangeBaseAddr.u64;
610 return VINF_SUCCESS;
611}
612
613
614/**
615 * Reads to the Exclusion Range Limit Register.
616 */
617static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
618{
619 RT_NOREF(pDevIns, offReg);
620 *pu64Value = pThis->ExclRangeLimit.u64;
621 return VINF_SUCCESS;
622}
623
624
625/**
626 * Reads to the Extended Feature Register.
627 */
628static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
629{
630 RT_NOREF(pDevIns, offReg);
631 *pu64Value = pThis->ExtFeat.u64;
632 return VINF_SUCCESS;
633}
634
635
636/**
637 * Reads to the PPR Log Base Address Register.
638 */
639static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
640{
641 RT_NOREF(pDevIns, offReg);
642 *pu64Value = pThis->PprLogBaseAddr.u64;
643 return VINF_SUCCESS;
644}
645
646
647/**
648 * Writes the Hardware Event Register (Hi).
649 */
650static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
651{
652 RT_NOREF(pDevIns, offReg);
653 *pu64Value = pThis->HwEvtHi.u64;
654 return VINF_SUCCESS;
655}
656
657
658/**
659 * Reads the Hardware Event Register (Lo).
660 */
661static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
662{
663 RT_NOREF(pDevIns, offReg);
664 *pu64Value = pThis->HwEvtLo;
665 return VINF_SUCCESS;
666}
667
668
669/**
670 * Reads the Hardware Event Status Register.
671 */
672static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
673{
674 RT_NOREF(pDevIns, offReg);
675 *pu64Value = pThis->HwEvtStatus.u64;
676 return VINF_SUCCESS;
677}
678
679
680/**
681 * Reads to the GA Log Base Address Register.
682 */
683static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
684{
685 RT_NOREF(pDevIns, offReg);
686 *pu64Value = pThis->GALogBaseAddr.u64;
687 return VINF_SUCCESS;
688}
689
690
691/**
692 * Reads to the PPR Log B Base Address Register.
693 */
694static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
695{
696 RT_NOREF(pDevIns, offReg);
697 *pu64Value = pThis->PprLogBBaseAddr.u64;
698 return VINF_SUCCESS;
699}
700
701
702/**
703 * Reads to the Event Log B Base Address Register.
704 */
705static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
706{
707 RT_NOREF(pDevIns, offReg);
708 *pu64Value = pThis->EvtLogBBaseAddr.u64;
709 return VINF_SUCCESS;
710}
711
712
713/**
714 * Reads the Device Table Segment Base Address Register.
715 */
716static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
717{
718 RT_NOREF(pDevIns);
719
720 /* Figure out which segment is being written. */
721 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
722 uint8_t const idxSegment = offSegment + 1;
723 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
724
725 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
726 return VINF_SUCCESS;
727}
728
729
730/**
731 * Reads the Device Specific Feature Extension (DSFX) Register.
732 */
733static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
734{
735 RT_NOREF(pDevIns, offReg);
736 *pu64Value = pThis->DevSpecificFeat.u64;
737 return VINF_SUCCESS;
738}
739
740/**
741 * Reads the Device Specific Control Extension (DSCX) Register.
742 */
743static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
744{
745 RT_NOREF(pDevIns, offReg);
746 *pu64Value = pThis->DevSpecificCtrl.u64;
747 return VINF_SUCCESS;
748}
749
750
751/**
752 * Reads the Device Specific Status Extension (DSSX) Register.
753 */
754static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
755{
756 RT_NOREF(pDevIns, offReg);
757 *pu64Value = pThis->DevSpecificStatus.u64;
758 return VINF_SUCCESS;
759}
760
761
762/**
763 * Reads the MSI Vector Register 0 (32-bit) or the MSI Vector Register 1 (32-bit).
764 */
765static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
766{
767 RT_NOREF(pDevIns, offReg);
768 if (offReg == IOMMU_MMIO_OFF_MSI_VECTOR_0)
769 *pu64Value = pThis->MiscInfo.au32[0];
770 else
771 {
772 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_VECTOR_1, ("%#x\n", offReg));
773 *pu64Value = pThis->MiscInfo.au32[1];
774 }
775 return VINF_SUCCESS;
776}
777
778
779#ifdef IOMMU_NEW_REGISTER_ACCESS
780/**
781 * Reads the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
782 * Register (32-bit).
783 */
784static VBOXSTRICTRC iommuAmdMsiCapHdrOrAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
785{
786 RT_NOREF(pThis);
787 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
788 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
789 if (offReg == IOMMU_MMIO_OFF_MSI_CAP_HDR)
790 *pu64Value = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
791 else
792 {
793 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_ADDR_LO, ("%#x\n", offReg));
794 *pu64Value = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
795 }
796 return VINF_SUCCESS;
797}
798
799
800/**
801 * Reads the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
802 */
803static VBOXSTRICTRC iommuAmdMsiAddrHiOrData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
804{
805 RT_NOREF(pThis);
806 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
807 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
808
809 if (offReg == IOMMU_MMIO_OFF_MSI_ADDR_HI)
810 *pu64Value = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
811 else
812 {
813 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_DATA, ("%#x\n", offReg));
814 *pu64Value = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
815 }
816 return VINF_SUCCESS;
817}
818#endif
819
820/**
821 * Reads the Command Buffer Head Pointer Register.
822 */
823static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
824{
825 RT_NOREF(pDevIns, offReg);
826 *pu64Value = pThis->CmdBufHeadPtr.u64;
827 return VINF_SUCCESS;
828}
829
830
831/**
832 * Reads the Command Buffer Tail Pointer Register.
833 */
834static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
835{
836 RT_NOREF(pDevIns, offReg);
837 *pu64Value = pThis->CmdBufTailPtr.u64;
838 return VINF_SUCCESS;
839}
840
841
842/**
843 * Reads the Event Log Head Pointer Register.
844 */
845static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
846{
847 RT_NOREF(pDevIns, offReg);
848 *pu64Value = pThis->EvtLogHeadPtr.u64;
849 return VINF_SUCCESS;
850}
851
852
853/**
854 * Reads the Event Log Tail Pointer Register.
855 */
856static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
857{
858 RT_NOREF(pDevIns, offReg);
859 *pu64Value = pThis->EvtLogTailPtr.u64;
860 return VINF_SUCCESS;
861}
862
863
864/**
865 * Reads the Status Register.
866 */
867static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
868{
869 RT_NOREF(pDevIns, offReg);
870 *pu64Value = pThis->Status.u64;
871 return VINF_SUCCESS;
872}
873
874#ifndef IOMMU_NEW_REGISTER_ACCESS
875static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
876{
877 RT_NOREF(pDevIns, pThis, offReg, u64Value);
878 return VINF_SUCCESS;
879}
880#endif
881
882
883/**
884 * Writes the Device Table Base Address Register.
885 */
886static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
887{
888 RT_NOREF(pDevIns, offReg);
889
890 /* Mask out all unrecognized bits. */
891 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
892
893 /* Update the register. */
894 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
895 return VINF_SUCCESS;
896}
897
898
899/**
900 * Writes the Command Buffer Base Address Register.
901 */
902static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
903{
904 RT_NOREF(pDevIns, offReg);
905
906 /*
907 * While this is not explicitly specified like the event log base address register,
908 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
909 * Inconsistent specs :/
910 */
911 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
912 if (Status.n.u1CmdBufRunning)
913 {
914 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
915 return VINF_SUCCESS;
916 }
917
918 /* Mask out all unrecognized bits. */
919 CMD_BUF_BAR_T CmdBufBaseAddr;
920 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
921
922 /* Validate the length. */
923 if (CmdBufBaseAddr.n.u4Len >= 8)
924 {
925 /* Update the register. */
926 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
927
928 /*
929 * Writing the command buffer base address, clears the command buffer head and tail pointers.
930 * See AMD spec. 2.4 "Commands".
931 */
932 pThis->CmdBufHeadPtr.u64 = 0;
933 pThis->CmdBufTailPtr.u64 = 0;
934 }
935 else
936 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
937
938 return VINF_SUCCESS;
939}
940
941
942/**
943 * Writes the Event Log Base Address Register.
944 */
945static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
946{
947 RT_NOREF(pDevIns, offReg);
948
949 /*
950 * IOMMU behavior is undefined when software writes this register when event logging is running.
951 * In our emulation, we ignore the write entirely.
952 * See AMD IOMMU spec. "Event Log Base Address Register".
953 */
954 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
955 if (Status.n.u1EvtLogRunning)
956 {
957 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
958 return VINF_SUCCESS;
959 }
960
961 /* Mask out all unrecognized bits. */
962 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
963 EVT_LOG_BAR_T EvtLogBaseAddr;
964 EvtLogBaseAddr.u64 = u64Value;
965
966 /* Validate the length. */
967 if (EvtLogBaseAddr.n.u4Len >= 8)
968 {
969 /* Update the register. */
970 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
971
972 /*
973 * Writing the event log base address, clears the event log head and tail pointers.
974 * See AMD spec. 2.5 "Event Logging".
975 */
976 pThis->EvtLogHeadPtr.u64 = 0;
977 pThis->EvtLogTailPtr.u64 = 0;
978 }
979 else
980 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
981
982 return VINF_SUCCESS;
983}
984
985
986/**
987 * Writes the Control Register.
988 */
989static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
990{
991 RT_NOREF(pDevIns, offReg);
992
993 /* Mask out all unrecognized bits. */
994 u64Value &= IOMMU_CTRL_VALID_MASK;
995 IOMMU_CTRL_T NewCtrl;
996 NewCtrl.u64 = u64Value;
997
998 /* Ensure the device table segments are within limits. */
999 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
1000 {
1001 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
1002
1003 /* Update the register. */
1004 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
1005
1006 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
1007 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
1008
1009 /* Enable or disable event logging when the bit transitions. */
1010 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
1011 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1012 if ( fOldEvtLogEn != fNewEvtLogEn
1013 || fOldIommuEn != fNewIommuEn)
1014 {
1015 if ( fNewIommuEn
1016 && fNewEvtLogEn)
1017 {
1018 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1019 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1020 }
1021 else
1022 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1023 }
1024
1025 /* Enable or disable command buffer processing when the bit transitions. */
1026 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1027 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1028 if ( fOldCmdBufEn != fNewCmdBufEn
1029 || fOldIommuEn != fNewIommuEn)
1030 {
1031 if ( fNewCmdBufEn
1032 && fNewIommuEn)
1033 {
1034 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1035 LogFunc(("Command buffer enabled\n"));
1036
1037 /* Wake up the command thread to start processing commands. */
1038 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1039 }
1040 else
1041 {
1042 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1043 LogFunc(("Command buffer disabled\n"));
1044 }
1045 }
1046 }
1047 else
1048 {
1049 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1050 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1051 }
1052
1053 return VINF_SUCCESS;
1054}
1055
1056
1057/**
1058 * Writes to the Exclusion Range Base Address Register.
1059 */
1060static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1061{
1062 RT_NOREF(pDevIns, offReg);
1063 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1064 return VINF_SUCCESS;
1065}
1066
1067
1068/**
1069 * Writes to the Exclusion Range Limit Register.
1070 */
1071static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1072{
1073 RT_NOREF(pDevIns, offReg);
1074 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1075 u64Value |= UINT64_C(0xfff);
1076 pThis->ExclRangeLimit.u64 = u64Value;
1077 return VINF_SUCCESS;
1078}
1079
1080
1081/**
1082 * Writes the Hardware Event Register (Hi).
1083 */
1084static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1085{
1086 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1087 RT_NOREF(pDevIns, offReg);
1088 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1089 pThis->HwEvtHi.u64 = u64Value;
1090 return VINF_SUCCESS;
1091}
1092
1093
1094/**
1095 * Writes the Hardware Event Register (Lo).
1096 */
1097static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1098{
1099 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1100 RT_NOREF(pDevIns, offReg);
1101 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1102 pThis->HwEvtLo = u64Value;
1103 return VINF_SUCCESS;
1104}
1105
1106
1107/**
1108 * Writes the Hardware Event Status Register.
1109 */
1110static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1111{
1112 RT_NOREF(pDevIns, offReg);
1113
1114 /* Mask out all unrecognized bits. */
1115 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1116
1117 /*
1118 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1119 * If the current status bits or the bits being written are both 0, we've nothing to do.
1120 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1121 */
1122 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1123 if (!(HwStatus & RT_BIT(0)))
1124 return VINF_SUCCESS;
1125 if (u64Value & HwStatus & RT_BIT_64(0))
1126 HwStatus &= ~RT_BIT_64(0);
1127 if (u64Value & HwStatus & RT_BIT_64(1))
1128 HwStatus &= ~RT_BIT_64(1);
1129
1130 /* Update the register. */
1131 pThis->HwEvtStatus.u64 = HwStatus;
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/**
1137 * Writes the Device Table Segment Base Address Register.
1138 */
1139static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1140{
1141 RT_NOREF(pDevIns);
1142
1143 /* Figure out which segment is being written. */
1144 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1145 uint8_t const idxSegment = offSegment + 1;
1146 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1147
1148 /* Mask out all unrecognized bits. */
1149 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1150 DEV_TAB_BAR_T DevTabSegBar;
1151 DevTabSegBar.u64 = u64Value;
1152
1153 /* Validate the size. */
1154 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1155 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1156 if (uSegSize <= uMaxSegSize)
1157 {
1158 /* Update the register. */
1159 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1160 }
1161 else
1162 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1163
1164 return VINF_SUCCESS;
1165}
1166
1167
1168#ifndef IOMMU_NEW_REGISTER_ACCESS
1169/**
1170 * Writes the MSI Capability Header Register.
1171 */
1172static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1173{
1174 RT_NOREF(pThis, offReg);
1175 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1176 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1177 MSI_CAP_HDR_T MsiCapHdr;
1178 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1179 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1180 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1181 return VINF_SUCCESS;
1182}
1183
1184
1185/**
1186 * Writes the MSI Address (Lo) Register (32-bit).
1187 */
1188static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1189{
1190 RT_NOREF(pThis, offReg);
1191 Assert(!RT_HI_U32(u64Value));
1192 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1193 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1194 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
1195 return VINF_SUCCESS;
1196}
1197
1198
1199/**
1200 * Writes the MSI Address (Hi) Register (32-bit).
1201 */
1202static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1203{
1204 RT_NOREF(pThis, offReg);
1205 Assert(!RT_HI_U32(u64Value));
1206 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1207 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1208 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
1209 return VINF_SUCCESS;
1210}
1211
1212
1213/**
1214 * Writes the MSI Data Register (32-bit).
1215 */
1216static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1217{
1218 RT_NOREF(pThis, offReg);
1219 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1220 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1221 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
1222 return VINF_SUCCESS;
1223}
1224#else
1225/**
1226 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1227 * Register (32-bit).
1228 */
1229static VBOXSTRICTRC iommuAmdMsiCapHdrOrAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1230{
1231 RT_NOREF(pThis);
1232 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1233 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1234 if (offReg == IOMMU_MMIO_OFF_MSI_CAP_HDR)
1235 {
1236 /* MsiMultMessEn not supported, so only MsiEn is the writable bit. */
1237 MSI_CAP_HDR_T MsiCapHdr;
1238 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1239 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1240 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1241 }
1242 else
1243 {
1244 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_ADDR_LO, ("%#x\n", offReg));
1245 uint32_t const uMsiAddrLo = u64Value & VBOX_MSI_ADDR_VALID_MASK;
1246 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1247 }
1248 return VINF_SUCCESS;
1249}
1250
1251
1252/**
1253 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1254 */
1255static VBOXSTRICTRC iommuAmdMsiAddrHiOrData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1256{
1257 RT_NOREF(pThis);
1258 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1259 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1260 if (offReg == IOMMU_MMIO_OFF_MSI_ADDR_HI)
1261 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
1262 else
1263 {
1264 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_DATA, ("%#x\n", offReg));
1265 uint32_t const uMsiData = u64Value & VBOX_MSI_DATA_VALID_MASK;
1266 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1267 }
1268 return VINF_SUCCESS;
1269}
1270#endif
1271
1272
1273/**
1274 * Writes the Command Buffer Head Pointer Register.
1275 */
1276static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1277{
1278 RT_NOREF(pDevIns, offReg);
1279
1280 /*
1281 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1282 * In our emulation, we ignore the write entirely.
1283 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1284 */
1285 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1286 if (Status.n.u1CmdBufRunning)
1287 {
1288 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1289 return VINF_SUCCESS;
1290 }
1291
1292 /*
1293 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1294 * In our emulation, we ignore the write entirely.
1295 */
1296 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1297 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1298 Assert(cbBuf <= _512K);
1299 if (offBuf >= cbBuf)
1300 {
1301 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1302 return VINF_SUCCESS;
1303 }
1304
1305 /* Update the register. */
1306 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1307
1308 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1309
1310 Log5Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1311 return VINF_SUCCESS;
1312}
1313
1314
1315/**
1316 * Writes the Command Buffer Tail Pointer Register.
1317 */
1318static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1319{
1320 RT_NOREF(pDevIns, offReg);
1321
1322 /*
1323 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1324 * In our emulation, we ignore the write entirely.
1325 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1326 */
1327 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1328 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1329 Assert(cbBuf <= _512K);
1330 if (offBuf >= cbBuf)
1331 {
1332 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1333 return VINF_SUCCESS;
1334 }
1335
1336 /*
1337 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1338 * head pointer after adding one or more commands to the buffer.
1339 *
1340 * However, we cannot enforce this strictly because it's legal for software to shrink the
1341 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1342 * at 0). Software might even make the queue empty by making head and tail equal which is
1343 * allowed. I don't think we can or should try too hard to prevent software shooting itself
1344 * in the foot here. As long as we make sure the offset value is within the circular buffer
1345 * bounds (which we do by masking bits above) it should be sufficient.
1346 */
1347 pThis->CmdBufTailPtr.au32[0] = offBuf;
1348
1349 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1350
1351 Log5Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1352 return VINF_SUCCESS;
1353}
1354
1355
1356/**
1357 * Writes the Event Log Head Pointer Register.
1358 */
1359static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1360{
1361 RT_NOREF(pDevIns, offReg);
1362
1363 /*
1364 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1365 * In our emulation, we ignore the write entirely.
1366 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1367 */
1368 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1369 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1370 Assert(cbBuf <= _512K);
1371 if (offBuf >= cbBuf)
1372 {
1373 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1374 return VINF_SUCCESS;
1375 }
1376
1377 /* Update the register. */
1378 pThis->EvtLogHeadPtr.au32[0] = offBuf;
1379
1380 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1381 return VINF_SUCCESS;
1382}
1383
1384
1385/**
1386 * Writes the Event Log Tail Pointer Register.
1387 */
1388static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1389{
1390 RT_NOREF(pDevIns, offReg);
1391 NOREF(pThis);
1392
1393 /*
1394 * IOMMU behavior is undefined when software writes this register when the event log is running.
1395 * In our emulation, we ignore the write entirely.
1396 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1397 */
1398 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1399 if (Status.n.u1EvtLogRunning)
1400 {
1401 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1402 return VINF_SUCCESS;
1403 }
1404
1405 /*
1406 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1407 * In our emulation, we ignore the write entirely.
1408 */
1409 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1410 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1411 Assert(cbBuf <= _512K);
1412 if (offBuf >= cbBuf)
1413 {
1414 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1415 return VINF_SUCCESS;
1416 }
1417
1418 /* Update the register. */
1419 pThis->EvtLogTailPtr.au32[0] = offBuf;
1420
1421 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1422 return VINF_SUCCESS;
1423}
1424
1425
1426/**
1427 * Writes the Status Register.
1428 */
1429static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1430{
1431 RT_NOREF(pDevIns, offReg);
1432
1433 /* Mask out all unrecognized bits. */
1434 u64Value &= IOMMU_STATUS_VALID_MASK;
1435
1436 /*
1437 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1438 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1439 */
1440 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1441 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1442 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1443 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1444
1445 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1446
1447 /* Update the register. */
1448 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1449 return VINF_SUCCESS;
1450}
1451
1452#ifdef IOMMU_NEW_REGISTER_ACCESS
1453/**
1454 * Register access table 0.
1455 * The MMIO offset of each entry must be a multiple of 8!
1456 */
1457static const IOMMUREGACC g_aRegAccess0[] =
1458{
1459 /* MMIO off. Register name Read function Write function Reg. size */
1460 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w, 8 },
1461 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w, 8 },
1462 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w, 8 },
1463 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w, 8 },
1464 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w, 8 },
1465 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w, 8 },
1466 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL, 8 },
1467 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL, 8 },
1468 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w, 8 },
1469 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w, 8 },
1470 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w, 8 },
1471 { /* 0x58 */ NULL, NULL, NULL, 0 },
1472
1473 { /* 0x60 */ "SMI_FLT_0", NULL, NULL, 8 },
1474 { /* 0x68 */ "SMI_FLT_1", NULL, NULL, 8 },
1475 { /* 0x70 */ "SMI_FLT_2", NULL, NULL, 8 },
1476 { /* 0x78 */ "SMI_FLT_3", NULL, NULL, 8 },
1477 { /* 0x80 */ "SMI_FLT_4", NULL, NULL, 8 },
1478 { /* 0x88 */ "SMI_FLT_5", NULL, NULL, 8 },
1479 { /* 0x90 */ "SMI_FLT_6", NULL, NULL, 8 },
1480 { /* 0x98 */ "SMI_FLT_7", NULL, NULL, 8 },
1481 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL, 8 },
1482 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL, 8 },
1483 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL, 8 },
1484 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL, 8 },
1485 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL, 8 },
1486 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL, 8 },
1487 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL, 8 },
1488 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL, 8 },
1489
1490 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL, 8 },
1491 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL, 8 },
1492 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL, 8 },
1493 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL, 8 },
1494
1495 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1496 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1497 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1498 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1499 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1500 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1501 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1502
1503 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL, 8 },
1504 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL, 8 },
1505 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL, 8 },
1506
1507 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, NULL, 4 },
1508 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrOrAddrLo_r, iommuAmdMsiCapHdrOrAddrLo_w, 4 },
1509 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiOrData_r, iommuAmdMsiAddrHiOrData_w, 4 },
1510 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL, 4 },
1511
1512 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL, 8 },
1513 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL, 8 },
1514 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL, 8 },
1515};
1516AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1517
1518/**
1519 * Register access table 1.
1520 * The MMIO offset of each entry must be a multiple of 8!
1521 */
1522static const IOMMUREGACC g_aRegAccess1[] =
1523{
1524 /* MMIO offset Register name Read function Write function Register size. */
1525 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL, 8 },
1526 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL, 8 },
1527 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL, 8 },
1528 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL, 8 },
1529 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL, 8 },
1530 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL, 8 },
1531 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL, 8 },
1532 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL, 8 },
1533 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL, 8 },
1534 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL, 8 },
1535 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL, 8 },
1536 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL, 8 }
1537};
1538AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1539
1540/**
1541 * Register access table 2.
1542 * The MMIO offset of each entry must be a multiple of 8!
1543 */
1544static const IOMMUREGACC g_aRegAccess2[] =
1545{
1546 /* MMIO offset Register name Read Function Write function Register size (bytes) */
1547 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL, 8 },
1548
1549 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w, 8 },
1550 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w, 8 },
1551 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w, 8 },
1552 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w, 8 },
1553
1554 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w, 8 },
1555 { /* 0x2028 */ NULL, NULL, NULL, 0 },
1556
1557 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL, 8 },
1558 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL, 8 },
1559
1560 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL, 8 },
1561 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL, 8 },
1562
1563 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL, 8 },
1564 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL, 8 },
1565
1566 { /* 0x2060 */ NULL, NULL, NULL, 0 },
1567 { /* 0x2068 */ NULL, NULL, NULL, 0 },
1568
1569 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL, 8 },
1570 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL, 8 },
1571
1572 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL, 8 },
1573 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL, 8 },
1574 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL, 8 }
1575};
1576AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1577#endif
1578
1579
1580/**
1581 * Writes an IOMMU register (32-bit and 64-bit).
1582 *
1583 * @returns Strict VBox status code.
1584 * @param pDevIns The IOMMU device instance.
1585 * @param off MMIO byte offset to the register.
1586 * @param cb The size of the write access.
1587 * @param uValue The value being written.
1588 *
1589 * @thread EMT.
1590 */
1591static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1592{
1593 /*
1594 * Validate the access in case of IOM bug or incorrect assumption.
1595 */
1596 Assert(off < IOMMU_MMIO_REGION_SIZE);
1597 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1598 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1599
1600 Log5Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1601
1602 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1603#ifndef IOMMU_NEW_REGISTER_ACCESS
1604 switch (off)
1605 {
1606 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1607 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1608 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1609 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1610 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1611 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1612 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1613
1614 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1615 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1616 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1617 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1618
1619 case IOMMU_MMIO_OFF_GALOG_BAR:
1620 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1621
1622 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1623 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1624
1625 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1626 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1627 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1628 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1629 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1630 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1631 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1632
1633 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1634 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1635 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1636
1637 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1638 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1639 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1640 {
1641 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1642 if (cb == 4 || RT_FAILURE(rcStrict))
1643 return rcStrict;
1644 uValue >>= 32;
1645 RT_FALL_THRU();
1646 }
1647 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1648 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1649 {
1650 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1651 if (cb == 4 || RT_FAILURE(rcStrict))
1652 return rcStrict;
1653 uValue >>= 32;
1654 RT_FALL_THRU();
1655 }
1656 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1657 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1658
1659 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1660
1661 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1662 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1663 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1664
1665 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1666 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1667 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1668 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1669 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1670 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1671 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1672 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1673 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1674 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1675 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1676 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1677
1678 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1679
1680 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1681 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1682 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1683 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1684
1685 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1686
1687 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1688 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1689
1690 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1691 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1692
1693 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1694 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1695
1696 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1697 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1698
1699 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1700 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1701 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1702
1703 /* Not implemented. */
1704 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1705 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1706 {
1707 LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1708 return VINF_SUCCESS;
1709 }
1710
1711 /* Unknown. */
1712 default:
1713 {
1714 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1715 return VINF_SUCCESS;
1716 }
1717 }
1718#else
1719 /*
1720 * Figure out which table the register belongs to and validate its index.
1721 */
1722 PCIOMMUREGACC pReg;
1723 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1724 {
1725 uint32_t const idxReg = off >> 3;
1726 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1727 pReg = &g_aRegAccess0[idxReg];
1728 }
1729 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1730 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1731 {
1732 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1733 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1734 pReg = &g_aRegAccess1[idxReg];
1735 }
1736 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1737 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1738 {
1739 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1740 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1741 pReg = &g_aRegAccess2[idxReg];
1742 }
1743 else
1744 {
1745 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1746 return VINF_SUCCESS;
1747 }
1748
1749 /*
1750 * Ensure the register is writable and proceed.
1751 * If a write handler doesn't exist, it's either a reserved or read-only register.
1752 */
1753 if (pReg->pfnWrite)
1754 {
1755 /*
1756 * If the write access is aligned and matches the register size, dispatch right away.
1757 * This handles all aligned, 32-bit writes as well as aligned 64-bit writes.
1758 */
1759 if ( cb == pReg->cb
1760 && !(off & (cb - 1)))
1761 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1762
1763 /*
1764 * A 32-bit write for a 64-bit register.
1765 * We shouldn't get sizes other than 32 bits here as we've specified so with IOM.
1766 */
1767 Assert(cb == 4);
1768 if (!(off & 7))
1769 {
1770 /*
1771 * Lower 32 bits of the register is being written.
1772 * Merge with higher 32 bits (after reading the full value from the register).
1773 */
1774 uint64_t u64Read;
1775 if (pReg->pfnRead)
1776 {
1777 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1778 if (RT_FAILURE(rcStrict))
1779 {
1780 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1781 return rcStrict;
1782 }
1783 }
1784 else
1785 u64Read = 0;
1786
1787 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
1788 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1789 }
1790
1791 /*
1792 * Higher 32 bits of the register is being written.
1793 * Merge with lower 32 bits (after reading the full value from the register).
1794 */
1795 Assert(!(off & 3));
1796 Assert(off & 7);
1797 Assert(off > 4);
1798 uint64_t u64Read;
1799 if (pReg->pfnRead)
1800 {
1801 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1802 if (RT_FAILURE(rcStrict))
1803 {
1804 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1805 return rcStrict;
1806 }
1807 }
1808 else
1809 u64Read = 0;
1810
1811 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
1812 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1813 }
1814 else
1815 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1816
1817 return VINF_SUCCESS;
1818#endif
1819}
1820
1821
1822/**
1823 * Reads an IOMMU register (64-bit) given its MMIO offset.
1824 *
1825 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1826 * boundary include the lower half of the subsequent register.
1827 *
1828 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1829 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1830 * software will only perform 32-bit reads on those 32-bit registers that are
1831 * aligned on 8-byte boundaries.
1832 *
1833 * @returns Strict VBox status code.
1834 * @param pDevIns The IOMMU device instance.
1835 * @param off The MMIO offset of the register in bytes.
1836 * @param puResult Where to store the value being read.
1837 *
1838 * @thread EMT.
1839 */
1840static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1841{
1842 Assert(off < IOMMU_MMIO_REGION_SIZE);
1843 Assert(!(off & 7) || !(off & 3));
1844
1845 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1846 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1847 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1848
1849 Log5Func(("off=%#x\n", off));
1850
1851 /** @todo IOMMU: fine-grained locking? */
1852 uint64_t uReg;
1853 switch (off)
1854 {
1855 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1856 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1857 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1858 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1859 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1860 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1861 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1862
1863 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1864 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1865 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1866 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1867
1868 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1869 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1870
1871 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1872 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1873
1874 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1875 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1876 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1877 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1878 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1879 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1880 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1881 {
1882 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1883 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1884 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1885 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1886 break;
1887 }
1888
1889 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1890 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1891 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1892
1893 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1894 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1895 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1896 {
1897 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1898 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1899 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1900 break;
1901 }
1902 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1903 {
1904 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1905 break;
1906 }
1907 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1908 {
1909 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1910 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1911 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1912 break;
1913 }
1914 case IOMMU_MMIO_OFF_MSI_DATA:
1915 {
1916 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1917 break;
1918 }
1919 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1920 {
1921 /*
1922 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1923 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1924 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1925 * 0 for this register.
1926 */
1927 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1928 break;
1929 }
1930
1931 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1932
1933 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1934 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1935 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1936
1937 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1938 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1939 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1940 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1941 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1942 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1943 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1944 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1945 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1946 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1947 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1948 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1949
1950 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1951
1952 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1953 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1954 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1955 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1956
1957 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
1958
1959 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
1960 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
1961
1962 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
1963 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
1964
1965 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
1966 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
1967
1968 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
1969 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
1970
1971 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
1972 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
1973 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
1974
1975 /* Not implemented. */
1976 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1977 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1978 {
1979 LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1980 uReg = 0;
1981 break;
1982 }
1983
1984 /* Unknown. */
1985 default:
1986 {
1987 LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
1988 uReg = 0;
1989 return VINF_IOM_MMIO_UNUSED_00;
1990 }
1991 }
1992
1993 *puResult = uReg;
1994 return VINF_SUCCESS;
1995}
1996
1997
1998/**
1999 * Raises the MSI interrupt for the IOMMU device.
2000 *
2001 * @param pDevIns The IOMMU device instance.
2002 *
2003 * @thread Any.
2004 * @remarks The IOMMU lock may or may not be held.
2005 */
2006static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
2007{
2008 LogFlowFunc(("\n"));
2009 if (iommuAmdIsMsiEnabled(pDevIns))
2010 {
2011 LogFunc(("Raising MSI\n"));
2012 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2013 }
2014}
2015
2016
2017/**
2018 * Clears the MSI interrupt for the IOMMU device.
2019 *
2020 * @param pDevIns The IOMMU device instance.
2021 *
2022 * @thread Any.
2023 * @remarks The IOMMU lock may or may not be held.
2024 */
2025static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
2026{
2027 if (iommuAmdIsMsiEnabled(pDevIns))
2028 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2029}
2030
2031
2032/**
2033 * Writes an entry to the event log in memory.
2034 *
2035 * @returns VBox status code.
2036 * @param pDevIns The IOMMU device instance.
2037 * @param pEvent The event to log.
2038 *
2039 * @thread Any.
2040 */
2041static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2042{
2043 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2044
2045 IOMMU_ASSERT_LOCKED(pDevIns);
2046
2047 /* Check if event logging is active and the log has not overflowed. */
2048 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2049 if ( Status.n.u1EvtLogRunning
2050 && !Status.n.u1EvtOverflow)
2051 {
2052 uint32_t const cbEvt = sizeof(*pEvent);
2053
2054 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2055 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2056 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2057
2058 /* Ensure we have space in the event log. */
2059 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2060 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2061 if (cEvts + 1 < cMaxEvts)
2062 {
2063 /* Write the event log entry to memory. */
2064 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2065 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2066 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2067 if (RT_FAILURE(rc))
2068 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2069
2070 /* Increment the event log tail pointer. */
2071 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2072 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2073
2074 /* Indicate that an event log entry was written. */
2075 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2076
2077 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2078 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2079 if (Ctrl.n.u1EvtIntrEn)
2080 iommuAmdRaiseMsiInterrupt(pDevIns);
2081 }
2082 else
2083 {
2084 /* Indicate that the event log has overflowed. */
2085 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2086
2087 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2088 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2089 if (Ctrl.n.u1EvtIntrEn)
2090 iommuAmdRaiseMsiInterrupt(pDevIns);
2091 }
2092 }
2093
2094 return VINF_SUCCESS;
2095}
2096
2097
2098/**
2099 * Sets an event in the hardware error registers.
2100 *
2101 * @param pDevIns The IOMMU device instance.
2102 * @param pEvent The event.
2103 *
2104 * @thread Any.
2105 */
2106static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2107{
2108 IOMMU_ASSERT_LOCKED(pDevIns);
2109
2110 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2111 if (pThis->ExtFeat.n.u1HwErrorSup)
2112 {
2113 if (pThis->HwEvtStatus.n.u1Valid)
2114 pThis->HwEvtStatus.n.u1Overflow = 1;
2115 pThis->HwEvtStatus.n.u1Valid = 1;
2116 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2117 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2118 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2119 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2120 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2121 }
2122}
2123
2124
2125/**
2126 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2127 *
2128 * @param uDevId The device ID.
2129 * @param uDomainId The domain ID.
2130 * @param GCPhysPtEntity The system physical address of the page table
2131 * entity.
2132 * @param enmOp The IOMMU operation being performed.
2133 * @param pEvtPageTabHwErr Where to store the initialized event.
2134 */
2135static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2136 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2137{
2138 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2139 pEvtPageTabHwErr->n.u16DevId = uDevId;
2140 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
2141 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
2142 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2143 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2144 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2145 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2146 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
2147 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
2148}
2149
2150
2151/**
2152 * Raises a PAGE_TAB_HARDWARE_ERROR event.
2153 *
2154 * @param pDevIns The IOMMU device instance.
2155 * @param enmOp The IOMMU operation being performed.
2156 * @param pEvtPageTabHwErr The page table hardware error event.
2157 *
2158 * @thread Any.
2159 */
2160static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2161{
2162 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
2163 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
2164
2165 IOMMU_LOCK_NORET(pDevIns);
2166
2167 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2168 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2169 if (enmOp != IOMMUOP_CMD)
2170 iommuAmdSetPciTargetAbort(pDevIns);
2171
2172 IOMMU_UNLOCK(pDevIns);
2173
2174 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
2175 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
2176 pEvtPageTabHwErr->n.u2Type));
2177}
2178
2179
2180/**
2181 * Initializes a COMMAND_HARDWARE_ERROR event.
2182 *
2183 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
2184 * @param pEvtCmdHwErr Where to store the initialized event.
2185 */
2186static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2187{
2188 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
2189 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
2190 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
2191 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
2192}
2193
2194
2195/**
2196 * Raises a COMMAND_HARDWARE_ERROR event.
2197 *
2198 * @param pDevIns The IOMMU device instance.
2199 * @param pEvtCmdHwErr The command hardware error event.
2200 *
2201 * @thread Any.
2202 */
2203static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2204{
2205 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
2206 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
2207 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2208
2209 IOMMU_LOCK_NORET(pDevIns);
2210
2211 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2212 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2213 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2214
2215 IOMMU_UNLOCK(pDevIns);
2216
2217 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
2218}
2219
2220
2221/**
2222 * Initializes a DEV_TAB_HARDWARE_ERROR event.
2223 *
2224 * @param uDevId The device ID.
2225 * @param GCPhysDte The system physical address of the failed device table
2226 * access.
2227 * @param enmOp The IOMMU operation being performed.
2228 * @param pEvtDevTabHwErr Where to store the initialized event.
2229 */
2230static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
2231 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2232{
2233 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
2234 pEvtDevTabHwErr->n.u16DevId = uDevId;
2235 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2236 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
2237 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2238 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2239 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2240 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
2241 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
2242}
2243
2244
2245/**
2246 * Raises a DEV_TAB_HARDWARE_ERROR event.
2247 *
2248 * @param pDevIns The IOMMU device instance.
2249 * @param enmOp The IOMMU operation being performed.
2250 * @param pEvtDevTabHwErr The device table hardware error event.
2251 *
2252 * @thread Any.
2253 */
2254static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2255{
2256 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2257 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2258
2259 IOMMU_LOCK_NORET(pDevIns);
2260
2261 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2262 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2263 if (enmOp != IOMMUOP_CMD)
2264 iommuAmdSetPciTargetAbort(pDevIns);
2265
2266 IOMMU_UNLOCK(pDevIns);
2267
2268 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2269 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2270}
2271
2272
2273/**
2274 * Initializes an ILLEGAL_COMMAND_ERROR event.
2275 *
2276 * @param GCPhysCmd The system physical address of the failed command
2277 * access.
2278 * @param pEvtIllegalCmd Where to store the initialized event.
2279 */
2280static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2281{
2282 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2283 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2284 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2285 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2286}
2287
2288
2289/**
2290 * Raises an ILLEGAL_COMMAND_ERROR event.
2291 *
2292 * @param pDevIns The IOMMU device instance.
2293 * @param pEvtIllegalCmd The illegal command error event.
2294 */
2295static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2296{
2297 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2298 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2299 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2300
2301 IOMMU_LOCK_NORET(pDevIns);
2302
2303 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2304 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2305
2306 IOMMU_UNLOCK(pDevIns);
2307
2308 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2309}
2310
2311
2312/**
2313 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2314 *
2315 * @param uDevId The device ID.
2316 * @param uIova The I/O virtual address.
2317 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2318 * event was caused by an invalid level encoding in the
2319 * DTE.
2320 * @param enmOp The IOMMU operation being performed.
2321 * @param pEvtIllegalDte Where to store the initialized event.
2322 */
2323static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2324 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2325{
2326 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2327 pEvtIllegalDte->n.u16DevId = uDevId;
2328 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2329 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2330 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2331 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2332 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2333 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2334 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2335 * IOMMU spec here but not for this field for I/O page fault event. */
2336 Assert(!(uIova & UINT64_C(0x3)));
2337}
2338
2339
2340/**
2341 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2342 *
2343 * @param pDevIns The IOMMU instance data.
2344 * @param enmOp The IOMMU operation being performed.
2345 * @param pEvtIllegalDte The illegal device table entry event.
2346 * @param enmEvtType The illegal device table entry event type.
2347 *
2348 * @thread Any.
2349 */
2350static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2351 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2352{
2353 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2354 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2355
2356 IOMMU_LOCK_NORET(pDevIns);
2357
2358 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2359 if (enmOp != IOMMUOP_CMD)
2360 iommuAmdSetPciTargetAbort(pDevIns);
2361
2362 IOMMU_UNLOCK(pDevIns);
2363
2364 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2365 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2366 NOREF(enmEvtType);
2367}
2368
2369
2370/**
2371 * Initializes an IO_PAGE_FAULT event.
2372 *
2373 * @param uDevId The device ID.
2374 * @param uDomainId The domain ID.
2375 * @param uIova The I/O virtual address being accessed.
2376 * @param fPresent Transaction to a page marked as present (including
2377 * DTE.V=1) or interrupt marked as remapped
2378 * (IRTE.RemapEn=1).
2379 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2380 * the I/O page fault was caused by invalid level
2381 * encoding.
2382 * @param fPermDenied Permission denied for the address being accessed.
2383 * @param enmOp The IOMMU operation being performed.
2384 * @param pEvtIoPageFault Where to store the initialized event.
2385 */
2386static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2387 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2388{
2389 Assert(!fPermDenied || fPresent);
2390 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2391 pEvtIoPageFault->n.u16DevId = uDevId;
2392 //pEvtIoPageFault->n.u4PasidHi = 0;
2393 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2394 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2395 //pEvtIoPageFault->n.u1NoExecute = 0;
2396 //pEvtIoPageFault->n.u1User = 0;
2397 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2398 pEvtIoPageFault->n.u1Present = fPresent;
2399 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2400 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2401 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2402 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2403 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2404 pEvtIoPageFault->n.u64Addr = uIova;
2405}
2406
2407
2408/**
2409 * Raises an IO_PAGE_FAULT event.
2410 *
2411 * @param pDevIns The IOMMU instance data.
2412 * @param pDte The device table entry. Optional, can be NULL
2413 * depending on @a enmOp.
2414 * @param pIrte The interrupt remapping table entry. Optional, can
2415 * be NULL depending on @a enmOp.
2416 * @param enmOp The IOMMU operation being performed.
2417 * @param pEvtIoPageFault The I/O page fault event.
2418 * @param enmEvtType The I/O page fault event type.
2419 *
2420 * @thread Any.
2421 */
2422static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2423 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2424{
2425 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2426 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2427
2428 IOMMU_LOCK_NORET(pDevIns);
2429
2430 bool fSuppressEvtLogging = false;
2431 if ( enmOp == IOMMUOP_MEM_READ
2432 || enmOp == IOMMUOP_MEM_WRITE)
2433 {
2434 if ( pDte
2435 && pDte->n.u1Valid)
2436 {
2437 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2438 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2439 * suppression. Perhaps will be possible when we complete IOTLB/cache
2440 * handling. */
2441 }
2442 }
2443 else if (enmOp == IOMMUOP_INTR_REQ)
2444 {
2445 if ( pDte
2446 && pDte->n.u1IntrMapValid)
2447 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2448
2449 if ( !fSuppressEvtLogging
2450 && pIrte)
2451 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2452 }
2453 /* else: Events are never suppressed for commands. */
2454
2455 switch (enmEvtType)
2456 {
2457 case kIoPageFaultType_PermDenied:
2458 {
2459 /* Cannot be triggered by a command. */
2460 Assert(enmOp != IOMMUOP_CMD);
2461 RT_FALL_THRU();
2462 }
2463 case kIoPageFaultType_DteRsvdPagingMode:
2464 case kIoPageFaultType_PteInvalidPageSize:
2465 case kIoPageFaultType_PteInvalidLvlEncoding:
2466 case kIoPageFaultType_SkippedLevelIovaNotZero:
2467 case kIoPageFaultType_PteRsvdNotZero:
2468 case kIoPageFaultType_PteValidNotSet:
2469 case kIoPageFaultType_DteTranslationDisabled:
2470 case kIoPageFaultType_PasidInvalidRange:
2471 {
2472 /*
2473 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2474 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
2475 */
2476 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2477 {
2478 if (!fSuppressEvtLogging)
2479 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2480 if (enmOp != IOMMUOP_CMD)
2481 iommuAmdSetPciTargetAbort(pDevIns);
2482 }
2483 break;
2484 }
2485
2486 case kIoPageFaultType_UserSupervisor:
2487 {
2488 /* Access is blocked and only creates an event log entry. */
2489 if (!fSuppressEvtLogging)
2490 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2491 break;
2492 }
2493
2494 case kIoPageFaultType_IrteAddrInvalid:
2495 case kIoPageFaultType_IrteRsvdNotZero:
2496 case kIoPageFaultType_IrteRemapEn:
2497 case kIoPageFaultType_IrteRsvdIntType:
2498 case kIoPageFaultType_IntrReqAborted:
2499 case kIoPageFaultType_IntrWithPasid:
2500 {
2501 /* Only trigerred by interrupt requests. */
2502 Assert(enmOp == IOMMUOP_INTR_REQ);
2503 if (!fSuppressEvtLogging)
2504 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2505 iommuAmdSetPciTargetAbort(pDevIns);
2506 break;
2507 }
2508
2509 case kIoPageFaultType_SmiFilterMismatch:
2510 {
2511 /* Not supported and probably will never be, assert. */
2512 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2513 break;
2514 }
2515
2516 case kIoPageFaultType_DevId_Invalid:
2517 {
2518 /* Cannot be triggered by a command. */
2519 Assert(enmOp != IOMMUOP_CMD);
2520 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2521 if (!fSuppressEvtLogging)
2522 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2523 if ( enmOp == IOMMUOP_MEM_READ
2524 || enmOp == IOMMUOP_MEM_WRITE)
2525 iommuAmdSetPciTargetAbort(pDevIns);
2526 break;
2527 }
2528 }
2529
2530 IOMMU_UNLOCK(pDevIns);
2531}
2532
2533
2534/**
2535 * Returns whether the I/O virtual address is to be excluded from translation and
2536 * permission checks.
2537 *
2538 * @returns @c true if the DVA is excluded, @c false otherwise.
2539 * @param pThis The IOMMU device state.
2540 * @param pDte The device table entry.
2541 * @param uIova The I/O virtual address.
2542 *
2543 * @remarks Ensure the exclusion range is enabled prior to calling this function.
2544 *
2545 * @thread Any.
2546 */
2547static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2548{
2549 /* Ensure the exclusion range is enabled. */
2550 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2551
2552 /* Check if the IOVA falls within the exclusion range. */
2553 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2554 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2555 if (uIovaExclLast - uIova >= uIovaExclFirst)
2556 {
2557 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2558 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2559 || pDte->n.u1AllowExclusion)
2560 return true;
2561 }
2562 return false;
2563}
2564
2565
2566/**
2567 * Reads a device table entry from guest memory given the device ID.
2568 *
2569 * @returns VBox status code.
2570 * @param pDevIns The IOMMU device instance.
2571 * @param uDevId The device ID.
2572 * @param enmOp The IOMMU operation being performed.
2573 * @param pDte Where to store the device table entry.
2574 *
2575 * @thread Any.
2576 */
2577static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2578{
2579 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2580 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2581
2582 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2583 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2584 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
2585
2586 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2587 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2588
2589 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2590 uint16_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2591 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2592
2593 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2594 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2595 if (RT_FAILURE(rc))
2596 {
2597 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2598
2599 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2600 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2601 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2602 return VERR_IOMMU_IPE_1;
2603 }
2604
2605 return rc;
2606}
2607
2608
2609/**
2610 * Walks the I/O page table to translate the I/O virtual address to a system
2611 * physical address.
2612 *
2613 * @returns VBox status code.
2614 * @param pDevIns The IOMMU device instance.
2615 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2616 * @param uDevId The device ID.
2617 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2618 * permissions for the access being made.
2619 * @param pDte The device table entry.
2620 * @param enmOp The IOMMU operation being performed.
2621 * @param pWalkResult Where to store the results of the I/O page walk. This is
2622 * only updated when VINF_SUCCESS is returned.
2623 *
2624 * @thread Any.
2625 */
2626static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2627 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2628{
2629 Assert(pDte->n.u1Valid);
2630 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2631
2632 /* If the translation is not valid, raise an I/O page fault. */
2633 if (pDte->n.u1TranslationValid)
2634 { /* likely */ }
2635 else
2636 {
2637 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2638 * doesn't explicitly say whether an I/O page fault is raised. From other
2639 * places in the spec. it seems early page walk terminations (starting with
2640 * the DTE) return the state computed so far and raises an I/O page fault. So
2641 * returning an invalid translation rather than skipping translation. */
2642 LogFunc(("Translation valid bit not set -> IOPF\n"));
2643 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2644 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2645 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2646 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2647 kIoPageFaultType_DteTranslationDisabled);
2648 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2649 }
2650
2651 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2652 uint8_t const uMaxLevel = pDte->n.u3Mode;
2653 if (uMaxLevel != 0)
2654 { /* likely */ }
2655 else
2656 {
2657 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2658 if ((fAccess & fDtePerm) != fAccess)
2659 {
2660 LogFunc(("Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
2661 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2662 }
2663 pWalkResult->GCPhysSpa = uIova;
2664 pWalkResult->cShift = 0;
2665 pWalkResult->fIoPerm = fDtePerm;
2666 return VINF_SUCCESS;
2667 }
2668
2669 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2670 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2671 { /* likely */ }
2672 else
2673 {
2674 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2675 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2676 * I'm just going with I/O page fault. */
2677 LogFunc(("Invalid root page table level %#x -> IOPF\n", uMaxLevel));
2678 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2679 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2680 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2681 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2682 kIoPageFaultType_PteInvalidLvlEncoding);
2683 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2684 }
2685
2686 /* Check permissions bits of the root page table. */
2687 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2688 if ((fAccess & fRootPtePerm) == fAccess)
2689 { /* likely */ }
2690 else
2691 {
2692 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2693 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2694 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2695 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2696 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2697 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2698 }
2699
2700 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2701 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2702 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2703 * table entry every time. Not sure if it's worth optimizing that case now
2704 * or if at all. */
2705
2706 /* The virtual address bits indexing table. */
2707 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2708 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2709 UINT64_C(0x00000000001ff000),
2710 UINT64_C(0x000000003fe00000),
2711 UINT64_C(0x0000007fc0000000),
2712 UINT64_C(0x0000ff8000000000),
2713 UINT64_C(0x01ff000000000000),
2714 UINT64_C(0xfe00000000000000),
2715 UINT64_C(0x0000000000000000) };
2716 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2717 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2718
2719 /* Traverse the I/O page table starting with the page directory in the DTE. */
2720 IOPTENTITY_T PtEntity;
2721 PtEntity.u64 = pDte->au64[0];
2722 for (;;)
2723 {
2724 /* Figure out the system physical address of the page table at the current level. */
2725 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2726
2727 /* Read the page table entity at the current level. */
2728 {
2729 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2730 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2731 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2732 uint64_t const offPte = idxPte << 3;
2733 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2734 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2735 if (RT_FAILURE(rc))
2736 {
2737 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2738 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2739 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2740 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2741 return VERR_IOMMU_IPE_2;
2742 }
2743 }
2744
2745 /* Check present bit. */
2746 if (PtEntity.n.u1Present)
2747 { /* likely */ }
2748 else
2749 {
2750 LogFunc(("Page table entry not present -> IOPF\n"));
2751 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2752 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2753 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2754 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2755 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2756 }
2757
2758 /* Check permission bits. */
2759 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2760 if ((fAccess & fPtePerm) == fAccess)
2761 { /* likely */ }
2762 else
2763 {
2764 LogFunc(("Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF\n", fAccess, fPtePerm));
2765 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2766 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2767 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2768 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2769 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2770 }
2771
2772 /* If this is a PTE, we're at the final level and we're done. */
2773 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2774 if (uNextLevel == 0)
2775 {
2776 /* The page size of the translation is the default (4K). */
2777 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2778 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2779 pWalkResult->fIoPerm = fPtePerm;
2780 return VINF_SUCCESS;
2781 }
2782 if (uNextLevel == 7)
2783 {
2784 /* The default page size of the translation is overridden. */
2785 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2786 uint8_t cShift = X86_PAGE_4K_SHIFT;
2787 while (GCPhysPte & RT_BIT_64(cShift++))
2788 ;
2789
2790 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2791 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2792 if ( cShift > s_acIovaLevelShifts[uLevel]
2793 && cShift < s_acIovaLevelShifts[uLevel + 1])
2794 {
2795 pWalkResult->GCPhysSpa = GCPhysPte;
2796 pWalkResult->cShift = cShift;
2797 pWalkResult->fIoPerm = fPtePerm;
2798 return VINF_SUCCESS;
2799 }
2800
2801 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2802 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2803 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2804 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2805 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2806 kIoPageFaultType_PteInvalidPageSize);
2807 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2808 }
2809
2810 /* Validate the next level encoding of the PDE. */
2811#if IOMMU_MAX_HOST_PT_LEVEL < 6
2812 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2813 { /* likely */ }
2814 else
2815 {
2816 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2817 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2818 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2819 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2820 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2821 kIoPageFaultType_PteInvalidLvlEncoding);
2822 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2823 }
2824#else
2825 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2826#endif
2827
2828 /* Validate level transition. */
2829 if (uNextLevel < uLevel)
2830 { /* likely */ }
2831 else
2832 {
2833 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2834 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2835 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2836 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2837 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2838 kIoPageFaultType_PteInvalidLvlEncoding);
2839 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2840 }
2841
2842 /* Ensure IOVA bits of skipped levels are zero. */
2843 Assert(uLevel > 0);
2844 uint64_t uIovaSkipMask = 0;
2845 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2846 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2847 if (!(uIova & uIovaSkipMask))
2848 { /* likely */ }
2849 else
2850 {
2851 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2852 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2853 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2854 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2855 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2856 kIoPageFaultType_SkippedLevelIovaNotZero);
2857 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2858 }
2859
2860 /* Continue with traversing the page directory at this level. */
2861 }
2862}
2863
2864
2865/**
2866 * Looks up an I/O virtual address from the device table.
2867 *
2868 * @returns VBox status code.
2869 * @param pDevIns The IOMMU instance data.
2870 * @param uDevId The device ID.
2871 * @param uIova The I/O virtual address to lookup.
2872 * @param cbAccess The size of the access.
2873 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2874 * permissions for the access being made.
2875 * @param enmOp The IOMMU operation being performed.
2876 * @param pGCPhysSpa Where to store the translated system physical address. Only
2877 * valid when translation succeeds and VINF_SUCCESS is
2878 * returned!
2879 *
2880 * @thread Any.
2881 */
2882static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2883 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2884{
2885 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2886
2887 /* Read the device table entry from memory. */
2888 DTE_T Dte;
2889 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2890 if (RT_SUCCESS(rc))
2891 {
2892 /* If the DTE is not valid, addresses are forwarded without translation */
2893 if (Dte.n.u1Valid)
2894 { /* likely */ }
2895 else
2896 {
2897 /** @todo IOMMU: Add to IOLTB cache. */
2898 *pGCPhysSpa = uIova;
2899 return VINF_SUCCESS;
2900 }
2901
2902 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2903 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2904 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2905 if (RT_LIKELY( !fRsvd0
2906 && !fRsvd1))
2907 { /* likely */ }
2908 else
2909 {
2910 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2911 EVT_ILLEGAL_DTE_T Event;
2912 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2913 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2914 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2915 }
2916
2917 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2918 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
2919 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2920 { /* likely */ }
2921 else
2922 {
2923 /** @todo IOMMU: Add to IOLTB cache. */
2924 *pGCPhysSpa = uIova;
2925 return VINF_SUCCESS;
2926 }
2927
2928 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
2929 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
2930
2931 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
2932 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2933 uint64_t cbRemaining = cbAccess;
2934 for (;;)
2935 {
2936 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
2937 IOWALKRESULT WalkResult;
2938 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
2939 if (RT_SUCCESS(rc))
2940 {
2941 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
2942
2943 /* Store the translated base address before continuing to check permissions for any more pages. */
2944 if (cbRemaining == cbAccess)
2945 {
2946 RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2947 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2948 }
2949
2950 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
2951 if (cbRemaining > cbPhysPage - offIova)
2952 {
2953 cbRemaining -= (cbPhysPage - offIova);
2954 uBaseIova += cbPhysPage;
2955 offIova = 0;
2956 }
2957 else
2958 break;
2959 }
2960 else
2961 {
2962 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
2963 uBaseIova, fAccess, rc));
2964 *pGCPhysSpa = NIL_RTGCPHYS;
2965 return rc;
2966 }
2967 }
2968
2969 return rc;
2970 }
2971
2972 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2973 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2974}
2975
2976
2977/**
2978 * Memory read request from a device.
2979 *
2980 * @returns VBox status code.
2981 * @param pDevIns The IOMMU device instance.
2982 * @param uDevId The device ID (bus, device, function).
2983 * @param uIova The I/O virtual address being read.
2984 * @param cbRead The number of bytes being read.
2985 * @param pGCPhysSpa Where to store the translated system physical address.
2986 *
2987 * @thread Any.
2988 */
2989static DECLCALLBACK(int) iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
2990 PRTGCPHYS pGCPhysSpa)
2991{
2992 /* Validate. */
2993 Assert(pDevIns);
2994 Assert(pGCPhysSpa);
2995 Assert(cbRead > 0);
2996
2997 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2998 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
2999
3000 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3001 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3002 if (Ctrl.n.u1IommuEn)
3003 {
3004 /** @todo IOMMU: IOTLB cache lookup. */
3005
3006 /* Lookup the IOVA from the device table. */
3007 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
3008 }
3009
3010 *pGCPhysSpa = uIova;
3011 return VINF_SUCCESS;
3012}
3013
3014
3015/**
3016 * Memory write request from a device.
3017 *
3018 * @returns VBox status code.
3019 * @param pDevIns The IOMMU device instance.
3020 * @param uDevId The device ID (bus, device, function).
3021 * @param uIova The I/O virtual address being written.
3022 * @param cbWrite The number of bytes being written.
3023 * @param pGCPhysSpa Where to store the translated physical address.
3024 *
3025 * @thread Any.
3026 */
3027static DECLCALLBACK(int) iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
3028 PRTGCPHYS pGCPhysSpa)
3029{
3030 /* Validate. */
3031 Assert(pDevIns);
3032 Assert(pGCPhysSpa);
3033 Assert(cbWrite > 0);
3034
3035 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3036 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
3037
3038 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3039 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3040 if (Ctrl.n.u1IommuEn)
3041 {
3042 /** @todo IOMMU: IOTLB cache lookup. */
3043
3044 /* Lookup the IOVA from the device table. */
3045 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
3046 }
3047
3048 *pGCPhysSpa = uIova;
3049 return VINF_SUCCESS;
3050}
3051
3052
3053/**
3054 * Reads an interrupt remapping table entry from guest memory given its DTE.
3055 *
3056 * @returns VBox status code.
3057 * @param pDevIns The IOMMU device instance.
3058 * @param uDevId The device ID.
3059 * @param pDte The device table entry.
3060 * @param GCPhysIn The source MSI address.
3061 * @param uDataIn The source MSI data.
3062 * @param enmOp The IOMMU operation being performed.
3063 * @param pIrte Where to store the interrupt remapping table entry.
3064 *
3065 * @thread Any.
3066 */
3067static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
3068 IOMMUOP enmOp, PIRTE_T pIrte)
3069{
3070 /* Ensure the IRTE length is valid. */
3071 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
3072
3073 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
3074 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
3075 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
3076 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
3077
3078 /* Ensure the IRTE falls completely within the interrupt table. */
3079 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
3080 { /* likely */ }
3081 else
3082 {
3083 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
3084 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
3085
3086 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3087 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
3088 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3089 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3090 kIoPageFaultType_IrteAddrInvalid);
3091 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3092 }
3093
3094 /* Read the IRTE from memory. */
3095 Assert(!(GCPhysIrte & 3));
3096 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
3097 if (RT_SUCCESS(rc))
3098 return VINF_SUCCESS;
3099
3100 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
3101 * situation. Is it an I/O page fault or a device table hardware error?
3102 * There's no interrupt table hardware error event, but it's unclear what
3103 * we should do here. */
3104 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
3105 return VERR_IOMMU_IPE_4;
3106}
3107
3108
3109/**
3110 * Remaps the interrupt using the interrupt remapping table.
3111 *
3112 * @returns VBox status code.
3113 * @param pDevIns The IOMMU instance data.
3114 * @param uDevId The device ID.
3115 * @param pDte The device table entry.
3116 * @param enmOp The IOMMU operation being performed.
3117 * @param pMsiIn The source MSI.
3118 * @param pMsiOut Where to store the remapped MSI.
3119 *
3120 * @thread Any.
3121 */
3122static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
3123 PMSIMSG pMsiOut)
3124{
3125 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
3126
3127 IRTE_T Irte;
3128 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
3129 if (RT_SUCCESS(rc))
3130 {
3131 if (Irte.n.u1RemapEnable)
3132 {
3133 if (!Irte.n.u1GuestMode)
3134 {
3135 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
3136 {
3137 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
3138 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
3139 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
3140 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
3141
3142 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
3143 pMsiOut->Data.u32 = pMsiIn->Data.u32;
3144 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
3145 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
3146
3147 return VINF_SUCCESS;
3148 }
3149
3150 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3151 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3152 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3153 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3154 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
3155 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3156 }
3157
3158 LogFunc(("Guest mode not supported -> IOPF\n"));
3159 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3160 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3161 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3162 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3163 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3164 }
3165
3166 LogFunc(("Remapping disabled -> IOPF\n"));
3167 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3168 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3169 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3170 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3171 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3172 }
3173
3174 return rc;
3175}
3176
3177
3178/**
3179 * Looks up an MSI interrupt from the interrupt remapping table.
3180 *
3181 * @returns VBox status code.
3182 * @param pDevIns The IOMMU instance data.
3183 * @param uDevId The device ID.
3184 * @param enmOp The IOMMU operation being performed.
3185 * @param pMsiIn The source MSI.
3186 * @param pMsiOut Where to store the remapped MSI.
3187 *
3188 * @thread Any.
3189 */
3190static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3191{
3192 /* Read the device table entry from memory. */
3193 LogFlowFunc(("uDevId=%#x enmOp=%u\n", uDevId, enmOp));
3194
3195 DTE_T Dte;
3196 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3197 if (RT_SUCCESS(rc))
3198 {
3199 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
3200 if (Dte.n.u1IntrMapValid)
3201 {
3202 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3203 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3204 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3205 if (RT_LIKELY( !fRsvd0
3206 && !fRsvd1))
3207 { /* likely */ }
3208 else
3209 {
3210 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3211 fRsvd1));
3212 EVT_ILLEGAL_DTE_T Event;
3213 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3214 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3215 return VERR_IOMMU_INTR_REMAP_FAILED;
3216 }
3217
3218 /*
3219 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3220 * that's connected through HyperTransport it might be possible; but for us, it
3221 * doesn't seem we need to specially handle these pins.
3222 */
3223
3224 /*
3225 * Validate the MSI source address.
3226 *
3227 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3228 * CPU is concerned, the MSI region is fixed and we must ensure no other device
3229 * claims the region as I/O space.
3230 *
3231 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3232 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3233 * See Intel spec. 10.11.1 "Message Address Register Format".
3234 */
3235 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3236 {
3237 /*
3238 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3239 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3240 */
3241 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3242 bool fPassThru = false;
3243 switch (u8DeliveryMode)
3244 {
3245 case VBOX_MSI_DELIVERY_MODE_FIXED:
3246 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3247 {
3248 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3249 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3250 {
3251 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
3252 iommuAmdSetPciTargetAbort(pDevIns);
3253 return VERR_IOMMU_INTR_REMAP_DENIED;
3254 }
3255
3256 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3257 {
3258 fPassThru = true;
3259 break;
3260 }
3261
3262 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3263 {
3264 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3265 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3266 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3267 {
3268 /*
3269 * We don't support guest interrupt remapping yet. When we do, we'll need to
3270 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3271 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3272 * already reads the control register, add that as a parameter when we eventually
3273 * support guest interrupt remapping. For now, just assert.
3274 */
3275 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3276 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3277 NOREF(pThis);
3278
3279 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3280 }
3281
3282 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3283 EVT_ILLEGAL_DTE_T Event;
3284 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3285 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3286 return VERR_IOMMU_INTR_REMAP_FAILED;
3287 }
3288
3289 /* Paranoia. */
3290 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
3291
3292 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3293
3294 EVT_ILLEGAL_DTE_T Event;
3295 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3296 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3297 return VERR_IOMMU_INTR_REMAP_FAILED;
3298 }
3299
3300 /* SMIs are passed through unmapped. We don't implement SMI filters. */
3301 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3302 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3303 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3304 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3305 default:
3306 {
3307 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3308 iommuAmdSetPciTargetAbort(pDevIns);
3309 return VERR_IOMMU_INTR_REMAP_FAILED;
3310 }
3311 }
3312
3313 if (fPassThru)
3314 {
3315 *pMsiOut = *pMsiIn;
3316 return VINF_SUCCESS;
3317 }
3318
3319 iommuAmdSetPciTargetAbort(pDevIns);
3320 return VERR_IOMMU_INTR_REMAP_DENIED;
3321 }
3322 else
3323 {
3324 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3325 return VERR_IOMMU_INTR_REMAP_FAILED;
3326 }
3327 }
3328 else
3329 {
3330 /** @todo IOMMU: Add to interrupt remapping cache. */
3331 LogFlowFunc(("DTE interrupt map not valid\n"));
3332 *pMsiOut = *pMsiIn;
3333 return VINF_SUCCESS;
3334 }
3335 }
3336
3337 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3338 return VERR_IOMMU_INTR_REMAP_FAILED;
3339}
3340
3341
3342/**
3343 * Interrupt remap request from a device.
3344 *
3345 * @returns VBox status code.
3346 * @param pDevIns The IOMMU device instance.
3347 * @param uDevId The device ID (bus, device, function).
3348 * @param pMsiIn The source MSI.
3349 * @param pMsiOut Where to store the remapped MSI.
3350 */
3351static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3352{
3353 /* Validate. */
3354 Assert(pDevIns);
3355 Assert(pMsiIn);
3356 Assert(pMsiOut);
3357
3358 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3359 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3360
3361 LogFlowFunc(("uDevId=%#x\n", uDevId));
3362
3363 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3364 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3365 if (Ctrl.n.u1IommuEn)
3366 {
3367 /** @todo Cache? */
3368
3369 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3370 }
3371
3372 *pMsiOut = *pMsiIn;
3373 return VINF_SUCCESS;
3374}
3375
3376
3377/**
3378 * @callback_method_impl{FNIOMMMIONEWWRITE}
3379 */
3380static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3381{
3382 NOREF(pvUser);
3383 Assert(cb == 4 || cb == 8);
3384 Assert(!(off & (cb - 1)));
3385
3386 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3387 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3388
3389 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
3390 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
3391}
3392
3393
3394/**
3395 * @callback_method_impl{FNIOMMMIONEWREAD}
3396 */
3397static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3398{
3399 NOREF(pvUser);
3400 Assert(cb == 4 || cb == 8);
3401 Assert(!(off & (cb - 1)));
3402
3403 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3404 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3405
3406 uint64_t uResult;
3407 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
3408 if (cb == 8)
3409 *(uint64_t *)pv = uResult;
3410 else
3411 *(uint32_t *)pv = (uint32_t)uResult;
3412
3413 return rcStrict;
3414}
3415
3416# ifdef IN_RING3
3417
3418/**
3419 * Processes an IOMMU command.
3420 *
3421 * @returns VBox status code.
3422 * @param pDevIns The IOMMU device instance.
3423 * @param pCmd The command to process.
3424 * @param GCPhysCmd The system physical address of the command.
3425 * @param pEvtError Where to store the error event in case of failures.
3426 *
3427 * @thread Command thread.
3428 */
3429static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3430{
3431 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3432
3433 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3434 STAM_COUNTER_INC(&pThis->StatCmd);
3435
3436 uint8_t const bCmd = pCmd->n.u4Opcode;
3437 switch (bCmd)
3438 {
3439 case IOMMU_CMD_COMPLETION_WAIT:
3440 {
3441 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3442
3443 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3444 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
3445
3446 /* Validate reserved bits in the command. */
3447 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3448 {
3449 /* If Completion Store is requested, write the StoreData to the specified address. */
3450 if (pCmdComWait->n.u1Store)
3451 {
3452 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3453 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3454 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3455 if (RT_FAILURE(rc))
3456 {
3457 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3458 GCPhysStore, rc));
3459 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3460 return VERR_IOMMU_CMD_HW_ERROR;
3461 }
3462 }
3463
3464 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3465 if (pCmdComWait->n.u1Interrupt)
3466 {
3467 IOMMU_LOCK(pDevIns);
3468 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3469 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3470 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3471 IOMMU_UNLOCK(pDevIns);
3472
3473 if (fRaiseInt)
3474 iommuAmdRaiseMsiInterrupt(pDevIns);
3475 }
3476 return VINF_SUCCESS;
3477 }
3478 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3479 return VERR_IOMMU_CMD_INVALID_FORMAT;
3480 }
3481
3482 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3483 {
3484 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3485 * then. */
3486 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3487 return VINF_SUCCESS;
3488 }
3489
3490 case IOMMU_CMD_INV_IOMMU_PAGES:
3491 {
3492 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3493 * then. */
3494 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3495 return VINF_SUCCESS;
3496 }
3497
3498 case IOMMU_CMD_INV_IOTLB_PAGES:
3499 {
3500 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3501
3502 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3503 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3504 {
3505 /** @todo IOMMU: Implement remote IOTLB invalidation. */
3506 return VERR_NOT_IMPLEMENTED;
3507 }
3508 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3509 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3510 }
3511
3512 case IOMMU_CMD_INV_INTR_TABLE:
3513 {
3514 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3515 * then. */
3516 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3517 return VINF_SUCCESS;
3518 }
3519
3520 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3521 {
3522 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3523 if (pThis->ExtFeat.n.u1PrefetchSup)
3524 {
3525 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
3526 return VINF_SUCCESS;
3527 }
3528 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3529 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3530 }
3531
3532 case IOMMU_CMD_COMPLETE_PPR_REQ:
3533 {
3534 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3535
3536 /* We don't support PPR requests yet. */
3537 Assert(!pThis->ExtFeat.n.u1PprSup);
3538 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3539 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3540 }
3541
3542 case IOMMU_CMD_INV_IOMMU_ALL:
3543 {
3544 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3545
3546 if (pThis->ExtFeat.n.u1InvAllSup)
3547 {
3548 /** @todo IOMMU: Invalidate all. Pretend success until then. */
3549 return VINF_SUCCESS;
3550 }
3551 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3552 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3553 }
3554 }
3555
3556 STAM_COUNTER_DEC(&pThis->StatCmd);
3557 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3558 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3559 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3560}
3561
3562
3563/**
3564 * The IOMMU command thread.
3565 *
3566 * @returns VBox status code.
3567 * @param pDevIns The IOMMU device instance.
3568 * @param pThread The command thread.
3569 */
3570static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3571{
3572 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3573
3574 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3575 return VINF_SUCCESS;
3576
3577 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3578 {
3579 /*
3580 * Sleep perpetually until we are woken up to process commands.
3581 */
3582 {
3583 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3584 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3585 if (!fSignaled)
3586 {
3587 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3588 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3589 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3590 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3591 break;
3592 Log5Func(("Woken up with rc=%Rrc\n", rc));
3593 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3594 }
3595 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3596 }
3597
3598 /*
3599 * Fetch and process IOMMU commands.
3600 */
3601 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
3602 * at a time) and is expensive due to calls to PGM for fetching guest memory.
3603 * We could optimize by fetching a bunch of commands at a time reducing
3604 * number of calls to PGM. In the longer run we could lock the memory and
3605 * mappings and accessing them directly. */
3606 IOMMU_LOCK(pDevIns);
3607
3608 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3609 if (Status.n.u1CmdBufRunning)
3610 {
3611 /* Get the offset we need to read the command from memory (circular buffer offset). */
3612 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3613 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3614 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3615 Assert(offHead < cbCmdBuf);
3616 while (offHead != pThis->CmdBufTailPtr.n.off)
3617 {
3618 /* Read the command from memory. */
3619 CMD_GENERIC_T Cmd;
3620 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3621 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3622 if (RT_SUCCESS(rc))
3623 {
3624 /* Increment the command buffer head pointer. */
3625 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3626 pThis->CmdBufHeadPtr.n.off = offHead;
3627
3628 /* Process the fetched command. */
3629 EVT_GENERIC_T EvtError;
3630 IOMMU_UNLOCK(pDevIns);
3631 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3632 IOMMU_LOCK(pDevIns);
3633 if (RT_FAILURE(rc))
3634 {
3635 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3636 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3637 {
3638 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3639 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3640 }
3641 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3642 {
3643 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3644 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", Cmd.n.u4Opcode));
3645 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3646 }
3647 break;
3648 }
3649 }
3650 else
3651 {
3652 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmd, rc));
3653 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3654 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3655 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3656 break;
3657 }
3658 }
3659 }
3660
3661 IOMMU_UNLOCK(pDevIns);
3662 }
3663
3664 LogFlowFunc(("Command thread terminating\n"));
3665 return VINF_SUCCESS;
3666}
3667
3668
3669/**
3670 * Wakes up the command thread so it can respond to a state change.
3671 *
3672 * @returns VBox status code.
3673 * @param pDevIns The IOMMU device instance.
3674 * @param pThread The command thread.
3675 */
3676static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3677{
3678 RT_NOREF(pThread);
3679 LogFlowFunc(("\n"));
3680 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3681 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3682}
3683
3684
3685/**
3686 * @callback_method_impl{FNPCICONFIGREAD}
3687 */
3688static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3689 unsigned cb, uint32_t *pu32Value)
3690{
3691 /** @todo IOMMU: PCI config read stat counter. */
3692 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3693 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3694 return rcStrict;
3695}
3696
3697
3698/**
3699 * @callback_method_impl{FNPCICONFIGWRITE}
3700 */
3701static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3702 unsigned cb, uint32_t u32Value)
3703{
3704 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3705
3706 /*
3707 * Discard writes to read-only registers that are specific to the IOMMU.
3708 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3709 * See PCI spec. 6.1. "Configuration Space Organization".
3710 */
3711 switch (uAddress)
3712 {
3713 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3714 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3715 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3716 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3717 {
3718 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3719 return VINF_SUCCESS;
3720 }
3721 }
3722
3723 IOMMU_LOCK(pDevIns);
3724
3725 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3726 switch (uAddress)
3727 {
3728 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3729 {
3730 if (pThis->IommuBar.n.u1Enable)
3731 {
3732 rcStrict = VINF_SUCCESS;
3733 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3734 break;
3735 }
3736
3737 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3738 if (pThis->IommuBar.n.u1Enable)
3739 {
3740 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3741 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3742 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3743 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
3744
3745 /* If the MMIO region is already mapped at the specified address, we're done. */
3746 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
3747 if (GCPhysMmioBasePrev == GCPhysMmioBase)
3748 {
3749 rcStrict = VINF_SUCCESS;
3750 break;
3751 }
3752
3753 /* Unmap the previous MMIO region (which is at a different address). */
3754 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
3755 {
3756 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
3757 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3758 if (RT_FAILURE(rcStrict))
3759 {
3760 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3761 break;
3762 }
3763 }
3764
3765 /* Map the newly specified MMIO region. */
3766 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
3767 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3768 if (RT_FAILURE(rcStrict))
3769 {
3770 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3771 break;
3772 }
3773 }
3774 else
3775 rcStrict = VINF_SUCCESS;
3776 break;
3777 }
3778
3779 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3780 {
3781 if (!pThis->IommuBar.n.u1Enable)
3782 pThis->IommuBar.au32[1] = u32Value;
3783 else
3784 {
3785 rcStrict = VINF_SUCCESS;
3786 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3787 }
3788 break;
3789 }
3790
3791 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3792 {
3793 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3794 RT_FALL_THRU();
3795 }
3796 default:
3797 {
3798 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3799 break;
3800 }
3801 }
3802
3803 IOMMU_UNLOCK(pDevIns);
3804
3805 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
3806 return rcStrict;
3807}
3808
3809
3810/**
3811 * @callback_method_impl{FNDBGFHANDLERDEV}
3812 */
3813static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3814{
3815 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3816 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3817 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3818
3819 bool fVerbose;
3820 if ( pszArgs
3821 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3822 fVerbose = true;
3823 else
3824 fVerbose = false;
3825
3826 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3827 /* Device Table Base Addresses (all segments). */
3828 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3829 {
3830 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3831 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3832 if (fVerbose)
3833 {
3834 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3835 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
3836 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3837 }
3838 }
3839 /* Command Buffer Base Address Register. */
3840 {
3841 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3842 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3843 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3844 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3845 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
3846 if (fVerbose)
3847 {
3848 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3849 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3850 cEntries, cbBuffer);
3851 }
3852 }
3853 /* Event Log Base Address Register. */
3854 {
3855 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3856 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3857 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3858 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3859 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
3860 if (fVerbose)
3861 {
3862 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3863 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3864 cEntries, cbBuffer);
3865 }
3866 }
3867 /* IOMMU Control Register. */
3868 {
3869 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3870 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3871 if (fVerbose)
3872 {
3873 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3874 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3875 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3876 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3877 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3878 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3879 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3880 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3881 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3882 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3883 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3884 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3885 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3886 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3887 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3888 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3889 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3890 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3891 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3892 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3893 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3894 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3895 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3896 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3897 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3898 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3899 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3900 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3901 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3902 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3903 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3904 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3905 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3906 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3907 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3908 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3909 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3910 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3911 }
3912 }
3913 /* Exclusion Base Address Register. */
3914 {
3915 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3916 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3917 if (fVerbose)
3918 {
3919 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3920 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3921 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
3922 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
3923 }
3924 }
3925 /* Exclusion Range Limit Register. */
3926 {
3927 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3928 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3929 if (fVerbose)
3930 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
3931 }
3932 /* Extended Feature Register. */
3933 {
3934 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3935 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3936 if (fVerbose)
3937 {
3938 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3939 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3940 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3941 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3942 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3943 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3944 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3945 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3946 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3947 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3948 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3949 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3950 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3951 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3952 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3953 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3954 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3955 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3956 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3957 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
3958 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
3959 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3960 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3961 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3962 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3963 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3964 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3965 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3966 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3967 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3968 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3969 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3970 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3971 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3972 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3973 }
3974 }
3975 /* PPR Log Base Address Register. */
3976 {
3977 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3978 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
3979 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3980 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3981 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3982 if (fVerbose)
3983 {
3984 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3985 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3986 cEntries, cbBuffer);
3987 }
3988 }
3989 /* Hardware Event (Hi) Register. */
3990 {
3991 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
3992 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
3993 if (fVerbose)
3994 {
3995 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
3996 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
3997 }
3998 }
3999 /* Hardware Event (Lo) Register. */
4000 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4001 /* Hardware Event Status. */
4002 {
4003 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4004 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4005 if (fVerbose)
4006 {
4007 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4008 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4009 }
4010 }
4011 /* Guest Virtual-APIC Log Base Address Register. */
4012 {
4013 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4014 uint8_t const uEncodedLen = GALogBar.n.u4Len;
4015 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4016 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4017 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4018 if (fVerbose)
4019 {
4020 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4021 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4022 cEntries, cbBuffer);
4023 }
4024 }
4025 /* Guest Virtual-APIC Log Tail Address Register. */
4026 {
4027 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4028 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4029 if (fVerbose)
4030 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4031 }
4032 /* PPR Log B Base Address Register. */
4033 {
4034 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4035 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4036 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4037 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4038 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4039 if (fVerbose)
4040 {
4041 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4042 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4043 cEntries, cbBuffer);
4044 }
4045 }
4046 /* Event Log B Base Address Register. */
4047 {
4048 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4049 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4050 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4051 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4052 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4053 if (fVerbose)
4054 {
4055 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4056 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4057 cEntries, cbBuffer);
4058 }
4059 }
4060 /* Device-Specific Feature Extension Register. */
4061 {
4062 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4063 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4064 if (fVerbose)
4065 {
4066 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4067 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4068 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4069 }
4070 }
4071 /* Device-Specific Control Extension Register. */
4072 {
4073 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4074 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4075 if (fVerbose)
4076 {
4077 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4078 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4079 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4080 }
4081 }
4082 /* Device-Specific Status Extension Register. */
4083 {
4084 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4085 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
4086 if (fVerbose)
4087 {
4088 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4089 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4090 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4091 }
4092 }
4093 /* Miscellaneous Information Register (Lo and Hi). */
4094 {
4095 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
4096 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
4097 if (fVerbose)
4098 {
4099 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
4100 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
4101 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
4102 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
4103 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
4104 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
4105 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
4106 }
4107 }
4108 /* MSI Capability Header. */
4109 {
4110 MSI_CAP_HDR_T MsiCapHdr;
4111 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4112 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4113 if (fVerbose)
4114 {
4115 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4116 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4117 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4118 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4119 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4120 }
4121 }
4122 /* MSI Address Register (Lo and Hi). */
4123 {
4124 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4125 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4126 MSIADDR MsiAddr;
4127 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4128 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4129 if (fVerbose)
4130 {
4131 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
4132 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
4133 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
4134 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
4135 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
4136 }
4137 }
4138 /* MSI Data. */
4139 {
4140 MSIDATA MsiData;
4141 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4142 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4143 if (fVerbose)
4144 {
4145 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
4146 MsiData.n.u8Vector);
4147 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
4148 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
4149 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4150 "level" : "edge");
4151 }
4152 }
4153 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4154 {
4155 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4156 MsiMapCapHdr.u32 = 0;
4157 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4158 if (fVerbose)
4159 {
4160 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4161 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4162 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4163 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4164 }
4165 }
4166 /* Performance Optimization Control Register. */
4167 {
4168 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4169 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4170 if (fVerbose)
4171 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4172 }
4173 /* XT (x2APIC) General Interrupt Control Register. */
4174 {
4175 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4176 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4177 if (fVerbose)
4178 {
4179 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4180 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4181 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4182 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4183 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4184 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4185 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4186 }
4187 }
4188 /* XT (x2APIC) PPR Interrupt Control Register. */
4189 {
4190 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4191 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4192 if (fVerbose)
4193 {
4194 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4195 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4196 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4197 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4198 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4199 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4200 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4201 }
4202 }
4203 /* XT (X2APIC) GA Log Interrupt Control Register. */
4204 {
4205 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4206 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4207 if (fVerbose)
4208 {
4209 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4210 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4211 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4212 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4213 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4214 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4215 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4216 }
4217 }
4218 /* MARC Registers. */
4219 {
4220 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4221 {
4222 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4223 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4224 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4225
4226 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4227 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4228 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4229 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4230
4231 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4232 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4233 }
4234 }
4235 /* Reserved Register. */
4236 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4237 /* Command Buffer Head Pointer Register. */
4238 {
4239 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4240 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4241 CmdBufHeadPtr.n.off);
4242 }
4243 /* Command Buffer Tail Pointer Register. */
4244 {
4245 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4246 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4247 CmdBufTailPtr.n.off);
4248 }
4249 /* Event Log Head Pointer Register. */
4250 {
4251 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4252 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4253 EvtLogHeadPtr.n.off);
4254 }
4255 /* Event Log Tail Pointer Register. */
4256 {
4257 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4258 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4259 EvtLogTailPtr.n.off);
4260 }
4261 /* Status Register. */
4262 {
4263 IOMMU_STATUS_T const Status = pThis->Status;
4264 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4265 if (fVerbose)
4266 {
4267 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4268 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4269 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4270 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4271 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4272 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4273 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4274 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4275 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4276 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4277 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4278 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4279 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4280 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4281 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4282 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4283 }
4284 }
4285 /* PPR Log Head Pointer. */
4286 {
4287 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4288 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4289 PprLogHeadPtr.n.off);
4290 }
4291 /* PPR Log Tail Pointer. */
4292 {
4293 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4294 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4295 PprLogTailPtr.n.off);
4296 }
4297 /* Guest Virtual-APIC Log Head Pointer. */
4298 {
4299 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4300 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4301 GALogHeadPtr.n.u12GALogPtr);
4302 }
4303 /* Guest Virtual-APIC Log Tail Pointer. */
4304 {
4305 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4306 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4307 GALogTailPtr.n.u12GALogPtr);
4308 }
4309 /* PPR Log B Head Pointer. */
4310 {
4311 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4312 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4313 PprLogBHeadPtr.n.off);
4314 }
4315 /* PPR Log B Tail Pointer. */
4316 {
4317 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4318 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4319 PprLogBTailPtr.n.off);
4320 }
4321 /* Event Log B Head Pointer. */
4322 {
4323 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4324 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4325 EvtLogBHeadPtr.n.off);
4326 }
4327 /* Event Log B Tail Pointer. */
4328 {
4329 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4330 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4331 EvtLogBTailPtr.n.off);
4332 }
4333 /* PPR Log Auto Response Register. */
4334 {
4335 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4336 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4337 if (fVerbose)
4338 {
4339 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4340 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4341 }
4342 }
4343 /* PPR Log Overflow Early Warning Indicator Register. */
4344 {
4345 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4346 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4347 if (fVerbose)
4348 {
4349 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4350 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4351 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4352 }
4353 }
4354 /* PPR Log Overflow Early Warning Indicator Register. */
4355 {
4356 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4357 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4358 if (fVerbose)
4359 {
4360 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4361 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4362 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4363 }
4364 }
4365}
4366
4367
4368/**
4369 * Dumps the DTE via the info callback helper.
4370 *
4371 * @param pHlp The info helper.
4372 * @param pDte The device table entry.
4373 * @param pszPrefix The string prefix.
4374 */
4375static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4376{
4377 AssertReturnVoid(pHlp);
4378 AssertReturnVoid(pDte);
4379 AssertReturnVoid(pszPrefix);
4380
4381 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4382 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4383 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4384 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4385 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4386 pDte->n.u40PageTableRootPtrLo << 12);
4387 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4388 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4389 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4390 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4391 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4392 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4393 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4394 (pDte->n.u21GstCr3TableRootPtrHi << 31)
4395 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
4396 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
4397 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4398 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4399 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4400 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4401 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4402 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4403 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4404 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4405 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4406 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4407 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4408 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4409 pHlp->pfnPrintf(pHlp, "\n");
4410
4411 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4412 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4413 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4414 {
4415 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4416 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4417 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4418 cbIntrTable);
4419 }
4420 else
4421 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4422 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4423 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4424 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4425 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4426 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4427 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4428 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4429 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4430 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4431 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4432 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4433 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4434 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4435 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4436 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4437 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4438}
4439
4440
4441/**
4442 * @callback_method_impl{FNDBGFHANDLERDEV}
4443 */
4444static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4445{
4446 if (pszArgs)
4447 {
4448 uint16_t uDevId = 0;
4449 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4450 if (RT_SUCCESS(rc))
4451 {
4452 DTE_T Dte;
4453 rc = iommuAmdReadDte(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4454 if (RT_SUCCESS(rc))
4455 {
4456 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4457 return;
4458 }
4459
4460 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4461 }
4462 else
4463 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4464 }
4465 else
4466 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4467}
4468
4469
4470#if 0
4471/**
4472 * @callback_method_impl{FNDBGFHANDLERDEV}
4473 */
4474static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4475{
4476 RT_NOREF(pszArgs);
4477
4478 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4479 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4480 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4481
4482 uint8_t cTables = 0;
4483 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4484 {
4485 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4486 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4487 if (GCPhysDevTab)
4488 ++cTables;
4489 }
4490
4491 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4492 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4493 if (!cTables)
4494 return;
4495
4496 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4497 {
4498 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4499 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4500 if (GCPhysDevTab)
4501 {
4502 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4503 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4504 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4505
4506 void *pvDevTab = RTMemAllocZ(cbDevTab);
4507 if (RT_LIKELY(pvDevTab))
4508 {
4509 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4510 if (RT_SUCCESS(rc))
4511 {
4512 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4513 {
4514 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
4515 if ( pDte->n.u1Valid
4516 || pDte->n.u1IntrMapValid)
4517 {
4518 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4519 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4520 }
4521 }
4522 pHlp->pfnPrintf(pHlp, "\n");
4523 }
4524 else
4525 {
4526 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4527 cbDevTab, rc);
4528 }
4529
4530 RTMemFree(pvDevTab);
4531 }
4532 else
4533 {
4534 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4535 return;
4536 }
4537 }
4538 }
4539}
4540#endif
4541
4542/**
4543 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4544 */
4545static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4546{
4547 /** @todo IOMMU: Save state. */
4548 RT_NOREF2(pDevIns, pSSM);
4549 LogFlowFunc(("\n"));
4550 return VERR_NOT_IMPLEMENTED;
4551}
4552
4553
4554/**
4555 * @callback_method_impl{FNSSMDEVLOADEXEC}
4556 */
4557static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4558{
4559 /** @todo IOMMU: Load state. */
4560 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4561 LogFlowFunc(("\n"));
4562 return VERR_NOT_IMPLEMENTED;
4563}
4564
4565
4566/**
4567 * @interface_method_impl{PDMDEVREG,pfnReset}
4568 */
4569static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4570{
4571 /*
4572 * Resets read-write portion of the IOMMU state.
4573 *
4574 * State data not initialized here is expected to be initialized during
4575 * device construction and remain read-only through the lifetime of the VM.
4576 */
4577 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4578 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4579 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4580
4581 IOMMU_LOCK_NORET(pDevIns);
4582
4583 LogFlowFunc(("\n"));
4584
4585 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4586
4587 pThis->CmdBufBaseAddr.u64 = 0;
4588 pThis->CmdBufBaseAddr.n.u4Len = 8;
4589
4590 pThis->EvtLogBaseAddr.u64 = 0;
4591 pThis->EvtLogBaseAddr.n.u4Len = 8;
4592
4593 pThis->Ctrl.u64 = 0;
4594 pThis->Ctrl.n.u1Coherent = 1;
4595 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4596
4597 pThis->ExclRangeBaseAddr.u64 = 0;
4598 pThis->ExclRangeLimit.u64 = 0;
4599
4600 pThis->PprLogBaseAddr.u64 = 0;
4601 pThis->PprLogBaseAddr.n.u4Len = 8;
4602
4603 pThis->HwEvtHi.u64 = 0;
4604 pThis->HwEvtLo = 0;
4605 pThis->HwEvtStatus.u64 = 0;
4606
4607 pThis->GALogBaseAddr.u64 = 0;
4608 pThis->GALogBaseAddr.n.u4Len = 8;
4609 pThis->GALogTailAddr.u64 = 0;
4610
4611 pThis->PprLogBBaseAddr.u64 = 0;
4612 pThis->PprLogBBaseAddr.n.u4Len = 8;
4613
4614 pThis->EvtLogBBaseAddr.u64 = 0;
4615 pThis->EvtLogBBaseAddr.n.u4Len = 8;
4616
4617 pThis->PerfOptCtrl.u32 = 0;
4618
4619 pThis->XtGenIntrCtrl.u64 = 0;
4620 pThis->XtPprIntrCtrl.u64 = 0;
4621 pThis->XtGALogIntrCtrl.u64 = 0;
4622
4623 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4624
4625 pThis->CmdBufHeadPtr.u64 = 0;
4626 pThis->CmdBufTailPtr.u64 = 0;
4627 pThis->EvtLogHeadPtr.u64 = 0;
4628 pThis->EvtLogTailPtr.u64 = 0;
4629
4630 pThis->Status.u64 = 0;
4631
4632 pThis->PprLogHeadPtr.u64 = 0;
4633 pThis->PprLogTailPtr.u64 = 0;
4634
4635 pThis->GALogHeadPtr.u64 = 0;
4636 pThis->GALogTailPtr.u64 = 0;
4637
4638 pThis->PprLogBHeadPtr.u64 = 0;
4639 pThis->PprLogBTailPtr.u64 = 0;
4640
4641 pThis->EvtLogBHeadPtr.u64 = 0;
4642 pThis->EvtLogBTailPtr.u64 = 0;
4643
4644 pThis->PprLogAutoResp.u64 = 0;
4645 pThis->PprLogOverflowEarly.u64 = 0;
4646 pThis->PprLogBOverflowEarly.u64 = 0;
4647
4648 pThis->IommuBar.u64 = 0;
4649 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4650 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4651
4652 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4653
4654 IOMMU_UNLOCK(pDevIns);
4655}
4656
4657
4658/**
4659 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4660 */
4661static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4662{
4663 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4664 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4665 LogFlowFunc(("\n"));
4666
4667 /* Close the command thread semaphore. */
4668 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4669 {
4670 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4671 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4672 }
4673 return VINF_SUCCESS;
4674}
4675
4676
4677/**
4678 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4679 */
4680static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4681{
4682 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4683 RT_NOREF(pCfg);
4684
4685 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4686 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4687 pThisCC->pDevInsR3 = pDevIns;
4688
4689 LogFlowFunc(("iInstance=%d\n", iInstance));
4690
4691 /*
4692 * Register the IOMMU with PDM.
4693 */
4694 PDMIOMMUREGR3 IommuReg;
4695 RT_ZERO(IommuReg);
4696 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4697 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4698 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4699 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4700 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4701 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4702 if (RT_FAILURE(rc))
4703 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4704 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4705 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4706 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4707 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4708 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4709 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4710 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4711 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4712
4713 /*
4714 * Initialize read-only PCI configuration space.
4715 */
4716 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4717 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4718
4719 /* Header. */
4720 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4721 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4722 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
4723 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4724 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4725 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4726 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4727 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4728 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4729 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4730 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4731 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4732 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4733 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4734
4735 /* Capability Header. */
4736 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4737 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4738 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4739 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
4740 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4741 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4742 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4743 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4744 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4745 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4746 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4747
4748 /* Base Address Register. */
4749 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4750 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4751
4752 /* IOMMU Range Register. */
4753 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4754
4755 /* Misc. Information Register. */
4756 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4757 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4758 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4759 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4760 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4761 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4762 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4763 uint32_t const uMiscInfoReg1 = 0;
4764 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4765 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4766
4767 /* MSI Capability Header register. */
4768 PDMMSIREG MsiReg;
4769 RT_ZERO(MsiReg);
4770 MsiReg.cMsiVectors = 1;
4771 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4772 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4773 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4774
4775 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4776#if 0
4777 /* MSI Address Lo. */
4778 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4779 /* MSI Address Hi. */
4780 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4781 /* MSI Data. */
4782 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4783#endif
4784
4785#if 0
4786 /** @todo IOMMU: I don't know if we need to support this, enable later if
4787 * required. */
4788 /* MSI Mapping Capability Header register. */
4789 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4790 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4791 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4792 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4793 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4794 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4795 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4796#endif
4797
4798 /*
4799 * Register the PCI function with PDM.
4800 */
4801 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4802 AssertLogRelRCReturn(rc, rc);
4803
4804 /*
4805 * Register MSI support for the PCI device.
4806 * This must be done -after- register it as a PCI device!
4807 */
4808 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4809 AssertRCReturn(rc, rc);
4810
4811 /*
4812 * Intercept PCI config. space accesses.
4813 */
4814 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4815 AssertLogRelRCReturn(rc, rc);
4816
4817 /*
4818 * Create the MMIO region.
4819 * Mapping of the region is done when software configures it via PCI config space.
4820 */
4821 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4822 NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING,
4823 "AMD-IOMMU", &pThis->hMmio);
4824 AssertLogRelRCReturn(rc, rc);
4825
4826 /*
4827 * Register saved state.
4828 */
4829 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4830 NULL, NULL, NULL,
4831 NULL, iommuAmdR3SaveExec, NULL,
4832 NULL, iommuAmdR3LoadExec, NULL);
4833 AssertLogRelRCReturn(rc, rc);
4834
4835 /*
4836 * Register debugger info items.
4837 */
4838 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
4839 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
4840#if 0
4841 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
4842#endif
4843
4844# ifdef VBOX_WITH_STATISTICS
4845 /*
4846 * Statistics.
4847 */
4848 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4849 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4850
4851 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4852 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4853
4854 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemapR3", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
4855 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRZ", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
4856
4857 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
4858 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
4859 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
4860 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
4861 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
4862 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
4863 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
4864 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
4865 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
4866# endif
4867
4868 /*
4869 * Create the command thread and its event semaphore.
4870 */
4871 char szDevIommu[64];
4872 RT_ZERO(szDevIommu);
4873 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
4874 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
4875 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
4876 AssertLogRelRCReturn(rc, rc);
4877
4878 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
4879 AssertLogRelRCReturn(rc, rc);
4880
4881 /*
4882 * Initialize read-only registers.
4883 * NOTE! Fields here must match their corresponding field in the ACPI tables.
4884 */
4885 /** @todo Don't remove the =0 assignment for now. It's just there so it's easier
4886 * for me to see existing features that we might want to implement. Do it
4887 * later. */
4888 pThis->ExtFeat.u64 = 0;
4889 pThis->ExtFeat.n.u1PrefetchSup = 0;
4890 pThis->ExtFeat.n.u1PprSup = 0;
4891 pThis->ExtFeat.n.u1X2ApicSup = 0;
4892 pThis->ExtFeat.n.u1NoExecuteSup = 0;
4893 pThis->ExtFeat.n.u1GstTranslateSup = 0;
4894 pThis->ExtFeat.n.u1InvAllSup = 1;
4895 pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4896 pThis->ExtFeat.n.u1HwErrorSup = 1;
4897 pThis->ExtFeat.n.u1PerfCounterSup = 0;
4898 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4899 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4900 pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
4901 pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
4902 pThis->ExtFeat.n.u2SmiFilterSup = 0;
4903 pThis->ExtFeat.n.u3SmiFilterCount = 0;
4904 pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
4905 pThis->ExtFeat.n.u2DualPprLogSup = 0;
4906 pThis->ExtFeat.n.u2DualEvtLogSup = 0;
4907 pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
4908 pThis->ExtFeat.n.u1UserSupervisorSup = 0;
4909 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
4910 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
4911 pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
4912 pThis->ExtFeat.n.u1PprAutoRespSup = 0;
4913 pThis->ExtFeat.n.u2MarcSup = 0;
4914 pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
4915 pThis->ExtFeat.n.u1PerfOptSup = 0;
4916 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
4917 pThis->ExtFeat.n.u1GstIoSup = 0;
4918 pThis->ExtFeat.n.u1HostAccessSup = 0;
4919 pThis->ExtFeat.n.u1EnhancedPprSup = 0;
4920 pThis->ExtFeat.n.u1AttrForwardSup = 0;
4921 pThis->ExtFeat.n.u1HostDirtySup = 0;
4922 pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
4923 pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
4924 pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
4925
4926 pThis->RsvdReg = 0;
4927
4928 pThis->DevSpecificFeat.u64 = 0;
4929 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
4930 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
4931
4932 pThis->DevSpecificCtrl.u64 = 0;
4933 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
4934 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
4935
4936 pThis->DevSpecificStatus.u64 = 0;
4937 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
4938 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
4939
4940 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
4941
4942 /*
4943 * Initialize parts of the IOMMU state as it would during reset.
4944 * Must be called -after- initializing PCI config. space registers.
4945 */
4946 iommuAmdR3Reset(pDevIns);
4947
4948 return VINF_SUCCESS;
4949}
4950
4951# else /* !IN_RING3 */
4952
4953/**
4954 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4955 */
4956static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
4957{
4958 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4959 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4960 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4961
4962 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4963
4964 /* Set up the MMIO RZ handlers. */
4965 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
4966 AssertRCReturn(rc, rc);
4967
4968 /* Set up the IOMMU RZ callbacks. */
4969 PDMIOMMUREGCC IommuReg;
4970 RT_ZERO(IommuReg);
4971 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4972 IommuReg.idxIommu = pThis->idxIommu;
4973 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4974 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4975 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4976 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4977 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4978 AssertRCReturn(rc, rc);
4979
4980 return VINF_SUCCESS;
4981}
4982
4983# endif /* !IN_RING3 */
4984
4985/**
4986 * The device registration structure.
4987 */
4988const PDMDEVREG g_DeviceIommuAmd =
4989{
4990 /* .u32Version = */ PDM_DEVREG_VERSION,
4991 /* .uReserved0 = */ 0,
4992 /* .szName = */ "iommu-amd",
4993 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4994 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4995 /* .cMaxInstances = */ ~0U,
4996 /* .uSharedVersion = */ 42,
4997 /* .cbInstanceShared = */ sizeof(IOMMU),
4998 /* .cbInstanceCC = */ sizeof(IOMMUCC),
4999 /* .cbInstanceRC = */ sizeof(IOMMURC),
5000 /* .cMaxPciDevices = */ 1,
5001 /* .cMaxMsixVectors = */ 0,
5002 /* .pszDescription = */ "IOMMU (AMD)",
5003#if defined(IN_RING3)
5004 /* .pszRCMod = */ "VBoxDDRC.rc",
5005 /* .pszR0Mod = */ "VBoxDDR0.r0",
5006 /* .pfnConstruct = */ iommuAmdR3Construct,
5007 /* .pfnDestruct = */ iommuAmdR3Destruct,
5008 /* .pfnRelocate = */ NULL,
5009 /* .pfnMemSetup = */ NULL,
5010 /* .pfnPowerOn = */ NULL,
5011 /* .pfnReset = */ iommuAmdR3Reset,
5012 /* .pfnSuspend = */ NULL,
5013 /* .pfnResume = */ NULL,
5014 /* .pfnAttach = */ NULL,
5015 /* .pfnDetach = */ NULL,
5016 /* .pfnQueryInterface = */ NULL,
5017 /* .pfnInitComplete = */ NULL,
5018 /* .pfnPowerOff = */ NULL,
5019 /* .pfnSoftReset = */ NULL,
5020 /* .pfnReserved0 = */ NULL,
5021 /* .pfnReserved1 = */ NULL,
5022 /* .pfnReserved2 = */ NULL,
5023 /* .pfnReserved3 = */ NULL,
5024 /* .pfnReserved4 = */ NULL,
5025 /* .pfnReserved5 = */ NULL,
5026 /* .pfnReserved6 = */ NULL,
5027 /* .pfnReserved7 = */ NULL,
5028#elif defined(IN_RING0)
5029 /* .pfnEarlyConstruct = */ NULL,
5030 /* .pfnConstruct = */ iommuAmdRZConstruct,
5031 /* .pfnDestruct = */ NULL,
5032 /* .pfnFinalDestruct = */ NULL,
5033 /* .pfnRequest = */ NULL,
5034 /* .pfnReserved0 = */ NULL,
5035 /* .pfnReserved1 = */ NULL,
5036 /* .pfnReserved2 = */ NULL,
5037 /* .pfnReserved3 = */ NULL,
5038 /* .pfnReserved4 = */ NULL,
5039 /* .pfnReserved5 = */ NULL,
5040 /* .pfnReserved6 = */ NULL,
5041 /* .pfnReserved7 = */ NULL,
5042#elif defined(IN_RC)
5043 /* .pfnConstruct = */ iommuAmdRZConstruct,
5044 /* .pfnReserved0 = */ NULL,
5045 /* .pfnReserved1 = */ NULL,
5046 /* .pfnReserved2 = */ NULL,
5047 /* .pfnReserved3 = */ NULL,
5048 /* .pfnReserved4 = */ NULL,
5049 /* .pfnReserved5 = */ NULL,
5050 /* .pfnReserved6 = */ NULL,
5051 /* .pfnReserved7 = */ NULL,
5052#else
5053# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5054#endif
5055 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
5056};
5057
5058#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5059
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