VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86210

Last change on this file since 86210 was 86210, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Extract common code in preparation for reworking MMIO register reads (to support high 32-bit reads on 64-bit registers).
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1/* $Id: DevIommuAmd.cpp 86210 2020-09-22 07:08:56Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31
32#include "VBoxDD.h"
33#include "DevIommuAmd.h"
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** Release log prefix string. */
40#define IOMMU_LOG_PFX "IOMMU-AMD"
41/** The current saved state version. */
42#define IOMMU_SAVED_STATE_VERSION 1
43/** The IOTLB entry magic. */
44#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46#ifndef DEBUG_ramshankar
47/** Temporary, make permanent later (get rid of define entirely and remove old
48 * code). This allow ssub-qword accesses to qword registers. Write accesses
49 * seems to work (needs testing one sub-path of the code), Read accesses not yet
50 * converted. */
51# define IOMMU_NEW_REGISTER_ACCESS
52#endif
53
54
55/*********************************************************************************************************************************
56* Structures and Typedefs *
57*********************************************************************************************************************************/
58/**
59 * Acquires the IOMMU PDM lock.
60 * This will make a long jump to ring-3 to acquire the lock if necessary.
61 */
62#define IOMMU_LOCK(a_pDevIns) \
63 do { \
64 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
65 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
66 { /* likely */ } \
67 else \
68 return rcLock; \
69 } while (0)
70
71/**
72 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
73 * This will make a long jump to ring-3 to acquire the lock if necessary.
74 */
75#define IOMMU_LOCK_NORET(a_pDevIns) \
76 do { \
77 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
78 AssertRC(rcLock); \
79 } while (0)
80
81/**
82 * Releases the IOMMU PDM lock.
83 */
84#define IOMMU_UNLOCK(a_pDevIns) \
85 do { \
86 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
87 } while (0)
88
89/**
90 * Asserts that the critsect is owned by this thread.
91 */
92#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
93 do { \
94 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95 } while (0)
96
97/**
98 * Asserts that the critsect is not owned by this thread.
99 */
100#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
101 do { \
102 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
103 } while (0)
104
105/**
106 * IOMMU operations (transaction) types.
107 */
108typedef enum IOMMUOP
109{
110 /** Address translation request. */
111 IOMMUOP_TRANSLATE_REQ = 0,
112 /** Memory read request. */
113 IOMMUOP_MEM_READ,
114 /** Memory write request. */
115 IOMMUOP_MEM_WRITE,
116 /** Interrupt request. */
117 IOMMUOP_INTR_REQ,
118 /** Command. */
119 IOMMUOP_CMD
120} IOMMUOP;
121AssertCompileSize(IOMMUOP, 4);
122
123/**
124 * I/O page walk result.
125 */
126typedef struct
127{
128 /** The translated system physical address. */
129 RTGCPHYS GCPhysSpa;
130 /** The number of offset bits in the system physical address. */
131 uint8_t cShift;
132 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
133 uint8_t fIoPerm;
134 /** Padding. */
135 uint8_t abPadding[2];
136} IOWALKRESULT;
137/** Pointer to an I/O walk result struct. */
138typedef IOWALKRESULT *PIOWALKRESULT;
139/** Pointer to a const I/O walk result struct. */
140typedef IOWALKRESULT *PCIOWALKRESULT;
141
142/**
143 * IOMMU I/O TLB Entry.
144 * Keep this as small and aligned as possible.
145 */
146typedef struct
147{
148 /** The translated system physical address (SPA) of the page. */
149 RTGCPHYS GCPhysSpa;
150 /** The index of the 4K page within a large page. */
151 uint32_t idxSubPage;
152 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
153 uint8_t fIoPerm;
154 /** The number of offset bits in the translation indicating page size. */
155 uint8_t cShift;
156 /** Alignment padding. */
157 uint8_t afPadding[2];
158} IOTLBE_T;
159AssertCompileSize(IOTLBE_T, 16);
160/** Pointer to an IOMMU I/O TLB entry struct. */
161typedef IOTLBE_T *PIOTLBE_T;
162/** Pointer to a const IOMMU I/O TLB entry struct. */
163typedef IOTLBE_T const *PCIOTLBE_T;
164
165/**
166 * The shared IOMMU device state.
167 */
168typedef struct IOMMU
169{
170 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
171 uint32_t idxIommu;
172 /** Alignment padding. */
173 uint32_t uPadding0;
174
175 /** Whether the command thread is sleeping. */
176 bool volatile fCmdThreadSleeping;
177 /** Alignment padding. */
178 uint8_t afPadding0[3];
179 /** Whether the command thread has been signaled for wake up. */
180 bool volatile fCmdThreadSignaled;
181 /** Alignment padding. */
182 uint8_t afPadding1[3];
183
184 /** The event semaphore the command thread waits on. */
185 SUPSEMEVENT hEvtCmdThread;
186 /** The MMIO handle. */
187 IOMMMIOHANDLE hMmio;
188
189 /** @name PCI: Base capability block registers.
190 * @{ */
191 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
192 /** @} */
193
194 /** @name MMIO: Control and status registers.
195 * @{ */
196 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
197 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
198 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
199 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
200 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
201 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
202 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
203 /** @} */
204
205 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
206 * @{ */
207 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
208 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
209 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
210 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
211 /** @} */
212
213 /** @todo IOMMU: SMI filter. */
214
215 /** @name MMIO: Guest Virtual-APIC Log registers.
216 * @{ */
217 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
218 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
219 /** @} */
220
221 /** @name MMIO: Alternate PPR and Event Log registers.
222 * @{ */
223 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
224 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
225 /** @} */
226
227 /** @name MMIO: Device-specific feature registers.
228 * @{ */
229 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
230 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
231 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
232 /** @} */
233
234 /** @name MMIO: MSI Capability Block registers.
235 * @{ */
236 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
237 /** @} */
238
239 /** @name MMIO: Performance Optimization Control registers.
240 * @{ */
241 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
242 /** @} */
243
244 /** @name MMIO: x2APIC Control registers.
245 * @{ */
246 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
247 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
248 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
249 /** @} */
250
251 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
252 * @{ */
253 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
254 /** @} */
255
256 /** @name MMIO: Reserved register.
257 * @{ */
258 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
259 /** @} */
260
261 /** @name MMIO: Command and Event Log pointer registers.
262 * @{ */
263 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
264 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
265 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
266 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
267 /** @} */
268
269 /** @name MMIO: Command and Event Status register.
270 * @{ */
271 IOMMU_STATUS_T Status; /**< IOMMU status register. */
272 /** @} */
273
274 /** @name MMIO: PPR Log Head and Tail pointer registers.
275 * @{ */
276 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
277 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
278 /** @} */
279
280 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
281 * @{ */
282 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
283 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
284 /** @} */
285
286 /** @name MMIO: PPR Log B Head and Tail pointer registers.
287 * @{ */
288 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
289 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
290 /** @} */
291
292 /** @name MMIO: Event Log B Head and Tail pointer registers.
293 * @{ */
294 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
295 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
296 /** @} */
297
298 /** @name MMIO: PPR Log Overflow protection registers.
299 * @{ */
300 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
301 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
302 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
303 /** @} */
304
305 /** @todo IOMMU: IOMMU Event counter registers. */
306
307#ifdef VBOX_WITH_STATISTICS
308 /** @name IOMMU: Stat counters.
309 * @{ */
310 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
311 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
312
313 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
314 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
315
316 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
317 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
318
319 STAMCOUNTER StatCmd; /**< Number of commands processed. */
320 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
321 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
322 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
323 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
324 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
325 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
326 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
327 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
328 /** @} */
329#endif
330} IOMMU;
331/** Pointer to the IOMMU device state. */
332typedef struct IOMMU *PIOMMU;
333/** Pointer to the const IOMMU device state. */
334typedef const struct IOMMU *PCIOMMU;
335AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
336AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
337AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
338AssertCompileMemberAlignment(IOMMU, hMmio, 8);
339AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
340
341/**
342 * The ring-3 IOMMU device state.
343 */
344typedef struct IOMMUR3
345{
346 /** Device instance. */
347 PPDMDEVINSR3 pDevInsR3;
348 /** The IOMMU helpers. */
349 PCPDMIOMMUHLPR3 pIommuHlpR3;
350 /** The command thread handle. */
351 R3PTRTYPE(PPDMTHREAD) pCmdThread;
352} IOMMUR3;
353/** Pointer to the ring-3 IOMMU device state. */
354typedef IOMMUR3 *PIOMMUR3;
355
356/**
357 * The ring-0 IOMMU device state.
358 */
359typedef struct IOMMUR0
360{
361 /** Device instance. */
362 PPDMDEVINSR0 pDevInsR0;
363 /** The IOMMU helpers. */
364 PCPDMIOMMUHLPR0 pIommuHlpR0;
365} IOMMUR0;
366/** Pointer to the ring-0 IOMMU device state. */
367typedef IOMMUR0 *PIOMMUR0;
368
369/**
370 * The raw-mode IOMMU device state.
371 */
372typedef struct IOMMURC
373{
374 /** Device instance. */
375 PPDMDEVINSR0 pDevInsRC;
376 /** The IOMMU helpers. */
377 PCPDMIOMMUHLPRC pIommuHlpRC;
378} IOMMURC;
379/** Pointer to the raw-mode IOMMU device state. */
380typedef IOMMURC *PIOMMURC;
381
382/** The IOMMU device state for the current context. */
383typedef CTX_SUFF(IOMMU) IOMMUCC;
384/** Pointer to the IOMMU device state for the current context. */
385typedef CTX_SUFF(PIOMMU) PIOMMUCC;
386
387/**
388 * IOMMU register access.
389 */
390typedef struct IOMMUREGACC
391{
392 const char *pszName;
393 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
394 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
395 uint8_t cb;
396} IOMMUREGACC;
397/** Pointer to an IOMMU register access. */
398typedef IOMMUREGACC *PIOMMUREGACC;
399/** Pointer to a const IOMMU register access. */
400typedef IOMMUREGACC const *PCIOMMUREGACC;
401
402
403/*********************************************************************************************************************************
404* Global Variables *
405*********************************************************************************************************************************/
406/**
407 * An array of the number of device table segments supported.
408 * Indexed by u2DevTabSegSup.
409 */
410static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
411
412/**
413 * An array of the masks to select the device table segment index from a device ID.
414 */
415static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
416
417/**
418 * An array of the shift values to select the device table segment index from a
419 * device ID.
420 */
421static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
422
423/**
424 * The maximum size (inclusive) of each device table segment (0 to 7).
425 * Indexed by the device table segment index.
426 */
427static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
428
429
430#ifndef VBOX_DEVICE_STRUCT_TESTCASE
431/**
432 * Gets the maximum number of buffer entries for the given buffer length.
433 *
434 * @returns Number of buffer entries.
435 * @param uEncodedLen The length (power-of-2 encoded).
436 */
437DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
438{
439 Assert(uEncodedLen > 7);
440 return 2 << (uEncodedLen - 1);
441}
442
443
444/**
445 * Gets the total length of the buffer given a base register's encoded length.
446 *
447 * @returns The length of the buffer in bytes.
448 * @param uEncodedLen The length (power-of-2 encoded).
449 */
450DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
451{
452 Assert(uEncodedLen > 7);
453 return (2 << (uEncodedLen - 1)) << 4;
454}
455
456
457/**
458 * Gets the number of (unconsumed) entries in the event log.
459 *
460 * @returns The number of entries in the event log.
461 * @param pThis The IOMMU device state.
462 */
463static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
464{
465 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
466 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
467 if (idxTail >= idxHead)
468 return idxTail - idxHead;
469
470 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
471 return cMaxEvts - idxHead + idxTail;
472}
473
474
475/**
476 * Gets the number of (unconsumed) commands in the command buffer.
477 *
478 * @returns The number of commands in the command buffer.
479 * @param pThis The IOMMU device state.
480 */
481static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
482{
483 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
484 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
485 if (idxTail >= idxHead)
486 return idxTail - idxHead;
487
488 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
489 return cMaxCmds - idxHead + idxTail;
490}
491
492
493DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
494{
495 IOMMU_STATUS_T Status;
496 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
497 return Status;
498}
499
500
501DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
502{
503 IOMMU_CTRL_T Ctrl;
504 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
505 return Ctrl;
506}
507
508
509/**
510 * Returns whether MSI is enabled for the IOMMU.
511 *
512 * @returns Whether MSI is enabled.
513 * @param pDevIns The IOMMU device instance.
514 *
515 * @note There should be a PCIDevXxx function for this.
516 */
517static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
518{
519 MSI_CAP_HDR_T MsiCapHdr;
520 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
521 return MsiCapHdr.n.u1MsiEnable;
522}
523
524
525/**
526 * Signals a PCI target abort.
527 *
528 * @param pDevIns The IOMMU device instance.
529 */
530static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
531{
532 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
533 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
534 PDMPciDevSetStatus(pPciDev, u16Status);
535}
536
537
538/**
539 * Wakes up the command thread if there are commands to be processed or if
540 * processing is requested to be stopped by software.
541 *
542 * @param pDevIns The IOMMU device instance.
543 */
544static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
545{
546 IOMMU_ASSERT_LOCKED(pDevIns);
547 Log5Func(("\n"));
548
549 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
550 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
551 if (Status.n.u1CmdBufRunning)
552 {
553 Log5Func(("Signaling command thread\n"));
554 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
555 }
556}
557
558
559/**
560 * Reads the Device Table Base Address Register.
561 */
562static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
563{
564 RT_NOREF(pDevIns, offReg);
565 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
566 return VINF_SUCCESS;
567}
568
569
570/**
571 * Reads the Command Buffer Base Address Register.
572 */
573static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
574{
575 RT_NOREF(pDevIns, offReg);
576 *pu64Value = pThis->CmdBufBaseAddr.u64;
577 return VINF_SUCCESS;
578}
579
580
581/**
582 * Reads the Event Log Base Address Register.
583 */
584static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
585{
586 RT_NOREF(pDevIns, offReg);
587 *pu64Value = pThis->EvtLogBaseAddr.u64;
588 return VINF_SUCCESS;
589}
590
591
592/**
593 * Reads the Control Register.
594 */
595static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
596{
597 RT_NOREF(pDevIns, offReg);
598 *pu64Value = pThis->Ctrl.u64;
599 return VINF_SUCCESS;
600}
601
602
603/**
604 * Reads the Exclusion Range Base Address Register.
605 */
606static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
607{
608 RT_NOREF(pDevIns, offReg);
609 *pu64Value = pThis->ExclRangeBaseAddr.u64;
610 return VINF_SUCCESS;
611}
612
613
614/**
615 * Reads to the Exclusion Range Limit Register.
616 */
617static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
618{
619 RT_NOREF(pDevIns, offReg);
620 *pu64Value = pThis->ExclRangeLimit.u64;
621 return VINF_SUCCESS;
622}
623
624
625/**
626 * Reads to the Extended Feature Register.
627 */
628static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
629{
630 RT_NOREF(pDevIns, offReg);
631 *pu64Value = pThis->ExtFeat.u64;
632 return VINF_SUCCESS;
633}
634
635
636/**
637 * Reads to the PPR Log Base Address Register.
638 */
639static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
640{
641 RT_NOREF(pDevIns, offReg);
642 *pu64Value = pThis->PprLogBaseAddr.u64;
643 return VINF_SUCCESS;
644}
645
646
647/**
648 * Writes the Hardware Event Register (Hi).
649 */
650static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
651{
652 RT_NOREF(pDevIns, offReg);
653 *pu64Value = pThis->HwEvtHi.u64;
654 return VINF_SUCCESS;
655}
656
657
658/**
659 * Reads the Hardware Event Register (Lo).
660 */
661static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
662{
663 RT_NOREF(pDevIns, offReg);
664 *pu64Value = pThis->HwEvtLo;
665 return VINF_SUCCESS;
666}
667
668
669/**
670 * Reads the Hardware Event Status Register.
671 */
672static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
673{
674 RT_NOREF(pDevIns, offReg);
675 *pu64Value = pThis->HwEvtStatus.u64;
676 return VINF_SUCCESS;
677}
678
679
680/**
681 * Reads to the GA Log Base Address Register.
682 */
683static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
684{
685 RT_NOREF(pDevIns, offReg);
686 *pu64Value = pThis->GALogBaseAddr.u64;
687 return VINF_SUCCESS;
688}
689
690
691/**
692 * Reads to the PPR Log B Base Address Register.
693 */
694static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
695{
696 RT_NOREF(pDevIns, offReg);
697 *pu64Value = pThis->PprLogBBaseAddr.u64;
698 return VINF_SUCCESS;
699}
700
701
702/**
703 * Reads to the Event Log B Base Address Register.
704 */
705static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
706{
707 RT_NOREF(pDevIns, offReg);
708 *pu64Value = pThis->EvtLogBBaseAddr.u64;
709 return VINF_SUCCESS;
710}
711
712
713/**
714 * Reads the Device Table Segment Base Address Register.
715 */
716static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
717{
718 RT_NOREF(pDevIns);
719
720 /* Figure out which segment is being written. */
721 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
722 uint8_t const idxSegment = offSegment + 1;
723 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
724
725 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
726 return VINF_SUCCESS;
727}
728
729
730/**
731 * Reads the Device Specific Feature Extension (DSFX) Register.
732 */
733static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
734{
735 RT_NOREF(pDevIns, offReg);
736 *pu64Value = pThis->DevSpecificFeat.u64;
737 return VINF_SUCCESS;
738}
739
740/**
741 * Reads the Device Specific Control Extension (DSCX) Register.
742 */
743static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
744{
745 RT_NOREF(pDevIns, offReg);
746 *pu64Value = pThis->DevSpecificCtrl.u64;
747 return VINF_SUCCESS;
748}
749
750
751/**
752 * Reads the Device Specific Status Extension (DSSX) Register.
753 */
754static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
755{
756 RT_NOREF(pDevIns, offReg);
757 *pu64Value = pThis->DevSpecificStatus.u64;
758 return VINF_SUCCESS;
759}
760
761
762/**
763 * Reads the MSI Vector Register 0 (32-bit) or the MSI Vector Register 1 (32-bit).
764 */
765static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
766{
767 RT_NOREF(pDevIns, offReg);
768 if (offReg == IOMMU_MMIO_OFF_MSI_VECTOR_0)
769 *pu64Value = pThis->MiscInfo.au32[0];
770 else
771 {
772 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_VECTOR_1, ("%#x\n", offReg));
773 *pu64Value = pThis->MiscInfo.au32[1];
774 }
775 return VINF_SUCCESS;
776}
777
778
779#ifdef IOMMU_NEW_REGISTER_ACCESS
780/**
781 * Reads the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
782 * Register (32-bit).
783 */
784static VBOXSTRICTRC iommuAmdMsiCapHdrOrAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
785{
786 RT_NOREF(pThis);
787 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
788 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
789 if (offReg == IOMMU_MMIO_OFF_MSI_CAP_HDR)
790 *pu64Value = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
791 else
792 {
793 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_ADDR_LO, ("%#x\n", offReg));
794 *pu64Value = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
795 }
796 return VINF_SUCCESS;
797}
798
799
800/**
801 * Reads the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
802 */
803static VBOXSTRICTRC iommuAmdMsiAddrHiOrData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
804{
805 RT_NOREF(pThis);
806 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
807 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
808
809 if (offReg == IOMMU_MMIO_OFF_MSI_ADDR_HI)
810 *pu64Value = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
811 else
812 {
813 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_DATA, ("%#x\n", offReg));
814 *pu64Value = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
815 }
816 return VINF_SUCCESS;
817}
818#endif
819
820/**
821 * Reads the Command Buffer Head Pointer Register.
822 */
823static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
824{
825 RT_NOREF(pDevIns, offReg);
826 *pu64Value = pThis->CmdBufHeadPtr.u64;
827 return VINF_SUCCESS;
828}
829
830
831/**
832 * Reads the Command Buffer Tail Pointer Register.
833 */
834static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
835{
836 RT_NOREF(pDevIns, offReg);
837 *pu64Value = pThis->CmdBufTailPtr.u64;
838 return VINF_SUCCESS;
839}
840
841
842/**
843 * Reads the Event Log Head Pointer Register.
844 */
845static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
846{
847 RT_NOREF(pDevIns, offReg);
848 *pu64Value = pThis->EvtLogHeadPtr.u64;
849 return VINF_SUCCESS;
850}
851
852
853/**
854 * Reads the Event Log Tail Pointer Register.
855 */
856static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
857{
858 RT_NOREF(pDevIns, offReg);
859 *pu64Value = pThis->EvtLogTailPtr.u64;
860 return VINF_SUCCESS;
861}
862
863
864/**
865 * Reads the Status Register.
866 */
867static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
868{
869 RT_NOREF(pDevIns, offReg);
870 *pu64Value = pThis->Status.u64;
871 return VINF_SUCCESS;
872}
873
874#ifndef IOMMU_NEW_REGISTER_ACCESS
875static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
876{
877 RT_NOREF(pDevIns, pThis, offReg, u64Value);
878 return VINF_SUCCESS;
879}
880#endif
881
882
883/**
884 * Writes the Device Table Base Address Register.
885 */
886static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
887{
888 RT_NOREF(pDevIns, offReg);
889
890 /* Mask out all unrecognized bits. */
891 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
892
893 /* Update the register. */
894 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
895 return VINF_SUCCESS;
896}
897
898
899/**
900 * Writes the Command Buffer Base Address Register.
901 */
902static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
903{
904 RT_NOREF(pDevIns, offReg);
905
906 /*
907 * While this is not explicitly specified like the event log base address register,
908 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
909 * Inconsistent specs :/
910 */
911 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
912 if (Status.n.u1CmdBufRunning)
913 {
914 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
915 return VINF_SUCCESS;
916 }
917
918 /* Mask out all unrecognized bits. */
919 CMD_BUF_BAR_T CmdBufBaseAddr;
920 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
921
922 /* Validate the length. */
923 if (CmdBufBaseAddr.n.u4Len >= 8)
924 {
925 /* Update the register. */
926 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
927
928 /*
929 * Writing the command buffer base address, clears the command buffer head and tail pointers.
930 * See AMD spec. 2.4 "Commands".
931 */
932 pThis->CmdBufHeadPtr.u64 = 0;
933 pThis->CmdBufTailPtr.u64 = 0;
934 }
935 else
936 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
937
938 return VINF_SUCCESS;
939}
940
941
942/**
943 * Writes the Event Log Base Address Register.
944 */
945static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
946{
947 RT_NOREF(pDevIns, offReg);
948
949 /*
950 * IOMMU behavior is undefined when software writes this register when event logging is running.
951 * In our emulation, we ignore the write entirely.
952 * See AMD IOMMU spec. "Event Log Base Address Register".
953 */
954 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
955 if (Status.n.u1EvtLogRunning)
956 {
957 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
958 return VINF_SUCCESS;
959 }
960
961 /* Mask out all unrecognized bits. */
962 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
963 EVT_LOG_BAR_T EvtLogBaseAddr;
964 EvtLogBaseAddr.u64 = u64Value;
965
966 /* Validate the length. */
967 if (EvtLogBaseAddr.n.u4Len >= 8)
968 {
969 /* Update the register. */
970 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
971
972 /*
973 * Writing the event log base address, clears the event log head and tail pointers.
974 * See AMD spec. 2.5 "Event Logging".
975 */
976 pThis->EvtLogHeadPtr.u64 = 0;
977 pThis->EvtLogTailPtr.u64 = 0;
978 }
979 else
980 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
981
982 return VINF_SUCCESS;
983}
984
985
986/**
987 * Writes the Control Register.
988 */
989static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
990{
991 RT_NOREF(pDevIns, offReg);
992
993 /* Mask out all unrecognized bits. */
994 u64Value &= IOMMU_CTRL_VALID_MASK;
995 IOMMU_CTRL_T NewCtrl;
996 NewCtrl.u64 = u64Value;
997
998 /* Ensure the device table segments are within limits. */
999 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
1000 {
1001 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
1002
1003 /* Update the register. */
1004 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
1005
1006 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
1007 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
1008
1009 /* Enable or disable event logging when the bit transitions. */
1010 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
1011 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1012 if ( fOldEvtLogEn != fNewEvtLogEn
1013 || fOldIommuEn != fNewIommuEn)
1014 {
1015 if ( fNewIommuEn
1016 && fNewEvtLogEn)
1017 {
1018 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1019 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1020 }
1021 else
1022 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1023 }
1024
1025 /* Enable or disable command buffer processing when the bit transitions. */
1026 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1027 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1028 if ( fOldCmdBufEn != fNewCmdBufEn
1029 || fOldIommuEn != fNewIommuEn)
1030 {
1031 if ( fNewCmdBufEn
1032 && fNewIommuEn)
1033 {
1034 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1035 LogFunc(("Command buffer enabled\n"));
1036
1037 /* Wake up the command thread to start processing commands. */
1038 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1039 }
1040 else
1041 {
1042 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1043 LogFunc(("Command buffer disabled\n"));
1044 }
1045 }
1046 }
1047 else
1048 {
1049 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1050 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1051 }
1052
1053 return VINF_SUCCESS;
1054}
1055
1056
1057/**
1058 * Writes to the Exclusion Range Base Address Register.
1059 */
1060static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1061{
1062 RT_NOREF(pDevIns, offReg);
1063 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1064 return VINF_SUCCESS;
1065}
1066
1067
1068/**
1069 * Writes to the Exclusion Range Limit Register.
1070 */
1071static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1072{
1073 RT_NOREF(pDevIns, offReg);
1074 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1075 u64Value |= UINT64_C(0xfff);
1076 pThis->ExclRangeLimit.u64 = u64Value;
1077 return VINF_SUCCESS;
1078}
1079
1080
1081/**
1082 * Writes the Hardware Event Register (Hi).
1083 */
1084static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1085{
1086 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1087 RT_NOREF(pDevIns, offReg);
1088 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1089 pThis->HwEvtHi.u64 = u64Value;
1090 return VINF_SUCCESS;
1091}
1092
1093
1094/**
1095 * Writes the Hardware Event Register (Lo).
1096 */
1097static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1098{
1099 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1100 RT_NOREF(pDevIns, offReg);
1101 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1102 pThis->HwEvtLo = u64Value;
1103 return VINF_SUCCESS;
1104}
1105
1106
1107/**
1108 * Writes the Hardware Event Status Register.
1109 */
1110static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1111{
1112 RT_NOREF(pDevIns, offReg);
1113
1114 /* Mask out all unrecognized bits. */
1115 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1116
1117 /*
1118 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1119 * If the current status bits or the bits being written are both 0, we've nothing to do.
1120 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1121 */
1122 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1123 if (!(HwStatus & RT_BIT(0)))
1124 return VINF_SUCCESS;
1125 if (u64Value & HwStatus & RT_BIT_64(0))
1126 HwStatus &= ~RT_BIT_64(0);
1127 if (u64Value & HwStatus & RT_BIT_64(1))
1128 HwStatus &= ~RT_BIT_64(1);
1129
1130 /* Update the register. */
1131 pThis->HwEvtStatus.u64 = HwStatus;
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/**
1137 * Writes the Device Table Segment Base Address Register.
1138 */
1139static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1140{
1141 RT_NOREF(pDevIns);
1142
1143 /* Figure out which segment is being written. */
1144 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1145 uint8_t const idxSegment = offSegment + 1;
1146 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1147
1148 /* Mask out all unrecognized bits. */
1149 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1150 DEV_TAB_BAR_T DevTabSegBar;
1151 DevTabSegBar.u64 = u64Value;
1152
1153 /* Validate the size. */
1154 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1155 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1156 if (uSegSize <= uMaxSegSize)
1157 {
1158 /* Update the register. */
1159 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1160 }
1161 else
1162 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1163
1164 return VINF_SUCCESS;
1165}
1166
1167
1168#ifndef IOMMU_NEW_REGISTER_ACCESS
1169/**
1170 * Writes the MSI Capability Header Register.
1171 */
1172static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1173{
1174 RT_NOREF(pThis, offReg);
1175 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1176 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1177 MSI_CAP_HDR_T MsiCapHdr;
1178 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1179 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1180 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1181 return VINF_SUCCESS;
1182}
1183
1184
1185/**
1186 * Writes the MSI Address (Lo) Register (32-bit).
1187 */
1188static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1189{
1190 RT_NOREF(pThis, offReg);
1191 Assert(!RT_HI_U32(u64Value));
1192 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1193 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1194 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
1195 return VINF_SUCCESS;
1196}
1197
1198
1199/**
1200 * Writes the MSI Address (Hi) Register (32-bit).
1201 */
1202static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1203{
1204 RT_NOREF(pThis, offReg);
1205 Assert(!RT_HI_U32(u64Value));
1206 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1207 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1208 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
1209 return VINF_SUCCESS;
1210}
1211
1212
1213/**
1214 * Writes the MSI Data Register (32-bit).
1215 */
1216static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1217{
1218 RT_NOREF(pThis, offReg);
1219 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1220 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1221 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
1222 return VINF_SUCCESS;
1223}
1224#else
1225/**
1226 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1227 * Register (32-bit).
1228 */
1229static VBOXSTRICTRC iommuAmdMsiCapHdrOrAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1230{
1231 RT_NOREF(pThis);
1232 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1233 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1234 if (offReg == IOMMU_MMIO_OFF_MSI_CAP_HDR)
1235 {
1236 /* MsiMultMessEn not supported, so only MsiEn is the writable bit. */
1237 MSI_CAP_HDR_T MsiCapHdr;
1238 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1239 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1240 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1241 }
1242 else
1243 {
1244 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_ADDR_LO, ("%#x\n", offReg));
1245 uint32_t const uMsiAddrLo = u64Value & VBOX_MSI_ADDR_VALID_MASK;
1246 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1247 }
1248 return VINF_SUCCESS;
1249}
1250
1251
1252/**
1253 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1254 */
1255static VBOXSTRICTRC iommuAmdMsiAddrHiOrData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1256{
1257 RT_NOREF(pThis);
1258 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1259 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1260 if (offReg == IOMMU_MMIO_OFF_MSI_ADDR_HI)
1261 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
1262 else
1263 {
1264 AssertMsg(offReg == IOMMU_MMIO_OFF_MSI_DATA, ("%#x\n", offReg));
1265 uint32_t const uMsiData = u64Value & VBOX_MSI_DATA_VALID_MASK;
1266 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1267 }
1268 return VINF_SUCCESS;
1269}
1270#endif
1271
1272
1273/**
1274 * Writes the Command Buffer Head Pointer Register.
1275 */
1276static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1277{
1278 RT_NOREF(pDevIns, offReg);
1279
1280 /*
1281 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1282 * In our emulation, we ignore the write entirely.
1283 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1284 */
1285 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1286 if (Status.n.u1CmdBufRunning)
1287 {
1288 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1289 return VINF_SUCCESS;
1290 }
1291
1292 /*
1293 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1294 * In our emulation, we ignore the write entirely.
1295 */
1296 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1297 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1298 Assert(cbBuf <= _512K);
1299 if (offBuf >= cbBuf)
1300 {
1301 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1302 return VINF_SUCCESS;
1303 }
1304
1305 /* Update the register. */
1306 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1307
1308 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1309
1310 Log5Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1311 return VINF_SUCCESS;
1312}
1313
1314
1315/**
1316 * Writes the Command Buffer Tail Pointer Register.
1317 */
1318static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1319{
1320 RT_NOREF(pDevIns, offReg);
1321
1322 /*
1323 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1324 * In our emulation, we ignore the write entirely.
1325 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1326 */
1327 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1328 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1329 Assert(cbBuf <= _512K);
1330 if (offBuf >= cbBuf)
1331 {
1332 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1333 return VINF_SUCCESS;
1334 }
1335
1336 /*
1337 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1338 * head pointer after adding one or more commands to the buffer.
1339 *
1340 * However, we cannot enforce this strictly because it's legal for software to shrink the
1341 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1342 * at 0). Software might even make the queue empty by making head and tail equal which is
1343 * allowed. I don't think we can or should try too hard to prevent software shooting itself
1344 * in the foot here. As long as we make sure the offset value is within the circular buffer
1345 * bounds (which we do by masking bits above) it should be sufficient.
1346 */
1347 pThis->CmdBufTailPtr.au32[0] = offBuf;
1348
1349 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1350
1351 Log5Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1352 return VINF_SUCCESS;
1353}
1354
1355
1356/**
1357 * Writes the Event Log Head Pointer Register.
1358 */
1359static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1360{
1361 RT_NOREF(pDevIns, offReg);
1362
1363 /*
1364 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1365 * In our emulation, we ignore the write entirely.
1366 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1367 */
1368 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1369 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1370 Assert(cbBuf <= _512K);
1371 if (offBuf >= cbBuf)
1372 {
1373 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1374 return VINF_SUCCESS;
1375 }
1376
1377 /* Update the register. */
1378 pThis->EvtLogHeadPtr.au32[0] = offBuf;
1379
1380 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1381 return VINF_SUCCESS;
1382}
1383
1384
1385/**
1386 * Writes the Event Log Tail Pointer Register.
1387 */
1388static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1389{
1390 RT_NOREF(pDevIns, offReg);
1391 NOREF(pThis);
1392
1393 /*
1394 * IOMMU behavior is undefined when software writes this register when the event log is running.
1395 * In our emulation, we ignore the write entirely.
1396 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1397 */
1398 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1399 if (Status.n.u1EvtLogRunning)
1400 {
1401 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1402 return VINF_SUCCESS;
1403 }
1404
1405 /*
1406 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1407 * In our emulation, we ignore the write entirely.
1408 */
1409 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1410 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1411 Assert(cbBuf <= _512K);
1412 if (offBuf >= cbBuf)
1413 {
1414 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1415 return VINF_SUCCESS;
1416 }
1417
1418 /* Update the register. */
1419 pThis->EvtLogTailPtr.au32[0] = offBuf;
1420
1421 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1422 return VINF_SUCCESS;
1423}
1424
1425
1426/**
1427 * Writes the Status Register.
1428 */
1429static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1430{
1431 RT_NOREF(pDevIns, offReg);
1432
1433 /* Mask out all unrecognized bits. */
1434 u64Value &= IOMMU_STATUS_VALID_MASK;
1435
1436 /*
1437 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1438 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1439 */
1440 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1441 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1442 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1443 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1444
1445 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1446
1447 /* Update the register. */
1448 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1449 return VINF_SUCCESS;
1450}
1451
1452#ifdef IOMMU_NEW_REGISTER_ACCESS
1453/**
1454 * Register access table 0.
1455 * The MMIO offset of each entry must be a multiple of 8!
1456 */
1457static const IOMMUREGACC g_aRegAccess0[] =
1458{
1459 /* MMIO off. Register name Read function Write function Reg. size */
1460 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w, 8 },
1461 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w, 8 },
1462 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w, 8 },
1463 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w, 8 },
1464 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w, 8 },
1465 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w, 8 },
1466 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL, 8 },
1467 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL, 8 },
1468 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w, 8 },
1469 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w, 8 },
1470 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w, 8 },
1471 { /* 0x58 */ NULL, NULL, NULL, 0 },
1472
1473 { /* 0x60 */ "SMI_FLT_0", NULL, NULL, 8 },
1474 { /* 0x68 */ "SMI_FLT_1", NULL, NULL, 8 },
1475 { /* 0x70 */ "SMI_FLT_2", NULL, NULL, 8 },
1476 { /* 0x78 */ "SMI_FLT_3", NULL, NULL, 8 },
1477 { /* 0x80 */ "SMI_FLT_4", NULL, NULL, 8 },
1478 { /* 0x88 */ "SMI_FLT_5", NULL, NULL, 8 },
1479 { /* 0x90 */ "SMI_FLT_6", NULL, NULL, 8 },
1480 { /* 0x98 */ "SMI_FLT_7", NULL, NULL, 8 },
1481 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL, 8 },
1482 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL, 8 },
1483 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL, 8 },
1484 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL, 8 },
1485 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL, 8 },
1486 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL, 8 },
1487 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL, 8 },
1488 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL, 8 },
1489
1490 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL, 8 },
1491 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL, 8 },
1492 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL, 8 },
1493 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL, 8 },
1494
1495 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1496 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1497 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1498 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1499 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1500 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1501 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w, 8 },
1502
1503 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL, 8 },
1504 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL, 8 },
1505 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL, 8 },
1506
1507 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, NULL, 4 },
1508 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrOrAddrLo_r, iommuAmdMsiCapHdrOrAddrLo_w, 4 },
1509 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiOrData_r, iommuAmdMsiAddrHiOrData_w, 4 },
1510 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL, 4 },
1511
1512 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL, 8 },
1513 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL, 8 },
1514 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL, 8 },
1515};
1516AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1517
1518/**
1519 * Register access table 1.
1520 * The MMIO offset of each entry must be a multiple of 8!
1521 */
1522static const IOMMUREGACC g_aRegAccess1[] =
1523{
1524 /* MMIO offset Register name Read function Write function Register size. */
1525 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL, 8 },
1526 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL, 8 },
1527 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL, 8 },
1528 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL, 8 },
1529 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL, 8 },
1530 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL, 8 },
1531 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL, 8 },
1532 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL, 8 },
1533 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL, 8 },
1534 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL, 8 },
1535 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL, 8 },
1536 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL, 8 }
1537};
1538AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1539
1540/**
1541 * Register access table 2.
1542 * The MMIO offset of each entry must be a multiple of 8!
1543 */
1544static const IOMMUREGACC g_aRegAccess2[] =
1545{
1546 /* MMIO offset Register name Read Function Write function Register size (bytes) */
1547 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL, 8 },
1548
1549 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w, 8 },
1550 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w, 8 },
1551 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w, 8 },
1552 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w, 8 },
1553
1554 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w, 8 },
1555 { /* 0x2028 */ NULL, NULL, NULL, 0 },
1556
1557 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL, 8 },
1558 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL, 8 },
1559
1560 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL, 8 },
1561 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL, 8 },
1562
1563 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL, 8 },
1564 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL, 8 },
1565
1566 { /* 0x2060 */ NULL, NULL, NULL, 0 },
1567 { /* 0x2068 */ NULL, NULL, NULL, 0 },
1568
1569 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL, 8 },
1570 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL, 8 },
1571
1572 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL, 8 },
1573 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL, 8 },
1574 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL, 8 }
1575};
1576AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1577
1578
1579/**
1580 * Gets the register access structure given its MMIO offset.
1581 *
1582 * @returns The register access structure, or NULL if the offset is invalid.
1583 * @param off The MMIO offset of the register being accessed.
1584 */
1585static PCIOMMUREGACC iommuAmdGetRegAccessForOffset(uint32_t off)
1586{
1587 /* Figure out which table the register belongs to and validate its index. */
1588 PCIOMMUREGACC pReg;
1589 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1590 {
1591 uint32_t const idxReg = off >> 3;
1592 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1593 pReg = &g_aRegAccess0[idxReg];
1594 }
1595 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1596 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1597 {
1598 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1599 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1600 pReg = &g_aRegAccess1[idxReg];
1601 }
1602 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1603 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1604 {
1605 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1606 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1607 pReg = &g_aRegAccess2[idxReg];
1608 }
1609 else
1610 return NULL;
1611
1612 return pReg;
1613}
1614#endif
1615
1616
1617/**
1618 * Writes an IOMMU register (32-bit and 64-bit).
1619 *
1620 * @returns Strict VBox status code.
1621 * @param pDevIns The IOMMU device instance.
1622 * @param off MMIO byte offset to the register.
1623 * @param cb The size of the write access.
1624 * @param uValue The value being written.
1625 *
1626 * @thread EMT.
1627 */
1628static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1629{
1630 /*
1631 * Validate the access in case of IOM bug or incorrect assumption.
1632 */
1633 Assert(off < IOMMU_MMIO_REGION_SIZE);
1634 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1635 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1636
1637 Log5Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1638
1639 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1640#ifndef IOMMU_NEW_REGISTER_ACCESS
1641 switch (off)
1642 {
1643 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1644 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1645 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1646 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1647 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1648 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1649 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1650
1651 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1652 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1653 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1654 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1655
1656 case IOMMU_MMIO_OFF_GALOG_BAR:
1657 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1658
1659 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1660 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1661
1662 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1663 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1664 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1665 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1666 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1667 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1668 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1669
1670 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1671 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1672 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1673
1674 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1675 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1676 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1677 {
1678 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1679 if (cb == 4 || RT_FAILURE(rcStrict))
1680 return rcStrict;
1681 uValue >>= 32;
1682 RT_FALL_THRU();
1683 }
1684 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1685 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1686 {
1687 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1688 if (cb == 4 || RT_FAILURE(rcStrict))
1689 return rcStrict;
1690 uValue >>= 32;
1691 RT_FALL_THRU();
1692 }
1693 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1694 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1695
1696 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1697
1698 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1699 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1700 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1701
1702 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1703 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1704 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1705 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1706 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1707 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1708 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1709 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1710 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1711 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1712 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1713 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1714
1715 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1716
1717 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1718 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1719 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1720 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1721
1722 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1723
1724 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1725 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1726
1727 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1728 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1729
1730 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1731 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1732
1733 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1734 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1735
1736 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1737 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1738 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1739
1740 /* Not implemented. */
1741 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1742 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1743 {
1744 LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1745 return VINF_SUCCESS;
1746 }
1747
1748 /* Unknown. */
1749 default:
1750 {
1751 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1752 return VINF_SUCCESS;
1753 }
1754 }
1755#else
1756 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1757 if (pReg)
1758 { /* likely */ }
1759 else
1760 {
1761 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1762 return VINF_SUCCESS;
1763 }
1764
1765 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
1766 if (pReg->pfnWrite)
1767 { /* likely */ }
1768 else
1769 {
1770 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1771 return VINF_SUCCESS;
1772 }
1773
1774 /*
1775 * If the write access is aligned and matches the register size, dispatch right away.
1776 * This handles all aligned, 32-bit writes as well as aligned 64-bit writes.
1777 */
1778 if ( cb == pReg->cb
1779 && !(off & (cb - 1)))
1780 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1781
1782 /*
1783 * A 32-bit write for a 64-bit register.
1784 * We shouldn't get sizes other than 32 bits here as we've specified so with IOM.
1785 */
1786 Assert(cb == 4);
1787 if (!(off & 7))
1788 {
1789 /*
1790 * Lower 32 bits of the register is being written.
1791 * Merge with higher 32 bits (after reading the full value from the register).
1792 */
1793 uint64_t u64Read;
1794 if (pReg->pfnRead)
1795 {
1796 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1797 if (RT_FAILURE(rcStrict))
1798 {
1799 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1800 return rcStrict;
1801 }
1802 }
1803 else
1804 u64Read = 0;
1805
1806 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
1807 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1808 }
1809
1810 /*
1811 * Higher 32 bits of the register is being written.
1812 * Merge with lower 32 bits (after reading the full value from the register).
1813 */
1814 Assert(!(off & 3));
1815 Assert(off & 7);
1816 Assert(off > 4);
1817 uint64_t u64Read;
1818 if (pReg->pfnRead)
1819 {
1820 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1821 if (RT_FAILURE(rcStrict))
1822 {
1823 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1824 return rcStrict;
1825 }
1826 }
1827 else
1828 u64Read = 0;
1829
1830 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
1831 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1832#endif
1833}
1834
1835
1836/**
1837 * Reads an IOMMU register (64-bit) given its MMIO offset.
1838 *
1839 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1840 * boundary include the lower half of the subsequent register.
1841 *
1842 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1843 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1844 * software will only perform 32-bit reads on those 32-bit registers that are
1845 * aligned on 8-byte boundaries.
1846 *
1847 * @returns Strict VBox status code.
1848 * @param pDevIns The IOMMU device instance.
1849 * @param off The MMIO offset of the register in bytes.
1850 * @param puResult Where to store the value being read.
1851 *
1852 * @thread EMT.
1853 */
1854static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1855{
1856 Assert(off < IOMMU_MMIO_REGION_SIZE);
1857 Assert(!(off & 7) || !(off & 3));
1858
1859 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1860 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1861 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1862
1863 Log5Func(("off=%#x\n", off));
1864
1865 /** @todo IOMMU: fine-grained locking? */
1866 uint64_t uReg;
1867 switch (off)
1868 {
1869 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1870 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1871 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1872 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1873 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1874 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1875 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1876
1877 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1878 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1879 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1880 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1881
1882 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1883 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1884
1885 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1886 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1887
1888 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1889 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1890 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1891 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1892 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1893 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1894 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1895 {
1896 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1897 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1898 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1899 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1900 break;
1901 }
1902
1903 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1904 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1905 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1906
1907 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1908 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1909 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1910 {
1911 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1912 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1913 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1914 break;
1915 }
1916 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1917 {
1918 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1919 break;
1920 }
1921 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1922 {
1923 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1924 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1925 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1926 break;
1927 }
1928 case IOMMU_MMIO_OFF_MSI_DATA:
1929 {
1930 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1931 break;
1932 }
1933 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1934 {
1935 /*
1936 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1937 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1938 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1939 * 0 for this register.
1940 */
1941 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1942 break;
1943 }
1944
1945 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1946
1947 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1948 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1949 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1950
1951 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1952 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1953 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1954 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1955 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1956 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1957 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1958 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1959 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1960 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1961 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1962 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1963
1964 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1965
1966 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1967 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1968 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1969 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1970
1971 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
1972
1973 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
1974 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
1975
1976 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
1977 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
1978
1979 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
1980 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
1981
1982 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
1983 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
1984
1985 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
1986 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
1987 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
1988
1989 /* Not implemented. */
1990 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1991 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1992 {
1993 LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1994 uReg = 0;
1995 break;
1996 }
1997
1998 /* Unknown. */
1999 default:
2000 {
2001 LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
2002 uReg = 0;
2003 return VINF_IOM_MMIO_UNUSED_00;
2004 }
2005 }
2006
2007 *puResult = uReg;
2008 return VINF_SUCCESS;
2009}
2010
2011
2012/**
2013 * Raises the MSI interrupt for the IOMMU device.
2014 *
2015 * @param pDevIns The IOMMU device instance.
2016 *
2017 * @thread Any.
2018 * @remarks The IOMMU lock may or may not be held.
2019 */
2020static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
2021{
2022 LogFlowFunc(("\n"));
2023 if (iommuAmdIsMsiEnabled(pDevIns))
2024 {
2025 LogFunc(("Raising MSI\n"));
2026 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2027 }
2028}
2029
2030
2031/**
2032 * Clears the MSI interrupt for the IOMMU device.
2033 *
2034 * @param pDevIns The IOMMU device instance.
2035 *
2036 * @thread Any.
2037 * @remarks The IOMMU lock may or may not be held.
2038 */
2039static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
2040{
2041 if (iommuAmdIsMsiEnabled(pDevIns))
2042 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2043}
2044
2045
2046/**
2047 * Writes an entry to the event log in memory.
2048 *
2049 * @returns VBox status code.
2050 * @param pDevIns The IOMMU device instance.
2051 * @param pEvent The event to log.
2052 *
2053 * @thread Any.
2054 */
2055static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2056{
2057 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2058
2059 IOMMU_ASSERT_LOCKED(pDevIns);
2060
2061 /* Check if event logging is active and the log has not overflowed. */
2062 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2063 if ( Status.n.u1EvtLogRunning
2064 && !Status.n.u1EvtOverflow)
2065 {
2066 uint32_t const cbEvt = sizeof(*pEvent);
2067
2068 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2069 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2070 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2071
2072 /* Ensure we have space in the event log. */
2073 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2074 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2075 if (cEvts + 1 < cMaxEvts)
2076 {
2077 /* Write the event log entry to memory. */
2078 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2079 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2080 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2081 if (RT_FAILURE(rc))
2082 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2083
2084 /* Increment the event log tail pointer. */
2085 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2086 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2087
2088 /* Indicate that an event log entry was written. */
2089 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2090
2091 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2092 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2093 if (Ctrl.n.u1EvtIntrEn)
2094 iommuAmdRaiseMsiInterrupt(pDevIns);
2095 }
2096 else
2097 {
2098 /* Indicate that the event log has overflowed. */
2099 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2100
2101 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2102 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2103 if (Ctrl.n.u1EvtIntrEn)
2104 iommuAmdRaiseMsiInterrupt(pDevIns);
2105 }
2106 }
2107
2108 return VINF_SUCCESS;
2109}
2110
2111
2112/**
2113 * Sets an event in the hardware error registers.
2114 *
2115 * @param pDevIns The IOMMU device instance.
2116 * @param pEvent The event.
2117 *
2118 * @thread Any.
2119 */
2120static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2121{
2122 IOMMU_ASSERT_LOCKED(pDevIns);
2123
2124 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2125 if (pThis->ExtFeat.n.u1HwErrorSup)
2126 {
2127 if (pThis->HwEvtStatus.n.u1Valid)
2128 pThis->HwEvtStatus.n.u1Overflow = 1;
2129 pThis->HwEvtStatus.n.u1Valid = 1;
2130 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2131 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2132 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2133 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2134 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2135 }
2136}
2137
2138
2139/**
2140 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2141 *
2142 * @param uDevId The device ID.
2143 * @param uDomainId The domain ID.
2144 * @param GCPhysPtEntity The system physical address of the page table
2145 * entity.
2146 * @param enmOp The IOMMU operation being performed.
2147 * @param pEvtPageTabHwErr Where to store the initialized event.
2148 */
2149static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2150 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2151{
2152 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2153 pEvtPageTabHwErr->n.u16DevId = uDevId;
2154 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
2155 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
2156 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2157 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2158 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2159 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2160 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
2161 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
2162}
2163
2164
2165/**
2166 * Raises a PAGE_TAB_HARDWARE_ERROR event.
2167 *
2168 * @param pDevIns The IOMMU device instance.
2169 * @param enmOp The IOMMU operation being performed.
2170 * @param pEvtPageTabHwErr The page table hardware error event.
2171 *
2172 * @thread Any.
2173 */
2174static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2175{
2176 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
2177 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
2178
2179 IOMMU_LOCK_NORET(pDevIns);
2180
2181 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2182 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2183 if (enmOp != IOMMUOP_CMD)
2184 iommuAmdSetPciTargetAbort(pDevIns);
2185
2186 IOMMU_UNLOCK(pDevIns);
2187
2188 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
2189 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
2190 pEvtPageTabHwErr->n.u2Type));
2191}
2192
2193
2194/**
2195 * Initializes a COMMAND_HARDWARE_ERROR event.
2196 *
2197 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
2198 * @param pEvtCmdHwErr Where to store the initialized event.
2199 */
2200static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2201{
2202 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
2203 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
2204 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
2205 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
2206}
2207
2208
2209/**
2210 * Raises a COMMAND_HARDWARE_ERROR event.
2211 *
2212 * @param pDevIns The IOMMU device instance.
2213 * @param pEvtCmdHwErr The command hardware error event.
2214 *
2215 * @thread Any.
2216 */
2217static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2218{
2219 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
2220 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
2221 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2222
2223 IOMMU_LOCK_NORET(pDevIns);
2224
2225 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2226 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2227 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2228
2229 IOMMU_UNLOCK(pDevIns);
2230
2231 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
2232}
2233
2234
2235/**
2236 * Initializes a DEV_TAB_HARDWARE_ERROR event.
2237 *
2238 * @param uDevId The device ID.
2239 * @param GCPhysDte The system physical address of the failed device table
2240 * access.
2241 * @param enmOp The IOMMU operation being performed.
2242 * @param pEvtDevTabHwErr Where to store the initialized event.
2243 */
2244static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
2245 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2246{
2247 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
2248 pEvtDevTabHwErr->n.u16DevId = uDevId;
2249 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2250 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
2251 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2252 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2253 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2254 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
2255 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
2256}
2257
2258
2259/**
2260 * Raises a DEV_TAB_HARDWARE_ERROR event.
2261 *
2262 * @param pDevIns The IOMMU device instance.
2263 * @param enmOp The IOMMU operation being performed.
2264 * @param pEvtDevTabHwErr The device table hardware error event.
2265 *
2266 * @thread Any.
2267 */
2268static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2269{
2270 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2271 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2272
2273 IOMMU_LOCK_NORET(pDevIns);
2274
2275 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2276 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2277 if (enmOp != IOMMUOP_CMD)
2278 iommuAmdSetPciTargetAbort(pDevIns);
2279
2280 IOMMU_UNLOCK(pDevIns);
2281
2282 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2283 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2284}
2285
2286
2287/**
2288 * Initializes an ILLEGAL_COMMAND_ERROR event.
2289 *
2290 * @param GCPhysCmd The system physical address of the failed command
2291 * access.
2292 * @param pEvtIllegalCmd Where to store the initialized event.
2293 */
2294static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2295{
2296 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2297 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2298 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2299 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2300}
2301
2302
2303/**
2304 * Raises an ILLEGAL_COMMAND_ERROR event.
2305 *
2306 * @param pDevIns The IOMMU device instance.
2307 * @param pEvtIllegalCmd The illegal command error event.
2308 */
2309static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2310{
2311 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2312 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2313 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2314
2315 IOMMU_LOCK_NORET(pDevIns);
2316
2317 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2318 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2319
2320 IOMMU_UNLOCK(pDevIns);
2321
2322 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2323}
2324
2325
2326/**
2327 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2328 *
2329 * @param uDevId The device ID.
2330 * @param uIova The I/O virtual address.
2331 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2332 * event was caused by an invalid level encoding in the
2333 * DTE.
2334 * @param enmOp The IOMMU operation being performed.
2335 * @param pEvtIllegalDte Where to store the initialized event.
2336 */
2337static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2338 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2339{
2340 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2341 pEvtIllegalDte->n.u16DevId = uDevId;
2342 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2343 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2344 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2345 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2346 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2347 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2348 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2349 * IOMMU spec here but not for this field for I/O page fault event. */
2350 Assert(!(uIova & UINT64_C(0x3)));
2351}
2352
2353
2354/**
2355 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2356 *
2357 * @param pDevIns The IOMMU instance data.
2358 * @param enmOp The IOMMU operation being performed.
2359 * @param pEvtIllegalDte The illegal device table entry event.
2360 * @param enmEvtType The illegal device table entry event type.
2361 *
2362 * @thread Any.
2363 */
2364static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2365 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2366{
2367 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2368 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2369
2370 IOMMU_LOCK_NORET(pDevIns);
2371
2372 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2373 if (enmOp != IOMMUOP_CMD)
2374 iommuAmdSetPciTargetAbort(pDevIns);
2375
2376 IOMMU_UNLOCK(pDevIns);
2377
2378 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2379 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2380 NOREF(enmEvtType);
2381}
2382
2383
2384/**
2385 * Initializes an IO_PAGE_FAULT event.
2386 *
2387 * @param uDevId The device ID.
2388 * @param uDomainId The domain ID.
2389 * @param uIova The I/O virtual address being accessed.
2390 * @param fPresent Transaction to a page marked as present (including
2391 * DTE.V=1) or interrupt marked as remapped
2392 * (IRTE.RemapEn=1).
2393 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2394 * the I/O page fault was caused by invalid level
2395 * encoding.
2396 * @param fPermDenied Permission denied for the address being accessed.
2397 * @param enmOp The IOMMU operation being performed.
2398 * @param pEvtIoPageFault Where to store the initialized event.
2399 */
2400static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2401 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2402{
2403 Assert(!fPermDenied || fPresent);
2404 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2405 pEvtIoPageFault->n.u16DevId = uDevId;
2406 //pEvtIoPageFault->n.u4PasidHi = 0;
2407 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2408 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2409 //pEvtIoPageFault->n.u1NoExecute = 0;
2410 //pEvtIoPageFault->n.u1User = 0;
2411 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2412 pEvtIoPageFault->n.u1Present = fPresent;
2413 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2414 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2415 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2416 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2417 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2418 pEvtIoPageFault->n.u64Addr = uIova;
2419}
2420
2421
2422/**
2423 * Raises an IO_PAGE_FAULT event.
2424 *
2425 * @param pDevIns The IOMMU instance data.
2426 * @param pDte The device table entry. Optional, can be NULL
2427 * depending on @a enmOp.
2428 * @param pIrte The interrupt remapping table entry. Optional, can
2429 * be NULL depending on @a enmOp.
2430 * @param enmOp The IOMMU operation being performed.
2431 * @param pEvtIoPageFault The I/O page fault event.
2432 * @param enmEvtType The I/O page fault event type.
2433 *
2434 * @thread Any.
2435 */
2436static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2437 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2438{
2439 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2440 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2441
2442 IOMMU_LOCK_NORET(pDevIns);
2443
2444 bool fSuppressEvtLogging = false;
2445 if ( enmOp == IOMMUOP_MEM_READ
2446 || enmOp == IOMMUOP_MEM_WRITE)
2447 {
2448 if ( pDte
2449 && pDte->n.u1Valid)
2450 {
2451 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2452 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2453 * suppression. Perhaps will be possible when we complete IOTLB/cache
2454 * handling. */
2455 }
2456 }
2457 else if (enmOp == IOMMUOP_INTR_REQ)
2458 {
2459 if ( pDte
2460 && pDte->n.u1IntrMapValid)
2461 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2462
2463 if ( !fSuppressEvtLogging
2464 && pIrte)
2465 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2466 }
2467 /* else: Events are never suppressed for commands. */
2468
2469 switch (enmEvtType)
2470 {
2471 case kIoPageFaultType_PermDenied:
2472 {
2473 /* Cannot be triggered by a command. */
2474 Assert(enmOp != IOMMUOP_CMD);
2475 RT_FALL_THRU();
2476 }
2477 case kIoPageFaultType_DteRsvdPagingMode:
2478 case kIoPageFaultType_PteInvalidPageSize:
2479 case kIoPageFaultType_PteInvalidLvlEncoding:
2480 case kIoPageFaultType_SkippedLevelIovaNotZero:
2481 case kIoPageFaultType_PteRsvdNotZero:
2482 case kIoPageFaultType_PteValidNotSet:
2483 case kIoPageFaultType_DteTranslationDisabled:
2484 case kIoPageFaultType_PasidInvalidRange:
2485 {
2486 /*
2487 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2488 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
2489 */
2490 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2491 {
2492 if (!fSuppressEvtLogging)
2493 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2494 if (enmOp != IOMMUOP_CMD)
2495 iommuAmdSetPciTargetAbort(pDevIns);
2496 }
2497 break;
2498 }
2499
2500 case kIoPageFaultType_UserSupervisor:
2501 {
2502 /* Access is blocked and only creates an event log entry. */
2503 if (!fSuppressEvtLogging)
2504 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2505 break;
2506 }
2507
2508 case kIoPageFaultType_IrteAddrInvalid:
2509 case kIoPageFaultType_IrteRsvdNotZero:
2510 case kIoPageFaultType_IrteRemapEn:
2511 case kIoPageFaultType_IrteRsvdIntType:
2512 case kIoPageFaultType_IntrReqAborted:
2513 case kIoPageFaultType_IntrWithPasid:
2514 {
2515 /* Only trigerred by interrupt requests. */
2516 Assert(enmOp == IOMMUOP_INTR_REQ);
2517 if (!fSuppressEvtLogging)
2518 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2519 iommuAmdSetPciTargetAbort(pDevIns);
2520 break;
2521 }
2522
2523 case kIoPageFaultType_SmiFilterMismatch:
2524 {
2525 /* Not supported and probably will never be, assert. */
2526 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2527 break;
2528 }
2529
2530 case kIoPageFaultType_DevId_Invalid:
2531 {
2532 /* Cannot be triggered by a command. */
2533 Assert(enmOp != IOMMUOP_CMD);
2534 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2535 if (!fSuppressEvtLogging)
2536 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2537 if ( enmOp == IOMMUOP_MEM_READ
2538 || enmOp == IOMMUOP_MEM_WRITE)
2539 iommuAmdSetPciTargetAbort(pDevIns);
2540 break;
2541 }
2542 }
2543
2544 IOMMU_UNLOCK(pDevIns);
2545}
2546
2547
2548/**
2549 * Returns whether the I/O virtual address is to be excluded from translation and
2550 * permission checks.
2551 *
2552 * @returns @c true if the DVA is excluded, @c false otherwise.
2553 * @param pThis The IOMMU device state.
2554 * @param pDte The device table entry.
2555 * @param uIova The I/O virtual address.
2556 *
2557 * @remarks Ensure the exclusion range is enabled prior to calling this function.
2558 *
2559 * @thread Any.
2560 */
2561static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2562{
2563 /* Ensure the exclusion range is enabled. */
2564 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2565
2566 /* Check if the IOVA falls within the exclusion range. */
2567 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2568 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2569 if (uIovaExclLast - uIova >= uIovaExclFirst)
2570 {
2571 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2572 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2573 || pDte->n.u1AllowExclusion)
2574 return true;
2575 }
2576 return false;
2577}
2578
2579
2580/**
2581 * Reads a device table entry from guest memory given the device ID.
2582 *
2583 * @returns VBox status code.
2584 * @param pDevIns The IOMMU device instance.
2585 * @param uDevId The device ID.
2586 * @param enmOp The IOMMU operation being performed.
2587 * @param pDte Where to store the device table entry.
2588 *
2589 * @thread Any.
2590 */
2591static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2592{
2593 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2594 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2595
2596 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2597 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2598 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegMasks));
2599
2600 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2601 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2602
2603 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2604 uint16_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2605 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2606
2607 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2608 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2609 if (RT_FAILURE(rc))
2610 {
2611 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2612
2613 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2614 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2615 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2616 return VERR_IOMMU_IPE_1;
2617 }
2618
2619 return rc;
2620}
2621
2622
2623/**
2624 * Walks the I/O page table to translate the I/O virtual address to a system
2625 * physical address.
2626 *
2627 * @returns VBox status code.
2628 * @param pDevIns The IOMMU device instance.
2629 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2630 * @param uDevId The device ID.
2631 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2632 * permissions for the access being made.
2633 * @param pDte The device table entry.
2634 * @param enmOp The IOMMU operation being performed.
2635 * @param pWalkResult Where to store the results of the I/O page walk. This is
2636 * only updated when VINF_SUCCESS is returned.
2637 *
2638 * @thread Any.
2639 */
2640static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2641 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2642{
2643 Assert(pDte->n.u1Valid);
2644 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2645
2646 /* If the translation is not valid, raise an I/O page fault. */
2647 if (pDte->n.u1TranslationValid)
2648 { /* likely */ }
2649 else
2650 {
2651 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2652 * doesn't explicitly say whether an I/O page fault is raised. From other
2653 * places in the spec. it seems early page walk terminations (starting with
2654 * the DTE) return the state computed so far and raises an I/O page fault. So
2655 * returning an invalid translation rather than skipping translation. */
2656 LogFunc(("Translation valid bit not set -> IOPF\n"));
2657 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2658 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2659 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2660 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2661 kIoPageFaultType_DteTranslationDisabled);
2662 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2663 }
2664
2665 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2666 uint8_t const uMaxLevel = pDte->n.u3Mode;
2667 if (uMaxLevel != 0)
2668 { /* likely */ }
2669 else
2670 {
2671 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2672 if ((fAccess & fDtePerm) != fAccess)
2673 {
2674 LogFunc(("Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
2675 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2676 }
2677 pWalkResult->GCPhysSpa = uIova;
2678 pWalkResult->cShift = 0;
2679 pWalkResult->fIoPerm = fDtePerm;
2680 return VINF_SUCCESS;
2681 }
2682
2683 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2684 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2685 { /* likely */ }
2686 else
2687 {
2688 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2689 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2690 * I'm just going with I/O page fault. */
2691 LogFunc(("Invalid root page table level %#x -> IOPF\n", uMaxLevel));
2692 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2693 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2694 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2695 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2696 kIoPageFaultType_PteInvalidLvlEncoding);
2697 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2698 }
2699
2700 /* Check permissions bits of the root page table. */
2701 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2702 if ((fAccess & fRootPtePerm) == fAccess)
2703 { /* likely */ }
2704 else
2705 {
2706 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2707 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2708 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2709 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2710 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2711 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2712 }
2713
2714 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2715 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2716 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2717 * table entry every time. Not sure if it's worth optimizing that case now
2718 * or if at all. */
2719
2720 /* The virtual address bits indexing table. */
2721 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2722 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2723 UINT64_C(0x00000000001ff000),
2724 UINT64_C(0x000000003fe00000),
2725 UINT64_C(0x0000007fc0000000),
2726 UINT64_C(0x0000ff8000000000),
2727 UINT64_C(0x01ff000000000000),
2728 UINT64_C(0xfe00000000000000),
2729 UINT64_C(0x0000000000000000) };
2730 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2731 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2732
2733 /* Traverse the I/O page table starting with the page directory in the DTE. */
2734 IOPTENTITY_T PtEntity;
2735 PtEntity.u64 = pDte->au64[0];
2736 for (;;)
2737 {
2738 /* Figure out the system physical address of the page table at the current level. */
2739 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2740
2741 /* Read the page table entity at the current level. */
2742 {
2743 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2744 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2745 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2746 uint64_t const offPte = idxPte << 3;
2747 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2748 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2749 if (RT_FAILURE(rc))
2750 {
2751 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2752 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2753 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2754 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2755 return VERR_IOMMU_IPE_2;
2756 }
2757 }
2758
2759 /* Check present bit. */
2760 if (PtEntity.n.u1Present)
2761 { /* likely */ }
2762 else
2763 {
2764 LogFunc(("Page table entry not present -> IOPF\n"));
2765 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2766 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2767 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2768 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2769 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2770 }
2771
2772 /* Check permission bits. */
2773 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2774 if ((fAccess & fPtePerm) == fAccess)
2775 { /* likely */ }
2776 else
2777 {
2778 LogFunc(("Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF\n", fAccess, fPtePerm));
2779 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2780 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2781 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2782 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2783 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2784 }
2785
2786 /* If this is a PTE, we're at the final level and we're done. */
2787 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2788 if (uNextLevel == 0)
2789 {
2790 /* The page size of the translation is the default (4K). */
2791 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2792 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2793 pWalkResult->fIoPerm = fPtePerm;
2794 return VINF_SUCCESS;
2795 }
2796 if (uNextLevel == 7)
2797 {
2798 /* The default page size of the translation is overridden. */
2799 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2800 uint8_t cShift = X86_PAGE_4K_SHIFT;
2801 while (GCPhysPte & RT_BIT_64(cShift++))
2802 ;
2803
2804 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2805 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2806 if ( cShift > s_acIovaLevelShifts[uLevel]
2807 && cShift < s_acIovaLevelShifts[uLevel + 1])
2808 {
2809 pWalkResult->GCPhysSpa = GCPhysPte;
2810 pWalkResult->cShift = cShift;
2811 pWalkResult->fIoPerm = fPtePerm;
2812 return VINF_SUCCESS;
2813 }
2814
2815 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2816 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2817 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2818 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2819 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2820 kIoPageFaultType_PteInvalidPageSize);
2821 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2822 }
2823
2824 /* Validate the next level encoding of the PDE. */
2825#if IOMMU_MAX_HOST_PT_LEVEL < 6
2826 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2827 { /* likely */ }
2828 else
2829 {
2830 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2831 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2832 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2833 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2834 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2835 kIoPageFaultType_PteInvalidLvlEncoding);
2836 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2837 }
2838#else
2839 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2840#endif
2841
2842 /* Validate level transition. */
2843 if (uNextLevel < uLevel)
2844 { /* likely */ }
2845 else
2846 {
2847 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2848 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2849 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2850 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2851 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2852 kIoPageFaultType_PteInvalidLvlEncoding);
2853 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2854 }
2855
2856 /* Ensure IOVA bits of skipped levels are zero. */
2857 Assert(uLevel > 0);
2858 uint64_t uIovaSkipMask = 0;
2859 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2860 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2861 if (!(uIova & uIovaSkipMask))
2862 { /* likely */ }
2863 else
2864 {
2865 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2866 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2867 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2868 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2869 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2870 kIoPageFaultType_SkippedLevelIovaNotZero);
2871 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2872 }
2873
2874 /* Continue with traversing the page directory at this level. */
2875 }
2876}
2877
2878
2879/**
2880 * Looks up an I/O virtual address from the device table.
2881 *
2882 * @returns VBox status code.
2883 * @param pDevIns The IOMMU instance data.
2884 * @param uDevId The device ID.
2885 * @param uIova The I/O virtual address to lookup.
2886 * @param cbAccess The size of the access.
2887 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2888 * permissions for the access being made.
2889 * @param enmOp The IOMMU operation being performed.
2890 * @param pGCPhysSpa Where to store the translated system physical address. Only
2891 * valid when translation succeeds and VINF_SUCCESS is
2892 * returned!
2893 *
2894 * @thread Any.
2895 */
2896static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2897 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2898{
2899 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2900
2901 /* Read the device table entry from memory. */
2902 DTE_T Dte;
2903 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2904 if (RT_SUCCESS(rc))
2905 {
2906 /* If the DTE is not valid, addresses are forwarded without translation */
2907 if (Dte.n.u1Valid)
2908 { /* likely */ }
2909 else
2910 {
2911 /** @todo IOMMU: Add to IOLTB cache. */
2912 *pGCPhysSpa = uIova;
2913 return VINF_SUCCESS;
2914 }
2915
2916 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2917 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2918 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2919 if (RT_LIKELY( !fRsvd0
2920 && !fRsvd1))
2921 { /* likely */ }
2922 else
2923 {
2924 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2925 EVT_ILLEGAL_DTE_T Event;
2926 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2927 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2928 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2929 }
2930
2931 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2932 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable
2933 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2934 { /* likely */ }
2935 else
2936 {
2937 /** @todo IOMMU: Add to IOLTB cache. */
2938 *pGCPhysSpa = uIova;
2939 return VINF_SUCCESS;
2940 }
2941
2942 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
2943 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
2944
2945 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
2946 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2947 uint64_t cbRemaining = cbAccess;
2948 for (;;)
2949 {
2950 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
2951 IOWALKRESULT WalkResult;
2952 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
2953 if (RT_SUCCESS(rc))
2954 {
2955 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
2956
2957 /* Store the translated base address before continuing to check permissions for any more pages. */
2958 if (cbRemaining == cbAccess)
2959 {
2960 RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2961 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2962 }
2963
2964 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
2965 if (cbRemaining > cbPhysPage - offIova)
2966 {
2967 cbRemaining -= (cbPhysPage - offIova);
2968 uBaseIova += cbPhysPage;
2969 offIova = 0;
2970 }
2971 else
2972 break;
2973 }
2974 else
2975 {
2976 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
2977 uBaseIova, fAccess, rc));
2978 *pGCPhysSpa = NIL_RTGCPHYS;
2979 return rc;
2980 }
2981 }
2982
2983 return rc;
2984 }
2985
2986 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2987 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2988}
2989
2990
2991/**
2992 * Memory read request from a device.
2993 *
2994 * @returns VBox status code.
2995 * @param pDevIns The IOMMU device instance.
2996 * @param uDevId The device ID (bus, device, function).
2997 * @param uIova The I/O virtual address being read.
2998 * @param cbRead The number of bytes being read.
2999 * @param pGCPhysSpa Where to store the translated system physical address.
3000 *
3001 * @thread Any.
3002 */
3003static DECLCALLBACK(int) iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
3004 PRTGCPHYS pGCPhysSpa)
3005{
3006 /* Validate. */
3007 Assert(pDevIns);
3008 Assert(pGCPhysSpa);
3009 Assert(cbRead > 0);
3010
3011 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3012 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
3013
3014 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3015 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3016 if (Ctrl.n.u1IommuEn)
3017 {
3018 /** @todo IOMMU: IOTLB cache lookup. */
3019
3020 /* Lookup the IOVA from the device table. */
3021 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
3022 }
3023
3024 *pGCPhysSpa = uIova;
3025 return VINF_SUCCESS;
3026}
3027
3028
3029/**
3030 * Memory write request from a device.
3031 *
3032 * @returns VBox status code.
3033 * @param pDevIns The IOMMU device instance.
3034 * @param uDevId The device ID (bus, device, function).
3035 * @param uIova The I/O virtual address being written.
3036 * @param cbWrite The number of bytes being written.
3037 * @param pGCPhysSpa Where to store the translated physical address.
3038 *
3039 * @thread Any.
3040 */
3041static DECLCALLBACK(int) iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
3042 PRTGCPHYS pGCPhysSpa)
3043{
3044 /* Validate. */
3045 Assert(pDevIns);
3046 Assert(pGCPhysSpa);
3047 Assert(cbWrite > 0);
3048
3049 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3050 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
3051
3052 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3053 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3054 if (Ctrl.n.u1IommuEn)
3055 {
3056 /** @todo IOMMU: IOTLB cache lookup. */
3057
3058 /* Lookup the IOVA from the device table. */
3059 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
3060 }
3061
3062 *pGCPhysSpa = uIova;
3063 return VINF_SUCCESS;
3064}
3065
3066
3067/**
3068 * Reads an interrupt remapping table entry from guest memory given its DTE.
3069 *
3070 * @returns VBox status code.
3071 * @param pDevIns The IOMMU device instance.
3072 * @param uDevId The device ID.
3073 * @param pDte The device table entry.
3074 * @param GCPhysIn The source MSI address.
3075 * @param uDataIn The source MSI data.
3076 * @param enmOp The IOMMU operation being performed.
3077 * @param pIrte Where to store the interrupt remapping table entry.
3078 *
3079 * @thread Any.
3080 */
3081static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
3082 IOMMUOP enmOp, PIRTE_T pIrte)
3083{
3084 /* Ensure the IRTE length is valid. */
3085 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
3086
3087 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
3088 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
3089 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
3090 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
3091
3092 /* Ensure the IRTE falls completely within the interrupt table. */
3093 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
3094 { /* likely */ }
3095 else
3096 {
3097 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
3098 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
3099
3100 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3101 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
3102 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3103 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3104 kIoPageFaultType_IrteAddrInvalid);
3105 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3106 }
3107
3108 /* Read the IRTE from memory. */
3109 Assert(!(GCPhysIrte & 3));
3110 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
3111 if (RT_SUCCESS(rc))
3112 return VINF_SUCCESS;
3113
3114 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
3115 * situation. Is it an I/O page fault or a device table hardware error?
3116 * There's no interrupt table hardware error event, but it's unclear what
3117 * we should do here. */
3118 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
3119 return VERR_IOMMU_IPE_4;
3120}
3121
3122
3123/**
3124 * Remaps the interrupt using the interrupt remapping table.
3125 *
3126 * @returns VBox status code.
3127 * @param pDevIns The IOMMU instance data.
3128 * @param uDevId The device ID.
3129 * @param pDte The device table entry.
3130 * @param enmOp The IOMMU operation being performed.
3131 * @param pMsiIn The source MSI.
3132 * @param pMsiOut Where to store the remapped MSI.
3133 *
3134 * @thread Any.
3135 */
3136static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
3137 PMSIMSG pMsiOut)
3138{
3139 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
3140
3141 IRTE_T Irte;
3142 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
3143 if (RT_SUCCESS(rc))
3144 {
3145 if (Irte.n.u1RemapEnable)
3146 {
3147 if (!Irte.n.u1GuestMode)
3148 {
3149 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
3150 {
3151 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
3152 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
3153 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
3154 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
3155
3156 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
3157 pMsiOut->Data.u32 = pMsiIn->Data.u32;
3158 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
3159 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
3160
3161 return VINF_SUCCESS;
3162 }
3163
3164 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3165 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3166 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3167 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3168 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
3169 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3170 }
3171
3172 LogFunc(("Guest mode not supported -> IOPF\n"));
3173 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3174 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3175 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3176 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3177 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3178 }
3179
3180 LogFunc(("Remapping disabled -> IOPF\n"));
3181 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3182 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3183 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3184 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3185 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3186 }
3187
3188 return rc;
3189}
3190
3191
3192/**
3193 * Looks up an MSI interrupt from the interrupt remapping table.
3194 *
3195 * @returns VBox status code.
3196 * @param pDevIns The IOMMU instance data.
3197 * @param uDevId The device ID.
3198 * @param enmOp The IOMMU operation being performed.
3199 * @param pMsiIn The source MSI.
3200 * @param pMsiOut Where to store the remapped MSI.
3201 *
3202 * @thread Any.
3203 */
3204static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3205{
3206 /* Read the device table entry from memory. */
3207 LogFlowFunc(("uDevId=%#x enmOp=%u\n", uDevId, enmOp));
3208
3209 DTE_T Dte;
3210 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3211 if (RT_SUCCESS(rc))
3212 {
3213 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
3214 if (Dte.n.u1IntrMapValid)
3215 {
3216 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3217 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3218 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3219 if (RT_LIKELY( !fRsvd0
3220 && !fRsvd1))
3221 { /* likely */ }
3222 else
3223 {
3224 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3225 fRsvd1));
3226 EVT_ILLEGAL_DTE_T Event;
3227 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3228 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3229 return VERR_IOMMU_INTR_REMAP_FAILED;
3230 }
3231
3232 /*
3233 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3234 * that's connected through HyperTransport it might be possible; but for us, it
3235 * doesn't seem we need to specially handle these pins.
3236 */
3237
3238 /*
3239 * Validate the MSI source address.
3240 *
3241 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3242 * CPU is concerned, the MSI region is fixed and we must ensure no other device
3243 * claims the region as I/O space.
3244 *
3245 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3246 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3247 * See Intel spec. 10.11.1 "Message Address Register Format".
3248 */
3249 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3250 {
3251 /*
3252 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3253 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3254 */
3255 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3256 bool fPassThru = false;
3257 switch (u8DeliveryMode)
3258 {
3259 case VBOX_MSI_DELIVERY_MODE_FIXED:
3260 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3261 {
3262 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3263 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3264 {
3265 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
3266 iommuAmdSetPciTargetAbort(pDevIns);
3267 return VERR_IOMMU_INTR_REMAP_DENIED;
3268 }
3269
3270 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3271 {
3272 fPassThru = true;
3273 break;
3274 }
3275
3276 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3277 {
3278 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3279 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3280 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3281 {
3282 /*
3283 * We don't support guest interrupt remapping yet. When we do, we'll need to
3284 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3285 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3286 * already reads the control register, add that as a parameter when we eventually
3287 * support guest interrupt remapping. For now, just assert.
3288 */
3289 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3290 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3291 NOREF(pThis);
3292
3293 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3294 }
3295
3296 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3297 EVT_ILLEGAL_DTE_T Event;
3298 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3299 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3300 return VERR_IOMMU_INTR_REMAP_FAILED;
3301 }
3302
3303 /* Paranoia. */
3304 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
3305
3306 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3307
3308 EVT_ILLEGAL_DTE_T Event;
3309 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3310 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3311 return VERR_IOMMU_INTR_REMAP_FAILED;
3312 }
3313
3314 /* SMIs are passed through unmapped. We don't implement SMI filters. */
3315 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3316 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3317 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3318 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3319 default:
3320 {
3321 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3322 iommuAmdSetPciTargetAbort(pDevIns);
3323 return VERR_IOMMU_INTR_REMAP_FAILED;
3324 }
3325 }
3326
3327 if (fPassThru)
3328 {
3329 *pMsiOut = *pMsiIn;
3330 return VINF_SUCCESS;
3331 }
3332
3333 iommuAmdSetPciTargetAbort(pDevIns);
3334 return VERR_IOMMU_INTR_REMAP_DENIED;
3335 }
3336 else
3337 {
3338 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3339 return VERR_IOMMU_INTR_REMAP_FAILED;
3340 }
3341 }
3342 else
3343 {
3344 /** @todo IOMMU: Add to interrupt remapping cache. */
3345 LogFlowFunc(("DTE interrupt map not valid\n"));
3346 *pMsiOut = *pMsiIn;
3347 return VINF_SUCCESS;
3348 }
3349 }
3350
3351 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3352 return VERR_IOMMU_INTR_REMAP_FAILED;
3353}
3354
3355
3356/**
3357 * Interrupt remap request from a device.
3358 *
3359 * @returns VBox status code.
3360 * @param pDevIns The IOMMU device instance.
3361 * @param uDevId The device ID (bus, device, function).
3362 * @param pMsiIn The source MSI.
3363 * @param pMsiOut Where to store the remapped MSI.
3364 */
3365static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3366{
3367 /* Validate. */
3368 Assert(pDevIns);
3369 Assert(pMsiIn);
3370 Assert(pMsiOut);
3371
3372 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3373 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3374
3375 LogFlowFunc(("uDevId=%#x\n", uDevId));
3376
3377 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3378 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3379 if (Ctrl.n.u1IommuEn)
3380 {
3381 /** @todo Cache? */
3382
3383 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3384 }
3385
3386 *pMsiOut = *pMsiIn;
3387 return VINF_SUCCESS;
3388}
3389
3390
3391/**
3392 * @callback_method_impl{FNIOMMMIONEWWRITE}
3393 */
3394static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3395{
3396 NOREF(pvUser);
3397 Assert(cb == 4 || cb == 8);
3398 Assert(!(off & (cb - 1)));
3399
3400 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3401 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3402
3403 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
3404 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
3405}
3406
3407
3408/**
3409 * @callback_method_impl{FNIOMMMIONEWREAD}
3410 */
3411static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3412{
3413 NOREF(pvUser);
3414 Assert(cb == 4 || cb == 8);
3415 Assert(!(off & (cb - 1)));
3416
3417 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3418 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3419
3420 uint64_t uResult;
3421 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
3422 if (cb == 8)
3423 *(uint64_t *)pv = uResult;
3424 else
3425 *(uint32_t *)pv = (uint32_t)uResult;
3426
3427 return rcStrict;
3428}
3429
3430# ifdef IN_RING3
3431
3432/**
3433 * Processes an IOMMU command.
3434 *
3435 * @returns VBox status code.
3436 * @param pDevIns The IOMMU device instance.
3437 * @param pCmd The command to process.
3438 * @param GCPhysCmd The system physical address of the command.
3439 * @param pEvtError Where to store the error event in case of failures.
3440 *
3441 * @thread Command thread.
3442 */
3443static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3444{
3445 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3446
3447 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3448 STAM_COUNTER_INC(&pThis->StatCmd);
3449
3450 uint8_t const bCmd = pCmd->n.u4Opcode;
3451 switch (bCmd)
3452 {
3453 case IOMMU_CMD_COMPLETION_WAIT:
3454 {
3455 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3456
3457 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3458 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
3459
3460 /* Validate reserved bits in the command. */
3461 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3462 {
3463 /* If Completion Store is requested, write the StoreData to the specified address. */
3464 if (pCmdComWait->n.u1Store)
3465 {
3466 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3467 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3468 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3469 if (RT_FAILURE(rc))
3470 {
3471 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3472 GCPhysStore, rc));
3473 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3474 return VERR_IOMMU_CMD_HW_ERROR;
3475 }
3476 }
3477
3478 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3479 if (pCmdComWait->n.u1Interrupt)
3480 {
3481 IOMMU_LOCK(pDevIns);
3482 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3483 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3484 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3485 IOMMU_UNLOCK(pDevIns);
3486
3487 if (fRaiseInt)
3488 iommuAmdRaiseMsiInterrupt(pDevIns);
3489 }
3490 return VINF_SUCCESS;
3491 }
3492 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3493 return VERR_IOMMU_CMD_INVALID_FORMAT;
3494 }
3495
3496 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3497 {
3498 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3499 * then. */
3500 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3501 return VINF_SUCCESS;
3502 }
3503
3504 case IOMMU_CMD_INV_IOMMU_PAGES:
3505 {
3506 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3507 * then. */
3508 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3509 return VINF_SUCCESS;
3510 }
3511
3512 case IOMMU_CMD_INV_IOTLB_PAGES:
3513 {
3514 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3515
3516 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3517 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3518 {
3519 /** @todo IOMMU: Implement remote IOTLB invalidation. */
3520 return VERR_NOT_IMPLEMENTED;
3521 }
3522 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3523 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3524 }
3525
3526 case IOMMU_CMD_INV_INTR_TABLE:
3527 {
3528 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3529 * then. */
3530 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3531 return VINF_SUCCESS;
3532 }
3533
3534 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3535 {
3536 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3537 if (pThis->ExtFeat.n.u1PrefetchSup)
3538 {
3539 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
3540 return VINF_SUCCESS;
3541 }
3542 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3543 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3544 }
3545
3546 case IOMMU_CMD_COMPLETE_PPR_REQ:
3547 {
3548 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3549
3550 /* We don't support PPR requests yet. */
3551 Assert(!pThis->ExtFeat.n.u1PprSup);
3552 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3553 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3554 }
3555
3556 case IOMMU_CMD_INV_IOMMU_ALL:
3557 {
3558 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3559
3560 if (pThis->ExtFeat.n.u1InvAllSup)
3561 {
3562 /** @todo IOMMU: Invalidate all. Pretend success until then. */
3563 return VINF_SUCCESS;
3564 }
3565 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3566 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3567 }
3568 }
3569
3570 STAM_COUNTER_DEC(&pThis->StatCmd);
3571 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3572 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3573 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3574}
3575
3576
3577/**
3578 * The IOMMU command thread.
3579 *
3580 * @returns VBox status code.
3581 * @param pDevIns The IOMMU device instance.
3582 * @param pThread The command thread.
3583 */
3584static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3585{
3586 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3587
3588 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3589 return VINF_SUCCESS;
3590
3591 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3592 {
3593 /*
3594 * Sleep perpetually until we are woken up to process commands.
3595 */
3596 {
3597 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3598 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3599 if (!fSignaled)
3600 {
3601 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3602 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3603 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3604 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3605 break;
3606 Log5Func(("Woken up with rc=%Rrc\n", rc));
3607 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3608 }
3609 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3610 }
3611
3612 /*
3613 * Fetch and process IOMMU commands.
3614 */
3615 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
3616 * at a time) and is expensive due to calls to PGM for fetching guest memory.
3617 * We could optimize by fetching a bunch of commands at a time reducing
3618 * number of calls to PGM. In the longer run we could lock the memory and
3619 * mappings and accessing them directly. */
3620 IOMMU_LOCK(pDevIns);
3621
3622 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3623 if (Status.n.u1CmdBufRunning)
3624 {
3625 /* Get the offset we need to read the command from memory (circular buffer offset). */
3626 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3627 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3628 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3629 Assert(offHead < cbCmdBuf);
3630 while (offHead != pThis->CmdBufTailPtr.n.off)
3631 {
3632 /* Read the command from memory. */
3633 CMD_GENERIC_T Cmd;
3634 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3635 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3636 if (RT_SUCCESS(rc))
3637 {
3638 /* Increment the command buffer head pointer. */
3639 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3640 pThis->CmdBufHeadPtr.n.off = offHead;
3641
3642 /* Process the fetched command. */
3643 EVT_GENERIC_T EvtError;
3644 IOMMU_UNLOCK(pDevIns);
3645 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3646 IOMMU_LOCK(pDevIns);
3647 if (RT_FAILURE(rc))
3648 {
3649 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3650 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3651 {
3652 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3653 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3654 }
3655 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3656 {
3657 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3658 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", Cmd.n.u4Opcode));
3659 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3660 }
3661 break;
3662 }
3663 }
3664 else
3665 {
3666 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmd, rc));
3667 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3668 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3669 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3670 break;
3671 }
3672 }
3673 }
3674
3675 IOMMU_UNLOCK(pDevIns);
3676 }
3677
3678 LogFlowFunc(("Command thread terminating\n"));
3679 return VINF_SUCCESS;
3680}
3681
3682
3683/**
3684 * Wakes up the command thread so it can respond to a state change.
3685 *
3686 * @returns VBox status code.
3687 * @param pDevIns The IOMMU device instance.
3688 * @param pThread The command thread.
3689 */
3690static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3691{
3692 RT_NOREF(pThread);
3693 LogFlowFunc(("\n"));
3694 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3695 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3696}
3697
3698
3699/**
3700 * @callback_method_impl{FNPCICONFIGREAD}
3701 */
3702static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3703 unsigned cb, uint32_t *pu32Value)
3704{
3705 /** @todo IOMMU: PCI config read stat counter. */
3706 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3707 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3708 return rcStrict;
3709}
3710
3711
3712/**
3713 * @callback_method_impl{FNPCICONFIGWRITE}
3714 */
3715static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3716 unsigned cb, uint32_t u32Value)
3717{
3718 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3719
3720 /*
3721 * Discard writes to read-only registers that are specific to the IOMMU.
3722 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3723 * See PCI spec. 6.1. "Configuration Space Organization".
3724 */
3725 switch (uAddress)
3726 {
3727 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3728 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3729 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3730 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3731 {
3732 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3733 return VINF_SUCCESS;
3734 }
3735 }
3736
3737 IOMMU_LOCK(pDevIns);
3738
3739 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3740 switch (uAddress)
3741 {
3742 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3743 {
3744 if (pThis->IommuBar.n.u1Enable)
3745 {
3746 rcStrict = VINF_SUCCESS;
3747 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3748 break;
3749 }
3750
3751 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3752 if (pThis->IommuBar.n.u1Enable)
3753 {
3754 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3755 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3756 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3757 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
3758
3759 /* If the MMIO region is already mapped at the specified address, we're done. */
3760 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
3761 if (GCPhysMmioBasePrev == GCPhysMmioBase)
3762 {
3763 rcStrict = VINF_SUCCESS;
3764 break;
3765 }
3766
3767 /* Unmap the previous MMIO region (which is at a different address). */
3768 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
3769 {
3770 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
3771 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3772 if (RT_FAILURE(rcStrict))
3773 {
3774 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3775 break;
3776 }
3777 }
3778
3779 /* Map the newly specified MMIO region. */
3780 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
3781 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3782 if (RT_FAILURE(rcStrict))
3783 {
3784 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3785 break;
3786 }
3787 }
3788 else
3789 rcStrict = VINF_SUCCESS;
3790 break;
3791 }
3792
3793 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3794 {
3795 if (!pThis->IommuBar.n.u1Enable)
3796 pThis->IommuBar.au32[1] = u32Value;
3797 else
3798 {
3799 rcStrict = VINF_SUCCESS;
3800 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3801 }
3802 break;
3803 }
3804
3805 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3806 {
3807 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3808 RT_FALL_THRU();
3809 }
3810 default:
3811 {
3812 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3813 break;
3814 }
3815 }
3816
3817 IOMMU_UNLOCK(pDevIns);
3818
3819 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
3820 return rcStrict;
3821}
3822
3823
3824/**
3825 * @callback_method_impl{FNDBGFHANDLERDEV}
3826 */
3827static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3828{
3829 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3830 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3831 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3832
3833 bool fVerbose;
3834 if ( pszArgs
3835 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3836 fVerbose = true;
3837 else
3838 fVerbose = false;
3839
3840 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3841 /* Device Table Base Addresses (all segments). */
3842 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3843 {
3844 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3845 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3846 if (fVerbose)
3847 {
3848 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3849 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
3850 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3851 }
3852 }
3853 /* Command Buffer Base Address Register. */
3854 {
3855 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3856 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3857 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3858 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3859 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
3860 if (fVerbose)
3861 {
3862 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3863 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3864 cEntries, cbBuffer);
3865 }
3866 }
3867 /* Event Log Base Address Register. */
3868 {
3869 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3870 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3871 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3872 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3873 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
3874 if (fVerbose)
3875 {
3876 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3877 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3878 cEntries, cbBuffer);
3879 }
3880 }
3881 /* IOMMU Control Register. */
3882 {
3883 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3884 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3885 if (fVerbose)
3886 {
3887 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3888 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3889 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3890 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3891 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3892 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3893 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3894 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3895 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3896 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3897 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3898 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3899 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3900 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3901 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3902 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3903 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3904 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3905 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3906 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3907 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3908 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3909 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3910 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3911 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3912 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3913 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3914 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3915 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3916 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3917 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3918 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3919 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3920 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3921 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3922 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3923 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3924 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3925 }
3926 }
3927 /* Exclusion Base Address Register. */
3928 {
3929 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3930 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3931 if (fVerbose)
3932 {
3933 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3934 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3935 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
3936 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
3937 }
3938 }
3939 /* Exclusion Range Limit Register. */
3940 {
3941 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3942 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3943 if (fVerbose)
3944 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
3945 }
3946 /* Extended Feature Register. */
3947 {
3948 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3949 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3950 if (fVerbose)
3951 {
3952 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3953 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3954 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3955 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3956 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3957 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3958 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3959 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3960 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3961 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3962 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3963 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3964 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3965 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3966 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3967 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3968 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3969 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3970 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3971 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
3972 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
3973 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3974 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3975 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3976 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3977 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3978 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3979 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3980 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3981 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3982 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3983 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3984 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3985 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3986 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3987 }
3988 }
3989 /* PPR Log Base Address Register. */
3990 {
3991 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3992 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
3993 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3994 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3995 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3996 if (fVerbose)
3997 {
3998 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3999 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4000 cEntries, cbBuffer);
4001 }
4002 }
4003 /* Hardware Event (Hi) Register. */
4004 {
4005 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4006 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4007 if (fVerbose)
4008 {
4009 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4010 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4011 }
4012 }
4013 /* Hardware Event (Lo) Register. */
4014 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4015 /* Hardware Event Status. */
4016 {
4017 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4018 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4019 if (fVerbose)
4020 {
4021 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4022 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4023 }
4024 }
4025 /* Guest Virtual-APIC Log Base Address Register. */
4026 {
4027 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4028 uint8_t const uEncodedLen = GALogBar.n.u4Len;
4029 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4030 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4031 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4032 if (fVerbose)
4033 {
4034 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4035 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4036 cEntries, cbBuffer);
4037 }
4038 }
4039 /* Guest Virtual-APIC Log Tail Address Register. */
4040 {
4041 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4042 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4043 if (fVerbose)
4044 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4045 }
4046 /* PPR Log B Base Address Register. */
4047 {
4048 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4049 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4050 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4051 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4052 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4053 if (fVerbose)
4054 {
4055 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4056 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4057 cEntries, cbBuffer);
4058 }
4059 }
4060 /* Event Log B Base Address Register. */
4061 {
4062 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4063 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4064 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4065 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4066 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4067 if (fVerbose)
4068 {
4069 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4070 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4071 cEntries, cbBuffer);
4072 }
4073 }
4074 /* Device-Specific Feature Extension Register. */
4075 {
4076 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4077 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4078 if (fVerbose)
4079 {
4080 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4081 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4082 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4083 }
4084 }
4085 /* Device-Specific Control Extension Register. */
4086 {
4087 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4088 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4089 if (fVerbose)
4090 {
4091 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4092 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4093 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4094 }
4095 }
4096 /* Device-Specific Status Extension Register. */
4097 {
4098 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4099 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
4100 if (fVerbose)
4101 {
4102 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4103 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4104 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4105 }
4106 }
4107 /* Miscellaneous Information Register (Lo and Hi). */
4108 {
4109 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
4110 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
4111 if (fVerbose)
4112 {
4113 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
4114 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
4115 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
4116 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
4117 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
4118 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
4119 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
4120 }
4121 }
4122 /* MSI Capability Header. */
4123 {
4124 MSI_CAP_HDR_T MsiCapHdr;
4125 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4126 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4127 if (fVerbose)
4128 {
4129 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4130 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4131 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4132 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4133 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4134 }
4135 }
4136 /* MSI Address Register (Lo and Hi). */
4137 {
4138 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4139 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4140 MSIADDR MsiAddr;
4141 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4142 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4143 if (fVerbose)
4144 {
4145 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
4146 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
4147 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
4148 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
4149 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
4150 }
4151 }
4152 /* MSI Data. */
4153 {
4154 MSIDATA MsiData;
4155 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4156 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4157 if (fVerbose)
4158 {
4159 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
4160 MsiData.n.u8Vector);
4161 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
4162 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
4163 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4164 "level" : "edge");
4165 }
4166 }
4167 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4168 {
4169 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4170 MsiMapCapHdr.u32 = 0;
4171 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4172 if (fVerbose)
4173 {
4174 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4175 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4176 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4177 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4178 }
4179 }
4180 /* Performance Optimization Control Register. */
4181 {
4182 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4183 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4184 if (fVerbose)
4185 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4186 }
4187 /* XT (x2APIC) General Interrupt Control Register. */
4188 {
4189 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4190 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4191 if (fVerbose)
4192 {
4193 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4194 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4195 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4196 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4197 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4198 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4199 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4200 }
4201 }
4202 /* XT (x2APIC) PPR Interrupt Control Register. */
4203 {
4204 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4205 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4206 if (fVerbose)
4207 {
4208 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4209 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4210 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4211 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4212 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4213 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4214 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4215 }
4216 }
4217 /* XT (X2APIC) GA Log Interrupt Control Register. */
4218 {
4219 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4220 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4221 if (fVerbose)
4222 {
4223 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4224 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4225 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4226 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4227 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4228 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4229 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4230 }
4231 }
4232 /* MARC Registers. */
4233 {
4234 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4235 {
4236 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4237 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4238 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4239
4240 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4241 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4242 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4243 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4244
4245 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4246 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4247 }
4248 }
4249 /* Reserved Register. */
4250 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4251 /* Command Buffer Head Pointer Register. */
4252 {
4253 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4254 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4255 CmdBufHeadPtr.n.off);
4256 }
4257 /* Command Buffer Tail Pointer Register. */
4258 {
4259 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4260 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4261 CmdBufTailPtr.n.off);
4262 }
4263 /* Event Log Head Pointer Register. */
4264 {
4265 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4266 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4267 EvtLogHeadPtr.n.off);
4268 }
4269 /* Event Log Tail Pointer Register. */
4270 {
4271 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4272 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4273 EvtLogTailPtr.n.off);
4274 }
4275 /* Status Register. */
4276 {
4277 IOMMU_STATUS_T const Status = pThis->Status;
4278 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4279 if (fVerbose)
4280 {
4281 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4282 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4283 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4284 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4285 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4286 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4287 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4288 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4289 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4290 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4291 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4292 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4293 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4294 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4295 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4296 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4297 }
4298 }
4299 /* PPR Log Head Pointer. */
4300 {
4301 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4302 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4303 PprLogHeadPtr.n.off);
4304 }
4305 /* PPR Log Tail Pointer. */
4306 {
4307 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4308 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4309 PprLogTailPtr.n.off);
4310 }
4311 /* Guest Virtual-APIC Log Head Pointer. */
4312 {
4313 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4314 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4315 GALogHeadPtr.n.u12GALogPtr);
4316 }
4317 /* Guest Virtual-APIC Log Tail Pointer. */
4318 {
4319 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4320 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4321 GALogTailPtr.n.u12GALogPtr);
4322 }
4323 /* PPR Log B Head Pointer. */
4324 {
4325 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4326 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4327 PprLogBHeadPtr.n.off);
4328 }
4329 /* PPR Log B Tail Pointer. */
4330 {
4331 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4332 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4333 PprLogBTailPtr.n.off);
4334 }
4335 /* Event Log B Head Pointer. */
4336 {
4337 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4338 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4339 EvtLogBHeadPtr.n.off);
4340 }
4341 /* Event Log B Tail Pointer. */
4342 {
4343 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4344 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4345 EvtLogBTailPtr.n.off);
4346 }
4347 /* PPR Log Auto Response Register. */
4348 {
4349 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4350 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4351 if (fVerbose)
4352 {
4353 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4354 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4355 }
4356 }
4357 /* PPR Log Overflow Early Warning Indicator Register. */
4358 {
4359 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4360 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4361 if (fVerbose)
4362 {
4363 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4364 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4365 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4366 }
4367 }
4368 /* PPR Log Overflow Early Warning Indicator Register. */
4369 {
4370 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4371 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4372 if (fVerbose)
4373 {
4374 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4375 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4376 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4377 }
4378 }
4379}
4380
4381
4382/**
4383 * Dumps the DTE via the info callback helper.
4384 *
4385 * @param pHlp The info helper.
4386 * @param pDte The device table entry.
4387 * @param pszPrefix The string prefix.
4388 */
4389static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4390{
4391 AssertReturnVoid(pHlp);
4392 AssertReturnVoid(pDte);
4393 AssertReturnVoid(pszPrefix);
4394
4395 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4396 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4397 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4398 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4399 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4400 pDte->n.u40PageTableRootPtrLo << 12);
4401 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4402 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4403 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4404 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4405 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4406 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4407 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4408 (pDte->n.u21GstCr3TableRootPtrHi << 31)
4409 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
4410 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
4411 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4412 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4413 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4414 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4415 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4416 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4417 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4418 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4419 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4420 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4421 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4422 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4423 pHlp->pfnPrintf(pHlp, "\n");
4424
4425 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4426 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4427 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4428 {
4429 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4430 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4431 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4432 cbIntrTable);
4433 }
4434 else
4435 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4436 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4437 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4438 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4439 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4440 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4441 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4442 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4443 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4444 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4445 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4446 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4447 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4448 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4449 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4450 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4451 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4452}
4453
4454
4455/**
4456 * @callback_method_impl{FNDBGFHANDLERDEV}
4457 */
4458static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4459{
4460 if (pszArgs)
4461 {
4462 uint16_t uDevId = 0;
4463 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4464 if (RT_SUCCESS(rc))
4465 {
4466 DTE_T Dte;
4467 rc = iommuAmdReadDte(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4468 if (RT_SUCCESS(rc))
4469 {
4470 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4471 return;
4472 }
4473
4474 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4475 }
4476 else
4477 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4478 }
4479 else
4480 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4481}
4482
4483
4484#if 0
4485/**
4486 * @callback_method_impl{FNDBGFHANDLERDEV}
4487 */
4488static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4489{
4490 RT_NOREF(pszArgs);
4491
4492 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4493 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4494 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4495
4496 uint8_t cTables = 0;
4497 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4498 {
4499 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4500 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4501 if (GCPhysDevTab)
4502 ++cTables;
4503 }
4504
4505 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4506 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4507 if (!cTables)
4508 return;
4509
4510 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4511 {
4512 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4513 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4514 if (GCPhysDevTab)
4515 {
4516 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4517 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4518 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4519
4520 void *pvDevTab = RTMemAllocZ(cbDevTab);
4521 if (RT_LIKELY(pvDevTab))
4522 {
4523 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4524 if (RT_SUCCESS(rc))
4525 {
4526 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4527 {
4528 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
4529 if ( pDte->n.u1Valid
4530 || pDte->n.u1IntrMapValid)
4531 {
4532 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4533 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4534 }
4535 }
4536 pHlp->pfnPrintf(pHlp, "\n");
4537 }
4538 else
4539 {
4540 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4541 cbDevTab, rc);
4542 }
4543
4544 RTMemFree(pvDevTab);
4545 }
4546 else
4547 {
4548 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4549 return;
4550 }
4551 }
4552 }
4553}
4554#endif
4555
4556/**
4557 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4558 */
4559static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4560{
4561 /** @todo IOMMU: Save state. */
4562 RT_NOREF2(pDevIns, pSSM);
4563 LogFlowFunc(("\n"));
4564 return VERR_NOT_IMPLEMENTED;
4565}
4566
4567
4568/**
4569 * @callback_method_impl{FNSSMDEVLOADEXEC}
4570 */
4571static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4572{
4573 /** @todo IOMMU: Load state. */
4574 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4575 LogFlowFunc(("\n"));
4576 return VERR_NOT_IMPLEMENTED;
4577}
4578
4579
4580/**
4581 * @interface_method_impl{PDMDEVREG,pfnReset}
4582 */
4583static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4584{
4585 /*
4586 * Resets read-write portion of the IOMMU state.
4587 *
4588 * State data not initialized here is expected to be initialized during
4589 * device construction and remain read-only through the lifetime of the VM.
4590 */
4591 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4592 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4593 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4594
4595 IOMMU_LOCK_NORET(pDevIns);
4596
4597 LogFlowFunc(("\n"));
4598
4599 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4600
4601 pThis->CmdBufBaseAddr.u64 = 0;
4602 pThis->CmdBufBaseAddr.n.u4Len = 8;
4603
4604 pThis->EvtLogBaseAddr.u64 = 0;
4605 pThis->EvtLogBaseAddr.n.u4Len = 8;
4606
4607 pThis->Ctrl.u64 = 0;
4608 pThis->Ctrl.n.u1Coherent = 1;
4609 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4610
4611 pThis->ExclRangeBaseAddr.u64 = 0;
4612 pThis->ExclRangeLimit.u64 = 0;
4613
4614 pThis->PprLogBaseAddr.u64 = 0;
4615 pThis->PprLogBaseAddr.n.u4Len = 8;
4616
4617 pThis->HwEvtHi.u64 = 0;
4618 pThis->HwEvtLo = 0;
4619 pThis->HwEvtStatus.u64 = 0;
4620
4621 pThis->GALogBaseAddr.u64 = 0;
4622 pThis->GALogBaseAddr.n.u4Len = 8;
4623 pThis->GALogTailAddr.u64 = 0;
4624
4625 pThis->PprLogBBaseAddr.u64 = 0;
4626 pThis->PprLogBBaseAddr.n.u4Len = 8;
4627
4628 pThis->EvtLogBBaseAddr.u64 = 0;
4629 pThis->EvtLogBBaseAddr.n.u4Len = 8;
4630
4631 pThis->PerfOptCtrl.u32 = 0;
4632
4633 pThis->XtGenIntrCtrl.u64 = 0;
4634 pThis->XtPprIntrCtrl.u64 = 0;
4635 pThis->XtGALogIntrCtrl.u64 = 0;
4636
4637 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4638
4639 pThis->CmdBufHeadPtr.u64 = 0;
4640 pThis->CmdBufTailPtr.u64 = 0;
4641 pThis->EvtLogHeadPtr.u64 = 0;
4642 pThis->EvtLogTailPtr.u64 = 0;
4643
4644 pThis->Status.u64 = 0;
4645
4646 pThis->PprLogHeadPtr.u64 = 0;
4647 pThis->PprLogTailPtr.u64 = 0;
4648
4649 pThis->GALogHeadPtr.u64 = 0;
4650 pThis->GALogTailPtr.u64 = 0;
4651
4652 pThis->PprLogBHeadPtr.u64 = 0;
4653 pThis->PprLogBTailPtr.u64 = 0;
4654
4655 pThis->EvtLogBHeadPtr.u64 = 0;
4656 pThis->EvtLogBTailPtr.u64 = 0;
4657
4658 pThis->PprLogAutoResp.u64 = 0;
4659 pThis->PprLogOverflowEarly.u64 = 0;
4660 pThis->PprLogBOverflowEarly.u64 = 0;
4661
4662 pThis->IommuBar.u64 = 0;
4663 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4664 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4665
4666 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4667
4668 IOMMU_UNLOCK(pDevIns);
4669}
4670
4671
4672/**
4673 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4674 */
4675static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4676{
4677 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4678 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4679 LogFlowFunc(("\n"));
4680
4681 /* Close the command thread semaphore. */
4682 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4683 {
4684 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4685 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4686 }
4687 return VINF_SUCCESS;
4688}
4689
4690
4691/**
4692 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4693 */
4694static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4695{
4696 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4697 RT_NOREF(pCfg);
4698
4699 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4700 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4701 pThisCC->pDevInsR3 = pDevIns;
4702
4703 LogFlowFunc(("iInstance=%d\n", iInstance));
4704
4705 /*
4706 * Register the IOMMU with PDM.
4707 */
4708 PDMIOMMUREGR3 IommuReg;
4709 RT_ZERO(IommuReg);
4710 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4711 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4712 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4713 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4714 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4715 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4716 if (RT_FAILURE(rc))
4717 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4718 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4719 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4720 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4721 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4722 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4723 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4724 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4725 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4726
4727 /*
4728 * Initialize read-only PCI configuration space.
4729 */
4730 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4731 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4732
4733 /* Header. */
4734 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4735 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4736 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
4737 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4738 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4739 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4740 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4741 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4742 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4743 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4744 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4745 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4746 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4747 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4748
4749 /* Capability Header. */
4750 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4751 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4752 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4753 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
4754 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4755 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4756 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4757 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4758 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4759 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4760 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4761
4762 /* Base Address Register. */
4763 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4764 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4765
4766 /* IOMMU Range Register. */
4767 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4768
4769 /* Misc. Information Register. */
4770 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4771 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4772 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4773 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4774 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4775 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4776 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4777 uint32_t const uMiscInfoReg1 = 0;
4778 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4779 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4780
4781 /* MSI Capability Header register. */
4782 PDMMSIREG MsiReg;
4783 RT_ZERO(MsiReg);
4784 MsiReg.cMsiVectors = 1;
4785 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4786 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4787 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4788
4789 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4790#if 0
4791 /* MSI Address Lo. */
4792 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4793 /* MSI Address Hi. */
4794 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4795 /* MSI Data. */
4796 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4797#endif
4798
4799#if 0
4800 /** @todo IOMMU: I don't know if we need to support this, enable later if
4801 * required. */
4802 /* MSI Mapping Capability Header register. */
4803 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4804 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4805 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4806 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4807 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4808 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4809 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4810#endif
4811
4812 /*
4813 * Register the PCI function with PDM.
4814 */
4815 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4816 AssertLogRelRCReturn(rc, rc);
4817
4818 /*
4819 * Register MSI support for the PCI device.
4820 * This must be done -after- register it as a PCI device!
4821 */
4822 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4823 AssertRCReturn(rc, rc);
4824
4825 /*
4826 * Intercept PCI config. space accesses.
4827 */
4828 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4829 AssertLogRelRCReturn(rc, rc);
4830
4831 /*
4832 * Create the MMIO region.
4833 * Mapping of the region is done when software configures it via PCI config space.
4834 */
4835 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4836 NULL /* pvUser */, IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING,
4837 "AMD-IOMMU", &pThis->hMmio);
4838 AssertLogRelRCReturn(rc, rc);
4839
4840 /*
4841 * Register saved state.
4842 */
4843 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4844 NULL, NULL, NULL,
4845 NULL, iommuAmdR3SaveExec, NULL,
4846 NULL, iommuAmdR3LoadExec, NULL);
4847 AssertLogRelRCReturn(rc, rc);
4848
4849 /*
4850 * Register debugger info items.
4851 */
4852 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
4853 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
4854#if 0
4855 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
4856#endif
4857
4858# ifdef VBOX_WITH_STATISTICS
4859 /*
4860 * Statistics.
4861 */
4862 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioReadR3", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4863 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioReadRZ", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4864
4865 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWriteR3", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4866 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWriteRZ", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4867
4868 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemapR3", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
4869 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRZ", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
4870
4871 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
4872 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
4873 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
4874 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
4875 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
4876 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
4877 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
4878 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
4879 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
4880# endif
4881
4882 /*
4883 * Create the command thread and its event semaphore.
4884 */
4885 char szDevIommu[64];
4886 RT_ZERO(szDevIommu);
4887 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
4888 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
4889 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
4890 AssertLogRelRCReturn(rc, rc);
4891
4892 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
4893 AssertLogRelRCReturn(rc, rc);
4894
4895 /*
4896 * Initialize read-only registers.
4897 * NOTE! Fields here must match their corresponding field in the ACPI tables.
4898 */
4899 /** @todo Don't remove the =0 assignment for now. It's just there so it's easier
4900 * for me to see existing features that we might want to implement. Do it
4901 * later. */
4902 pThis->ExtFeat.u64 = 0;
4903 pThis->ExtFeat.n.u1PrefetchSup = 0;
4904 pThis->ExtFeat.n.u1PprSup = 0;
4905 pThis->ExtFeat.n.u1X2ApicSup = 0;
4906 pThis->ExtFeat.n.u1NoExecuteSup = 0;
4907 pThis->ExtFeat.n.u1GstTranslateSup = 0;
4908 pThis->ExtFeat.n.u1InvAllSup = 1;
4909 pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4910 pThis->ExtFeat.n.u1HwErrorSup = 1;
4911 pThis->ExtFeat.n.u1PerfCounterSup = 0;
4912 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4913 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4914 pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
4915 pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
4916 pThis->ExtFeat.n.u2SmiFilterSup = 0;
4917 pThis->ExtFeat.n.u3SmiFilterCount = 0;
4918 pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
4919 pThis->ExtFeat.n.u2DualPprLogSup = 0;
4920 pThis->ExtFeat.n.u2DualEvtLogSup = 0;
4921 pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
4922 pThis->ExtFeat.n.u1UserSupervisorSup = 0;
4923 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
4924 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
4925 pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
4926 pThis->ExtFeat.n.u1PprAutoRespSup = 0;
4927 pThis->ExtFeat.n.u2MarcSup = 0;
4928 pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
4929 pThis->ExtFeat.n.u1PerfOptSup = 0;
4930 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
4931 pThis->ExtFeat.n.u1GstIoSup = 0;
4932 pThis->ExtFeat.n.u1HostAccessSup = 0;
4933 pThis->ExtFeat.n.u1EnhancedPprSup = 0;
4934 pThis->ExtFeat.n.u1AttrForwardSup = 0;
4935 pThis->ExtFeat.n.u1HostDirtySup = 0;
4936 pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
4937 pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
4938 pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
4939
4940 pThis->RsvdReg = 0;
4941
4942 pThis->DevSpecificFeat.u64 = 0;
4943 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
4944 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
4945
4946 pThis->DevSpecificCtrl.u64 = 0;
4947 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
4948 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
4949
4950 pThis->DevSpecificStatus.u64 = 0;
4951 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
4952 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
4953
4954 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
4955
4956 /*
4957 * Initialize parts of the IOMMU state as it would during reset.
4958 * Must be called -after- initializing PCI config. space registers.
4959 */
4960 iommuAmdR3Reset(pDevIns);
4961
4962 return VINF_SUCCESS;
4963}
4964
4965# else /* !IN_RING3 */
4966
4967/**
4968 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4969 */
4970static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
4971{
4972 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4973 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4974 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4975
4976 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4977
4978 /* Set up the MMIO RZ handlers. */
4979 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
4980 AssertRCReturn(rc, rc);
4981
4982 /* Set up the IOMMU RZ callbacks. */
4983 PDMIOMMUREGCC IommuReg;
4984 RT_ZERO(IommuReg);
4985 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4986 IommuReg.idxIommu = pThis->idxIommu;
4987 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4988 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4989 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4990 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4991 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4992 AssertRCReturn(rc, rc);
4993
4994 return VINF_SUCCESS;
4995}
4996
4997# endif /* !IN_RING3 */
4998
4999/**
5000 * The device registration structure.
5001 */
5002const PDMDEVREG g_DeviceIommuAmd =
5003{
5004 /* .u32Version = */ PDM_DEVREG_VERSION,
5005 /* .uReserved0 = */ 0,
5006 /* .szName = */ "iommu-amd",
5007 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
5008 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
5009 /* .cMaxInstances = */ ~0U,
5010 /* .uSharedVersion = */ 42,
5011 /* .cbInstanceShared = */ sizeof(IOMMU),
5012 /* .cbInstanceCC = */ sizeof(IOMMUCC),
5013 /* .cbInstanceRC = */ sizeof(IOMMURC),
5014 /* .cMaxPciDevices = */ 1,
5015 /* .cMaxMsixVectors = */ 0,
5016 /* .pszDescription = */ "IOMMU (AMD)",
5017#if defined(IN_RING3)
5018 /* .pszRCMod = */ "VBoxDDRC.rc",
5019 /* .pszR0Mod = */ "VBoxDDR0.r0",
5020 /* .pfnConstruct = */ iommuAmdR3Construct,
5021 /* .pfnDestruct = */ iommuAmdR3Destruct,
5022 /* .pfnRelocate = */ NULL,
5023 /* .pfnMemSetup = */ NULL,
5024 /* .pfnPowerOn = */ NULL,
5025 /* .pfnReset = */ iommuAmdR3Reset,
5026 /* .pfnSuspend = */ NULL,
5027 /* .pfnResume = */ NULL,
5028 /* .pfnAttach = */ NULL,
5029 /* .pfnDetach = */ NULL,
5030 /* .pfnQueryInterface = */ NULL,
5031 /* .pfnInitComplete = */ NULL,
5032 /* .pfnPowerOff = */ NULL,
5033 /* .pfnSoftReset = */ NULL,
5034 /* .pfnReserved0 = */ NULL,
5035 /* .pfnReserved1 = */ NULL,
5036 /* .pfnReserved2 = */ NULL,
5037 /* .pfnReserved3 = */ NULL,
5038 /* .pfnReserved4 = */ NULL,
5039 /* .pfnReserved5 = */ NULL,
5040 /* .pfnReserved6 = */ NULL,
5041 /* .pfnReserved7 = */ NULL,
5042#elif defined(IN_RING0)
5043 /* .pfnEarlyConstruct = */ NULL,
5044 /* .pfnConstruct = */ iommuAmdRZConstruct,
5045 /* .pfnDestruct = */ NULL,
5046 /* .pfnFinalDestruct = */ NULL,
5047 /* .pfnRequest = */ NULL,
5048 /* .pfnReserved0 = */ NULL,
5049 /* .pfnReserved1 = */ NULL,
5050 /* .pfnReserved2 = */ NULL,
5051 /* .pfnReserved3 = */ NULL,
5052 /* .pfnReserved4 = */ NULL,
5053 /* .pfnReserved5 = */ NULL,
5054 /* .pfnReserved6 = */ NULL,
5055 /* .pfnReserved7 = */ NULL,
5056#elif defined(IN_RC)
5057 /* .pfnConstruct = */ iommuAmdRZConstruct,
5058 /* .pfnReserved0 = */ NULL,
5059 /* .pfnReserved1 = */ NULL,
5060 /* .pfnReserved2 = */ NULL,
5061 /* .pfnReserved3 = */ NULL,
5062 /* .pfnReserved4 = */ NULL,
5063 /* .pfnReserved5 = */ NULL,
5064 /* .pfnReserved6 = */ NULL,
5065 /* .pfnReserved7 = */ NULL,
5066#else
5067# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5068#endif
5069 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
5070};
5071
5072#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5073
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