VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86313

Last change on this file since 86313 was 86313, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Linux build fixes.
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1/* $Id: DevIommuAmd.cpp 86313 2020-09-28 11:13:06Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31
32#include "VBoxDD.h"
33#include "DevIommuAmd.h"
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** Release log prefix string. */
40#define IOMMU_LOG_PFX "IOMMU-AMD"
41/** The current saved state version. */
42#define IOMMU_SAVED_STATE_VERSION 1
43/** The IOTLB entry magic. */
44#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46#ifndef DEBUG_ramshankar
47/** Temporary, make permanent later (get rid of define entirely and remove old
48 * code). This allow ssub-qword accesses to qword registers. Write accesses
49 * seems to work (needs testing one sub-path of the code), Read accesses not yet
50 * converted. */
51# define IOMMU_NEW_REGISTER_ACCESS
52#endif
53
54
55/*********************************************************************************************************************************
56* Structures and Typedefs *
57*********************************************************************************************************************************/
58/**
59 * Acquires the IOMMU PDM lock.
60 * This will make a long jump to ring-3 to acquire the lock if necessary.
61 */
62#define IOMMU_LOCK(a_pDevIns) \
63 do { \
64 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
65 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
66 { /* likely */ } \
67 else \
68 return rcLock; \
69 } while (0)
70
71/**
72 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
73 * This will make a long jump to ring-3 to acquire the lock if necessary.
74 */
75#define IOMMU_LOCK_NORET(a_pDevIns) \
76 do { \
77 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
78 AssertRC(rcLock); \
79 } while (0)
80
81/**
82 * Releases the IOMMU PDM lock.
83 */
84#define IOMMU_UNLOCK(a_pDevIns) \
85 do { \
86 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
87 } while (0)
88
89/**
90 * Asserts that the critsect is owned by this thread.
91 */
92#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
93 do { \
94 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95 } while (0)
96
97/**
98 * Asserts that the critsect is not owned by this thread.
99 */
100#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
101 do { \
102 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
103 } while (0)
104
105/**
106 * IOMMU operations (transaction) types.
107 */
108typedef enum IOMMUOP
109{
110 /** Address translation request. */
111 IOMMUOP_TRANSLATE_REQ = 0,
112 /** Memory read request. */
113 IOMMUOP_MEM_READ,
114 /** Memory write request. */
115 IOMMUOP_MEM_WRITE,
116 /** Interrupt request. */
117 IOMMUOP_INTR_REQ,
118 /** Command. */
119 IOMMUOP_CMD
120} IOMMUOP;
121AssertCompileSize(IOMMUOP, 4);
122
123/**
124 * I/O page walk result.
125 */
126typedef struct
127{
128 /** The translated system physical address. */
129 RTGCPHYS GCPhysSpa;
130 /** The number of offset bits in the system physical address. */
131 uint8_t cShift;
132 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
133 uint8_t fIoPerm;
134 /** Padding. */
135 uint8_t abPadding[2];
136} IOWALKRESULT;
137/** Pointer to an I/O walk result struct. */
138typedef IOWALKRESULT *PIOWALKRESULT;
139/** Pointer to a const I/O walk result struct. */
140typedef IOWALKRESULT *PCIOWALKRESULT;
141
142/**
143 * IOMMU I/O TLB Entry.
144 * Keep this as small and aligned as possible.
145 */
146typedef struct
147{
148 /** The translated system physical address (SPA) of the page. */
149 RTGCPHYS GCPhysSpa;
150 /** The index of the 4K page within a large page. */
151 uint32_t idxSubPage;
152 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
153 uint8_t fIoPerm;
154 /** The number of offset bits in the translation indicating page size. */
155 uint8_t cShift;
156 /** Alignment padding. */
157 uint8_t afPadding[2];
158} IOTLBE_T;
159AssertCompileSize(IOTLBE_T, 16);
160/** Pointer to an IOMMU I/O TLB entry struct. */
161typedef IOTLBE_T *PIOTLBE_T;
162/** Pointer to a const IOMMU I/O TLB entry struct. */
163typedef IOTLBE_T const *PCIOTLBE_T;
164
165/**
166 * The shared IOMMU device state.
167 */
168typedef struct IOMMU
169{
170 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
171 uint32_t idxIommu;
172 /** Alignment padding. */
173 uint32_t uPadding0;
174
175 /** Whether the command thread is sleeping. */
176 bool volatile fCmdThreadSleeping;
177 /** Alignment padding. */
178 uint8_t afPadding0[3];
179 /** Whether the command thread has been signaled for wake up. */
180 bool volatile fCmdThreadSignaled;
181 /** Alignment padding. */
182 uint8_t afPadding1[3];
183
184 /** The event semaphore the command thread waits on. */
185 SUPSEMEVENT hEvtCmdThread;
186 /** The MMIO handle. */
187 IOMMMIOHANDLE hMmio;
188
189 /** @name PCI: Base capability block registers.
190 * @{ */
191 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
192 /** @} */
193
194 /** @name MMIO: Control and status registers.
195 * @{ */
196 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
197 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
198 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
199 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
200 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
201 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
202 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
203 /** @} */
204
205 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
206 * @{ */
207 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
208 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
209 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
210 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
211 /** @} */
212
213 /** @todo IOMMU: SMI filter. */
214
215 /** @name MMIO: Guest Virtual-APIC Log registers.
216 * @{ */
217 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
218 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
219 /** @} */
220
221 /** @name MMIO: Alternate PPR and Event Log registers.
222 * @{ */
223 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
224 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
225 /** @} */
226
227 /** @name MMIO: Device-specific feature registers.
228 * @{ */
229 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
230 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
231 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
232 /** @} */
233
234 /** @name MMIO: MSI Capability Block registers.
235 * @{ */
236 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
237 /** @} */
238
239 /** @name MMIO: Performance Optimization Control registers.
240 * @{ */
241 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
242 /** @} */
243
244 /** @name MMIO: x2APIC Control registers.
245 * @{ */
246 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
247 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
248 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
249 /** @} */
250
251 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
252 * @{ */
253 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
254 /** @} */
255
256 /** @name MMIO: Reserved register.
257 * @{ */
258 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
259 /** @} */
260
261 /** @name MMIO: Command and Event Log pointer registers.
262 * @{ */
263 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
264 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
265 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
266 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
267 /** @} */
268
269 /** @name MMIO: Command and Event Status register.
270 * @{ */
271 IOMMU_STATUS_T Status; /**< IOMMU status register. */
272 /** @} */
273
274 /** @name MMIO: PPR Log Head and Tail pointer registers.
275 * @{ */
276 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
277 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
278 /** @} */
279
280 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
281 * @{ */
282 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
283 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
284 /** @} */
285
286 /** @name MMIO: PPR Log B Head and Tail pointer registers.
287 * @{ */
288 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
289 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
290 /** @} */
291
292 /** @name MMIO: Event Log B Head and Tail pointer registers.
293 * @{ */
294 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
295 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
296 /** @} */
297
298 /** @name MMIO: PPR Log Overflow protection registers.
299 * @{ */
300 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
301 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
302 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
303 /** @} */
304
305 /** @todo IOMMU: IOMMU Event counter registers. */
306
307#ifdef VBOX_WITH_STATISTICS
308 /** @name IOMMU: Stat counters.
309 * @{ */
310 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
311 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
312
313 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
314 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
315
316 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
317 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
318
319 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
320 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
321 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
322 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
323
324 STAMCOUNTER StatCmd; /**< Number of commands processed. */
325 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
326 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
327 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
328 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
329 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
330 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
331 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
332 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
333 /** @} */
334#endif
335} IOMMU;
336/** Pointer to the IOMMU device state. */
337typedef struct IOMMU *PIOMMU;
338/** Pointer to the const IOMMU device state. */
339typedef const struct IOMMU *PCIOMMU;
340AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
341AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
342AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
343AssertCompileMemberAlignment(IOMMU, hMmio, 8);
344AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
345
346/**
347 * The ring-3 IOMMU device state.
348 */
349typedef struct IOMMUR3
350{
351 /** Device instance. */
352 PPDMDEVINSR3 pDevInsR3;
353 /** The IOMMU helpers. */
354 PCPDMIOMMUHLPR3 pIommuHlpR3;
355 /** The command thread handle. */
356 R3PTRTYPE(PPDMTHREAD) pCmdThread;
357} IOMMUR3;
358/** Pointer to the ring-3 IOMMU device state. */
359typedef IOMMUR3 *PIOMMUR3;
360
361/**
362 * The ring-0 IOMMU device state.
363 */
364typedef struct IOMMUR0
365{
366 /** Device instance. */
367 PPDMDEVINSR0 pDevInsR0;
368 /** The IOMMU helpers. */
369 PCPDMIOMMUHLPR0 pIommuHlpR0;
370} IOMMUR0;
371/** Pointer to the ring-0 IOMMU device state. */
372typedef IOMMUR0 *PIOMMUR0;
373
374/**
375 * The raw-mode IOMMU device state.
376 */
377typedef struct IOMMURC
378{
379 /** Device instance. */
380 PPDMDEVINSR0 pDevInsRC;
381 /** The IOMMU helpers. */
382 PCPDMIOMMUHLPRC pIommuHlpRC;
383} IOMMURC;
384/** Pointer to the raw-mode IOMMU device state. */
385typedef IOMMURC *PIOMMURC;
386
387/** The IOMMU device state for the current context. */
388typedef CTX_SUFF(IOMMU) IOMMUCC;
389/** Pointer to the IOMMU device state for the current context. */
390typedef CTX_SUFF(PIOMMU) PIOMMUCC;
391
392/**
393 * IOMMU register access.
394 */
395typedef struct IOMMUREGACC
396{
397 const char *pszName;
398 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
399 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
400} IOMMUREGACC;
401/** Pointer to an IOMMU register access. */
402typedef IOMMUREGACC *PIOMMUREGACC;
403/** Pointer to a const IOMMU register access. */
404typedef IOMMUREGACC const *PCIOMMUREGACC;
405
406
407/*********************************************************************************************************************************
408* Global Variables *
409*********************************************************************************************************************************/
410/**
411 * An array of the number of device table segments supported.
412 * Indexed by u2DevTabSegSup.
413 */
414static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
415
416/**
417 * An array of the masks to select the device table segment index from a device ID.
418 */
419static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
420
421/**
422 * An array of the shift values to select the device table segment index from a
423 * device ID.
424 */
425static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
426
427/**
428 * The maximum size (inclusive) of each device table segment (0 to 7).
429 * Indexed by the device table segment index.
430 */
431static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
432
433
434#ifndef VBOX_DEVICE_STRUCT_TESTCASE
435/**
436 * Gets the maximum number of buffer entries for the given buffer length.
437 *
438 * @returns Number of buffer entries.
439 * @param uEncodedLen The length (power-of-2 encoded).
440 */
441DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
442{
443 Assert(uEncodedLen > 7);
444 return 2 << (uEncodedLen - 1);
445}
446
447
448/**
449 * Gets the total length of the buffer given a base register's encoded length.
450 *
451 * @returns The length of the buffer in bytes.
452 * @param uEncodedLen The length (power-of-2 encoded).
453 */
454DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
455{
456 Assert(uEncodedLen > 7);
457 return (2 << (uEncodedLen - 1)) << 4;
458}
459
460
461/**
462 * Gets the number of (unconsumed) entries in the event log.
463 *
464 * @returns The number of entries in the event log.
465 * @param pThis The IOMMU device state.
466 */
467static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
468{
469 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
470 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
471 if (idxTail >= idxHead)
472 return idxTail - idxHead;
473
474 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
475 return cMaxEvts - idxHead + idxTail;
476}
477
478
479#if 0
480/**
481 * Gets the number of (unconsumed) commands in the command buffer.
482 *
483 * @returns The number of commands in the command buffer.
484 * @param pThis The IOMMU device state.
485 */
486static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
487{
488 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
489 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
490 if (idxTail >= idxHead)
491 return idxTail - idxHead;
492
493 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
494 return cMaxCmds - idxHead + idxTail;
495}
496#endif
497
498
499DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
500{
501 IOMMU_STATUS_T Status;
502 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
503 return Status;
504}
505
506
507DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
508{
509 IOMMU_CTRL_T Ctrl;
510 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
511 return Ctrl;
512}
513
514
515/**
516 * Returns whether MSI is enabled for the IOMMU.
517 *
518 * @returns Whether MSI is enabled.
519 * @param pDevIns The IOMMU device instance.
520 *
521 * @note There should be a PCIDevXxx function for this.
522 */
523static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
524{
525 MSI_CAP_HDR_T MsiCapHdr;
526 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
527 return MsiCapHdr.n.u1MsiEnable;
528}
529
530
531/**
532 * Signals a PCI target abort.
533 *
534 * @param pDevIns The IOMMU device instance.
535 */
536static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
537{
538 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
539 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
540 PDMPciDevSetStatus(pPciDev, u16Status);
541}
542
543
544/**
545 * Wakes up the command thread if there are commands to be processed or if
546 * processing is requested to be stopped by software.
547 *
548 * @param pDevIns The IOMMU device instance.
549 */
550static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
551{
552 IOMMU_ASSERT_LOCKED(pDevIns);
553 Log5Func(("\n"));
554
555 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
556 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
557 if (Status.n.u1CmdBufRunning)
558 {
559 Log5Func(("Signaling command thread\n"));
560 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
561 }
562}
563
564
565/**
566 * Reads the Device Table Base Address Register.
567 */
568static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
569{
570 RT_NOREF(pDevIns, offReg);
571 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
572 return VINF_SUCCESS;
573}
574
575
576/**
577 * Reads the Command Buffer Base Address Register.
578 */
579static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
580{
581 RT_NOREF(pDevIns, offReg);
582 *pu64Value = pThis->CmdBufBaseAddr.u64;
583 return VINF_SUCCESS;
584}
585
586
587/**
588 * Reads the Event Log Base Address Register.
589 */
590static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
591{
592 RT_NOREF(pDevIns, offReg);
593 *pu64Value = pThis->EvtLogBaseAddr.u64;
594 return VINF_SUCCESS;
595}
596
597
598/**
599 * Reads the Control Register.
600 */
601static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
602{
603 RT_NOREF(pDevIns, offReg);
604 *pu64Value = pThis->Ctrl.u64;
605 return VINF_SUCCESS;
606}
607
608
609/**
610 * Reads the Exclusion Range Base Address Register.
611 */
612static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
613{
614 RT_NOREF(pDevIns, offReg);
615 *pu64Value = pThis->ExclRangeBaseAddr.u64;
616 return VINF_SUCCESS;
617}
618
619
620/**
621 * Reads to the Exclusion Range Limit Register.
622 */
623static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
624{
625 RT_NOREF(pDevIns, offReg);
626 *pu64Value = pThis->ExclRangeLimit.u64;
627 return VINF_SUCCESS;
628}
629
630
631/**
632 * Reads to the Extended Feature Register.
633 */
634static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
635{
636 RT_NOREF(pDevIns, offReg);
637 *pu64Value = pThis->ExtFeat.u64;
638 return VINF_SUCCESS;
639}
640
641
642/**
643 * Reads to the PPR Log Base Address Register.
644 */
645static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
646{
647 RT_NOREF(pDevIns, offReg);
648 *pu64Value = pThis->PprLogBaseAddr.u64;
649 return VINF_SUCCESS;
650}
651
652
653/**
654 * Writes the Hardware Event Register (Hi).
655 */
656static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
657{
658 RT_NOREF(pDevIns, offReg);
659 *pu64Value = pThis->HwEvtHi.u64;
660 return VINF_SUCCESS;
661}
662
663
664/**
665 * Reads the Hardware Event Register (Lo).
666 */
667static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
668{
669 RT_NOREF(pDevIns, offReg);
670 *pu64Value = pThis->HwEvtLo;
671 return VINF_SUCCESS;
672}
673
674
675/**
676 * Reads the Hardware Event Status Register.
677 */
678static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
679{
680 RT_NOREF(pDevIns, offReg);
681 *pu64Value = pThis->HwEvtStatus.u64;
682 return VINF_SUCCESS;
683}
684
685
686/**
687 * Reads to the GA Log Base Address Register.
688 */
689static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
690{
691 RT_NOREF(pDevIns, offReg);
692 *pu64Value = pThis->GALogBaseAddr.u64;
693 return VINF_SUCCESS;
694}
695
696
697/**
698 * Reads to the PPR Log B Base Address Register.
699 */
700static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
701{
702 RT_NOREF(pDevIns, offReg);
703 *pu64Value = pThis->PprLogBBaseAddr.u64;
704 return VINF_SUCCESS;
705}
706
707
708/**
709 * Reads to the Event Log B Base Address Register.
710 */
711static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
712{
713 RT_NOREF(pDevIns, offReg);
714 *pu64Value = pThis->EvtLogBBaseAddr.u64;
715 return VINF_SUCCESS;
716}
717
718
719/**
720 * Reads the Device Table Segment Base Address Register.
721 */
722static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
723{
724 RT_NOREF(pDevIns);
725
726 /* Figure out which segment is being written. */
727 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
728 uint8_t const idxSegment = offSegment + 1;
729 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
730
731 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
732 return VINF_SUCCESS;
733}
734
735
736/**
737 * Reads the Device Specific Feature Extension (DSFX) Register.
738 */
739static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
740{
741 RT_NOREF(pDevIns, offReg);
742 *pu64Value = pThis->DevSpecificFeat.u64;
743 return VINF_SUCCESS;
744}
745
746/**
747 * Reads the Device Specific Control Extension (DSCX) Register.
748 */
749static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
750{
751 RT_NOREF(pDevIns, offReg);
752 *pu64Value = pThis->DevSpecificCtrl.u64;
753 return VINF_SUCCESS;
754}
755
756
757/**
758 * Reads the Device Specific Status Extension (DSSX) Register.
759 */
760static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
761{
762 RT_NOREF(pDevIns, offReg);
763 *pu64Value = pThis->DevSpecificStatus.u64;
764 return VINF_SUCCESS;
765}
766
767
768/**
769 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
770 */
771static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
772{
773 RT_NOREF(pDevIns, offReg);
774 uint32_t const uLo = pThis->MiscInfo.au32[0];
775 uint32_t const uHi = pThis->MiscInfo.au32[1];
776 *pu64Value = RT_MAKE_U64(uLo, uHi);
777 return VINF_SUCCESS;
778}
779
780
781#ifdef IOMMU_NEW_REGISTER_ACCESS
782/**
783 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
784 * Register (32-bit).
785 */
786static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
787{
788 RT_NOREF(pThis, offReg);
789 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
790 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
791 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
792 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
793 *pu64Value = RT_MAKE_U64(uLo, uHi);
794 return VINF_SUCCESS;
795}
796
797
798/**
799 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
800 */
801static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
802{
803 RT_NOREF(pThis, offReg);
804 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
805 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
806 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
807 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
808 *pu64Value = RT_MAKE_U64(uLo, uHi);
809 return VINF_SUCCESS;
810}
811#endif
812
813
814/**
815 * Reads the Command Buffer Head Pointer Register.
816 */
817static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
818{
819 RT_NOREF(pDevIns, offReg);
820 *pu64Value = pThis->CmdBufHeadPtr.u64;
821 return VINF_SUCCESS;
822}
823
824
825/**
826 * Reads the Command Buffer Tail Pointer Register.
827 */
828static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
829{
830 RT_NOREF(pDevIns, offReg);
831 *pu64Value = pThis->CmdBufTailPtr.u64;
832 return VINF_SUCCESS;
833}
834
835
836/**
837 * Reads the Event Log Head Pointer Register.
838 */
839static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
840{
841 RT_NOREF(pDevIns, offReg);
842 *pu64Value = pThis->EvtLogHeadPtr.u64;
843 return VINF_SUCCESS;
844}
845
846
847/**
848 * Reads the Event Log Tail Pointer Register.
849 */
850static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
851{
852 RT_NOREF(pDevIns, offReg);
853 *pu64Value = pThis->EvtLogTailPtr.u64;
854 return VINF_SUCCESS;
855}
856
857
858/**
859 * Reads the Status Register.
860 */
861static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
862{
863 RT_NOREF(pDevIns, offReg);
864 *pu64Value = pThis->Status.u64;
865 return VINF_SUCCESS;
866}
867
868#ifndef IOMMU_NEW_REGISTER_ACCESS
869static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
870{
871 RT_NOREF(pDevIns, pThis, offReg, u64Value);
872 return VINF_SUCCESS;
873}
874#endif
875
876
877/**
878 * Writes the Device Table Base Address Register.
879 */
880static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
881{
882 RT_NOREF(pDevIns, offReg);
883
884 /* Mask out all unrecognized bits. */
885 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
886
887 /* Update the register. */
888 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
889 return VINF_SUCCESS;
890}
891
892
893/**
894 * Writes the Command Buffer Base Address Register.
895 */
896static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
897{
898 RT_NOREF(pDevIns, offReg);
899
900 /*
901 * While this is not explicitly specified like the event log base address register,
902 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
903 * Inconsistent specs :/
904 */
905 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
906 if (Status.n.u1CmdBufRunning)
907 {
908 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
909 return VINF_SUCCESS;
910 }
911
912 /* Mask out all unrecognized bits. */
913 CMD_BUF_BAR_T CmdBufBaseAddr;
914 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
915
916 /* Validate the length. */
917 if (CmdBufBaseAddr.n.u4Len >= 8)
918 {
919 /* Update the register. */
920 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
921
922 /*
923 * Writing the command buffer base address, clears the command buffer head and tail pointers.
924 * See AMD spec. 2.4 "Commands".
925 */
926 pThis->CmdBufHeadPtr.u64 = 0;
927 pThis->CmdBufTailPtr.u64 = 0;
928 }
929 else
930 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
931
932 return VINF_SUCCESS;
933}
934
935
936/**
937 * Writes the Event Log Base Address Register.
938 */
939static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
940{
941 RT_NOREF(pDevIns, offReg);
942
943 /*
944 * IOMMU behavior is undefined when software writes this register when event logging is running.
945 * In our emulation, we ignore the write entirely.
946 * See AMD IOMMU spec. "Event Log Base Address Register".
947 */
948 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
949 if (Status.n.u1EvtLogRunning)
950 {
951 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
952 return VINF_SUCCESS;
953 }
954
955 /* Mask out all unrecognized bits. */
956 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
957 EVT_LOG_BAR_T EvtLogBaseAddr;
958 EvtLogBaseAddr.u64 = u64Value;
959
960 /* Validate the length. */
961 if (EvtLogBaseAddr.n.u4Len >= 8)
962 {
963 /* Update the register. */
964 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
965
966 /*
967 * Writing the event log base address, clears the event log head and tail pointers.
968 * See AMD spec. 2.5 "Event Logging".
969 */
970 pThis->EvtLogHeadPtr.u64 = 0;
971 pThis->EvtLogTailPtr.u64 = 0;
972 }
973 else
974 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
975
976 return VINF_SUCCESS;
977}
978
979
980/**
981 * Writes the Control Register.
982 */
983static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
984{
985 RT_NOREF(pDevIns, offReg);
986
987 /* Mask out all unrecognized bits. */
988 u64Value &= IOMMU_CTRL_VALID_MASK;
989 IOMMU_CTRL_T NewCtrl;
990 NewCtrl.u64 = u64Value;
991
992 /* Ensure the device table segments are within limits. */
993 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
994 {
995 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
996
997 /* Update the register. */
998 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
999
1000 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
1001 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
1002
1003 /* Enable or disable event logging when the bit transitions. */
1004 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
1005 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1006 if ( fOldEvtLogEn != fNewEvtLogEn
1007 || fOldIommuEn != fNewIommuEn)
1008 {
1009 if ( fNewIommuEn
1010 && fNewEvtLogEn)
1011 {
1012 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1013 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1014 }
1015 else
1016 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1017 }
1018
1019 /* Enable or disable command buffer processing when the bit transitions. */
1020 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1021 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1022 if ( fOldCmdBufEn != fNewCmdBufEn
1023 || fOldIommuEn != fNewIommuEn)
1024 {
1025 if ( fNewCmdBufEn
1026 && fNewIommuEn)
1027 {
1028 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1029 LogFunc(("Command buffer enabled\n"));
1030
1031 /* Wake up the command thread to start processing commands. */
1032 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1033 }
1034 else
1035 {
1036 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1037 LogFunc(("Command buffer disabled\n"));
1038 }
1039 }
1040 }
1041 else
1042 {
1043 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1044 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1045 }
1046
1047 return VINF_SUCCESS;
1048}
1049
1050
1051/**
1052 * Writes to the Exclusion Range Base Address Register.
1053 */
1054static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1055{
1056 RT_NOREF(pDevIns, offReg);
1057 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1058 return VINF_SUCCESS;
1059}
1060
1061
1062/**
1063 * Writes to the Exclusion Range Limit Register.
1064 */
1065static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1066{
1067 RT_NOREF(pDevIns, offReg);
1068 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1069 u64Value |= UINT64_C(0xfff);
1070 pThis->ExclRangeLimit.u64 = u64Value;
1071 return VINF_SUCCESS;
1072}
1073
1074
1075/**
1076 * Writes the Hardware Event Register (Hi).
1077 */
1078static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1079{
1080 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1081 RT_NOREF(pDevIns, offReg);
1082 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1083 pThis->HwEvtHi.u64 = u64Value;
1084 return VINF_SUCCESS;
1085}
1086
1087
1088/**
1089 * Writes the Hardware Event Register (Lo).
1090 */
1091static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1092{
1093 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1094 RT_NOREF(pDevIns, offReg);
1095 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1096 pThis->HwEvtLo = u64Value;
1097 return VINF_SUCCESS;
1098}
1099
1100
1101/**
1102 * Writes the Hardware Event Status Register.
1103 */
1104static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1105{
1106 RT_NOREF(pDevIns, offReg);
1107
1108 /* Mask out all unrecognized bits. */
1109 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1110
1111 /*
1112 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1113 * If the current status bits or the bits being written are both 0, we've nothing to do.
1114 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1115 */
1116 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1117 if (!(HwStatus & RT_BIT(0)))
1118 return VINF_SUCCESS;
1119 if (u64Value & HwStatus & RT_BIT_64(0))
1120 HwStatus &= ~RT_BIT_64(0);
1121 if (u64Value & HwStatus & RT_BIT_64(1))
1122 HwStatus &= ~RT_BIT_64(1);
1123
1124 /* Update the register. */
1125 pThis->HwEvtStatus.u64 = HwStatus;
1126 return VINF_SUCCESS;
1127}
1128
1129
1130/**
1131 * Writes the Device Table Segment Base Address Register.
1132 */
1133static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1134{
1135 RT_NOREF(pDevIns);
1136
1137 /* Figure out which segment is being written. */
1138 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1139 uint8_t const idxSegment = offSegment + 1;
1140 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1141
1142 /* Mask out all unrecognized bits. */
1143 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1144 DEV_TAB_BAR_T DevTabSegBar;
1145 DevTabSegBar.u64 = u64Value;
1146
1147 /* Validate the size. */
1148 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1149 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1150 if (uSegSize <= uMaxSegSize)
1151 {
1152 /* Update the register. */
1153 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1154 }
1155 else
1156 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1157
1158 return VINF_SUCCESS;
1159}
1160
1161
1162#ifndef IOMMU_NEW_REGISTER_ACCESS
1163/**
1164 * Writes the MSI Capability Header Register.
1165 */
1166static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1167{
1168 RT_NOREF(pThis, offReg);
1169 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1170 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1171 MSI_CAP_HDR_T MsiCapHdr;
1172 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1173 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1174 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1175 return VINF_SUCCESS;
1176}
1177
1178
1179/**
1180 * Writes the MSI Address (Lo) Register (32-bit).
1181 */
1182static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1183{
1184 RT_NOREF(pThis, offReg);
1185 Assert(!RT_HI_U32(u64Value));
1186 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1187 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1188 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
1189 return VINF_SUCCESS;
1190}
1191
1192
1193/**
1194 * Writes the MSI Address (Hi) Register (32-bit).
1195 */
1196static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1197{
1198 RT_NOREF(pThis, offReg);
1199 Assert(!RT_HI_U32(u64Value));
1200 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1201 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1202 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
1203 return VINF_SUCCESS;
1204}
1205
1206
1207/**
1208 * Writes the MSI Data Register (32-bit).
1209 */
1210static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1211{
1212 RT_NOREF(pThis, offReg);
1213 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1214 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1215 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
1216 return VINF_SUCCESS;
1217}
1218#else
1219/**
1220 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1221 */
1222static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1223{
1224 RT_NOREF(pDevIns, offReg);
1225
1226 /* MSI Vector Register 0 is read-only. */
1227 /* MSI Vector Register 1. */
1228 uint32_t const uReg = u64Value >> 32;
1229 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
1230 return VINF_SUCCESS;
1231}
1232
1233
1234/**
1235 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1236 * Register (32-bit).
1237 */
1238static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1239{
1240 RT_NOREF(pThis, offReg);
1241 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1242 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1243
1244 /* MSI capability header. */
1245 {
1246 uint32_t const uReg = u64Value;
1247 MSI_CAP_HDR_T MsiCapHdr;
1248 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1249 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1250 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1251 }
1252
1253 /* MSI Address Lo. */
1254 {
1255 uint32_t const uReg = u64Value >> 32;
1256 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
1257 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1258 }
1259
1260 return VINF_SUCCESS;
1261}
1262
1263
1264/**
1265 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1266 */
1267static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1268{
1269 RT_NOREF(pThis, offReg);
1270 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1271 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1272
1273 /* MSI Address Hi. */
1274 {
1275 uint32_t const uReg = u64Value;
1276 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
1277 }
1278
1279 /* MSI Data. */
1280 {
1281 uint32_t const uReg = u64Value >> 32;
1282 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
1283 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1284 }
1285
1286 return VINF_SUCCESS;
1287}
1288#endif
1289
1290
1291/**
1292 * Writes the Command Buffer Head Pointer Register.
1293 */
1294static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1295{
1296 RT_NOREF(pDevIns, offReg);
1297
1298 /*
1299 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1300 * In our emulation, we ignore the write entirely.
1301 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1302 */
1303 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1304 if (Status.n.u1CmdBufRunning)
1305 {
1306 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1307 return VINF_SUCCESS;
1308 }
1309
1310 /*
1311 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1312 * In our emulation, we ignore the write entirely.
1313 */
1314 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1315 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1316 Assert(cbBuf <= _512K);
1317 if (offBuf >= cbBuf)
1318 {
1319 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1320 return VINF_SUCCESS;
1321 }
1322
1323 /* Update the register. */
1324 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1325
1326 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1327
1328 Log5Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1329 return VINF_SUCCESS;
1330}
1331
1332
1333/**
1334 * Writes the Command Buffer Tail Pointer Register.
1335 */
1336static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1337{
1338 RT_NOREF(pDevIns, offReg);
1339
1340 /*
1341 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1342 * In our emulation, we ignore the write entirely.
1343 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1344 */
1345 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1346 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1347 Assert(cbBuf <= _512K);
1348 if (offBuf >= cbBuf)
1349 {
1350 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1351 return VINF_SUCCESS;
1352 }
1353
1354 /*
1355 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1356 * head pointer after adding one or more commands to the buffer.
1357 *
1358 * However, we cannot enforce this strictly because it's legal for software to shrink the
1359 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1360 * at 0). Software might even make the queue empty by making head and tail equal which is
1361 * allowed. I don't think we can or should try too hard to prevent software shooting itself
1362 * in the foot here. As long as we make sure the offset value is within the circular buffer
1363 * bounds (which we do by masking bits above) it should be sufficient.
1364 */
1365 pThis->CmdBufTailPtr.au32[0] = offBuf;
1366
1367 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1368
1369 Log5Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1370 return VINF_SUCCESS;
1371}
1372
1373
1374/**
1375 * Writes the Event Log Head Pointer Register.
1376 */
1377static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1378{
1379 RT_NOREF(pDevIns, offReg);
1380
1381 /*
1382 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1383 * In our emulation, we ignore the write entirely.
1384 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1385 */
1386 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1387 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1388 Assert(cbBuf <= _512K);
1389 if (offBuf >= cbBuf)
1390 {
1391 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1392 return VINF_SUCCESS;
1393 }
1394
1395 /* Update the register. */
1396 pThis->EvtLogHeadPtr.au32[0] = offBuf;
1397
1398 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1399 return VINF_SUCCESS;
1400}
1401
1402
1403/**
1404 * Writes the Event Log Tail Pointer Register.
1405 */
1406static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1407{
1408 RT_NOREF(pDevIns, offReg);
1409 NOREF(pThis);
1410
1411 /*
1412 * IOMMU behavior is undefined when software writes this register when the event log is running.
1413 * In our emulation, we ignore the write entirely.
1414 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1415 */
1416 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1417 if (Status.n.u1EvtLogRunning)
1418 {
1419 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1420 return VINF_SUCCESS;
1421 }
1422
1423 /*
1424 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1425 * In our emulation, we ignore the write entirely.
1426 */
1427 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1428 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1429 Assert(cbBuf <= _512K);
1430 if (offBuf >= cbBuf)
1431 {
1432 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1433 return VINF_SUCCESS;
1434 }
1435
1436 /* Update the register. */
1437 pThis->EvtLogTailPtr.au32[0] = offBuf;
1438
1439 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1440 return VINF_SUCCESS;
1441}
1442
1443
1444/**
1445 * Writes the Status Register.
1446 */
1447static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1448{
1449 RT_NOREF(pDevIns, offReg);
1450
1451 /* Mask out all unrecognized bits. */
1452 u64Value &= IOMMU_STATUS_VALID_MASK;
1453
1454 /*
1455 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1456 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1457 */
1458 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1459 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1460 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1461 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1462
1463 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1464
1465 /* Update the register. */
1466 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1467 return VINF_SUCCESS;
1468}
1469
1470#ifdef IOMMU_NEW_REGISTER_ACCESS
1471/**
1472 * Register access table 0.
1473 * The MMIO offset of each entry must be a multiple of 8!
1474 */
1475static const IOMMUREGACC g_aRegAccess0[] =
1476{
1477 /* MMIO off. Register name Read function Write function */
1478 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
1479 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
1480 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
1481 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
1482 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
1483 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
1484 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
1485 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
1486 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
1487 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
1488 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
1489 { /* 0x58 */ NULL, NULL, NULL },
1490
1491 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
1492 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
1493 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
1494 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
1495 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
1496 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
1497 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
1498 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
1499 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
1500 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
1501 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
1502 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
1503 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
1504 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
1505 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
1506 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
1507
1508 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
1509 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
1510 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
1511 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
1512
1513 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1514 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1515 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1516 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1517 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1518 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1519 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1520
1521 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
1522 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
1523 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
1524
1525 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
1526 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
1527 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
1528 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
1529
1530 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
1531 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
1532 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
1533};
1534AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1535
1536/**
1537 * Register access table 1.
1538 * The MMIO offset of each entry must be a multiple of 8!
1539 */
1540static const IOMMUREGACC g_aRegAccess1[] =
1541{
1542 /* MMIO offset Register name Read function Write function */
1543 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
1544 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
1545 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
1546 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
1547 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
1548 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
1549 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
1550 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
1551 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
1552 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
1553 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
1554 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
1555};
1556AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1557
1558/**
1559 * Register access table 2.
1560 * The MMIO offset of each entry must be a multiple of 8!
1561 */
1562static const IOMMUREGACC g_aRegAccess2[] =
1563{
1564 /* MMIO offset Register name Read Function Write function */
1565 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
1566
1567 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
1568 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
1569 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
1570 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
1571
1572 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
1573 { /* 0x2028 */ NULL, NULL, NULL },
1574
1575 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
1576 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
1577
1578 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
1579 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
1580
1581 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
1582 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
1583
1584 { /* 0x2060 */ NULL, NULL, NULL },
1585 { /* 0x2068 */ NULL, NULL, NULL },
1586
1587 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
1588 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
1589
1590 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
1591 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
1592 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
1593};
1594AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1595
1596
1597/**
1598 * Gets the register access structure given its MMIO offset.
1599 *
1600 * @returns The register access structure, or NULL if the offset is invalid.
1601 * @param off The MMIO offset of the register being accessed.
1602 */
1603static PCIOMMUREGACC iommuAmdGetRegAccessForOffset(uint32_t off)
1604{
1605 /* Figure out which table the register belongs to and validate its index. */
1606 PCIOMMUREGACC pReg;
1607 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1608 {
1609 uint32_t const idxReg = off >> 3;
1610 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1611 pReg = &g_aRegAccess0[idxReg];
1612 }
1613 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1614 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1615 {
1616 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1617 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1618 pReg = &g_aRegAccess1[idxReg];
1619 }
1620 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1621 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1622 {
1623 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1624 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1625 pReg = &g_aRegAccess2[idxReg];
1626 }
1627 else
1628 return NULL;
1629
1630 return pReg;
1631}
1632#endif
1633
1634
1635/**
1636 * Writes an IOMMU register (32-bit and 64-bit).
1637 *
1638 * @returns Strict VBox status code.
1639 * @param pDevIns The IOMMU device instance.
1640 * @param off MMIO byte offset to the register.
1641 * @param cb The size of the write access.
1642 * @param uValue The value being written.
1643 *
1644 * @thread EMT.
1645 */
1646static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1647{
1648 /*
1649 * Validate the access in case of IOM bug or incorrect assumption.
1650 */
1651 Assert(off < IOMMU_MMIO_REGION_SIZE);
1652 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1653 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1654
1655 Log5Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1656
1657 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1658#ifndef IOMMU_NEW_REGISTER_ACCESS
1659 switch (off)
1660 {
1661 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1662 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1663 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1664 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1665 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1666 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1667 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1668
1669 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1670 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1671 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1672 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1673
1674 case IOMMU_MMIO_OFF_GALOG_BAR:
1675 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1676
1677 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1678 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1679
1680 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1681 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1682 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1683 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1684 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1685 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1686 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1687
1688 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1689 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1690 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1691
1692 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1693 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1694 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1695 {
1696 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1697 if (cb == 4 || RT_FAILURE(rcStrict))
1698 return rcStrict;
1699 uValue >>= 32;
1700 RT_FALL_THRU();
1701 }
1702 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1703 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1704 {
1705 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1706 if (cb == 4 || RT_FAILURE(rcStrict))
1707 return rcStrict;
1708 uValue >>= 32;
1709 RT_FALL_THRU();
1710 }
1711 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1712 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1713
1714 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1715
1716 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1717 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1718 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1719
1720 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1721 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1722 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1723 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1724 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1725 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1726 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1727 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1728 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1729 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1730 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1731 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1732
1733 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1734
1735 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1736 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1737 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1738 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1739
1740 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1741
1742 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1743 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1744
1745 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1746 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1747
1748 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1749 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1750
1751 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1752 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1753
1754 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1755 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1756 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1757
1758 /* Not implemented. */
1759 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1760 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1761 {
1762 LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1763 return VINF_SUCCESS;
1764 }
1765
1766 /* Unknown. */
1767 default:
1768 {
1769 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1770 return VINF_SUCCESS;
1771 }
1772 }
1773#else
1774 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1775 if (pReg)
1776 { /* likely */ }
1777 else
1778 {
1779 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
1780 return VINF_SUCCESS;
1781 }
1782
1783 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
1784 if (pReg->pfnWrite)
1785 { /* likely */ }
1786 else
1787 {
1788 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1789 return VINF_SUCCESS;
1790 }
1791
1792 /*
1793 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
1794 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
1795 * consecutive 32-bit registers.
1796 */
1797 if (cb == 8)
1798 {
1799 if (!(off & 7))
1800 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1801
1802 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1803 return VINF_SUCCESS;
1804 }
1805
1806 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
1807 Assert(cb == 4);
1808 if (!(off & 7))
1809 {
1810 /*
1811 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
1812 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1813 */
1814 uint64_t u64Read;
1815 if (pReg->pfnRead)
1816 {
1817 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1818 if (RT_FAILURE(rcStrict))
1819 {
1820 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1821 return rcStrict;
1822 }
1823 }
1824 else
1825 u64Read = 0;
1826
1827 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
1828 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1829 }
1830
1831 /*
1832 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
1833 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1834 */
1835 Assert(!(off & 3));
1836 Assert(off & 7);
1837 Assert(off >= 4);
1838 uint64_t u64Read;
1839 if (pReg->pfnRead)
1840 {
1841 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1842 if (RT_FAILURE(rcStrict))
1843 {
1844 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1845 return rcStrict;
1846 }
1847 }
1848 else
1849 u64Read = 0;
1850
1851 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
1852 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1853#endif
1854}
1855
1856
1857/**
1858 * Reads an IOMMU register (64-bit) given its MMIO offset.
1859 *
1860 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1861 * boundary include the lower half of the subsequent register.
1862 *
1863 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1864 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1865 * software will only perform 32-bit reads on those 32-bit registers that are
1866 * aligned on 8-byte boundaries.
1867 *
1868 * @returns Strict VBox status code.
1869 * @param pDevIns The IOMMU device instance.
1870 * @param off The MMIO offset of the register in bytes.
1871 * @param puResult Where to store the value being read.
1872 *
1873 * @thread EMT.
1874 */
1875static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1876{
1877 Assert(off < IOMMU_MMIO_REGION_SIZE);
1878 Assert(!(off & 7) || !(off & 3));
1879
1880 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1881 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1882 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1883
1884 Log5Func(("off=%#x\n", off));
1885
1886#ifndef IOMMU_NEW_REGISTER_ACCESS
1887 /** @todo IOMMU: fine-grained locking? */
1888 uint64_t uReg;
1889 switch (off)
1890 {
1891 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1892 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1893 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1894 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1895 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1896 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1897 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1898
1899 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1900 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1901 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1902 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1903
1904 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1905 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1906
1907 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1908 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1909
1910 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1911 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1912 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1913 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1914 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1915 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1916 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1917 {
1918 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1919 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1920 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1921 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1922 break;
1923 }
1924
1925 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1926 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1927 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1928
1929 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1930 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1931 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1932 {
1933 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1934 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1935 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1936 break;
1937 }
1938 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1939 {
1940 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1941 break;
1942 }
1943 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1944 {
1945 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1946 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1947 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1948 break;
1949 }
1950 case IOMMU_MMIO_OFF_MSI_DATA:
1951 {
1952 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1953 break;
1954 }
1955 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1956 {
1957 /*
1958 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1959 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1960 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1961 * 0 for this register.
1962 */
1963 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1964 break;
1965 }
1966
1967 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1968
1969 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1970 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1971 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1972
1973 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1974 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1975 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1976 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1977 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1978 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1979 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1980 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1981 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1982 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1983 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1984 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1985
1986 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1987
1988 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1989 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1990 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1991 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1992
1993 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
1994
1995 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
1996 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
1997
1998 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
1999 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
2000
2001 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
2002 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
2003
2004 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
2005 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
2006
2007 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
2008 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
2009 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
2010
2011 /* Not implemented. */
2012 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
2013 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
2014 {
2015 LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
2016 uReg = 0;
2017 break;
2018 }
2019
2020 /* Unknown. */
2021 default:
2022 {
2023 LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
2024 uReg = 0;
2025 return VINF_IOM_MMIO_UNUSED_00;
2026 }
2027 }
2028
2029 *puResult = uReg;
2030 return VINF_SUCCESS;
2031#else
2032 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
2033 if (pReg)
2034 { /* likely */ }
2035 else
2036 {
2037 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2038 return VINF_IOM_MMIO_UNUSED_FF;
2039 }
2040
2041 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2042 if (pReg->pfnRead)
2043 { /* likely */ }
2044 else
2045 {
2046 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2047 return VINF_IOM_MMIO_UNUSED_00;
2048 }
2049
2050 /*
2051 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2052 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2053 */
2054 if (!(off & 7))
2055 return pReg->pfnRead(pDevIns, pThis, off, puResult);
2056
2057 /*
2058 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2059 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2060 */
2061 Assert(!(off & 3));
2062 Assert(off & 7);
2063 Assert(off >= 4);
2064 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2065 if (RT_SUCCESS(rcStrict))
2066 *puResult >>= 32;
2067 else
2068 {
2069 *puResult = 0;
2070 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2071 }
2072
2073 return rcStrict;
2074#endif
2075}
2076
2077
2078/**
2079 * Raises the MSI interrupt for the IOMMU device.
2080 *
2081 * @param pDevIns The IOMMU device instance.
2082 *
2083 * @thread Any.
2084 * @remarks The IOMMU lock may or may not be held.
2085 */
2086static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
2087{
2088 LogFlowFunc(("\n"));
2089 if (iommuAmdIsMsiEnabled(pDevIns))
2090 {
2091 LogFunc(("Raising MSI\n"));
2092 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2093 }
2094}
2095
2096#if 0
2097/**
2098 * Clears the MSI interrupt for the IOMMU device.
2099 *
2100 * @param pDevIns The IOMMU device instance.
2101 *
2102 * @thread Any.
2103 * @remarks The IOMMU lock may or may not be held.
2104 */
2105static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
2106{
2107 if (iommuAmdIsMsiEnabled(pDevIns))
2108 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2109}
2110#endif
2111
2112/**
2113 * Writes an entry to the event log in memory.
2114 *
2115 * @returns VBox status code.
2116 * @param pDevIns The IOMMU device instance.
2117 * @param pEvent The event to log.
2118 *
2119 * @thread Any.
2120 */
2121static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2122{
2123 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2124
2125 IOMMU_ASSERT_LOCKED(pDevIns);
2126
2127 /* Check if event logging is active and the log has not overflowed. */
2128 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2129 if ( Status.n.u1EvtLogRunning
2130 && !Status.n.u1EvtOverflow)
2131 {
2132 uint32_t const cbEvt = sizeof(*pEvent);
2133
2134 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2135 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2136 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2137
2138 /* Ensure we have space in the event log. */
2139 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2140 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2141 if (cEvts + 1 < cMaxEvts)
2142 {
2143 /* Write the event log entry to memory. */
2144 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2145 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2146 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2147 if (RT_FAILURE(rc))
2148 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2149
2150 /* Increment the event log tail pointer. */
2151 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2152 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2153
2154 /* Indicate that an event log entry was written. */
2155 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2156
2157 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2158 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2159 if (Ctrl.n.u1EvtIntrEn)
2160 iommuAmdRaiseMsiInterrupt(pDevIns);
2161 }
2162 else
2163 {
2164 /* Indicate that the event log has overflowed. */
2165 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2166
2167 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2168 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2169 if (Ctrl.n.u1EvtIntrEn)
2170 iommuAmdRaiseMsiInterrupt(pDevIns);
2171 }
2172 }
2173
2174 return VINF_SUCCESS;
2175}
2176
2177
2178/**
2179 * Sets an event in the hardware error registers.
2180 *
2181 * @param pDevIns The IOMMU device instance.
2182 * @param pEvent The event.
2183 *
2184 * @thread Any.
2185 */
2186static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2187{
2188 IOMMU_ASSERT_LOCKED(pDevIns);
2189
2190 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2191 if (pThis->ExtFeat.n.u1HwErrorSup)
2192 {
2193 if (pThis->HwEvtStatus.n.u1Valid)
2194 pThis->HwEvtStatus.n.u1Overflow = 1;
2195 pThis->HwEvtStatus.n.u1Valid = 1;
2196 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2197 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2198 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2199 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2200 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2201 }
2202}
2203
2204
2205/**
2206 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2207 *
2208 * @param uDevId The device ID.
2209 * @param uDomainId The domain ID.
2210 * @param GCPhysPtEntity The system physical address of the page table
2211 * entity.
2212 * @param enmOp The IOMMU operation being performed.
2213 * @param pEvtPageTabHwErr Where to store the initialized event.
2214 */
2215static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2216 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2217{
2218 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2219 pEvtPageTabHwErr->n.u16DevId = uDevId;
2220 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
2221 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
2222 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2223 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2224 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2225 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2226 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
2227 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
2228}
2229
2230
2231/**
2232 * Raises a PAGE_TAB_HARDWARE_ERROR event.
2233 *
2234 * @param pDevIns The IOMMU device instance.
2235 * @param enmOp The IOMMU operation being performed.
2236 * @param pEvtPageTabHwErr The page table hardware error event.
2237 *
2238 * @thread Any.
2239 */
2240static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2241{
2242 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
2243 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
2244
2245 IOMMU_LOCK_NORET(pDevIns);
2246
2247 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2248 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2249 if (enmOp != IOMMUOP_CMD)
2250 iommuAmdSetPciTargetAbort(pDevIns);
2251
2252 IOMMU_UNLOCK(pDevIns);
2253
2254 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
2255 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
2256 pEvtPageTabHwErr->n.u2Type));
2257}
2258
2259
2260#ifdef IN_RING3
2261/**
2262 * Initializes a COMMAND_HARDWARE_ERROR event.
2263 *
2264 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
2265 * @param pEvtCmdHwErr Where to store the initialized event.
2266 */
2267static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2268{
2269 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
2270 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
2271 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
2272 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
2273}
2274
2275
2276/**
2277 * Raises a COMMAND_HARDWARE_ERROR event.
2278 *
2279 * @param pDevIns The IOMMU device instance.
2280 * @param pEvtCmdHwErr The command hardware error event.
2281 *
2282 * @thread Any.
2283 */
2284static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2285{
2286 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
2287 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
2288 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2289
2290 IOMMU_LOCK_NORET(pDevIns);
2291
2292 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2293 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2294 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2295
2296 IOMMU_UNLOCK(pDevIns);
2297
2298 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
2299}
2300#endif /* IN_RING3 */
2301
2302
2303/**
2304 * Initializes a DEV_TAB_HARDWARE_ERROR event.
2305 *
2306 * @param uDevId The device ID.
2307 * @param GCPhysDte The system physical address of the failed device table
2308 * access.
2309 * @param enmOp The IOMMU operation being performed.
2310 * @param pEvtDevTabHwErr Where to store the initialized event.
2311 */
2312static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
2313 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2314{
2315 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
2316 pEvtDevTabHwErr->n.u16DevId = uDevId;
2317 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2318 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
2319 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2320 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2321 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2322 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
2323 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
2324}
2325
2326
2327/**
2328 * Raises a DEV_TAB_HARDWARE_ERROR event.
2329 *
2330 * @param pDevIns The IOMMU device instance.
2331 * @param enmOp The IOMMU operation being performed.
2332 * @param pEvtDevTabHwErr The device table hardware error event.
2333 *
2334 * @thread Any.
2335 */
2336static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2337{
2338 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2339 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2340
2341 IOMMU_LOCK_NORET(pDevIns);
2342
2343 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2344 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2345 if (enmOp != IOMMUOP_CMD)
2346 iommuAmdSetPciTargetAbort(pDevIns);
2347
2348 IOMMU_UNLOCK(pDevIns);
2349
2350 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2351 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2352}
2353
2354#ifdef IN_RING3
2355/**
2356 * Initializes an ILLEGAL_COMMAND_ERROR event.
2357 *
2358 * @param GCPhysCmd The system physical address of the failed command
2359 * access.
2360 * @param pEvtIllegalCmd Where to store the initialized event.
2361 */
2362static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2363{
2364 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2365 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2366 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2367 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2368}
2369
2370
2371/**
2372 * Raises an ILLEGAL_COMMAND_ERROR event.
2373 *
2374 * @param pDevIns The IOMMU device instance.
2375 * @param pEvtIllegalCmd The illegal command error event.
2376 */
2377static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2378{
2379 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2380 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2381 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2382
2383 IOMMU_LOCK_NORET(pDevIns);
2384
2385 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2386 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2387
2388 IOMMU_UNLOCK(pDevIns);
2389
2390 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2391}
2392#endif /* IN_RING3 */
2393
2394
2395/**
2396 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2397 *
2398 * @param uDevId The device ID.
2399 * @param uIova The I/O virtual address.
2400 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2401 * event was caused by an invalid level encoding in the
2402 * DTE.
2403 * @param enmOp The IOMMU operation being performed.
2404 * @param pEvtIllegalDte Where to store the initialized event.
2405 */
2406static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2407 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2408{
2409 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2410 pEvtIllegalDte->n.u16DevId = uDevId;
2411 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2412 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2413 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2414 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2415 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2416 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2417 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2418 * IOMMU spec here but not for this field for I/O page fault event. */
2419 Assert(!(uIova & UINT64_C(0x3)));
2420}
2421
2422
2423/**
2424 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2425 *
2426 * @param pDevIns The IOMMU instance data.
2427 * @param enmOp The IOMMU operation being performed.
2428 * @param pEvtIllegalDte The illegal device table entry event.
2429 * @param enmEvtType The illegal device table entry event type.
2430 *
2431 * @thread Any.
2432 */
2433static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2434 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2435{
2436 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2437 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2438
2439 IOMMU_LOCK_NORET(pDevIns);
2440
2441 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2442 if (enmOp != IOMMUOP_CMD)
2443 iommuAmdSetPciTargetAbort(pDevIns);
2444
2445 IOMMU_UNLOCK(pDevIns);
2446
2447 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2448 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2449 NOREF(enmEvtType);
2450}
2451
2452
2453/**
2454 * Initializes an IO_PAGE_FAULT event.
2455 *
2456 * @param uDevId The device ID.
2457 * @param uDomainId The domain ID.
2458 * @param uIova The I/O virtual address being accessed.
2459 * @param fPresent Transaction to a page marked as present (including
2460 * DTE.V=1) or interrupt marked as remapped
2461 * (IRTE.RemapEn=1).
2462 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2463 * the I/O page fault was caused by invalid level
2464 * encoding.
2465 * @param fPermDenied Permission denied for the address being accessed.
2466 * @param enmOp The IOMMU operation being performed.
2467 * @param pEvtIoPageFault Where to store the initialized event.
2468 */
2469static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2470 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2471{
2472 Assert(!fPermDenied || fPresent);
2473 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2474 pEvtIoPageFault->n.u16DevId = uDevId;
2475 //pEvtIoPageFault->n.u4PasidHi = 0;
2476 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2477 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2478 //pEvtIoPageFault->n.u1NoExecute = 0;
2479 //pEvtIoPageFault->n.u1User = 0;
2480 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2481 pEvtIoPageFault->n.u1Present = fPresent;
2482 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2483 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2484 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2485 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2486 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2487 pEvtIoPageFault->n.u64Addr = uIova;
2488}
2489
2490
2491/**
2492 * Raises an IO_PAGE_FAULT event.
2493 *
2494 * @param pDevIns The IOMMU instance data.
2495 * @param pDte The device table entry. Optional, can be NULL
2496 * depending on @a enmOp.
2497 * @param pIrte The interrupt remapping table entry. Optional, can
2498 * be NULL depending on @a enmOp.
2499 * @param enmOp The IOMMU operation being performed.
2500 * @param pEvtIoPageFault The I/O page fault event.
2501 * @param enmEvtType The I/O page fault event type.
2502 *
2503 * @thread Any.
2504 */
2505static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2506 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2507{
2508 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2509 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2510
2511 IOMMU_LOCK_NORET(pDevIns);
2512
2513 bool fSuppressEvtLogging = false;
2514 if ( enmOp == IOMMUOP_MEM_READ
2515 || enmOp == IOMMUOP_MEM_WRITE)
2516 {
2517 if ( pDte
2518 && pDte->n.u1Valid)
2519 {
2520 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2521 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2522 * suppression. Perhaps will be possible when we complete IOTLB/cache
2523 * handling. */
2524 }
2525 }
2526 else if (enmOp == IOMMUOP_INTR_REQ)
2527 {
2528 if ( pDte
2529 && pDte->n.u1IntrMapValid)
2530 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2531
2532 if ( !fSuppressEvtLogging
2533 && pIrte)
2534 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2535 }
2536 /* else: Events are never suppressed for commands. */
2537
2538 switch (enmEvtType)
2539 {
2540 case kIoPageFaultType_PermDenied:
2541 {
2542 /* Cannot be triggered by a command. */
2543 Assert(enmOp != IOMMUOP_CMD);
2544 RT_FALL_THRU();
2545 }
2546 case kIoPageFaultType_DteRsvdPagingMode:
2547 case kIoPageFaultType_PteInvalidPageSize:
2548 case kIoPageFaultType_PteInvalidLvlEncoding:
2549 case kIoPageFaultType_SkippedLevelIovaNotZero:
2550 case kIoPageFaultType_PteRsvdNotZero:
2551 case kIoPageFaultType_PteValidNotSet:
2552 case kIoPageFaultType_DteTranslationDisabled:
2553 case kIoPageFaultType_PasidInvalidRange:
2554 {
2555 /*
2556 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2557 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
2558 */
2559 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2560 {
2561 if (!fSuppressEvtLogging)
2562 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2563 if (enmOp != IOMMUOP_CMD)
2564 iommuAmdSetPciTargetAbort(pDevIns);
2565 }
2566 break;
2567 }
2568
2569 case kIoPageFaultType_UserSupervisor:
2570 {
2571 /* Access is blocked and only creates an event log entry. */
2572 if (!fSuppressEvtLogging)
2573 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2574 break;
2575 }
2576
2577 case kIoPageFaultType_IrteAddrInvalid:
2578 case kIoPageFaultType_IrteRsvdNotZero:
2579 case kIoPageFaultType_IrteRemapEn:
2580 case kIoPageFaultType_IrteRsvdIntType:
2581 case kIoPageFaultType_IntrReqAborted:
2582 case kIoPageFaultType_IntrWithPasid:
2583 {
2584 /* Only trigerred by interrupt requests. */
2585 Assert(enmOp == IOMMUOP_INTR_REQ);
2586 if (!fSuppressEvtLogging)
2587 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2588 iommuAmdSetPciTargetAbort(pDevIns);
2589 break;
2590 }
2591
2592 case kIoPageFaultType_SmiFilterMismatch:
2593 {
2594 /* Not supported and probably will never be, assert. */
2595 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2596 break;
2597 }
2598
2599 case kIoPageFaultType_DevId_Invalid:
2600 {
2601 /* Cannot be triggered by a command. */
2602 Assert(enmOp != IOMMUOP_CMD);
2603 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2604 if (!fSuppressEvtLogging)
2605 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2606 if ( enmOp == IOMMUOP_MEM_READ
2607 || enmOp == IOMMUOP_MEM_WRITE)
2608 iommuAmdSetPciTargetAbort(pDevIns);
2609 break;
2610 }
2611 }
2612
2613 IOMMU_UNLOCK(pDevIns);
2614}
2615
2616
2617/**
2618 * Returns whether the I/O virtual address is to be excluded from translation and
2619 * permission checks.
2620 *
2621 * @returns @c true if the DVA is excluded, @c false otherwise.
2622 * @param pThis The IOMMU device state.
2623 * @param pDte The device table entry.
2624 * @param uIova The I/O virtual address.
2625 *
2626 * @remarks Ensure the exclusion range is enabled prior to calling this function.
2627 *
2628 * @thread Any.
2629 */
2630static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2631{
2632 /* Ensure the exclusion range is enabled. */
2633 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2634
2635 /* Check if the IOVA falls within the exclusion range. */
2636 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2637 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2638 if (uIovaExclLast - uIova >= uIovaExclFirst)
2639 {
2640 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2641 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2642 || pDte->n.u1AllowExclusion)
2643 return true;
2644 }
2645 return false;
2646}
2647
2648
2649/**
2650 * Reads a device table entry from guest memory given the device ID.
2651 *
2652 * @returns VBox status code.
2653 * @param pDevIns The IOMMU device instance.
2654 * @param uDevId The device ID.
2655 * @param enmOp The IOMMU operation being performed.
2656 * @param pDte Where to store the device table entry.
2657 *
2658 * @thread Any.
2659 */
2660static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2661{
2662 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2663 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2664
2665 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2666 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2667
2668 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2669 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2670 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
2671
2672 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2673 uint16_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2674 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2675
2676 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2677 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2678 if (RT_FAILURE(rc))
2679 {
2680 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2681
2682 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2683 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2684 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2685 return VERR_IOMMU_IPE_1;
2686 }
2687
2688 return rc;
2689}
2690
2691
2692/**
2693 * Walks the I/O page table to translate the I/O virtual address to a system
2694 * physical address.
2695 *
2696 * @returns VBox status code.
2697 * @param pDevIns The IOMMU device instance.
2698 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2699 * @param uDevId The device ID.
2700 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2701 * permissions for the access being made.
2702 * @param pDte The device table entry.
2703 * @param enmOp The IOMMU operation being performed.
2704 * @param pWalkResult Where to store the results of the I/O page walk. This is
2705 * only updated when VINF_SUCCESS is returned.
2706 *
2707 * @thread Any.
2708 */
2709static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2710 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2711{
2712 Assert(pDte->n.u1Valid);
2713 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2714
2715 /* If the translation is not valid, raise an I/O page fault. */
2716 if (pDte->n.u1TranslationValid)
2717 { /* likely */ }
2718 else
2719 {
2720 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2721 * doesn't explicitly say whether an I/O page fault is raised. From other
2722 * places in the spec. it seems early page walk terminations (starting with
2723 * the DTE) return the state computed so far and raises an I/O page fault. So
2724 * returning an invalid translation rather than skipping translation. */
2725 LogFunc(("Translation valid bit not set -> IOPF\n"));
2726 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2727 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2728 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2729 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2730 kIoPageFaultType_DteTranslationDisabled);
2731 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2732 }
2733
2734 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2735 uint8_t const uMaxLevel = pDte->n.u3Mode;
2736 if (uMaxLevel != 0)
2737 { /* likely */ }
2738 else
2739 {
2740 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2741 if ((fAccess & fDtePerm) != fAccess)
2742 {
2743 LogFunc(("Access denied for IOVA (%#RX64). fAccess=%#x fDtePerm=%#x\n", uIova, fAccess, fDtePerm));
2744 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2745 }
2746 pWalkResult->GCPhysSpa = uIova;
2747 pWalkResult->cShift = 0;
2748 pWalkResult->fIoPerm = fDtePerm;
2749 return VINF_SUCCESS;
2750 }
2751
2752 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2753 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2754 { /* likely */ }
2755 else
2756 {
2757 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2758 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2759 * I'm just going with I/O page fault. */
2760 LogFunc(("Invalid root page table level %#x -> IOPF\n", uMaxLevel));
2761 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2762 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2763 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2764 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2765 kIoPageFaultType_PteInvalidLvlEncoding);
2766 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2767 }
2768
2769 /* Check permissions bits of the root page table. */
2770 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2771 if ((fAccess & fRootPtePerm) == fAccess)
2772 { /* likely */ }
2773 else
2774 {
2775 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2776 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2777 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2778 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2779 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2780 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2781 }
2782
2783 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2784 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2785 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2786 * table entry every time. Not sure if it's worth optimizing that case now
2787 * or if at all. */
2788
2789 /* The virtual address bits indexing table. */
2790 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2791 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2792 UINT64_C(0x00000000001ff000),
2793 UINT64_C(0x000000003fe00000),
2794 UINT64_C(0x0000007fc0000000),
2795 UINT64_C(0x0000ff8000000000),
2796 UINT64_C(0x01ff000000000000),
2797 UINT64_C(0xfe00000000000000),
2798 UINT64_C(0x0000000000000000) };
2799 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2800 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2801
2802 /* Traverse the I/O page table starting with the page directory in the DTE. */
2803 IOPTENTITY_T PtEntity;
2804 PtEntity.u64 = pDte->au64[0];
2805 for (;;)
2806 {
2807 /* Figure out the system physical address of the page table at the current level. */
2808 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2809
2810 /* Read the page table entity at the current level. */
2811 {
2812 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2813 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2814 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2815 uint64_t const offPte = idxPte << 3;
2816 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2817 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2818 if (RT_FAILURE(rc))
2819 {
2820 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2821 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2822 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2823 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2824 return VERR_IOMMU_IPE_2;
2825 }
2826 }
2827
2828 /* Check present bit. */
2829 if (PtEntity.n.u1Present)
2830 { /* likely */ }
2831 else
2832 {
2833 LogFunc(("Page table entry not present -> IOPF\n"));
2834 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2835 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2836 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2837 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2838 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2839 }
2840
2841 /* Check permission bits. */
2842 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2843 if ((fAccess & fPtePerm) == fAccess)
2844 { /* likely */ }
2845 else
2846 {
2847 LogFunc(("Page table entry permission denied (fAccess=%#x fPtePerm=%#x) -> IOPF\n", fAccess, fPtePerm));
2848 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2849 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2850 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2851 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2852 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2853 }
2854
2855 /* If this is a PTE, we're at the final level and we're done. */
2856 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2857 if (uNextLevel == 0)
2858 {
2859 /* The page size of the translation is the default (4K). */
2860 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2861 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2862 pWalkResult->fIoPerm = fPtePerm;
2863 return VINF_SUCCESS;
2864 }
2865 if (uNextLevel == 7)
2866 {
2867 /* The default page size of the translation is overridden. */
2868 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2869 uint8_t cShift = X86_PAGE_4K_SHIFT;
2870 while (GCPhysPte & RT_BIT_64(cShift++))
2871 ;
2872
2873 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2874 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2875 if ( cShift > s_acIovaLevelShifts[uLevel]
2876 && cShift < s_acIovaLevelShifts[uLevel + 1])
2877 {
2878 pWalkResult->GCPhysSpa = GCPhysPte;
2879 pWalkResult->cShift = cShift;
2880 pWalkResult->fIoPerm = fPtePerm;
2881 return VINF_SUCCESS;
2882 }
2883
2884 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2885 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2886 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2887 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2888 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2889 kIoPageFaultType_PteInvalidPageSize);
2890 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2891 }
2892
2893 /* Validate the next level encoding of the PDE. */
2894#if IOMMU_MAX_HOST_PT_LEVEL < 6
2895 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2896 { /* likely */ }
2897 else
2898 {
2899 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2900 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2901 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2902 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2903 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2904 kIoPageFaultType_PteInvalidLvlEncoding);
2905 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2906 }
2907#else
2908 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2909#endif
2910
2911 /* Validate level transition. */
2912 if (uNextLevel < uLevel)
2913 { /* likely */ }
2914 else
2915 {
2916 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2917 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2918 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2919 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2920 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2921 kIoPageFaultType_PteInvalidLvlEncoding);
2922 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2923 }
2924
2925 /* Ensure IOVA bits of skipped levels are zero. */
2926 Assert(uLevel > 0);
2927 uint64_t uIovaSkipMask = 0;
2928 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2929 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2930 if (!(uIova & uIovaSkipMask))
2931 { /* likely */ }
2932 else
2933 {
2934 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2935 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2936 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2937 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2938 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2939 kIoPageFaultType_SkippedLevelIovaNotZero);
2940 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2941 }
2942
2943 /* Continue with traversing the page directory at this level. */
2944 }
2945}
2946
2947
2948/**
2949 * Looks up an I/O virtual address from the device table.
2950 *
2951 * @returns VBox status code.
2952 * @param pDevIns The IOMMU instance data.
2953 * @param uDevId The device ID.
2954 * @param uIova The I/O virtual address to lookup.
2955 * @param cbAccess The size of the access.
2956 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2957 * permissions for the access being made.
2958 * @param enmOp The IOMMU operation being performed.
2959 * @param pGCPhysSpa Where to store the translated system physical address. Only
2960 * valid when translation succeeds and VINF_SUCCESS is
2961 * returned!
2962 *
2963 * @thread Any.
2964 */
2965static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2966 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2967{
2968 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2969
2970 /* Read the device table entry from memory. */
2971 DTE_T Dte;
2972 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2973 if (RT_SUCCESS(rc))
2974 {
2975 /* If the DTE is not valid, addresses are forwarded without translation */
2976 if (Dte.n.u1Valid)
2977 { /* likely */ }
2978 else
2979 {
2980 /** @todo IOMMU: Add to IOLTB cache. */
2981 *pGCPhysSpa = uIova;
2982 return VINF_SUCCESS;
2983 }
2984
2985 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2986 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2987 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2988 if (RT_LIKELY( !fRsvd0
2989 && !fRsvd1))
2990 { /* likely */ }
2991 else
2992 {
2993 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2994 EVT_ILLEGAL_DTE_T Event;
2995 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2996 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2997 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2998 }
2999
3000 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
3001 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable /** @todo lock or make atomic read? */
3002 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
3003 { /* likely */ }
3004 else
3005 {
3006 /** @todo IOMMU: Add to IOLTB cache. */
3007 *pGCPhysSpa = uIova;
3008 return VINF_SUCCESS;
3009 }
3010
3011 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
3012 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
3013
3014 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
3015 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
3016 uint64_t cbRemaining = cbAccess;
3017 for (;;)
3018 {
3019 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
3020 IOWALKRESULT WalkResult;
3021 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
3022 if (RT_SUCCESS(rc))
3023 {
3024 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
3025
3026 /* Store the translated base address before continuing to check permissions for any more pages. */
3027 if (cbRemaining == cbAccess)
3028 {
3029 RTGCPHYS const offSpa = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
3030 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
3031 }
3032
3033 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
3034 if (cbRemaining > cbPhysPage - offIova)
3035 {
3036 cbRemaining -= (cbPhysPage - offIova);
3037 uBaseIova += cbPhysPage;
3038 offIova = 0;
3039 }
3040 else
3041 break;
3042 }
3043 else
3044 {
3045 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
3046 uBaseIova, fAccess, rc));
3047 *pGCPhysSpa = NIL_RTGCPHYS;
3048 return rc;
3049 }
3050 }
3051
3052 return rc;
3053 }
3054
3055 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3056 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3057}
3058
3059
3060/**
3061 * Memory read request from a device.
3062 *
3063 * @returns VBox status code.
3064 * @param pDevIns The IOMMU device instance.
3065 * @param uDevId The device ID (bus, device, function).
3066 * @param uIova The I/O virtual address being read.
3067 * @param cbRead The number of bytes being read.
3068 * @param pGCPhysSpa Where to store the translated system physical address.
3069 *
3070 * @thread Any.
3071 */
3072static DECLCALLBACK(int) iommuAmdDeviceMemRead(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbRead,
3073 PRTGCPHYS pGCPhysSpa)
3074{
3075 /* Validate. */
3076 Assert(pDevIns);
3077 Assert(pGCPhysSpa);
3078 Assert(cbRead > 0);
3079
3080 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3081
3082 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3083 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3084 if (Ctrl.n.u1IommuEn)
3085 {
3086 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
3087 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbRead=%u\n", uDevId, uIova, cbRead));
3088
3089 /** @todo IOMMU: IOTLB cache lookup. */
3090
3091 /* Lookup the IOVA from the device table. */
3092 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbRead, IOMMU_IO_PERM_READ, IOMMUOP_MEM_READ, pGCPhysSpa);
3093 }
3094
3095 *pGCPhysSpa = uIova;
3096 return VINF_SUCCESS;
3097}
3098
3099
3100/**
3101 * Memory write request from a device.
3102 *
3103 * @returns VBox status code.
3104 * @param pDevIns The IOMMU device instance.
3105 * @param uDevId The device ID (bus, device, function).
3106 * @param uIova The I/O virtual address being written.
3107 * @param cbWrite The number of bytes being written.
3108 * @param pGCPhysSpa Where to store the translated physical address.
3109 *
3110 * @thread Any.
3111 */
3112static DECLCALLBACK(int) iommuAmdDeviceMemWrite(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbWrite,
3113 PRTGCPHYS pGCPhysSpa)
3114{
3115 /* Validate. */
3116 Assert(pDevIns);
3117 Assert(pGCPhysSpa);
3118 Assert(cbWrite > 0);
3119
3120 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3121
3122 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3123 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3124 if (Ctrl.n.u1IommuEn)
3125 {
3126 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
3127 LogFlowFunc(("uDevId=%#x uIova=%#RX64 cbWrite=%u\n", uDevId, uIova, cbWrite));
3128
3129 /** @todo IOMMU: IOTLB cache lookup. */
3130
3131 /* Lookup the IOVA from the device table. */
3132 return iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbWrite, IOMMU_IO_PERM_WRITE, IOMMUOP_MEM_WRITE, pGCPhysSpa);
3133 }
3134
3135 *pGCPhysSpa = uIova;
3136 return VINF_SUCCESS;
3137}
3138
3139
3140/**
3141 * Reads an interrupt remapping table entry from guest memory given its DTE.
3142 *
3143 * @returns VBox status code.
3144 * @param pDevIns The IOMMU device instance.
3145 * @param uDevId The device ID.
3146 * @param pDte The device table entry.
3147 * @param GCPhysIn The source MSI address.
3148 * @param uDataIn The source MSI data.
3149 * @param enmOp The IOMMU operation being performed.
3150 * @param pIrte Where to store the interrupt remapping table entry.
3151 *
3152 * @thread Any.
3153 */
3154static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
3155 IOMMUOP enmOp, PIRTE_T pIrte)
3156{
3157 /* Ensure the IRTE length is valid. */
3158 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
3159
3160 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
3161 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
3162 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
3163 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
3164
3165 /* Ensure the IRTE falls completely within the interrupt table. */
3166 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
3167 { /* likely */ }
3168 else
3169 {
3170 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
3171 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
3172
3173 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3174 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
3175 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3176 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3177 kIoPageFaultType_IrteAddrInvalid);
3178 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3179 }
3180
3181 /* Read the IRTE from memory. */
3182 Assert(!(GCPhysIrte & 3));
3183 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
3184 if (RT_SUCCESS(rc))
3185 return VINF_SUCCESS;
3186
3187 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
3188 * situation. Is it an I/O page fault or a device table hardware error?
3189 * There's no interrupt table hardware error event, but it's unclear what
3190 * we should do here. */
3191 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
3192 return VERR_IOMMU_IPE_4;
3193}
3194
3195
3196/**
3197 * Remaps the interrupt using the interrupt remapping table.
3198 *
3199 * @returns VBox status code.
3200 * @param pDevIns The IOMMU instance data.
3201 * @param uDevId The device ID.
3202 * @param pDte The device table entry.
3203 * @param enmOp The IOMMU operation being performed.
3204 * @param pMsiIn The source MSI.
3205 * @param pMsiOut Where to store the remapped MSI.
3206 *
3207 * @thread Any.
3208 */
3209static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
3210 PMSIMSG pMsiOut)
3211{
3212 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
3213
3214 IRTE_T Irte;
3215 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
3216 if (RT_SUCCESS(rc))
3217 {
3218 if (Irte.n.u1RemapEnable)
3219 {
3220 if (!Irte.n.u1GuestMode)
3221 {
3222 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
3223 {
3224 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
3225 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
3226 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
3227 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
3228
3229 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
3230 pMsiOut->Data.u32 = pMsiIn->Data.u32;
3231 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
3232 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
3233
3234 return VINF_SUCCESS;
3235 }
3236
3237 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3238 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3239 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3240 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3241 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
3242 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3243 }
3244
3245 LogFunc(("Guest mode not supported -> IOPF\n"));
3246 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3247 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3248 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3249 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3250 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3251 }
3252
3253 LogFunc(("Remapping disabled -> IOPF\n"));
3254 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3255 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3256 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3257 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3258 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3259 }
3260
3261 return rc;
3262}
3263
3264
3265/**
3266 * Looks up an MSI interrupt from the interrupt remapping table.
3267 *
3268 * @returns VBox status code.
3269 * @param pDevIns The IOMMU instance data.
3270 * @param uDevId The device ID.
3271 * @param enmOp The IOMMU operation being performed.
3272 * @param pMsiIn The source MSI.
3273 * @param pMsiOut Where to store the remapped MSI.
3274 *
3275 * @thread Any.
3276 */
3277static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3278{
3279 /* Read the device table entry from memory. */
3280 LogFlowFunc(("uDevId=%#x enmOp=%u\n", uDevId, enmOp));
3281
3282 DTE_T Dte;
3283 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3284 if (RT_SUCCESS(rc))
3285 {
3286 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
3287 if (Dte.n.u1IntrMapValid)
3288 {
3289 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3290 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3291 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3292 if (RT_LIKELY( !fRsvd0
3293 && !fRsvd1))
3294 { /* likely */ }
3295 else
3296 {
3297 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3298 fRsvd1));
3299 EVT_ILLEGAL_DTE_T Event;
3300 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3301 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3302 return VERR_IOMMU_INTR_REMAP_FAILED;
3303 }
3304
3305 /*
3306 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3307 * that's connected through HyperTransport it might be possible; but for us, it
3308 * doesn't seem we need to specially handle these pins.
3309 */
3310
3311 /*
3312 * Validate the MSI source address.
3313 *
3314 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3315 * CPU is concerned, the MSI region is fixed and we must ensure no other device
3316 * claims the region as I/O space.
3317 *
3318 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3319 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3320 * See Intel spec. 10.11.1 "Message Address Register Format".
3321 */
3322 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3323 {
3324 /*
3325 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3326 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3327 */
3328 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3329 bool fPassThru = false;
3330 switch (u8DeliveryMode)
3331 {
3332 case VBOX_MSI_DELIVERY_MODE_FIXED:
3333 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3334 {
3335 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3336 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3337 {
3338 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
3339 iommuAmdSetPciTargetAbort(pDevIns);
3340 return VERR_IOMMU_INTR_REMAP_DENIED;
3341 }
3342
3343 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3344 {
3345 fPassThru = true;
3346 break;
3347 }
3348
3349 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3350 {
3351 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3352 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3353 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3354 {
3355 /*
3356 * We don't support guest interrupt remapping yet. When we do, we'll need to
3357 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3358 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3359 * already reads the control register, add that as a parameter when we eventually
3360 * support guest interrupt remapping. For now, just assert.
3361 */
3362 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3363 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3364 NOREF(pThis);
3365
3366 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3367 }
3368
3369 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3370 EVT_ILLEGAL_DTE_T Event;
3371 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3372 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3373 return VERR_IOMMU_INTR_REMAP_FAILED;
3374 }
3375
3376 /* Paranoia. */
3377 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
3378
3379 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3380
3381 EVT_ILLEGAL_DTE_T Event;
3382 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3383 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3384 return VERR_IOMMU_INTR_REMAP_FAILED;
3385 }
3386
3387 /* SMIs are passed through unmapped. We don't implement SMI filters. */
3388 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3389 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3390 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3391 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3392 default:
3393 {
3394 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3395 iommuAmdSetPciTargetAbort(pDevIns);
3396 return VERR_IOMMU_INTR_REMAP_FAILED;
3397 }
3398 }
3399
3400 if (fPassThru)
3401 {
3402 *pMsiOut = *pMsiIn;
3403 return VINF_SUCCESS;
3404 }
3405
3406 iommuAmdSetPciTargetAbort(pDevIns);
3407 return VERR_IOMMU_INTR_REMAP_DENIED;
3408 }
3409 else
3410 {
3411 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3412 return VERR_IOMMU_INTR_REMAP_FAILED;
3413 }
3414 }
3415 else
3416 {
3417 /** @todo IOMMU: Add to interrupt remapping cache. */
3418 LogFlowFunc(("DTE interrupt map not valid\n"));
3419 *pMsiOut = *pMsiIn;
3420 return VINF_SUCCESS;
3421 }
3422 }
3423
3424 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3425 return VERR_IOMMU_INTR_REMAP_FAILED;
3426}
3427
3428
3429/**
3430 * Interrupt remap request from a device.
3431 *
3432 * @returns VBox status code.
3433 * @param pDevIns The IOMMU device instance.
3434 * @param uDevId The device ID (bus, device, function).
3435 * @param pMsiIn The source MSI.
3436 * @param pMsiOut Where to store the remapped MSI.
3437 */
3438static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3439{
3440 /* Validate. */
3441 Assert(pDevIns);
3442 Assert(pMsiIn);
3443 Assert(pMsiOut);
3444
3445 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3446
3447 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3448 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3449 if (Ctrl.n.u1IommuEn)
3450 {
3451 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3452 LogFlowFunc(("uDevId=%#x\n", uDevId));
3453 /** @todo Cache? */
3454
3455 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3456 }
3457
3458 *pMsiOut = *pMsiIn;
3459 return VINF_SUCCESS;
3460}
3461
3462
3463/**
3464 * @callback_method_impl{FNIOMMMIONEWWRITE}
3465 */
3466static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3467{
3468 NOREF(pvUser);
3469 Assert(cb == 4 || cb == 8);
3470 Assert(!(off & (cb - 1)));
3471
3472 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3473 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3474
3475 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
3476 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
3477}
3478
3479
3480/**
3481 * @callback_method_impl{FNIOMMMIONEWREAD}
3482 */
3483static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3484{
3485 NOREF(pvUser);
3486 Assert(cb == 4 || cb == 8);
3487 Assert(!(off & (cb - 1)));
3488
3489 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3490 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3491
3492 uint64_t uResult;
3493 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
3494 if (cb == 8)
3495 *(uint64_t *)pv = uResult;
3496 else
3497 *(uint32_t *)pv = (uint32_t)uResult;
3498
3499 return rcStrict;
3500}
3501
3502# ifdef IN_RING3
3503
3504/**
3505 * Processes an IOMMU command.
3506 *
3507 * @returns VBox status code.
3508 * @param pDevIns The IOMMU device instance.
3509 * @param pCmd The command to process.
3510 * @param GCPhysCmd The system physical address of the command.
3511 * @param pEvtError Where to store the error event in case of failures.
3512 *
3513 * @thread Command thread.
3514 */
3515static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3516{
3517 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3518
3519 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3520 STAM_COUNTER_INC(&pThis->StatCmd);
3521
3522 uint8_t const bCmd = pCmd->n.u4Opcode;
3523 switch (bCmd)
3524 {
3525 case IOMMU_CMD_COMPLETION_WAIT:
3526 {
3527 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3528
3529 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3530 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
3531
3532 /* Validate reserved bits in the command. */
3533 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3534 {
3535 /* If Completion Store is requested, write the StoreData to the specified address. */
3536 if (pCmdComWait->n.u1Store)
3537 {
3538 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3539 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3540 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3541 if (RT_FAILURE(rc))
3542 {
3543 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3544 GCPhysStore, rc));
3545 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3546 return VERR_IOMMU_CMD_HW_ERROR;
3547 }
3548 }
3549
3550 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3551 if (pCmdComWait->n.u1Interrupt)
3552 {
3553 IOMMU_LOCK(pDevIns);
3554 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3555 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3556 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3557 IOMMU_UNLOCK(pDevIns);
3558
3559 if (fRaiseInt)
3560 iommuAmdRaiseMsiInterrupt(pDevIns);
3561 }
3562 return VINF_SUCCESS;
3563 }
3564 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3565 return VERR_IOMMU_CMD_INVALID_FORMAT;
3566 }
3567
3568 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3569 {
3570 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3571 * then. */
3572 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3573 return VINF_SUCCESS;
3574 }
3575
3576 case IOMMU_CMD_INV_IOMMU_PAGES:
3577 {
3578 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3579 * then. */
3580 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3581 return VINF_SUCCESS;
3582 }
3583
3584 case IOMMU_CMD_INV_IOTLB_PAGES:
3585 {
3586 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3587
3588 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3589 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3590 {
3591 /** @todo IOMMU: Implement remote IOTLB invalidation. */
3592 return VERR_NOT_IMPLEMENTED;
3593 }
3594 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3595 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3596 }
3597
3598 case IOMMU_CMD_INV_INTR_TABLE:
3599 {
3600 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3601 * then. */
3602 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3603 return VINF_SUCCESS;
3604 }
3605
3606 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3607 {
3608 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3609 if (pThis->ExtFeat.n.u1PrefetchSup)
3610 {
3611 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
3612 return VINF_SUCCESS;
3613 }
3614 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3615 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3616 }
3617
3618 case IOMMU_CMD_COMPLETE_PPR_REQ:
3619 {
3620 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3621
3622 /* We don't support PPR requests yet. */
3623 Assert(!pThis->ExtFeat.n.u1PprSup);
3624 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3625 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3626 }
3627
3628 case IOMMU_CMD_INV_IOMMU_ALL:
3629 {
3630 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3631
3632 if (pThis->ExtFeat.n.u1InvAllSup)
3633 {
3634 /** @todo IOMMU: Invalidate all. Pretend success until then. */
3635 return VINF_SUCCESS;
3636 }
3637 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3638 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3639 }
3640 }
3641
3642 STAM_COUNTER_DEC(&pThis->StatCmd);
3643 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3644 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3645 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3646}
3647
3648
3649/**
3650 * The IOMMU command thread.
3651 *
3652 * @returns VBox status code.
3653 * @param pDevIns The IOMMU device instance.
3654 * @param pThread The command thread.
3655 */
3656static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3657{
3658 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3659
3660 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3661 return VINF_SUCCESS;
3662
3663 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3664 {
3665 /*
3666 * Sleep perpetually until we are woken up to process commands.
3667 */
3668 {
3669 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3670 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3671 if (!fSignaled)
3672 {
3673 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3674 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3675 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3676 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3677 break;
3678 Log5Func(("Woken up with rc=%Rrc\n", rc));
3679 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3680 }
3681 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3682 }
3683
3684 /*
3685 * Fetch and process IOMMU commands.
3686 */
3687 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
3688 * at a time) and is expensive due to calls to PGM for fetching guest memory.
3689 * We could optimize by fetching a bunch of commands at a time reducing
3690 * number of calls to PGM. In the longer run we could lock the memory and
3691 * mappings and accessing them directly. */
3692 IOMMU_LOCK(pDevIns);
3693
3694 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3695 if (Status.n.u1CmdBufRunning)
3696 {
3697 /* Get the offset we need to read the command from memory (circular buffer offset). */
3698 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3699 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3700 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3701 Assert(offHead < cbCmdBuf);
3702 while (offHead != pThis->CmdBufTailPtr.n.off)
3703 {
3704 /* Read the command from memory. */
3705 CMD_GENERIC_T Cmd;
3706 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3707 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3708 if (RT_SUCCESS(rc))
3709 {
3710 /* Increment the command buffer head pointer. */
3711 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3712 pThis->CmdBufHeadPtr.n.off = offHead;
3713
3714 /* Process the fetched command. */
3715 EVT_GENERIC_T EvtError;
3716 IOMMU_UNLOCK(pDevIns);
3717 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3718 IOMMU_LOCK(pDevIns);
3719 if (RT_FAILURE(rc))
3720 {
3721 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3722 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3723 {
3724 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3725 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3726 }
3727 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3728 {
3729 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3730 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", Cmd.n.u4Opcode));
3731 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3732 }
3733 break;
3734 }
3735 }
3736 else
3737 {
3738 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmd, rc));
3739 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3740 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3741 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3742 break;
3743 }
3744 }
3745 }
3746
3747 IOMMU_UNLOCK(pDevIns);
3748 }
3749
3750 LogFlowFunc(("Command thread terminating\n"));
3751 return VINF_SUCCESS;
3752}
3753
3754
3755/**
3756 * Wakes up the command thread so it can respond to a state change.
3757 *
3758 * @returns VBox status code.
3759 * @param pDevIns The IOMMU device instance.
3760 * @param pThread The command thread.
3761 */
3762static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3763{
3764 RT_NOREF(pThread);
3765 LogFlowFunc(("\n"));
3766 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3767 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3768}
3769
3770
3771/**
3772 * @callback_method_impl{FNPCICONFIGREAD}
3773 */
3774static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3775 unsigned cb, uint32_t *pu32Value)
3776{
3777 /** @todo IOMMU: PCI config read stat counter. */
3778 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3779 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3780 return rcStrict;
3781}
3782
3783
3784/**
3785 * @callback_method_impl{FNPCICONFIGWRITE}
3786 */
3787static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3788 unsigned cb, uint32_t u32Value)
3789{
3790 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3791
3792 /*
3793 * Discard writes to read-only registers that are specific to the IOMMU.
3794 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3795 * See PCI spec. 6.1. "Configuration Space Organization".
3796 */
3797 switch (uAddress)
3798 {
3799 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3800 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3801 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3802 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3803 {
3804 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3805 return VINF_SUCCESS;
3806 }
3807 }
3808
3809 IOMMU_LOCK(pDevIns);
3810
3811 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3812 switch (uAddress)
3813 {
3814 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3815 {
3816 if (pThis->IommuBar.n.u1Enable)
3817 {
3818 rcStrict = VINF_SUCCESS;
3819 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3820 break;
3821 }
3822
3823 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3824 if (pThis->IommuBar.n.u1Enable)
3825 {
3826 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3827 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3828 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3829 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
3830
3831 /* If the MMIO region is already mapped at the specified address, we're done. */
3832 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
3833 if (GCPhysMmioBasePrev == GCPhysMmioBase)
3834 {
3835 rcStrict = VINF_SUCCESS;
3836 break;
3837 }
3838
3839 /* Unmap the previous MMIO region (which is at a different address). */
3840 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
3841 {
3842 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
3843 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3844 if (RT_FAILURE(rcStrict))
3845 {
3846 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3847 break;
3848 }
3849 }
3850
3851 /* Map the newly specified MMIO region. */
3852 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
3853 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3854 if (RT_FAILURE(rcStrict))
3855 {
3856 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3857 break;
3858 }
3859 }
3860 else
3861 rcStrict = VINF_SUCCESS;
3862 break;
3863 }
3864
3865 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3866 {
3867 if (!pThis->IommuBar.n.u1Enable)
3868 pThis->IommuBar.au32[1] = u32Value;
3869 else
3870 {
3871 rcStrict = VINF_SUCCESS;
3872 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3873 }
3874 break;
3875 }
3876
3877 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3878 {
3879 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3880 RT_FALL_THRU();
3881 }
3882 default:
3883 {
3884 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3885 break;
3886 }
3887 }
3888
3889 IOMMU_UNLOCK(pDevIns);
3890
3891 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
3892 return rcStrict;
3893}
3894
3895
3896/**
3897 * @callback_method_impl{FNDBGFHANDLERDEV}
3898 */
3899static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3900{
3901 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3902 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3903 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3904
3905 bool fVerbose;
3906 if ( pszArgs
3907 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3908 fVerbose = true;
3909 else
3910 fVerbose = false;
3911
3912 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3913 /* Device Table Base Addresses (all segments). */
3914 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3915 {
3916 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3917 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3918 if (fVerbose)
3919 {
3920 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3921 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
3922 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3923 }
3924 }
3925 /* Command Buffer Base Address Register. */
3926 {
3927 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3928 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3929 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3930 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3931 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
3932 if (fVerbose)
3933 {
3934 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3935 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3936 cEntries, cbBuffer);
3937 }
3938 }
3939 /* Event Log Base Address Register. */
3940 {
3941 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3942 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3943 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3944 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3945 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
3946 if (fVerbose)
3947 {
3948 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3949 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3950 cEntries, cbBuffer);
3951 }
3952 }
3953 /* IOMMU Control Register. */
3954 {
3955 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3956 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3957 if (fVerbose)
3958 {
3959 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3960 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3961 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3962 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3963 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3964 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3965 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3966 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3967 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3968 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3969 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3970 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3971 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3972 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3973 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3974 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3975 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3976 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3977 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3978 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3979 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3980 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3981 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3982 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3983 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3984 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3985 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3986 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3987 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3988 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3989 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3990 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3991 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3992 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3993 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3994 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3995 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3996 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3997 }
3998 }
3999 /* Exclusion Base Address Register. */
4000 {
4001 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
4002 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
4003 if (fVerbose)
4004 {
4005 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
4006 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
4007 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
4008 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
4009 }
4010 }
4011 /* Exclusion Range Limit Register. */
4012 {
4013 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
4014 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
4015 if (fVerbose)
4016 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
4017 }
4018 /* Extended Feature Register. */
4019 {
4020 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
4021 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
4022 if (fVerbose)
4023 {
4024 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
4025 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
4026 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
4027 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
4028 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
4029 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
4030 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
4031 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
4032 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
4033 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
4034 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
4035 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
4036 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
4037 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
4038 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
4039 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
4040 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
4041 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
4042 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
4043 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
4044 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
4045 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
4046 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
4047 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
4048 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
4049 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
4050 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
4051 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
4052 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
4053 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
4054 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
4055 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
4056 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
4057 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
4058 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
4059 }
4060 }
4061 /* PPR Log Base Address Register. */
4062 {
4063 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
4064 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
4065 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4066 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4067 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
4068 if (fVerbose)
4069 {
4070 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4071 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4072 cEntries, cbBuffer);
4073 }
4074 }
4075 /* Hardware Event (Hi) Register. */
4076 {
4077 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4078 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4079 if (fVerbose)
4080 {
4081 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4082 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4083 }
4084 }
4085 /* Hardware Event (Lo) Register. */
4086 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4087 /* Hardware Event Status. */
4088 {
4089 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4090 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4091 if (fVerbose)
4092 {
4093 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4094 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4095 }
4096 }
4097 /* Guest Virtual-APIC Log Base Address Register. */
4098 {
4099 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4100 uint8_t const uEncodedLen = GALogBar.n.u4Len;
4101 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4102 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4103 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4104 if (fVerbose)
4105 {
4106 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4107 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4108 cEntries, cbBuffer);
4109 }
4110 }
4111 /* Guest Virtual-APIC Log Tail Address Register. */
4112 {
4113 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4114 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4115 if (fVerbose)
4116 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4117 }
4118 /* PPR Log B Base Address Register. */
4119 {
4120 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4121 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4122 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4123 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4124 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4125 if (fVerbose)
4126 {
4127 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4128 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4129 cEntries, cbBuffer);
4130 }
4131 }
4132 /* Event Log B Base Address Register. */
4133 {
4134 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4135 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4136 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4137 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4138 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4139 if (fVerbose)
4140 {
4141 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4142 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4143 cEntries, cbBuffer);
4144 }
4145 }
4146 /* Device-Specific Feature Extension Register. */
4147 {
4148 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4149 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4150 if (fVerbose)
4151 {
4152 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4153 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4154 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4155 }
4156 }
4157 /* Device-Specific Control Extension Register. */
4158 {
4159 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4160 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4161 if (fVerbose)
4162 {
4163 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4164 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4165 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4166 }
4167 }
4168 /* Device-Specific Status Extension Register. */
4169 {
4170 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4171 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
4172 if (fVerbose)
4173 {
4174 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4175 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4176 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4177 }
4178 }
4179 /* Miscellaneous Information Register (Lo and Hi). */
4180 {
4181 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
4182 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
4183 if (fVerbose)
4184 {
4185 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
4186 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
4187 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
4188 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
4189 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
4190 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
4191 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
4192 }
4193 }
4194 /* MSI Capability Header. */
4195 {
4196 MSI_CAP_HDR_T MsiCapHdr;
4197 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4198 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4199 if (fVerbose)
4200 {
4201 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4202 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4203 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4204 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4205 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4206 }
4207 }
4208 /* MSI Address Register (Lo and Hi). */
4209 {
4210 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4211 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4212 MSIADDR MsiAddr;
4213 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4214 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4215 if (fVerbose)
4216 {
4217 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
4218 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
4219 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
4220 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
4221 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
4222 }
4223 }
4224 /* MSI Data. */
4225 {
4226 MSIDATA MsiData;
4227 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4228 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4229 if (fVerbose)
4230 {
4231 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
4232 MsiData.n.u8Vector);
4233 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
4234 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
4235 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4236 "level" : "edge");
4237 }
4238 }
4239 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4240 {
4241 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4242 MsiMapCapHdr.u32 = 0;
4243 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4244 if (fVerbose)
4245 {
4246 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4247 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4248 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4249 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4250 }
4251 }
4252 /* Performance Optimization Control Register. */
4253 {
4254 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4255 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4256 if (fVerbose)
4257 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4258 }
4259 /* XT (x2APIC) General Interrupt Control Register. */
4260 {
4261 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4262 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4263 if (fVerbose)
4264 {
4265 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4266 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4267 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4268 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4269 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4270 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4271 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4272 }
4273 }
4274 /* XT (x2APIC) PPR Interrupt Control Register. */
4275 {
4276 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4277 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4278 if (fVerbose)
4279 {
4280 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4281 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4282 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4283 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4284 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4285 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4286 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4287 }
4288 }
4289 /* XT (X2APIC) GA Log Interrupt Control Register. */
4290 {
4291 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4292 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4293 if (fVerbose)
4294 {
4295 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4296 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4297 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4298 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4299 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4300 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4301 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4302 }
4303 }
4304 /* MARC Registers. */
4305 {
4306 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4307 {
4308 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4309 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4310 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4311
4312 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4313 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4314 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4315 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4316
4317 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4318 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4319 }
4320 }
4321 /* Reserved Register. */
4322 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4323 /* Command Buffer Head Pointer Register. */
4324 {
4325 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4326 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4327 CmdBufHeadPtr.n.off);
4328 }
4329 /* Command Buffer Tail Pointer Register. */
4330 {
4331 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4332 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4333 CmdBufTailPtr.n.off);
4334 }
4335 /* Event Log Head Pointer Register. */
4336 {
4337 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4338 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4339 EvtLogHeadPtr.n.off);
4340 }
4341 /* Event Log Tail Pointer Register. */
4342 {
4343 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4344 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4345 EvtLogTailPtr.n.off);
4346 }
4347 /* Status Register. */
4348 {
4349 IOMMU_STATUS_T const Status = pThis->Status;
4350 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4351 if (fVerbose)
4352 {
4353 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4354 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4355 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4356 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4357 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4358 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4359 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4360 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4361 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4362 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4363 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4364 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4365 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4366 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4367 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4368 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4369 }
4370 }
4371 /* PPR Log Head Pointer. */
4372 {
4373 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4374 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4375 PprLogHeadPtr.n.off);
4376 }
4377 /* PPR Log Tail Pointer. */
4378 {
4379 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4380 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4381 PprLogTailPtr.n.off);
4382 }
4383 /* Guest Virtual-APIC Log Head Pointer. */
4384 {
4385 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4386 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4387 GALogHeadPtr.n.u12GALogPtr);
4388 }
4389 /* Guest Virtual-APIC Log Tail Pointer. */
4390 {
4391 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4392 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4393 GALogTailPtr.n.u12GALogPtr);
4394 }
4395 /* PPR Log B Head Pointer. */
4396 {
4397 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4398 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4399 PprLogBHeadPtr.n.off);
4400 }
4401 /* PPR Log B Tail Pointer. */
4402 {
4403 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4404 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4405 PprLogBTailPtr.n.off);
4406 }
4407 /* Event Log B Head Pointer. */
4408 {
4409 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4410 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4411 EvtLogBHeadPtr.n.off);
4412 }
4413 /* Event Log B Tail Pointer. */
4414 {
4415 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4416 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4417 EvtLogBTailPtr.n.off);
4418 }
4419 /* PPR Log Auto Response Register. */
4420 {
4421 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4422 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4423 if (fVerbose)
4424 {
4425 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4426 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4427 }
4428 }
4429 /* PPR Log Overflow Early Warning Indicator Register. */
4430 {
4431 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4432 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4433 if (fVerbose)
4434 {
4435 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4436 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4437 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4438 }
4439 }
4440 /* PPR Log Overflow Early Warning Indicator Register. */
4441 {
4442 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4443 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4444 if (fVerbose)
4445 {
4446 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4447 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4448 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4449 }
4450 }
4451}
4452
4453
4454/**
4455 * Dumps the DTE via the info callback helper.
4456 *
4457 * @param pHlp The info helper.
4458 * @param pDte The device table entry.
4459 * @param pszPrefix The string prefix.
4460 */
4461static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4462{
4463 AssertReturnVoid(pHlp);
4464 AssertReturnVoid(pDte);
4465 AssertReturnVoid(pszPrefix);
4466
4467 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4468 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4469 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4470 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4471 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4472 pDte->n.u40PageTableRootPtrLo << 12);
4473 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4474 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4475 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4476 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4477 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4478 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4479 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4480 (pDte->n.u21GstCr3TableRootPtrHi << 31)
4481 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
4482 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
4483 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4484 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4485 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4486 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4487 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4488 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4489 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4490 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4491 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4492 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4493 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4494 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4495 pHlp->pfnPrintf(pHlp, "\n");
4496
4497 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4498 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4499 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4500 {
4501 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4502 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4503 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4504 cbIntrTable);
4505 }
4506 else
4507 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4508 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4509 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4510 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4511 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4512 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4513 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4514 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4515 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4516 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4517 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4518 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4519 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4520 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4521 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4522 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4523 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4524}
4525
4526
4527/**
4528 * @callback_method_impl{FNDBGFHANDLERDEV}
4529 */
4530static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4531{
4532 if (pszArgs)
4533 {
4534 uint16_t uDevId = 0;
4535 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4536 if (RT_SUCCESS(rc))
4537 {
4538 DTE_T Dte;
4539 rc = iommuAmdReadDte(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4540 if (RT_SUCCESS(rc))
4541 {
4542 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4543 return;
4544 }
4545
4546 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4547 }
4548 else
4549 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4550 }
4551 else
4552 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4553}
4554
4555
4556#if 0
4557/**
4558 * @callback_method_impl{FNDBGFHANDLERDEV}
4559 */
4560static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4561{
4562 RT_NOREF(pszArgs);
4563
4564 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4565 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4566 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4567
4568 uint8_t cTables = 0;
4569 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4570 {
4571 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4572 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4573 if (GCPhysDevTab)
4574 ++cTables;
4575 }
4576
4577 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4578 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4579 if (!cTables)
4580 return;
4581
4582 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4583 {
4584 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4585 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4586 if (GCPhysDevTab)
4587 {
4588 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4589 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4590 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4591
4592 void *pvDevTab = RTMemAllocZ(cbDevTab);
4593 if (RT_LIKELY(pvDevTab))
4594 {
4595 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4596 if (RT_SUCCESS(rc))
4597 {
4598 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4599 {
4600 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
4601 if ( pDte->n.u1Valid
4602 || pDte->n.u1IntrMapValid)
4603 {
4604 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4605 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4606 }
4607 }
4608 pHlp->pfnPrintf(pHlp, "\n");
4609 }
4610 else
4611 {
4612 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4613 cbDevTab, rc);
4614 }
4615
4616 RTMemFree(pvDevTab);
4617 }
4618 else
4619 {
4620 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4621 return;
4622 }
4623 }
4624 }
4625}
4626#endif
4627
4628/**
4629 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4630 */
4631static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4632{
4633 /** @todo IOMMU: Save state. */
4634 RT_NOREF2(pDevIns, pSSM);
4635 LogFlowFunc(("\n"));
4636 return VERR_NOT_IMPLEMENTED;
4637}
4638
4639
4640/**
4641 * @callback_method_impl{FNSSMDEVLOADEXEC}
4642 */
4643static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4644{
4645 /** @todo IOMMU: Load state. */
4646 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4647 LogFlowFunc(("\n"));
4648 return VERR_NOT_IMPLEMENTED;
4649}
4650
4651
4652/**
4653 * @interface_method_impl{PDMDEVREG,pfnReset}
4654 */
4655static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4656{
4657 /*
4658 * Resets read-write portion of the IOMMU state.
4659 *
4660 * State data not initialized here is expected to be initialized during
4661 * device construction and remain read-only through the lifetime of the VM.
4662 */
4663 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4664 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4665 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4666
4667 IOMMU_LOCK_NORET(pDevIns);
4668
4669 LogFlowFunc(("\n"));
4670
4671 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4672
4673 pThis->CmdBufBaseAddr.u64 = 0;
4674 pThis->CmdBufBaseAddr.n.u4Len = 8;
4675
4676 pThis->EvtLogBaseAddr.u64 = 0;
4677 pThis->EvtLogBaseAddr.n.u4Len = 8;
4678
4679 pThis->Ctrl.u64 = 0;
4680 pThis->Ctrl.n.u1Coherent = 1;
4681 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4682
4683 pThis->ExclRangeBaseAddr.u64 = 0;
4684 pThis->ExclRangeLimit.u64 = 0;
4685
4686 pThis->PprLogBaseAddr.u64 = 0;
4687 pThis->PprLogBaseAddr.n.u4Len = 8;
4688
4689 pThis->HwEvtHi.u64 = 0;
4690 pThis->HwEvtLo = 0;
4691 pThis->HwEvtStatus.u64 = 0;
4692
4693 pThis->GALogBaseAddr.u64 = 0;
4694 pThis->GALogBaseAddr.n.u4Len = 8;
4695 pThis->GALogTailAddr.u64 = 0;
4696
4697 pThis->PprLogBBaseAddr.u64 = 0;
4698 pThis->PprLogBBaseAddr.n.u4Len = 8;
4699
4700 pThis->EvtLogBBaseAddr.u64 = 0;
4701 pThis->EvtLogBBaseAddr.n.u4Len = 8;
4702
4703 pThis->PerfOptCtrl.u32 = 0;
4704
4705 pThis->XtGenIntrCtrl.u64 = 0;
4706 pThis->XtPprIntrCtrl.u64 = 0;
4707 pThis->XtGALogIntrCtrl.u64 = 0;
4708
4709 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4710
4711 pThis->CmdBufHeadPtr.u64 = 0;
4712 pThis->CmdBufTailPtr.u64 = 0;
4713 pThis->EvtLogHeadPtr.u64 = 0;
4714 pThis->EvtLogTailPtr.u64 = 0;
4715
4716 pThis->Status.u64 = 0;
4717
4718 pThis->PprLogHeadPtr.u64 = 0;
4719 pThis->PprLogTailPtr.u64 = 0;
4720
4721 pThis->GALogHeadPtr.u64 = 0;
4722 pThis->GALogTailPtr.u64 = 0;
4723
4724 pThis->PprLogBHeadPtr.u64 = 0;
4725 pThis->PprLogBTailPtr.u64 = 0;
4726
4727 pThis->EvtLogBHeadPtr.u64 = 0;
4728 pThis->EvtLogBTailPtr.u64 = 0;
4729
4730 pThis->PprLogAutoResp.u64 = 0;
4731 pThis->PprLogOverflowEarly.u64 = 0;
4732 pThis->PprLogBOverflowEarly.u64 = 0;
4733
4734 pThis->IommuBar.u64 = 0;
4735 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4736 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4737
4738 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4739
4740 IOMMU_UNLOCK(pDevIns);
4741}
4742
4743
4744/**
4745 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4746 */
4747static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4748{
4749 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4750 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4751 LogFlowFunc(("\n"));
4752
4753 /* Close the command thread semaphore. */
4754 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4755 {
4756 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4757 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4758 }
4759 return VINF_SUCCESS;
4760}
4761
4762
4763/**
4764 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4765 */
4766static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4767{
4768 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4769 RT_NOREF(pCfg);
4770
4771 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4772 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4773 pThisCC->pDevInsR3 = pDevIns;
4774
4775 LogFlowFunc(("iInstance=%d\n", iInstance));
4776
4777 /*
4778 * Register the IOMMU with PDM.
4779 */
4780 PDMIOMMUREGR3 IommuReg;
4781 RT_ZERO(IommuReg);
4782 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4783 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
4784 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
4785 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4786 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4787 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4788 if (RT_FAILURE(rc))
4789 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4790 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4791 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4792 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4793 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4794 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4795 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4796 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4797 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4798
4799 /*
4800 * Initialize read-only PCI configuration space.
4801 */
4802 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4803 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4804
4805 /* Header. */
4806 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4807 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4808 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
4809 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4810 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4811 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4812 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4813 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4814 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4815 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4816 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4817 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4818 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4819 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4820
4821 /* Capability Header. */
4822 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4823 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4824 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4825 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Offset to next capability */
4826 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4827 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4828 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4829 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4830 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4831 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4832 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4833
4834 /* Base Address Register. */
4835 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4836 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4837
4838 /* IOMMU Range Register. */
4839 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4840
4841 /* Misc. Information Register. */
4842 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4843 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4844 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4845 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4846 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4847 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4848 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4849 uint32_t const uMiscInfoReg1 = 0;
4850 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4851 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4852
4853 /* MSI Capability Header register. */
4854 PDMMSIREG MsiReg;
4855 RT_ZERO(MsiReg);
4856 MsiReg.cMsiVectors = 1;
4857 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4858 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4859 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4860
4861 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4862#if 0
4863 /* MSI Address Lo. */
4864 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4865 /* MSI Address Hi. */
4866 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4867 /* MSI Data. */
4868 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4869#endif
4870
4871#if 0
4872 /** @todo IOMMU: I don't know if we need to support this, enable later if
4873 * required. */
4874 /* MSI Mapping Capability Header register. */
4875 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4876 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4877 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4878 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4879 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4880 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4881 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4882#endif
4883
4884 /*
4885 * Register the PCI function with PDM.
4886 */
4887 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4888 AssertLogRelRCReturn(rc, rc);
4889
4890 /*
4891 * Register MSI support for the PCI device.
4892 * This must be done -after- register it as a PCI device!
4893 */
4894 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4895 AssertRCReturn(rc, rc);
4896
4897 /*
4898 * Intercept PCI config. space accesses.
4899 */
4900 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4901 AssertLogRelRCReturn(rc, rc);
4902
4903 /*
4904 * Create the MMIO region.
4905 * Mapping of the region is done when software configures it via PCI config space.
4906 */
4907 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4908 NULL /* pvUser */,
4909 IOMMMIO_FLAGS_READ_DWORD_QWORD
4910 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
4911 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
4912 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
4913 "AMD-IOMMU", &pThis->hMmio);
4914 AssertLogRelRCReturn(rc, rc);
4915
4916 /*
4917 * Register saved state.
4918 */
4919 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4920 NULL, NULL, NULL,
4921 NULL, iommuAmdR3SaveExec, NULL,
4922 NULL, iommuAmdR3LoadExec, NULL);
4923 AssertLogRelRCReturn(rc, rc);
4924
4925 /*
4926 * Register debugger info items.
4927 */
4928 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
4929 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
4930#if 0
4931 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
4932#endif
4933
4934# ifdef VBOX_WITH_STATISTICS
4935 /*
4936 * Statistics.
4937 */
4938 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4939 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4940
4941 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4942 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4943
4944 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
4945 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
4946
4947 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4948 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4949
4950 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4951 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4952
4953 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
4954 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
4955 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
4956 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
4957 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
4958 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
4959 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
4960 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
4961 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
4962# endif
4963
4964 /*
4965 * Create the command thread and its event semaphore.
4966 */
4967 char szDevIommu[64];
4968 RT_ZERO(szDevIommu);
4969 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
4970 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
4971 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
4972 AssertLogRelRCReturn(rc, rc);
4973
4974 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
4975 AssertLogRelRCReturn(rc, rc);
4976
4977 /*
4978 * Initialize read-only registers.
4979 * NOTE! Fields here must match their corresponding field in the ACPI tables.
4980 */
4981 /** @todo Don't remove the =0 assignment for now. It's just there so it's easier
4982 * for me to see existing features that we might want to implement. Do it
4983 * later. */
4984 pThis->ExtFeat.u64 = 0;
4985 pThis->ExtFeat.n.u1PrefetchSup = 0;
4986 pThis->ExtFeat.n.u1PprSup = 0;
4987 pThis->ExtFeat.n.u1X2ApicSup = 0;
4988 pThis->ExtFeat.n.u1NoExecuteSup = 0;
4989 pThis->ExtFeat.n.u1GstTranslateSup = 0;
4990 pThis->ExtFeat.n.u1InvAllSup = 1;
4991 pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4992 pThis->ExtFeat.n.u1HwErrorSup = 1;
4993 pThis->ExtFeat.n.u1PerfCounterSup = 0;
4994 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4995 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4996 pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
4997 pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
4998 pThis->ExtFeat.n.u2SmiFilterSup = 0;
4999 pThis->ExtFeat.n.u3SmiFilterCount = 0;
5000 pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5001 pThis->ExtFeat.n.u2DualPprLogSup = 0;
5002 pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5003 pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
5004 pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5005 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5006 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5007 pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5008 pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5009 pThis->ExtFeat.n.u2MarcSup = 0;
5010 pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5011 pThis->ExtFeat.n.u1PerfOptSup = 0;
5012 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5013 pThis->ExtFeat.n.u1GstIoSup = 0;
5014 pThis->ExtFeat.n.u1HostAccessSup = 0;
5015 pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5016 pThis->ExtFeat.n.u1AttrForwardSup = 0;
5017 pThis->ExtFeat.n.u1HostDirtySup = 0;
5018 pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5019 pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5020 pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5021
5022 pThis->RsvdReg = 0;
5023
5024 pThis->DevSpecificFeat.u64 = 0;
5025 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
5026 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
5027
5028 pThis->DevSpecificCtrl.u64 = 0;
5029 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
5030 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
5031
5032 pThis->DevSpecificStatus.u64 = 0;
5033 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
5034 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
5035
5036 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
5037
5038 /*
5039 * Initialize parts of the IOMMU state as it would during reset.
5040 * Must be called -after- initializing PCI config. space registers.
5041 */
5042 iommuAmdR3Reset(pDevIns);
5043
5044 return VINF_SUCCESS;
5045}
5046
5047# else /* !IN_RING3 */
5048
5049/**
5050 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5051 */
5052static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5053{
5054 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5055 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5056 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5057
5058 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5059
5060 /* Set up the MMIO RZ handlers. */
5061 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5062 AssertRCReturn(rc, rc);
5063
5064 /* Set up the IOMMU RZ callbacks. */
5065 PDMIOMMUREGCC IommuReg;
5066 RT_ZERO(IommuReg);
5067 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5068 IommuReg.idxIommu = pThis->idxIommu;
5069 IommuReg.pfnMemRead = iommuAmdDeviceMemRead;
5070 IommuReg.pfnMemWrite = iommuAmdDeviceMemWrite;
5071 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5072 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5073 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5074 AssertRCReturn(rc, rc);
5075
5076 return VINF_SUCCESS;
5077}
5078
5079# endif /* !IN_RING3 */
5080
5081/**
5082 * The device registration structure.
5083 */
5084const PDMDEVREG g_DeviceIommuAmd =
5085{
5086 /* .u32Version = */ PDM_DEVREG_VERSION,
5087 /* .uReserved0 = */ 0,
5088 /* .szName = */ "iommu-amd",
5089 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
5090 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
5091 /* .cMaxInstances = */ ~0U,
5092 /* .uSharedVersion = */ 42,
5093 /* .cbInstanceShared = */ sizeof(IOMMU),
5094 /* .cbInstanceCC = */ sizeof(IOMMUCC),
5095 /* .cbInstanceRC = */ sizeof(IOMMURC),
5096 /* .cMaxPciDevices = */ 1,
5097 /* .cMaxMsixVectors = */ 0,
5098 /* .pszDescription = */ "IOMMU (AMD)",
5099#if defined(IN_RING3)
5100 /* .pszRCMod = */ "VBoxDDRC.rc",
5101 /* .pszR0Mod = */ "VBoxDDR0.r0",
5102 /* .pfnConstruct = */ iommuAmdR3Construct,
5103 /* .pfnDestruct = */ iommuAmdR3Destruct,
5104 /* .pfnRelocate = */ NULL,
5105 /* .pfnMemSetup = */ NULL,
5106 /* .pfnPowerOn = */ NULL,
5107 /* .pfnReset = */ iommuAmdR3Reset,
5108 /* .pfnSuspend = */ NULL,
5109 /* .pfnResume = */ NULL,
5110 /* .pfnAttach = */ NULL,
5111 /* .pfnDetach = */ NULL,
5112 /* .pfnQueryInterface = */ NULL,
5113 /* .pfnInitComplete = */ NULL,
5114 /* .pfnPowerOff = */ NULL,
5115 /* .pfnSoftReset = */ NULL,
5116 /* .pfnReserved0 = */ NULL,
5117 /* .pfnReserved1 = */ NULL,
5118 /* .pfnReserved2 = */ NULL,
5119 /* .pfnReserved3 = */ NULL,
5120 /* .pfnReserved4 = */ NULL,
5121 /* .pfnReserved5 = */ NULL,
5122 /* .pfnReserved6 = */ NULL,
5123 /* .pfnReserved7 = */ NULL,
5124#elif defined(IN_RING0)
5125 /* .pfnEarlyConstruct = */ NULL,
5126 /* .pfnConstruct = */ iommuAmdRZConstruct,
5127 /* .pfnDestruct = */ NULL,
5128 /* .pfnFinalDestruct = */ NULL,
5129 /* .pfnRequest = */ NULL,
5130 /* .pfnReserved0 = */ NULL,
5131 /* .pfnReserved1 = */ NULL,
5132 /* .pfnReserved2 = */ NULL,
5133 /* .pfnReserved3 = */ NULL,
5134 /* .pfnReserved4 = */ NULL,
5135 /* .pfnReserved5 = */ NULL,
5136 /* .pfnReserved6 = */ NULL,
5137 /* .pfnReserved7 = */ NULL,
5138#elif defined(IN_RC)
5139 /* .pfnConstruct = */ iommuAmdRZConstruct,
5140 /* .pfnReserved0 = */ NULL,
5141 /* .pfnReserved1 = */ NULL,
5142 /* .pfnReserved2 = */ NULL,
5143 /* .pfnReserved3 = */ NULL,
5144 /* .pfnReserved4 = */ NULL,
5145 /* .pfnReserved5 = */ NULL,
5146 /* .pfnReserved6 = */ NULL,
5147 /* .pfnReserved7 = */ NULL,
5148#else
5149# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5150#endif
5151 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
5152};
5153
5154#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5155
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