VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86732

Last change on this file since 86732 was 86732, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Comment typos.
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1/* $Id: DevIommuAmd.cpp 86732 2020-10-28 11:26:09Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31
32#include "VBoxDD.h"
33#include "DevIommuAmd.h"
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** Release log prefix string. */
40#define IOMMU_LOG_PFX "AMD-IOMMU"
41/** The current saved state version. */
42#define IOMMU_SAVED_STATE_VERSION 1
43/** The IOTLB entry magic. */
44#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46#ifndef DEBUG_ramshankar
47/** Temporary, make permanent later (get rid of define entirely and remove old
48 * code). This allow ssub-qword accesses to qword registers. Write accesses
49 * seems to work (needs testing one sub-path of the code), Read accesses not yet
50 * converted. */
51# define IOMMU_NEW_REGISTER_ACCESS
52#endif
53
54
55/*********************************************************************************************************************************
56* Structures and Typedefs *
57*********************************************************************************************************************************/
58/**
59 * Acquires the IOMMU PDM lock.
60 * This will make a long jump to ring-3 to acquire the lock if necessary.
61 */
62#define IOMMU_LOCK(a_pDevIns) \
63 do { \
64 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
65 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
66 { /* likely */ } \
67 else \
68 return rcLock; \
69 } while (0)
70
71/**
72 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
73 * This will make a long jump to ring-3 to acquire the lock if necessary.
74 */
75#define IOMMU_LOCK_NORET(a_pDevIns) \
76 do { \
77 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
78 AssertRC(rcLock); \
79 } while (0)
80
81/**
82 * Releases the IOMMU PDM lock.
83 */
84#define IOMMU_UNLOCK(a_pDevIns) \
85 do { \
86 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
87 } while (0)
88
89/**
90 * Asserts that the critsect is owned by this thread.
91 */
92#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
93 do { \
94 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95 } while (0)
96
97/**
98 * Asserts that the critsect is not owned by this thread.
99 */
100#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
101 do { \
102 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
103 } while (0)
104
105/**
106 * IOMMU operations (transaction) types.
107 */
108typedef enum IOMMUOP
109{
110 /** Address translation request. */
111 IOMMUOP_TRANSLATE_REQ = 0,
112 /** Memory read request. */
113 IOMMUOP_MEM_READ,
114 /** Memory write request. */
115 IOMMUOP_MEM_WRITE,
116 /** Interrupt request. */
117 IOMMUOP_INTR_REQ,
118 /** Command. */
119 IOMMUOP_CMD
120} IOMMUOP;
121AssertCompileSize(IOMMUOP, 4);
122
123/**
124 * I/O page walk result.
125 */
126typedef struct
127{
128 /** The translated system physical address. */
129 RTGCPHYS GCPhysSpa;
130 /** The number of offset bits in the system physical address. */
131 uint8_t cShift;
132 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
133 uint8_t fIoPerm;
134 /** Padding. */
135 uint8_t abPadding[2];
136} IOWALKRESULT;
137/** Pointer to an I/O walk result struct. */
138typedef IOWALKRESULT *PIOWALKRESULT;
139/** Pointer to a const I/O walk result struct. */
140typedef IOWALKRESULT *PCIOWALKRESULT;
141
142/**
143 * IOMMU I/O TLB Entry.
144 * Keep this as small and aligned as possible.
145 */
146typedef struct
147{
148 /** The translated system physical address (SPA) of the page. */
149 RTGCPHYS GCPhysSpa;
150 /** The index of the 4K page within a large page. */
151 uint32_t idxSubPage;
152 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
153 uint8_t fIoPerm;
154 /** The number of offset bits in the translation indicating page size. */
155 uint8_t cShift;
156 /** Alignment padding. */
157 uint8_t afPadding[2];
158} IOTLBE_T;
159AssertCompileSize(IOTLBE_T, 16);
160/** Pointer to an IOMMU I/O TLB entry struct. */
161typedef IOTLBE_T *PIOTLBE_T;
162/** Pointer to a const IOMMU I/O TLB entry struct. */
163typedef IOTLBE_T const *PCIOTLBE_T;
164
165/**
166 * The shared IOMMU device state.
167 */
168typedef struct IOMMU
169{
170 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
171 uint32_t idxIommu;
172 /** Alignment padding. */
173 uint32_t uPadding0;
174
175 /** Whether the command thread is sleeping. */
176 bool volatile fCmdThreadSleeping;
177 /** Alignment padding. */
178 uint8_t afPadding0[3];
179 /** Whether the command thread has been signaled for wake up. */
180 bool volatile fCmdThreadSignaled;
181 /** Alignment padding. */
182 uint8_t afPadding1[3];
183
184 /** The event semaphore the command thread waits on. */
185 SUPSEMEVENT hEvtCmdThread;
186 /** The MMIO handle. */
187 IOMMMIOHANDLE hMmio;
188
189 /** @name PCI: Base capability block registers.
190 * @{ */
191 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
192 /** @} */
193
194 /** @name MMIO: Control and status registers.
195 * @{ */
196 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
197 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
198 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
199 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
200 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
201 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
202 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
203 /** @} */
204
205 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
206 * @{ */
207 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
208 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
209 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
210 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
211 /** @} */
212
213 /** @todo IOMMU: SMI filter. */
214
215 /** @name MMIO: Guest Virtual-APIC Log registers.
216 * @{ */
217 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
218 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
219 /** @} */
220
221 /** @name MMIO: Alternate PPR and Event Log registers.
222 * @{ */
223 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
224 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
225 /** @} */
226
227 /** @name MMIO: Device-specific feature registers.
228 * @{ */
229 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
230 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
231 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
232 /** @} */
233
234 /** @name MMIO: MSI Capability Block registers.
235 * @{ */
236 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
237 /** @} */
238
239 /** @name MMIO: Performance Optimization Control registers.
240 * @{ */
241 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
242 /** @} */
243
244 /** @name MMIO: x2APIC Control registers.
245 * @{ */
246 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
247 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
248 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
249 /** @} */
250
251 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
252 * @{ */
253 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
254 /** @} */
255
256 /** @name MMIO: Reserved register.
257 * @{ */
258 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
259 /** @} */
260
261 /** @name MMIO: Command and Event Log pointer registers.
262 * @{ */
263 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
264 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
265 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
266 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
267 /** @} */
268
269 /** @name MMIO: Command and Event Status register.
270 * @{ */
271 IOMMU_STATUS_T Status; /**< IOMMU status register. */
272 /** @} */
273
274 /** @name MMIO: PPR Log Head and Tail pointer registers.
275 * @{ */
276 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
277 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
278 /** @} */
279
280 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
281 * @{ */
282 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
283 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
284 /** @} */
285
286 /** @name MMIO: PPR Log B Head and Tail pointer registers.
287 * @{ */
288 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
289 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
290 /** @} */
291
292 /** @name MMIO: Event Log B Head and Tail pointer registers.
293 * @{ */
294 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
295 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
296 /** @} */
297
298 /** @name MMIO: PPR Log Overflow protection registers.
299 * @{ */
300 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
301 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
302 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
303 /** @} */
304
305 /** @todo IOMMU: IOMMU Event counter registers. */
306
307#ifdef VBOX_WITH_STATISTICS
308 /** @name IOMMU: Stat counters.
309 * @{ */
310 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
311 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
312 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
313 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
314
315 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
316 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
317
318 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
319 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
320 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
321 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
322
323 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
324 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
325 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
326 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
327
328 STAMCOUNTER StatCmd; /**< Number of commands processed. */
329 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
330 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
331 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
332 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
333 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
334 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
335 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
336 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
337 /** @} */
338#endif
339} IOMMU;
340/** Pointer to the IOMMU device state. */
341typedef struct IOMMU *PIOMMU;
342/** Pointer to the const IOMMU device state. */
343typedef const struct IOMMU *PCIOMMU;
344AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
345AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
346AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
347AssertCompileMemberAlignment(IOMMU, hMmio, 8);
348AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
349
350/**
351 * The ring-3 IOMMU device state.
352 */
353typedef struct IOMMUR3
354{
355 /** Device instance. */
356 PPDMDEVINSR3 pDevInsR3;
357 /** The IOMMU helpers. */
358 PCPDMIOMMUHLPR3 pIommuHlpR3;
359 /** The command thread handle. */
360 R3PTRTYPE(PPDMTHREAD) pCmdThread;
361} IOMMUR3;
362/** Pointer to the ring-3 IOMMU device state. */
363typedef IOMMUR3 *PIOMMUR3;
364
365/**
366 * The ring-0 IOMMU device state.
367 */
368typedef struct IOMMUR0
369{
370 /** Device instance. */
371 PPDMDEVINSR0 pDevInsR0;
372 /** The IOMMU helpers. */
373 PCPDMIOMMUHLPR0 pIommuHlpR0;
374} IOMMUR0;
375/** Pointer to the ring-0 IOMMU device state. */
376typedef IOMMUR0 *PIOMMUR0;
377
378/**
379 * The raw-mode IOMMU device state.
380 */
381typedef struct IOMMURC
382{
383 /** Device instance. */
384 PPDMDEVINSR0 pDevInsRC;
385 /** The IOMMU helpers. */
386 PCPDMIOMMUHLPRC pIommuHlpRC;
387} IOMMURC;
388/** Pointer to the raw-mode IOMMU device state. */
389typedef IOMMURC *PIOMMURC;
390
391/** The IOMMU device state for the current context. */
392typedef CTX_SUFF(IOMMU) IOMMUCC;
393/** Pointer to the IOMMU device state for the current context. */
394typedef CTX_SUFF(PIOMMU) PIOMMUCC;
395
396/**
397 * IOMMU register access.
398 */
399typedef struct IOMMUREGACC
400{
401 const char *pszName;
402 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
403 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
404} IOMMUREGACC;
405/** Pointer to an IOMMU register access. */
406typedef IOMMUREGACC *PIOMMUREGACC;
407/** Pointer to a const IOMMU register access. */
408typedef IOMMUREGACC const *PCIOMMUREGACC;
409
410
411/*********************************************************************************************************************************
412* Global Variables *
413*********************************************************************************************************************************/
414/**
415 * An array of the number of device table segments supported.
416 * Indexed by u2DevTabSegSup.
417 */
418static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
419
420/**
421 * An array of the masks to select the device table segment index from a device ID.
422 */
423static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
424
425/**
426 * An array of the shift values to select the device table segment index from a
427 * device ID.
428 */
429static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
430
431/**
432 * The maximum size (inclusive) of each device table segment (0 to 7).
433 * Indexed by the device table segment index.
434 */
435static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
436
437
438#ifndef VBOX_DEVICE_STRUCT_TESTCASE
439/**
440 * Gets the maximum number of buffer entries for the given buffer length.
441 *
442 * @returns Number of buffer entries.
443 * @param uEncodedLen The length (power-of-2 encoded).
444 */
445DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
446{
447 Assert(uEncodedLen > 7);
448 return 2 << (uEncodedLen - 1);
449}
450
451
452/**
453 * Gets the total length of the buffer given a base register's encoded length.
454 *
455 * @returns The length of the buffer in bytes.
456 * @param uEncodedLen The length (power-of-2 encoded).
457 */
458DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
459{
460 Assert(uEncodedLen > 7);
461 return (2 << (uEncodedLen - 1)) << 4;
462}
463
464
465/**
466 * Gets the number of (unconsumed) entries in the event log.
467 *
468 * @returns The number of entries in the event log.
469 * @param pThis The IOMMU device state.
470 */
471static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
472{
473 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
474 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
475 if (idxTail >= idxHead)
476 return idxTail - idxHead;
477
478 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
479 return cMaxEvts - idxHead + idxTail;
480}
481
482
483#if 0
484/**
485 * Gets the number of (unconsumed) commands in the command buffer.
486 *
487 * @returns The number of commands in the command buffer.
488 * @param pThis The IOMMU device state.
489 */
490static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
491{
492 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
493 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
494 if (idxTail >= idxHead)
495 return idxTail - idxHead;
496
497 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
498 return cMaxCmds - idxHead + idxTail;
499}
500#endif
501
502
503DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
504{
505 IOMMU_STATUS_T Status;
506 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
507 return Status;
508}
509
510
511DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
512{
513 IOMMU_CTRL_T Ctrl;
514 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
515 return Ctrl;
516}
517
518
519/**
520 * Returns whether MSI is enabled for the IOMMU.
521 *
522 * @returns Whether MSI is enabled.
523 * @param pDevIns The IOMMU device instance.
524 *
525 * @note There should be a PCIDevXxx function for this.
526 */
527static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
528{
529 MSI_CAP_HDR_T MsiCapHdr;
530 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
531 return MsiCapHdr.n.u1MsiEnable;
532}
533
534
535/**
536 * Signals a PCI target abort.
537 *
538 * @param pDevIns The IOMMU device instance.
539 */
540static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
541{
542 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
543 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
544 PDMPciDevSetStatus(pPciDev, u16Status);
545}
546
547
548/**
549 * Wakes up the command thread if there are commands to be processed or if
550 * processing is requested to be stopped by software.
551 *
552 * @param pDevIns The IOMMU device instance.
553 */
554static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
555{
556 IOMMU_ASSERT_LOCKED(pDevIns);
557 Log5Func(("\n"));
558
559 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
560 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
561 if (Status.n.u1CmdBufRunning)
562 {
563 Log5Func(("Signaling command thread\n"));
564 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
565 }
566}
567
568
569/**
570 * Reads the Device Table Base Address Register.
571 */
572static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
573{
574 RT_NOREF(pDevIns, offReg);
575 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
576 return VINF_SUCCESS;
577}
578
579
580/**
581 * Reads the Command Buffer Base Address Register.
582 */
583static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
584{
585 RT_NOREF(pDevIns, offReg);
586 *pu64Value = pThis->CmdBufBaseAddr.u64;
587 return VINF_SUCCESS;
588}
589
590
591/**
592 * Reads the Event Log Base Address Register.
593 */
594static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
595{
596 RT_NOREF(pDevIns, offReg);
597 *pu64Value = pThis->EvtLogBaseAddr.u64;
598 return VINF_SUCCESS;
599}
600
601
602/**
603 * Reads the Control Register.
604 */
605static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
606{
607 RT_NOREF(pDevIns, offReg);
608 *pu64Value = pThis->Ctrl.u64;
609 return VINF_SUCCESS;
610}
611
612
613/**
614 * Reads the Exclusion Range Base Address Register.
615 */
616static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
617{
618 RT_NOREF(pDevIns, offReg);
619 *pu64Value = pThis->ExclRangeBaseAddr.u64;
620 return VINF_SUCCESS;
621}
622
623
624/**
625 * Reads to the Exclusion Range Limit Register.
626 */
627static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
628{
629 RT_NOREF(pDevIns, offReg);
630 *pu64Value = pThis->ExclRangeLimit.u64;
631 return VINF_SUCCESS;
632}
633
634
635/**
636 * Reads to the Extended Feature Register.
637 */
638static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
639{
640 RT_NOREF(pDevIns, offReg);
641 *pu64Value = pThis->ExtFeat.u64;
642 return VINF_SUCCESS;
643}
644
645
646/**
647 * Reads to the PPR Log Base Address Register.
648 */
649static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
650{
651 RT_NOREF(pDevIns, offReg);
652 *pu64Value = pThis->PprLogBaseAddr.u64;
653 return VINF_SUCCESS;
654}
655
656
657/**
658 * Writes the Hardware Event Register (Hi).
659 */
660static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
661{
662 RT_NOREF(pDevIns, offReg);
663 *pu64Value = pThis->HwEvtHi.u64;
664 return VINF_SUCCESS;
665}
666
667
668/**
669 * Reads the Hardware Event Register (Lo).
670 */
671static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
672{
673 RT_NOREF(pDevIns, offReg);
674 *pu64Value = pThis->HwEvtLo;
675 return VINF_SUCCESS;
676}
677
678
679/**
680 * Reads the Hardware Event Status Register.
681 */
682static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
683{
684 RT_NOREF(pDevIns, offReg);
685 *pu64Value = pThis->HwEvtStatus.u64;
686 return VINF_SUCCESS;
687}
688
689
690/**
691 * Reads to the GA Log Base Address Register.
692 */
693static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
694{
695 RT_NOREF(pDevIns, offReg);
696 *pu64Value = pThis->GALogBaseAddr.u64;
697 return VINF_SUCCESS;
698}
699
700
701/**
702 * Reads to the PPR Log B Base Address Register.
703 */
704static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
705{
706 RT_NOREF(pDevIns, offReg);
707 *pu64Value = pThis->PprLogBBaseAddr.u64;
708 return VINF_SUCCESS;
709}
710
711
712/**
713 * Reads to the Event Log B Base Address Register.
714 */
715static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
716{
717 RT_NOREF(pDevIns, offReg);
718 *pu64Value = pThis->EvtLogBBaseAddr.u64;
719 return VINF_SUCCESS;
720}
721
722
723/**
724 * Reads the Device Table Segment Base Address Register.
725 */
726static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
727{
728 RT_NOREF(pDevIns);
729
730 /* Figure out which segment is being written. */
731 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
732 uint8_t const idxSegment = offSegment + 1;
733 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
734
735 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
736 return VINF_SUCCESS;
737}
738
739
740/**
741 * Reads the Device Specific Feature Extension (DSFX) Register.
742 */
743static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
744{
745 RT_NOREF(pDevIns, offReg);
746 *pu64Value = pThis->DevSpecificFeat.u64;
747 return VINF_SUCCESS;
748}
749
750/**
751 * Reads the Device Specific Control Extension (DSCX) Register.
752 */
753static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
754{
755 RT_NOREF(pDevIns, offReg);
756 *pu64Value = pThis->DevSpecificCtrl.u64;
757 return VINF_SUCCESS;
758}
759
760
761/**
762 * Reads the Device Specific Status Extension (DSSX) Register.
763 */
764static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
765{
766 RT_NOREF(pDevIns, offReg);
767 *pu64Value = pThis->DevSpecificStatus.u64;
768 return VINF_SUCCESS;
769}
770
771
772/**
773 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
774 */
775static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
776{
777 RT_NOREF(pDevIns, offReg);
778 uint32_t const uLo = pThis->MiscInfo.au32[0];
779 uint32_t const uHi = pThis->MiscInfo.au32[1];
780 *pu64Value = RT_MAKE_U64(uLo, uHi);
781 return VINF_SUCCESS;
782}
783
784
785#ifdef IOMMU_NEW_REGISTER_ACCESS
786/**
787 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
788 * Register (32-bit).
789 */
790static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
791{
792 RT_NOREF(pThis, offReg);
793 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
794 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
795 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
796 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
797 *pu64Value = RT_MAKE_U64(uLo, uHi);
798 return VINF_SUCCESS;
799}
800
801
802/**
803 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
804 */
805static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
806{
807 RT_NOREF(pThis, offReg);
808 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
809 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
810 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
811 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
812 *pu64Value = RT_MAKE_U64(uLo, uHi);
813 return VINF_SUCCESS;
814}
815#endif
816
817
818/**
819 * Reads the Command Buffer Head Pointer Register.
820 */
821static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
822{
823 RT_NOREF(pDevIns, offReg);
824 *pu64Value = pThis->CmdBufHeadPtr.u64;
825 return VINF_SUCCESS;
826}
827
828
829/**
830 * Reads the Command Buffer Tail Pointer Register.
831 */
832static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
833{
834 RT_NOREF(pDevIns, offReg);
835 *pu64Value = pThis->CmdBufTailPtr.u64;
836 return VINF_SUCCESS;
837}
838
839
840/**
841 * Reads the Event Log Head Pointer Register.
842 */
843static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
844{
845 RT_NOREF(pDevIns, offReg);
846 *pu64Value = pThis->EvtLogHeadPtr.u64;
847 return VINF_SUCCESS;
848}
849
850
851/**
852 * Reads the Event Log Tail Pointer Register.
853 */
854static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
855{
856 RT_NOREF(pDevIns, offReg);
857 *pu64Value = pThis->EvtLogTailPtr.u64;
858 return VINF_SUCCESS;
859}
860
861
862/**
863 * Reads the Status Register.
864 */
865static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
866{
867 RT_NOREF(pDevIns, offReg);
868 *pu64Value = pThis->Status.u64;
869 return VINF_SUCCESS;
870}
871
872#ifndef IOMMU_NEW_REGISTER_ACCESS
873static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
874{
875 RT_NOREF(pDevIns, pThis, offReg, u64Value);
876 return VINF_SUCCESS;
877}
878#endif
879
880
881/**
882 * Writes the Device Table Base Address Register.
883 */
884static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
885{
886 RT_NOREF(pDevIns, offReg);
887
888 /* Mask out all unrecognized bits. */
889 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
890
891 /* Update the register. */
892 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
893 return VINF_SUCCESS;
894}
895
896
897/**
898 * Writes the Command Buffer Base Address Register.
899 */
900static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
901{
902 RT_NOREF(pDevIns, offReg);
903
904 /*
905 * While this is not explicitly specified like the event log base address register,
906 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
907 * Inconsistent specs :/
908 */
909 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
910 if (Status.n.u1CmdBufRunning)
911 {
912 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
913 return VINF_SUCCESS;
914 }
915
916 /* Mask out all unrecognized bits. */
917 CMD_BUF_BAR_T CmdBufBaseAddr;
918 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
919
920 /* Validate the length. */
921 if (CmdBufBaseAddr.n.u4Len >= 8)
922 {
923 /* Update the register. */
924 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
925
926 /*
927 * Writing the command buffer base address, clears the command buffer head and tail pointers.
928 * See AMD spec. 2.4 "Commands".
929 */
930 pThis->CmdBufHeadPtr.u64 = 0;
931 pThis->CmdBufTailPtr.u64 = 0;
932 }
933 else
934 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
935
936 return VINF_SUCCESS;
937}
938
939
940/**
941 * Writes the Event Log Base Address Register.
942 */
943static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
944{
945 RT_NOREF(pDevIns, offReg);
946
947 /*
948 * IOMMU behavior is undefined when software writes this register when event logging is running.
949 * In our emulation, we ignore the write entirely.
950 * See AMD IOMMU spec. "Event Log Base Address Register".
951 */
952 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
953 if (Status.n.u1EvtLogRunning)
954 {
955 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
956 return VINF_SUCCESS;
957 }
958
959 /* Mask out all unrecognized bits. */
960 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
961 EVT_LOG_BAR_T EvtLogBaseAddr;
962 EvtLogBaseAddr.u64 = u64Value;
963
964 /* Validate the length. */
965 if (EvtLogBaseAddr.n.u4Len >= 8)
966 {
967 /* Update the register. */
968 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
969
970 /*
971 * Writing the event log base address, clears the event log head and tail pointers.
972 * See AMD spec. 2.5 "Event Logging".
973 */
974 pThis->EvtLogHeadPtr.u64 = 0;
975 pThis->EvtLogTailPtr.u64 = 0;
976 }
977 else
978 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
979
980 return VINF_SUCCESS;
981}
982
983
984/**
985 * Writes the Control Register.
986 */
987static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
988{
989 RT_NOREF(pDevIns, offReg);
990
991 /* Mask out all unrecognized bits. */
992 u64Value &= IOMMU_CTRL_VALID_MASK;
993 IOMMU_CTRL_T NewCtrl;
994 NewCtrl.u64 = u64Value;
995
996 /* Ensure the device table segments are within limits. */
997 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
998 {
999 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
1000
1001 /* Update the register. */
1002 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
1003
1004 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
1005 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
1006
1007 /* Enable or disable event logging when the bit transitions. */
1008 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
1009 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1010 if ( fOldEvtLogEn != fNewEvtLogEn
1011 || fOldIommuEn != fNewIommuEn)
1012 {
1013 if ( fNewIommuEn
1014 && fNewEvtLogEn)
1015 {
1016 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1017 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1018 }
1019 else
1020 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1021 }
1022
1023 /* Enable or disable command buffer processing when the bit transitions. */
1024 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1025 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1026 if ( fOldCmdBufEn != fNewCmdBufEn
1027 || fOldIommuEn != fNewIommuEn)
1028 {
1029 if ( fNewCmdBufEn
1030 && fNewIommuEn)
1031 {
1032 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1033 LogFunc(("Command buffer enabled\n"));
1034
1035 /* Wake up the command thread to start processing commands. */
1036 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1037 }
1038 else
1039 {
1040 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1041 LogFunc(("Command buffer disabled\n"));
1042 }
1043 }
1044 }
1045 else
1046 {
1047 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1048 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1049 }
1050
1051 return VINF_SUCCESS;
1052}
1053
1054
1055/**
1056 * Writes to the Exclusion Range Base Address Register.
1057 */
1058static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1059{
1060 RT_NOREF(pDevIns, offReg);
1061 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1062 return VINF_SUCCESS;
1063}
1064
1065
1066/**
1067 * Writes to the Exclusion Range Limit Register.
1068 */
1069static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1070{
1071 RT_NOREF(pDevIns, offReg);
1072 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1073 u64Value |= UINT64_C(0xfff);
1074 pThis->ExclRangeLimit.u64 = u64Value;
1075 return VINF_SUCCESS;
1076}
1077
1078
1079/**
1080 * Writes the Hardware Event Register (Hi).
1081 */
1082static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1083{
1084 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1085 RT_NOREF(pDevIns, offReg);
1086 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1087 pThis->HwEvtHi.u64 = u64Value;
1088 return VINF_SUCCESS;
1089}
1090
1091
1092/**
1093 * Writes the Hardware Event Register (Lo).
1094 */
1095static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1096{
1097 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1098 RT_NOREF(pDevIns, offReg);
1099 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1100 pThis->HwEvtLo = u64Value;
1101 return VINF_SUCCESS;
1102}
1103
1104
1105/**
1106 * Writes the Hardware Event Status Register.
1107 */
1108static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1109{
1110 RT_NOREF(pDevIns, offReg);
1111
1112 /* Mask out all unrecognized bits. */
1113 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1114
1115 /*
1116 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1117 * If the current status bits or the bits being written are both 0, we've nothing to do.
1118 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1119 */
1120 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1121 if (!(HwStatus & RT_BIT(0)))
1122 return VINF_SUCCESS;
1123 if (u64Value & HwStatus & RT_BIT_64(0))
1124 HwStatus &= ~RT_BIT_64(0);
1125 if (u64Value & HwStatus & RT_BIT_64(1))
1126 HwStatus &= ~RT_BIT_64(1);
1127
1128 /* Update the register. */
1129 pThis->HwEvtStatus.u64 = HwStatus;
1130 return VINF_SUCCESS;
1131}
1132
1133
1134/**
1135 * Writes the Device Table Segment Base Address Register.
1136 */
1137static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1138{
1139 RT_NOREF(pDevIns);
1140
1141 /* Figure out which segment is being written. */
1142 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1143 uint8_t const idxSegment = offSegment + 1;
1144 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1145
1146 /* Mask out all unrecognized bits. */
1147 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1148 DEV_TAB_BAR_T DevTabSegBar;
1149 DevTabSegBar.u64 = u64Value;
1150
1151 /* Validate the size. */
1152 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1153 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1154 if (uSegSize <= uMaxSegSize)
1155 {
1156 /* Update the register. */
1157 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1158 }
1159 else
1160 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1161
1162 return VINF_SUCCESS;
1163}
1164
1165
1166#ifndef IOMMU_NEW_REGISTER_ACCESS
1167/**
1168 * Writes the MSI Capability Header Register.
1169 */
1170static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1171{
1172 RT_NOREF(pThis, offReg);
1173 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1174 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1175 MSI_CAP_HDR_T MsiCapHdr;
1176 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1177 MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1178 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1179 return VINF_SUCCESS;
1180}
1181
1182
1183/**
1184 * Writes the MSI Address (Lo) Register (32-bit).
1185 */
1186static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1187{
1188 RT_NOREF(pThis, offReg);
1189 Assert(!RT_HI_U32(u64Value));
1190 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1191 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1192 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
1193 return VINF_SUCCESS;
1194}
1195
1196
1197/**
1198 * Writes the MSI Address (Hi) Register (32-bit).
1199 */
1200static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1201{
1202 RT_NOREF(pThis, offReg);
1203 Assert(!RT_HI_U32(u64Value));
1204 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1205 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1206 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
1207 return VINF_SUCCESS;
1208}
1209
1210
1211/**
1212 * Writes the MSI Data Register (32-bit).
1213 */
1214static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1215{
1216 RT_NOREF(pThis, offReg);
1217 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1218 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1219 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
1220 return VINF_SUCCESS;
1221}
1222#else
1223/**
1224 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1225 */
1226static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1227{
1228 RT_NOREF(pDevIns, offReg);
1229
1230 /* MSI Vector Register 0 is read-only. */
1231 /* MSI Vector Register 1. */
1232 uint32_t const uReg = u64Value >> 32;
1233 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
1234 return VINF_SUCCESS;
1235}
1236
1237
1238/**
1239 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1240 * Register (32-bit).
1241 */
1242static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1243{
1244 RT_NOREF(pThis, offReg);
1245 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1246 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1247
1248 /* MSI capability header. */
1249 {
1250 uint32_t const uReg = u64Value;
1251 MSI_CAP_HDR_T MsiCapHdr;
1252 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1253 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1254 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1255 }
1256
1257 /* MSI Address Lo. */
1258 {
1259 uint32_t const uReg = u64Value >> 32;
1260 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
1261 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1262 }
1263
1264 return VINF_SUCCESS;
1265}
1266
1267
1268/**
1269 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1270 */
1271static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1272{
1273 RT_NOREF(pThis, offReg);
1274 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1275 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1276
1277 /* MSI Address Hi. */
1278 {
1279 uint32_t const uReg = u64Value;
1280 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
1281 }
1282
1283 /* MSI Data. */
1284 {
1285 uint32_t const uReg = u64Value >> 32;
1286 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
1287 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1288 }
1289
1290 return VINF_SUCCESS;
1291}
1292#endif
1293
1294
1295/**
1296 * Writes the Command Buffer Head Pointer Register.
1297 */
1298static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1299{
1300 RT_NOREF(pDevIns, offReg);
1301
1302 /*
1303 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1304 * In our emulation, we ignore the write entirely.
1305 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1306 */
1307 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1308 if (Status.n.u1CmdBufRunning)
1309 {
1310 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1311 return VINF_SUCCESS;
1312 }
1313
1314 /*
1315 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1316 * In our emulation, we ignore the write entirely.
1317 */
1318 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1319 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1320 Assert(cbBuf <= _512K);
1321 if (offBuf >= cbBuf)
1322 {
1323 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1324 return VINF_SUCCESS;
1325 }
1326
1327 /* Update the register. */
1328 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1329
1330 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1331
1332 Log5Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1333 return VINF_SUCCESS;
1334}
1335
1336
1337/**
1338 * Writes the Command Buffer Tail Pointer Register.
1339 */
1340static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1341{
1342 RT_NOREF(pDevIns, offReg);
1343
1344 /*
1345 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1346 * In our emulation, we ignore the write entirely.
1347 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1348 */
1349 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1350 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1351 Assert(cbBuf <= _512K);
1352 if (offBuf >= cbBuf)
1353 {
1354 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1355 return VINF_SUCCESS;
1356 }
1357
1358 /*
1359 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1360 * head pointer after adding one or more commands to the buffer.
1361 *
1362 * However, we cannot enforce this strictly because it's legal for software to shrink the
1363 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1364 * at 0). Software might even make the queue empty by making head and tail equal which is
1365 * allowed. I don't think we can or should try too hard to prevent software shooting itself
1366 * in the foot here. As long as we make sure the offset value is within the circular buffer
1367 * bounds (which we do by masking bits above) it should be sufficient.
1368 */
1369 pThis->CmdBufTailPtr.au32[0] = offBuf;
1370
1371 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1372
1373 Log5Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1374 return VINF_SUCCESS;
1375}
1376
1377
1378/**
1379 * Writes the Event Log Head Pointer Register.
1380 */
1381static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1382{
1383 RT_NOREF(pDevIns, offReg);
1384
1385 /*
1386 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1387 * In our emulation, we ignore the write entirely.
1388 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1389 */
1390 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1391 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1392 Assert(cbBuf <= _512K);
1393 if (offBuf >= cbBuf)
1394 {
1395 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1396 return VINF_SUCCESS;
1397 }
1398
1399 /* Update the register. */
1400 pThis->EvtLogHeadPtr.au32[0] = offBuf;
1401
1402 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1403 return VINF_SUCCESS;
1404}
1405
1406
1407/**
1408 * Writes the Event Log Tail Pointer Register.
1409 */
1410static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1411{
1412 RT_NOREF(pDevIns, offReg);
1413 NOREF(pThis);
1414
1415 /*
1416 * IOMMU behavior is undefined when software writes this register when the event log is running.
1417 * In our emulation, we ignore the write entirely.
1418 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1419 */
1420 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1421 if (Status.n.u1EvtLogRunning)
1422 {
1423 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1424 return VINF_SUCCESS;
1425 }
1426
1427 /*
1428 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1429 * In our emulation, we ignore the write entirely.
1430 */
1431 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1432 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1433 Assert(cbBuf <= _512K);
1434 if (offBuf >= cbBuf)
1435 {
1436 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1437 return VINF_SUCCESS;
1438 }
1439
1440 /* Update the register. */
1441 pThis->EvtLogTailPtr.au32[0] = offBuf;
1442
1443 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1444 return VINF_SUCCESS;
1445}
1446
1447
1448/**
1449 * Writes the Status Register.
1450 */
1451static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1452{
1453 RT_NOREF(pDevIns, offReg);
1454
1455 /* Mask out all unrecognized bits. */
1456 u64Value &= IOMMU_STATUS_VALID_MASK;
1457
1458 /*
1459 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1460 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1461 */
1462 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1463 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1464 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1465 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1466
1467 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1468
1469 /* Update the register. */
1470 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1471 return VINF_SUCCESS;
1472}
1473
1474#ifdef IOMMU_NEW_REGISTER_ACCESS
1475/**
1476 * Register access table 0.
1477 * The MMIO offset of each entry must be a multiple of 8!
1478 */
1479static const IOMMUREGACC g_aRegAccess0[] =
1480{
1481 /* MMIO off. Register name Read function Write function */
1482 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
1483 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
1484 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
1485 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
1486 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
1487 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
1488 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
1489 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
1490 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
1491 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
1492 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
1493 { /* 0x58 */ NULL, NULL, NULL },
1494
1495 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
1496 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
1497 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
1498 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
1499 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
1500 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
1501 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
1502 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
1503 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
1504 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
1505 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
1506 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
1507 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
1508 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
1509 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
1510 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
1511
1512 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
1513 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
1514 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
1515 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
1516
1517 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1518 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1519 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1520 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1521 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1522 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1523 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1524
1525 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
1526 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
1527 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
1528
1529 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
1530 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
1531 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
1532 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
1533
1534 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
1535 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
1536 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
1537};
1538AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1539
1540/**
1541 * Register access table 1.
1542 * The MMIO offset of each entry must be a multiple of 8!
1543 */
1544static const IOMMUREGACC g_aRegAccess1[] =
1545{
1546 /* MMIO offset Register name Read function Write function */
1547 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
1548 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
1549 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
1550 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
1551 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
1552 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
1553 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
1554 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
1555 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
1556 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
1557 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
1558 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
1559};
1560AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1561
1562/**
1563 * Register access table 2.
1564 * The MMIO offset of each entry must be a multiple of 8!
1565 */
1566static const IOMMUREGACC g_aRegAccess2[] =
1567{
1568 /* MMIO offset Register name Read Function Write function */
1569 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
1570
1571 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
1572 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
1573 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
1574 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
1575
1576 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
1577 { /* 0x2028 */ NULL, NULL, NULL },
1578
1579 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
1580 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
1581
1582 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
1583 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
1584
1585 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
1586 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
1587
1588 { /* 0x2060 */ NULL, NULL, NULL },
1589 { /* 0x2068 */ NULL, NULL, NULL },
1590
1591 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
1592 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
1593
1594 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
1595 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
1596 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
1597};
1598AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1599
1600
1601/**
1602 * Gets the register access structure given its MMIO offset.
1603 *
1604 * @returns The register access structure, or NULL if the offset is invalid.
1605 * @param off The MMIO offset of the register being accessed.
1606 */
1607static PCIOMMUREGACC iommuAmdGetRegAccessForOffset(uint32_t off)
1608{
1609 /* Figure out which table the register belongs to and validate its index. */
1610 PCIOMMUREGACC pReg;
1611 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1612 {
1613 uint32_t const idxReg = off >> 3;
1614 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1615 pReg = &g_aRegAccess0[idxReg];
1616 }
1617 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1618 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1619 {
1620 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1621 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1622 pReg = &g_aRegAccess1[idxReg];
1623 }
1624 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1625 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1626 {
1627 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1628 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1629 pReg = &g_aRegAccess2[idxReg];
1630 }
1631 else
1632 return NULL;
1633
1634 return pReg;
1635}
1636#endif
1637
1638
1639/**
1640 * Writes an IOMMU register (32-bit and 64-bit).
1641 *
1642 * @returns Strict VBox status code.
1643 * @param pDevIns The IOMMU device instance.
1644 * @param off MMIO byte offset to the register.
1645 * @param cb The size of the write access.
1646 * @param uValue The value being written.
1647 *
1648 * @thread EMT.
1649 */
1650static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1651{
1652 /*
1653 * Validate the access in case of IOM bug or incorrect assumption.
1654 */
1655 Assert(off < IOMMU_MMIO_REGION_SIZE);
1656 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1657 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1658
1659 Log5Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1660
1661 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1662#ifndef IOMMU_NEW_REGISTER_ACCESS
1663 switch (off)
1664 {
1665 case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1666 case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1667 case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1668 case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1669 case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1670 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1671 case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1672
1673 case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1674 case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1675 case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1676 case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1677
1678 case IOMMU_MMIO_OFF_GALOG_BAR:
1679 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1680
1681 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1682 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1683
1684 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1685 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1686 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1687 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1688 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1689 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1690 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1691
1692 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1693 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1694 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1695
1696 case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1697 case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1698 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1699 {
1700 VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1701 if (cb == 4 || RT_FAILURE(rcStrict))
1702 return rcStrict;
1703 uValue >>= 32;
1704 RT_FALL_THRU();
1705 }
1706 case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1707 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1708 {
1709 VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1710 if (cb == 4 || RT_FAILURE(rcStrict))
1711 return rcStrict;
1712 uValue >>= 32;
1713 RT_FALL_THRU();
1714 }
1715 case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1716 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1717
1718 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1719
1720 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1721 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1722 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1723
1724 case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1725 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1726 case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1727 case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1728 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1729 case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1730 case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1731 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1732 case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1733 case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1734 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1735 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1736
1737 case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1738
1739 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1740 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1741 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1742 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1743
1744 case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1745
1746 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1747 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1748
1749 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1750 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1751
1752 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1753 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1754
1755 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1756 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1757
1758 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1759 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1760 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1761
1762 /* Not implemented. */
1763 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1764 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1765 {
1766 LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1767 return VINF_SUCCESS;
1768 }
1769
1770 /* Unknown. */
1771 default:
1772 {
1773 LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1774 return VINF_SUCCESS;
1775 }
1776 }
1777#else
1778 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1779 if (pReg)
1780 { /* likely */ }
1781 else
1782 {
1783 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
1784 return VINF_SUCCESS;
1785 }
1786
1787 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
1788 if (pReg->pfnWrite)
1789 { /* likely */ }
1790 else
1791 {
1792 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1793 return VINF_SUCCESS;
1794 }
1795
1796 /*
1797 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
1798 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
1799 * consecutive 32-bit registers.
1800 */
1801 if (cb == 8)
1802 {
1803 if (!(off & 7))
1804 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1805
1806 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1807 return VINF_SUCCESS;
1808 }
1809
1810 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
1811 Assert(cb == 4);
1812 if (!(off & 7))
1813 {
1814 /*
1815 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
1816 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1817 */
1818 uint64_t u64Read;
1819 if (pReg->pfnRead)
1820 {
1821 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1822 if (RT_FAILURE(rcStrict))
1823 {
1824 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1825 return rcStrict;
1826 }
1827 }
1828 else
1829 u64Read = 0;
1830
1831 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
1832 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1833 }
1834
1835 /*
1836 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
1837 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1838 */
1839 Assert(!(off & 3));
1840 Assert(off & 7);
1841 Assert(off >= 4);
1842 uint64_t u64Read;
1843 if (pReg->pfnRead)
1844 {
1845 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1846 if (RT_FAILURE(rcStrict))
1847 {
1848 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1849 return rcStrict;
1850 }
1851 }
1852 else
1853 u64Read = 0;
1854
1855 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
1856 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1857#endif
1858}
1859
1860
1861/**
1862 * Reads an IOMMU register (64-bit) given its MMIO offset.
1863 *
1864 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1865 * boundary include the lower half of the subsequent register.
1866 *
1867 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1868 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1869 * software will only perform 32-bit reads on those 32-bit registers that are
1870 * aligned on 8-byte boundaries.
1871 *
1872 * @returns Strict VBox status code.
1873 * @param pDevIns The IOMMU device instance.
1874 * @param off The MMIO offset of the register in bytes.
1875 * @param puResult Where to store the value being read.
1876 *
1877 * @thread EMT.
1878 */
1879static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1880{
1881 Assert(off < IOMMU_MMIO_REGION_SIZE);
1882 Assert(!(off & 7) || !(off & 3));
1883
1884 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1885 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1886 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1887
1888 Log5Func(("off=%#x\n", off));
1889
1890#ifndef IOMMU_NEW_REGISTER_ACCESS
1891 /** @todo IOMMU: fine-grained locking? */
1892 uint64_t uReg;
1893 switch (off)
1894 {
1895 case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1896 case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1897 case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1898 case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1899 case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1900 case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1901 case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1902
1903 case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1904 case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1905 case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1906 case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1907
1908 case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1909 case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1910
1911 case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1912 case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1913
1914 case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1915 case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1916 case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1917 case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1918 case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1919 case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1920 case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1921 {
1922 uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1923 uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1924 Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1925 uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1926 break;
1927 }
1928
1929 case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1930 case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1931 case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1932
1933 case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1934 case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1935 case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1936 {
1937 uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1938 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1939 uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1940 break;
1941 }
1942 case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1943 {
1944 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1945 break;
1946 }
1947 case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1948 {
1949 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1950 uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1951 uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1952 break;
1953 }
1954 case IOMMU_MMIO_OFF_MSI_DATA:
1955 {
1956 uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1957 break;
1958 }
1959 case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1960 {
1961 /*
1962 * The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1963 * The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1964 * though HyperTransport is supported. We don't support HyperTransport, we thus just return
1965 * 0 for this register.
1966 */
1967 uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1968 break;
1969 }
1970
1971 case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1972
1973 case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1974 case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1975 case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1976
1977 case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1978 case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1979 case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1980 case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1981 case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1982 case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1983 case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1984 case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1985 case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1986 case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1987 case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1988 case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1989
1990 case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1991
1992 case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1993 case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1994 case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1995 case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1996
1997 case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
1998
1999 case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
2000 case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
2001
2002 case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
2003 case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
2004
2005 case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
2006 case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
2007
2008 case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
2009 case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
2010
2011 case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
2012 case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
2013 case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
2014
2015 /* Not implemented. */
2016 case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
2017 case IOMMU_MMIO_OFF_SMI_FLT_LAST:
2018 {
2019 LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
2020 uReg = 0;
2021 break;
2022 }
2023
2024 /* Unknown. */
2025 default:
2026 {
2027 LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
2028 uReg = 0;
2029 return VINF_IOM_MMIO_UNUSED_00;
2030 }
2031 }
2032
2033 *puResult = uReg;
2034 return VINF_SUCCESS;
2035#else
2036 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
2037 if (pReg)
2038 { /* likely */ }
2039 else
2040 {
2041 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2042 return VINF_IOM_MMIO_UNUSED_FF;
2043 }
2044
2045 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2046 if (pReg->pfnRead)
2047 { /* likely */ }
2048 else
2049 {
2050 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2051 return VINF_IOM_MMIO_UNUSED_00;
2052 }
2053
2054 /*
2055 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2056 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2057 */
2058 if (!(off & 7))
2059 return pReg->pfnRead(pDevIns, pThis, off, puResult);
2060
2061 /*
2062 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2063 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2064 */
2065 Assert(!(off & 3));
2066 Assert(off & 7);
2067 Assert(off >= 4);
2068 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2069 if (RT_SUCCESS(rcStrict))
2070 *puResult >>= 32;
2071 else
2072 {
2073 *puResult = 0;
2074 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2075 }
2076
2077 return rcStrict;
2078#endif
2079}
2080
2081
2082/**
2083 * Raises the MSI interrupt for the IOMMU device.
2084 *
2085 * @param pDevIns The IOMMU device instance.
2086 *
2087 * @thread Any.
2088 * @remarks The IOMMU lock may or may not be held.
2089 */
2090static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
2091{
2092 LogFlowFunc(("\n"));
2093 if (iommuAmdIsMsiEnabled(pDevIns))
2094 {
2095 LogFunc(("Raising MSI\n"));
2096 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2097 }
2098}
2099
2100#if 0
2101/**
2102 * Clears the MSI interrupt for the IOMMU device.
2103 *
2104 * @param pDevIns The IOMMU device instance.
2105 *
2106 * @thread Any.
2107 * @remarks The IOMMU lock may or may not be held.
2108 */
2109static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
2110{
2111 if (iommuAmdIsMsiEnabled(pDevIns))
2112 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2113}
2114#endif
2115
2116/**
2117 * Writes an entry to the event log in memory.
2118 *
2119 * @returns VBox status code.
2120 * @param pDevIns The IOMMU device instance.
2121 * @param pEvent The event to log.
2122 *
2123 * @thread Any.
2124 */
2125static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2126{
2127 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2128
2129 IOMMU_ASSERT_LOCKED(pDevIns);
2130
2131 /* Check if event logging is active and the log has not overflowed. */
2132 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2133 if ( Status.n.u1EvtLogRunning
2134 && !Status.n.u1EvtOverflow)
2135 {
2136 uint32_t const cbEvt = sizeof(*pEvent);
2137
2138 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2139 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2140 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2141
2142 /* Ensure we have space in the event log. */
2143 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2144 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2145 if (cEvts + 1 < cMaxEvts)
2146 {
2147 /* Write the event log entry to memory. */
2148 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2149 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2150 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2151 if (RT_FAILURE(rc))
2152 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2153
2154 /* Increment the event log tail pointer. */
2155 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2156 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2157
2158 /* Indicate that an event log entry was written. */
2159 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2160
2161 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2162 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2163 if (Ctrl.n.u1EvtIntrEn)
2164 iommuAmdRaiseMsiInterrupt(pDevIns);
2165 }
2166 else
2167 {
2168 /* Indicate that the event log has overflowed. */
2169 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2170
2171 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2172 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2173 if (Ctrl.n.u1EvtIntrEn)
2174 iommuAmdRaiseMsiInterrupt(pDevIns);
2175 }
2176 }
2177
2178 return VINF_SUCCESS;
2179}
2180
2181
2182/**
2183 * Sets an event in the hardware error registers.
2184 *
2185 * @param pDevIns The IOMMU device instance.
2186 * @param pEvent The event.
2187 *
2188 * @thread Any.
2189 */
2190static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2191{
2192 IOMMU_ASSERT_LOCKED(pDevIns);
2193
2194 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2195 if (pThis->ExtFeat.n.u1HwErrorSup)
2196 {
2197 if (pThis->HwEvtStatus.n.u1Valid)
2198 pThis->HwEvtStatus.n.u1Overflow = 1;
2199 pThis->HwEvtStatus.n.u1Valid = 1;
2200 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2201 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2202 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2203 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2204 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2205 }
2206}
2207
2208
2209/**
2210 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2211 *
2212 * @param uDevId The device ID.
2213 * @param uDomainId The domain ID.
2214 * @param GCPhysPtEntity The system physical address of the page table
2215 * entity.
2216 * @param enmOp The IOMMU operation being performed.
2217 * @param pEvtPageTabHwErr Where to store the initialized event.
2218 */
2219static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2220 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2221{
2222 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2223 pEvtPageTabHwErr->n.u16DevId = uDevId;
2224 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
2225 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
2226 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2227 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2228 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2229 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2230 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
2231 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
2232}
2233
2234
2235/**
2236 * Raises a PAGE_TAB_HARDWARE_ERROR event.
2237 *
2238 * @param pDevIns The IOMMU device instance.
2239 * @param enmOp The IOMMU operation being performed.
2240 * @param pEvtPageTabHwErr The page table hardware error event.
2241 *
2242 * @thread Any.
2243 */
2244static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2245{
2246 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
2247 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
2248
2249 IOMMU_LOCK_NORET(pDevIns);
2250
2251 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2252 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2253 if (enmOp != IOMMUOP_CMD)
2254 iommuAmdSetPciTargetAbort(pDevIns);
2255
2256 IOMMU_UNLOCK(pDevIns);
2257
2258 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
2259 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
2260 pEvtPageTabHwErr->n.u2Type));
2261}
2262
2263
2264#ifdef IN_RING3
2265/**
2266 * Initializes a COMMAND_HARDWARE_ERROR event.
2267 *
2268 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
2269 * @param pEvtCmdHwErr Where to store the initialized event.
2270 */
2271static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2272{
2273 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
2274 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
2275 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
2276 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
2277}
2278
2279
2280/**
2281 * Raises a COMMAND_HARDWARE_ERROR event.
2282 *
2283 * @param pDevIns The IOMMU device instance.
2284 * @param pEvtCmdHwErr The command hardware error event.
2285 *
2286 * @thread Any.
2287 */
2288static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2289{
2290 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
2291 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
2292 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2293
2294 IOMMU_LOCK_NORET(pDevIns);
2295
2296 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2297 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2298 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2299
2300 IOMMU_UNLOCK(pDevIns);
2301
2302 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
2303}
2304#endif /* IN_RING3 */
2305
2306
2307/**
2308 * Initializes a DEV_TAB_HARDWARE_ERROR event.
2309 *
2310 * @param uDevId The device ID.
2311 * @param GCPhysDte The system physical address of the failed device table
2312 * access.
2313 * @param enmOp The IOMMU operation being performed.
2314 * @param pEvtDevTabHwErr Where to store the initialized event.
2315 */
2316static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
2317 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2318{
2319 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
2320 pEvtDevTabHwErr->n.u16DevId = uDevId;
2321 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2322 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
2323 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2324 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2325 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2326 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
2327 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
2328}
2329
2330
2331/**
2332 * Raises a DEV_TAB_HARDWARE_ERROR event.
2333 *
2334 * @param pDevIns The IOMMU device instance.
2335 * @param enmOp The IOMMU operation being performed.
2336 * @param pEvtDevTabHwErr The device table hardware error event.
2337 *
2338 * @thread Any.
2339 */
2340static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2341{
2342 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2343 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2344
2345 IOMMU_LOCK_NORET(pDevIns);
2346
2347 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2348 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2349 if (enmOp != IOMMUOP_CMD)
2350 iommuAmdSetPciTargetAbort(pDevIns);
2351
2352 IOMMU_UNLOCK(pDevIns);
2353
2354 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2355 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2356}
2357
2358#ifdef IN_RING3
2359/**
2360 * Initializes an ILLEGAL_COMMAND_ERROR event.
2361 *
2362 * @param GCPhysCmd The system physical address of the failed command
2363 * access.
2364 * @param pEvtIllegalCmd Where to store the initialized event.
2365 */
2366static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2367{
2368 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2369 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2370 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2371 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2372}
2373
2374
2375/**
2376 * Raises an ILLEGAL_COMMAND_ERROR event.
2377 *
2378 * @param pDevIns The IOMMU device instance.
2379 * @param pEvtIllegalCmd The illegal command error event.
2380 */
2381static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2382{
2383 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2384 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2385 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2386
2387 IOMMU_LOCK_NORET(pDevIns);
2388
2389 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2390 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2391
2392 IOMMU_UNLOCK(pDevIns);
2393
2394 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2395}
2396#endif /* IN_RING3 */
2397
2398
2399/**
2400 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2401 *
2402 * @param uDevId The device ID.
2403 * @param uIova The I/O virtual address.
2404 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2405 * event was caused by an invalid level encoding in the
2406 * DTE.
2407 * @param enmOp The IOMMU operation being performed.
2408 * @param pEvtIllegalDte Where to store the initialized event.
2409 */
2410static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2411 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2412{
2413 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2414 pEvtIllegalDte->n.u16DevId = uDevId;
2415 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2416 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2417 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2418 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2419 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2420 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2421 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2422 * IOMMU spec here but not for this field for I/O page fault event. */
2423 Assert(!(uIova & UINT64_C(0x3)));
2424}
2425
2426
2427/**
2428 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2429 *
2430 * @param pDevIns The IOMMU instance data.
2431 * @param enmOp The IOMMU operation being performed.
2432 * @param pEvtIllegalDte The illegal device table entry event.
2433 * @param enmEvtType The illegal device table entry event type.
2434 *
2435 * @thread Any.
2436 */
2437static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2438 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2439{
2440 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2441 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2442
2443 IOMMU_LOCK_NORET(pDevIns);
2444
2445 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2446 if (enmOp != IOMMUOP_CMD)
2447 iommuAmdSetPciTargetAbort(pDevIns);
2448
2449 IOMMU_UNLOCK(pDevIns);
2450
2451 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2452 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2453 NOREF(enmEvtType);
2454}
2455
2456
2457/**
2458 * Initializes an IO_PAGE_FAULT event.
2459 *
2460 * @param uDevId The device ID.
2461 * @param uDomainId The domain ID.
2462 * @param uIova The I/O virtual address being accessed.
2463 * @param fPresent Transaction to a page marked as present (including
2464 * DTE.V=1) or interrupt marked as remapped
2465 * (IRTE.RemapEn=1).
2466 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2467 * the I/O page fault was caused by invalid level
2468 * encoding.
2469 * @param fPermDenied Permission denied for the address being accessed.
2470 * @param enmOp The IOMMU operation being performed.
2471 * @param pEvtIoPageFault Where to store the initialized event.
2472 */
2473static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2474 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2475{
2476 Assert(!fPermDenied || fPresent);
2477 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2478 pEvtIoPageFault->n.u16DevId = uDevId;
2479 //pEvtIoPageFault->n.u4PasidHi = 0;
2480 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2481 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2482 //pEvtIoPageFault->n.u1NoExecute = 0;
2483 //pEvtIoPageFault->n.u1User = 0;
2484 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2485 pEvtIoPageFault->n.u1Present = fPresent;
2486 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2487 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2488 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2489 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2490 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2491 pEvtIoPageFault->n.u64Addr = uIova;
2492}
2493
2494
2495/**
2496 * Raises an IO_PAGE_FAULT event.
2497 *
2498 * @param pDevIns The IOMMU instance data.
2499 * @param pDte The device table entry. Optional, can be NULL
2500 * depending on @a enmOp.
2501 * @param pIrte The interrupt remapping table entry. Optional, can
2502 * be NULL depending on @a enmOp.
2503 * @param enmOp The IOMMU operation being performed.
2504 * @param pEvtIoPageFault The I/O page fault event.
2505 * @param enmEvtType The I/O page fault event type.
2506 *
2507 * @thread Any.
2508 */
2509static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2510 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2511{
2512 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2513 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2514
2515 IOMMU_LOCK_NORET(pDevIns);
2516
2517 bool fSuppressEvtLogging = false;
2518 if ( enmOp == IOMMUOP_MEM_READ
2519 || enmOp == IOMMUOP_MEM_WRITE)
2520 {
2521 if ( pDte
2522 && pDte->n.u1Valid)
2523 {
2524 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2525 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2526 * suppression. Perhaps will be possible when we complete IOTLB/cache
2527 * handling. */
2528 }
2529 }
2530 else if (enmOp == IOMMUOP_INTR_REQ)
2531 {
2532 if ( pDte
2533 && pDte->n.u1IntrMapValid)
2534 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2535
2536 if ( !fSuppressEvtLogging
2537 && pIrte)
2538 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2539 }
2540 /* else: Events are never suppressed for commands. */
2541
2542 switch (enmEvtType)
2543 {
2544 case kIoPageFaultType_PermDenied:
2545 {
2546 /* Cannot be triggered by a command. */
2547 Assert(enmOp != IOMMUOP_CMD);
2548 RT_FALL_THRU();
2549 }
2550 case kIoPageFaultType_DteRsvdPagingMode:
2551 case kIoPageFaultType_PteInvalidPageSize:
2552 case kIoPageFaultType_PteInvalidLvlEncoding:
2553 case kIoPageFaultType_SkippedLevelIovaNotZero:
2554 case kIoPageFaultType_PteRsvdNotZero:
2555 case kIoPageFaultType_PteValidNotSet:
2556 case kIoPageFaultType_DteTranslationDisabled:
2557 case kIoPageFaultType_PasidInvalidRange:
2558 {
2559 /*
2560 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2561 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
2562 */
2563 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2564 {
2565 if (!fSuppressEvtLogging)
2566 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2567 if (enmOp != IOMMUOP_CMD)
2568 iommuAmdSetPciTargetAbort(pDevIns);
2569 }
2570 break;
2571 }
2572
2573 case kIoPageFaultType_UserSupervisor:
2574 {
2575 /* Access is blocked and only creates an event log entry. */
2576 if (!fSuppressEvtLogging)
2577 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2578 break;
2579 }
2580
2581 case kIoPageFaultType_IrteAddrInvalid:
2582 case kIoPageFaultType_IrteRsvdNotZero:
2583 case kIoPageFaultType_IrteRemapEn:
2584 case kIoPageFaultType_IrteRsvdIntType:
2585 case kIoPageFaultType_IntrReqAborted:
2586 case kIoPageFaultType_IntrWithPasid:
2587 {
2588 /* Only trigerred by interrupt requests. */
2589 Assert(enmOp == IOMMUOP_INTR_REQ);
2590 if (!fSuppressEvtLogging)
2591 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2592 iommuAmdSetPciTargetAbort(pDevIns);
2593 break;
2594 }
2595
2596 case kIoPageFaultType_SmiFilterMismatch:
2597 {
2598 /* Not supported and probably will never be, assert. */
2599 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2600 break;
2601 }
2602
2603 case kIoPageFaultType_DevId_Invalid:
2604 {
2605 /* Cannot be triggered by a command. */
2606 Assert(enmOp != IOMMUOP_CMD);
2607 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2608 if (!fSuppressEvtLogging)
2609 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2610 if ( enmOp == IOMMUOP_MEM_READ
2611 || enmOp == IOMMUOP_MEM_WRITE)
2612 iommuAmdSetPciTargetAbort(pDevIns);
2613 break;
2614 }
2615 }
2616
2617 IOMMU_UNLOCK(pDevIns);
2618}
2619
2620
2621/**
2622 * Returns whether the I/O virtual address is to be excluded from translation and
2623 * permission checks.
2624 *
2625 * @returns @c true if the DVA is excluded, @c false otherwise.
2626 * @param pThis The IOMMU device state.
2627 * @param pDte The device table entry.
2628 * @param uIova The I/O virtual address.
2629 *
2630 * @remarks Ensure the exclusion range is enabled prior to calling this function.
2631 *
2632 * @thread Any.
2633 */
2634static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2635{
2636 /* Ensure the exclusion range is enabled. */
2637 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2638
2639 /* Check if the IOVA falls within the exclusion range. */
2640 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2641 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2642 if (uIovaExclLast - uIova >= uIovaExclFirst)
2643 {
2644 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2645 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2646 || pDte->n.u1AllowExclusion)
2647 return true;
2648 }
2649 return false;
2650}
2651
2652
2653/**
2654 * Reads a device table entry from guest memory given the device ID.
2655 *
2656 * @returns VBox status code.
2657 * @param pDevIns The IOMMU device instance.
2658 * @param uDevId The device ID.
2659 * @param enmOp The IOMMU operation being performed.
2660 * @param pDte Where to store the device table entry.
2661 *
2662 * @thread Any.
2663 */
2664static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2665{
2666 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2667 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2668
2669 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2670 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2671
2672 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2673 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2674 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
2675
2676 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2677 uint16_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2678 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2679
2680 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2681 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2682 if (RT_FAILURE(rc))
2683 {
2684 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2685
2686 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2687 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2688 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2689 return VERR_IOMMU_IPE_1;
2690 }
2691
2692 return rc;
2693}
2694
2695
2696/**
2697 * Walks the I/O page table to translate the I/O virtual address to a system
2698 * physical address.
2699 *
2700 * @returns VBox status code.
2701 * @param pDevIns The IOMMU device instance.
2702 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2703 * @param uDevId The device ID.
2704 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2705 * permissions for the access being made.
2706 * @param pDte The device table entry.
2707 * @param enmOp The IOMMU operation being performed.
2708 * @param pWalkResult Where to store the results of the I/O page walk. This is
2709 * only updated when VINF_SUCCESS is returned.
2710 *
2711 * @thread Any.
2712 */
2713static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2714 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2715{
2716 Assert(pDte->n.u1Valid);
2717 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2718
2719 /* If the translation is not valid, raise an I/O page fault. */
2720 if (pDte->n.u1TranslationValid)
2721 { /* likely */ }
2722 else
2723 {
2724 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2725 * doesn't explicitly say whether an I/O page fault is raised. From other
2726 * places in the spec. it seems early page walk terminations (starting with
2727 * the DTE) return the state computed so far and raises an I/O page fault. So
2728 * returning an invalid translation rather than skipping translation. */
2729 LogFunc(("Translation valid bit not set -> IOPF\n"));
2730 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2731 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2732 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2733 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2734 kIoPageFaultType_DteTranslationDisabled);
2735 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2736 }
2737
2738 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2739 uint8_t const uMaxLevel = pDte->n.u3Mode;
2740 if (uMaxLevel != 0)
2741 { /* likely */ }
2742 else
2743 {
2744 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2745 if ((fAccess & fDtePerm) != fAccess)
2746 {
2747 LogFunc(("Access denied for IOVA %#RX64. uDevId=%#x fAccess=%#x fDtePerm=%#x\n", uIova, uDevId, fAccess, fDtePerm));
2748 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2749 }
2750 pWalkResult->GCPhysSpa = uIova;
2751 pWalkResult->cShift = 0;
2752 pWalkResult->fIoPerm = fDtePerm;
2753 return VINF_SUCCESS;
2754 }
2755
2756 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2757 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2758 { /* likely */ }
2759 else
2760 {
2761 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2762 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2763 * I'm just going with I/O page fault. */
2764 LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
2765 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2766 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2767 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2768 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2769 kIoPageFaultType_PteInvalidLvlEncoding);
2770 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2771 }
2772
2773 /* Check permissions bits of the root page table. */
2774 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2775 if ((fAccess & fRootPtePerm) == fAccess)
2776 { /* likely */ }
2777 else
2778 {
2779 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2780 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2781 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2782 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2783 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2784 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2785 }
2786
2787 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2788 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2789 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2790 * table entry every time. Not sure if it's worth optimizing that case now
2791 * or if at all. */
2792
2793 /* The virtual address bits indexing table. */
2794 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2795 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2796 UINT64_C(0x00000000001ff000),
2797 UINT64_C(0x000000003fe00000),
2798 UINT64_C(0x0000007fc0000000),
2799 UINT64_C(0x0000ff8000000000),
2800 UINT64_C(0x01ff000000000000),
2801 UINT64_C(0xfe00000000000000),
2802 UINT64_C(0x0000000000000000) };
2803 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2804 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2805
2806 /* Traverse the I/O page table starting with the page directory in the DTE. */
2807 IOPTENTITY_T PtEntity;
2808 PtEntity.u64 = pDte->au64[0];
2809 for (;;)
2810 {
2811 /* Figure out the system physical address of the page table at the current level. */
2812 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2813
2814 /* Read the page table entity at the current level. */
2815 {
2816 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2817 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2818 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2819 uint64_t const offPte = idxPte << 3;
2820 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2821 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2822 if (RT_FAILURE(rc))
2823 {
2824 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2825 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2826 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2827 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2828 return VERR_IOMMU_IPE_2;
2829 }
2830 }
2831
2832 /* Check present bit. */
2833 if (PtEntity.n.u1Present)
2834 { /* likely */ }
2835 else
2836 {
2837 LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
2838 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2839 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2840 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2841 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2842 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2843 }
2844
2845 /* Check permission bits. */
2846 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2847 if ((fAccess & fPtePerm) == fAccess)
2848 { /* likely */ }
2849 else
2850 {
2851 LogFunc(("Page table entry access denied (uDevId=%#x fAccess=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fAccess, fPtePerm));
2852 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2853 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2854 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2855 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2856 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2857 }
2858
2859 /* If this is a PTE, we're at the final level and we're done. */
2860 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2861 if (uNextLevel == 0)
2862 {
2863 /* The page size of the translation is the default (4K). */
2864 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2865 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2866 pWalkResult->fIoPerm = fPtePerm;
2867 return VINF_SUCCESS;
2868 }
2869 if (uNextLevel == 7)
2870 {
2871 /* The default page size of the translation is overridden. */
2872 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2873 uint8_t cShift = X86_PAGE_4K_SHIFT;
2874 while (GCPhysPte & RT_BIT_64(cShift++))
2875 ;
2876
2877 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2878 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2879 if ( cShift > s_acIovaLevelShifts[uLevel]
2880 && cShift < s_acIovaLevelShifts[uLevel + 1])
2881 {
2882 pWalkResult->GCPhysSpa = GCPhysPte;
2883 pWalkResult->cShift = cShift;
2884 pWalkResult->fIoPerm = fPtePerm;
2885 return VINF_SUCCESS;
2886 }
2887
2888 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2889 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2890 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2891 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2892 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2893 kIoPageFaultType_PteInvalidPageSize);
2894 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2895 }
2896
2897 /* Validate the next level encoding of the PDE. */
2898#if IOMMU_MAX_HOST_PT_LEVEL < 6
2899 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2900 { /* likely */ }
2901 else
2902 {
2903 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2904 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2905 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2906 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2907 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2908 kIoPageFaultType_PteInvalidLvlEncoding);
2909 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2910 }
2911#else
2912 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2913#endif
2914
2915 /* Validate level transition. */
2916 if (uNextLevel < uLevel)
2917 { /* likely */ }
2918 else
2919 {
2920 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2921 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2922 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2923 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2924 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2925 kIoPageFaultType_PteInvalidLvlEncoding);
2926 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2927 }
2928
2929 /* Ensure IOVA bits of skipped levels are zero. */
2930 Assert(uLevel > 0);
2931 uint64_t uIovaSkipMask = 0;
2932 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2933 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2934 if (!(uIova & uIovaSkipMask))
2935 { /* likely */ }
2936 else
2937 {
2938 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2939 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2940 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2941 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2942 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2943 kIoPageFaultType_SkippedLevelIovaNotZero);
2944 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2945 }
2946
2947 /* Continue with traversing the page directory at this level. */
2948 }
2949}
2950
2951
2952/**
2953 * Looks up an I/O virtual address from the device table.
2954 *
2955 * @returns VBox status code.
2956 * @param pDevIns The IOMMU instance data.
2957 * @param uDevId The device ID.
2958 * @param uIova The I/O virtual address to lookup.
2959 * @param cbAccess The size of the access.
2960 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2961 * permissions for the access being made.
2962 * @param enmOp The IOMMU operation being performed.
2963 * @param pGCPhysSpa Where to store the translated system physical address. Only
2964 * valid when translation succeeds and VINF_SUCCESS is
2965 * returned!
2966 *
2967 * @thread Any.
2968 */
2969static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2970 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2971{
2972 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2973
2974 /* Read the device table entry from memory. */
2975 DTE_T Dte;
2976 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2977 if (RT_SUCCESS(rc))
2978 {
2979 /* If the DTE is not valid, addresses are forwarded without translation */
2980 if (Dte.n.u1Valid)
2981 { /* likely */ }
2982 else
2983 {
2984 /** @todo IOMMU: Add to IOLTB cache. */
2985 *pGCPhysSpa = uIova;
2986 return VINF_SUCCESS;
2987 }
2988
2989 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2990 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2991 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2992 if (RT_LIKELY( !fRsvd0
2993 && !fRsvd1))
2994 { /* likely */ }
2995 else
2996 {
2997 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2998 EVT_ILLEGAL_DTE_T Event;
2999 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
3000 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3001 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3002 }
3003
3004 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
3005 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable /** @todo lock or make atomic read? */
3006 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
3007 { /* likely */ }
3008 else
3009 {
3010 /** @todo IOMMU: Add to IOLTB cache. */
3011 *pGCPhysSpa = uIova;
3012 return VINF_SUCCESS;
3013 }
3014
3015 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
3016 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
3017
3018 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
3019 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
3020 uint64_t cbRemaining = cbAccess;
3021 for (;;)
3022 {
3023 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
3024 IOWALKRESULT WalkResult;
3025 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
3026 if (RT_SUCCESS(rc))
3027 {
3028 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
3029
3030 /* Store the translated base address before continuing to check permissions for any more pages. */
3031 if (cbRemaining == cbAccess)
3032 {
3033 uint64_t const offMask = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
3034 uint64_t const offSpa = uIova & offMask;
3035 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
3036 }
3037
3038 /* If the access exceeds the page size, check permissions for the subsequent page. */
3039 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
3040 if (cbRemaining > cbPhysPage - offIova)
3041 {
3042 cbRemaining -= (cbPhysPage - offIova);
3043 uBaseIova += cbPhysPage; /** @todo r=ramshankar: Should we mask the offset based on page size here? */
3044 offIova = 0;
3045 }
3046 else
3047 break;
3048 }
3049 else
3050 {
3051 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
3052 uBaseIova, fAccess, rc));
3053 *pGCPhysSpa = NIL_RTGCPHYS;
3054 return rc;
3055 }
3056 }
3057
3058 return rc;
3059 }
3060
3061 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3062 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3063}
3064
3065
3066/**
3067 * Memory access transaction from a device.
3068 *
3069 * @returns VBox status code.
3070 * @param pDevIns The IOMMU device instance.
3071 * @param uDevId The device ID (bus, device, function).
3072 * @param uIova The I/O virtual address being accessed.
3073 * @param cbAccess The number of bytes being accessed.
3074 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3075 * @param pGCPhysSpa Where to store the translated system physical address.
3076 *
3077 * @thread Any.
3078 */
3079static DECLCALLBACK(int) iommuAmdDeviceMemAccess(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
3080 uint32_t fFlags, PRTGCPHYS pGCPhysSpa)
3081{
3082 /* Validate. */
3083 AssertPtr(pDevIns);
3084 AssertPtr(pGCPhysSpa);
3085 Assert(cbAccess > 0);
3086 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3087
3088 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3089 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3090 if (Ctrl.n.u1IommuEn)
3091 {
3092 IOMMUOP enmOp;
3093 uint8_t fAccess;
3094 if (fFlags & PDMIOMMU_MEM_F_READ)
3095 {
3096 enmOp = IOMMUOP_MEM_READ;
3097 fAccess = IOMMU_IO_PERM_READ;
3098 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
3099 }
3100 else
3101 {
3102 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
3103 enmOp = IOMMUOP_MEM_WRITE;
3104 fAccess = IOMMU_IO_PERM_WRITE;
3105 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
3106 }
3107
3108#ifdef LOG_ENABLED
3109 static const char * const s_apszAccess[] = { "none", "read", "write" };
3110 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
3111 const char *pszAccess = s_apszAccess[fAccess];
3112 LogFlowFunc(("uDevId=%#x uIova=%#RX64 szAccess=%s cbAccess=%zu\n", uDevId, uIova, pszAccess, cbAccess));
3113#endif
3114
3115 /** @todo IOMMU: IOTLB cache lookup. */
3116
3117 /* Lookup the IOVA from the device table. */
3118 int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbAccess, fAccess, enmOp, pGCPhysSpa);
3119 if (RT_SUCCESS(rc))
3120 { /* likely */ }
3121 else
3122 LogFunc(("DTE lookup failed! uDevId=%#x uIova=%#RX64 fAccess=%s cbAccess=%zu rc=%Rrc\n", uDevId, uIova, fAccess,
3123 cbAccess, rc));
3124 return rc;
3125 }
3126
3127 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3128 *pGCPhysSpa = uIova;
3129 return VINF_SUCCESS;
3130}
3131
3132
3133/**
3134 * Memory access bulk (one or more 4K pages) request from a device.
3135 *
3136 * @returns VBox status code.
3137 * @param pDevIns The IOMMU device instance.
3138 * @param uDevId The device ID (bus, device, function).
3139 * @param cIovas The number of addresses being accessed.
3140 * @param pauIovas The I/O virtual addresses for each page being accessed.
3141 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3142 * @param paGCPhysSpa Where to store the translated physical addresses.
3143 *
3144 * @thread Any.
3145 */
3146static DECLCALLBACK(int) iommuAmdDeviceMemBulkAccess(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas,
3147 uint64_t const *pauIovas, uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
3148{
3149 /* Validate. */
3150 AssertPtr(pDevIns);
3151 Assert(cIovas > 0);
3152 AssertPtr(pauIovas);
3153 AssertPtr(paGCPhysSpa);
3154 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3155
3156 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3157 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3158 if (Ctrl.n.u1IommuEn)
3159 {
3160 IOMMUOP enmOp;
3161 uint8_t fAccess;
3162 if (fFlags & PDMIOMMU_MEM_F_READ)
3163 {
3164 enmOp = IOMMUOP_MEM_READ;
3165 fAccess = IOMMU_IO_PERM_READ;
3166 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
3167 }
3168 else
3169 {
3170 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
3171 enmOp = IOMMUOP_MEM_WRITE;
3172 fAccess = IOMMU_IO_PERM_WRITE;
3173 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
3174 }
3175
3176#ifdef LOG_ENABLED
3177 static const char * const s_apszAccess[] = { "none", "read", "write" };
3178 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
3179 const char *pszAccess = s_apszAccess[fAccess];
3180 LogFlowFunc(("uDevId=%#x cIovas=%zu szAccess=%s\n", uDevId, cIovas, pszAccess));
3181#endif
3182
3183 /** @todo IOMMU: IOTLB cache lookup. */
3184
3185 /* Lookup each IOVA from the device table. */
3186 for (size_t i = 0; i < cIovas; i++)
3187 {
3188 int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, pauIovas[i], X86_PAGE_SIZE, fAccess, enmOp, &paGCPhysSpa[i]);
3189 if (RT_SUCCESS(rc))
3190 { /* likely */ }
3191 else
3192 {
3193 LogFunc(("Failed! uDevId=%#x uIova=%#RX64 fAccess=%u rc=%Rrc\n", uDevId, pauIovas[i], fAccess, rc));
3194 return rc;
3195 }
3196 }
3197 }
3198 else
3199 {
3200 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3201 for (size_t i = 0; i < cIovas; i++)
3202 paGCPhysSpa[i] = pauIovas[i];
3203 }
3204
3205 return VINF_SUCCESS;
3206}
3207
3208
3209
3210/**
3211 * Reads an interrupt remapping table entry from guest memory given its DTE.
3212 *
3213 * @returns VBox status code.
3214 * @param pDevIns The IOMMU device instance.
3215 * @param uDevId The device ID.
3216 * @param pDte The device table entry.
3217 * @param GCPhysIn The source MSI address.
3218 * @param uDataIn The source MSI data.
3219 * @param enmOp The IOMMU operation being performed.
3220 * @param pIrte Where to store the interrupt remapping table entry.
3221 *
3222 * @thread Any.
3223 */
3224static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
3225 IOMMUOP enmOp, PIRTE_T pIrte)
3226{
3227 /* Ensure the IRTE length is valid. */
3228 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
3229
3230 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
3231 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
3232 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
3233 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
3234
3235 /* Ensure the IRTE falls completely within the interrupt table. */
3236 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
3237 { /* likely */ }
3238 else
3239 {
3240 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
3241 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
3242
3243 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3244 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
3245 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3246 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3247 kIoPageFaultType_IrteAddrInvalid);
3248 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3249 }
3250
3251 /* Read the IRTE from memory. */
3252 Assert(!(GCPhysIrte & 3));
3253 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
3254 if (RT_SUCCESS(rc))
3255 return VINF_SUCCESS;
3256
3257 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
3258 * situation. Is it an I/O page fault or a device table hardware error?
3259 * There's no interrupt table hardware error event, but it's unclear what
3260 * we should do here. */
3261 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
3262 return VERR_IOMMU_IPE_4;
3263}
3264
3265
3266/**
3267 * Remaps the interrupt using the interrupt remapping table.
3268 *
3269 * @returns VBox status code.
3270 * @param pDevIns The IOMMU instance data.
3271 * @param uDevId The device ID.
3272 * @param pDte The device table entry.
3273 * @param enmOp The IOMMU operation being performed.
3274 * @param pMsiIn The source MSI.
3275 * @param pMsiOut Where to store the remapped MSI.
3276 *
3277 * @thread Any.
3278 */
3279static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
3280 PMSIMSG pMsiOut)
3281{
3282 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
3283
3284 IRTE_T Irte;
3285 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
3286 if (RT_SUCCESS(rc))
3287 {
3288 if (Irte.n.u1RemapEnable)
3289 {
3290 if (!Irte.n.u1GuestMode)
3291 {
3292 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
3293 {
3294 /* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
3295 pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
3296 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
3297 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
3298
3299 /* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
3300 pMsiOut->Data.u32 = pMsiIn->Data.u32;
3301 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
3302 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
3303
3304 return VINF_SUCCESS;
3305 }
3306
3307 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3308 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3309 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3310 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3311 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
3312 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3313 }
3314
3315 LogFunc(("Guest mode not supported -> IOPF\n"));
3316 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3317 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3318 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3319 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3320 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3321 }
3322
3323 LogFunc(("Remapping disabled -> IOPF\n"));
3324 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3325 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3326 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3327 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3328 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3329 }
3330
3331 return rc;
3332}
3333
3334
3335/**
3336 * Looks up an MSI interrupt from the interrupt remapping table.
3337 *
3338 * @returns VBox status code.
3339 * @param pDevIns The IOMMU instance data.
3340 * @param uDevId The device ID.
3341 * @param enmOp The IOMMU operation being performed.
3342 * @param pMsiIn The source MSI.
3343 * @param pMsiOut Where to store the remapped MSI.
3344 *
3345 * @thread Any.
3346 */
3347static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3348{
3349 /* Read the device table entry from memory. */
3350 LogFlowFunc(("uDevId=%#x enmOp=%u\n", uDevId, enmOp));
3351
3352 DTE_T Dte;
3353 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3354 if (RT_SUCCESS(rc))
3355 {
3356 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
3357 if (Dte.n.u1IntrMapValid)
3358 {
3359 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3360 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3361 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3362 if (RT_LIKELY( !fRsvd0
3363 && !fRsvd1))
3364 { /* likely */ }
3365 else
3366 {
3367 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3368 fRsvd1));
3369 EVT_ILLEGAL_DTE_T Event;
3370 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3371 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3372 return VERR_IOMMU_INTR_REMAP_FAILED;
3373 }
3374
3375 /*
3376 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3377 * that's connected through HyperTransport it might be possible; but for us, it
3378 * doesn't seem we need to specially handle these pins.
3379 */
3380
3381 /*
3382 * Validate the MSI source address.
3383 *
3384 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3385 * CPU is concerned, the MSI region is fixed and we must ensure no other device
3386 * claims the region as I/O space.
3387 *
3388 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3389 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3390 * See Intel spec. 10.11.1 "Message Address Register Format".
3391 */
3392 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3393 {
3394 /*
3395 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3396 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3397 */
3398 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3399 bool fPassThru = false;
3400 switch (u8DeliveryMode)
3401 {
3402 case VBOX_MSI_DELIVERY_MODE_FIXED:
3403 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3404 {
3405 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3406 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3407 {
3408 LogFunc(("IntCtl=0: Target aborting fixed/arbitrated interrupt -> Target abort\n"));
3409 iommuAmdSetPciTargetAbort(pDevIns);
3410 return VERR_IOMMU_INTR_REMAP_DENIED;
3411 }
3412
3413 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3414 {
3415 fPassThru = true;
3416 break;
3417 }
3418
3419 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3420 {
3421 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3422 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3423 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3424 {
3425 /*
3426 * We don't support guest interrupt remapping yet. When we do, we'll need to
3427 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3428 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3429 * already reads the control register, add that as a parameter when we eventually
3430 * support guest interrupt remapping. For now, just assert.
3431 */
3432 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3433 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3434 NOREF(pThis);
3435
3436 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3437 }
3438
3439 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3440 EVT_ILLEGAL_DTE_T Event;
3441 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3442 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3443 return VERR_IOMMU_INTR_REMAP_FAILED;
3444 }
3445
3446 /* Paranoia. */
3447 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD);
3448
3449 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3450
3451 EVT_ILLEGAL_DTE_T Event;
3452 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3453 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3454 return VERR_IOMMU_INTR_REMAP_FAILED;
3455 }
3456
3457 /* SMIs are passed through unmapped. We don't implement SMI filters. */
3458 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3459 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3460 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3461 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3462 default:
3463 {
3464 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3465 iommuAmdSetPciTargetAbort(pDevIns);
3466 return VERR_IOMMU_INTR_REMAP_FAILED;
3467 }
3468 }
3469
3470 if (fPassThru)
3471 {
3472 *pMsiOut = *pMsiIn;
3473 return VINF_SUCCESS;
3474 }
3475
3476 iommuAmdSetPciTargetAbort(pDevIns);
3477 return VERR_IOMMU_INTR_REMAP_DENIED;
3478 }
3479 else
3480 {
3481 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3482 return VERR_IOMMU_INTR_REMAP_FAILED;
3483 }
3484 }
3485 else
3486 {
3487 /** @todo IOMMU: Add to interrupt remapping cache. */
3488 LogFlowFunc(("DTE interrupt map not valid\n"));
3489 *pMsiOut = *pMsiIn;
3490 return VINF_SUCCESS;
3491 }
3492 }
3493
3494 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3495 return VERR_IOMMU_INTR_REMAP_FAILED;
3496}
3497
3498
3499/**
3500 * Interrupt remap request from a device.
3501 *
3502 * @returns VBox status code.
3503 * @param pDevIns The IOMMU device instance.
3504 * @param uDevId The device ID (bus, device, function).
3505 * @param pMsiIn The source MSI.
3506 * @param pMsiOut Where to store the remapped MSI.
3507 */
3508static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3509{
3510 /* Validate. */
3511 Assert(pDevIns);
3512 Assert(pMsiIn);
3513 Assert(pMsiOut);
3514
3515 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3516
3517 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3518 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3519 if (Ctrl.n.u1IommuEn)
3520 {
3521 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3522 LogFlowFunc(("uDevId=%#x\n", uDevId));
3523 /** @todo Cache? */
3524
3525 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3526 }
3527
3528 *pMsiOut = *pMsiIn;
3529 return VINF_SUCCESS;
3530}
3531
3532
3533/**
3534 * @callback_method_impl{FNIOMMMIONEWWRITE}
3535 */
3536static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3537{
3538 NOREF(pvUser);
3539 Assert(cb == 4 || cb == 8);
3540 Assert(!(off & (cb - 1)));
3541
3542 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3543 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3544
3545 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
3546 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
3547}
3548
3549
3550/**
3551 * @callback_method_impl{FNIOMMMIONEWREAD}
3552 */
3553static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3554{
3555 NOREF(pvUser);
3556 Assert(cb == 4 || cb == 8);
3557 Assert(!(off & (cb - 1)));
3558
3559 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3560 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3561
3562 uint64_t uResult;
3563 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
3564 if (cb == 8)
3565 *(uint64_t *)pv = uResult;
3566 else
3567 *(uint32_t *)pv = (uint32_t)uResult;
3568
3569 return rcStrict;
3570}
3571
3572# ifdef IN_RING3
3573
3574/**
3575 * Processes an IOMMU command.
3576 *
3577 * @returns VBox status code.
3578 * @param pDevIns The IOMMU device instance.
3579 * @param pCmd The command to process.
3580 * @param GCPhysCmd The system physical address of the command.
3581 * @param pEvtError Where to store the error event in case of failures.
3582 *
3583 * @thread Command thread.
3584 */
3585static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3586{
3587 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3588
3589 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3590 STAM_COUNTER_INC(&pThis->StatCmd);
3591
3592 uint8_t const bCmd = pCmd->n.u4Opcode;
3593 switch (bCmd)
3594 {
3595 case IOMMU_CMD_COMPLETION_WAIT:
3596 {
3597 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3598
3599 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3600 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
3601
3602 /* Validate reserved bits in the command. */
3603 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3604 {
3605 /* If Completion Store is requested, write the StoreData to the specified address. */
3606 if (pCmdComWait->n.u1Store)
3607 {
3608 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3609 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3610 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3611 if (RT_FAILURE(rc))
3612 {
3613 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3614 GCPhysStore, rc));
3615 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3616 return VERR_IOMMU_CMD_HW_ERROR;
3617 }
3618 }
3619
3620 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3621 if (pCmdComWait->n.u1Interrupt)
3622 {
3623 IOMMU_LOCK(pDevIns);
3624 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3625 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3626 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3627 IOMMU_UNLOCK(pDevIns);
3628
3629 if (fRaiseInt)
3630 iommuAmdRaiseMsiInterrupt(pDevIns);
3631 }
3632 return VINF_SUCCESS;
3633 }
3634 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3635 return VERR_IOMMU_CMD_INVALID_FORMAT;
3636 }
3637
3638 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3639 {
3640 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3641 * then. */
3642 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3643 return VINF_SUCCESS;
3644 }
3645
3646 case IOMMU_CMD_INV_IOMMU_PAGES:
3647 {
3648 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3649 * then. */
3650 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3651 return VINF_SUCCESS;
3652 }
3653
3654 case IOMMU_CMD_INV_IOTLB_PAGES:
3655 {
3656 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3657
3658 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3659 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3660 {
3661 /** @todo IOMMU: Implement remote IOTLB invalidation. */
3662 return VERR_NOT_IMPLEMENTED;
3663 }
3664 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3665 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3666 }
3667
3668 case IOMMU_CMD_INV_INTR_TABLE:
3669 {
3670 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3671 * then. */
3672 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3673 return VINF_SUCCESS;
3674 }
3675
3676 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3677 {
3678 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3679 if (pThis->ExtFeat.n.u1PrefetchSup)
3680 {
3681 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
3682 return VINF_SUCCESS;
3683 }
3684 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3685 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3686 }
3687
3688 case IOMMU_CMD_COMPLETE_PPR_REQ:
3689 {
3690 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3691
3692 /* We don't support PPR requests yet. */
3693 Assert(!pThis->ExtFeat.n.u1PprSup);
3694 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3695 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3696 }
3697
3698 case IOMMU_CMD_INV_IOMMU_ALL:
3699 {
3700 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3701
3702 if (pThis->ExtFeat.n.u1InvAllSup)
3703 {
3704 /** @todo IOMMU: Invalidate all. Pretend success until then. */
3705 return VINF_SUCCESS;
3706 }
3707 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3708 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3709 }
3710 }
3711
3712 STAM_COUNTER_DEC(&pThis->StatCmd);
3713 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3714 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3715 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3716}
3717
3718
3719/**
3720 * The IOMMU command thread.
3721 *
3722 * @returns VBox status code.
3723 * @param pDevIns The IOMMU device instance.
3724 * @param pThread The command thread.
3725 */
3726static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3727{
3728 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3729
3730 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3731 return VINF_SUCCESS;
3732
3733 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3734 {
3735 /*
3736 * Sleep perpetually until we are woken up to process commands.
3737 */
3738 {
3739 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3740 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3741 if (!fSignaled)
3742 {
3743 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3744 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3745 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3746 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3747 break;
3748 Log5Func(("Woken up with rc=%Rrc\n", rc));
3749 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3750 }
3751 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3752 }
3753
3754 /*
3755 * Fetch and process IOMMU commands.
3756 */
3757 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
3758 * at a time) and is expensive due to calls to PGM for fetching guest memory.
3759 * We could optimize by fetching a bunch of commands at a time reducing
3760 * number of calls to PGM. In the longer run we could lock the memory and
3761 * mappings and accessing them directly. */
3762 IOMMU_LOCK(pDevIns);
3763
3764 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3765 if (Status.n.u1CmdBufRunning)
3766 {
3767 /* Get the offset we need to read the command from memory (circular buffer offset). */
3768 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3769 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3770 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3771 Assert(offHead < cbCmdBuf);
3772 while (offHead != pThis->CmdBufTailPtr.n.off)
3773 {
3774 /* Read the command from memory. */
3775 CMD_GENERIC_T Cmd;
3776 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3777 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3778 if (RT_SUCCESS(rc))
3779 {
3780 /* Increment the command buffer head pointer. */
3781 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3782 pThis->CmdBufHeadPtr.n.off = offHead;
3783
3784 /* Process the fetched command. */
3785 EVT_GENERIC_T EvtError;
3786 IOMMU_UNLOCK(pDevIns);
3787 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3788 IOMMU_LOCK(pDevIns);
3789 if (RT_FAILURE(rc))
3790 {
3791 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3792 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3793 {
3794 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3795 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3796 }
3797 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3798 {
3799 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3800 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", Cmd.n.u4Opcode));
3801 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3802 }
3803 break;
3804 }
3805 }
3806 else
3807 {
3808 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmd, rc));
3809 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3810 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3811 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3812 break;
3813 }
3814 }
3815 }
3816
3817 IOMMU_UNLOCK(pDevIns);
3818 }
3819
3820 LogFlowFunc(("Command thread terminating\n"));
3821 return VINF_SUCCESS;
3822}
3823
3824
3825/**
3826 * Wakes up the command thread so it can respond to a state change.
3827 *
3828 * @returns VBox status code.
3829 * @param pDevIns The IOMMU device instance.
3830 * @param pThread The command thread.
3831 */
3832static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3833{
3834 RT_NOREF(pThread);
3835 LogFlowFunc(("\n"));
3836 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3837 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3838}
3839
3840
3841/**
3842 * @callback_method_impl{FNPCICONFIGREAD}
3843 */
3844static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3845 unsigned cb, uint32_t *pu32Value)
3846{
3847 /** @todo IOMMU: PCI config read stat counter. */
3848 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3849 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3850 return rcStrict;
3851}
3852
3853
3854/**
3855 * @callback_method_impl{FNPCICONFIGWRITE}
3856 */
3857static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3858 unsigned cb, uint32_t u32Value)
3859{
3860 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3861
3862 /*
3863 * Discard writes to read-only registers that are specific to the IOMMU.
3864 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3865 * See PCI spec. 6.1. "Configuration Space Organization".
3866 */
3867 switch (uAddress)
3868 {
3869 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3870 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3871 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3872 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3873 {
3874 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3875 return VINF_SUCCESS;
3876 }
3877 }
3878
3879 IOMMU_LOCK(pDevIns);
3880
3881 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3882 switch (uAddress)
3883 {
3884 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3885 {
3886 if (pThis->IommuBar.n.u1Enable)
3887 {
3888 rcStrict = VINF_SUCCESS;
3889 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3890 break;
3891 }
3892
3893 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3894 if (pThis->IommuBar.n.u1Enable)
3895 {
3896 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3897 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3898 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3899 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
3900
3901 /* If the MMIO region is already mapped at the specified address, we're done. */
3902 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
3903 if (GCPhysMmioBasePrev == GCPhysMmioBase)
3904 {
3905 rcStrict = VINF_SUCCESS;
3906 break;
3907 }
3908
3909 /* Unmap the previous MMIO region (which is at a different address). */
3910 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
3911 {
3912 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
3913 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3914 if (RT_FAILURE(rcStrict))
3915 {
3916 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3917 break;
3918 }
3919 }
3920
3921 /* Map the newly specified MMIO region. */
3922 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
3923 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3924 if (RT_FAILURE(rcStrict))
3925 {
3926 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3927 break;
3928 }
3929 }
3930 else
3931 rcStrict = VINF_SUCCESS;
3932 break;
3933 }
3934
3935 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3936 {
3937 if (!pThis->IommuBar.n.u1Enable)
3938 pThis->IommuBar.au32[1] = u32Value;
3939 else
3940 {
3941 rcStrict = VINF_SUCCESS;
3942 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3943 }
3944 break;
3945 }
3946
3947 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3948 {
3949 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3950 RT_FALL_THRU();
3951 }
3952 default:
3953 {
3954 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3955 break;
3956 }
3957 }
3958
3959 IOMMU_UNLOCK(pDevIns);
3960
3961 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
3962 return rcStrict;
3963}
3964
3965
3966/**
3967 * @callback_method_impl{FNDBGFHANDLERDEV}
3968 */
3969static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3970{
3971 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3972 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3973 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3974
3975 bool fVerbose;
3976 if ( pszArgs
3977 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3978 fVerbose = true;
3979 else
3980 fVerbose = false;
3981
3982 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3983 /* Device Table Base Addresses (all segments). */
3984 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3985 {
3986 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3987 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3988 if (fVerbose)
3989 {
3990 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3991 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
3992 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3993 }
3994 }
3995 /* Command Buffer Base Address Register. */
3996 {
3997 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3998 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3999 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4000 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4001 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
4002 if (fVerbose)
4003 {
4004 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
4005 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4006 cEntries, cbBuffer);
4007 }
4008 }
4009 /* Event Log Base Address Register. */
4010 {
4011 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
4012 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
4013 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4014 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4015 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
4016 if (fVerbose)
4017 {
4018 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4019 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4020 cEntries, cbBuffer);
4021 }
4022 }
4023 /* IOMMU Control Register. */
4024 {
4025 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
4026 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
4027 if (fVerbose)
4028 {
4029 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
4030 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
4031 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
4032 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4033 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4034 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
4035 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
4036 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
4037 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
4038 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
4039 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
4040 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
4041 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
4042 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
4043 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
4044 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
4045 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
4046 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
4047 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
4048 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
4049 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
4050 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
4051 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
4052 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
4053 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
4054 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
4055 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
4056 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
4057 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
4058 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
4059 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
4060 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
4061 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
4062 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
4063 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
4064 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
4065 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
4066 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
4067 }
4068 }
4069 /* Exclusion Base Address Register. */
4070 {
4071 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
4072 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
4073 if (fVerbose)
4074 {
4075 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
4076 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
4077 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
4078 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
4079 }
4080 }
4081 /* Exclusion Range Limit Register. */
4082 {
4083 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
4084 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
4085 if (fVerbose)
4086 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
4087 }
4088 /* Extended Feature Register. */
4089 {
4090 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
4091 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
4092 if (fVerbose)
4093 {
4094 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
4095 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
4096 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
4097 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
4098 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
4099 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
4100 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
4101 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
4102 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
4103 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
4104 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
4105 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
4106 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
4107 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
4108 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
4109 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
4110 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
4111 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
4112 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
4113 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
4114 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
4115 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
4116 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
4117 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
4118 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
4119 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
4120 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
4121 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
4122 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
4123 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
4124 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
4125 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
4126 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
4127 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
4128 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
4129 }
4130 }
4131 /* PPR Log Base Address Register. */
4132 {
4133 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
4134 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
4135 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4136 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4137 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
4138 if (fVerbose)
4139 {
4140 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4141 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4142 cEntries, cbBuffer);
4143 }
4144 }
4145 /* Hardware Event (Hi) Register. */
4146 {
4147 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4148 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4149 if (fVerbose)
4150 {
4151 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4152 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4153 }
4154 }
4155 /* Hardware Event (Lo) Register. */
4156 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4157 /* Hardware Event Status. */
4158 {
4159 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4160 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4161 if (fVerbose)
4162 {
4163 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4164 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4165 }
4166 }
4167 /* Guest Virtual-APIC Log Base Address Register. */
4168 {
4169 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4170 uint8_t const uEncodedLen = GALogBar.n.u4Len;
4171 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4172 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4173 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4174 if (fVerbose)
4175 {
4176 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4177 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4178 cEntries, cbBuffer);
4179 }
4180 }
4181 /* Guest Virtual-APIC Log Tail Address Register. */
4182 {
4183 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4184 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4185 if (fVerbose)
4186 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4187 }
4188 /* PPR Log B Base Address Register. */
4189 {
4190 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4191 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4192 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4193 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4194 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4195 if (fVerbose)
4196 {
4197 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4198 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4199 cEntries, cbBuffer);
4200 }
4201 }
4202 /* Event Log B Base Address Register. */
4203 {
4204 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4205 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4206 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4207 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4208 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4209 if (fVerbose)
4210 {
4211 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4212 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4213 cEntries, cbBuffer);
4214 }
4215 }
4216 /* Device-Specific Feature Extension Register. */
4217 {
4218 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4219 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4220 if (fVerbose)
4221 {
4222 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4223 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4224 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4225 }
4226 }
4227 /* Device-Specific Control Extension Register. */
4228 {
4229 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4230 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4231 if (fVerbose)
4232 {
4233 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4234 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4235 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4236 }
4237 }
4238 /* Device-Specific Status Extension Register. */
4239 {
4240 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4241 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
4242 if (fVerbose)
4243 {
4244 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4245 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4246 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4247 }
4248 }
4249 /* Miscellaneous Information Register (Lo and Hi). */
4250 {
4251 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
4252 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
4253 if (fVerbose)
4254 {
4255 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
4256 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
4257 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
4258 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
4259 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
4260 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
4261 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
4262 }
4263 }
4264 /* MSI Capability Header. */
4265 {
4266 MSI_CAP_HDR_T MsiCapHdr;
4267 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4268 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4269 if (fVerbose)
4270 {
4271 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4272 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4273 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4274 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4275 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4276 }
4277 }
4278 /* MSI Address Register (Lo and Hi). */
4279 {
4280 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4281 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4282 MSIADDR MsiAddr;
4283 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4284 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4285 if (fVerbose)
4286 {
4287 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
4288 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
4289 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
4290 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
4291 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
4292 }
4293 }
4294 /* MSI Data. */
4295 {
4296 MSIDATA MsiData;
4297 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4298 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4299 if (fVerbose)
4300 {
4301 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
4302 MsiData.n.u8Vector);
4303 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
4304 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
4305 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4306 "level" : "edge");
4307 }
4308 }
4309 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4310 {
4311 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4312 MsiMapCapHdr.u32 = 0;
4313 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4314 if (fVerbose)
4315 {
4316 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4317 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4318 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4319 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4320 }
4321 }
4322 /* Performance Optimization Control Register. */
4323 {
4324 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4325 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4326 if (fVerbose)
4327 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4328 }
4329 /* XT (x2APIC) General Interrupt Control Register. */
4330 {
4331 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4332 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4333 if (fVerbose)
4334 {
4335 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4336 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4337 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4338 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4339 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4340 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4341 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4342 }
4343 }
4344 /* XT (x2APIC) PPR Interrupt Control Register. */
4345 {
4346 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4347 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4348 if (fVerbose)
4349 {
4350 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4351 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4352 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4353 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4354 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4355 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4356 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4357 }
4358 }
4359 /* XT (X2APIC) GA Log Interrupt Control Register. */
4360 {
4361 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4362 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4363 if (fVerbose)
4364 {
4365 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4366 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4367 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4368 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4369 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4370 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4371 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4372 }
4373 }
4374 /* MARC Registers. */
4375 {
4376 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4377 {
4378 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4379 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4380 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4381
4382 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4383 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4384 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4385 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4386
4387 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4388 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4389 }
4390 }
4391 /* Reserved Register. */
4392 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4393 /* Command Buffer Head Pointer Register. */
4394 {
4395 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4396 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4397 CmdBufHeadPtr.n.off);
4398 }
4399 /* Command Buffer Tail Pointer Register. */
4400 {
4401 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4402 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4403 CmdBufTailPtr.n.off);
4404 }
4405 /* Event Log Head Pointer Register. */
4406 {
4407 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4408 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4409 EvtLogHeadPtr.n.off);
4410 }
4411 /* Event Log Tail Pointer Register. */
4412 {
4413 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4414 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4415 EvtLogTailPtr.n.off);
4416 }
4417 /* Status Register. */
4418 {
4419 IOMMU_STATUS_T const Status = pThis->Status;
4420 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4421 if (fVerbose)
4422 {
4423 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4424 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4425 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4426 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4427 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4428 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4429 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4430 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4431 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4432 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4433 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4434 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4435 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4436 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4437 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4438 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4439 }
4440 }
4441 /* PPR Log Head Pointer. */
4442 {
4443 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4444 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4445 PprLogHeadPtr.n.off);
4446 }
4447 /* PPR Log Tail Pointer. */
4448 {
4449 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4450 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4451 PprLogTailPtr.n.off);
4452 }
4453 /* Guest Virtual-APIC Log Head Pointer. */
4454 {
4455 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4456 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4457 GALogHeadPtr.n.u12GALogPtr);
4458 }
4459 /* Guest Virtual-APIC Log Tail Pointer. */
4460 {
4461 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4462 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4463 GALogTailPtr.n.u12GALogPtr);
4464 }
4465 /* PPR Log B Head Pointer. */
4466 {
4467 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4468 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4469 PprLogBHeadPtr.n.off);
4470 }
4471 /* PPR Log B Tail Pointer. */
4472 {
4473 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4474 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4475 PprLogBTailPtr.n.off);
4476 }
4477 /* Event Log B Head Pointer. */
4478 {
4479 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4480 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4481 EvtLogBHeadPtr.n.off);
4482 }
4483 /* Event Log B Tail Pointer. */
4484 {
4485 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4486 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4487 EvtLogBTailPtr.n.off);
4488 }
4489 /* PPR Log Auto Response Register. */
4490 {
4491 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4492 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4493 if (fVerbose)
4494 {
4495 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4496 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4497 }
4498 }
4499 /* PPR Log Overflow Early Warning Indicator Register. */
4500 {
4501 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4502 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4503 if (fVerbose)
4504 {
4505 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4506 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4507 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4508 }
4509 }
4510 /* PPR Log Overflow Early Warning Indicator Register. */
4511 {
4512 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4513 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4514 if (fVerbose)
4515 {
4516 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4517 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4518 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4519 }
4520 }
4521}
4522
4523
4524/**
4525 * Dumps the DTE via the info callback helper.
4526 *
4527 * @param pHlp The info helper.
4528 * @param pDte The device table entry.
4529 * @param pszPrefix The string prefix.
4530 */
4531static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4532{
4533 AssertReturnVoid(pHlp);
4534 AssertReturnVoid(pDte);
4535 AssertReturnVoid(pszPrefix);
4536
4537 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4538 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4539 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4540 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4541 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4542 pDte->n.u40PageTableRootPtrLo << 12);
4543 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4544 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4545 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4546 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4547 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4548 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4549 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4550 (pDte->n.u21GstCr3TableRootPtrHi << 31)
4551 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
4552 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
4553 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4554 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4555 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4556 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4557 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4558 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4559 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4560 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4561 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4562 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4563 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4564 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4565 pHlp->pfnPrintf(pHlp, "\n");
4566
4567 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4568 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4569 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4570 {
4571 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4572 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4573 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4574 cbIntrTable);
4575 }
4576 else
4577 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4578 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4579 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4580 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4581 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4582 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4583 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4584 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4585 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4586 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4587 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4588 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4589 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4590 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4591 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4592 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4593 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4594}
4595
4596
4597/**
4598 * @callback_method_impl{FNDBGFHANDLERDEV}
4599 */
4600static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4601{
4602 if (pszArgs)
4603 {
4604 uint16_t uDevId = 0;
4605 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4606 if (RT_SUCCESS(rc))
4607 {
4608 DTE_T Dte;
4609 rc = iommuAmdReadDte(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4610 if (RT_SUCCESS(rc))
4611 {
4612 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4613 return;
4614 }
4615
4616 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4617 }
4618 else
4619 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4620 }
4621 else
4622 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4623}
4624
4625
4626#if 0
4627/**
4628 * @callback_method_impl{FNDBGFHANDLERDEV}
4629 */
4630static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4631{
4632 RT_NOREF(pszArgs);
4633
4634 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4635 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4636 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4637
4638 uint8_t cTables = 0;
4639 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4640 {
4641 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4642 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4643 if (GCPhysDevTab)
4644 ++cTables;
4645 }
4646
4647 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4648 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4649 if (!cTables)
4650 return;
4651
4652 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4653 {
4654 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4655 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4656 if (GCPhysDevTab)
4657 {
4658 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4659 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4660 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4661
4662 void *pvDevTab = RTMemAllocZ(cbDevTab);
4663 if (RT_LIKELY(pvDevTab))
4664 {
4665 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4666 if (RT_SUCCESS(rc))
4667 {
4668 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4669 {
4670 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
4671 if ( pDte->n.u1Valid
4672 || pDte->n.u1IntrMapValid)
4673 {
4674 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4675 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4676 }
4677 }
4678 pHlp->pfnPrintf(pHlp, "\n");
4679 }
4680 else
4681 {
4682 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4683 cbDevTab, rc);
4684 }
4685
4686 RTMemFree(pvDevTab);
4687 }
4688 else
4689 {
4690 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4691 return;
4692 }
4693 }
4694 }
4695}
4696#endif
4697
4698/**
4699 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4700 */
4701static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4702{
4703 /** @todo IOMMU: Save state. */
4704 RT_NOREF2(pDevIns, pSSM);
4705 LogFlowFunc(("\n"));
4706 return VERR_NOT_IMPLEMENTED;
4707}
4708
4709
4710/**
4711 * @callback_method_impl{FNSSMDEVLOADEXEC}
4712 */
4713static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4714{
4715 /** @todo IOMMU: Load state. */
4716 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4717 LogFlowFunc(("\n"));
4718 return VERR_NOT_IMPLEMENTED;
4719}
4720
4721
4722/**
4723 * @interface_method_impl{PDMDEVREG,pfnReset}
4724 */
4725static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4726{
4727 /*
4728 * Resets read-write portion of the IOMMU state.
4729 *
4730 * NOTE! State not initialized here is expected to be initialized during
4731 * device construction and remain read-only through the lifetime of the VM.
4732 */
4733 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4734 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4735 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4736
4737 IOMMU_LOCK_NORET(pDevIns);
4738
4739 LogFlowFunc(("\n"));
4740
4741 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4742
4743 pThis->CmdBufBaseAddr.u64 = 0;
4744 pThis->CmdBufBaseAddr.n.u4Len = 8;
4745
4746 pThis->EvtLogBaseAddr.u64 = 0;
4747 pThis->EvtLogBaseAddr.n.u4Len = 8;
4748
4749 pThis->Ctrl.u64 = 0;
4750 pThis->Ctrl.n.u1Coherent = 1;
4751 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4752
4753 pThis->ExclRangeBaseAddr.u64 = 0;
4754 pThis->ExclRangeLimit.u64 = 0;
4755
4756 pThis->PprLogBaseAddr.u64 = 0;
4757 pThis->PprLogBaseAddr.n.u4Len = 8;
4758
4759 pThis->HwEvtHi.u64 = 0;
4760 pThis->HwEvtLo = 0;
4761 pThis->HwEvtStatus.u64 = 0;
4762
4763 pThis->GALogBaseAddr.u64 = 0;
4764 pThis->GALogBaseAddr.n.u4Len = 8;
4765 pThis->GALogTailAddr.u64 = 0;
4766
4767 pThis->PprLogBBaseAddr.u64 = 0;
4768 pThis->PprLogBBaseAddr.n.u4Len = 8;
4769
4770 pThis->EvtLogBBaseAddr.u64 = 0;
4771 pThis->EvtLogBBaseAddr.n.u4Len = 8;
4772
4773 pThis->PerfOptCtrl.u32 = 0;
4774
4775 pThis->XtGenIntrCtrl.u64 = 0;
4776 pThis->XtPprIntrCtrl.u64 = 0;
4777 pThis->XtGALogIntrCtrl.u64 = 0;
4778
4779 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4780
4781 pThis->CmdBufHeadPtr.u64 = 0;
4782 pThis->CmdBufTailPtr.u64 = 0;
4783 pThis->EvtLogHeadPtr.u64 = 0;
4784 pThis->EvtLogTailPtr.u64 = 0;
4785
4786 pThis->Status.u64 = 0;
4787
4788 pThis->PprLogHeadPtr.u64 = 0;
4789 pThis->PprLogTailPtr.u64 = 0;
4790
4791 pThis->GALogHeadPtr.u64 = 0;
4792 pThis->GALogTailPtr.u64 = 0;
4793
4794 pThis->PprLogBHeadPtr.u64 = 0;
4795 pThis->PprLogBTailPtr.u64 = 0;
4796
4797 pThis->EvtLogBHeadPtr.u64 = 0;
4798 pThis->EvtLogBTailPtr.u64 = 0;
4799
4800 pThis->PprLogAutoResp.u64 = 0;
4801 pThis->PprLogOverflowEarly.u64 = 0;
4802 pThis->PprLogBOverflowEarly.u64 = 0;
4803
4804 pThis->IommuBar.u64 = 0;
4805 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4806 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4807
4808 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4809
4810 IOMMU_UNLOCK(pDevIns);
4811}
4812
4813
4814/**
4815 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4816 */
4817static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4818{
4819 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4820 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4821 LogFlowFunc(("\n"));
4822
4823 /* Close the command thread semaphore. */
4824 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4825 {
4826 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4827 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4828 }
4829 return VINF_SUCCESS;
4830}
4831
4832
4833/**
4834 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4835 */
4836static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4837{
4838 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4839 RT_NOREF(pCfg);
4840
4841 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4842 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4843 pThisCC->pDevInsR3 = pDevIns;
4844
4845 LogFlowFunc(("iInstance=%d\n", iInstance));
4846
4847 /*
4848 * Register the IOMMU with PDM.
4849 */
4850 PDMIOMMUREGR3 IommuReg;
4851 RT_ZERO(IommuReg);
4852 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4853 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
4854 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
4855 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4856 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4857 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4858 if (RT_FAILURE(rc))
4859 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4860 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4861 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4862 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4863 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4864 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4865 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4866 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4867 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4868
4869 /*
4870 * Initialize read-only PCI configuration space.
4871 */
4872 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4873 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4874
4875 /* Header. */
4876 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4877 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4878 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
4879 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4880 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4881 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4882 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4883 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4884 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4885 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4886 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4887 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4888 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4889 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4890
4891 /* Capability Header. */
4892 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4893 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4894 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4895 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
4896 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4897 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4898 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4899 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4900 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4901 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4902 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4903
4904 /* Base Address Register. */
4905 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4906 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4907
4908 /* IOMMU Range Register. */
4909 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4910
4911 /* Misc. Information Register. */
4912 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4913 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4914 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4915 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4916 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4917 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4918 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4919 uint32_t const uMiscInfoReg1 = 0;
4920 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4921 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4922
4923 /* MSI Capability Header register. */
4924 PDMMSIREG MsiReg;
4925 RT_ZERO(MsiReg);
4926 MsiReg.cMsiVectors = 1;
4927 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4928 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4929 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4930
4931 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4932#if 0
4933 /* MSI Address Lo. */
4934 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4935 /* MSI Address Hi. */
4936 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4937 /* MSI Data. */
4938 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4939#endif
4940
4941#if 0
4942 /** @todo IOMMU: I don't know if we need to support this, enable later if
4943 * required. */
4944 /* MSI Mapping Capability Header register. */
4945 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4946 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4947 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4948 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4949 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4950 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4951 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4952#endif
4953
4954 /*
4955 * Register the PCI function with PDM.
4956 */
4957 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4958 AssertLogRelRCReturn(rc, rc);
4959
4960 /*
4961 * Register MSI support for the PCI device.
4962 * This must be done -after- register it as a PCI device!
4963 */
4964 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4965 AssertRCReturn(rc, rc);
4966
4967 /*
4968 * Intercept PCI config. space accesses.
4969 */
4970 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4971 AssertLogRelRCReturn(rc, rc);
4972
4973 /*
4974 * Create the MMIO region.
4975 * Mapping of the region is done when software configures it via PCI config space.
4976 */
4977 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4978 NULL /* pvUser */,
4979 IOMMMIO_FLAGS_READ_DWORD_QWORD
4980 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
4981 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
4982 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
4983 "AMD-IOMMU", &pThis->hMmio);
4984 AssertLogRelRCReturn(rc, rc);
4985
4986 /*
4987 * Register saved state.
4988 */
4989 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4990 NULL, NULL, NULL,
4991 NULL, iommuAmdR3SaveExec, NULL,
4992 NULL, iommuAmdR3LoadExec, NULL);
4993 AssertLogRelRCReturn(rc, rc);
4994
4995 /*
4996 * Register debugger info items.
4997 */
4998 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
4999 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
5000#if 0
5001 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
5002#endif
5003
5004# ifdef VBOX_WITH_STATISTICS
5005 /*
5006 * Statistics.
5007 */
5008 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
5009 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
5010
5011 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
5012 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
5013
5014 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
5015 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
5016
5017 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
5018 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
5019
5020 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
5021 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
5022
5023 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
5024 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
5025
5026 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
5027 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
5028
5029 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
5030 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
5031 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
5032 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
5033 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
5034 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
5035 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
5036 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
5037 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
5038# endif
5039
5040 /*
5041 * Create the command thread and its event semaphore.
5042 */
5043 char szDevIommu[64];
5044 RT_ZERO(szDevIommu);
5045 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
5046 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5047 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
5048 AssertLogRelRCReturn(rc, rc);
5049
5050 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5051 AssertLogRelRCReturn(rc, rc);
5052
5053 /*
5054 * Initialize read-only registers.
5055 * NOTE! Fields here must match their corresponding field in the ACPI tables.
5056 */
5057 /* Don't remove the commented lines below as it lets us see all features at a glance. */
5058 pThis->ExtFeat.u64 = 0;
5059 //pThis->ExtFeat.n.u1PrefetchSup = 0;
5060 //pThis->ExtFeat.n.u1PprSup = 0;
5061 //pThis->ExtFeat.n.u1X2ApicSup = 0;
5062 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
5063 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
5064 pThis->ExtFeat.n.u1InvAllSup = 1;
5065 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5066 pThis->ExtFeat.n.u1HwErrorSup = 1;
5067 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
5068 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
5069 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
5070 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
5071 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
5072 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
5073 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
5074 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5075 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
5076 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5077 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
5078 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5079 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5080 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5081 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5082 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5083 //pThis->ExtFeat.n.u2MarcSup = 0;
5084 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5085 //pThis->ExtFeat.n.u1PerfOptSup = 0;
5086 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5087 //pThis->ExtFeat.n.u1GstIoSup = 0;
5088 //pThis->ExtFeat.n.u1HostAccessSup = 0;
5089 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5090 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
5091 //pThis->ExtFeat.n.u1HostDirtySup = 0;
5092 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5093 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5094 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5095
5096 pThis->RsvdReg = 0;
5097
5098 pThis->DevSpecificFeat.u64 = 0;
5099 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
5100 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
5101
5102 pThis->DevSpecificCtrl.u64 = 0;
5103 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
5104 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
5105
5106 pThis->DevSpecificStatus.u64 = 0;
5107 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
5108 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
5109
5110 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
5111
5112 /*
5113 * Initialize parts of the IOMMU state as it would during reset.
5114 * Must be called -after- initializing PCI config. space registers.
5115 */
5116 iommuAmdR3Reset(pDevIns);
5117
5118 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
5119 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
5120 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
5121 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
5122 pThis->ExtFeat.u64));
5123 return VINF_SUCCESS;
5124}
5125
5126# else /* !IN_RING3 */
5127
5128/**
5129 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5130 */
5131static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5132{
5133 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5134 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5135 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5136
5137 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5138
5139 /* Set up the MMIO RZ handlers. */
5140 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5141 AssertRCReturn(rc, rc);
5142
5143 /* Set up the IOMMU RZ callbacks. */
5144 PDMIOMMUREGCC IommuReg;
5145 RT_ZERO(IommuReg);
5146 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5147 IommuReg.idxIommu = pThis->idxIommu;
5148 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
5149 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
5150 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5151 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5152 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5153 AssertRCReturn(rc, rc);
5154
5155 return VINF_SUCCESS;
5156}
5157
5158# endif /* !IN_RING3 */
5159
5160/**
5161 * The device registration structure.
5162 */
5163const PDMDEVREG g_DeviceIommuAmd =
5164{
5165 /* .u32Version = */ PDM_DEVREG_VERSION,
5166 /* .uReserved0 = */ 0,
5167 /* .szName = */ "iommu-amd",
5168 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
5169 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
5170 /* .cMaxInstances = */ ~0U,
5171 /* .uSharedVersion = */ 42,
5172 /* .cbInstanceShared = */ sizeof(IOMMU),
5173 /* .cbInstanceCC = */ sizeof(IOMMUCC),
5174 /* .cbInstanceRC = */ sizeof(IOMMURC),
5175 /* .cMaxPciDevices = */ 1,
5176 /* .cMaxMsixVectors = */ 0,
5177 /* .pszDescription = */ "IOMMU (AMD)",
5178#if defined(IN_RING3)
5179 /* .pszRCMod = */ "VBoxDDRC.rc",
5180 /* .pszR0Mod = */ "VBoxDDR0.r0",
5181 /* .pfnConstruct = */ iommuAmdR3Construct,
5182 /* .pfnDestruct = */ iommuAmdR3Destruct,
5183 /* .pfnRelocate = */ NULL,
5184 /* .pfnMemSetup = */ NULL,
5185 /* .pfnPowerOn = */ NULL,
5186 /* .pfnReset = */ iommuAmdR3Reset,
5187 /* .pfnSuspend = */ NULL,
5188 /* .pfnResume = */ NULL,
5189 /* .pfnAttach = */ NULL,
5190 /* .pfnDetach = */ NULL,
5191 /* .pfnQueryInterface = */ NULL,
5192 /* .pfnInitComplete = */ NULL,
5193 /* .pfnPowerOff = */ NULL,
5194 /* .pfnSoftReset = */ NULL,
5195 /* .pfnReserved0 = */ NULL,
5196 /* .pfnReserved1 = */ NULL,
5197 /* .pfnReserved2 = */ NULL,
5198 /* .pfnReserved3 = */ NULL,
5199 /* .pfnReserved4 = */ NULL,
5200 /* .pfnReserved5 = */ NULL,
5201 /* .pfnReserved6 = */ NULL,
5202 /* .pfnReserved7 = */ NULL,
5203#elif defined(IN_RING0)
5204 /* .pfnEarlyConstruct = */ NULL,
5205 /* .pfnConstruct = */ iommuAmdRZConstruct,
5206 /* .pfnDestruct = */ NULL,
5207 /* .pfnFinalDestruct = */ NULL,
5208 /* .pfnRequest = */ NULL,
5209 /* .pfnReserved0 = */ NULL,
5210 /* .pfnReserved1 = */ NULL,
5211 /* .pfnReserved2 = */ NULL,
5212 /* .pfnReserved3 = */ NULL,
5213 /* .pfnReserved4 = */ NULL,
5214 /* .pfnReserved5 = */ NULL,
5215 /* .pfnReserved6 = */ NULL,
5216 /* .pfnReserved7 = */ NULL,
5217#elif defined(IN_RC)
5218 /* .pfnConstruct = */ iommuAmdRZConstruct,
5219 /* .pfnReserved0 = */ NULL,
5220 /* .pfnReserved1 = */ NULL,
5221 /* .pfnReserved2 = */ NULL,
5222 /* .pfnReserved3 = */ NULL,
5223 /* .pfnReserved4 = */ NULL,
5224 /* .pfnReserved5 = */ NULL,
5225 /* .pfnReserved6 = */ NULL,
5226 /* .pfnReserved7 = */ NULL,
5227#else
5228# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5229#endif
5230 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
5231};
5232
5233#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5234
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