DevIommuAmd.cpp@ 86920

Last change on this file since 86920 was 86920, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654 Print parsed device ID before dumping DTE info. in the debugger.
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1	/* $Id: DevIommuAmd.cpp 86920 2020-11-19 13:48:30Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - AMD implementation.
4	*/
5
6	/*
7	* Copyright (C) 2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/msi.h>
24	#include <VBox/iommu-amd.h>
25	#include <VBox/vmm/pdmdev.h>
26	#include <VBox/AssertGuest.h>
27
28	#include <iprt/x86.h>
29	#include <iprt/alloc.h>
30	#include <iprt/string.h>
31
32	#include "VBoxDD.h"
33	#include "DevIommuAmd.h"
34
35
36	/*********************************************************************************************************************************
37	* Defined Constants And Macros *
38	*********************************************************************************************************************************/
39	/** Release log prefix string. */
40	#define IOMMU_LOG_PFX "AMD-IOMMU"
41	/** The current saved state version. */
42	#define IOMMU_SAVED_STATE_VERSION 1
43	/** The IOTLB entry magic. */
44	#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46	#ifndef DEBUG_ramshankar
47	/** Temporary, make permanent later (get rid of define entirely and remove old
48	* code). This allow ssub-qword accesses to qword registers. Write accesses
49	* seems to work (needs testing one sub-path of the code), Read accesses not yet
50	* converted. */
51	# define IOMMU_NEW_REGISTER_ACCESS
52	#endif
53
54
55	/*********************************************************************************************************************************
56	* Structures and Typedefs *
57	*********************************************************************************************************************************/
58	/**
59	* Acquires the IOMMU PDM lock.
60	* This will make a long jump to ring-3 to acquire the lock if necessary.
61	*/
62	#define IOMMU_LOCK(a_pDevIns) \
63	do { \
64	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
65	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
66	{ /* likely */ } \
67	else \
68	return rcLock; \
69	} while (0)
70
71	/**
72	* Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
73	* This will make a long jump to ring-3 to acquire the lock if necessary.
74	*/
75	#define IOMMU_LOCK_NORET(a_pDevIns) \
76	do { \
77	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
78	AssertRC(rcLock); \
79	} while (0)
80
81	/**
82	* Releases the IOMMU PDM lock.
83	*/
84	#define IOMMU_UNLOCK(a_pDevIns) \
85	do { \
86	PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
87	} while (0)
88
89	/**
90	* Asserts that the critsect is owned by this thread.
91	*/
92	#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
93	do { \
94	Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95	} while (0)
96
97	/**
98	* Asserts that the critsect is not owned by this thread.
99	*/
100	#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
101	do { \
102	Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
103	} while (0)
104
105	/**
106	* IOMMU operations (transaction) types.
107	*/
108	typedef enum IOMMUOP
109	{
110	/** Address translation request. */
111	IOMMUOP_TRANSLATE_REQ = 0,
112	/** Memory read request. */
113	IOMMUOP_MEM_READ,
114	/** Memory write request. */
115	IOMMUOP_MEM_WRITE,
116	/** Interrupt request. */
117	IOMMUOP_INTR_REQ,
118	/** Command. */
119	IOMMUOP_CMD
120	} IOMMUOP;
121	AssertCompileSize(IOMMUOP, 4);
122
123	/**
124	* I/O page walk result.
125	*/
126	typedef struct
127	{
128	/** The translated system physical address. */
129	RTGCPHYS GCPhysSpa;
130	/** The number of offset bits in the system physical address. */
131	uint8_t cShift;
132	/** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
133	uint8_t fIoPerm;
134	/** Padding. */
135	uint8_t abPadding[2];
136	} IOWALKRESULT;
137	/** Pointer to an I/O walk result struct. */
138	typedef IOWALKRESULT *PIOWALKRESULT;
139	/** Pointer to a const I/O walk result struct. */
140	typedef IOWALKRESULT *PCIOWALKRESULT;
141
142	/**
143	* IOMMU I/O TLB Entry.
144	* Keep this as small and aligned as possible.
145	*/
146	typedef struct
147	{
148	/** The translated system physical address (SPA) of the page. */
149	RTGCPHYS GCPhysSpa;
150	/** The index of the 4K page within a large page. */
151	uint32_t idxSubPage;
152	/** The I/O access permissions (IOMMU_IO_PERM_XXX). */
153	uint8_t fIoPerm;
154	/** The number of offset bits in the translation indicating page size. */
155	uint8_t cShift;
156	/** Alignment padding. */
157	uint8_t afPadding[2];
158	} IOTLBE_T;
159	AssertCompileSize(IOTLBE_T, 16);
160	/** Pointer to an IOMMU I/O TLB entry struct. */
161	typedef IOTLBE_T *PIOTLBE_T;
162	/** Pointer to a const IOMMU I/O TLB entry struct. */
163	typedef IOTLBE_T const *PCIOTLBE_T;
164
165	/**
166	* The shared IOMMU device state.
167	*/
168	typedef struct IOMMU
169	{
170	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
171	uint32_t idxIommu;
172	/** Alignment padding. */
173	uint32_t uPadding0;
174
175	/** Whether the command thread is sleeping. */
176	bool volatile fCmdThreadSleeping;
177	/** Alignment padding. */
178	uint8_t afPadding0[3];
179	/** Whether the command thread has been signaled for wake up. */
180	bool volatile fCmdThreadSignaled;
181	/** Alignment padding. */
182	uint8_t afPadding1[3];
183
184	/** The event semaphore the command thread waits on. */
185	SUPSEMEVENT hEvtCmdThread;
186	/** The MMIO handle. */
187	IOMMMIOHANDLE hMmio;
188
189	/** @name PCI: Base capability block registers.
190	* @{ */
191	IOMMU_BAR_T IommuBar; /*< IOMMU base address register. /
192	/** @} */
193
194	/** @name MMIO: Control and status registers.
195	* @{ */
196	DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /*< Device table base address registers. /
197	CMD_BUF_BAR_T CmdBufBaseAddr; /*< Command buffer base address register. /
198	EVT_LOG_BAR_T EvtLogBaseAddr; /*< Event log base address register. /
199	IOMMU_CTRL_T Ctrl; /*< IOMMU control register. /
200	IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /*< IOMMU exclusion range base register. /
201	IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /*< IOMMU exclusion range limit. /
202	IOMMU_EXT_FEAT_T ExtFeat; /*< IOMMU extended feature register. /
203	/** @} */
204
205	/** @name MMIO: Peripheral Page Request (PPR) Log registers.
206	* @{ */
207	PPR_LOG_BAR_T PprLogBaseAddr; /*< PPR Log base address register. /
208	IOMMU_HW_EVT_HI_T HwEvtHi; /*< IOMMU hardware event register (Hi). /
209	IOMMU_HW_EVT_LO_T HwEvtLo; /*< IOMMU hardware event register (Lo). /
210	IOMMU_HW_EVT_STATUS_T HwEvtStatus; /*< IOMMU hardware event status. /
211	/** @} */
212
213	/** @todo IOMMU: SMI filter. */
214
215	/** @name MMIO: Guest Virtual-APIC Log registers.
216	* @{ */
217	GALOG_BAR_T GALogBaseAddr; /*< Guest Virtual-APIC Log base address register. /
218	GALOG_TAIL_ADDR_T GALogTailAddr; /*< Guest Virtual-APIC Log Tail address register. /
219	/** @} */
220
221	/** @name MMIO: Alternate PPR and Event Log registers.
222	* @{ */
223	PPR_LOG_B_BAR_T PprLogBBaseAddr; /*< PPR Log B base address register. /
224	EVT_LOG_B_BAR_T EvtLogBBaseAddr; /*< Event Log B base address register. /
225	/** @} */
226
227	/** @name MMIO: Device-specific feature registers.
228	* @{ */
229	DEV_SPECIFIC_FEAT_T DevSpecificFeat; /*< Device-specific feature extension register (DSFX). /
230	DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /*< Device-specific control extension register (DSCX). /
231	DEV_SPECIFIC_STATUS_T DevSpecificStatus; /*< Device-specific status extension register (DSSX). /
232	/** @} */
233
234	/** @name MMIO: MSI Capability Block registers.
235	* @{ */
236	MSI_MISC_INFO_T MiscInfo; /*< MSI Misc. info registers / MSI Vector registers. /
237	/** @} */
238
239	/** @name MMIO: Performance Optimization Control registers.
240	* @{ */
241	IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /*< IOMMU Performance optimization control register. /
242	/** @} */
243
244	/** @name MMIO: x2APIC Control registers.
245	* @{ */
246	IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /*< IOMMU X2APIC General interrupt control register. /
247	IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /*< IOMMU X2APIC PPR interrupt control register. /
248	IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /*< IOMMU X2APIC Guest Log interrupt control register. /
249	/** @} */
250
251	/** @name MMIO: Memory Address Routing & Control (MARC) registers.
252	* @{ */
253	MARC_APER_T aMarcApers[4]; /*< MARC Aperture Registers. /
254	/** @} */
255
256	/** @name MMIO: Reserved register.
257	* @{ */
258	IOMMU_RSVD_REG_T RsvdReg; /*< IOMMU Reserved Register. /
259	/** @} */
260
261	/** @name MMIO: Command and Event Log pointer registers.
262	* @{ */
263	CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /*< Command buffer head pointer register. /
264	CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /*< Command buffer tail pointer register. /
265	EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /*< Event log head pointer register. /
266	EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /*< Event log tail pointer register. /
267	/** @} */
268
269	/** @name MMIO: Command and Event Status register.
270	* @{ */
271	IOMMU_STATUS_T Status; /*< IOMMU status register. /
272	/** @} */
273
274	/** @name MMIO: PPR Log Head and Tail pointer registers.
275	* @{ */
276	PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /*< IOMMU PPR log head pointer register. /
277	PPR_LOG_TAIL_PTR_T PprLogTailPtr; /*< IOMMU PPR log tail pointer register. /
278	/** @} */
279
280	/** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
281	* @{ */
282	GALOG_HEAD_PTR_T GALogHeadPtr; /*< Guest Virtual-APIC log head pointer register. /
283	GALOG_TAIL_PTR_T GALogTailPtr; /*< Guest Virtual-APIC log tail pointer register. /
284	/** @} */
285
286	/** @name MMIO: PPR Log B Head and Tail pointer registers.
287	* @{ */
288	PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /*< PPR log B head pointer register. /
289	PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /*< PPR log B tail pointer register. /
290	/** @} */
291
292	/** @name MMIO: Event Log B Head and Tail pointer registers.
293	* @{ */
294	EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /*< Event log B head pointer register. /
295	EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /*< Event log B tail pointer register. /
296	/** @} */
297
298	/** @name MMIO: PPR Log Overflow protection registers.
299	* @{ */
300	PPR_LOG_AUTO_RESP_T PprLogAutoResp; /*< PPR Log Auto Response register. /
301	PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /*< PPR Log Overflow Early Indicator register. /
302	PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /*< PPR Log B Overflow Early Indicator register. /
303	/** @} */
304
305	/** @todo IOMMU: IOMMU Event counter registers. */
306
307	#ifdef VBOX_WITH_STATISTICS
308	/** @name IOMMU: Stat counters.
309	* @{ */
310	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
311	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
312	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
313	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
314
315	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
316	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
317
318	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
319	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
320	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
321	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
322
323	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
324	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
325	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
326	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
327
328	STAMCOUNTER StatCmd; /*< Number of commands processed. /
329	STAMCOUNTER StatCmdCompWait; /*< Number of Completion Wait commands processed. /
330	STAMCOUNTER StatCmdInvDte; /*< Number of Invalidate DTE commands processed. /
331	STAMCOUNTER StatCmdInvIommuPages; /*< Number of Invalidate IOMMU pages commands processed. /
332	STAMCOUNTER StatCmdInvIotlbPages; /*< Number of Invalidate IOTLB pages commands processed. /
333	STAMCOUNTER StatCmdInvIntrTable; /*< Number of Invalidate Interrupt Table commands processed. /
334	STAMCOUNTER StatCmdPrefIommuPages; /*< Number of Prefetch IOMMU Pages commands processed. /
335	STAMCOUNTER StatCmdCompletePprReq; /*< Number of Complete PPR Requests commands processed. /
336	STAMCOUNTER StatCmdInvIommuAll; /*< Number of Invalidate IOMMU All commands processed. /
337	/** @} */
338	#endif
339	} IOMMU;
340	/** Pointer to the IOMMU device state. */
341	typedef struct IOMMU *PIOMMU;
342	/** Pointer to the const IOMMU device state. */
343	typedef const struct IOMMU *PCIOMMU;
344	AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
345	AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
346	AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
347	AssertCompileMemberAlignment(IOMMU, hMmio, 8);
348	AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
349
350	/**
351	* The ring-3 IOMMU device state.
352	*/
353	typedef struct IOMMUR3
354	{
355	/** Device instance. */
356	PPDMDEVINSR3 pDevInsR3;
357	/** The IOMMU helpers. */
358	PCPDMIOMMUHLPR3 pIommuHlpR3;
359	/** The command thread handle. */
360	R3PTRTYPE(PPDMTHREAD) pCmdThread;
361	} IOMMUR3;
362	/** Pointer to the ring-3 IOMMU device state. */
363	typedef IOMMUR3 *PIOMMUR3;
364
365	/**
366	* The ring-0 IOMMU device state.
367	*/
368	typedef struct IOMMUR0
369	{
370	/** Device instance. */
371	PPDMDEVINSR0 pDevInsR0;
372	/** The IOMMU helpers. */
373	PCPDMIOMMUHLPR0 pIommuHlpR0;
374	} IOMMUR0;
375	/** Pointer to the ring-0 IOMMU device state. */
376	typedef IOMMUR0 *PIOMMUR0;
377
378	/**
379	* The raw-mode IOMMU device state.
380	*/
381	typedef struct IOMMURC
382	{
383	/** Device instance. */
384	PPDMDEVINSR0 pDevInsRC;
385	/** The IOMMU helpers. */
386	PCPDMIOMMUHLPRC pIommuHlpRC;
387	} IOMMURC;
388	/** Pointer to the raw-mode IOMMU device state. */
389	typedef IOMMURC *PIOMMURC;
390
391	/** The IOMMU device state for the current context. */
392	typedef CTX_SUFF(IOMMU) IOMMUCC;
393	/** Pointer to the IOMMU device state for the current context. */
394	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
395
396	/**
397	* IOMMU register access.
398	*/
399	typedef struct IOMMUREGACC
400	{
401	const char *pszName;
402	VBOXSTRICTRC (pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t pu64Value);
403	VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
404	} IOMMUREGACC;
405	/** Pointer to an IOMMU register access. */
406	typedef IOMMUREGACC *PIOMMUREGACC;
407	/** Pointer to a const IOMMU register access. */
408	typedef IOMMUREGACC const *PCIOMMUREGACC;
409
410
411	/*********************************************************************************************************************************
412	* Global Variables *
413	*********************************************************************************************************************************/
414	/**
415	* An array of the number of device table segments supported.
416	* Indexed by u2DevTabSegSup.
417	*/
418	static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
419
420	/**
421	* An array of the masks to select the device table segment index from a device ID.
422	*/
423	static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
424
425	/**
426	* An array of the shift values to select the device table segment index from a
427	* device ID.
428	*/
429	static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
430
431	/**
432	* The maximum size (inclusive) of each device table segment (0 to 7).
433	* Indexed by the device table segment index.
434	*/
435	static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
436
437
438	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
439	/**
440	* Gets the maximum number of buffer entries for the given buffer length.
441	*
442	* @returns Number of buffer entries.
443	* @param uEncodedLen The length (power-of-2 encoded).
444	*/
445	DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
446	{
447	Assert(uEncodedLen > 7);
448	return 2 << (uEncodedLen - 1);
449	}
450
451
452	/**
453	* Gets the total length of the buffer given a base register's encoded length.
454	*
455	* @returns The length of the buffer in bytes.
456	* @param uEncodedLen The length (power-of-2 encoded).
457	*/
458	DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
459	{
460	Assert(uEncodedLen > 7);
461	return (2 << (uEncodedLen - 1)) << 4;
462	}
463
464
465	/**
466	* Gets the number of (unconsumed) entries in the event log.
467	*
468	* @returns The number of entries in the event log.
469	* @param pThis The IOMMU device state.
470	*/
471	static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
472	{
473	uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
474	uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
475	if (idxTail >= idxHead)
476	return idxTail - idxHead;
477
478	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
479	return cMaxEvts - idxHead + idxTail;
480	}
481
482
483	#if 0
484	/**
485	* Gets the number of (unconsumed) commands in the command buffer.
486	*
487	* @returns The number of commands in the command buffer.
488	* @param pThis The IOMMU device state.
489	*/
490	static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
491	{
492	uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
493	uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
494	if (idxTail >= idxHead)
495	return idxTail - idxHead;
496
497	uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
498	return cMaxCmds - idxHead + idxTail;
499	}
500	#endif
501
502
503	DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
504	{
505	IOMMU_STATUS_T Status;
506	Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
507	return Status;
508	}
509
510
511	DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
512	{
513	IOMMU_CTRL_T Ctrl;
514	Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
515	return Ctrl;
516	}
517
518
519	/**
520	* Returns whether MSI is enabled for the IOMMU.
521	*
522	* @returns Whether MSI is enabled.
523	* @param pDevIns The IOMMU device instance.
524	*
525	* @note There should be a PCIDevXxx function for this.
526	*/
527	static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
528	{
529	MSI_CAP_HDR_T MsiCapHdr;
530	MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
531	return MsiCapHdr.n.u1MsiEnable;
532	}
533
534
535	/**
536	* Signals a PCI target abort.
537	*
538	* @param pDevIns The IOMMU device instance.
539	*/
540	static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
541	{
542	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
543	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
544	PDMPciDevSetStatus(pPciDev, u16Status);
545	}
546
547
548	/**
549	* Wakes up the command thread if there are commands to be processed or if
550	* processing is requested to be stopped by software.
551	*
552	* @param pDevIns The IOMMU device instance.
553	*/
554	static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
555	{
556	IOMMU_ASSERT_LOCKED(pDevIns);
557	Log5Func(("\n"));
558
559	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
560	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
561	if (Status.n.u1CmdBufRunning)
562	{
563	Log5Func(("Signaling command thread\n"));
564	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
565	}
566	}
567
568
569	/**
570	* Reads the Device Table Base Address Register.
571	*/
572	static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
573	{
574	RT_NOREF(pDevIns, offReg);
575	*pu64Value = pThis->aDevTabBaseAddrs[0].u64;
576	return VINF_SUCCESS;
577	}
578
579
580	/**
581	* Reads the Command Buffer Base Address Register.
582	*/
583	static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
584	{
585	RT_NOREF(pDevIns, offReg);
586	*pu64Value = pThis->CmdBufBaseAddr.u64;
587	return VINF_SUCCESS;
588	}
589
590
591	/**
592	* Reads the Event Log Base Address Register.
593	*/
594	static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
595	{
596	RT_NOREF(pDevIns, offReg);
597	*pu64Value = pThis->EvtLogBaseAddr.u64;
598	return VINF_SUCCESS;
599	}
600
601
602	/**
603	* Reads the Control Register.
604	*/
605	static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
606	{
607	RT_NOREF(pDevIns, offReg);
608	*pu64Value = pThis->Ctrl.u64;
609	return VINF_SUCCESS;
610	}
611
612
613	/**
614	* Reads the Exclusion Range Base Address Register.
615	*/
616	static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
617	{
618	RT_NOREF(pDevIns, offReg);
619	*pu64Value = pThis->ExclRangeBaseAddr.u64;
620	return VINF_SUCCESS;
621	}
622
623
624	/**
625	* Reads to the Exclusion Range Limit Register.
626	*/
627	static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
628	{
629	RT_NOREF(pDevIns, offReg);
630	*pu64Value = pThis->ExclRangeLimit.u64;
631	return VINF_SUCCESS;
632	}
633
634
635	/**
636	* Reads to the Extended Feature Register.
637	*/
638	static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
639	{
640	RT_NOREF(pDevIns, offReg);
641	*pu64Value = pThis->ExtFeat.u64;
642	return VINF_SUCCESS;
643	}
644
645
646	/**
647	* Reads to the PPR Log Base Address Register.
648	*/
649	static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
650	{
651	RT_NOREF(pDevIns, offReg);
652	*pu64Value = pThis->PprLogBaseAddr.u64;
653	return VINF_SUCCESS;
654	}
655
656
657	/**
658	* Writes the Hardware Event Register (Hi).
659	*/
660	static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
661	{
662	RT_NOREF(pDevIns, offReg);
663	*pu64Value = pThis->HwEvtHi.u64;
664	return VINF_SUCCESS;
665	}
666
667
668	/**
669	* Reads the Hardware Event Register (Lo).
670	*/
671	static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
672	{
673	RT_NOREF(pDevIns, offReg);
674	*pu64Value = pThis->HwEvtLo;
675	return VINF_SUCCESS;
676	}
677
678
679	/**
680	* Reads the Hardware Event Status Register.
681	*/
682	static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
683	{
684	RT_NOREF(pDevIns, offReg);
685	*pu64Value = pThis->HwEvtStatus.u64;
686	return VINF_SUCCESS;
687	}
688
689
690	/**
691	* Reads to the GA Log Base Address Register.
692	*/
693	static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
694	{
695	RT_NOREF(pDevIns, offReg);
696	*pu64Value = pThis->GALogBaseAddr.u64;
697	return VINF_SUCCESS;
698	}
699
700
701	/**
702	* Reads to the PPR Log B Base Address Register.
703	*/
704	static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
705	{
706	RT_NOREF(pDevIns, offReg);
707	*pu64Value = pThis->PprLogBBaseAddr.u64;
708	return VINF_SUCCESS;
709	}
710
711
712	/**
713	* Reads to the Event Log B Base Address Register.
714	*/
715	static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
716	{
717	RT_NOREF(pDevIns, offReg);
718	*pu64Value = pThis->EvtLogBBaseAddr.u64;
719	return VINF_SUCCESS;
720	}
721
722
723	/**
724	* Reads the Device Table Segment Base Address Register.
725	*/
726	static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
727	{
728	RT_NOREF(pDevIns);
729
730	/* Figure out which segment is being written. */
731	uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
732	uint8_t const idxSegment = offSegment + 1;
733	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
734
735	*pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
736	return VINF_SUCCESS;
737	}
738
739
740	/**
741	* Reads the Device Specific Feature Extension (DSFX) Register.
742	*/
743	static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
744	{
745	RT_NOREF(pDevIns, offReg);
746	*pu64Value = pThis->DevSpecificFeat.u64;
747	return VINF_SUCCESS;
748	}
749
750	/**
751	* Reads the Device Specific Control Extension (DSCX) Register.
752	*/
753	static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
754	{
755	RT_NOREF(pDevIns, offReg);
756	*pu64Value = pThis->DevSpecificCtrl.u64;
757	return VINF_SUCCESS;
758	}
759
760
761	/**
762	* Reads the Device Specific Status Extension (DSSX) Register.
763	*/
764	static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
765	{
766	RT_NOREF(pDevIns, offReg);
767	*pu64Value = pThis->DevSpecificStatus.u64;
768	return VINF_SUCCESS;
769	}
770
771
772	/**
773	* Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
774	*/
775	static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
776	{
777	RT_NOREF(pDevIns, offReg);
778	uint32_t const uLo = pThis->MiscInfo.au32[0];
779	uint32_t const uHi = pThis->MiscInfo.au32[1];
780	*pu64Value = RT_MAKE_U64(uLo, uHi);
781	return VINF_SUCCESS;
782	}
783
784
785	#ifdef IOMMU_NEW_REGISTER_ACCESS
786	/**
787	* Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
788	* Register (32-bit).
789	*/
790	static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
791	{
792	RT_NOREF(pThis, offReg);
793	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
794	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
795	uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
796	uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
797	*pu64Value = RT_MAKE_U64(uLo, uHi);
798	return VINF_SUCCESS;
799	}
800
801
802	/**
803	* Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
804	*/
805	static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
806	{
807	RT_NOREF(pThis, offReg);
808	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
809	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
810	uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
811	uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
812	*pu64Value = RT_MAKE_U64(uLo, uHi);
813	return VINF_SUCCESS;
814	}
815	#endif
816
817
818	/**
819	* Reads the Command Buffer Head Pointer Register.
820	*/
821	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
822	{
823	RT_NOREF(pDevIns, offReg);
824	*pu64Value = pThis->CmdBufHeadPtr.u64;
825	return VINF_SUCCESS;
826	}
827
828
829	/**
830	* Reads the Command Buffer Tail Pointer Register.
831	*/
832	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
833	{
834	RT_NOREF(pDevIns, offReg);
835	*pu64Value = pThis->CmdBufTailPtr.u64;
836	return VINF_SUCCESS;
837	}
838
839
840	/**
841	* Reads the Event Log Head Pointer Register.
842	*/
843	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
844	{
845	RT_NOREF(pDevIns, offReg);
846	*pu64Value = pThis->EvtLogHeadPtr.u64;
847	return VINF_SUCCESS;
848	}
849
850
851	/**
852	* Reads the Event Log Tail Pointer Register.
853	*/
854	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
855	{
856	RT_NOREF(pDevIns, offReg);
857	*pu64Value = pThis->EvtLogTailPtr.u64;
858	return VINF_SUCCESS;
859	}
860
861
862	/**
863	* Reads the Status Register.
864	*/
865	static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
866	{
867	RT_NOREF(pDevIns, offReg);
868	*pu64Value = pThis->Status.u64;
869	return VINF_SUCCESS;
870	}
871
872	#ifndef IOMMU_NEW_REGISTER_ACCESS
873	static VBOXSTRICTRC iommuAmdIgnore_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
874	{
875	RT_NOREF(pDevIns, pThis, offReg, u64Value);
876	return VINF_SUCCESS;
877	}
878	#endif
879
880
881	/**
882	* Writes the Device Table Base Address Register.
883	*/
884	static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
885	{
886	RT_NOREF(pDevIns, offReg);
887
888	/* Mask out all unrecognized bits. */
889	u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
890
891	/* Update the register. */
892	pThis->aDevTabBaseAddrs[0].u64 = u64Value;
893
894	/* Paranoia. */
895	Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
896	return VINF_SUCCESS;
897	}
898
899
900	/**
901	* Writes the Command Buffer Base Address Register.
902	*/
903	static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
904	{
905	RT_NOREF(pDevIns, offReg);
906
907	/*
908	* While this is not explicitly specified like the event log base address register,
909	* the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
910	* Inconsistent specs :/
911	*/
912	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
913	if (Status.n.u1CmdBufRunning)
914	{
915	LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
916	return VINF_SUCCESS;
917	}
918
919	/* Mask out all unrecognized bits. */
920	CMD_BUF_BAR_T CmdBufBaseAddr;
921	CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
922
923	/* Validate the length. */
924	if (CmdBufBaseAddr.n.u4Len >= 8)
925	{
926	/* Update the register. */
927	pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
928
929	/*
930	* Writing the command buffer base address, clears the command buffer head and tail pointers.
931	* See AMD spec. 2.4 "Commands".
932	*/
933	pThis->CmdBufHeadPtr.u64 = 0;
934	pThis->CmdBufTailPtr.u64 = 0;
935	}
936	else
937	LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
938
939	return VINF_SUCCESS;
940	}
941
942
943	/**
944	* Writes the Event Log Base Address Register.
945	*/
946	static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
947	{
948	RT_NOREF(pDevIns, offReg);
949
950	/*
951	* IOMMU behavior is undefined when software writes this register when event logging is running.
952	* In our emulation, we ignore the write entirely.
953	* See AMD IOMMU spec. "Event Log Base Address Register".
954	*/
955	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
956	if (Status.n.u1EvtLogRunning)
957	{
958	LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
959	return VINF_SUCCESS;
960	}
961
962	/* Mask out all unrecognized bits. */
963	u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
964	EVT_LOG_BAR_T EvtLogBaseAddr;
965	EvtLogBaseAddr.u64 = u64Value;
966
967	/* Validate the length. */
968	if (EvtLogBaseAddr.n.u4Len >= 8)
969	{
970	/* Update the register. */
971	pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
972
973	/*
974	* Writing the event log base address, clears the event log head and tail pointers.
975	* See AMD spec. 2.5 "Event Logging".
976	*/
977	pThis->EvtLogHeadPtr.u64 = 0;
978	pThis->EvtLogTailPtr.u64 = 0;
979	}
980	else
981	LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
982
983	return VINF_SUCCESS;
984	}
985
986
987	/**
988	* Writes the Control Register.
989	*/
990	static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
991	{
992	RT_NOREF(pDevIns, offReg);
993
994	/* Mask out all unrecognized bits. */
995	u64Value &= IOMMU_CTRL_VALID_MASK;
996	IOMMU_CTRL_T NewCtrl;
997	NewCtrl.u64 = u64Value;
998
999	/* Ensure the device table segments are within limits. */
1000	if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
1001	{
1002	IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
1003
1004	/* Update the register. */
1005	ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
1006
1007	bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
1008	bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
1009
1010	/* Enable or disable event logging when the bit transitions. */
1011	bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
1012	bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1013	if ( fOldEvtLogEn != fNewEvtLogEn
1014	\|\| fOldIommuEn != fNewIommuEn)
1015	{
1016	if ( fNewIommuEn
1017	&& fNewEvtLogEn)
1018	{
1019	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1020	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1021	}
1022	else
1023	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1024	}
1025
1026	/* Enable or disable command buffer processing when the bit transitions. */
1027	bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1028	bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1029	if ( fOldCmdBufEn != fNewCmdBufEn
1030	\|\| fOldIommuEn != fNewIommuEn)
1031	{
1032	if ( fNewCmdBufEn
1033	&& fNewIommuEn)
1034	{
1035	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1036	LogFunc(("Command buffer enabled\n"));
1037
1038	/* Wake up the command thread to start processing commands. */
1039	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1040	}
1041	else
1042	{
1043	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1044	LogFunc(("Command buffer disabled\n"));
1045	}
1046	}
1047	}
1048	else
1049	{
1050	LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1051	pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1052	}
1053
1054	return VINF_SUCCESS;
1055	}
1056
1057
1058	/**
1059	* Writes to the Exclusion Range Base Address Register.
1060	*/
1061	static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1062	{
1063	RT_NOREF(pDevIns, offReg);
1064	pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1065	return VINF_SUCCESS;
1066	}
1067
1068
1069	/**
1070	* Writes to the Exclusion Range Limit Register.
1071	*/
1072	static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1073	{
1074	RT_NOREF(pDevIns, offReg);
1075	u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1076	u64Value \|= UINT64_C(0xfff);
1077	pThis->ExclRangeLimit.u64 = u64Value;
1078	return VINF_SUCCESS;
1079	}
1080
1081
1082	/**
1083	* Writes the Hardware Event Register (Hi).
1084	*/
1085	static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1086	{
1087	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1088	RT_NOREF(pDevIns, offReg);
1089	LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1090	pThis->HwEvtHi.u64 = u64Value;
1091	return VINF_SUCCESS;
1092	}
1093
1094
1095	/**
1096	* Writes the Hardware Event Register (Lo).
1097	*/
1098	static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1099	{
1100	/** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1101	RT_NOREF(pDevIns, offReg);
1102	LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1103	pThis->HwEvtLo = u64Value;
1104	return VINF_SUCCESS;
1105	}
1106
1107
1108	/**
1109	* Writes the Hardware Event Status Register.
1110	*/
1111	static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1112	{
1113	RT_NOREF(pDevIns, offReg);
1114
1115	/* Mask out all unrecognized bits. */
1116	u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1117
1118	/*
1119	* The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1120	* If the current status bits or the bits being written are both 0, we've nothing to do.
1121	* The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1122	*/
1123	uint64_t HwStatus = pThis->HwEvtStatus.u64;
1124	if (!(HwStatus & RT_BIT(0)))
1125	return VINF_SUCCESS;
1126	if (u64Value & HwStatus & RT_BIT_64(0))
1127	HwStatus &= ~RT_BIT_64(0);
1128	if (u64Value & HwStatus & RT_BIT_64(1))
1129	HwStatus &= ~RT_BIT_64(1);
1130
1131	/* Update the register. */
1132	pThis->HwEvtStatus.u64 = HwStatus;
1133	return VINF_SUCCESS;
1134	}
1135
1136
1137	/**
1138	* Writes the Device Table Segment Base Address Register.
1139	*/
1140	static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1141	{
1142	RT_NOREF(pDevIns);
1143
1144	/* Figure out which segment is being written. */
1145	uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1146	uint8_t const idxSegment = offSegment + 1;
1147	Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1148
1149	/* Mask out all unrecognized bits. */
1150	u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1151	DEV_TAB_BAR_T DevTabSegBar;
1152	DevTabSegBar.u64 = u64Value;
1153
1154	/* Validate the size. */
1155	uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1156	uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1157	if (uSegSize <= uMaxSegSize)
1158	{
1159	/* Update the register. */
1160	pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1161	}
1162	else
1163	LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1164
1165	return VINF_SUCCESS;
1166	}
1167
1168
1169	#ifndef IOMMU_NEW_REGISTER_ACCESS
1170	/**
1171	* Writes the MSI Capability Header Register.
1172	*/
1173	static VBOXSTRICTRC iommuAmdMsiCapHdr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1174	{
1175	RT_NOREF(pThis, offReg);
1176	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1177	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1178	MSI_CAP_HDR_T MsiCapHdr;
1179	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1180	MsiCapHdr.n.u1MsiEnable = RT_BOOL(u64Value & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1181	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1182	return VINF_SUCCESS;
1183	}
1184
1185
1186	/**
1187	* Writes the MSI Address (Lo) Register (32-bit).
1188	*/
1189	static VBOXSTRICTRC iommuAmdMsiAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1190	{
1191	RT_NOREF(pThis, offReg);
1192	Assert(!RT_HI_U32(u64Value));
1193	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1194	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1195	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, u64Value & VBOX_MSI_ADDR_VALID_MASK);
1196	return VINF_SUCCESS;
1197	}
1198
1199
1200	/**
1201	* Writes the MSI Address (Hi) Register (32-bit).
1202	*/
1203	static VBOXSTRICTRC iommuAmdMsiAddrHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1204	{
1205	RT_NOREF(pThis, offReg);
1206	Assert(!RT_HI_U32(u64Value));
1207	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1208	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1209	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, u64Value);
1210	return VINF_SUCCESS;
1211	}
1212
1213
1214	/**
1215	* Writes the MSI Data Register (32-bit).
1216	*/
1217	static VBOXSTRICTRC iommuAmdMsiData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1218	{
1219	RT_NOREF(pThis, offReg);
1220	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1221	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1222	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, u64Value & VBOX_MSI_DATA_VALID_MASK);
1223	return VINF_SUCCESS;
1224	}
1225	#else
1226	/**
1227	* Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1228	*/
1229	static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1230	{
1231	RT_NOREF(pDevIns, offReg);
1232
1233	/* MSI Vector Register 0 is read-only. */
1234	/* MSI Vector Register 1. */
1235	uint32_t const uReg = u64Value >> 32;
1236	pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
1237	return VINF_SUCCESS;
1238	}
1239
1240
1241	/**
1242	* Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1243	* Register (32-bit).
1244	*/
1245	static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1246	{
1247	RT_NOREF(pThis, offReg);
1248	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1249	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1250
1251	/* MSI capability header. */
1252	{
1253	uint32_t const uReg = u64Value;
1254	MSI_CAP_HDR_T MsiCapHdr;
1255	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1256	MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1257	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1258	}
1259
1260	/* MSI Address Lo. */
1261	{
1262	uint32_t const uReg = u64Value >> 32;
1263	uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
1264	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1265	}
1266
1267	return VINF_SUCCESS;
1268	}
1269
1270
1271	/**
1272	* Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1273	*/
1274	static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1275	{
1276	RT_NOREF(pThis, offReg);
1277	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1278	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1279
1280	/* MSI Address Hi. */
1281	{
1282	uint32_t const uReg = u64Value;
1283	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
1284	}
1285
1286	/* MSI Data. */
1287	{
1288	uint32_t const uReg = u64Value >> 32;
1289	uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
1290	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1291	}
1292
1293	return VINF_SUCCESS;
1294	}
1295	#endif
1296
1297
1298	/**
1299	* Writes the Command Buffer Head Pointer Register.
1300	*/
1301	static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1302	{
1303	RT_NOREF(pDevIns, offReg);
1304
1305	/*
1306	* IOMMU behavior is undefined when software writes this register when the command buffer is running.
1307	* In our emulation, we ignore the write entirely.
1308	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1309	*/
1310	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1311	if (Status.n.u1CmdBufRunning)
1312	{
1313	LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1314	return VINF_SUCCESS;
1315	}
1316
1317	/*
1318	* IOMMU behavior is undefined when software writes a value outside the buffer length.
1319	* In our emulation, we ignore the write entirely.
1320	*/
1321	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1322	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1323	Assert(cbBuf <= _512K);
1324	if (offBuf >= cbBuf)
1325	{
1326	LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1327	return VINF_SUCCESS;
1328	}
1329
1330	/* Update the register. */
1331	pThis->CmdBufHeadPtr.au32[0] = offBuf;
1332
1333	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1334
1335	Log5Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1336	return VINF_SUCCESS;
1337	}
1338
1339
1340	/**
1341	* Writes the Command Buffer Tail Pointer Register.
1342	*/
1343	static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1344	{
1345	RT_NOREF(pDevIns, offReg);
1346
1347	/*
1348	* IOMMU behavior is undefined when software writes a value outside the buffer length.
1349	* In our emulation, we ignore the write entirely.
1350	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1351	*/
1352	uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1353	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1354	Assert(cbBuf <= _512K);
1355	if (offBuf >= cbBuf)
1356	{
1357	LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1358	return VINF_SUCCESS;
1359	}
1360
1361	/*
1362	* IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1363	* head pointer after adding one or more commands to the buffer.
1364	*
1365	* However, we cannot enforce this strictly because it's legal for software to shrink the
1366	* command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1367	* at 0). Software might even make the queue empty by making head and tail equal which is
1368	* allowed. I don't think we can or should try too hard to prevent software shooting itself
1369	* in the foot here. As long as we make sure the offset value is within the circular buffer
1370	* bounds (which we do by masking bits above) it should be sufficient.
1371	*/
1372	pThis->CmdBufTailPtr.au32[0] = offBuf;
1373
1374	iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1375
1376	Log5Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1377	return VINF_SUCCESS;
1378	}
1379
1380
1381	/**
1382	* Writes the Event Log Head Pointer Register.
1383	*/
1384	static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1385	{
1386	RT_NOREF(pDevIns, offReg);
1387
1388	/*
1389	* IOMMU behavior is undefined when software writes a value outside the buffer length.
1390	* In our emulation, we ignore the write entirely.
1391	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1392	*/
1393	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1394	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1395	Assert(cbBuf <= _512K);
1396	if (offBuf >= cbBuf)
1397	{
1398	LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1399	return VINF_SUCCESS;
1400	}
1401
1402	/* Update the register. */
1403	pThis->EvtLogHeadPtr.au32[0] = offBuf;
1404
1405	LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1406	return VINF_SUCCESS;
1407	}
1408
1409
1410	/**
1411	* Writes the Event Log Tail Pointer Register.
1412	*/
1413	static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1414	{
1415	RT_NOREF(pDevIns, offReg);
1416	NOREF(pThis);
1417
1418	/*
1419	* IOMMU behavior is undefined when software writes this register when the event log is running.
1420	* In our emulation, we ignore the write entirely.
1421	* See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1422	*/
1423	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1424	if (Status.n.u1EvtLogRunning)
1425	{
1426	LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1427	return VINF_SUCCESS;
1428	}
1429
1430	/*
1431	* IOMMU behavior is undefined when software writes a value outside the buffer length.
1432	* In our emulation, we ignore the write entirely.
1433	*/
1434	uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1435	uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1436	Assert(cbBuf <= _512K);
1437	if (offBuf >= cbBuf)
1438	{
1439	LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1440	return VINF_SUCCESS;
1441	}
1442
1443	/* Update the register. */
1444	pThis->EvtLogTailPtr.au32[0] = offBuf;
1445
1446	LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1447	return VINF_SUCCESS;
1448	}
1449
1450
1451	/**
1452	* Writes the Status Register.
1453	*/
1454	static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1455	{
1456	RT_NOREF(pDevIns, offReg);
1457
1458	/* Mask out all unrecognized bits. */
1459	u64Value &= IOMMU_STATUS_VALID_MASK;
1460
1461	/*
1462	* Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1463	* Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1464	*/
1465	IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1466	uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1467	uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1468	uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1469
1470	uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) \| fOldRoBits;
1471
1472	/* Update the register. */
1473	ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1474	return VINF_SUCCESS;
1475	}
1476
1477	#ifdef IOMMU_NEW_REGISTER_ACCESS
1478	/**
1479	* Register access table 0.
1480	* The MMIO offset of each entry must be a multiple of 8!
1481	*/
1482	static const IOMMUREGACC g_aRegAccess0[] =
1483	{
1484	/* MMIO off. Register name Read function Write function */
1485	{ /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
1486	{ /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
1487	{ /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
1488	{ /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
1489	{ /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
1490	{ /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
1491	{ /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
1492	{ /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
1493	{ /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
1494	{ /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
1495	{ /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
1496	{ /* 0x58 */ NULL, NULL, NULL },
1497
1498	{ /* 0x60 */ "SMI_FLT_0", NULL, NULL },
1499	{ /* 0x68 */ "SMI_FLT_1", NULL, NULL },
1500	{ /* 0x70 */ "SMI_FLT_2", NULL, NULL },
1501	{ /* 0x78 */ "SMI_FLT_3", NULL, NULL },
1502	{ /* 0x80 */ "SMI_FLT_4", NULL, NULL },
1503	{ /* 0x88 */ "SMI_FLT_5", NULL, NULL },
1504	{ /* 0x90 */ "SMI_FLT_6", NULL, NULL },
1505	{ /* 0x98 */ "SMI_FLT_7", NULL, NULL },
1506	{ /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
1507	{ /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
1508	{ /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
1509	{ /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
1510	{ /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
1511	{ /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
1512	{ /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
1513	{ /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
1514
1515	{ /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
1516	{ /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
1517	{ /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
1518	{ /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
1519
1520	{ /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1521	{ /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1522	{ /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1523	{ /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1524	{ /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1525	{ /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1526	{ /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1527
1528	{ /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
1529	{ /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
1530	{ /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
1531
1532	{ /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
1533	{ /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
1534	{ /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
1535	{ /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
1536
1537	{ /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
1538	{ /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
1539	{ /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
1540	};
1541	AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1542
1543	/**
1544	* Register access table 1.
1545	* The MMIO offset of each entry must be a multiple of 8!
1546	*/
1547	static const IOMMUREGACC g_aRegAccess1[] =
1548	{
1549	/* MMIO offset Register name Read function Write function */
1550	{ /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
1551	{ /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
1552	{ /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
1553	{ /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
1554	{ /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
1555	{ /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
1556	{ /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
1557	{ /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
1558	{ /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
1559	{ /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
1560	{ /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
1561	{ /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
1562	};
1563	AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1564
1565	/**
1566	* Register access table 2.
1567	* The MMIO offset of each entry must be a multiple of 8!
1568	*/
1569	static const IOMMUREGACC g_aRegAccess2[] =
1570	{
1571	/* MMIO offset Register name Read Function Write function */
1572	{ /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
1573
1574	{ /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
1575	{ /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
1576	{ /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
1577	{ /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
1578
1579	{ /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
1580	{ /* 0x2028 */ NULL, NULL, NULL },
1581
1582	{ /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
1583	{ /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
1584
1585	{ /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
1586	{ /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
1587
1588	{ /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
1589	{ /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
1590
1591	{ /* 0x2060 */ NULL, NULL, NULL },
1592	{ /* 0x2068 */ NULL, NULL, NULL },
1593
1594	{ /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
1595	{ /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
1596
1597	{ /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
1598	{ /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
1599	{ /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
1600	};
1601	AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1602
1603
1604	/**
1605	* Gets the register access structure given its MMIO offset.
1606	*
1607	* @returns The register access structure, or NULL if the offset is invalid.
1608	* @param off The MMIO offset of the register being accessed.
1609	*/
1610	static PCIOMMUREGACC iommuAmdGetRegAccessForOffset(uint32_t off)
1611	{
1612	/* Figure out which table the register belongs to and validate its index. */
1613	PCIOMMUREGACC pReg;
1614	if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1615	{
1616	uint32_t const idxReg = off >> 3;
1617	Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1618	pReg = &g_aRegAccess0[idxReg];
1619	}
1620	else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1621	&& off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1622	{
1623	uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1624	Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1625	pReg = &g_aRegAccess1[idxReg];
1626	}
1627	else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1628	&& off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1629	{
1630	uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1631	Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1632	pReg = &g_aRegAccess2[idxReg];
1633	}
1634	else
1635	return NULL;
1636
1637	return pReg;
1638	}
1639	#endif
1640
1641
1642	/**
1643	* Writes an IOMMU register (32-bit and 64-bit).
1644	*
1645	* @returns Strict VBox status code.
1646	* @param pDevIns The IOMMU device instance.
1647	* @param off MMIO byte offset to the register.
1648	* @param cb The size of the write access.
1649	* @param uValue The value being written.
1650	*
1651	* @thread EMT.
1652	*/
1653	static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1654	{
1655	/*
1656	* Validate the access in case of IOM bug or incorrect assumption.
1657	*/
1658	Assert(off < IOMMU_MMIO_REGION_SIZE);
1659	AssertMsgReturn(cb == 4 \|\| cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1660	AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1661
1662	Log5Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1663
1664	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1665	#ifndef IOMMU_NEW_REGISTER_ACCESS
1666	switch (off)
1667	{
1668	case IOMMU_MMIO_OFF_DEV_TAB_BAR: return iommuAmdDevTabBar_w(pDevIns, pThis, off, uValue);
1669	case IOMMU_MMIO_OFF_CMD_BUF_BAR: return iommuAmdCmdBufBar_w(pDevIns, pThis, off, uValue);
1670	case IOMMU_MMIO_OFF_EVT_LOG_BAR: return iommuAmdEvtLogBar_w(pDevIns, pThis, off, uValue);
1671	case IOMMU_MMIO_OFF_CTRL: return iommuAmdCtrl_w(pDevIns, pThis, off, uValue);
1672	case IOMMU_MMIO_OFF_EXCL_BAR: return iommuAmdExclRangeBar_w(pDevIns, pThis, off, uValue);
1673	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: return iommuAmdExclRangeLimit_w(pDevIns, pThis, off, uValue);
1674	case IOMMU_MMIO_OFF_EXT_FEAT: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1675
1676	case IOMMU_MMIO_OFF_PPR_LOG_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1677	case IOMMU_MMIO_OFF_HW_EVT_HI: return iommuAmdHwEvtHi_w(pDevIns, pThis, off, uValue);
1678	case IOMMU_MMIO_OFF_HW_EVT_LO: return iommuAmdHwEvtLo_w(pDevIns, pThis, off, uValue);
1679	case IOMMU_MMIO_OFF_HW_EVT_STATUS: return iommuAmdHwEvtStatus_w(pDevIns, pThis, off, uValue);
1680
1681	case IOMMU_MMIO_OFF_GALOG_BAR:
1682	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1683
1684	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR:
1685	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1686
1687	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1688	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1689	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1690	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1691	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1692	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1693	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7: return iommuAmdDevTabSegBar_w(pDevIns, pThis, off, uValue);
1694
1695	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT:
1696	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL:
1697	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1698
1699	case IOMMU_MMIO_OFF_MSI_VECTOR_0:
1700	case IOMMU_MMIO_OFF_MSI_VECTOR_1: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1701	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1702	{
1703	VBOXSTRICTRC rcStrict = iommuAmdMsiCapHdr_w(pDevIns, pThis, off, (uint32_t)uValue);
1704	if (cb == 4 \|\| RT_FAILURE(rcStrict))
1705	return rcStrict;
1706	uValue >>= 32;
1707	RT_FALL_THRU();
1708	}
1709	case IOMMU_MMIO_OFF_MSI_ADDR_LO: return iommuAmdMsiAddrLo_w(pDevIns, pThis, off, uValue);
1710	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1711	{
1712	VBOXSTRICTRC rcStrict = iommuAmdMsiAddrHi_w(pDevIns, pThis, off, (uint32_t)uValue);
1713	if (cb == 4 \|\| RT_FAILURE(rcStrict))
1714	return rcStrict;
1715	uValue >>= 32;
1716	RT_FALL_THRU();
1717	}
1718	case IOMMU_MMIO_OFF_MSI_DATA: return iommuAmdMsiData_w(pDevIns, pThis, off, uValue);
1719	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1720
1721	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1722
1723	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL:
1724	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL:
1725	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1726
1727	case IOMMU_MMIO_OFF_MARC_APER_BAR_0:
1728	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0:
1729	case IOMMU_MMIO_OFF_MARC_APER_LEN_0:
1730	case IOMMU_MMIO_OFF_MARC_APER_BAR_1:
1731	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1:
1732	case IOMMU_MMIO_OFF_MARC_APER_LEN_1:
1733	case IOMMU_MMIO_OFF_MARC_APER_BAR_2:
1734	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2:
1735	case IOMMU_MMIO_OFF_MARC_APER_LEN_2:
1736	case IOMMU_MMIO_OFF_MARC_APER_BAR_3:
1737	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3:
1738	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1739
1740	case IOMMU_MMIO_OFF_RSVD_REG: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1741
1742	case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: return iommuAmdCmdBufHeadPtr_w(pDevIns, pThis, off, uValue);
1743	case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: return iommuAmdCmdBufTailPtr_w(pDevIns, pThis, off, uValue);
1744	case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: return iommuAmdEvtLogHeadPtr_w(pDevIns, pThis, off, uValue);
1745	case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: return iommuAmdEvtLogTailPtr_w(pDevIns, pThis, off, uValue);
1746
1747	case IOMMU_MMIO_OFF_STATUS: return iommuAmdStatus_w(pDevIns, pThis, off, uValue);
1748
1749	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR:
1750	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR:
1751
1752	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR:
1753	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR:
1754
1755	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR:
1756	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR:
1757
1758	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR:
1759	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: return iommuAmdIgnore_w(pDevIns, pThis, off, uValue);
1760
1761	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP:
1762	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY:
1763	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY:
1764
1765	/* Not implemented. */
1766	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
1767	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
1768	{
1769	LogFunc(("Writing unsupported register: SMI filter %u -> Ignored\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
1770	return VINF_SUCCESS;
1771	}
1772
1773	/* Unknown. */
1774	default:
1775	{
1776	LogFunc(("Writing unknown register %u (%#x) with %#RX64 -> Ignored\n", off, off, uValue));
1777	return VINF_SUCCESS;
1778	}
1779	}
1780	#else
1781	PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1782	if (pReg)
1783	{ /* likely */ }
1784	else
1785	{
1786	LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
1787	return VINF_SUCCESS;
1788	}
1789
1790	/* If a write handler doesn't exist, it's either a reserved or read-only register. */
1791	if (pReg->pfnWrite)
1792	{ /* likely */ }
1793	else
1794	{
1795	LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1796	return VINF_SUCCESS;
1797	}
1798
1799	/*
1800	* If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
1801	* This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
1802	* consecutive 32-bit registers.
1803	*/
1804	if (cb == 8)
1805	{
1806	if (!(off & 7))
1807	return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1808
1809	LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1810	return VINF_SUCCESS;
1811	}
1812
1813	/* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
1814	Assert(cb == 4);
1815	if (!(off & 7))
1816	{
1817	/*
1818	* Lower 32 bits of a 64-bit register or a 32-bit register is being written.
1819	* Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1820	*/
1821	uint64_t u64Read;
1822	if (pReg->pfnRead)
1823	{
1824	VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1825	if (RT_FAILURE(rcStrict))
1826	{
1827	LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1828	return rcStrict;
1829	}
1830	}
1831	else
1832	u64Read = 0;
1833
1834	uValue = (u64Read & UINT64_C(0xffffffff00000000)) \| uValue;
1835	return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1836	}
1837
1838	/*
1839	* Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
1840	* Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1841	*/
1842	Assert(!(off & 3));
1843	Assert(off & 7);
1844	Assert(off >= 4);
1845	uint64_t u64Read;
1846	if (pReg->pfnRead)
1847	{
1848	VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1849	if (RT_FAILURE(rcStrict))
1850	{
1851	LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1852	return rcStrict;
1853	}
1854	}
1855	else
1856	u64Read = 0;
1857
1858	uValue = (uValue << 32) \| (u64Read & UINT64_C(0xffffffff));
1859	return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1860	#endif
1861	}
1862
1863
1864	/**
1865	* Reads an IOMMU register (64-bit) given its MMIO offset.
1866	*
1867	* All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1868	* boundary include the lower half of the subsequent register.
1869	*
1870	* This is because most registers are 64-bit and aligned on 8-byte boundaries but
1871	* some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1872	* software will only perform 32-bit reads on those 32-bit registers that are
1873	* aligned on 8-byte boundaries.
1874	*
1875	* @returns Strict VBox status code.
1876	* @param pDevIns The IOMMU device instance.
1877	* @param off The MMIO offset of the register in bytes.
1878	* @param puResult Where to store the value being read.
1879	*
1880	* @thread EMT.
1881	*/
1882	static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1883	{
1884	Assert(off < IOMMU_MMIO_REGION_SIZE);
1885	Assert(!(off & 7) \|\| !(off & 3));
1886
1887	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1888	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1889	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1890
1891	Log5Func(("off=%#x\n", off));
1892
1893	#ifndef IOMMU_NEW_REGISTER_ACCESS
1894	/** @todo IOMMU: fine-grained locking? */
1895	uint64_t uReg;
1896	switch (off)
1897	{
1898	case IOMMU_MMIO_OFF_DEV_TAB_BAR: uReg = pThis->aDevTabBaseAddrs[0].u64; break;
1899	case IOMMU_MMIO_OFF_CMD_BUF_BAR: uReg = pThis->CmdBufBaseAddr.u64; break;
1900	case IOMMU_MMIO_OFF_EVT_LOG_BAR: uReg = pThis->EvtLogBaseAddr.u64; break;
1901	case IOMMU_MMIO_OFF_CTRL: uReg = pThis->Ctrl.u64; break;
1902	case IOMMU_MMIO_OFF_EXCL_BAR: uReg = pThis->ExclRangeBaseAddr.u64; break;
1903	case IOMMU_MMIO_OFF_EXCL_RANGE_LIMIT: uReg = pThis->ExclRangeLimit.u64; break;
1904	case IOMMU_MMIO_OFF_EXT_FEAT: uReg = pThis->ExtFeat.u64; break;
1905
1906	case IOMMU_MMIO_OFF_PPR_LOG_BAR: uReg = pThis->PprLogBaseAddr.u64; break;
1907	case IOMMU_MMIO_OFF_HW_EVT_HI: uReg = pThis->HwEvtHi.u64; break;
1908	case IOMMU_MMIO_OFF_HW_EVT_LO: uReg = pThis->HwEvtLo; break;
1909	case IOMMU_MMIO_OFF_HW_EVT_STATUS: uReg = pThis->HwEvtStatus.u64; break;
1910
1911	case IOMMU_MMIO_OFF_GALOG_BAR: uReg = pThis->GALogBaseAddr.u64; break;
1912	case IOMMU_MMIO_OFF_GALOG_TAIL_ADDR: uReg = pThis->GALogTailAddr.u64; break;
1913
1914	case IOMMU_MMIO_OFF_PPR_LOG_B_BAR: uReg = pThis->PprLogBBaseAddr.u64; break;
1915	case IOMMU_MMIO_OFF_PPR_EVT_B_BAR: uReg = pThis->EvtLogBBaseAddr.u64; break;
1916
1917	case IOMMU_MMIO_OFF_DEV_TAB_SEG_1:
1918	case IOMMU_MMIO_OFF_DEV_TAB_SEG_2:
1919	case IOMMU_MMIO_OFF_DEV_TAB_SEG_3:
1920	case IOMMU_MMIO_OFF_DEV_TAB_SEG_4:
1921	case IOMMU_MMIO_OFF_DEV_TAB_SEG_5:
1922	case IOMMU_MMIO_OFF_DEV_TAB_SEG_6:
1923	case IOMMU_MMIO_OFF_DEV_TAB_SEG_7:
1924	{
1925	uint8_t const offDevTabSeg = (off - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1926	uint8_t const idxDevTabSeg = offDevTabSeg + 1;
1927	Assert(idxDevTabSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1928	uReg = pThis->aDevTabBaseAddrs[idxDevTabSeg].u64;
1929	break;
1930	}
1931
1932	case IOMMU_MMIO_OFF_DEV_SPECIFIC_FEAT: uReg = pThis->DevSpecificFeat.u64; break;
1933	case IOMMU_MMIO_OFF_DEV_SPECIFIC_CTRL: uReg = pThis->DevSpecificCtrl.u64; break;
1934	case IOMMU_MMIO_OFF_DEV_SPECIFIC_STATUS: uReg = pThis->DevSpecificStatus.u64; break;
1935
1936	case IOMMU_MMIO_OFF_MSI_VECTOR_0: uReg = pThis->MiscInfo.u64; break;
1937	case IOMMU_MMIO_OFF_MSI_VECTOR_1: uReg = pThis->MiscInfo.au32[1]; break;
1938	case IOMMU_MMIO_OFF_MSI_CAP_HDR:
1939	{
1940	uint32_t const uMsiCapHdr = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1941	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1942	uReg = RT_MAKE_U64(uMsiCapHdr, uMsiAddrLo);
1943	break;
1944	}
1945	case IOMMU_MMIO_OFF_MSI_ADDR_LO:
1946	{
1947	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1948	break;
1949	}
1950	case IOMMU_MMIO_OFF_MSI_ADDR_HI:
1951	{
1952	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1953	uint32_t const uMsiData = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1954	uReg = RT_MAKE_U64(uMsiAddrHi, uMsiData);
1955	break;
1956	}
1957	case IOMMU_MMIO_OFF_MSI_DATA:
1958	{
1959	uReg = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1960	break;
1961	}
1962	case IOMMU_MMIO_OFF_MSI_MAPPING_CAP_HDR:
1963	{
1964	/*
1965	* The PCI spec. lists MSI Mapping Capability 08H as related to HyperTransport capability.
1966	* The AMD IOMMU spec. fails to mention it explicitly and lists values for this register as
1967	* though HyperTransport is supported. We don't support HyperTransport, we thus just return
1968	* 0 for this register.
1969	*/
1970	uReg = RT_MAKE_U64(0, pThis->PerfOptCtrl.u32);
1971	break;
1972	}
1973
1974	case IOMMU_MMIO_OFF_PERF_OPT_CTRL: uReg = pThis->PerfOptCtrl.u32; break;
1975
1976	case IOMMU_MMIO_OFF_XT_GEN_INTR_CTRL: uReg = pThis->XtGenIntrCtrl.u64; break;
1977	case IOMMU_MMIO_OFF_XT_PPR_INTR_CTRL: uReg = pThis->XtPprIntrCtrl.u64; break;
1978	case IOMMU_MMIO_OFF_XT_GALOG_INT_CTRL: uReg = pThis->XtGALogIntrCtrl.u64; break;
1979
1980	case IOMMU_MMIO_OFF_MARC_APER_BAR_0: uReg = pThis->aMarcApers[0].Base.u64; break;
1981	case IOMMU_MMIO_OFF_MARC_APER_RELOC_0: uReg = pThis->aMarcApers[0].Reloc.u64; break;
1982	case IOMMU_MMIO_OFF_MARC_APER_LEN_0: uReg = pThis->aMarcApers[0].Length.u64; break;
1983	case IOMMU_MMIO_OFF_MARC_APER_BAR_1: uReg = pThis->aMarcApers[1].Base.u64; break;
1984	case IOMMU_MMIO_OFF_MARC_APER_RELOC_1: uReg = pThis->aMarcApers[1].Reloc.u64; break;
1985	case IOMMU_MMIO_OFF_MARC_APER_LEN_1: uReg = pThis->aMarcApers[1].Length.u64; break;
1986	case IOMMU_MMIO_OFF_MARC_APER_BAR_2: uReg = pThis->aMarcApers[2].Base.u64; break;
1987	case IOMMU_MMIO_OFF_MARC_APER_RELOC_2: uReg = pThis->aMarcApers[2].Reloc.u64; break;
1988	case IOMMU_MMIO_OFF_MARC_APER_LEN_2: uReg = pThis->aMarcApers[2].Length.u64; break;
1989	case IOMMU_MMIO_OFF_MARC_APER_BAR_3: uReg = pThis->aMarcApers[3].Base.u64; break;
1990	case IOMMU_MMIO_OFF_MARC_APER_RELOC_3: uReg = pThis->aMarcApers[3].Reloc.u64; break;
1991	case IOMMU_MMIO_OFF_MARC_APER_LEN_3: uReg = pThis->aMarcApers[3].Length.u64; break;
1992
1993	case IOMMU_MMIO_OFF_RSVD_REG: uReg = pThis->RsvdReg; break;
1994
1995	case IOMMU_MMIO_OFF_CMD_BUF_HEAD_PTR: uReg = pThis->CmdBufHeadPtr.u64; break;
1996	case IOMMU_MMIO_OFF_CMD_BUF_TAIL_PTR: uReg = pThis->CmdBufTailPtr.u64; break;
1997	case IOMMU_MMIO_OFF_EVT_LOG_HEAD_PTR: uReg = pThis->EvtLogHeadPtr.u64; break;
1998	case IOMMU_MMIO_OFF_EVT_LOG_TAIL_PTR: uReg = pThis->EvtLogTailPtr.u64; break;
1999
2000	case IOMMU_MMIO_OFF_STATUS: uReg = pThis->Status.u64; break;
2001
2002	case IOMMU_MMIO_OFF_PPR_LOG_HEAD_PTR: uReg = pThis->PprLogHeadPtr.u64; break;
2003	case IOMMU_MMIO_OFF_PPR_LOG_TAIL_PTR: uReg = pThis->PprLogTailPtr.u64; break;
2004
2005	case IOMMU_MMIO_OFF_GALOG_HEAD_PTR: uReg = pThis->GALogHeadPtr.u64; break;
2006	case IOMMU_MMIO_OFF_GALOG_TAIL_PTR: uReg = pThis->GALogTailPtr.u64; break;
2007
2008	case IOMMU_MMIO_OFF_PPR_LOG_B_HEAD_PTR: uReg = pThis->PprLogBHeadPtr.u64; break;
2009	case IOMMU_MMIO_OFF_PPR_LOG_B_TAIL_PTR: uReg = pThis->PprLogBTailPtr.u64; break;
2010
2011	case IOMMU_MMIO_OFF_EVT_LOG_B_HEAD_PTR: uReg = pThis->EvtLogBHeadPtr.u64; break;
2012	case IOMMU_MMIO_OFF_EVT_LOG_B_TAIL_PTR: uReg = pThis->EvtLogBTailPtr.u64; break;
2013
2014	case IOMMU_MMIO_OFF_PPR_LOG_AUTO_RESP: uReg = pThis->PprLogAutoResp.u64; break;
2015	case IOMMU_MMIO_OFF_PPR_LOG_OVERFLOW_EARLY: uReg = pThis->PprLogOverflowEarly.u64; break;
2016	case IOMMU_MMIO_OFF_PPR_LOG_B_OVERFLOW_EARLY: uReg = pThis->PprLogBOverflowEarly.u64; break;
2017
2018	/* Not implemented. */
2019	case IOMMU_MMIO_OFF_SMI_FLT_FIRST:
2020	case IOMMU_MMIO_OFF_SMI_FLT_LAST:
2021	{
2022	LogFunc(("Reading unsupported register: SMI filter %u\n", (off - IOMMU_MMIO_OFF_SMI_FLT_FIRST) >> 3));
2023	uReg = 0;
2024	break;
2025	}
2026
2027	/* Unknown. */
2028	default:
2029	{
2030	LogFunc(("Reading unknown register %u (%#x) -> 0\n", off, off));
2031	uReg = 0;
2032	return VINF_IOM_MMIO_UNUSED_00;
2033	}
2034	}
2035
2036	*puResult = uReg;
2037	return VINF_SUCCESS;
2038	#else
2039	NOREF(pPciDev);
2040	PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
2041	if (pReg)
2042	{ /* likely */ }
2043	else
2044	{
2045	LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2046	return VINF_IOM_MMIO_UNUSED_FF;
2047	}
2048
2049	/* If a read handler doesn't exist, it's a reserved or unknown register. */
2050	if (pReg->pfnRead)
2051	{ /* likely */ }
2052	else
2053	{
2054	LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2055	return VINF_IOM_MMIO_UNUSED_00;
2056	}
2057
2058	/*
2059	* If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2060	* The caller takes care of truncating upper 32 bits for 32-bit reads.
2061	*/
2062	if (!(off & 7))
2063	return pReg->pfnRead(pDevIns, pThis, off, puResult);
2064
2065	/*
2066	* High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2067	* Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2068	*/
2069	Assert(!(off & 3));
2070	Assert(off & 7);
2071	Assert(off >= 4);
2072	VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2073	if (RT_SUCCESS(rcStrict))
2074	*puResult >>= 32;
2075	else
2076	{
2077	*puResult = 0;
2078	LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2079	}
2080
2081	return rcStrict;
2082	#endif
2083	}
2084
2085
2086	/**
2087	* Raises the MSI interrupt for the IOMMU device.
2088	*
2089	* @param pDevIns The IOMMU device instance.
2090	*
2091	* @thread Any.
2092	* @remarks The IOMMU lock may or may not be held.
2093	*/
2094	static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
2095	{
2096	LogFlowFunc(("\n"));
2097	if (iommuAmdIsMsiEnabled(pDevIns))
2098	{
2099	LogFunc(("Raising MSI\n"));
2100	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2101	}
2102	}
2103
2104	#if 0
2105	/**
2106	* Clears the MSI interrupt for the IOMMU device.
2107	*
2108	* @param pDevIns The IOMMU device instance.
2109	*
2110	* @thread Any.
2111	* @remarks The IOMMU lock may or may not be held.
2112	*/
2113	static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
2114	{
2115	if (iommuAmdIsMsiEnabled(pDevIns))
2116	PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2117	}
2118	#endif
2119
2120	/**
2121	* Writes an entry to the event log in memory.
2122	*
2123	* @returns VBox status code.
2124	* @param pDevIns The IOMMU device instance.
2125	* @param pEvent The event to log.
2126	*
2127	* @thread Any.
2128	*/
2129	static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2130	{
2131	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2132
2133	IOMMU_ASSERT_LOCKED(pDevIns);
2134
2135	/* Check if event logging is active and the log has not overflowed. */
2136	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2137	if ( Status.n.u1EvtLogRunning
2138	&& !Status.n.u1EvtOverflow)
2139	{
2140	uint32_t const cbEvt = sizeof(*pEvent);
2141
2142	/* Get the offset we need to write the event to in memory (circular buffer offset). */
2143	uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2144	Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2145
2146	/* Ensure we have space in the event log. */
2147	uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2148	uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2149	if (cEvts + 1 < cMaxEvts)
2150	{
2151	/* Write the event log entry to memory. */
2152	RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2153	RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2154	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2155	if (RT_FAILURE(rc))
2156	LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2157
2158	/* Increment the event log tail pointer. */
2159	uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2160	pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2161
2162	/* Indicate that an event log entry was written. */
2163	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2164
2165	/* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2166	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2167	if (Ctrl.n.u1EvtIntrEn)
2168	iommuAmdRaiseMsiInterrupt(pDevIns);
2169	}
2170	else
2171	{
2172	/* Indicate that the event log has overflowed. */
2173	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2174
2175	/* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2176	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2177	if (Ctrl.n.u1EvtIntrEn)
2178	iommuAmdRaiseMsiInterrupt(pDevIns);
2179	}
2180	}
2181
2182	return VINF_SUCCESS;
2183	}
2184
2185
2186	/**
2187	* Sets an event in the hardware error registers.
2188	*
2189	* @param pDevIns The IOMMU device instance.
2190	* @param pEvent The event.
2191	*
2192	* @thread Any.
2193	*/
2194	static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2195	{
2196	IOMMU_ASSERT_LOCKED(pDevIns);
2197
2198	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2199	if (pThis->ExtFeat.n.u1HwErrorSup)
2200	{
2201	if (pThis->HwEvtStatus.n.u1Valid)
2202	pThis->HwEvtStatus.n.u1Overflow = 1;
2203	pThis->HwEvtStatus.n.u1Valid = 1;
2204	pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2205	pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2206	Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2207	\|\| pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2208	\|\| pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2209	}
2210	}
2211
2212
2213	/**
2214	* Initializes a PAGE_TAB_HARDWARE_ERROR event.
2215	*
2216	* @param uDevId The device ID.
2217	* @param uDomainId The domain ID.
2218	* @param GCPhysPtEntity The system physical address of the page table
2219	* entity.
2220	* @param enmOp The IOMMU operation being performed.
2221	* @param pEvtPageTabHwErr Where to store the initialized event.
2222	*/
2223	static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2224	PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2225	{
2226	memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2227	pEvtPageTabHwErr->n.u16DevId = uDevId;
2228	pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
2229	pEvtPageTabHwErr->n.u1GuestOrNested = 0;
2230	pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2231	pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2232	pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2233	pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2234	pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
2235	pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
2236	}
2237
2238
2239	/**
2240	* Raises a PAGE_TAB_HARDWARE_ERROR event.
2241	*
2242	* @param pDevIns The IOMMU device instance.
2243	* @param enmOp The IOMMU operation being performed.
2244	* @param pEvtPageTabHwErr The page table hardware error event.
2245	*
2246	* @thread Any.
2247	*/
2248	static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2249	{
2250	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
2251	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
2252
2253	IOMMU_LOCK_NORET(pDevIns);
2254
2255	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2256	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2257	if (enmOp != IOMMUOP_CMD)
2258	iommuAmdSetPciTargetAbort(pDevIns);
2259
2260	IOMMU_UNLOCK(pDevIns);
2261
2262	LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
2263	pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
2264	pEvtPageTabHwErr->n.u2Type));
2265	}
2266
2267
2268	#ifdef IN_RING3
2269	/**
2270	* Initializes a COMMAND_HARDWARE_ERROR event.
2271	*
2272	* @param GCPhysAddr The system physical address the IOMMU attempted to access.
2273	* @param pEvtCmdHwErr Where to store the initialized event.
2274	*/
2275	static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2276	{
2277	memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
2278	pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
2279	pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
2280	pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
2281	}
2282
2283
2284	/**
2285	* Raises a COMMAND_HARDWARE_ERROR event.
2286	*
2287	* @param pDevIns The IOMMU device instance.
2288	* @param pEvtCmdHwErr The command hardware error event.
2289	*
2290	* @thread Any.
2291	*/
2292	static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2293	{
2294	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
2295	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
2296	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2297
2298	IOMMU_LOCK_NORET(pDevIns);
2299
2300	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2301	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2302	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2303
2304	IOMMU_UNLOCK(pDevIns);
2305
2306	LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
2307	}
2308	#endif /* IN_RING3 */
2309
2310
2311	/**
2312	* Initializes a DEV_TAB_HARDWARE_ERROR event.
2313	*
2314	* @param uDevId The device ID.
2315	* @param GCPhysDte The system physical address of the failed device table
2316	* access.
2317	* @param enmOp The IOMMU operation being performed.
2318	* @param pEvtDevTabHwErr Where to store the initialized event.
2319	*/
2320	static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
2321	PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2322	{
2323	memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
2324	pEvtDevTabHwErr->n.u16DevId = uDevId;
2325	pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2326	/** @todo IOMMU: Any other transaction type that can set read/write bit? */
2327	pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2328	pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2329	pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2330	pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
2331	pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
2332	}
2333
2334
2335	/**
2336	* Raises a DEV_TAB_HARDWARE_ERROR event.
2337	*
2338	* @param pDevIns The IOMMU device instance.
2339	* @param enmOp The IOMMU operation being performed.
2340	* @param pEvtDevTabHwErr The device table hardware error event.
2341	*
2342	* @thread Any.
2343	*/
2344	static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2345	{
2346	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2347	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2348
2349	IOMMU_LOCK_NORET(pDevIns);
2350
2351	iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2352	iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2353	if (enmOp != IOMMUOP_CMD)
2354	iommuAmdSetPciTargetAbort(pDevIns);
2355
2356	IOMMU_UNLOCK(pDevIns);
2357
2358	LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2359	pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2360	}
2361
2362	#ifdef IN_RING3
2363	/**
2364	* Initializes an ILLEGAL_COMMAND_ERROR event.
2365	*
2366	* @param GCPhysCmd The system physical address of the failed command
2367	* access.
2368	* @param pEvtIllegalCmd Where to store the initialized event.
2369	*/
2370	static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2371	{
2372	Assert(!(GCPhysCmd & UINT64_C(0xf)));
2373	memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2374	pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2375	pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2376	}
2377
2378
2379	/**
2380	* Raises an ILLEGAL_COMMAND_ERROR event.
2381	*
2382	* @param pDevIns The IOMMU device instance.
2383	* @param pEvtIllegalCmd The illegal command error event.
2384	*/
2385	static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2386	{
2387	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2388	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2389	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2390
2391	IOMMU_LOCK_NORET(pDevIns);
2392
2393	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2394	ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2395
2396	IOMMU_UNLOCK(pDevIns);
2397
2398	LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2399	}
2400	#endif /* IN_RING3 */
2401
2402
2403	/**
2404	* Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2405	*
2406	* @param uDevId The device ID.
2407	* @param uIova The I/O virtual address.
2408	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2409	* event was caused by an invalid level encoding in the
2410	* DTE.
2411	* @param enmOp The IOMMU operation being performed.
2412	* @param pEvtIllegalDte Where to store the initialized event.
2413	*/
2414	static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2415	PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2416	{
2417	memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2418	pEvtIllegalDte->n.u16DevId = uDevId;
2419	pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2420	pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2421	pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2422	pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2423	pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2424	pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2425	/** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2426	* IOMMU spec here but not for this field for I/O page fault event. */
2427	Assert(!(uIova & UINT64_C(0x3)));
2428	}
2429
2430
2431	/**
2432	* Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2433	*
2434	* @param pDevIns The IOMMU instance data.
2435	* @param enmOp The IOMMU operation being performed.
2436	* @param pEvtIllegalDte The illegal device table entry event.
2437	* @param enmEvtType The illegal device table entry event type.
2438	*
2439	* @thread Any.
2440	*/
2441	static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2442	EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2443	{
2444	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2445	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2446
2447	IOMMU_LOCK_NORET(pDevIns);
2448
2449	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2450	if (enmOp != IOMMUOP_CMD)
2451	iommuAmdSetPciTargetAbort(pDevIns);
2452
2453	IOMMU_UNLOCK(pDevIns);
2454
2455	LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2456	pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2457	NOREF(enmEvtType);
2458	}
2459
2460
2461	/**
2462	* Initializes an IO_PAGE_FAULT event.
2463	*
2464	* @param uDevId The device ID.
2465	* @param uDomainId The domain ID.
2466	* @param uIova The I/O virtual address being accessed.
2467	* @param fPresent Transaction to a page marked as present (including
2468	* DTE.V=1) or interrupt marked as remapped
2469	* (IRTE.RemapEn=1).
2470	* @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2471	* the I/O page fault was caused by invalid level
2472	* encoding.
2473	* @param fPermDenied Permission denied for the address being accessed.
2474	* @param enmOp The IOMMU operation being performed.
2475	* @param pEvtIoPageFault Where to store the initialized event.
2476	*/
2477	static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2478	bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2479	{
2480	Assert(!fPermDenied \|\| fPresent);
2481	memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2482	pEvtIoPageFault->n.u16DevId = uDevId;
2483	//pEvtIoPageFault->n.u4PasidHi = 0;
2484	pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2485	//pEvtIoPageFault->n.u1GuestOrNested = 0;
2486	//pEvtIoPageFault->n.u1NoExecute = 0;
2487	//pEvtIoPageFault->n.u1User = 0;
2488	pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2489	pEvtIoPageFault->n.u1Present = fPresent;
2490	pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2491	pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2492	pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2493	pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2494	pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2495	pEvtIoPageFault->n.u64Addr = uIova;
2496	}
2497
2498
2499	/**
2500	* Raises an IO_PAGE_FAULT event.
2501	*
2502	* @param pDevIns The IOMMU instance data.
2503	* @param pDte The device table entry. Optional, can be NULL
2504	* depending on @a enmOp.
2505	* @param pIrte The interrupt remapping table entry. Optional, can
2506	* be NULL depending on @a enmOp.
2507	* @param enmOp The IOMMU operation being performed.
2508	* @param pEvtIoPageFault The I/O page fault event.
2509	* @param enmEvtType The I/O page fault event type.
2510	*
2511	* @thread Any.
2512	*/
2513	static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2514	PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2515	{
2516	AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2517	PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2518
2519	IOMMU_LOCK_NORET(pDevIns);
2520
2521	bool fSuppressEvtLogging = false;
2522	if ( enmOp == IOMMUOP_MEM_READ
2523	\|\| enmOp == IOMMUOP_MEM_WRITE)
2524	{
2525	if ( pDte
2526	&& pDte->n.u1Valid)
2527	{
2528	fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2529	/** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2530	* suppression. Perhaps will be possible when we complete IOTLB/cache
2531	* handling. */
2532	}
2533	}
2534	else if (enmOp == IOMMUOP_INTR_REQ)
2535	{
2536	if ( pDte
2537	&& pDte->n.u1IntrMapValid)
2538	fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2539
2540	if ( !fSuppressEvtLogging
2541	&& pIrte)
2542	fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2543	}
2544	/* else: Events are never suppressed for commands. */
2545
2546	switch (enmEvtType)
2547	{
2548	case kIoPageFaultType_PermDenied:
2549	{
2550	/* Cannot be triggered by a command. */
2551	Assert(enmOp != IOMMUOP_CMD);
2552	RT_FALL_THRU();
2553	}
2554	case kIoPageFaultType_DteRsvdPagingMode:
2555	case kIoPageFaultType_PteInvalidPageSize:
2556	case kIoPageFaultType_PteInvalidLvlEncoding:
2557	case kIoPageFaultType_SkippedLevelIovaNotZero:
2558	case kIoPageFaultType_PteRsvdNotZero:
2559	case kIoPageFaultType_PteValidNotSet:
2560	case kIoPageFaultType_DteTranslationDisabled:
2561	case kIoPageFaultType_PasidInvalidRange:
2562	{
2563	/*
2564	* For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2565	* create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
2566	*/
2567	if (enmOp != IOMMUOP_TRANSLATE_REQ)
2568	{
2569	if (!fSuppressEvtLogging)
2570	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2571	if (enmOp != IOMMUOP_CMD)
2572	iommuAmdSetPciTargetAbort(pDevIns);
2573	}
2574	break;
2575	}
2576
2577	case kIoPageFaultType_UserSupervisor:
2578	{
2579	/* Access is blocked and only creates an event log entry. */
2580	if (!fSuppressEvtLogging)
2581	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2582	break;
2583	}
2584
2585	case kIoPageFaultType_IrteAddrInvalid:
2586	case kIoPageFaultType_IrteRsvdNotZero:
2587	case kIoPageFaultType_IrteRemapEn:
2588	case kIoPageFaultType_IrteRsvdIntType:
2589	case kIoPageFaultType_IntrReqAborted:
2590	case kIoPageFaultType_IntrWithPasid:
2591	{
2592	/* Only trigerred by interrupt requests. */
2593	Assert(enmOp == IOMMUOP_INTR_REQ);
2594	if (!fSuppressEvtLogging)
2595	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2596	iommuAmdSetPciTargetAbort(pDevIns);
2597	break;
2598	}
2599
2600	case kIoPageFaultType_SmiFilterMismatch:
2601	{
2602	/* Not supported and probably will never be, assert. */
2603	AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2604	break;
2605	}
2606
2607	case kIoPageFaultType_DevId_Invalid:
2608	{
2609	/* Cannot be triggered by a command. */
2610	Assert(enmOp != IOMMUOP_CMD);
2611	Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2612	if (!fSuppressEvtLogging)
2613	iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2614	if ( enmOp == IOMMUOP_MEM_READ
2615	\|\| enmOp == IOMMUOP_MEM_WRITE)
2616	iommuAmdSetPciTargetAbort(pDevIns);
2617	break;
2618	}
2619	}
2620
2621	IOMMU_UNLOCK(pDevIns);
2622	}
2623
2624
2625	/**
2626	* Returns whether the I/O virtual address is to be excluded from translation and
2627	* permission checks.
2628	*
2629	* @returns @c true if the DVA is excluded, @c false otherwise.
2630	* @param pThis The IOMMU device state.
2631	* @param pDte The device table entry.
2632	* @param uIova The I/O virtual address.
2633	*
2634	* @remarks Ensure the exclusion range is enabled prior to calling this function.
2635	*
2636	* @thread Any.
2637	*/
2638	static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2639	{
2640	/* Ensure the exclusion range is enabled. */
2641	Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2642
2643	/* Check if the IOVA falls within the exclusion range. */
2644	uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2645	uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2646	if (uIovaExclLast - uIova >= uIovaExclFirst)
2647	{
2648	/* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2649	if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2650	\|\| pDte->n.u1AllowExclusion)
2651	return true;
2652	}
2653	return false;
2654	}
2655
2656
2657	/**
2658	* Reads a device table entry from guest memory given the device ID.
2659	*
2660	* @returns VBox status code.
2661	* @param pDevIns The IOMMU device instance.
2662	* @param uDevId The device ID.
2663	* @param enmOp The IOMMU operation being performed.
2664	* @param pDte Where to store the device table entry.
2665	*
2666	* @thread Any.
2667	*/
2668	static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2669	{
2670	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2671	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2672
2673	/* Figure out which device table segment is being accessed. */
2674	uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2675	Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2676
2677	uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2678	Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2679	AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
2680
2681	RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2682	uint32_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2683	RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2684
2685	/* Ensure the DTE falls completely within the device table segment. */
2686	uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
2687	if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
2688	{
2689	/* Read the device table entry from guest memory. */
2690	Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2691	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2692	if (RT_SUCCESS(rc))
2693	return rc;
2694
2695	/* Raise a device table hardware error. */
2696	LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2697
2698	EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2699	iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2700	iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2701	return VERR_IOMMU_DTE_READ_FAILED;
2702	}
2703
2704	/* Raise an I/O page fault for out-of-bounds acccess. */
2705	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2706	iommuAmdInitIoPageFaultEvent(uDevId, 0 /* uDomainId /, 0 / uIova /, false / fPresent /, false / fRsvdNotZero */,
2707	false /* fPermDenied */, enmOp, &EvtIoPageFault);
2708	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_DevId_Invalid);
2709	return VERR_IOMMU_DTE_BAD_OFFSET;
2710	}
2711
2712
2713	/**
2714	* Walks the I/O page table to translate the I/O virtual address to a system
2715	* physical address.
2716	*
2717	* @returns VBox status code.
2718	* @param pDevIns The IOMMU device instance.
2719	* @param uIova The I/O virtual address to translate. Must be 4K aligned.
2720	* @param uDevId The device ID.
2721	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2722	* permissions for the access being made.
2723	* @param pDte The device table entry.
2724	* @param enmOp The IOMMU operation being performed.
2725	* @param pWalkResult Where to store the results of the I/O page walk. This is
2726	* only updated when VINF_SUCCESS is returned.
2727	*
2728	* @thread Any.
2729	*/
2730	static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2731	IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2732	{
2733	Assert(pDte->n.u1Valid);
2734	Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2735
2736	/* If the translation is not valid, raise an I/O page fault. */
2737	if (pDte->n.u1TranslationValid)
2738	{ /* likely */ }
2739	else
2740	{
2741	/** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2742	* doesn't explicitly say whether an I/O page fault is raised. From other
2743	* places in the spec. it seems early page walk terminations (starting with
2744	* the DTE) return the state computed so far and raises an I/O page fault. So
2745	* returning an invalid translation rather than skipping translation. */
2746	LogFunc(("Translation valid bit not set -> IOPF\n"));
2747	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2748	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
2749	false /* fPermDenied */, enmOp, &EvtIoPageFault);
2750	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2751	kIoPageFaultType_DteTranslationDisabled);
2752	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2753	}
2754
2755	/* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2756	uint8_t const uMaxLevel = pDte->n.u3Mode;
2757	if (uMaxLevel != 0)
2758	{ /* likely */ }
2759	else
2760	{
2761	uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2762	if ((fAccess & fDtePerm) != fAccess)
2763	{
2764	LogFunc(("Access denied for IOVA %#RX64. uDevId=%#x fAccess=%#x fDtePerm=%#x\n", uIova, uDevId, fAccess, fDtePerm));
2765	return VERR_IOMMU_ADDR_ACCESS_DENIED;
2766	}
2767	pWalkResult->GCPhysSpa = uIova;
2768	pWalkResult->cShift = 0;
2769	pWalkResult->fIoPerm = fDtePerm;
2770	return VINF_SUCCESS;
2771	}
2772
2773	/* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2774	if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2775	{ /* likely */ }
2776	else
2777	{
2778	/** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2779	* raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2780	* I'm just going with I/O page fault. */
2781	LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
2782	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2783	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
2784	false /* fPermDenied */, enmOp, &EvtIoPageFault);
2785	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2786	kIoPageFaultType_PteInvalidLvlEncoding);
2787	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2788	}
2789
2790	/* Check permissions bits of the root page table. */
2791	uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2792	if ((fAccess & fRootPtePerm) == fAccess)
2793	{ /* likely */ }
2794	else
2795	{
2796	LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2797	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2798	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
2799	true /* fPermDenied */, enmOp, &EvtIoPageFault);
2800	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2801	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2802	}
2803
2804	/** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2805	* function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2806	* accesses from the 2nd page. We can avoid re-checking the DTE root-page
2807	* table entry every time. Not sure if it's worth optimizing that case now
2808	* or if at all. */
2809
2810	/* The virtual address bits indexing table. */
2811	static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2812	static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2813	UINT64_C(0x00000000001ff000),
2814	UINT64_C(0x000000003fe00000),
2815	UINT64_C(0x0000007fc0000000),
2816	UINT64_C(0x0000ff8000000000),
2817	UINT64_C(0x01ff000000000000),
2818	UINT64_C(0xfe00000000000000),
2819	UINT64_C(0x0000000000000000) };
2820	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2821	AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2822
2823	/* Traverse the I/O page table starting with the page directory in the DTE. */
2824	IOPTENTITY_T PtEntity;
2825	PtEntity.u64 = pDte->au64[0];
2826	for (;;)
2827	{
2828	/* Figure out the system physical address of the page table at the current level. */
2829	uint8_t const uLevel = PtEntity.n.u3NextLevel;
2830
2831	/* Read the page table entity at the current level. */
2832	{
2833	Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2834	Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2835	uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2836	uint64_t const offPte = idxPte << 3;
2837	RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2838	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2839	if (RT_FAILURE(rc))
2840	{
2841	LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2842	EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2843	iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2844	iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2845	return VERR_IOMMU_IPE_2;
2846	}
2847	}
2848
2849	/* Check present bit. */
2850	if (PtEntity.n.u1Present)
2851	{ /* likely */ }
2852	else
2853	{
2854	LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
2855	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2856	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent /, false / fRsvdNotZero */,
2857	false /* fPermDenied */, enmOp, &EvtIoPageFault);
2858	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2859	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2860	}
2861
2862	/* Check permission bits. */
2863	uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2864	if ((fAccess & fPtePerm) == fAccess)
2865	{ /* likely */ }
2866	else
2867	{
2868	LogFunc(("Page table entry access denied (uDevId=%#x fAccess=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fAccess, fPtePerm));
2869	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2870	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
2871	true /* fPermDenied */, enmOp, &EvtIoPageFault);
2872	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2873	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2874	}
2875
2876	/* If this is a PTE, we're at the final level and we're done. */
2877	uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2878	if (uNextLevel == 0)
2879	{
2880	/* The page size of the translation is the default (4K). */
2881	pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2882	pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2883	pWalkResult->fIoPerm = fPtePerm;
2884	return VINF_SUCCESS;
2885	}
2886	if (uNextLevel == 7)
2887	{
2888	/* The default page size of the translation is overridden. */
2889	RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2890	uint8_t cShift = X86_PAGE_4K_SHIFT;
2891	while (GCPhysPte & RT_BIT_64(cShift++))
2892	;
2893
2894	/* The page size must be larger than the default size and lower than the default size of the higher level. */
2895	Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2896	if ( cShift > s_acIovaLevelShifts[uLevel]
2897	&& cShift < s_acIovaLevelShifts[uLevel + 1])
2898	{
2899	pWalkResult->GCPhysSpa = GCPhysPte;
2900	pWalkResult->cShift = cShift;
2901	pWalkResult->fIoPerm = fPtePerm;
2902	return VINF_SUCCESS;
2903	}
2904
2905	LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2906	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2907	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
2908	false /* fPermDenied */, enmOp, &EvtIoPageFault);
2909	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2910	kIoPageFaultType_PteInvalidPageSize);
2911	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2912	}
2913
2914	/* Validate the next level encoding of the PDE. */
2915	#if IOMMU_MAX_HOST_PT_LEVEL < 6
2916	if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2917	{ /* likely */ }
2918	else
2919	{
2920	LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2921	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2922	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
2923	false /* fPermDenied */, enmOp, &EvtIoPageFault);
2924	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2925	kIoPageFaultType_PteInvalidLvlEncoding);
2926	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2927	}
2928	#else
2929	Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2930	#endif
2931
2932	/* Validate level transition. */
2933	if (uNextLevel < uLevel)
2934	{ /* likely */ }
2935	else
2936	{
2937	LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2938	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2939	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
2940	false /* fPermDenied */, enmOp, &EvtIoPageFault);
2941	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2942	kIoPageFaultType_PteInvalidLvlEncoding);
2943	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2944	}
2945
2946	/* Ensure IOVA bits of skipped levels are zero. */
2947	Assert(uLevel > 0);
2948	uint64_t uIovaSkipMask = 0;
2949	for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2950	uIovaSkipMask \|= s_auIovaLevelMasks[idxLevel];
2951	if (!(uIova & uIovaSkipMask))
2952	{ /* likely */ }
2953	else
2954	{
2955	LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2956	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2957	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent /, false / fRsvdNotZero */,
2958	false /* fPermDenied */, enmOp, &EvtIoPageFault);
2959	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2960	kIoPageFaultType_SkippedLevelIovaNotZero);
2961	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2962	}
2963
2964	/* Continue with traversing the page directory at this level. */
2965	}
2966	}
2967
2968
2969	/**
2970	* Looks up an I/O virtual address from the device table.
2971	*
2972	* @returns VBox status code.
2973	* @param pDevIns The IOMMU instance data.
2974	* @param uDevId The device ID.
2975	* @param uIova The I/O virtual address to lookup.
2976	* @param cbAccess The size of the access.
2977	* @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2978	* permissions for the access being made.
2979	* @param enmOp The IOMMU operation being performed.
2980	* @param pGCPhysSpa Where to store the translated system physical address. Only
2981	* valid when translation succeeds and VINF_SUCCESS is
2982	* returned!
2983	*
2984	* @thread Any.
2985	*/
2986	static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2987	IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2988	{
2989	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2990
2991	/* Read the device table entry from memory. */
2992	DTE_T Dte;
2993	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2994	if (RT_SUCCESS(rc))
2995	{
2996	/* If the DTE is not valid, addresses are forwarded without translation */
2997	if (Dte.n.u1Valid)
2998	{ /* likely */ }
2999	else
3000	{
3001	/** @todo IOMMU: Add to IOLTB cache. */
3002	*pGCPhysSpa = uIova;
3003	return VINF_SUCCESS;
3004	}
3005
3006	/* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3007	uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3008	uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3009	if (RT_LIKELY( !fRsvd0
3010	&& !fRsvd1))
3011	{ /* likely */ }
3012	else
3013	{
3014	LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
3015	EVT_ILLEGAL_DTE_T Event;
3016	iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
3017	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3018	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3019	}
3020
3021	/* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
3022	if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable /** @todo lock or make atomic read? */
3023	\|\| !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
3024	{ /* likely */ }
3025	else
3026	{
3027	/** @todo IOMMU: Add to IOLTB cache. */
3028	*pGCPhysSpa = uIova;
3029	return VINF_SUCCESS;
3030	}
3031
3032	/** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
3033	* below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
3034
3035	uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
3036	uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
3037	uint64_t cbRemaining = cbAccess;
3038	for (;;)
3039	{
3040	/* Walk the I/O page tables to translate the IOVA and check permission for the access. */
3041	IOWALKRESULT WalkResult;
3042	rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
3043	if (RT_SUCCESS(rc))
3044	{
3045	/** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
3046
3047	/* If translation is disabled for this device (root paging mode is 0), we're done. */
3048	if (WalkResult.cShift == 0)
3049	{
3050	*pGCPhysSpa = uIova;
3051	break;
3052	}
3053
3054	/* Store the translated base address before continuing to check permissions for any more pages. */
3055	Assert(WalkResult.cShift >= X86_PAGE_4K_SHIFT);
3056	if (cbRemaining == cbAccess)
3057	{
3058	uint64_t const offMask = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
3059	uint64_t const offSpa = uIova & offMask;
3060	*pGCPhysSpa = WalkResult.GCPhysSpa \| offSpa;
3061	}
3062
3063	/* If the access exceeds the page size, check permissions for the subsequent page. */
3064	uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
3065	if (cbRemaining > cbPhysPage - offIova)
3066	{
3067	cbRemaining -= (cbPhysPage - offIova);
3068	uBaseIova += cbPhysPage; /** @todo r=ramshankar: Should we mask the offset based on page size here? */
3069	offIova = 0;
3070	}
3071	else
3072	break;
3073	}
3074	else
3075	{
3076	LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
3077	uBaseIova, fAccess, rc));
3078	*pGCPhysSpa = NIL_RTGCPHYS;
3079	return rc;
3080	}
3081	}
3082
3083	return rc;
3084	}
3085
3086	LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3087	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3088	}
3089
3090
3091	/**
3092	* Memory access transaction from a device.
3093	*
3094	* @returns VBox status code.
3095	* @param pDevIns The IOMMU device instance.
3096	* @param uDevId The device ID (bus, device, function).
3097	* @param uIova The I/O virtual address being accessed.
3098	* @param cbAccess The number of bytes being accessed.
3099	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3100	* @param pGCPhysSpa Where to store the translated system physical address.
3101	*
3102	* @thread Any.
3103	*/
3104	static DECLCALLBACK(int) iommuAmdDeviceMemAccess(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
3105	uint32_t fFlags, PRTGCPHYS pGCPhysSpa)
3106	{
3107	/* Validate. */
3108	AssertPtr(pDevIns);
3109	AssertPtr(pGCPhysSpa);
3110	Assert(cbAccess > 0);
3111	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3112
3113	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3114	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3115	if (Ctrl.n.u1IommuEn)
3116	{
3117	IOMMUOP enmOp;
3118	uint8_t fAccess;
3119	if (fFlags & PDMIOMMU_MEM_F_READ)
3120	{
3121	enmOp = IOMMUOP_MEM_READ;
3122	fAccess = IOMMU_IO_PERM_READ;
3123	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
3124	}
3125	else
3126	{
3127	Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
3128	enmOp = IOMMUOP_MEM_WRITE;
3129	fAccess = IOMMU_IO_PERM_WRITE;
3130	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
3131	}
3132
3133	#ifdef LOG_ENABLED
3134	static const char * const s_apszAccess[] = { "none", "read", "write" };
3135	Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
3136	const char *pszAccess = s_apszAccess[fAccess];
3137	LogFlowFunc(("uDevId=%#x uIova=%#RX64 szAccess=%s cbAccess=%zu\n", uDevId, uIova, pszAccess, cbAccess));
3138	#endif
3139
3140	/** @todo IOMMU: IOTLB cache lookup. */
3141
3142	/* Lookup the IOVA from the device table. */
3143	int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbAccess, fAccess, enmOp, pGCPhysSpa);
3144	if (RT_SUCCESS(rc))
3145	{ /* likely */ }
3146	else
3147	LogFunc(("DTE lookup failed! uDevId=%#x uIova=%#RX64 fAccess=%s cbAccess=%zu rc=%Rrc\n", uDevId, uIova, fAccess,
3148	cbAccess, rc));
3149	return rc;
3150	}
3151
3152	/* Addresses are forwarded without translation when the IOMMU is disabled. */
3153	*pGCPhysSpa = uIova;
3154	return VINF_SUCCESS;
3155	}
3156
3157
3158	/**
3159	* Memory access bulk (one or more 4K pages) request from a device.
3160	*
3161	* @returns VBox status code.
3162	* @param pDevIns The IOMMU device instance.
3163	* @param uDevId The device ID (bus, device, function).
3164	* @param cIovas The number of addresses being accessed.
3165	* @param pauIovas The I/O virtual addresses for each page being accessed.
3166	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3167	* @param paGCPhysSpa Where to store the translated physical addresses.
3168	*
3169	* @thread Any.
3170	*/
3171	static DECLCALLBACK(int) iommuAmdDeviceMemBulkAccess(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas,
3172	uint64_t const *pauIovas, uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
3173	{
3174	/* Validate. */
3175	AssertPtr(pDevIns);
3176	Assert(cIovas > 0);
3177	AssertPtr(pauIovas);
3178	AssertPtr(paGCPhysSpa);
3179	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3180
3181	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3182	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3183	if (Ctrl.n.u1IommuEn)
3184	{
3185	IOMMUOP enmOp;
3186	uint8_t fAccess;
3187	if (fFlags & PDMIOMMU_MEM_F_READ)
3188	{
3189	enmOp = IOMMUOP_MEM_READ;
3190	fAccess = IOMMU_IO_PERM_READ;
3191	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
3192	}
3193	else
3194	{
3195	Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
3196	enmOp = IOMMUOP_MEM_WRITE;
3197	fAccess = IOMMU_IO_PERM_WRITE;
3198	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
3199	}
3200
3201	#ifdef LOG_ENABLED
3202	static const char * const s_apszAccess[] = { "none", "read", "write" };
3203	Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
3204	const char *pszAccess = s_apszAccess[fAccess];
3205	LogFlowFunc(("uDevId=%#x cIovas=%zu szAccess=%s\n", uDevId, cIovas, pszAccess));
3206	#endif
3207
3208	/** @todo IOMMU: IOTLB cache lookup. */
3209
3210	/* Lookup each IOVA from the device table. */
3211	for (size_t i = 0; i < cIovas; i++)
3212	{
3213	int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, pauIovas[i], X86_PAGE_SIZE, fAccess, enmOp, &paGCPhysSpa[i]);
3214	if (RT_SUCCESS(rc))
3215	{ /* likely */ }
3216	else
3217	{
3218	LogFunc(("Failed! uDevId=%#x uIova=%#RX64 fAccess=%u rc=%Rrc\n", uDevId, pauIovas[i], fAccess, rc));
3219	return rc;
3220	}
3221	}
3222	}
3223	else
3224	{
3225	/* Addresses are forwarded without translation when the IOMMU is disabled. */
3226	for (size_t i = 0; i < cIovas; i++)
3227	paGCPhysSpa[i] = pauIovas[i];
3228	}
3229
3230	return VINF_SUCCESS;
3231	}
3232
3233
3234
3235	/**
3236	* Reads an interrupt remapping table entry from guest memory given its DTE.
3237	*
3238	* @returns VBox status code.
3239	* @param pDevIns The IOMMU device instance.
3240	* @param uDevId The device ID.
3241	* @param pDte The device table entry.
3242	* @param GCPhysIn The source MSI address (used for reporting errors).
3243	* @param uDataIn The source MSI data.
3244	* @param enmOp The IOMMU operation being performed.
3245	* @param pIrte Where to store the interrupt remapping table entry.
3246	*
3247	* @thread Any.
3248	*/
3249	static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
3250	IOMMUOP enmOp, PIRTE_T pIrte)
3251	{
3252	/* Ensure the IRTE length is valid. */
3253	Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
3254
3255	RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
3256	uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
3257	uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
3258	RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
3259
3260	/* Ensure the IRTE falls completely within the interrupt table. */
3261	if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
3262	{ /* likely */ }
3263	else
3264	{
3265	LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
3266	GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
3267
3268	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3269	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent /, false / fRsvdNotZero */,
3270	false /* fPermDenied */, enmOp, &EvtIoPageFault);
3271	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteAddrInvalid);
3272	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3273	}
3274
3275	/* Read the IRTE from memory. */
3276	Assert(!(GCPhysIrte & 3));
3277	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
3278	if (RT_SUCCESS(rc))
3279	return VINF_SUCCESS;
3280
3281	/** @todo The IOMMU spec. does not tell what kind of error is reported in this
3282	* situation. Is it an I/O page fault or a device table hardware error?
3283	* There's no interrupt table hardware error event, but it's unclear what
3284	* we should do here. */
3285	LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
3286	return VERR_IOMMU_IPE_4;
3287	}
3288
3289
3290	/**
3291	* Remaps the interrupt using the interrupt remapping table.
3292	*
3293	* @returns VBox status code.
3294	* @param pDevIns The IOMMU instance data.
3295	* @param uDevId The device ID.
3296	* @param pDte The device table entry.
3297	* @param enmOp The IOMMU operation being performed.
3298	* @param pMsiIn The source MSI.
3299	* @param pMsiOut Where to store the remapped MSI.
3300	*
3301	* @thread Any.
3302	*/
3303	static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
3304	PMSIMSG pMsiOut)
3305	{
3306	Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
3307
3308	IRTE_T Irte;
3309	int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
3310	if (RT_SUCCESS(rc))
3311	{
3312	if (Irte.n.u1RemapEnable)
3313	{
3314	if (!Irte.n.u1GuestMode)
3315	{
3316	if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
3317	{
3318	/* Preserve all bits from the source MSI address that don't map 1:1 from the IRTE. */
3319	pMsiOut->Addr.u64 = pMsiIn->Addr.u64;
3320	pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
3321	pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
3322
3323	/* Preserve all bits from the source MSI data that don't map 1:1 from the IRTE. */
3324	pMsiOut->Data.u32 = pMsiIn->Data.u32;
3325	pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
3326	pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
3327
3328	return VINF_SUCCESS;
3329	}
3330
3331	LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3332	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3333	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3334	true /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
3335	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
3336	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3337	}
3338
3339	LogFunc(("Guest mode not supported -> IOPF\n"));
3340	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3341	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3342	true /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
3343	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3344	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3345	}
3346
3347	LogFunc(("Remapping disabled -> IOPF\n"));
3348	EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3349	iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3350	false /* fRsvdNotZero /, false / fPermDenied */, enmOp, &EvtIoPageFault);
3351	iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3352	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3353	}
3354
3355	return rc;
3356	}
3357
3358
3359	/**
3360	* Looks up an MSI interrupt from the interrupt remapping table.
3361	*
3362	* @returns VBox status code.
3363	* @param pDevIns The IOMMU instance data.
3364	* @param uDevId The device ID.
3365	* @param enmOp The IOMMU operation being performed.
3366	* @param pMsiIn The source MSI.
3367	* @param pMsiOut Where to store the remapped MSI.
3368	*
3369	* @thread Any.
3370	*/
3371	static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3372	{
3373	/* Read the device table entry from memory. */
3374	LogFlowFunc(("uDevId=%#x (%#x:%#x:%#x) enmOp=%u\n", uDevId,
3375	((uDevId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
3376	((uDevId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (uDevId & VBOX_PCI_DEVFN_FUN_MASK), enmOp));
3377
3378	DTE_T Dte;
3379	int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3380	if (RT_SUCCESS(rc))
3381	{
3382	/* If the DTE is not valid, all interrupts are forwarded without remapping. */
3383	if (Dte.n.u1IntrMapValid)
3384	{
3385	/* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3386	uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3387	uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3388	if (RT_LIKELY( !fRsvd0
3389	&& !fRsvd1))
3390	{ /* likely */ }
3391	else
3392	{
3393	LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3394	fRsvd1));
3395	EVT_ILLEGAL_DTE_T Event;
3396	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3397	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3398	return VERR_IOMMU_INTR_REMAP_FAILED;
3399	}
3400
3401	/*
3402	* LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3403	* that's connected through HyperTransport it might be possible; but for us, it
3404	* doesn't seem we need to specially handle these pins.
3405	*/
3406
3407	/*
3408	* Validate the MSI source address.
3409	*
3410	* 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3411	* CPU is concerned, the MSI region is fixed and we must ensure no other device
3412	* claims the region as I/O space.
3413	*
3414	* See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3415	* See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3416	* See Intel spec. 10.11.1 "Message Address Register Format".
3417	*/
3418	if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3419	{
3420	/*
3421	* The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3422	* See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3423	*/
3424	uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3425	bool fPassThru = false;
3426	switch (u8DeliveryMode)
3427	{
3428	case VBOX_MSI_DELIVERY_MODE_FIXED:
3429	case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3430	{
3431	uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3432	if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3433	{
3434	/* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3435	uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3436	if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3437	{
3438	/*
3439	* We don't support guest interrupt remapping yet. When we do, we'll need to
3440	* check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3441	* in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3442	* already reads the control register, add that as a parameter when we eventually
3443	* support guest interrupt remapping. For now, just assert.
3444	*/
3445	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3446	Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3447	NOREF(pThis);
3448
3449	return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3450	}
3451
3452	LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3453	EVT_ILLEGAL_DTE_T Event;
3454	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3455	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3456	return VERR_IOMMU_INTR_REMAP_FAILED;
3457	}
3458
3459	if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3460	{
3461	fPassThru = true;
3462	break;
3463	}
3464
3465	if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3466	{
3467	LogFunc(("IntCtl=0: Remapping disallowed for fixed/arbitrated interrupt (%#x) -> Target abort\n",
3468	pMsiIn->Data.n.u8Vector));
3469	iommuAmdSetPciTargetAbort(pDevIns);
3470	return VERR_IOMMU_INTR_REMAP_DENIED;
3471	}
3472
3473	Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
3474	LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3475	EVT_ILLEGAL_DTE_T Event;
3476	iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3477	iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3478	return VERR_IOMMU_INTR_REMAP_FAILED;
3479	}
3480
3481	/* SMIs are passed through unmapped. We don't implement SMI filters. */
3482	case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3483	case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3484	case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3485	case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3486	default:
3487	{
3488	LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3489	iommuAmdSetPciTargetAbort(pDevIns);
3490	return VERR_IOMMU_INTR_REMAP_FAILED;
3491	}
3492	}
3493
3494	/*
3495	* For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
3496	* See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
3497	*/
3498	if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
3499	\|\| !pMsiIn->Addr.n.u1DestMode)
3500	{
3501	if (fPassThru)
3502	{
3503	pMsiOut = pMsiIn;
3504	return VINF_SUCCESS;
3505	}
3506	LogFunc(("Remapping/passthru disallowed for interrupt %#x -> Target abort\n", pMsiIn->Data.n.u8Vector));
3507	}
3508	else
3509	LogFunc(("Logical destination mode invalid for delivery mode %#x\n -> Target abort\n", u8DeliveryMode));
3510
3511	iommuAmdSetPciTargetAbort(pDevIns);
3512	return VERR_IOMMU_INTR_REMAP_DENIED;
3513	}
3514	else
3515	{
3516	LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3517	return VERR_IOMMU_INTR_REMAP_FAILED;
3518	}
3519	}
3520	else
3521	{
3522	/** @todo IOMMU: Add to interrupt remapping cache. */
3523	LogFlowFunc(("DTE interrupt map not valid\n"));
3524	pMsiOut = pMsiIn;
3525	return VINF_SUCCESS;
3526	}
3527	}
3528
3529	LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3530	return VERR_IOMMU_INTR_REMAP_FAILED;
3531	}
3532
3533
3534	/**
3535	* Interrupt remap request from a device.
3536	*
3537	* @returns VBox status code.
3538	* @param pDevIns The IOMMU device instance.
3539	* @param uDevId The device ID (bus, device, function).
3540	* @param pMsiIn The source MSI.
3541	* @param pMsiOut Where to store the remapped MSI.
3542	*/
3543	static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3544	{
3545	/* Validate. */
3546	Assert(pDevIns);
3547	Assert(pMsiIn);
3548	Assert(pMsiOut);
3549
3550	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3551
3552	/* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3553	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3554	if (Ctrl.n.u1IommuEn)
3555	{
3556	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3557	/** @todo Cache? */
3558
3559	return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3560	}
3561
3562	pMsiOut = pMsiIn;
3563	return VINF_SUCCESS;
3564	}
3565
3566
3567	/**
3568	* @callback_method_impl{FNIOMMMIONEWWRITE}
3569	*/
3570	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3571	{
3572	NOREF(pvUser);
3573	Assert(cb == 4 \|\| cb == 8);
3574	Assert(!(off & (cb - 1)));
3575
3576	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3577	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3578
3579	uint64_t const uValue = cb == 8 ? (uint64_t const )pv : (uint32_t const )pv;
3580	return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
3581	}
3582
3583
3584	/**
3585	* @callback_method_impl{FNIOMMMIONEWREAD}
3586	*/
3587	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3588	{
3589	NOREF(pvUser);
3590	Assert(cb == 4 \|\| cb == 8);
3591	Assert(!(off & (cb - 1)));
3592
3593	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3594	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3595
3596	uint64_t uResult;
3597	VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
3598	if (cb == 8)
3599	(uint64_t )pv = uResult;
3600	else
3601	(uint32_t )pv = (uint32_t)uResult;
3602
3603	return rcStrict;
3604	}
3605
3606	# ifdef IN_RING3
3607
3608	/**
3609	* Processes an IOMMU command.
3610	*
3611	* @returns VBox status code.
3612	* @param pDevIns The IOMMU device instance.
3613	* @param pCmd The command to process.
3614	* @param GCPhysCmd The system physical address of the command.
3615	* @param pEvtError Where to store the error event in case of failures.
3616	*
3617	* @thread Command thread.
3618	*/
3619	static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3620	{
3621	IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3622
3623	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3624	STAM_COUNTER_INC(&pThis->StatCmd);
3625
3626	uint8_t const bCmd = pCmd->n.u4Opcode;
3627	switch (bCmd)
3628	{
3629	case IOMMU_CMD_COMPLETION_WAIT:
3630	{
3631	STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3632
3633	PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3634	AssertCompile(sizeof(pCmdComWait) == sizeof(pCmd));
3635
3636	/* Validate reserved bits in the command. */
3637	if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3638	{
3639	/* If Completion Store is requested, write the StoreData to the specified address. */
3640	if (pCmdComWait->n.u1Store)
3641	{
3642	RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3643	uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3644	int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3645	if (RT_FAILURE(rc))
3646	{
3647	LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3648	GCPhysStore, rc));
3649	iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3650	return VERR_IOMMU_CMD_HW_ERROR;
3651	}
3652	}
3653
3654	/* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3655	if (pCmdComWait->n.u1Interrupt)
3656	{
3657	IOMMU_LOCK(pDevIns);
3658	ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3659	IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3660	bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3661	IOMMU_UNLOCK(pDevIns);
3662
3663	if (fRaiseInt)
3664	iommuAmdRaiseMsiInterrupt(pDevIns);
3665	}
3666	return VINF_SUCCESS;
3667	}
3668	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3669	return VERR_IOMMU_CMD_INVALID_FORMAT;
3670	}
3671
3672	case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3673	{
3674	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3675	* then. */
3676	STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3677	return VINF_SUCCESS;
3678	}
3679
3680	case IOMMU_CMD_INV_IOMMU_PAGES:
3681	{
3682	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3683	* then. */
3684	STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3685	return VINF_SUCCESS;
3686	}
3687
3688	case IOMMU_CMD_INV_IOTLB_PAGES:
3689	{
3690	STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3691
3692	uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3693	if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3694	{
3695	/** @todo IOMMU: Implement remote IOTLB invalidation. */
3696	return VERR_NOT_IMPLEMENTED;
3697	}
3698	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3699	return VERR_IOMMU_CMD_NOT_SUPPORTED;
3700	}
3701
3702	case IOMMU_CMD_INV_INTR_TABLE:
3703	{
3704	/** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3705	* then. */
3706	STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3707	return VINF_SUCCESS;
3708	}
3709
3710	case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3711	{
3712	STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3713	if (pThis->ExtFeat.n.u1PrefetchSup)
3714	{
3715	/** @todo IOMMU: Implement prefetch. Pretend success until then. */
3716	return VINF_SUCCESS;
3717	}
3718	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3719	return VERR_IOMMU_CMD_NOT_SUPPORTED;
3720	}
3721
3722	case IOMMU_CMD_COMPLETE_PPR_REQ:
3723	{
3724	STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3725
3726	/* We don't support PPR requests yet. */
3727	Assert(!pThis->ExtFeat.n.u1PprSup);
3728	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3729	return VERR_IOMMU_CMD_NOT_SUPPORTED;
3730	}
3731
3732	case IOMMU_CMD_INV_IOMMU_ALL:
3733	{
3734	STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3735
3736	if (pThis->ExtFeat.n.u1InvAllSup)
3737	{
3738	/** @todo IOMMU: Invalidate all. Pretend success until then. */
3739	return VINF_SUCCESS;
3740	}
3741	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3742	return VERR_IOMMU_CMD_NOT_SUPPORTED;
3743	}
3744	}
3745
3746	STAM_COUNTER_DEC(&pThis->StatCmd);
3747	LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3748	iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3749	return VERR_IOMMU_CMD_NOT_SUPPORTED;
3750	}
3751
3752
3753	/**
3754	* The IOMMU command thread.
3755	*
3756	* @returns VBox status code.
3757	* @param pDevIns The IOMMU device instance.
3758	* @param pThread The command thread.
3759	*/
3760	static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3761	{
3762	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3763
3764	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3765	return VINF_SUCCESS;
3766
3767	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3768	{
3769	/*
3770	* Sleep perpetually until we are woken up to process commands.
3771	*/
3772	{
3773	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3774	bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3775	if (!fSignaled)
3776	{
3777	Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3778	int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3779	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3780	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3781	break;
3782	Log5Func(("Woken up with rc=%Rrc\n", rc));
3783	ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3784	}
3785	ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3786	}
3787
3788	/*
3789	* Fetch and process IOMMU commands.
3790	*/
3791	/** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
3792	* at a time) and is expensive due to calls to PGM for fetching guest memory.
3793	* We could optimize by fetching a bunch of commands at a time reducing
3794	* number of calls to PGM. In the longer run we could lock the memory and
3795	* mappings and accessing them directly. */
3796	IOMMU_LOCK(pDevIns);
3797
3798	IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3799	if (Status.n.u1CmdBufRunning)
3800	{
3801	/* Get the offset we need to read the command from memory (circular buffer offset). */
3802	uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3803	uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3804	Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3805	Assert(offHead < cbCmdBuf);
3806	while (offHead != pThis->CmdBufTailPtr.n.off)
3807	{
3808	/* Read the command from memory. */
3809	CMD_GENERIC_T Cmd;
3810	RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3811	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3812	if (RT_SUCCESS(rc))
3813	{
3814	/* Increment the command buffer head pointer. */
3815	offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3816	pThis->CmdBufHeadPtr.n.off = offHead;
3817
3818	/* Process the fetched command. */
3819	EVT_GENERIC_T EvtError;
3820	IOMMU_UNLOCK(pDevIns);
3821	rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3822	IOMMU_LOCK(pDevIns);
3823	if (RT_FAILURE(rc))
3824	{
3825	if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3826	\|\| rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3827	{
3828	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3829	iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3830	}
3831	else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3832	{
3833	Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3834	LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", Cmd.n.u4Opcode));
3835	iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3836	}
3837	break;
3838	}
3839	}
3840	else
3841	{
3842	LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmd, rc));
3843	EVT_CMD_HW_ERR_T EvtCmdHwErr;
3844	iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3845	iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3846	break;
3847	}
3848	}
3849	}
3850
3851	IOMMU_UNLOCK(pDevIns);
3852	}
3853
3854	LogFlowFunc(("Command thread terminating\n"));
3855	return VINF_SUCCESS;
3856	}
3857
3858
3859	/**
3860	* Wakes up the command thread so it can respond to a state change.
3861	*
3862	* @returns VBox status code.
3863	* @param pDevIns The IOMMU device instance.
3864	* @param pThread The command thread.
3865	*/
3866	static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3867	{
3868	RT_NOREF(pThread);
3869	LogFlowFunc(("\n"));
3870	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3871	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3872	}
3873
3874
3875	/**
3876	* @callback_method_impl{FNPCICONFIGREAD}
3877	*/
3878	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3879	unsigned cb, uint32_t *pu32Value)
3880	{
3881	/** @todo IOMMU: PCI config read stat counter. */
3882	VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3883	Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3884	return rcStrict;
3885	}
3886
3887
3888	/**
3889	* @callback_method_impl{FNPCICONFIGWRITE}
3890	*/
3891	static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3892	unsigned cb, uint32_t u32Value)
3893	{
3894	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3895
3896	/*
3897	* Discard writes to read-only registers that are specific to the IOMMU.
3898	* Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3899	* See PCI spec. 6.1. "Configuration Space Organization".
3900	*/
3901	switch (uAddress)
3902	{
3903	case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3904	case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3905	case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3906	case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3907	{
3908	LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3909	return VINF_SUCCESS;
3910	}
3911	}
3912
3913	IOMMU_LOCK(pDevIns);
3914
3915	VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3916	switch (uAddress)
3917	{
3918	case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3919	{
3920	if (pThis->IommuBar.n.u1Enable)
3921	{
3922	rcStrict = VINF_SUCCESS;
3923	LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3924	break;
3925	}
3926
3927	pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3928	if (pThis->IommuBar.n.u1Enable)
3929	{
3930	Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3931	Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3932	RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3933	RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
3934
3935	/* If the MMIO region is already mapped at the specified address, we're done. */
3936	Assert(GCPhysMmioBase != NIL_RTGCPHYS);
3937	if (GCPhysMmioBasePrev == GCPhysMmioBase)
3938	{
3939	rcStrict = VINF_SUCCESS;
3940	break;
3941	}
3942
3943	/* Unmap the previous MMIO region (which is at a different address). */
3944	if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
3945	{
3946	LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
3947	rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3948	if (RT_FAILURE(rcStrict))
3949	{
3950	LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3951	break;
3952	}
3953	}
3954
3955	/* Map the newly specified MMIO region. */
3956	LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
3957	rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3958	if (RT_FAILURE(rcStrict))
3959	{
3960	LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3961	break;
3962	}
3963	}
3964	else
3965	rcStrict = VINF_SUCCESS;
3966	break;
3967	}
3968
3969	case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3970	{
3971	if (!pThis->IommuBar.n.u1Enable)
3972	pThis->IommuBar.au32[1] = u32Value;
3973	else
3974	{
3975	rcStrict = VINF_SUCCESS;
3976	LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3977	}
3978	break;
3979	}
3980
3981	case IOMMU_PCI_OFF_MSI_CAP_HDR:
3982	{
3983	u32Value \|= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3984	RT_FALL_THRU();
3985	}
3986	default:
3987	{
3988	rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3989	break;
3990	}
3991	}
3992
3993	IOMMU_UNLOCK(pDevIns);
3994
3995	Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
3996	return rcStrict;
3997	}
3998
3999
4000	/**
4001	* @callback_method_impl{FNDBGFHANDLERDEV}
4002	*/
4003	static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4004	{
4005	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4006	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4007	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4008
4009	bool fVerbose;
4010	if ( pszArgs
4011	&& !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
4012	fVerbose = true;
4013	else
4014	fVerbose = false;
4015
4016	pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
4017	/* Device Table Base Addresses (all segments). */
4018	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4019	{
4020	DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
4021	pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
4022	if (fVerbose)
4023	{
4024	pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
4025	IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
4026	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
4027	}
4028	}
4029	/* Command Buffer Base Address Register. */
4030	{
4031	CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
4032	uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
4033	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4034	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4035	pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
4036	if (fVerbose)
4037	{
4038	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
4039	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4040	cEntries, cbBuffer);
4041	}
4042	}
4043	/* Event Log Base Address Register. */
4044	{
4045	EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
4046	uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
4047	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4048	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4049	pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
4050	if (fVerbose)
4051	{
4052	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4053	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4054	cEntries, cbBuffer);
4055	}
4056	}
4057	/* IOMMU Control Register. */
4058	{
4059	IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
4060	pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
4061	if (fVerbose)
4062	{
4063	pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
4064	pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
4065	pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
4066	pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4067	pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4068	pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
4069	pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
4070	pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
4071	pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
4072	pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
4073	pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
4074	pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
4075	pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
4076	pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
4077	pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
4078	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
4079	pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
4080	pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
4081	pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
4082	pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
4083	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
4084	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
4085	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
4086	pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
4087	pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
4088	pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
4089	pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
4090	pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
4091	pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
4092	pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
4093	pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
4094	pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
4095	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
4096	pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
4097	pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
4098	pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
4099	pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
4100	pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
4101	}
4102	}
4103	/* Exclusion Base Address Register. */
4104	{
4105	IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
4106	pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
4107	if (fVerbose)
4108	{
4109	pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
4110	pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
4111	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
4112	ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
4113	}
4114	}
4115	/* Exclusion Range Limit Register. */
4116	{
4117	IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
4118	pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
4119	if (fVerbose)
4120	pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
4121	}
4122	/* Extended Feature Register. */
4123	{
4124	IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
4125	pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
4126	if (fVerbose)
4127	{
4128	pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
4129	pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
4130	pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
4131	pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
4132	pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
4133	pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
4134	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
4135	pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
4136	pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
4137	pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
4138	pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
4139	pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
4140	pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
4141	pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
4142	pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
4143	pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
4144	pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
4145	pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
4146	pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
4147	pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
4148	g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
4149	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
4150	pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
4151	pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
4152	pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
4153	pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
4154	pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
4155	pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
4156	pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
4157	pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
4158	pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
4159	pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
4160	pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
4161	pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
4162	pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
4163	}
4164	}
4165	/* PPR Log Base Address Register. */
4166	{
4167	PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
4168	uint8_t const uEncodedLen = PprLogBar.n.u4Len;
4169	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4170	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4171	pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
4172	if (fVerbose)
4173	{
4174	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4175	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4176	cEntries, cbBuffer);
4177	}
4178	}
4179	/* Hardware Event (Hi) Register. */
4180	{
4181	IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4182	pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4183	if (fVerbose)
4184	{
4185	pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4186	pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4187	}
4188	}
4189	/* Hardware Event (Lo) Register. */
4190	pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4191	/* Hardware Event Status. */
4192	{
4193	IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4194	pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4195	if (fVerbose)
4196	{
4197	pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4198	pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4199	}
4200	}
4201	/* Guest Virtual-APIC Log Base Address Register. */
4202	{
4203	GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4204	uint8_t const uEncodedLen = GALogBar.n.u4Len;
4205	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4206	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4207	pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4208	if (fVerbose)
4209	{
4210	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4211	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4212	cEntries, cbBuffer);
4213	}
4214	}
4215	/* Guest Virtual-APIC Log Tail Address Register. */
4216	{
4217	GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4218	pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4219	if (fVerbose)
4220	pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4221	}
4222	/* PPR Log B Base Address Register. */
4223	{
4224	PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4225	uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4226	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4227	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4228	pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4229	if (fVerbose)
4230	{
4231	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4232	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4233	cEntries, cbBuffer);
4234	}
4235	}
4236	/* Event Log B Base Address Register. */
4237	{
4238	EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4239	uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4240	uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4241	uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4242	pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4243	if (fVerbose)
4244	{
4245	pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4246	pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4247	cEntries, cbBuffer);
4248	}
4249	}
4250	/* Device-Specific Feature Extension Register. */
4251	{
4252	DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4253	pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4254	if (fVerbose)
4255	{
4256	pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4257	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4258	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4259	}
4260	}
4261	/* Device-Specific Control Extension Register. */
4262	{
4263	DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4264	pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4265	if (fVerbose)
4266	{
4267	pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4268	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4269	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4270	}
4271	}
4272	/* Device-Specific Status Extension Register. */
4273	{
4274	DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4275	pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
4276	if (fVerbose)
4277	{
4278	pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4279	pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4280	pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4281	}
4282	}
4283	/* Miscellaneous Information Register (Lo and Hi). */
4284	{
4285	MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
4286	pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
4287	if (fVerbose)
4288	{
4289	pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
4290	pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
4291	pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
4292	pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
4293	pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
4294	pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
4295	pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
4296	}
4297	}
4298	/* MSI Capability Header. */
4299	{
4300	MSI_CAP_HDR_T MsiCapHdr;
4301	MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4302	pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4303	if (fVerbose)
4304	{
4305	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4306	pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4307	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4308	pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4309	pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4310	}
4311	}
4312	/* MSI Address Register (Lo and Hi). */
4313	{
4314	uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4315	uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4316	MSIADDR MsiAddr;
4317	MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4318	pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4319	if (fVerbose)
4320	{
4321	pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
4322	pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
4323	pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
4324	pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
4325	pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
4326	}
4327	}
4328	/* MSI Data. */
4329	{
4330	MSIDATA MsiData;
4331	MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4332	pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4333	if (fVerbose)
4334	{
4335	pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
4336	MsiData.n.u8Vector);
4337	pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
4338	pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
4339	pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4340	"level" : "edge");
4341	}
4342	}
4343	/* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4344	{
4345	MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4346	MsiMapCapHdr.u32 = 0;
4347	pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4348	if (fVerbose)
4349	{
4350	pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4351	pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4352	pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4353	pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4354	}
4355	}
4356	/* Performance Optimization Control Register. */
4357	{
4358	IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4359	pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4360	if (fVerbose)
4361	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4362	}
4363	/* XT (x2APIC) General Interrupt Control Register. */
4364	{
4365	IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4366	pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4367	if (fVerbose)
4368	{
4369	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4370	!XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4371	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4372	RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4373	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4374	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4375	!XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4376	}
4377	}
4378	/* XT (x2APIC) PPR Interrupt Control Register. */
4379	{
4380	IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4381	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4382	if (fVerbose)
4383	{
4384	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4385	!XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4386	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4387	RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4388	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4389	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4390	!XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4391	}
4392	}
4393	/* XT (X2APIC) GA Log Interrupt Control Register. */
4394	{
4395	IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4396	pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4397	if (fVerbose)
4398	{
4399	pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4400	!XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4401	pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4402	RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4403	pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4404	pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4405	!XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4406	}
4407	}
4408	/* MARC Registers. */
4409	{
4410	for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4411	{
4412	pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4413	MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4414	pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4415
4416	MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4417	pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4418	MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4419	MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4420
4421	MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4422	pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4423	}
4424	}
4425	/* Reserved Register. */
4426	pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4427	/* Command Buffer Head Pointer Register. */
4428	{
4429	CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4430	pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4431	CmdBufHeadPtr.n.off);
4432	}
4433	/* Command Buffer Tail Pointer Register. */
4434	{
4435	CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4436	pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4437	CmdBufTailPtr.n.off);
4438	}
4439	/* Event Log Head Pointer Register. */
4440	{
4441	EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4442	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4443	EvtLogHeadPtr.n.off);
4444	}
4445	/* Event Log Tail Pointer Register. */
4446	{
4447	EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4448	pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4449	EvtLogTailPtr.n.off);
4450	}
4451	/* Status Register. */
4452	{
4453	IOMMU_STATUS_T const Status = pThis->Status;
4454	pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4455	if (fVerbose)
4456	{
4457	pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4458	pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4459	pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4460	pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4461	pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4462	pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4463	pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4464	pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4465	pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4466	pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4467	pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4468	pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4469	pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4470	pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4471	pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4472	pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4473	}
4474	}
4475	/* PPR Log Head Pointer. */
4476	{
4477	PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4478	pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4479	PprLogHeadPtr.n.off);
4480	}
4481	/* PPR Log Tail Pointer. */
4482	{
4483	PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4484	pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4485	PprLogTailPtr.n.off);
4486	}
4487	/* Guest Virtual-APIC Log Head Pointer. */
4488	{
4489	GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4490	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4491	GALogHeadPtr.n.u12GALogPtr);
4492	}
4493	/* Guest Virtual-APIC Log Tail Pointer. */
4494	{
4495	GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4496	pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4497	GALogTailPtr.n.u12GALogPtr);
4498	}
4499	/* PPR Log B Head Pointer. */
4500	{
4501	PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4502	pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4503	PprLogBHeadPtr.n.off);
4504	}
4505	/* PPR Log B Tail Pointer. */
4506	{
4507	PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4508	pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4509	PprLogBTailPtr.n.off);
4510	}
4511	/* Event Log B Head Pointer. */
4512	{
4513	EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4514	pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4515	EvtLogBHeadPtr.n.off);
4516	}
4517	/* Event Log B Tail Pointer. */
4518	{
4519	EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4520	pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4521	EvtLogBTailPtr.n.off);
4522	}
4523	/* PPR Log Auto Response Register. */
4524	{
4525	PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4526	pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4527	if (fVerbose)
4528	{
4529	pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4530	pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4531	}
4532	}
4533	/* PPR Log Overflow Early Warning Indicator Register. */
4534	{
4535	PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4536	pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4537	if (fVerbose)
4538	{
4539	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4540	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4541	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4542	}
4543	}
4544	/* PPR Log Overflow Early Warning Indicator Register. */
4545	{
4546	PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4547	pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4548	if (fVerbose)
4549	{
4550	pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4551	pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4552	pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4553	}
4554	}
4555	}
4556
4557
4558	/**
4559	* Dumps the DTE via the info callback helper.
4560	*
4561	* @param pHlp The info helper.
4562	* @param pDte The device table entry.
4563	* @param pszPrefix The string prefix.
4564	*/
4565	static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4566	{
4567	AssertReturnVoid(pHlp);
4568	AssertReturnVoid(pDte);
4569	AssertReturnVoid(pszPrefix);
4570
4571	pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4572	pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4573	pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4574	pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4575	pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4576	pDte->n.u40PageTableRootPtrLo << 12);
4577	pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4578	pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4579	pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4580	pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4581	pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4582	pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4583	pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4584	(pDte->n.u21GstCr3TableRootPtrHi << 31)
4585	\| (pDte->n.u16GstCr3TableRootPtrMid << 15)
4586	\| (pDte->n.u3GstCr3TableRootPtrLo << 12));
4587	pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4588	pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4589	pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4590	pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4591	pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4592	pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4593	pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4594	pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4595	pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4596	pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4597	pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4598	pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4599	pHlp->pfnPrintf(pHlp, "\n");
4600
4601	pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4602	uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4603	if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4604	{
4605	uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4606	uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4607	pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4608	cbIntrTable);
4609	}
4610	else
4611	pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4612	pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4613	pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4614	pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4615	pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4616	pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4617	pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4618	pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4619	pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4620	pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4621	pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4622	pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4623	pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4624	pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4625	pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4626	pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4627	pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4628	}
4629
4630
4631	/**
4632	* @callback_method_impl{FNDBGFHANDLERDEV}
4633	*/
4634	static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4635	{
4636	if (pszArgs)
4637	{
4638	uint16_t uDevId = 0;
4639	int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4640	if (RT_SUCCESS(rc))
4641	{
4642	DTE_T Dte;
4643	rc = iommuAmdReadDte(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4644	if (RT_SUCCESS(rc))
4645	{
4646	pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", uDevId);
4647	iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4648	return;
4649	}
4650
4651	pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4652	}
4653	else
4654	pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4655	}
4656	else
4657	pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4658	}
4659
4660
4661	#if 0
4662	/**
4663	* @callback_method_impl{FNDBGFHANDLERDEV}
4664	*/
4665	static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4666	{
4667	RT_NOREF(pszArgs);
4668
4669	PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4670	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4671	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4672
4673	uint8_t cTables = 0;
4674	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4675	{
4676	DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4677	RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4678	if (GCPhysDevTab)
4679	++cTables;
4680	}
4681
4682	pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4683	pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4684	if (!cTables)
4685	return;
4686
4687	for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4688	{
4689	DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4690	RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4691	if (GCPhysDevTab)
4692	{
4693	uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4694	uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4695	pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4696
4697	void *pvDevTab = RTMemAllocZ(cbDevTab);
4698	if (RT_LIKELY(pvDevTab))
4699	{
4700	int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4701	if (RT_SUCCESS(rc))
4702	{
4703	for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4704	{
4705	PCDTE_T pDte = (PCDTE_T)((char )pvDevTab + idxDte sizeof(DTE_T));
4706	if ( pDte->n.u1Valid
4707	\|\| pDte->n.u1IntrMapValid)
4708	{
4709	pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4710	iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4711	}
4712	}
4713	pHlp->pfnPrintf(pHlp, "\n");
4714	}
4715	else
4716	{
4717	pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4718	cbDevTab, rc);
4719	}
4720
4721	RTMemFree(pvDevTab);
4722	}
4723	else
4724	{
4725	pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4726	return;
4727	}
4728	}
4729	}
4730	}
4731	#endif
4732
4733	/**
4734	* @callback_method_impl{FNSSMDEVSAVEEXEC}
4735	*/
4736	static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4737	{
4738	/** @todo IOMMU: Save state. */
4739	RT_NOREF2(pDevIns, pSSM);
4740	LogFlowFunc(("\n"));
4741	return VERR_NOT_IMPLEMENTED;
4742	}
4743
4744
4745	/**
4746	* @callback_method_impl{FNSSMDEVLOADEXEC}
4747	*/
4748	static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4749	{
4750	/** @todo IOMMU: Load state. */
4751	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4752	LogFlowFunc(("\n"));
4753	return VERR_NOT_IMPLEMENTED;
4754	}
4755
4756
4757	/**
4758	* @interface_method_impl{PDMDEVREG,pfnReset}
4759	*/
4760	static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4761	{
4762	/*
4763	* Resets read-write portion of the IOMMU state.
4764	*
4765	* NOTE! State not initialized here is expected to be initialized during
4766	* device construction and remain read-only through the lifetime of the VM.
4767	*/
4768	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4769	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4770	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4771
4772	IOMMU_LOCK_NORET(pDevIns);
4773
4774	LogFlowFunc(("\n"));
4775
4776	memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4777
4778	pThis->CmdBufBaseAddr.u64 = 0;
4779	pThis->CmdBufBaseAddr.n.u4Len = 8;
4780
4781	pThis->EvtLogBaseAddr.u64 = 0;
4782	pThis->EvtLogBaseAddr.n.u4Len = 8;
4783
4784	pThis->Ctrl.u64 = 0;
4785	pThis->Ctrl.n.u1Coherent = 1;
4786	Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4787
4788	pThis->ExclRangeBaseAddr.u64 = 0;
4789	pThis->ExclRangeLimit.u64 = 0;
4790
4791	pThis->PprLogBaseAddr.u64 = 0;
4792	pThis->PprLogBaseAddr.n.u4Len = 8;
4793
4794	pThis->HwEvtHi.u64 = 0;
4795	pThis->HwEvtLo = 0;
4796	pThis->HwEvtStatus.u64 = 0;
4797
4798	pThis->GALogBaseAddr.u64 = 0;
4799	pThis->GALogBaseAddr.n.u4Len = 8;
4800	pThis->GALogTailAddr.u64 = 0;
4801
4802	pThis->PprLogBBaseAddr.u64 = 0;
4803	pThis->PprLogBBaseAddr.n.u4Len = 8;
4804
4805	pThis->EvtLogBBaseAddr.u64 = 0;
4806	pThis->EvtLogBBaseAddr.n.u4Len = 8;
4807
4808	pThis->PerfOptCtrl.u32 = 0;
4809
4810	pThis->XtGenIntrCtrl.u64 = 0;
4811	pThis->XtPprIntrCtrl.u64 = 0;
4812	pThis->XtGALogIntrCtrl.u64 = 0;
4813
4814	memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4815
4816	pThis->CmdBufHeadPtr.u64 = 0;
4817	pThis->CmdBufTailPtr.u64 = 0;
4818	pThis->EvtLogHeadPtr.u64 = 0;
4819	pThis->EvtLogTailPtr.u64 = 0;
4820
4821	pThis->Status.u64 = 0;
4822
4823	pThis->PprLogHeadPtr.u64 = 0;
4824	pThis->PprLogTailPtr.u64 = 0;
4825
4826	pThis->GALogHeadPtr.u64 = 0;
4827	pThis->GALogTailPtr.u64 = 0;
4828
4829	pThis->PprLogBHeadPtr.u64 = 0;
4830	pThis->PprLogBTailPtr.u64 = 0;
4831
4832	pThis->EvtLogBHeadPtr.u64 = 0;
4833	pThis->EvtLogBTailPtr.u64 = 0;
4834
4835	pThis->PprLogAutoResp.u64 = 0;
4836	pThis->PprLogOverflowEarly.u64 = 0;
4837	pThis->PprLogBOverflowEarly.u64 = 0;
4838
4839	pThis->IommuBar.u64 = 0;
4840	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4841	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4842
4843	PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4844
4845	IOMMU_UNLOCK(pDevIns);
4846	}
4847
4848
4849	/**
4850	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4851	*/
4852	static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4853	{
4854	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4855	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4856	LogFlowFunc(("\n"));
4857
4858	/* Close the command thread semaphore. */
4859	if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4860	{
4861	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4862	pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4863	}
4864	return VINF_SUCCESS;
4865	}
4866
4867
4868	/**
4869	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4870	*/
4871	static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4872	{
4873	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4874	RT_NOREF(pCfg);
4875
4876	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4877	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4878	pThisCC->pDevInsR3 = pDevIns;
4879
4880	LogFlowFunc(("iInstance=%d\n", iInstance));
4881
4882	/*
4883	* Register the IOMMU with PDM.
4884	*/
4885	PDMIOMMUREGR3 IommuReg;
4886	RT_ZERO(IommuReg);
4887	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4888	IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
4889	IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
4890	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4891	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4892	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4893	if (RT_FAILURE(rc))
4894	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4895	if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4896	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4897	N_("IOMMU helper version mismatch; got %#x expected %#x"),
4898	pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4899	if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4900	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4901	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4902	pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4903
4904	/*
4905	* Initialize read-only PCI configuration space.
4906	*/
4907	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4908	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4909
4910	/* Header. */
4911	PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4912	PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4913	PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
4914	PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4915	PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4916	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4917	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4918	PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4919	PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4920	PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4921	PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4922	PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4923	PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4924	PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4925
4926	/* Capability Header. */
4927	/* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4928	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4929	RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4930	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
4931	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4932	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4933	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4934	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4935	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4936	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4937	\| RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4938
4939	/* Base Address Register. */
4940	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4941	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4942
4943	/* IOMMU Range Register. */
4944	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4945
4946	/* Misc. Information Register. */
4947	/* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4948	uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4949	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4950	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4951	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4952	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4953	\| RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4954	uint32_t const uMiscInfoReg1 = 0;
4955	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4956	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4957
4958	/* MSI Capability Header register. */
4959	PDMMSIREG MsiReg;
4960	RT_ZERO(MsiReg);
4961	MsiReg.cMsiVectors = 1;
4962	MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4963	MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4964	MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4965
4966	/* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4967	#if 0
4968	/* MSI Address Lo. */
4969	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4970	/* MSI Address Hi. */
4971	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4972	/* MSI Data. */
4973	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4974	#endif
4975
4976	#if 0
4977	/** @todo IOMMU: I don't know if we need to support this, enable later if
4978	* required. */
4979	/* MSI Mapping Capability Header register. */
4980	PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4981	RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4982	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4983	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4984	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4985	\| RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4986	/* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4987	#endif
4988
4989	/*
4990	* Register the PCI function with PDM.
4991	*/
4992	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4993	AssertLogRelRCReturn(rc, rc);
4994
4995	/*
4996	* Register MSI support for the PCI device.
4997	* This must be done -after- register it as a PCI device!
4998	*/
4999	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5000	AssertRCReturn(rc, rc);
5001
5002	/*
5003	* Intercept PCI config. space accesses.
5004	*/
5005	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
5006	AssertLogRelRCReturn(rc, rc);
5007
5008	/*
5009	* Create the MMIO region.
5010	* Mapping of the region is done when software configures it via PCI config space.
5011	*/
5012	rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
5013	NULL /* pvUser */,
5014	IOMMMIO_FLAGS_READ_DWORD_QWORD
5015	\| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
5016	\| IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
5017	\| IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
5018	"AMD-IOMMU", &pThis->hMmio);
5019	AssertLogRelRCReturn(rc, rc);
5020
5021	/*
5022	* Register saved state.
5023	*/
5024	rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
5025	NULL, NULL, NULL,
5026	NULL, iommuAmdR3SaveExec, NULL,
5027	NULL, iommuAmdR3LoadExec, NULL);
5028	AssertLogRelRCReturn(rc, rc);
5029
5030	/*
5031	* Register debugger info items.
5032	*/
5033	PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
5034	PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
5035	#if 0
5036	PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
5037	#endif
5038
5039	# ifdef VBOX_WITH_STATISTICS
5040	/*
5041	* Statistics.
5042	*/
5043	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
5044	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
5045
5046	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
5047	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
5048
5049	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
5050	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
5051
5052	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
5053	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
5054
5055	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
5056	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
5057
5058	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
5059	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
5060
5061	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
5062	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
5063
5064	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
5065	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
5066	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
5067	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
5068	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
5069	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
5070	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
5071	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
5072	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
5073	# endif
5074
5075	/*
5076	* Create the command thread and its event semaphore.
5077	*/
5078	char szDevIommu[64];
5079	RT_ZERO(szDevIommu);
5080	RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
5081	rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5082	0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
5083	AssertLogRelRCReturn(rc, rc);
5084
5085	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5086	AssertLogRelRCReturn(rc, rc);
5087
5088	/*
5089	* Initialize read-only registers.
5090	* NOTE! Fields here must match their corresponding field in the ACPI tables.
5091	*/
5092	/* Don't remove the commented lines below as it lets us see all features at a glance. */
5093	pThis->ExtFeat.u64 = 0;
5094	//pThis->ExtFeat.n.u1PrefetchSup = 0;
5095	//pThis->ExtFeat.n.u1PprSup = 0;
5096	//pThis->ExtFeat.n.u1X2ApicSup = 0;
5097	//pThis->ExtFeat.n.u1NoExecuteSup = 0;
5098	//pThis->ExtFeat.n.u1GstTranslateSup = 0;
5099	pThis->ExtFeat.n.u1InvAllSup = 1;
5100	//pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5101	pThis->ExtFeat.n.u1HwErrorSup = 1;
5102	//pThis->ExtFeat.n.u1PerfCounterSup = 0;
5103	AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
5104	pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
5105	//pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
5106	//pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
5107	//pThis->ExtFeat.n.u2SmiFilterSup = 0;
5108	//pThis->ExtFeat.n.u3SmiFilterCount = 0;
5109	//pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5110	//pThis->ExtFeat.n.u2DualPprLogSup = 0;
5111	//pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5112	//pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
5113	//pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5114	AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5115	pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5116	//pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5117	//pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5118	//pThis->ExtFeat.n.u2MarcSup = 0;
5119	//pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5120	//pThis->ExtFeat.n.u1PerfOptSup = 0;
5121	pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5122	//pThis->ExtFeat.n.u1GstIoSup = 0;
5123	//pThis->ExtFeat.n.u1HostAccessSup = 0;
5124	//pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5125	//pThis->ExtFeat.n.u1AttrForwardSup = 0;
5126	//pThis->ExtFeat.n.u1HostDirtySup = 0;
5127	//pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5128	//pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5129	//pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5130
5131	pThis->RsvdReg = 0;
5132
5133	pThis->DevSpecificFeat.u64 = 0;
5134	pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
5135	pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
5136
5137	pThis->DevSpecificCtrl.u64 = 0;
5138	pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
5139	pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
5140
5141	pThis->DevSpecificStatus.u64 = 0;
5142	pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
5143	pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
5144
5145	pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
5146
5147	/*
5148	* Initialize parts of the IOMMU state as it would during reset.
5149	* Must be called -after- initializing PCI config. space registers.
5150	*/
5151	iommuAmdR3Reset(pDevIns);
5152
5153	LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
5154	pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
5155	pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
5156	pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
5157	pThis->ExtFeat.u64));
5158	return VINF_SUCCESS;
5159	}
5160
5161	# else /* !IN_RING3 */
5162
5163	/**
5164	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5165	*/
5166	static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5167	{
5168	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5169	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5170	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5171
5172	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5173
5174	/* Set up the MMIO RZ handlers. */
5175	int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5176	AssertRCReturn(rc, rc);
5177
5178	/* Set up the IOMMU RZ callbacks. */
5179	PDMIOMMUREGCC IommuReg;
5180	RT_ZERO(IommuReg);
5181	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5182	IommuReg.idxIommu = pThis->idxIommu;
5183	IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
5184	IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
5185	IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5186	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5187	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5188	AssertRCReturn(rc, rc);
5189
5190	return VINF_SUCCESS;
5191	}
5192
5193	# endif /* !IN_RING3 */
5194
5195	/**
5196	* The device registration structure.
5197	*/
5198	const PDMDEVREG g_DeviceIommuAmd =
5199	{
5200	/* .u32Version = */ PDM_DEVREG_VERSION,
5201	/* .uReserved0 = */ 0,
5202	/* .szName = */ "iommu-amd",
5203	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
5204	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
5205	/* .cMaxInstances = */ ~0U,
5206	/* .uSharedVersion = */ 42,
5207	/* .cbInstanceShared = */ sizeof(IOMMU),
5208	/* .cbInstanceCC = */ sizeof(IOMMUCC),
5209	/* .cbInstanceRC = */ sizeof(IOMMURC),
5210	/* .cMaxPciDevices = */ 1,
5211	/* .cMaxMsixVectors = */ 0,
5212	/* .pszDescription = */ "IOMMU (AMD)",
5213	#if defined(IN_RING3)
5214	/* .pszRCMod = */ "VBoxDDRC.rc",
5215	/* .pszR0Mod = */ "VBoxDDR0.r0",
5216	/* .pfnConstruct = */ iommuAmdR3Construct,
5217	/* .pfnDestruct = */ iommuAmdR3Destruct,
5218	/* .pfnRelocate = */ NULL,
5219	/* .pfnMemSetup = */ NULL,
5220	/* .pfnPowerOn = */ NULL,
5221	/* .pfnReset = */ iommuAmdR3Reset,
5222	/* .pfnSuspend = */ NULL,
5223	/* .pfnResume = */ NULL,
5224	/* .pfnAttach = */ NULL,
5225	/* .pfnDetach = */ NULL,
5226	/* .pfnQueryInterface = */ NULL,
5227	/* .pfnInitComplete = */ NULL,
5228	/* .pfnPowerOff = */ NULL,
5229	/* .pfnSoftReset = */ NULL,
5230	/* .pfnReserved0 = */ NULL,
5231	/* .pfnReserved1 = */ NULL,
5232	/* .pfnReserved2 = */ NULL,
5233	/* .pfnReserved3 = */ NULL,
5234	/* .pfnReserved4 = */ NULL,
5235	/* .pfnReserved5 = */ NULL,
5236	/* .pfnReserved6 = */ NULL,
5237	/* .pfnReserved7 = */ NULL,
5238	#elif defined(IN_RING0)
5239	/* .pfnEarlyConstruct = */ NULL,
5240	/* .pfnConstruct = */ iommuAmdRZConstruct,
5241	/* .pfnDestruct = */ NULL,
5242	/* .pfnFinalDestruct = */ NULL,
5243	/* .pfnRequest = */ NULL,
5244	/* .pfnReserved0 = */ NULL,
5245	/* .pfnReserved1 = */ NULL,
5246	/* .pfnReserved2 = */ NULL,
5247	/* .pfnReserved3 = */ NULL,
5248	/* .pfnReserved4 = */ NULL,
5249	/* .pfnReserved5 = */ NULL,
5250	/* .pfnReserved6 = */ NULL,
5251	/* .pfnReserved7 = */ NULL,
5252	#elif defined(IN_RC)
5253	/* .pfnConstruct = */ iommuAmdRZConstruct,
5254	/* .pfnReserved0 = */ NULL,
5255	/* .pfnReserved1 = */ NULL,
5256	/* .pfnReserved2 = */ NULL,
5257	/* .pfnReserved3 = */ NULL,
5258	/* .pfnReserved4 = */ NULL,
5259	/* .pfnReserved5 = */ NULL,
5260	/* .pfnReserved6 = */ NULL,
5261	/* .pfnReserved7 = */ NULL,
5262	#else
5263	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5264	#endif
5265	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5266	};
5267
5268	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5269

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86920

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