VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 86982

Last change on this file since 86982 was 86982, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 A bit of cleanup.
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1/* $Id: DevIommuAmd.cpp 86982 2020-11-26 11:29:29Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/alloc.h>
30#include <iprt/string.h>
31
32#include "VBoxDD.h"
33#include "DevIommuAmd.h"
34
35
36/*********************************************************************************************************************************
37* Defined Constants And Macros *
38*********************************************************************************************************************************/
39/** Release log prefix string. */
40#define IOMMU_LOG_PFX "AMD-IOMMU"
41/** The current saved state version. */
42#define IOMMU_SAVED_STATE_VERSION 1
43/** The IOTLB entry magic. */
44#define IOMMU_IOTLBE_MAGIC 0x10acce55
45
46
47/*********************************************************************************************************************************
48* Structures and Typedefs *
49*********************************************************************************************************************************/
50/**
51 * Acquires the IOMMU PDM lock.
52 * This will make a long jump to ring-3 to acquire the lock if necessary.
53 */
54#define IOMMU_LOCK(a_pDevIns) \
55 do { \
56 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
57 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
58 { /* likely */ } \
59 else \
60 return rcLock; \
61 } while (0)
62
63/**
64 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
65 * This will make a long jump to ring-3 to acquire the lock if necessary.
66 */
67#define IOMMU_LOCK_NORET(a_pDevIns) \
68 do { \
69 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
70 AssertRC(rcLock); \
71 } while (0)
72
73/**
74 * Releases the IOMMU PDM lock.
75 */
76#define IOMMU_UNLOCK(a_pDevIns) \
77 do { \
78 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
79 } while (0)
80
81/**
82 * Asserts that the critsect is owned by this thread.
83 */
84#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
85 do { \
86 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
87 } while (0)
88
89/**
90 * Asserts that the critsect is not owned by this thread.
91 */
92#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
93 do { \
94 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
95 } while (0)
96
97/**
98 * IOMMU operations (transaction) types.
99 */
100typedef enum IOMMUOP
101{
102 /** Address translation request. */
103 IOMMUOP_TRANSLATE_REQ = 0,
104 /** Memory read request. */
105 IOMMUOP_MEM_READ,
106 /** Memory write request. */
107 IOMMUOP_MEM_WRITE,
108 /** Interrupt request. */
109 IOMMUOP_INTR_REQ,
110 /** Command. */
111 IOMMUOP_CMD
112} IOMMUOP;
113AssertCompileSize(IOMMUOP, 4);
114
115/**
116 * I/O page walk result.
117 */
118typedef struct
119{
120 /** The translated system physical address. */
121 RTGCPHYS GCPhysSpa;
122 /** The number of offset bits in the system physical address. */
123 uint8_t cShift;
124 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
125 uint8_t fIoPerm;
126 /** Padding. */
127 uint8_t abPadding[2];
128} IOWALKRESULT;
129/** Pointer to an I/O walk result struct. */
130typedef IOWALKRESULT *PIOWALKRESULT;
131/** Pointer to a const I/O walk result struct. */
132typedef IOWALKRESULT *PCIOWALKRESULT;
133
134/**
135 * IOMMU I/O TLB Entry.
136 * Keep this as small and aligned as possible.
137 */
138typedef struct
139{
140 /** The translated system physical address (SPA) of the page. */
141 RTGCPHYS GCPhysSpa;
142 /** The index of the 4K page within a large page. */
143 uint32_t idxSubPage;
144 /** The I/O access permissions (IOMMU_IO_PERM_XXX). */
145 uint8_t fIoPerm;
146 /** The number of offset bits in the translation indicating page size. */
147 uint8_t cShift;
148 /** Alignment padding. */
149 uint8_t afPadding[2];
150} IOTLBE_T;
151AssertCompileSize(IOTLBE_T, 16);
152/** Pointer to an IOMMU I/O TLB entry struct. */
153typedef IOTLBE_T *PIOTLBE_T;
154/** Pointer to a const IOMMU I/O TLB entry struct. */
155typedef IOTLBE_T const *PCIOTLBE_T;
156
157/**
158 * The shared IOMMU device state.
159 */
160typedef struct IOMMU
161{
162 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
163 uint32_t idxIommu;
164 /** Alignment padding. */
165 uint32_t uPadding0;
166
167 /** Whether the command thread is sleeping. */
168 bool volatile fCmdThreadSleeping;
169 /** Alignment padding. */
170 uint8_t afPadding0[3];
171 /** Whether the command thread has been signaled for wake up. */
172 bool volatile fCmdThreadSignaled;
173 /** Alignment padding. */
174 uint8_t afPadding1[3];
175
176 /** The event semaphore the command thread waits on. */
177 SUPSEMEVENT hEvtCmdThread;
178 /** The MMIO handle. */
179 IOMMMIOHANDLE hMmio;
180
181 /** @name PCI: Base capability block registers.
182 * @{ */
183 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
184 /** @} */
185
186 /** @name MMIO: Control and status registers.
187 * @{ */
188 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
189 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
190 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
191 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
192 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
193 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
194 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
195 /** @} */
196
197 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
198 * @{ */
199 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
200 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
201 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
202 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
203 /** @} */
204
205 /** @todo IOMMU: SMI filter. */
206
207 /** @name MMIO: Guest Virtual-APIC Log registers.
208 * @{ */
209 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
210 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
211 /** @} */
212
213 /** @name MMIO: Alternate PPR and Event Log registers.
214 * @{ */
215 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
216 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
217 /** @} */
218
219 /** @name MMIO: Device-specific feature registers.
220 * @{ */
221 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
222 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
223 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
224 /** @} */
225
226 /** @name MMIO: MSI Capability Block registers.
227 * @{ */
228 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
229 /** @} */
230
231 /** @name MMIO: Performance Optimization Control registers.
232 * @{ */
233 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
234 /** @} */
235
236 /** @name MMIO: x2APIC Control registers.
237 * @{ */
238 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
239 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
240 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
241 /** @} */
242
243 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
244 * @{ */
245 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
246 /** @} */
247
248 /** @name MMIO: Reserved register.
249 * @{ */
250 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
251 /** @} */
252
253 /** @name MMIO: Command and Event Log pointer registers.
254 * @{ */
255 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
256 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
257 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
258 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
259 /** @} */
260
261 /** @name MMIO: Command and Event Status register.
262 * @{ */
263 IOMMU_STATUS_T Status; /**< IOMMU status register. */
264 /** @} */
265
266 /** @name MMIO: PPR Log Head and Tail pointer registers.
267 * @{ */
268 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
269 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
270 /** @} */
271
272 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
273 * @{ */
274 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
275 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
276 /** @} */
277
278 /** @name MMIO: PPR Log B Head and Tail pointer registers.
279 * @{ */
280 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
281 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
282 /** @} */
283
284 /** @name MMIO: Event Log B Head and Tail pointer registers.
285 * @{ */
286 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
287 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
288 /** @} */
289
290 /** @name MMIO: PPR Log Overflow protection registers.
291 * @{ */
292 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
293 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
294 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
295 /** @} */
296
297 /** @todo IOMMU: IOMMU Event counter registers. */
298
299#ifdef VBOX_WITH_STATISTICS
300 /** @name IOMMU: Stat counters.
301 * @{ */
302 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
303 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
304 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
305 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
306
307 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
308 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
309
310 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
311 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
312 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
313 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
314
315 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
316 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
317 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
318 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
319
320 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
321 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
322 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
323 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
324 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
325 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
326 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
327 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
328 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
329 /** @} */
330#endif
331} IOMMU;
332/** Pointer to the IOMMU device state. */
333typedef struct IOMMU *PIOMMU;
334/** Pointer to the const IOMMU device state. */
335typedef const struct IOMMU *PCIOMMU;
336AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
337AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
338AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
339AssertCompileMemberAlignment(IOMMU, hMmio, 8);
340AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
341AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
342AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
343AssertCompileMemberAlignment(IOMMU, Status, 8);
344
345/**
346 * The ring-3 IOMMU device state.
347 */
348typedef struct IOMMUR3
349{
350 /** Device instance. */
351 PPDMDEVINSR3 pDevInsR3;
352 /** The IOMMU helpers. */
353 PCPDMIOMMUHLPR3 pIommuHlpR3;
354 /** The command thread handle. */
355 R3PTRTYPE(PPDMTHREAD) pCmdThread;
356} IOMMUR3;
357/** Pointer to the ring-3 IOMMU device state. */
358typedef IOMMUR3 *PIOMMUR3;
359
360/**
361 * The ring-0 IOMMU device state.
362 */
363typedef struct IOMMUR0
364{
365 /** Device instance. */
366 PPDMDEVINSR0 pDevInsR0;
367 /** The IOMMU helpers. */
368 PCPDMIOMMUHLPR0 pIommuHlpR0;
369} IOMMUR0;
370/** Pointer to the ring-0 IOMMU device state. */
371typedef IOMMUR0 *PIOMMUR0;
372
373/**
374 * The raw-mode IOMMU device state.
375 */
376typedef struct IOMMURC
377{
378 /** Device instance. */
379 PPDMDEVINSR0 pDevInsRC;
380 /** The IOMMU helpers. */
381 PCPDMIOMMUHLPRC pIommuHlpRC;
382} IOMMURC;
383/** Pointer to the raw-mode IOMMU device state. */
384typedef IOMMURC *PIOMMURC;
385
386/** The IOMMU device state for the current context. */
387typedef CTX_SUFF(IOMMU) IOMMUCC;
388/** Pointer to the IOMMU device state for the current context. */
389typedef CTX_SUFF(PIOMMU) PIOMMUCC;
390
391/**
392 * IOMMU register access.
393 */
394typedef struct IOMMUREGACC
395{
396 const char *pszName;
397 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
398 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
399} IOMMUREGACC;
400/** Pointer to an IOMMU register access. */
401typedef IOMMUREGACC *PIOMMUREGACC;
402/** Pointer to a const IOMMU register access. */
403typedef IOMMUREGACC const *PCIOMMUREGACC;
404
405
406/*********************************************************************************************************************************
407* Global Variables *
408*********************************************************************************************************************************/
409/**
410 * An array of the number of device table segments supported.
411 * Indexed by u2DevTabSegSup.
412 */
413static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
414
415/**
416 * An array of the masks to select the device table segment index from a device ID.
417 */
418static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
419
420/**
421 * An array of the shift values to select the device table segment index from a
422 * device ID.
423 */
424static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
425
426/**
427 * The maximum size (inclusive) of each device table segment (0 to 7).
428 * Indexed by the device table segment index.
429 */
430static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
431
432
433#ifndef VBOX_DEVICE_STRUCT_TESTCASE
434/**
435 * Gets the maximum number of buffer entries for the given buffer length.
436 *
437 * @returns Number of buffer entries.
438 * @param uEncodedLen The length (power-of-2 encoded).
439 */
440DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
441{
442 Assert(uEncodedLen > 7);
443 return 2 << (uEncodedLen - 1);
444}
445
446
447/**
448 * Gets the total length of the buffer given a base register's encoded length.
449 *
450 * @returns The length of the buffer in bytes.
451 * @param uEncodedLen The length (power-of-2 encoded).
452 */
453DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
454{
455 Assert(uEncodedLen > 7);
456 return (2 << (uEncodedLen - 1)) << 4;
457}
458
459
460/**
461 * Gets the number of (unconsumed) entries in the event log.
462 *
463 * @returns The number of entries in the event log.
464 * @param pThis The IOMMU device state.
465 */
466static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
467{
468 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
469 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
470 if (idxTail >= idxHead)
471 return idxTail - idxHead;
472
473 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
474 return cMaxEvts - idxHead + idxTail;
475}
476
477
478#if 0
479/**
480 * Gets the number of (unconsumed) commands in the command buffer.
481 *
482 * @returns The number of commands in the command buffer.
483 * @param pThis The IOMMU device state.
484 */
485static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
486{
487 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
488 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
489 if (idxTail >= idxHead)
490 return idxTail - idxHead;
491
492 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
493 return cMaxCmds - idxHead + idxTail;
494}
495#endif
496
497
498DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
499{
500 IOMMU_STATUS_T Status;
501 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
502 return Status;
503}
504
505
506DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
507{
508 IOMMU_CTRL_T Ctrl;
509 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
510 return Ctrl;
511}
512
513
514/**
515 * Returns whether MSI is enabled for the IOMMU.
516 *
517 * @returns Whether MSI is enabled.
518 * @param pDevIns The IOMMU device instance.
519 *
520 * @note There should be a PCIDevXxx function for this.
521 */
522static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
523{
524 MSI_CAP_HDR_T MsiCapHdr;
525 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
526 return MsiCapHdr.n.u1MsiEnable;
527}
528
529
530/**
531 * Signals a PCI target abort.
532 *
533 * @param pDevIns The IOMMU device instance.
534 */
535static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
536{
537 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
538 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
539 PDMPciDevSetStatus(pPciDev, u16Status);
540}
541
542
543/**
544 * Wakes up the command thread if there are commands to be processed or if
545 * processing is requested to be stopped by software.
546 *
547 * @param pDevIns The IOMMU device instance.
548 */
549static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
550{
551 IOMMU_ASSERT_LOCKED(pDevIns);
552 Log4Func(("\n"));
553
554 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
555 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
556 if (Status.n.u1CmdBufRunning)
557 {
558 Log4Func(("Signaling command thread\n"));
559 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
560 }
561}
562
563
564/**
565 * Reads the Device Table Base Address Register.
566 */
567static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
568{
569 RT_NOREF(pDevIns, offReg);
570 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
571 return VINF_SUCCESS;
572}
573
574
575/**
576 * Reads the Command Buffer Base Address Register.
577 */
578static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
579{
580 RT_NOREF(pDevIns, offReg);
581 *pu64Value = pThis->CmdBufBaseAddr.u64;
582 return VINF_SUCCESS;
583}
584
585
586/**
587 * Reads the Event Log Base Address Register.
588 */
589static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
590{
591 RT_NOREF(pDevIns, offReg);
592 *pu64Value = pThis->EvtLogBaseAddr.u64;
593 return VINF_SUCCESS;
594}
595
596
597/**
598 * Reads the Control Register.
599 */
600static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
601{
602 RT_NOREF(pDevIns, offReg);
603 *pu64Value = pThis->Ctrl.u64;
604 return VINF_SUCCESS;
605}
606
607
608/**
609 * Reads the Exclusion Range Base Address Register.
610 */
611static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
612{
613 RT_NOREF(pDevIns, offReg);
614 *pu64Value = pThis->ExclRangeBaseAddr.u64;
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Reads to the Exclusion Range Limit Register.
621 */
622static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
623{
624 RT_NOREF(pDevIns, offReg);
625 *pu64Value = pThis->ExclRangeLimit.u64;
626 return VINF_SUCCESS;
627}
628
629
630/**
631 * Reads to the Extended Feature Register.
632 */
633static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
634{
635 RT_NOREF(pDevIns, offReg);
636 *pu64Value = pThis->ExtFeat.u64;
637 return VINF_SUCCESS;
638}
639
640
641/**
642 * Reads to the PPR Log Base Address Register.
643 */
644static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
645{
646 RT_NOREF(pDevIns, offReg);
647 *pu64Value = pThis->PprLogBaseAddr.u64;
648 return VINF_SUCCESS;
649}
650
651
652/**
653 * Writes the Hardware Event Register (Hi).
654 */
655static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
656{
657 RT_NOREF(pDevIns, offReg);
658 *pu64Value = pThis->HwEvtHi.u64;
659 return VINF_SUCCESS;
660}
661
662
663/**
664 * Reads the Hardware Event Register (Lo).
665 */
666static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
667{
668 RT_NOREF(pDevIns, offReg);
669 *pu64Value = pThis->HwEvtLo;
670 return VINF_SUCCESS;
671}
672
673
674/**
675 * Reads the Hardware Event Status Register.
676 */
677static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
678{
679 RT_NOREF(pDevIns, offReg);
680 *pu64Value = pThis->HwEvtStatus.u64;
681 return VINF_SUCCESS;
682}
683
684
685/**
686 * Reads to the GA Log Base Address Register.
687 */
688static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
689{
690 RT_NOREF(pDevIns, offReg);
691 *pu64Value = pThis->GALogBaseAddr.u64;
692 return VINF_SUCCESS;
693}
694
695
696/**
697 * Reads to the PPR Log B Base Address Register.
698 */
699static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
700{
701 RT_NOREF(pDevIns, offReg);
702 *pu64Value = pThis->PprLogBBaseAddr.u64;
703 return VINF_SUCCESS;
704}
705
706
707/**
708 * Reads to the Event Log B Base Address Register.
709 */
710static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
711{
712 RT_NOREF(pDevIns, offReg);
713 *pu64Value = pThis->EvtLogBBaseAddr.u64;
714 return VINF_SUCCESS;
715}
716
717
718/**
719 * Reads the Device Table Segment Base Address Register.
720 */
721static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
722{
723 RT_NOREF(pDevIns);
724
725 /* Figure out which segment is being written. */
726 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
727 uint8_t const idxSegment = offSegment + 1;
728 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
729
730 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
731 return VINF_SUCCESS;
732}
733
734
735/**
736 * Reads the Device Specific Feature Extension (DSFX) Register.
737 */
738static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
739{
740 RT_NOREF(pDevIns, offReg);
741 *pu64Value = pThis->DevSpecificFeat.u64;
742 return VINF_SUCCESS;
743}
744
745/**
746 * Reads the Device Specific Control Extension (DSCX) Register.
747 */
748static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
749{
750 RT_NOREF(pDevIns, offReg);
751 *pu64Value = pThis->DevSpecificCtrl.u64;
752 return VINF_SUCCESS;
753}
754
755
756/**
757 * Reads the Device Specific Status Extension (DSSX) Register.
758 */
759static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
760{
761 RT_NOREF(pDevIns, offReg);
762 *pu64Value = pThis->DevSpecificStatus.u64;
763 return VINF_SUCCESS;
764}
765
766
767/**
768 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
769 */
770static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
771{
772 RT_NOREF(pDevIns, offReg);
773 uint32_t const uLo = pThis->MiscInfo.au32[0];
774 uint32_t const uHi = pThis->MiscInfo.au32[1];
775 *pu64Value = RT_MAKE_U64(uLo, uHi);
776 return VINF_SUCCESS;
777}
778
779
780/**
781 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
782 * Register (32-bit).
783 */
784static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
785{
786 RT_NOREF(pThis, offReg);
787 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
788 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
789 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
790 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
791 *pu64Value = RT_MAKE_U64(uLo, uHi);
792 return VINF_SUCCESS;
793}
794
795
796/**
797 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
798 */
799static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
800{
801 RT_NOREF(pThis, offReg);
802 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
803 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
804 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
805 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
806 *pu64Value = RT_MAKE_U64(uLo, uHi);
807 return VINF_SUCCESS;
808}
809
810
811/**
812 * Reads the Command Buffer Head Pointer Register.
813 */
814static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
815{
816 RT_NOREF(pDevIns, offReg);
817 *pu64Value = pThis->CmdBufHeadPtr.u64;
818 return VINF_SUCCESS;
819}
820
821
822/**
823 * Reads the Command Buffer Tail Pointer Register.
824 */
825static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
826{
827 RT_NOREF(pDevIns, offReg);
828 *pu64Value = pThis->CmdBufTailPtr.u64;
829 return VINF_SUCCESS;
830}
831
832
833/**
834 * Reads the Event Log Head Pointer Register.
835 */
836static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
837{
838 RT_NOREF(pDevIns, offReg);
839 *pu64Value = pThis->EvtLogHeadPtr.u64;
840 return VINF_SUCCESS;
841}
842
843
844/**
845 * Reads the Event Log Tail Pointer Register.
846 */
847static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
848{
849 RT_NOREF(pDevIns, offReg);
850 *pu64Value = pThis->EvtLogTailPtr.u64;
851 return VINF_SUCCESS;
852}
853
854
855/**
856 * Reads the Status Register.
857 */
858static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
859{
860 RT_NOREF(pDevIns, offReg);
861 *pu64Value = pThis->Status.u64;
862 return VINF_SUCCESS;
863}
864
865
866/**
867 * Writes the Device Table Base Address Register.
868 */
869static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
870{
871 RT_NOREF(pDevIns, offReg);
872
873 /* Mask out all unrecognized bits. */
874 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
875
876 /* Update the register. */
877 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
878
879 /* Paranoia. */
880 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
881 return VINF_SUCCESS;
882}
883
884
885/**
886 * Writes the Command Buffer Base Address Register.
887 */
888static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
889{
890 RT_NOREF(pDevIns, offReg);
891
892 /*
893 * While this is not explicitly specified like the event log base address register,
894 * the AMD spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
895 * Inconsistent specs :/
896 */
897 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
898 if (Status.n.u1CmdBufRunning)
899 {
900 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
901 return VINF_SUCCESS;
902 }
903
904 /* Mask out all unrecognized bits. */
905 CMD_BUF_BAR_T CmdBufBaseAddr;
906 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
907
908 /* Validate the length. */
909 if (CmdBufBaseAddr.n.u4Len >= 8)
910 {
911 /* Update the register. */
912 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
913
914 /*
915 * Writing the command buffer base address, clears the command buffer head and tail pointers.
916 * See AMD spec. 2.4 "Commands".
917 */
918 pThis->CmdBufHeadPtr.u64 = 0;
919 pThis->CmdBufTailPtr.u64 = 0;
920 }
921 else
922 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
923
924 return VINF_SUCCESS;
925}
926
927
928/**
929 * Writes the Event Log Base Address Register.
930 */
931static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
932{
933 RT_NOREF(pDevIns, offReg);
934
935 /*
936 * IOMMU behavior is undefined when software writes this register when event logging is running.
937 * In our emulation, we ignore the write entirely.
938 * See AMD IOMMU spec. "Event Log Base Address Register".
939 */
940 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
941 if (Status.n.u1EvtLogRunning)
942 {
943 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
944 return VINF_SUCCESS;
945 }
946
947 /* Mask out all unrecognized bits. */
948 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
949 EVT_LOG_BAR_T EvtLogBaseAddr;
950 EvtLogBaseAddr.u64 = u64Value;
951
952 /* Validate the length. */
953 if (EvtLogBaseAddr.n.u4Len >= 8)
954 {
955 /* Update the register. */
956 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
957
958 /*
959 * Writing the event log base address, clears the event log head and tail pointers.
960 * See AMD spec. 2.5 "Event Logging".
961 */
962 pThis->EvtLogHeadPtr.u64 = 0;
963 pThis->EvtLogTailPtr.u64 = 0;
964 }
965 else
966 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
967
968 return VINF_SUCCESS;
969}
970
971
972/**
973 * Writes the Control Register.
974 */
975static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
976{
977 RT_NOREF(pDevIns, offReg);
978
979 /* Mask out all unrecognized bits. */
980 u64Value &= IOMMU_CTRL_VALID_MASK;
981 IOMMU_CTRL_T NewCtrl;
982 NewCtrl.u64 = u64Value;
983
984 /* Ensure the device table segments are within limits. */
985 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
986 {
987 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
988
989 /* Update the register. */
990 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
991
992 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
993 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
994
995 /* Enable or disable event logging when the bit transitions. */
996 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
997 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
998 if ( fOldEvtLogEn != fNewEvtLogEn
999 || fOldIommuEn != fNewIommuEn)
1000 {
1001 if ( fNewIommuEn
1002 && fNewEvtLogEn)
1003 {
1004 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1005 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1006 }
1007 else
1008 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1009 }
1010
1011 /* Enable or disable command buffer processing when the bit transitions. */
1012 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1013 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1014 if ( fOldCmdBufEn != fNewCmdBufEn
1015 || fOldIommuEn != fNewIommuEn)
1016 {
1017 if ( fNewCmdBufEn
1018 && fNewIommuEn)
1019 {
1020 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1021 LogFunc(("Command buffer enabled\n"));
1022
1023 /* Wake up the command thread to start processing commands. */
1024 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1025 }
1026 else
1027 {
1028 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1029 LogFunc(("Command buffer disabled\n"));
1030 }
1031 }
1032 }
1033 else
1034 {
1035 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1036 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1037 }
1038
1039 return VINF_SUCCESS;
1040}
1041
1042
1043/**
1044 * Writes to the Exclusion Range Base Address Register.
1045 */
1046static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1047{
1048 RT_NOREF(pDevIns, offReg);
1049 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1050 return VINF_SUCCESS;
1051}
1052
1053
1054/**
1055 * Writes to the Exclusion Range Limit Register.
1056 */
1057static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1058{
1059 RT_NOREF(pDevIns, offReg);
1060 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1061 u64Value |= UINT64_C(0xfff);
1062 pThis->ExclRangeLimit.u64 = u64Value;
1063 return VINF_SUCCESS;
1064}
1065
1066
1067/**
1068 * Writes the Hardware Event Register (Hi).
1069 */
1070static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1071{
1072 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1073 RT_NOREF(pDevIns, offReg);
1074 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1075 pThis->HwEvtHi.u64 = u64Value;
1076 return VINF_SUCCESS;
1077}
1078
1079
1080/**
1081 * Writes the Hardware Event Register (Lo).
1082 */
1083static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1084{
1085 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1086 RT_NOREF(pDevIns, offReg);
1087 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1088 pThis->HwEvtLo = u64Value;
1089 return VINF_SUCCESS;
1090}
1091
1092
1093/**
1094 * Writes the Hardware Event Status Register.
1095 */
1096static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1097{
1098 RT_NOREF(pDevIns, offReg);
1099
1100 /* Mask out all unrecognized bits. */
1101 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1102
1103 /*
1104 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1105 * If the current status bits or the bits being written are both 0, we've nothing to do.
1106 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1107 */
1108 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1109 if (!(HwStatus & RT_BIT(0)))
1110 return VINF_SUCCESS;
1111 if (u64Value & HwStatus & RT_BIT_64(0))
1112 HwStatus &= ~RT_BIT_64(0);
1113 if (u64Value & HwStatus & RT_BIT_64(1))
1114 HwStatus &= ~RT_BIT_64(1);
1115
1116 /* Update the register. */
1117 pThis->HwEvtStatus.u64 = HwStatus;
1118 return VINF_SUCCESS;
1119}
1120
1121
1122/**
1123 * Writes the Device Table Segment Base Address Register.
1124 */
1125static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1126{
1127 RT_NOREF(pDevIns);
1128
1129 /* Figure out which segment is being written. */
1130 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1131 uint8_t const idxSegment = offSegment + 1;
1132 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1133
1134 /* Mask out all unrecognized bits. */
1135 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1136 DEV_TAB_BAR_T DevTabSegBar;
1137 DevTabSegBar.u64 = u64Value;
1138
1139 /* Validate the size. */
1140 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1141 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1142 if (uSegSize <= uMaxSegSize)
1143 {
1144 /* Update the register. */
1145 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1146 }
1147 else
1148 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1149
1150 return VINF_SUCCESS;
1151}
1152
1153
1154/**
1155 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1156 */
1157static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1158{
1159 RT_NOREF(pDevIns, offReg);
1160
1161 /* MSI Vector Register 0 is read-only. */
1162 /* MSI Vector Register 1. */
1163 uint32_t const uReg = u64Value >> 32;
1164 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
1165 return VINF_SUCCESS;
1166}
1167
1168
1169/**
1170 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1171 * Register (32-bit).
1172 */
1173static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1174{
1175 RT_NOREF(pThis, offReg);
1176 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1177 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1178
1179 /* MSI capability header. */
1180 {
1181 uint32_t const uReg = u64Value;
1182 MSI_CAP_HDR_T MsiCapHdr;
1183 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1184 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1185 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1186 }
1187
1188 /* MSI Address Lo. */
1189 {
1190 uint32_t const uReg = u64Value >> 32;
1191 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
1192 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1193 }
1194
1195 return VINF_SUCCESS;
1196}
1197
1198
1199/**
1200 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1201 */
1202static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1203{
1204 RT_NOREF(pThis, offReg);
1205 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1206 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1207
1208 /* MSI Address Hi. */
1209 {
1210 uint32_t const uReg = u64Value;
1211 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
1212 }
1213
1214 /* MSI Data. */
1215 {
1216 uint32_t const uReg = u64Value >> 32;
1217 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
1218 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1219 }
1220
1221 return VINF_SUCCESS;
1222}
1223
1224
1225/**
1226 * Writes the Command Buffer Head Pointer Register.
1227 */
1228static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1229{
1230 RT_NOREF(pDevIns, offReg);
1231
1232 /*
1233 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1234 * In our emulation, we ignore the write entirely.
1235 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1236 */
1237 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1238 if (Status.n.u1CmdBufRunning)
1239 {
1240 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1241 return VINF_SUCCESS;
1242 }
1243
1244 /*
1245 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1246 * In our emulation, we ignore the write entirely.
1247 */
1248 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1249 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1250 Assert(cbBuf <= _512K);
1251 if (offBuf >= cbBuf)
1252 {
1253 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1254 return VINF_SUCCESS;
1255 }
1256
1257 /* Update the register. */
1258 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1259
1260 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1261
1262 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1263 return VINF_SUCCESS;
1264}
1265
1266
1267/**
1268 * Writes the Command Buffer Tail Pointer Register.
1269 */
1270static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1271{
1272 RT_NOREF(pDevIns, offReg);
1273
1274 /*
1275 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1276 * In our emulation, we ignore the write entirely.
1277 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1278 */
1279 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1280 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1281 Assert(cbBuf <= _512K);
1282 if (offBuf >= cbBuf)
1283 {
1284 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1285 return VINF_SUCCESS;
1286 }
1287
1288 /*
1289 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1290 * head pointer after adding one or more commands to the buffer.
1291 *
1292 * However, we cannot enforce this strictly because it's legal for software to shrink the
1293 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1294 * at 0). Software might even make the queue empty by making head and tail equal which is
1295 * allowed. I don't think we can or should try too hard to prevent software shooting itself
1296 * in the foot here. As long as we make sure the offset value is within the circular buffer
1297 * bounds (which we do by masking bits above) it should be sufficient.
1298 */
1299 pThis->CmdBufTailPtr.au32[0] = offBuf;
1300
1301 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1302
1303 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1304 return VINF_SUCCESS;
1305}
1306
1307
1308/**
1309 * Writes the Event Log Head Pointer Register.
1310 */
1311static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1312{
1313 RT_NOREF(pDevIns, offReg);
1314
1315 /*
1316 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1317 * In our emulation, we ignore the write entirely.
1318 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1319 */
1320 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1321 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1322 Assert(cbBuf <= _512K);
1323 if (offBuf >= cbBuf)
1324 {
1325 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1326 return VINF_SUCCESS;
1327 }
1328
1329 /* Update the register. */
1330 pThis->EvtLogHeadPtr.au32[0] = offBuf;
1331
1332 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1333 return VINF_SUCCESS;
1334}
1335
1336
1337/**
1338 * Writes the Event Log Tail Pointer Register.
1339 */
1340static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1341{
1342 RT_NOREF(pDevIns, offReg);
1343 NOREF(pThis);
1344
1345 /*
1346 * IOMMU behavior is undefined when software writes this register when the event log is running.
1347 * In our emulation, we ignore the write entirely.
1348 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1349 */
1350 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1351 if (Status.n.u1EvtLogRunning)
1352 {
1353 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1354 return VINF_SUCCESS;
1355 }
1356
1357 /*
1358 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1359 * In our emulation, we ignore the write entirely.
1360 */
1361 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1362 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1363 Assert(cbBuf <= _512K);
1364 if (offBuf >= cbBuf)
1365 {
1366 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1367 return VINF_SUCCESS;
1368 }
1369
1370 /* Update the register. */
1371 pThis->EvtLogTailPtr.au32[0] = offBuf;
1372
1373 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1374 return VINF_SUCCESS;
1375}
1376
1377
1378/**
1379 * Writes the Status Register.
1380 */
1381static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1382{
1383 RT_NOREF(pDevIns, offReg);
1384
1385 /* Mask out all unrecognized bits. */
1386 u64Value &= IOMMU_STATUS_VALID_MASK;
1387
1388 /*
1389 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1390 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1391 */
1392 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1393 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1394 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1395 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1396
1397 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1398
1399 /* Update the register. */
1400 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1401 return VINF_SUCCESS;
1402}
1403
1404
1405/**
1406 * Register access table 0.
1407 * The MMIO offset of each entry must be a multiple of 8!
1408 */
1409static const IOMMUREGACC g_aRegAccess0[] =
1410{
1411 /* MMIO off. Register name Read function Write function */
1412 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
1413 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
1414 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
1415 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
1416 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
1417 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
1418 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
1419 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
1420 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
1421 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
1422 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
1423 { /* 0x58 */ NULL, NULL, NULL },
1424
1425 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
1426 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
1427 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
1428 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
1429 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
1430 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
1431 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
1432 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
1433 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
1434 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
1435 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
1436 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
1437 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
1438 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
1439 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
1440 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
1441
1442 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
1443 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
1444 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
1445 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
1446
1447 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1448 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1449 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1450 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1451 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1452 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1453 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1454
1455 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
1456 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
1457 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
1458
1459 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
1460 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
1461 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
1462 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
1463
1464 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
1465 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
1466 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
1467};
1468AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1469
1470/**
1471 * Register access table 1.
1472 * The MMIO offset of each entry must be a multiple of 8!
1473 */
1474static const IOMMUREGACC g_aRegAccess1[] =
1475{
1476 /* MMIO offset Register name Read function Write function */
1477 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
1478 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
1479 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
1480 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
1481 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
1482 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
1483 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
1484 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
1485 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
1486 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
1487 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
1488 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
1489};
1490AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1491
1492/**
1493 * Register access table 2.
1494 * The MMIO offset of each entry must be a multiple of 8!
1495 */
1496static const IOMMUREGACC g_aRegAccess2[] =
1497{
1498 /* MMIO offset Register name Read Function Write function */
1499 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
1500
1501 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
1502 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
1503 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
1504 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
1505
1506 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
1507 { /* 0x2028 */ NULL, NULL, NULL },
1508
1509 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
1510 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
1511
1512 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
1513 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
1514
1515 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
1516 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
1517
1518 { /* 0x2060 */ NULL, NULL, NULL },
1519 { /* 0x2068 */ NULL, NULL, NULL },
1520
1521 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
1522 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
1523
1524 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
1525 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
1526 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
1527};
1528AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1529
1530
1531/**
1532 * Gets the register access structure given its MMIO offset.
1533 *
1534 * @returns The register access structure, or NULL if the offset is invalid.
1535 * @param off The MMIO offset of the register being accessed.
1536 */
1537static PCIOMMUREGACC iommuAmdGetRegAccessForOffset(uint32_t off)
1538{
1539 /* Figure out which table the register belongs to and validate its index. */
1540 PCIOMMUREGACC pReg;
1541 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1542 {
1543 uint32_t const idxReg = off >> 3;
1544 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1545 pReg = &g_aRegAccess0[idxReg];
1546 }
1547 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1548 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1549 {
1550 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1551 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1552 pReg = &g_aRegAccess1[idxReg];
1553 }
1554 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1555 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1556 {
1557 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1558 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1559 pReg = &g_aRegAccess2[idxReg];
1560 }
1561 else
1562 return NULL;
1563
1564 return pReg;
1565}
1566
1567
1568/**
1569 * Writes an IOMMU register (32-bit and 64-bit).
1570 *
1571 * @returns Strict VBox status code.
1572 * @param pDevIns The IOMMU device instance.
1573 * @param off MMIO byte offset to the register.
1574 * @param cb The size of the write access.
1575 * @param uValue The value being written.
1576 *
1577 * @thread EMT.
1578 */
1579static VBOXSTRICTRC iommuAmdWriteRegister(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1580{
1581 /*
1582 * Validate the access in case of IOM bug or incorrect assumption.
1583 */
1584 Assert(off < IOMMU_MMIO_REGION_SIZE);
1585 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1586 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1587
1588 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1589
1590 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1591 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1592 if (pReg)
1593 { /* likely */ }
1594 else
1595 {
1596 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
1597 return VINF_SUCCESS;
1598 }
1599
1600 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
1601 if (pReg->pfnWrite)
1602 { /* likely */ }
1603 else
1604 {
1605 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1606 return VINF_SUCCESS;
1607 }
1608
1609 /*
1610 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
1611 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
1612 * consecutive 32-bit registers.
1613 */
1614 if (cb == 8)
1615 {
1616 if (!(off & 7))
1617 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1618
1619 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1620 return VINF_SUCCESS;
1621 }
1622
1623 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
1624 Assert(cb == 4);
1625 if (!(off & 7))
1626 {
1627 /*
1628 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
1629 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1630 */
1631 uint64_t u64Read;
1632 if (pReg->pfnRead)
1633 {
1634 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1635 if (RT_FAILURE(rcStrict))
1636 {
1637 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1638 return rcStrict;
1639 }
1640 }
1641 else
1642 u64Read = 0;
1643
1644 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
1645 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1646 }
1647
1648 /*
1649 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
1650 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1651 */
1652 Assert(!(off & 3));
1653 Assert(off & 7);
1654 Assert(off >= 4);
1655 uint64_t u64Read;
1656 if (pReg->pfnRead)
1657 {
1658 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1659 if (RT_FAILURE(rcStrict))
1660 {
1661 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1662 return rcStrict;
1663 }
1664 }
1665 else
1666 u64Read = 0;
1667
1668 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
1669 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1670}
1671
1672
1673/**
1674 * Reads an IOMMU register (64-bit) given its MMIO offset.
1675 *
1676 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1677 * boundary include the lower half of the subsequent register.
1678 *
1679 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1680 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1681 * software will only perform 32-bit reads on those 32-bit registers that are
1682 * aligned on 8-byte boundaries.
1683 *
1684 * @returns Strict VBox status code.
1685 * @param pDevIns The IOMMU device instance.
1686 * @param off The MMIO offset of the register in bytes.
1687 * @param puResult Where to store the value being read.
1688 *
1689 * @thread EMT.
1690 */
1691static VBOXSTRICTRC iommuAmdReadRegister(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1692{
1693 Assert(off < IOMMU_MMIO_REGION_SIZE);
1694 Assert(!(off & 7) || !(off & 3));
1695
1696 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1697 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1698 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
1699
1700 Log4Func(("off=%#x\n", off));
1701
1702 PCIOMMUREGACC pReg = iommuAmdGetRegAccessForOffset(off);
1703 if (pReg)
1704 { /* likely */ }
1705 else
1706 {
1707 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
1708 return VINF_IOM_MMIO_UNUSED_FF;
1709 }
1710
1711 /* If a read handler doesn't exist, it's a reserved or unknown register. */
1712 if (pReg->pfnRead)
1713 { /* likely */ }
1714 else
1715 {
1716 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
1717 return VINF_IOM_MMIO_UNUSED_00;
1718 }
1719
1720 /*
1721 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
1722 * The caller takes care of truncating upper 32 bits for 32-bit reads.
1723 */
1724 if (!(off & 7))
1725 return pReg->pfnRead(pDevIns, pThis, off, puResult);
1726
1727 /*
1728 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
1729 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
1730 */
1731 Assert(!(off & 3));
1732 Assert(off & 7);
1733 Assert(off >= 4);
1734 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
1735 if (RT_SUCCESS(rcStrict))
1736 *puResult >>= 32;
1737 else
1738 {
1739 *puResult = 0;
1740 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1741 }
1742
1743 return rcStrict;
1744}
1745
1746
1747/**
1748 * Raises the MSI interrupt for the IOMMU device.
1749 *
1750 * @param pDevIns The IOMMU device instance.
1751 *
1752 * @thread Any.
1753 * @remarks The IOMMU lock may or may not be held.
1754 */
1755static void iommuAmdRaiseMsiInterrupt(PPDMDEVINS pDevIns)
1756{
1757 LogFlowFunc(("\n"));
1758 if (iommuAmdIsMsiEnabled(pDevIns))
1759 {
1760 LogFunc(("Raising MSI\n"));
1761 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
1762 }
1763}
1764
1765#if 0
1766/**
1767 * Clears the MSI interrupt for the IOMMU device.
1768 *
1769 * @param pDevIns The IOMMU device instance.
1770 *
1771 * @thread Any.
1772 * @remarks The IOMMU lock may or may not be held.
1773 */
1774static void iommuAmdClearMsiInterrupt(PPDMDEVINS pDevIns)
1775{
1776 if (iommuAmdIsMsiEnabled(pDevIns))
1777 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
1778}
1779#endif
1780
1781/**
1782 * Writes an entry to the event log in memory.
1783 *
1784 * @returns VBox status code.
1785 * @param pDevIns The IOMMU device instance.
1786 * @param pEvent The event to log.
1787 *
1788 * @thread Any.
1789 */
1790static int iommuAmdWriteEvtLogEntry(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1791{
1792 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1793
1794 IOMMU_ASSERT_LOCKED(pDevIns);
1795
1796 /* Check if event logging is active and the log has not overflowed. */
1797 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1798 if ( Status.n.u1EvtLogRunning
1799 && !Status.n.u1EvtOverflow)
1800 {
1801 uint32_t const cbEvt = sizeof(*pEvent);
1802
1803 /* Get the offset we need to write the event to in memory (circular buffer offset). */
1804 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
1805 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
1806
1807 /* Ensure we have space in the event log. */
1808 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
1809 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
1810 if (cEvts + 1 < cMaxEvts)
1811 {
1812 /* Write the event log entry to memory. */
1813 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
1814 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
1815 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
1816 if (RT_FAILURE(rc))
1817 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
1818
1819 /* Increment the event log tail pointer. */
1820 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1821 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
1822
1823 /* Indicate that an event log entry was written. */
1824 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
1825
1826 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
1827 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1828 if (Ctrl.n.u1EvtIntrEn)
1829 iommuAmdRaiseMsiInterrupt(pDevIns);
1830 }
1831 else
1832 {
1833 /* Indicate that the event log has overflowed. */
1834 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
1835
1836 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
1837 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
1838 if (Ctrl.n.u1EvtIntrEn)
1839 iommuAmdRaiseMsiInterrupt(pDevIns);
1840 }
1841 }
1842
1843 return VINF_SUCCESS;
1844}
1845
1846
1847/**
1848 * Sets an event in the hardware error registers.
1849 *
1850 * @param pDevIns The IOMMU device instance.
1851 * @param pEvent The event.
1852 *
1853 * @thread Any.
1854 */
1855static void iommuAmdSetHwError(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
1856{
1857 IOMMU_ASSERT_LOCKED(pDevIns);
1858
1859 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1860 if (pThis->ExtFeat.n.u1HwErrorSup)
1861 {
1862 if (pThis->HwEvtStatus.n.u1Valid)
1863 pThis->HwEvtStatus.n.u1Overflow = 1;
1864 pThis->HwEvtStatus.n.u1Valid = 1;
1865 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
1866 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
1867 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
1868 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
1869 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
1870 }
1871}
1872
1873
1874/**
1875 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
1876 *
1877 * @param uDevId The device ID.
1878 * @param uDomainId The domain ID.
1879 * @param GCPhysPtEntity The system physical address of the page table
1880 * entity.
1881 * @param enmOp The IOMMU operation being performed.
1882 * @param pEvtPageTabHwErr Where to store the initialized event.
1883 */
1884static void iommuAmdInitPageTabHwErrorEvent(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
1885 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1886{
1887 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
1888 pEvtPageTabHwErr->n.u16DevId = uDevId;
1889 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
1890 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
1891 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1892 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1893 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1894 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1895 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
1896 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
1897}
1898
1899
1900/**
1901 * Raises a PAGE_TAB_HARDWARE_ERROR event.
1902 *
1903 * @param pDevIns The IOMMU device instance.
1904 * @param enmOp The IOMMU operation being performed.
1905 * @param pEvtPageTabHwErr The page table hardware error event.
1906 *
1907 * @thread Any.
1908 */
1909static void iommuAmdRaisePageTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
1910{
1911 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
1912 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
1913
1914 IOMMU_LOCK_NORET(pDevIns);
1915
1916 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1917 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1918 if (enmOp != IOMMUOP_CMD)
1919 iommuAmdSetPciTargetAbort(pDevIns);
1920
1921 IOMMU_UNLOCK(pDevIns);
1922
1923 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
1924 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
1925 pEvtPageTabHwErr->n.u2Type));
1926}
1927
1928
1929#ifdef IN_RING3
1930/**
1931 * Initializes a COMMAND_HARDWARE_ERROR event.
1932 *
1933 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
1934 * @param pEvtCmdHwErr Where to store the initialized event.
1935 */
1936static void iommuAmdInitCmdHwErrorEvent(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1937{
1938 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
1939 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
1940 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
1941 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
1942}
1943
1944
1945/**
1946 * Raises a COMMAND_HARDWARE_ERROR event.
1947 *
1948 * @param pDevIns The IOMMU device instance.
1949 * @param pEvtCmdHwErr The command hardware error event.
1950 *
1951 * @thread Any.
1952 */
1953static void iommuAmdRaiseCmdHwErrorEvent(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
1954{
1955 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
1956 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
1957 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1958
1959 IOMMU_LOCK_NORET(pDevIns);
1960
1961 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
1962 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
1963 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1964
1965 IOMMU_UNLOCK(pDevIns);
1966
1967 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
1968}
1969#endif /* IN_RING3 */
1970
1971
1972/**
1973 * Initializes a DEV_TAB_HARDWARE_ERROR event.
1974 *
1975 * @param uDevId The device ID.
1976 * @param GCPhysDte The system physical address of the failed device table
1977 * access.
1978 * @param enmOp The IOMMU operation being performed.
1979 * @param pEvtDevTabHwErr Where to store the initialized event.
1980 */
1981static void iommuAmdInitDevTabHwErrorEvent(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
1982 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
1983{
1984 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
1985 pEvtDevTabHwErr->n.u16DevId = uDevId;
1986 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
1987 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
1988 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
1989 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
1990 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
1991 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
1992 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
1993}
1994
1995
1996/**
1997 * Raises a DEV_TAB_HARDWARE_ERROR event.
1998 *
1999 * @param pDevIns The IOMMU device instance.
2000 * @param enmOp The IOMMU operation being performed.
2001 * @param pEvtDevTabHwErr The device table hardware error event.
2002 *
2003 * @thread Any.
2004 */
2005static void iommuAmdRaiseDevTabHwErrorEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2006{
2007 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2008 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2009
2010 IOMMU_LOCK_NORET(pDevIns);
2011
2012 iommuAmdSetHwError(pDevIns, (PCEVT_GENERIC_T)pEvent);
2013 iommuAmdWriteEvtLogEntry(pDevIns, (PCEVT_GENERIC_T)pEvent);
2014 if (enmOp != IOMMUOP_CMD)
2015 iommuAmdSetPciTargetAbort(pDevIns);
2016
2017 IOMMU_UNLOCK(pDevIns);
2018
2019 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2020 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2021}
2022
2023#ifdef IN_RING3
2024/**
2025 * Initializes an ILLEGAL_COMMAND_ERROR event.
2026 *
2027 * @param GCPhysCmd The system physical address of the failed command
2028 * access.
2029 * @param pEvtIllegalCmd Where to store the initialized event.
2030 */
2031static void iommuAmdInitIllegalCmdEvent(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2032{
2033 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2034 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2035 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2036 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2037}
2038
2039
2040/**
2041 * Raises an ILLEGAL_COMMAND_ERROR event.
2042 *
2043 * @param pDevIns The IOMMU device instance.
2044 * @param pEvtIllegalCmd The illegal command error event.
2045 */
2046static void iommuAmdRaiseIllegalCmdEvent(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2047{
2048 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2049 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2050 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2051
2052 IOMMU_LOCK_NORET(pDevIns);
2053
2054 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2055 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2056
2057 IOMMU_UNLOCK(pDevIns);
2058
2059 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2060}
2061#endif /* IN_RING3 */
2062
2063
2064/**
2065 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2066 *
2067 * @param uDevId The device ID.
2068 * @param uIova The I/O virtual address.
2069 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2070 * event was caused by an invalid level encoding in the
2071 * DTE.
2072 * @param enmOp The IOMMU operation being performed.
2073 * @param pEvtIllegalDte Where to store the initialized event.
2074 */
2075static void iommuAmdInitIllegalDteEvent(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2076 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2077{
2078 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2079 pEvtIllegalDte->n.u16DevId = uDevId;
2080 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2081 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2082 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2083 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2084 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2085 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2086 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2087 * IOMMU spec here but not for this field for I/O page fault event. */
2088 Assert(!(uIova & UINT64_C(0x3)));
2089}
2090
2091
2092/**
2093 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2094 *
2095 * @param pDevIns The IOMMU instance data.
2096 * @param enmOp The IOMMU operation being performed.
2097 * @param pEvtIllegalDte The illegal device table entry event.
2098 * @param enmEvtType The illegal device table entry event type.
2099 *
2100 * @thread Any.
2101 */
2102static void iommuAmdRaiseIllegalDteEvent(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2103 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2104{
2105 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2106 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2107
2108 IOMMU_LOCK_NORET(pDevIns);
2109
2110 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2111 if (enmOp != IOMMUOP_CMD)
2112 iommuAmdSetPciTargetAbort(pDevIns);
2113
2114 IOMMU_UNLOCK(pDevIns);
2115
2116 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2117 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2118 NOREF(enmEvtType);
2119}
2120
2121
2122/**
2123 * Initializes an IO_PAGE_FAULT event.
2124 *
2125 * @param uDevId The device ID.
2126 * @param uDomainId The domain ID.
2127 * @param uIova The I/O virtual address being accessed.
2128 * @param fPresent Transaction to a page marked as present (including
2129 * DTE.V=1) or interrupt marked as remapped
2130 * (IRTE.RemapEn=1).
2131 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2132 * the I/O page fault was caused by invalid level
2133 * encoding.
2134 * @param fPermDenied Permission denied for the address being accessed.
2135 * @param enmOp The IOMMU operation being performed.
2136 * @param pEvtIoPageFault Where to store the initialized event.
2137 */
2138static void iommuAmdInitIoPageFaultEvent(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2139 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2140{
2141 Assert(!fPermDenied || fPresent);
2142 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2143 pEvtIoPageFault->n.u16DevId = uDevId;
2144 //pEvtIoPageFault->n.u4PasidHi = 0;
2145 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2146 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2147 //pEvtIoPageFault->n.u1NoExecute = 0;
2148 //pEvtIoPageFault->n.u1User = 0;
2149 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2150 pEvtIoPageFault->n.u1Present = fPresent;
2151 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2152 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2153 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2154 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2155 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2156 pEvtIoPageFault->n.u64Addr = uIova;
2157}
2158
2159
2160/**
2161 * Raises an IO_PAGE_FAULT event.
2162 *
2163 * @param pDevIns The IOMMU instance data.
2164 * @param pDte The device table entry. Optional, can be NULL
2165 * depending on @a enmOp.
2166 * @param pIrte The interrupt remapping table entry. Optional, can
2167 * be NULL depending on @a enmOp.
2168 * @param enmOp The IOMMU operation being performed.
2169 * @param pEvtIoPageFault The I/O page fault event.
2170 * @param enmEvtType The I/O page fault event type.
2171 *
2172 * @thread Any.
2173 */
2174static void iommuAmdRaiseIoPageFaultEvent(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2175 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2176{
2177 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2178 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2179
2180 IOMMU_LOCK_NORET(pDevIns);
2181
2182 bool fSuppressEvtLogging = false;
2183 if ( enmOp == IOMMUOP_MEM_READ
2184 || enmOp == IOMMUOP_MEM_WRITE)
2185 {
2186 if ( pDte
2187 && pDte->n.u1Valid)
2188 {
2189 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2190 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2191 * suppression. Perhaps will be possible when we complete IOTLB/cache
2192 * handling. */
2193 }
2194 }
2195 else if (enmOp == IOMMUOP_INTR_REQ)
2196 {
2197 if ( pDte
2198 && pDte->n.u1IntrMapValid)
2199 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2200
2201 if ( !fSuppressEvtLogging
2202 && pIrte)
2203 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2204 }
2205 /* else: Events are never suppressed for commands. */
2206
2207 switch (enmEvtType)
2208 {
2209 case kIoPageFaultType_PermDenied:
2210 {
2211 /* Cannot be triggered by a command. */
2212 Assert(enmOp != IOMMUOP_CMD);
2213 RT_FALL_THRU();
2214 }
2215 case kIoPageFaultType_DteRsvdPagingMode:
2216 case kIoPageFaultType_PteInvalidPageSize:
2217 case kIoPageFaultType_PteInvalidLvlEncoding:
2218 case kIoPageFaultType_SkippedLevelIovaNotZero:
2219 case kIoPageFaultType_PteRsvdNotZero:
2220 case kIoPageFaultType_PteValidNotSet:
2221 case kIoPageFaultType_DteTranslationDisabled:
2222 case kIoPageFaultType_PasidInvalidRange:
2223 {
2224 /*
2225 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2226 * create an event log entry. See AMD spec. 2.1.3.2 "I/O Page Faults".
2227 */
2228 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2229 {
2230 if (!fSuppressEvtLogging)
2231 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2232 if (enmOp != IOMMUOP_CMD)
2233 iommuAmdSetPciTargetAbort(pDevIns);
2234 }
2235 break;
2236 }
2237
2238 case kIoPageFaultType_UserSupervisor:
2239 {
2240 /* Access is blocked and only creates an event log entry. */
2241 if (!fSuppressEvtLogging)
2242 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2243 break;
2244 }
2245
2246 case kIoPageFaultType_IrteAddrInvalid:
2247 case kIoPageFaultType_IrteRsvdNotZero:
2248 case kIoPageFaultType_IrteRemapEn:
2249 case kIoPageFaultType_IrteRsvdIntType:
2250 case kIoPageFaultType_IntrReqAborted:
2251 case kIoPageFaultType_IntrWithPasid:
2252 {
2253 /* Only trigerred by interrupt requests. */
2254 Assert(enmOp == IOMMUOP_INTR_REQ);
2255 if (!fSuppressEvtLogging)
2256 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2257 iommuAmdSetPciTargetAbort(pDevIns);
2258 break;
2259 }
2260
2261 case kIoPageFaultType_SmiFilterMismatch:
2262 {
2263 /* Not supported and probably will never be, assert. */
2264 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2265 break;
2266 }
2267
2268 case kIoPageFaultType_DevId_Invalid:
2269 {
2270 /* Cannot be triggered by a command. */
2271 Assert(enmOp != IOMMUOP_CMD);
2272 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2273 if (!fSuppressEvtLogging)
2274 iommuAmdWriteEvtLogEntry(pDevIns, pEvent);
2275 if ( enmOp == IOMMUOP_MEM_READ
2276 || enmOp == IOMMUOP_MEM_WRITE)
2277 iommuAmdSetPciTargetAbort(pDevIns);
2278 break;
2279 }
2280 }
2281
2282 IOMMU_UNLOCK(pDevIns);
2283}
2284
2285
2286/**
2287 * Returns whether the I/O virtual address is to be excluded from translation and
2288 * permission checks.
2289 *
2290 * @returns @c true if the DVA is excluded, @c false otherwise.
2291 * @param pThis The IOMMU device state.
2292 * @param pDte The device table entry.
2293 * @param uIova The I/O virtual address.
2294 *
2295 * @remarks Ensure the exclusion range is enabled prior to calling this function.
2296 *
2297 * @thread Any.
2298 */
2299static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2300{
2301 /* Ensure the exclusion range is enabled. */
2302 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2303
2304 /* Check if the IOVA falls within the exclusion range. */
2305 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2306 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2307 if (uIovaExclLast - uIova >= uIovaExclFirst)
2308 {
2309 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2310 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2311 || pDte->n.u1AllowExclusion)
2312 return true;
2313 }
2314 return false;
2315}
2316
2317
2318/**
2319 * Reads a device table entry from guest memory given the device ID.
2320 *
2321 * @returns VBox status code.
2322 * @param pDevIns The IOMMU device instance.
2323 * @param uDevId The device ID.
2324 * @param enmOp The IOMMU operation being performed.
2325 * @param pDte Where to store the device table entry.
2326 *
2327 * @thread Any.
2328 */
2329static int iommuAmdReadDte(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2330{
2331 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2332 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2333
2334 /* Figure out which device table segment is being accessed. */
2335 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2336 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2337
2338 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2339 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2340 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
2341
2342 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2343 uint32_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2344 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2345
2346 /* Ensure the DTE falls completely within the device table segment. */
2347 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
2348 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
2349 {
2350 /* Read the device table entry from guest memory. */
2351 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2352 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2353 if (RT_SUCCESS(rc))
2354 return rc;
2355
2356 /* Raise a device table hardware error. */
2357 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2358
2359 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2360 iommuAmdInitDevTabHwErrorEvent(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2361 iommuAmdRaiseDevTabHwErrorEvent(pDevIns, enmOp, &EvtDevTabHwErr);
2362 return VERR_IOMMU_DTE_READ_FAILED;
2363 }
2364
2365 /* Raise an I/O page fault for out-of-bounds acccess. */
2366 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2367 iommuAmdInitIoPageFaultEvent(uDevId, 0 /* uDomainId */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
2368 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2369 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_DevId_Invalid);
2370 return VERR_IOMMU_DTE_BAD_OFFSET;
2371}
2372
2373
2374/**
2375 * Walks the I/O page table to translate the I/O virtual address to a system
2376 * physical address.
2377 *
2378 * @returns VBox status code.
2379 * @param pDevIns The IOMMU device instance.
2380 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2381 * @param uDevId The device ID.
2382 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2383 * permissions for the access being made.
2384 * @param pDte The device table entry.
2385 * @param enmOp The IOMMU operation being performed.
2386 * @param pWalkResult Where to store the results of the I/O page walk. This is
2387 * only updated when VINF_SUCCESS is returned.
2388 *
2389 * @thread Any.
2390 */
2391static int iommuAmdWalkIoPageTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2392 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2393{
2394 Assert(pDte->n.u1Valid);
2395 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2396
2397 /* If the translation is not valid, raise an I/O page fault. */
2398 if (pDte->n.u1TranslationValid)
2399 { /* likely */ }
2400 else
2401 {
2402 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2403 * doesn't explicitly say whether an I/O page fault is raised. From other
2404 * places in the spec. it seems early page walk terminations (starting with
2405 * the DTE) return the state computed so far and raises an I/O page fault. So
2406 * returning an invalid translation rather than skipping translation. */
2407 LogFunc(("Translation valid bit not set -> IOPF\n"));
2408 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2409 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2410 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2411 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2412 kIoPageFaultType_DteTranslationDisabled);
2413 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2414 }
2415
2416 /* If the root page table level is 0, translation is skipped and access is controlled by the permission bits. */
2417 uint8_t const uMaxLevel = pDte->n.u3Mode;
2418 if (uMaxLevel != 0)
2419 { /* likely */ }
2420 else
2421 {
2422 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2423 if ((fAccess & fDtePerm) != fAccess)
2424 {
2425 LogFunc(("Access denied for IOVA %#RX64. uDevId=%#x fAccess=%#x fDtePerm=%#x\n", uIova, uDevId, fAccess, fDtePerm));
2426 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2427 }
2428 pWalkResult->GCPhysSpa = uIova;
2429 pWalkResult->cShift = 0;
2430 pWalkResult->fIoPerm = fDtePerm;
2431 return VINF_SUCCESS;
2432 }
2433
2434 /* If the root page table level exceeds the allowed host-address translation level, page walk is terminated. */
2435 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2436 { /* likely */ }
2437 else
2438 {
2439 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2440 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2441 * I'm just going with I/O page fault. */
2442 LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
2443 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2444 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2445 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2446 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2447 kIoPageFaultType_PteInvalidLvlEncoding);
2448 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2449 }
2450
2451 /* Check permissions bits of the root page table. */
2452 uint8_t const fRootPtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2453 if ((fAccess & fRootPtePerm) == fAccess)
2454 { /* likely */ }
2455 else
2456 {
2457 LogFunc(("Permission denied (fAccess=%#x fRootPtePerm=%#x) -> IOPF\n", fAccess, fRootPtePerm));
2458 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2459 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2460 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2461 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2462 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2463 }
2464
2465 /** @todo r=ramshankar: IOMMU: Consider splitting the rest of this into a separate
2466 * function called iommuAmdWalkIoPageDirectory() and call it for multi-page
2467 * accesses from the 2nd page. We can avoid re-checking the DTE root-page
2468 * table entry every time. Not sure if it's worth optimizing that case now
2469 * or if at all. */
2470
2471 /* The virtual address bits indexing table. */
2472 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2473 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2474 UINT64_C(0x00000000001ff000),
2475 UINT64_C(0x000000003fe00000),
2476 UINT64_C(0x0000007fc0000000),
2477 UINT64_C(0x0000ff8000000000),
2478 UINT64_C(0x01ff000000000000),
2479 UINT64_C(0xfe00000000000000),
2480 UINT64_C(0x0000000000000000) };
2481 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2482 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2483
2484 /* Traverse the I/O page table starting with the page directory in the DTE. */
2485 IOPTENTITY_T PtEntity;
2486 PtEntity.u64 = pDte->au64[0];
2487 for (;;)
2488 {
2489 /* Figure out the system physical address of the page table at the current level. */
2490 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2491
2492 /* Read the page table entity at the current level. */
2493 {
2494 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2495 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2496 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2497 uint64_t const offPte = idxPte << 3;
2498 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2499 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2500 if (RT_FAILURE(rc))
2501 {
2502 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2503 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2504 iommuAmdInitPageTabHwErrorEvent(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2505 iommuAmdRaisePageTabHwErrorEvent(pDevIns, enmOp, &EvtPageTabHwErr);
2506 return VERR_IOMMU_IPE_2;
2507 }
2508 }
2509
2510 /* Check present bit. */
2511 if (PtEntity.n.u1Present)
2512 { /* likely */ }
2513 else
2514 {
2515 LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
2516 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2517 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2518 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2519 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2520 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2521 }
2522
2523 /* Check permission bits. */
2524 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2525 if ((fAccess & fPtePerm) == fAccess)
2526 { /* likely */ }
2527 else
2528 {
2529 LogFunc(("Page table entry access denied (uDevId=%#x fAccess=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fAccess, fPtePerm));
2530 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2531 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2532 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2533 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2534 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2535 }
2536
2537 /* If this is a PTE, we're at the final level and we're done. */
2538 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2539 if (uNextLevel == 0)
2540 {
2541 /* The page size of the translation is the default (4K). */
2542 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2543 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2544 pWalkResult->fIoPerm = fPtePerm;
2545 return VINF_SUCCESS;
2546 }
2547 if (uNextLevel == 7)
2548 {
2549 /* The default page size of the translation is overridden. */
2550 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2551 uint8_t cShift = X86_PAGE_4K_SHIFT;
2552 while (GCPhysPte & RT_BIT_64(cShift++))
2553 ;
2554
2555 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2556 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2557 if ( cShift > s_acIovaLevelShifts[uLevel]
2558 && cShift < s_acIovaLevelShifts[uLevel + 1])
2559 {
2560 pWalkResult->GCPhysSpa = GCPhysPte;
2561 pWalkResult->cShift = cShift;
2562 pWalkResult->fIoPerm = fPtePerm;
2563 return VINF_SUCCESS;
2564 }
2565
2566 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2567 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2568 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2569 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2570 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2571 kIoPageFaultType_PteInvalidPageSize);
2572 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2573 }
2574
2575 /* Validate the next level encoding of the PDE. */
2576#if IOMMU_MAX_HOST_PT_LEVEL < 6
2577 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2578 { /* likely */ }
2579 else
2580 {
2581 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2582 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2583 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2584 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2585 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2586 kIoPageFaultType_PteInvalidLvlEncoding);
2587 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2588 }
2589#else
2590 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2591#endif
2592
2593 /* Validate level transition. */
2594 if (uNextLevel < uLevel)
2595 { /* likely */ }
2596 else
2597 {
2598 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2599 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2600 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2601 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2602 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2603 kIoPageFaultType_PteInvalidLvlEncoding);
2604 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2605 }
2606
2607 /* Ensure IOVA bits of skipped levels are zero. */
2608 Assert(uLevel > 0);
2609 uint64_t uIovaSkipMask = 0;
2610 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2611 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2612 if (!(uIova & uIovaSkipMask))
2613 { /* likely */ }
2614 else
2615 {
2616 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2617 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2618 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2619 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2620 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2621 kIoPageFaultType_SkippedLevelIovaNotZero);
2622 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2623 }
2624
2625 /* Continue with traversing the page directory at this level. */
2626 }
2627}
2628
2629
2630/**
2631 * Looks up an I/O virtual address from the device table.
2632 *
2633 * @returns VBox status code.
2634 * @param pDevIns The IOMMU instance data.
2635 * @param uDevId The device ID.
2636 * @param uIova The I/O virtual address to lookup.
2637 * @param cbAccess The size of the access.
2638 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2639 * permissions for the access being made.
2640 * @param enmOp The IOMMU operation being performed.
2641 * @param pGCPhysSpa Where to store the translated system physical address. Only
2642 * valid when translation succeeds and VINF_SUCCESS is
2643 * returned!
2644 *
2645 * @thread Any.
2646 */
2647static int iommuAmdLookupDeviceTable(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2648 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa)
2649{
2650 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2651
2652 /* Read the device table entry from memory. */
2653 DTE_T Dte;
2654 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
2655 if (RT_SUCCESS(rc))
2656 {
2657 /* If the DTE is not valid, addresses are forwarded without translation */
2658 if (Dte.n.u1Valid)
2659 { /* likely */ }
2660 else
2661 {
2662 /** @todo IOMMU: Add to IOLTB cache. */
2663 *pGCPhysSpa = uIova;
2664 return VINF_SUCCESS;
2665 }
2666
2667 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2668 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2669 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2670 if (RT_LIKELY( !fRsvd0
2671 && !fRsvd1))
2672 { /* likely */ }
2673 else
2674 {
2675 LogFunc(("Invalid reserved bits in DTE (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
2676 EVT_ILLEGAL_DTE_T Event;
2677 iommuAmdInitIllegalDteEvent(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
2678 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
2679 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2680 }
2681
2682 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2683 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable /** @todo lock or make atomic read? */
2684 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2685 { /* likely */ }
2686 else
2687 {
2688 /** @todo IOMMU: Add to IOLTB cache. */
2689 *pGCPhysSpa = uIova;
2690 return VINF_SUCCESS;
2691 }
2692
2693 /** @todo IOMMU: Perhaps do the <= 4K access case first, if the generic loop
2694 * below gets too expensive and when we have iommuAmdWalkIoPageDirectory. */
2695
2696 uint64_t uBaseIova = uIova & X86_PAGE_4K_BASE_MASK;
2697 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2698 uint64_t cbRemaining = cbAccess;
2699 for (;;)
2700 {
2701 /* Walk the I/O page tables to translate the IOVA and check permission for the access. */
2702 IOWALKRESULT WalkResult;
2703 rc = iommuAmdWalkIoPageTable(pDevIns, uDevId, uBaseIova, fAccess, &Dte, enmOp, &WalkResult);
2704 if (RT_SUCCESS(rc))
2705 {
2706 /** @todo IOMMU: Split large pages into 4K IOTLB entries and add to IOTLB cache. */
2707
2708 /* If translation is disabled for this device (root paging mode is 0), we're done. */
2709 if (WalkResult.cShift == 0)
2710 {
2711 *pGCPhysSpa = uIova;
2712 break;
2713 }
2714
2715 /* Store the translated base address before continuing to check permissions for any more pages. */
2716 Assert(WalkResult.cShift >= X86_PAGE_4K_SHIFT);
2717 if (cbRemaining == cbAccess)
2718 {
2719 uint64_t const offMask = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2720 uint64_t const offSpa = uIova & offMask;
2721 *pGCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2722 }
2723
2724 /* If the access exceeds the page size, check permissions for the subsequent page. */
2725 uint64_t const cbPhysPage = UINT64_C(1) << WalkResult.cShift;
2726 if (cbRemaining > cbPhysPage - offIova)
2727 {
2728 cbRemaining -= (cbPhysPage - offIova);
2729 uBaseIova += cbPhysPage; /** @todo r=ramshankar: Should we mask the offset based on page size here? */
2730 offIova = 0;
2731 }
2732 else
2733 break;
2734 }
2735 else
2736 {
2737 LogFunc(("I/O page table walk failed. uIova=%#RX64 uBaseIova=%#RX64 fAccess=%u rc=%Rrc\n", uIova,
2738 uBaseIova, fAccess, rc));
2739 *pGCPhysSpa = NIL_RTGCPHYS;
2740 return rc;
2741 }
2742 }
2743
2744 return rc;
2745 }
2746
2747 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
2748 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2749}
2750
2751
2752/**
2753 * Memory access transaction from a device.
2754 *
2755 * @returns VBox status code.
2756 * @param pDevIns The IOMMU device instance.
2757 * @param uDevId The device ID (bus, device, function).
2758 * @param uIova The I/O virtual address being accessed.
2759 * @param cbAccess The number of bytes being accessed.
2760 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2761 * @param pGCPhysSpa Where to store the translated system physical address.
2762 *
2763 * @thread Any.
2764 */
2765static DECLCALLBACK(int) iommuAmdDeviceMemAccess(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
2766 uint32_t fFlags, PRTGCPHYS pGCPhysSpa)
2767{
2768 /* Validate. */
2769 AssertPtr(pDevIns);
2770 AssertPtr(pGCPhysSpa);
2771 Assert(cbAccess > 0);
2772 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2773
2774 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2775 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2776 if (Ctrl.n.u1IommuEn)
2777 {
2778 IOMMUOP enmOp;
2779 uint8_t fAccess;
2780 if (fFlags & PDMIOMMU_MEM_F_READ)
2781 {
2782 enmOp = IOMMUOP_MEM_READ;
2783 fAccess = IOMMU_IO_PERM_READ;
2784 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2785 }
2786 else
2787 {
2788 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
2789 enmOp = IOMMUOP_MEM_WRITE;
2790 fAccess = IOMMU_IO_PERM_WRITE;
2791 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2792 }
2793
2794#ifdef LOG_ENABLED
2795 static const char * const s_apszAccess[] = { "none", "read", "write" };
2796 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
2797 const char *pszAccess = s_apszAccess[fAccess];
2798 LogFlowFunc(("uDevId=%#x uIova=%#RX64 szAccess=%s cbAccess=%zu\n", uDevId, uIova, pszAccess, cbAccess));
2799#endif
2800
2801 /** @todo IOMMU: IOTLB cache lookup. */
2802
2803 /* Lookup the IOVA from the device table. */
2804 int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, uIova, cbAccess, fAccess, enmOp, pGCPhysSpa);
2805 if (RT_SUCCESS(rc))
2806 { /* likely */ }
2807 else
2808 LogFunc(("DTE lookup failed! uDevId=%#x uIova=%#RX64 fAccess=%u cbAccess=%zu rc=%#Rrc\n", uDevId, uIova, fAccess,
2809 cbAccess, rc));
2810 return rc;
2811 }
2812
2813 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2814 *pGCPhysSpa = uIova;
2815 return VINF_SUCCESS;
2816}
2817
2818
2819/**
2820 * Memory access bulk (one or more 4K pages) request from a device.
2821 *
2822 * @returns VBox status code.
2823 * @param pDevIns The IOMMU device instance.
2824 * @param uDevId The device ID (bus, device, function).
2825 * @param cIovas The number of addresses being accessed.
2826 * @param pauIovas The I/O virtual addresses for each page being accessed.
2827 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2828 * @param paGCPhysSpa Where to store the translated physical addresses.
2829 *
2830 * @thread Any.
2831 */
2832static DECLCALLBACK(int) iommuAmdDeviceMemBulkAccess(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas,
2833 uint64_t const *pauIovas, uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2834{
2835 /* Validate. */
2836 AssertPtr(pDevIns);
2837 Assert(cIovas > 0);
2838 AssertPtr(pauIovas);
2839 AssertPtr(paGCPhysSpa);
2840 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2841
2842 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2843 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2844 if (Ctrl.n.u1IommuEn)
2845 {
2846 IOMMUOP enmOp;
2847 uint8_t fAccess;
2848 if (fFlags & PDMIOMMU_MEM_F_READ)
2849 {
2850 enmOp = IOMMUOP_MEM_READ;
2851 fAccess = IOMMU_IO_PERM_READ;
2852 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2853 }
2854 else
2855 {
2856 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
2857 enmOp = IOMMUOP_MEM_WRITE;
2858 fAccess = IOMMU_IO_PERM_WRITE;
2859 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2860 }
2861
2862#ifdef LOG_ENABLED
2863 static const char * const s_apszAccess[] = { "none", "read", "write" };
2864 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
2865 const char *pszAccess = s_apszAccess[fAccess];
2866 LogFlowFunc(("uDevId=%#x cIovas=%zu szAccess=%s\n", uDevId, cIovas, pszAccess));
2867#endif
2868
2869 /** @todo IOMMU: IOTLB cache lookup. */
2870
2871 /* Lookup each IOVA from the device table. */
2872 for (size_t i = 0; i < cIovas; i++)
2873 {
2874 int rc = iommuAmdLookupDeviceTable(pDevIns, uDevId, pauIovas[i], X86_PAGE_SIZE, fAccess, enmOp, &paGCPhysSpa[i]);
2875 if (RT_SUCCESS(rc))
2876 { /* likely */ }
2877 else
2878 {
2879 LogFunc(("Failed! uDevId=%#x uIova=%#RX64 fAccess=%u rc=%Rrc\n", uDevId, pauIovas[i], fAccess, rc));
2880 return rc;
2881 }
2882 }
2883 }
2884 else
2885 {
2886 /* Addresses are forwarded without translation when the IOMMU is disabled. */
2887 for (size_t i = 0; i < cIovas; i++)
2888 paGCPhysSpa[i] = pauIovas[i];
2889 }
2890
2891 return VINF_SUCCESS;
2892}
2893
2894
2895
2896/**
2897 * Reads an interrupt remapping table entry from guest memory given its DTE.
2898 *
2899 * @returns VBox status code.
2900 * @param pDevIns The IOMMU device instance.
2901 * @param uDevId The device ID.
2902 * @param pDte The device table entry.
2903 * @param GCPhysIn The source MSI address (used for reporting errors).
2904 * @param uDataIn The source MSI data.
2905 * @param enmOp The IOMMU operation being performed.
2906 * @param pIrte Where to store the interrupt remapping table entry.
2907 *
2908 * @thread Any.
2909 */
2910static int iommuAmdReadIrte(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
2911 IOMMUOP enmOp, PIRTE_T pIrte)
2912{
2913 /* Ensure the IRTE length is valid. */
2914 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
2915
2916 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
2917 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
2918 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
2919 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
2920
2921 /* Ensure the IRTE falls completely within the interrupt table. */
2922 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
2923 { /* likely */ }
2924 else
2925 {
2926 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
2927 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
2928
2929 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2930 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
2931 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2932 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteAddrInvalid);
2933 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2934 }
2935
2936 /* Read the IRTE from memory. */
2937 Assert(!(GCPhysIrte & 3));
2938 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
2939 if (RT_SUCCESS(rc))
2940 return VINF_SUCCESS;
2941
2942 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
2943 * situation. Is it an I/O page fault or a device table hardware error?
2944 * There's no interrupt table hardware error event, but it's unclear what
2945 * we should do here. */
2946 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
2947 return VERR_IOMMU_IPE_4;
2948}
2949
2950
2951/**
2952 * Remaps the interrupt using the interrupt remapping table.
2953 *
2954 * @returns VBox status code.
2955 * @param pDevIns The IOMMU instance data.
2956 * @param uDevId The device ID.
2957 * @param pDte The device table entry.
2958 * @param enmOp The IOMMU operation being performed.
2959 * @param pMsiIn The source MSI.
2960 * @param pMsiOut Where to store the remapped MSI.
2961 *
2962 * @thread Any.
2963 */
2964static int iommuAmdRemapIntr(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
2965 PMSIMSG pMsiOut)
2966{
2967 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
2968
2969 IRTE_T Irte;
2970 int rc = iommuAmdReadIrte(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
2971 if (RT_SUCCESS(rc))
2972 {
2973 if (Irte.n.u1RemapEnable)
2974 {
2975 if (!Irte.n.u1GuestMode)
2976 {
2977 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
2978 {
2979 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
2980 *pMsiOut = *pMsiIn;
2981
2982 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
2983 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
2984
2985 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
2986 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
2987
2988 return VINF_SUCCESS;
2989 }
2990
2991 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
2992 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2993 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
2994 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
2995 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
2996 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2997 }
2998
2999 LogFunc(("Guest mode not supported -> IOPF\n"));
3000 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3001 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3002 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3003 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3004 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3005 }
3006
3007 LogFunc(("Remapping disabled -> IOPF\n"));
3008 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3009 iommuAmdInitIoPageFaultEvent(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3010 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3011 iommuAmdRaiseIoPageFaultEvent(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3012 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3013 }
3014
3015 return rc;
3016}
3017
3018
3019/**
3020 * Looks up an MSI interrupt from the interrupt remapping table.
3021 *
3022 * @returns VBox status code.
3023 * @param pDevIns The IOMMU instance data.
3024 * @param uDevId The device ID.
3025 * @param enmOp The IOMMU operation being performed.
3026 * @param pMsiIn The source MSI.
3027 * @param pMsiOut Where to store the remapped MSI.
3028 *
3029 * @thread Any.
3030 */
3031static int iommuAmdLookupIntrTable(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3032{
3033 /* Read the device table entry from memory. */
3034 LogFlowFunc(("uDevId=%#x (%#x:%#x:%#x) enmOp=%u\n", uDevId,
3035 ((uDevId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
3036 ((uDevId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (uDevId & VBOX_PCI_DEVFN_FUN_MASK), enmOp));
3037
3038 DTE_T Dte;
3039 int rc = iommuAmdReadDte(pDevIns, uDevId, enmOp, &Dte);
3040 if (RT_SUCCESS(rc))
3041 {
3042 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
3043 if (Dte.n.u1IntrMapValid)
3044 {
3045 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3046 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3047 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3048 if (RT_LIKELY( !fRsvd0
3049 && !fRsvd1))
3050 { /* likely */ }
3051 else
3052 {
3053 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3054 fRsvd1));
3055 EVT_ILLEGAL_DTE_T Event;
3056 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3057 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3058 return VERR_IOMMU_INTR_REMAP_FAILED;
3059 }
3060
3061 /*
3062 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3063 * that's connected through HyperTransport it might be possible; but for us, it
3064 * doesn't seem we need to specially handle these pins.
3065 */
3066
3067 /*
3068 * Validate the MSI source address.
3069 *
3070 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3071 * CPU is concerned, the MSI region is fixed and we must ensure no other device
3072 * claims the region as I/O space.
3073 *
3074 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3075 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3076 * See Intel spec. 10.11.1 "Message Address Register Format".
3077 */
3078 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3079 {
3080 /*
3081 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3082 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3083 */
3084 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3085 bool fPassThru = false;
3086 switch (u8DeliveryMode)
3087 {
3088 case VBOX_MSI_DELIVERY_MODE_FIXED:
3089 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3090 {
3091 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3092 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3093 {
3094 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3095 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3096 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3097 {
3098 /*
3099 * We don't support guest interrupt remapping yet. When we do, we'll need to
3100 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3101 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3102 * already reads the control register, add that as a parameter when we eventually
3103 * support guest interrupt remapping. For now, just assert.
3104 */
3105 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3106 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3107 NOREF(pThis);
3108
3109 return iommuAmdRemapIntr(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3110 }
3111
3112 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3113 EVT_ILLEGAL_DTE_T Event;
3114 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3115 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3116 return VERR_IOMMU_INTR_REMAP_FAILED;
3117 }
3118
3119 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3120 {
3121 fPassThru = true;
3122 break;
3123 }
3124
3125 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3126 {
3127 LogFunc(("IntCtl=0: Remapping disallowed for fixed/arbitrated interrupt (%#x) -> Target abort\n",
3128 pMsiIn->Data.n.u8Vector));
3129 iommuAmdSetPciTargetAbort(pDevIns);
3130 return VERR_IOMMU_INTR_REMAP_DENIED;
3131 }
3132
3133 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
3134 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3135 EVT_ILLEGAL_DTE_T Event;
3136 iommuAmdInitIllegalDteEvent(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3137 iommuAmdRaiseIllegalDteEvent(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3138 return VERR_IOMMU_INTR_REMAP_FAILED;
3139 }
3140
3141 /* SMIs are passed through unmapped. We don't implement SMI filters. */
3142 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3143 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3144 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3145 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3146 default:
3147 {
3148 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3149 iommuAmdSetPciTargetAbort(pDevIns);
3150 return VERR_IOMMU_INTR_REMAP_FAILED;
3151 }
3152 }
3153
3154 /*
3155 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
3156 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
3157 */
3158 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
3159 || !pMsiIn->Addr.n.u1DestMode)
3160 {
3161 if (fPassThru)
3162 {
3163 *pMsiOut = *pMsiIn;
3164 return VINF_SUCCESS;
3165 }
3166 LogFunc(("Remapping/passthru disallowed for interrupt %#x -> Target abort\n", pMsiIn->Data.n.u8Vector));
3167 }
3168 else
3169 LogFunc(("Logical destination mode invalid for delivery mode %#x\n -> Target abort\n", u8DeliveryMode));
3170
3171 iommuAmdSetPciTargetAbort(pDevIns);
3172 return VERR_IOMMU_INTR_REMAP_DENIED;
3173 }
3174 else
3175 {
3176 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3177 return VERR_IOMMU_INTR_REMAP_FAILED;
3178 }
3179 }
3180 else
3181 {
3182 /** @todo IOMMU: Add to interrupt remapping cache. */
3183 LogFlowFunc(("DTE interrupt map not valid\n"));
3184 *pMsiOut = *pMsiIn;
3185 return VINF_SUCCESS;
3186 }
3187 }
3188
3189 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3190 return VERR_IOMMU_INTR_REMAP_FAILED;
3191}
3192
3193
3194/**
3195 * Interrupt remap request from a device.
3196 *
3197 * @returns VBox status code.
3198 * @param pDevIns The IOMMU device instance.
3199 * @param uDevId The device ID (bus, device, function).
3200 * @param pMsiIn The source MSI.
3201 * @param pMsiOut Where to store the remapped MSI.
3202 */
3203static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3204{
3205 /* Validate. */
3206 Assert(pDevIns);
3207 Assert(pMsiIn);
3208 Assert(pMsiOut);
3209
3210 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3211
3212 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3213 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3214 if (Ctrl.n.u1IommuEn)
3215 {
3216 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3217 /** @todo Cache? */
3218
3219 return iommuAmdLookupIntrTable(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3220 }
3221
3222 *pMsiOut = *pMsiIn;
3223 return VINF_SUCCESS;
3224}
3225
3226
3227/**
3228 * @callback_method_impl{FNIOMMMIONEWWRITE}
3229 */
3230static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3231{
3232 NOREF(pvUser);
3233 Assert(cb == 4 || cb == 8);
3234 Assert(!(off & (cb - 1)));
3235
3236 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3237 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3238
3239 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
3240 return iommuAmdWriteRegister(pDevIns, off, cb, uValue);
3241}
3242
3243
3244/**
3245 * @callback_method_impl{FNIOMMMIONEWREAD}
3246 */
3247static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3248{
3249 NOREF(pvUser);
3250 Assert(cb == 4 || cb == 8);
3251 Assert(!(off & (cb - 1)));
3252
3253 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3254 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3255
3256 uint64_t uResult;
3257 VBOXSTRICTRC rcStrict = iommuAmdReadRegister(pDevIns, off, &uResult);
3258 if (cb == 8)
3259 *(uint64_t *)pv = uResult;
3260 else
3261 *(uint32_t *)pv = (uint32_t)uResult;
3262
3263 return rcStrict;
3264}
3265
3266# ifdef IN_RING3
3267
3268/**
3269 * Processes an IOMMU command.
3270 *
3271 * @returns VBox status code.
3272 * @param pDevIns The IOMMU device instance.
3273 * @param pCmd The command to process.
3274 * @param GCPhysCmd The system physical address of the command.
3275 * @param pEvtError Where to store the error event in case of failures.
3276 *
3277 * @thread Command thread.
3278 */
3279static int iommuAmdR3ProcessCmd(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3280{
3281 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3282
3283 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3284 STAM_COUNTER_INC(&pThis->StatCmd);
3285
3286 uint8_t const bCmd = pCmd->n.u4Opcode;
3287 switch (bCmd)
3288 {
3289 case IOMMU_CMD_COMPLETION_WAIT:
3290 {
3291 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3292
3293 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3294 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
3295
3296 /* Validate reserved bits in the command. */
3297 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3298 {
3299 /* If Completion Store is requested, write the StoreData to the specified address. */
3300 if (pCmdComWait->n.u1Store)
3301 {
3302 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3303 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3304 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3305 if (RT_FAILURE(rc))
3306 {
3307 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3308 GCPhysStore, rc));
3309 iommuAmdInitCmdHwErrorEvent(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3310 return VERR_IOMMU_CMD_HW_ERROR;
3311 }
3312 }
3313
3314 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3315 if (pCmdComWait->n.u1Interrupt)
3316 {
3317 IOMMU_LOCK(pDevIns);
3318 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3319 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3320 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3321 IOMMU_UNLOCK(pDevIns);
3322
3323 if (fRaiseInt)
3324 iommuAmdRaiseMsiInterrupt(pDevIns);
3325 }
3326 return VINF_SUCCESS;
3327 }
3328 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3329 return VERR_IOMMU_CMD_INVALID_FORMAT;
3330 }
3331
3332 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3333 {
3334 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3335 * then. */
3336 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3337 return VINF_SUCCESS;
3338 }
3339
3340 case IOMMU_CMD_INV_IOMMU_PAGES:
3341 {
3342 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3343 * then. */
3344 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3345 return VINF_SUCCESS;
3346 }
3347
3348 case IOMMU_CMD_INV_IOTLB_PAGES:
3349 {
3350 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3351
3352 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3353 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3354 {
3355 /** @todo IOMMU: Implement remote IOTLB invalidation. */
3356 return VERR_NOT_IMPLEMENTED;
3357 }
3358 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3359 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3360 }
3361
3362 case IOMMU_CMD_INV_INTR_TABLE:
3363 {
3364 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3365 * then. */
3366 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3367 return VINF_SUCCESS;
3368 }
3369
3370 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3371 {
3372 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3373 if (pThis->ExtFeat.n.u1PrefetchSup)
3374 {
3375 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
3376 return VINF_SUCCESS;
3377 }
3378 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3379 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3380 }
3381
3382 case IOMMU_CMD_COMPLETE_PPR_REQ:
3383 {
3384 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3385
3386 /* We don't support PPR requests yet. */
3387 Assert(!pThis->ExtFeat.n.u1PprSup);
3388 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3389 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3390 }
3391
3392 case IOMMU_CMD_INV_IOMMU_ALL:
3393 {
3394 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3395
3396 if (pThis->ExtFeat.n.u1InvAllSup)
3397 {
3398 /** @todo IOMMU: Invalidate all. Pretend success until then. */
3399 return VINF_SUCCESS;
3400 }
3401 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3402 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3403 }
3404 }
3405
3406 STAM_COUNTER_DEC(&pThis->StatCmd);
3407 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3408 iommuAmdInitIllegalCmdEvent(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3409 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3410}
3411
3412
3413/**
3414 * The IOMMU command thread.
3415 *
3416 * @returns VBox status code.
3417 * @param pDevIns The IOMMU device instance.
3418 * @param pThread The command thread.
3419 */
3420static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3421{
3422 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3423
3424 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3425 return VINF_SUCCESS;
3426
3427 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3428 {
3429 /*
3430 * Sleep perpetually until we are woken up to process commands.
3431 */
3432 {
3433 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3434 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3435 if (!fSignaled)
3436 {
3437 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3438 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3439 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3440 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3441 break;
3442 Log4Func(("Woken up with rc=%Rrc\n", rc));
3443 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3444 }
3445 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3446 }
3447
3448 /*
3449 * Fetch and process IOMMU commands.
3450 */
3451 /** @todo r=ramshankar: This employs a simplistic method of fetching commands (one
3452 * at a time) and is expensive due to calls to PGM for fetching guest memory.
3453 * We could optimize by fetching a bunch of commands at a time reducing
3454 * number of calls to PGM. In the longer run we could lock the memory and
3455 * mappings and accessing them directly. */
3456 IOMMU_LOCK(pDevIns);
3457
3458 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3459 if (Status.n.u1CmdBufRunning)
3460 {
3461 /* Get the offset we need to read the command from memory (circular buffer offset). */
3462 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3463 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3464 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3465 Assert(offHead < cbCmdBuf);
3466 while (offHead != pThis->CmdBufTailPtr.n.off)
3467 {
3468 /* Read the command from memory. */
3469 CMD_GENERIC_T Cmd;
3470 RTGCPHYS const GCPhysCmd = (pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT) + offHead;
3471 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmd, &Cmd, sizeof(Cmd));
3472 if (RT_SUCCESS(rc))
3473 {
3474 /* Increment the command buffer head pointer. */
3475 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3476 pThis->CmdBufHeadPtr.n.off = offHead;
3477
3478 /* Process the fetched command. */
3479 EVT_GENERIC_T EvtError;
3480 IOMMU_UNLOCK(pDevIns);
3481 rc = iommuAmdR3ProcessCmd(pDevIns, &Cmd, GCPhysCmd, &EvtError);
3482 IOMMU_LOCK(pDevIns);
3483 if (RT_FAILURE(rc))
3484 {
3485 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3486 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3487 {
3488 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3489 iommuAmdRaiseIllegalCmdEvent(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3490 }
3491 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3492 {
3493 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3494 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", Cmd.n.u4Opcode));
3495 iommuAmdRaiseCmdHwErrorEvent(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3496 }
3497 break;
3498 }
3499 }
3500 else
3501 {
3502 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmd, rc));
3503 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3504 iommuAmdInitCmdHwErrorEvent(GCPhysCmd, &EvtCmdHwErr);
3505 iommuAmdRaiseCmdHwErrorEvent(pDevIns, &EvtCmdHwErr);
3506 break;
3507 }
3508 }
3509 }
3510
3511 IOMMU_UNLOCK(pDevIns);
3512 }
3513
3514 LogFlowFunc(("Command thread terminating\n"));
3515 return VINF_SUCCESS;
3516}
3517
3518
3519/**
3520 * Wakes up the command thread so it can respond to a state change.
3521 *
3522 * @returns VBox status code.
3523 * @param pDevIns The IOMMU device instance.
3524 * @param pThread The command thread.
3525 */
3526static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3527{
3528 RT_NOREF(pThread);
3529 LogFlowFunc(("\n"));
3530 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3531 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3532}
3533
3534
3535/**
3536 * @callback_method_impl{FNPCICONFIGREAD}
3537 */
3538static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3539 unsigned cb, uint32_t *pu32Value)
3540{
3541 /** @todo IOMMU: PCI config read stat counter. */
3542 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3543 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3544 return rcStrict;
3545}
3546
3547
3548/**
3549 * @callback_method_impl{FNPCICONFIGWRITE}
3550 */
3551static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3552 unsigned cb, uint32_t u32Value)
3553{
3554 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3555
3556 /*
3557 * Discard writes to read-only registers that are specific to the IOMMU.
3558 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3559 * See PCI spec. 6.1. "Configuration Space Organization".
3560 */
3561 switch (uAddress)
3562 {
3563 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3564 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3565 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3566 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3567 {
3568 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3569 return VINF_SUCCESS;
3570 }
3571 }
3572
3573 IOMMU_LOCK(pDevIns);
3574
3575 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3576 switch (uAddress)
3577 {
3578 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3579 {
3580 if (pThis->IommuBar.n.u1Enable)
3581 {
3582 rcStrict = VINF_SUCCESS;
3583 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3584 break;
3585 }
3586
3587 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3588 if (pThis->IommuBar.n.u1Enable)
3589 {
3590 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3591 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3592 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
3593 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
3594
3595 /* If the MMIO region is already mapped at the specified address, we're done. */
3596 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
3597 if (GCPhysMmioBasePrev == GCPhysMmioBase)
3598 {
3599 rcStrict = VINF_SUCCESS;
3600 break;
3601 }
3602
3603 /* Unmap the previous MMIO region (which is at a different address). */
3604 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
3605 {
3606 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
3607 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
3608 if (RT_FAILURE(rcStrict))
3609 {
3610 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3611 break;
3612 }
3613 }
3614
3615 /* Map the newly specified MMIO region. */
3616 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
3617 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
3618 if (RT_FAILURE(rcStrict))
3619 {
3620 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3621 break;
3622 }
3623 }
3624 else
3625 rcStrict = VINF_SUCCESS;
3626 break;
3627 }
3628
3629 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
3630 {
3631 if (!pThis->IommuBar.n.u1Enable)
3632 pThis->IommuBar.au32[1] = u32Value;
3633 else
3634 {
3635 rcStrict = VINF_SUCCESS;
3636 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
3637 }
3638 break;
3639 }
3640
3641 case IOMMU_PCI_OFF_MSI_CAP_HDR:
3642 {
3643 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
3644 RT_FALL_THRU();
3645 }
3646 default:
3647 {
3648 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
3649 break;
3650 }
3651 }
3652
3653 IOMMU_UNLOCK(pDevIns);
3654
3655 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
3656 return rcStrict;
3657}
3658
3659
3660/**
3661 * @callback_method_impl{FNDBGFHANDLERDEV}
3662 */
3663static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3664{
3665 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3666 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3667 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3668
3669 bool fVerbose;
3670 if ( pszArgs
3671 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3672 fVerbose = true;
3673 else
3674 fVerbose = false;
3675
3676 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
3677 /* Device Table Base Addresses (all segments). */
3678 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
3679 {
3680 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
3681 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
3682 if (fVerbose)
3683 {
3684 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
3685 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
3686 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
3687 }
3688 }
3689 /* Command Buffer Base Address Register. */
3690 {
3691 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
3692 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
3693 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3694 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3695 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
3696 if (fVerbose)
3697 {
3698 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
3699 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3700 cEntries, cbBuffer);
3701 }
3702 }
3703 /* Event Log Base Address Register. */
3704 {
3705 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
3706 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
3707 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3708 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3709 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
3710 if (fVerbose)
3711 {
3712 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3713 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3714 cEntries, cbBuffer);
3715 }
3716 }
3717 /* IOMMU Control Register. */
3718 {
3719 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
3720 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
3721 if (fVerbose)
3722 {
3723 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
3724 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
3725 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
3726 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3727 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
3728 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
3729 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
3730 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
3731 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
3732 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
3733 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
3734 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
3735 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
3736 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
3737 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
3738 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
3739 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
3740 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
3741 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
3742 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
3743 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
3744 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
3745 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
3746 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
3747 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
3748 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
3749 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
3750 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
3751 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
3752 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
3753 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
3754 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
3755 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
3756 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
3757 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
3758 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
3759 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
3760 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
3761 }
3762 }
3763 /* Exclusion Base Address Register. */
3764 {
3765 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
3766 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
3767 if (fVerbose)
3768 {
3769 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
3770 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
3771 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
3772 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
3773 }
3774 }
3775 /* Exclusion Range Limit Register. */
3776 {
3777 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
3778 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
3779 if (fVerbose)
3780 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
3781 }
3782 /* Extended Feature Register. */
3783 {
3784 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
3785 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
3786 if (fVerbose)
3787 {
3788 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
3789 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
3790 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
3791 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
3792 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
3793 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
3794 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
3795 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
3796 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
3797 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
3798 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
3799 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
3800 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
3801 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
3802 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
3803 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
3804 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
3805 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
3806 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
3807 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
3808 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
3809 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
3810 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
3811 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
3812 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
3813 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
3814 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
3815 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
3816 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
3817 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
3818 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
3819 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
3820 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
3821 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
3822 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
3823 }
3824 }
3825 /* PPR Log Base Address Register. */
3826 {
3827 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
3828 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
3829 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3830 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3831 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
3832 if (fVerbose)
3833 {
3834 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3835 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3836 cEntries, cbBuffer);
3837 }
3838 }
3839 /* Hardware Event (Hi) Register. */
3840 {
3841 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
3842 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
3843 if (fVerbose)
3844 {
3845 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
3846 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
3847 }
3848 }
3849 /* Hardware Event (Lo) Register. */
3850 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
3851 /* Hardware Event Status. */
3852 {
3853 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
3854 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
3855 if (fVerbose)
3856 {
3857 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
3858 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
3859 }
3860 }
3861 /* Guest Virtual-APIC Log Base Address Register. */
3862 {
3863 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
3864 uint8_t const uEncodedLen = GALogBar.n.u4Len;
3865 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3866 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3867 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
3868 if (fVerbose)
3869 {
3870 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
3871 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3872 cEntries, cbBuffer);
3873 }
3874 }
3875 /* Guest Virtual-APIC Log Tail Address Register. */
3876 {
3877 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
3878 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
3879 if (fVerbose)
3880 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
3881 }
3882 /* PPR Log B Base Address Register. */
3883 {
3884 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
3885 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
3886 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3887 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3888 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
3889 if (fVerbose)
3890 {
3891 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3892 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3893 cEntries, cbBuffer);
3894 }
3895 }
3896 /* Event Log B Base Address Register. */
3897 {
3898 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
3899 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
3900 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
3901 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
3902 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
3903 if (fVerbose)
3904 {
3905 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
3906 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
3907 cEntries, cbBuffer);
3908 }
3909 }
3910 /* Device-Specific Feature Extension Register. */
3911 {
3912 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
3913 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
3914 if (fVerbose)
3915 {
3916 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
3917 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
3918 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
3919 }
3920 }
3921 /* Device-Specific Control Extension Register. */
3922 {
3923 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
3924 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
3925 if (fVerbose)
3926 {
3927 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
3928 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
3929 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
3930 }
3931 }
3932 /* Device-Specific Status Extension Register. */
3933 {
3934 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
3935 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
3936 if (fVerbose)
3937 {
3938 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
3939 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
3940 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
3941 }
3942 }
3943 /* Miscellaneous Information Register (Lo and Hi). */
3944 {
3945 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
3946 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
3947 if (fVerbose)
3948 {
3949 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
3950 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
3951 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
3952 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
3953 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
3954 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
3955 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
3956 }
3957 }
3958 /* MSI Capability Header. */
3959 {
3960 MSI_CAP_HDR_T MsiCapHdr;
3961 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
3962 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
3963 if (fVerbose)
3964 {
3965 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
3966 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
3967 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
3968 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
3969 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
3970 }
3971 }
3972 /* MSI Address Register (Lo and Hi). */
3973 {
3974 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
3975 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
3976 MSIADDR MsiAddr;
3977 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
3978 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
3979 if (fVerbose)
3980 {
3981 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
3982 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
3983 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
3984 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
3985 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
3986 }
3987 }
3988 /* MSI Data. */
3989 {
3990 MSIDATA MsiData;
3991 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
3992 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
3993 if (fVerbose)
3994 {
3995 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
3996 MsiData.n.u8Vector);
3997 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
3998 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
3999 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4000 "level" : "edge");
4001 }
4002 }
4003 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4004 {
4005 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4006 MsiMapCapHdr.u32 = 0;
4007 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4008 if (fVerbose)
4009 {
4010 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4011 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4012 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4013 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4014 }
4015 }
4016 /* Performance Optimization Control Register. */
4017 {
4018 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4019 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4020 if (fVerbose)
4021 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4022 }
4023 /* XT (x2APIC) General Interrupt Control Register. */
4024 {
4025 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4026 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4027 if (fVerbose)
4028 {
4029 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4030 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4031 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4032 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4033 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4034 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4035 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4036 }
4037 }
4038 /* XT (x2APIC) PPR Interrupt Control Register. */
4039 {
4040 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4041 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4042 if (fVerbose)
4043 {
4044 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4045 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4046 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4047 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4048 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4049 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4050 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4051 }
4052 }
4053 /* XT (X2APIC) GA Log Interrupt Control Register. */
4054 {
4055 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4056 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4057 if (fVerbose)
4058 {
4059 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4060 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4061 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4062 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4063 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4064 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4065 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4066 }
4067 }
4068 /* MARC Registers. */
4069 {
4070 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4071 {
4072 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4073 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4074 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4075
4076 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4077 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4078 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4079 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4080
4081 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4082 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4083 }
4084 }
4085 /* Reserved Register. */
4086 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4087 /* Command Buffer Head Pointer Register. */
4088 {
4089 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4090 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4091 CmdBufHeadPtr.n.off);
4092 }
4093 /* Command Buffer Tail Pointer Register. */
4094 {
4095 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4096 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4097 CmdBufTailPtr.n.off);
4098 }
4099 /* Event Log Head Pointer Register. */
4100 {
4101 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4102 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4103 EvtLogHeadPtr.n.off);
4104 }
4105 /* Event Log Tail Pointer Register. */
4106 {
4107 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4108 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4109 EvtLogTailPtr.n.off);
4110 }
4111 /* Status Register. */
4112 {
4113 IOMMU_STATUS_T const Status = pThis->Status;
4114 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4115 if (fVerbose)
4116 {
4117 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4118 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4119 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4120 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4121 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4122 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4123 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4124 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4125 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4126 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4127 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4128 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4129 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4130 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4131 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4132 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4133 }
4134 }
4135 /* PPR Log Head Pointer. */
4136 {
4137 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4138 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4139 PprLogHeadPtr.n.off);
4140 }
4141 /* PPR Log Tail Pointer. */
4142 {
4143 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4144 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4145 PprLogTailPtr.n.off);
4146 }
4147 /* Guest Virtual-APIC Log Head Pointer. */
4148 {
4149 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4150 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4151 GALogHeadPtr.n.u12GALogPtr);
4152 }
4153 /* Guest Virtual-APIC Log Tail Pointer. */
4154 {
4155 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4156 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4157 GALogTailPtr.n.u12GALogPtr);
4158 }
4159 /* PPR Log B Head Pointer. */
4160 {
4161 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4162 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4163 PprLogBHeadPtr.n.off);
4164 }
4165 /* PPR Log B Tail Pointer. */
4166 {
4167 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4168 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4169 PprLogBTailPtr.n.off);
4170 }
4171 /* Event Log B Head Pointer. */
4172 {
4173 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4174 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4175 EvtLogBHeadPtr.n.off);
4176 }
4177 /* Event Log B Tail Pointer. */
4178 {
4179 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4180 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4181 EvtLogBTailPtr.n.off);
4182 }
4183 /* PPR Log Auto Response Register. */
4184 {
4185 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4186 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4187 if (fVerbose)
4188 {
4189 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4190 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4191 }
4192 }
4193 /* PPR Log Overflow Early Warning Indicator Register. */
4194 {
4195 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4196 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4197 if (fVerbose)
4198 {
4199 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4200 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4201 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4202 }
4203 }
4204 /* PPR Log Overflow Early Warning Indicator Register. */
4205 {
4206 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4207 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4208 if (fVerbose)
4209 {
4210 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4211 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4212 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4213 }
4214 }
4215}
4216
4217
4218/**
4219 * Dumps the DTE via the info callback helper.
4220 *
4221 * @param pHlp The info helper.
4222 * @param pDte The device table entry.
4223 * @param pszPrefix The string prefix.
4224 */
4225static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4226{
4227 AssertReturnVoid(pHlp);
4228 AssertReturnVoid(pDte);
4229 AssertReturnVoid(pszPrefix);
4230
4231 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4232 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4233 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4234 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4235 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4236 pDte->n.u40PageTableRootPtrLo << 12);
4237 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4238 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4239 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4240 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4241 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4242 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4243 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4244 (pDte->n.u21GstCr3TableRootPtrHi << 31)
4245 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
4246 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
4247 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4248 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4249 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4250 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4251 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4252 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4253 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4254 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4255 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4256 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4257 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4258 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4259 pHlp->pfnPrintf(pHlp, "\n");
4260
4261 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4262 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4263 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4264 {
4265 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4266 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4267 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4268 cbIntrTable);
4269 }
4270 else
4271 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4272 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4273 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4274 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4275 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4276 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4277 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4278 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4279 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4280 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4281 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4282 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4283 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4284 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4285 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4286 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4287 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4288}
4289
4290
4291/**
4292 * @callback_method_impl{FNDBGFHANDLERDEV}
4293 */
4294static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4295{
4296 if (pszArgs)
4297 {
4298 uint16_t uDevId = 0;
4299 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4300 if (RT_SUCCESS(rc))
4301 {
4302 DTE_T Dte;
4303 rc = iommuAmdReadDte(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4304 if (RT_SUCCESS(rc))
4305 {
4306 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", uDevId);
4307 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4308 return;
4309 }
4310
4311 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4312 }
4313 else
4314 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4315 }
4316 else
4317 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4318}
4319
4320
4321#if 0
4322/**
4323 * @callback_method_impl{FNDBGFHANDLERDEV}
4324 */
4325static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4326{
4327 RT_NOREF(pszArgs);
4328
4329 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4330 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4331 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4332
4333 uint8_t cTables = 0;
4334 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4335 {
4336 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4337 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4338 if (GCPhysDevTab)
4339 ++cTables;
4340 }
4341
4342 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4343 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4344 if (!cTables)
4345 return;
4346
4347 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4348 {
4349 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4350 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4351 if (GCPhysDevTab)
4352 {
4353 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4354 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4355 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4356
4357 void *pvDevTab = RTMemAllocZ(cbDevTab);
4358 if (RT_LIKELY(pvDevTab))
4359 {
4360 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4361 if (RT_SUCCESS(rc))
4362 {
4363 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4364 {
4365 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
4366 if ( pDte->n.u1Valid
4367 || pDte->n.u1IntrMapValid)
4368 {
4369 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4370 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4371 }
4372 }
4373 pHlp->pfnPrintf(pHlp, "\n");
4374 }
4375 else
4376 {
4377 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4378 cbDevTab, rc);
4379 }
4380
4381 RTMemFree(pvDevTab);
4382 }
4383 else
4384 {
4385 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4386 return;
4387 }
4388 }
4389 }
4390}
4391#endif
4392
4393/**
4394 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4395 */
4396static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4397{
4398 /** @todo IOMMU: Save state. */
4399 RT_NOREF2(pDevIns, pSSM);
4400 LogFlowFunc(("\n"));
4401 return VERR_NOT_IMPLEMENTED;
4402}
4403
4404
4405/**
4406 * @callback_method_impl{FNSSMDEVLOADEXEC}
4407 */
4408static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4409{
4410 /** @todo IOMMU: Load state. */
4411 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4412 LogFlowFunc(("\n"));
4413 return VERR_NOT_IMPLEMENTED;
4414}
4415
4416
4417/**
4418 * @interface_method_impl{PDMDEVREG,pfnReset}
4419 */
4420static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4421{
4422 /*
4423 * Resets read-write portion of the IOMMU state.
4424 *
4425 * NOTE! State not initialized here is expected to be initialized during
4426 * device construction and remain read-only through the lifetime of the VM.
4427 */
4428 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4429 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4430 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4431
4432 IOMMU_LOCK_NORET(pDevIns);
4433
4434 LogFlowFunc(("\n"));
4435
4436 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4437
4438 pThis->CmdBufBaseAddr.u64 = 0;
4439 pThis->CmdBufBaseAddr.n.u4Len = 8;
4440
4441 pThis->EvtLogBaseAddr.u64 = 0;
4442 pThis->EvtLogBaseAddr.n.u4Len = 8;
4443
4444 pThis->Ctrl.u64 = 0;
4445 pThis->Ctrl.n.u1Coherent = 1;
4446 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4447
4448 pThis->ExclRangeBaseAddr.u64 = 0;
4449 pThis->ExclRangeLimit.u64 = 0;
4450
4451 pThis->PprLogBaseAddr.u64 = 0;
4452 pThis->PprLogBaseAddr.n.u4Len = 8;
4453
4454 pThis->HwEvtHi.u64 = 0;
4455 pThis->HwEvtLo = 0;
4456 pThis->HwEvtStatus.u64 = 0;
4457
4458 pThis->GALogBaseAddr.u64 = 0;
4459 pThis->GALogBaseAddr.n.u4Len = 8;
4460 pThis->GALogTailAddr.u64 = 0;
4461
4462 pThis->PprLogBBaseAddr.u64 = 0;
4463 pThis->PprLogBBaseAddr.n.u4Len = 8;
4464
4465 pThis->EvtLogBBaseAddr.u64 = 0;
4466 pThis->EvtLogBBaseAddr.n.u4Len = 8;
4467
4468 pThis->PerfOptCtrl.u32 = 0;
4469
4470 pThis->XtGenIntrCtrl.u64 = 0;
4471 pThis->XtPprIntrCtrl.u64 = 0;
4472 pThis->XtGALogIntrCtrl.u64 = 0;
4473
4474 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4475
4476 pThis->CmdBufHeadPtr.u64 = 0;
4477 pThis->CmdBufTailPtr.u64 = 0;
4478 pThis->EvtLogHeadPtr.u64 = 0;
4479 pThis->EvtLogTailPtr.u64 = 0;
4480
4481 pThis->Status.u64 = 0;
4482
4483 pThis->PprLogHeadPtr.u64 = 0;
4484 pThis->PprLogTailPtr.u64 = 0;
4485
4486 pThis->GALogHeadPtr.u64 = 0;
4487 pThis->GALogTailPtr.u64 = 0;
4488
4489 pThis->PprLogBHeadPtr.u64 = 0;
4490 pThis->PprLogBTailPtr.u64 = 0;
4491
4492 pThis->EvtLogBHeadPtr.u64 = 0;
4493 pThis->EvtLogBTailPtr.u64 = 0;
4494
4495 pThis->PprLogAutoResp.u64 = 0;
4496 pThis->PprLogOverflowEarly.u64 = 0;
4497 pThis->PprLogBOverflowEarly.u64 = 0;
4498
4499 pThis->IommuBar.u64 = 0;
4500 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4501 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4502
4503 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4504
4505 IOMMU_UNLOCK(pDevIns);
4506}
4507
4508
4509/**
4510 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4511 */
4512static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4513{
4514 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4515 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4516 LogFlowFunc(("\n"));
4517
4518 /* Close the command thread semaphore. */
4519 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4520 {
4521 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4522 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4523 }
4524 return VINF_SUCCESS;
4525}
4526
4527
4528/**
4529 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4530 */
4531static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4532{
4533 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4534 RT_NOREF(pCfg);
4535
4536 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4537 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4538 pThisCC->pDevInsR3 = pDevIns;
4539
4540 LogFlowFunc(("iInstance=%d\n", iInstance));
4541
4542 /*
4543 * Register the IOMMU with PDM.
4544 */
4545 PDMIOMMUREGR3 IommuReg;
4546 RT_ZERO(IommuReg);
4547 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4548 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
4549 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
4550 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4551 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4552 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4553 if (RT_FAILURE(rc))
4554 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4555 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4556 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4557 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4558 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4559 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4560 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4561 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4562 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4563
4564 /*
4565 * Initialize read-only PCI configuration space.
4566 */
4567 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4568 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4569
4570 /* Header. */
4571 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4572 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
4573 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
4574 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
4575 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4576 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4577 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
4578 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
4579 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
4580 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
4581 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
4582 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
4583 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
4584 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
4585
4586 /* Capability Header. */
4587 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
4588 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
4589 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
4590 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
4591 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
4592 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
4593 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
4594 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
4595 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
4596 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
4597 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
4598
4599 /* Base Address Register. */
4600 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
4601 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
4602
4603 /* IOMMU Range Register. */
4604 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
4605
4606 /* Misc. Information Register. */
4607 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
4608 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
4609 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
4610 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
4611 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
4612 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
4613 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
4614 uint32_t const uMiscInfoReg1 = 0;
4615 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
4616 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
4617
4618 /* MSI Capability Header register. */
4619 PDMMSIREG MsiReg;
4620 RT_ZERO(MsiReg);
4621 MsiReg.cMsiVectors = 1;
4622 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
4623 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
4624 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD spec. 2.8 "IOMMU Interrupt Support". */
4625
4626 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
4627#if 0
4628 /* MSI Address Lo. */
4629 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
4630 /* MSI Address Hi. */
4631 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
4632 /* MSI Data. */
4633 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
4634#endif
4635
4636#if 0
4637 /** @todo IOMMU: I don't know if we need to support this, enable later if
4638 * required. */
4639 /* MSI Mapping Capability Header register. */
4640 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
4641 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
4642 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
4643 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
4644 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
4645 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
4646 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
4647#endif
4648
4649 /*
4650 * Register the PCI function with PDM.
4651 */
4652 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4653 AssertLogRelRCReturn(rc, rc);
4654
4655 /*
4656 * Register MSI support for the PCI device.
4657 * This must be done -after- register it as a PCI device!
4658 */
4659 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4660 AssertRCReturn(rc, rc);
4661
4662 /*
4663 * Intercept PCI config. space accesses.
4664 */
4665 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
4666 AssertLogRelRCReturn(rc, rc);
4667
4668 /*
4669 * Create the MMIO region.
4670 * Mapping of the region is done when software configures it via PCI config space.
4671 */
4672 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
4673 NULL /* pvUser */,
4674 IOMMMIO_FLAGS_READ_DWORD_QWORD
4675 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
4676 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
4677 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
4678 "AMD-IOMMU", &pThis->hMmio);
4679 AssertLogRelRCReturn(rc, rc);
4680
4681 /*
4682 * Register saved state.
4683 */
4684 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
4685 NULL, NULL, NULL,
4686 NULL, iommuAmdR3SaveExec, NULL,
4687 NULL, iommuAmdR3LoadExec, NULL);
4688 AssertLogRelRCReturn(rc, rc);
4689
4690 /*
4691 * Register debugger info items.
4692 */
4693 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
4694 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
4695#if 0
4696 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
4697#endif
4698
4699# ifdef VBOX_WITH_STATISTICS
4700 /*
4701 * Statistics.
4702 */
4703 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4704 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4705
4706 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4707 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4708
4709 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
4710 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
4711
4712 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4713 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4714
4715 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4716 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4717
4718 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4719 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4720
4721 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4722 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4723
4724 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
4725 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
4726 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
4727 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
4728 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
4729 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
4730 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
4731 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
4732 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
4733# endif
4734
4735 /*
4736 * Create the command thread and its event semaphore.
4737 */
4738 char szDevIommu[64];
4739 RT_ZERO(szDevIommu);
4740 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
4741 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
4742 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
4743 AssertLogRelRCReturn(rc, rc);
4744
4745 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
4746 AssertLogRelRCReturn(rc, rc);
4747
4748 /*
4749 * Initialize read-only registers.
4750 * NOTE! Fields here must match their corresponding field in the ACPI tables.
4751 */
4752 /* Don't remove the commented lines below as it lets us see all features at a glance. */
4753 pThis->ExtFeat.u64 = 0;
4754 //pThis->ExtFeat.n.u1PrefetchSup = 0;
4755 //pThis->ExtFeat.n.u1PprSup = 0;
4756 //pThis->ExtFeat.n.u1X2ApicSup = 0;
4757 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
4758 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
4759 pThis->ExtFeat.n.u1InvAllSup = 1;
4760 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
4761 pThis->ExtFeat.n.u1HwErrorSup = 1;
4762 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
4763 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
4764 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
4765 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
4766 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
4767 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
4768 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
4769 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
4770 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
4771 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
4772 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
4773 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
4774 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
4775 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
4776 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
4777 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
4778 //pThis->ExtFeat.n.u2MarcSup = 0;
4779 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
4780 //pThis->ExtFeat.n.u1PerfOptSup = 0;
4781 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
4782 //pThis->ExtFeat.n.u1GstIoSup = 0;
4783 //pThis->ExtFeat.n.u1HostAccessSup = 0;
4784 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
4785 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
4786 //pThis->ExtFeat.n.u1HostDirtySup = 0;
4787 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
4788 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
4789 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
4790
4791 pThis->RsvdReg = 0;
4792
4793 pThis->DevSpecificFeat.u64 = 0;
4794 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
4795 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
4796
4797 pThis->DevSpecificCtrl.u64 = 0;
4798 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
4799 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
4800
4801 pThis->DevSpecificStatus.u64 = 0;
4802 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
4803 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
4804
4805 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
4806
4807 /*
4808 * Initialize parts of the IOMMU state as it would during reset.
4809 * Must be called -after- initializing PCI config. space registers.
4810 */
4811 iommuAmdR3Reset(pDevIns);
4812
4813 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
4814 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
4815 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
4816 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
4817 pThis->ExtFeat.u64));
4818 return VINF_SUCCESS;
4819}
4820
4821# else /* !IN_RING3 */
4822
4823/**
4824 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4825 */
4826static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
4827{
4828 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4829 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4830 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4831
4832 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4833
4834 /* Set up the MMIO RZ handlers. */
4835 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
4836 AssertRCReturn(rc, rc);
4837
4838 /* Set up the IOMMU RZ callbacks. */
4839 PDMIOMMUREGCC IommuReg;
4840 RT_ZERO(IommuReg);
4841 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4842 IommuReg.idxIommu = pThis->idxIommu;
4843 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
4844 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
4845 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4846 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4847 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4848 AssertRCReturn(rc, rc);
4849
4850 return VINF_SUCCESS;
4851}
4852
4853# endif /* !IN_RING3 */
4854
4855/**
4856 * The device registration structure.
4857 */
4858const PDMDEVREG g_DeviceIommuAmd =
4859{
4860 /* .u32Version = */ PDM_DEVREG_VERSION,
4861 /* .uReserved0 = */ 0,
4862 /* .szName = */ "iommu-amd",
4863 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4864 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4865 /* .cMaxInstances = */ ~0U,
4866 /* .uSharedVersion = */ 42,
4867 /* .cbInstanceShared = */ sizeof(IOMMU),
4868 /* .cbInstanceCC = */ sizeof(IOMMUCC),
4869 /* .cbInstanceRC = */ sizeof(IOMMURC),
4870 /* .cMaxPciDevices = */ 1,
4871 /* .cMaxMsixVectors = */ 0,
4872 /* .pszDescription = */ "IOMMU (AMD)",
4873#if defined(IN_RING3)
4874 /* .pszRCMod = */ "VBoxDDRC.rc",
4875 /* .pszR0Mod = */ "VBoxDDR0.r0",
4876 /* .pfnConstruct = */ iommuAmdR3Construct,
4877 /* .pfnDestruct = */ iommuAmdR3Destruct,
4878 /* .pfnRelocate = */ NULL,
4879 /* .pfnMemSetup = */ NULL,
4880 /* .pfnPowerOn = */ NULL,
4881 /* .pfnReset = */ iommuAmdR3Reset,
4882 /* .pfnSuspend = */ NULL,
4883 /* .pfnResume = */ NULL,
4884 /* .pfnAttach = */ NULL,
4885 /* .pfnDetach = */ NULL,
4886 /* .pfnQueryInterface = */ NULL,
4887 /* .pfnInitComplete = */ NULL,
4888 /* .pfnPowerOff = */ NULL,
4889 /* .pfnSoftReset = */ NULL,
4890 /* .pfnReserved0 = */ NULL,
4891 /* .pfnReserved1 = */ NULL,
4892 /* .pfnReserved2 = */ NULL,
4893 /* .pfnReserved3 = */ NULL,
4894 /* .pfnReserved4 = */ NULL,
4895 /* .pfnReserved5 = */ NULL,
4896 /* .pfnReserved6 = */ NULL,
4897 /* .pfnReserved7 = */ NULL,
4898#elif defined(IN_RING0)
4899 /* .pfnEarlyConstruct = */ NULL,
4900 /* .pfnConstruct = */ iommuAmdRZConstruct,
4901 /* .pfnDestruct = */ NULL,
4902 /* .pfnFinalDestruct = */ NULL,
4903 /* .pfnRequest = */ NULL,
4904 /* .pfnReserved0 = */ NULL,
4905 /* .pfnReserved1 = */ NULL,
4906 /* .pfnReserved2 = */ NULL,
4907 /* .pfnReserved3 = */ NULL,
4908 /* .pfnReserved4 = */ NULL,
4909 /* .pfnReserved5 = */ NULL,
4910 /* .pfnReserved6 = */ NULL,
4911 /* .pfnReserved7 = */ NULL,
4912#elif defined(IN_RC)
4913 /* .pfnConstruct = */ iommuAmdRZConstruct,
4914 /* .pfnReserved0 = */ NULL,
4915 /* .pfnReserved1 = */ NULL,
4916 /* .pfnReserved2 = */ NULL,
4917 /* .pfnReserved3 = */ NULL,
4918 /* .pfnReserved4 = */ NULL,
4919 /* .pfnReserved5 = */ NULL,
4920 /* .pfnReserved6 = */ NULL,
4921 /* .pfnReserved7 = */ NULL,
4922#else
4923# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4924#endif
4925 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4926};
4927
4928#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4929
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