VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 87499

Last change on this file since 87499 was 87499, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 IOTLB cache bits.
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1/* $Id: DevIommuAmd.cpp 87499 2021-02-01 13:55:23Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/string.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47/** Enable the IOTLBE cache. */
48#define IOMMU_WITH_IOTLBE_CACHE
49
50#ifdef IOMMU_WITH_IOTLBE_CACHE
51/** The maximum number of IOTLB entries. */
52# define IOMMU_IOTLBE_MAX 512
53/** The mask of bits for the domain ID of the IOTLBE key. */
54# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
55/** The number of bits to shift for the domain ID of the IOTLBE key. */
56# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
57#endif
58
59
60/*********************************************************************************************************************************
61* Structures and Typedefs *
62*********************************************************************************************************************************/
63/**
64 * Acquires the IOMMU PDM lock.
65 * This will make a long jump to ring-3 to acquire the lock if necessary.
66 */
67#define IOMMU_LOCK(a_pDevIns) \
68 do { \
69 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
70 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
71 { /* likely */ } \
72 else \
73 return rcLock; \
74 } while (0)
75
76/**
77 * Acquires the IOMMU PDM lock (asserts on failure rather than returning an error).
78 * This will make a long jump to ring-3 to acquire the lock if necessary.
79 */
80#define IOMMU_LOCK_NORET(a_pDevIns) \
81 do { \
82 int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo), VINF_SUCCESS); \
83 AssertRC(rcLock); \
84 } while (0)
85
86/**
87 * Releases the IOMMU PDM lock.
88 */
89#define IOMMU_UNLOCK(a_pDevIns) \
90 do { \
91 PDMDevHlpCritSectLeave((a_pDevIns), (a_pDevIns)->CTX_SUFF(pCritSectRo)); \
92 } while (0)
93
94/**
95 * Asserts that the critsect is owned by this thread.
96 */
97#define IOMMU_ASSERT_LOCKED(a_pDevIns) \
98 do { \
99 Assert(PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
100 } while (0)
101
102/**
103 * Asserts that the critsect is not owned by this thread.
104 */
105#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) \
106 do { \
107 Assert(!PDMDevHlpCritSectIsOwner(pDevIns, pDevIns->CTX_SUFF(pCritSectRo))); \
108 } while (0)
109
110/**
111 * IOMMU operations (transaction) types.
112 */
113typedef enum IOMMUOP
114{
115 /** Address translation request. */
116 IOMMUOP_TRANSLATE_REQ = 0,
117 /** Memory read request. */
118 IOMMUOP_MEM_READ,
119 /** Memory write request. */
120 IOMMUOP_MEM_WRITE,
121 /** Interrupt request. */
122 IOMMUOP_INTR_REQ,
123 /** Command. */
124 IOMMUOP_CMD
125} IOMMUOP;
126AssertCompileSize(IOMMUOP, 4);
127
128/**
129 * I/O page walk result.
130 */
131typedef struct IOWALKRESULT
132{
133 /** The translated system physical address. */
134 RTGCPHYS GCPhysSpa;
135 /** The number of offset bits in the system physical address. */
136 uint8_t cShift;
137 /** The I/O permissions allowed by the translation (IOMMU_IO_PERM_XXX). */
138 uint8_t fIoPerm;
139 /** Padding. */
140 uint8_t abPadding[2];
141} IOWALKRESULT;
142/** Pointer to an I/O walk result struct. */
143typedef IOWALKRESULT *PIOWALKRESULT;
144/** Pointer to a const I/O walk result struct. */
145typedef IOWALKRESULT *PCIOWALKRESULT;
146
147/**
148 * IOMMU I/O Device ID mapping.
149 */
150#pragma pack(1)
151typedef struct IODOMAIN
152{
153 /** The domain ID assigned by software. */
154 uint16_t uDomainId;
155 /** Whether the device ID is valid (if not, lookups must re-read DTE). */
156 bool fValid;
157 bool afAlignment[1];
158} IODOMAIN;
159#pragma pack()
160/** Pointer to an I/O domain struct. */
161typedef IODOMAIN *PIODOMAIN;
162/** Pointer to a const I/O domain struct. */
163typedef IODOMAIN *PCIODOMAIN;
164AssertCompileSize(IODOMAIN, 4);
165
166/**
167 * IOMMU I/O TLB Entry.
168 * Keep this as small and aligned as possible.
169 */
170typedef struct IOTLBE
171{
172 /** The AVL tree core. */
173 AVLRU64NODECORE Core;
174 /** List node for the LRU (Least Recently Used) list used for eviction. */
175 RTLISTNODE NdLru;
176 /** The I/O walk result of the translation. */
177 IOWALKRESULT WalkResult;
178} IOTLBE;
179AssertCompileSizeAlignment(IOTLBE, 8);
180/** Pointer to an IOMMU I/O TLB entry struct. */
181typedef IOTLBE *PIOTLBE;
182/** Pointer to a const IOMMU I/O TLB entry struct. */
183typedef IOTLBE const *PCIOTLBE;
184
185/**
186 * The shared IOMMU device state.
187 */
188typedef struct IOMMU
189{
190 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
191 uint32_t idxIommu;
192 /** IOMMU magic. */
193 uint32_t u32Magic;
194
195 /** Whether the command thread is sleeping. */
196 bool volatile fCmdThreadSleeping;
197 /** Alignment padding. */
198 uint8_t afPadding0[3];
199 /** Whether the command thread has been signaled for wake up. */
200 bool volatile fCmdThreadSignaled;
201 /** Alignment padding. */
202 uint8_t afPadding1[3];
203
204 /** The event semaphore the command thread waits on. */
205 SUPSEMEVENT hEvtCmdThread;
206 /** The MMIO handle. */
207 IOMMMIOHANDLE hMmio;
208
209#ifdef IOMMU_WITH_IOTLBE_CACHE
210 /** L1 Cache - Maps [DeviceId] to [DomainId]. */
211 PIODOMAIN paDomainIds;
212 /** Pointer to array of allocated IOTLBEs. */
213 PIOTLBE paIotlbes;
214 /** L2 Cache - Maps [DomainId,Iova] to [IOTLBE]. */
215 AVLRU64TREE TreeIotlbe;
216 /** LRU list anchor for IOTLB entries. */
217 RTLISTANCHOR LstLruIotlbe;
218 /** Index of the next unused IOTLB. */
219 uint32_t idxUnusedIotlbe;
220 /** Number of cached IOTLB entries in the tree. */
221 uint32_t cCachedIotlbes;
222#endif
223
224 /** @name PCI: Base capability block registers.
225 * @{ */
226 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
227 /** @} */
228
229 /** @name MMIO: Control and status registers.
230 * @{ */
231 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
232 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
233 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
234 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
235 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
236 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
237 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
238 /** @} */
239
240 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
241 * @{ */
242 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
243 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
244 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
245 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
246 /** @} */
247
248 /** @todo IOMMU: SMI filter. */
249
250 /** @name MMIO: Guest Virtual-APIC Log registers.
251 * @{ */
252 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
253 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
254 /** @} */
255
256 /** @name MMIO: Alternate PPR and Event Log registers.
257 * @{ */
258 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
259 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
260 /** @} */
261
262 /** @name MMIO: Device-specific feature registers.
263 * @{ */
264 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
265 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
266 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
267 /** @} */
268
269 /** @name MMIO: MSI Capability Block registers.
270 * @{ */
271 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
272 /** @} */
273
274 /** @name MMIO: Performance Optimization Control registers.
275 * @{ */
276 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
277 /** @} */
278
279 /** @name MMIO: x2APIC Control registers.
280 * @{ */
281 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
282 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
283 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
284 /** @} */
285
286 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
287 * @{ */
288 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
289 /** @} */
290
291 /** @name MMIO: Reserved register.
292 * @{ */
293 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
294 /** @} */
295
296 /** @name MMIO: Command and Event Log pointer registers.
297 * @{ */
298 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
299 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
300 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
301 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
302 /** @} */
303
304 /** @name MMIO: Command and Event Status register.
305 * @{ */
306 IOMMU_STATUS_T Status; /**< IOMMU status register. */
307 /** @} */
308
309 /** @name MMIO: PPR Log Head and Tail pointer registers.
310 * @{ */
311 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
312 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
313 /** @} */
314
315 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
316 * @{ */
317 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
318 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
319 /** @} */
320
321 /** @name MMIO: PPR Log B Head and Tail pointer registers.
322 * @{ */
323 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
324 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
325 /** @} */
326
327 /** @name MMIO: Event Log B Head and Tail pointer registers.
328 * @{ */
329 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
330 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
331 /** @} */
332
333 /** @name MMIO: PPR Log Overflow protection registers.
334 * @{ */
335 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
336 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
337 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
338 /** @} */
339
340 /** @todo IOMMU: IOMMU Event counter registers. */
341
342#ifdef VBOX_WITH_STATISTICS
343 /** @name IOMMU: Stat counters.
344 * @{ */
345 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
346 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
347 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
348 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
349
350 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
351 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
352
353 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
354 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
355 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
356 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
357
358 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
359 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
360 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
361 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
362
363 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
364 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
365 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
366 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
367 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
368 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
369 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
370 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
371 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
372
373 STAMCOUNTER StatDteLookupNonContig; /**< Number of non-contiguous address region translations. */
374 STAMPROFILEADV StatDteLookup; /**< Profiling of device table entry lookup (uncached). */
375 /** @} */
376#endif
377} IOMMU;
378/** Pointer to the IOMMU device state. */
379typedef struct IOMMU *PIOMMU;
380/** Pointer to the const IOMMU device state. */
381typedef const struct IOMMU *PCIOMMU;
382AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
383AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
384AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
385AssertCompileMemberAlignment(IOMMU, hMmio, 8);
386#ifdef IOMMU_WITH_IOTLBE_CACHE
387AssertCompileMemberAlignment(IOMMU, paDomainIds, 8);
388AssertCompileMemberAlignment(IOMMU, paIotlbes, 8);
389AssertCompileMemberAlignment(IOMMU, TreeIotlbe, 8);
390AssertCompileMemberAlignment(IOMMU, LstLruIotlbe, 8);
391#endif
392AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
393AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
394AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
395AssertCompileMemberAlignment(IOMMU, Status, 8);
396
397/**
398 * The ring-3 IOMMU device state.
399 */
400typedef struct IOMMUR3
401{
402 /** Device instance. */
403 PPDMDEVINSR3 pDevInsR3;
404 /** The IOMMU helpers. */
405 PCPDMIOMMUHLPR3 pIommuHlpR3;
406 /** The command thread handle. */
407 R3PTRTYPE(PPDMTHREAD) pCmdThread;
408} IOMMUR3;
409/** Pointer to the ring-3 IOMMU device state. */
410typedef IOMMUR3 *PIOMMUR3;
411
412/**
413 * The ring-0 IOMMU device state.
414 */
415typedef struct IOMMUR0
416{
417 /** Device instance. */
418 PPDMDEVINSR0 pDevInsR0;
419 /** The IOMMU helpers. */
420 PCPDMIOMMUHLPR0 pIommuHlpR0;
421} IOMMUR0;
422/** Pointer to the ring-0 IOMMU device state. */
423typedef IOMMUR0 *PIOMMUR0;
424
425/**
426 * The raw-mode IOMMU device state.
427 */
428typedef struct IOMMURC
429{
430 /** Device instance. */
431 PPDMDEVINSR0 pDevInsRC;
432 /** The IOMMU helpers. */
433 PCPDMIOMMUHLPRC pIommuHlpRC;
434} IOMMURC;
435/** Pointer to the raw-mode IOMMU device state. */
436typedef IOMMURC *PIOMMURC;
437
438/** The IOMMU device state for the current context. */
439typedef CTX_SUFF(IOMMU) IOMMUCC;
440/** Pointer to the IOMMU device state for the current context. */
441typedef CTX_SUFF(PIOMMU) PIOMMUCC;
442
443/**
444 * IOMMU register access.
445 */
446typedef struct IOMMUREGACC
447{
448 const char *pszName;
449 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
450 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
451} IOMMUREGACC;
452/** Pointer to an IOMMU register access. */
453typedef IOMMUREGACC *PIOMMUREGACC;
454/** Pointer to a const IOMMU register access. */
455typedef IOMMUREGACC const *PCIOMMUREGACC;
456
457
458/*********************************************************************************************************************************
459* Global Variables *
460*********************************************************************************************************************************/
461/**
462 * An array of the number of device table segments supported.
463 * Indexed by u2DevTabSegSup.
464 */
465static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
466
467/**
468 * An array of the masks to select the device table segment index from a device ID.
469 */
470static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
471
472/**
473 * An array of the shift values to select the device table segment index from a
474 * device ID.
475 */
476static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
477
478/**
479 * The maximum size (inclusive) of each device table segment (0 to 7).
480 * Indexed by the device table segment index.
481 */
482static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
483
484
485#ifndef VBOX_DEVICE_STRUCT_TESTCASE
486/**
487 * Gets the maximum number of buffer entries for the given buffer length.
488 *
489 * @returns Number of buffer entries.
490 * @param uEncodedLen The length (power-of-2 encoded).
491 */
492DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
493{
494 Assert(uEncodedLen > 7);
495 Assert(uEncodedLen < 16);
496 return 2 << (uEncodedLen - 1);
497}
498
499
500/**
501 * Gets the total length of the buffer given a base register's encoded length.
502 *
503 * @returns The length of the buffer in bytes.
504 * @param uEncodedLen The length (power-of-2 encoded).
505 */
506DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
507{
508 Assert(uEncodedLen > 7);
509 Assert(uEncodedLen < 16);
510 return (2 << (uEncodedLen - 1)) << 4;
511}
512
513
514/**
515 * Gets the number of (unconsumed) entries in the event log.
516 *
517 * @returns The number of entries in the event log.
518 * @param pThis The IOMMU device state.
519 */
520static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
521{
522 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
523 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
524 if (idxTail >= idxHead)
525 return idxTail - idxHead;
526
527 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
528 return cMaxEvts - idxHead + idxTail;
529}
530
531
532#if 0
533/**
534 * Gets the number of (unconsumed) commands in the command buffer.
535 *
536 * @returns The number of commands in the command buffer.
537 * @param pThis The IOMMU device state.
538 */
539static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
540{
541 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
542 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
543 if (idxTail >= idxHead)
544 return idxTail - idxHead;
545
546 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
547 return cMaxCmds - idxHead + idxTail;
548}
549#endif
550
551
552#ifdef IOMMU_WITH_IOTLBE_CACHE
553/**
554 * @callback_method_impl{AVLRU64CALLBACK}
555 */
556static DECLCALLBACK(int) iommuAmdDestroyIotlbe(PAVLRU64NODECORE pCore, void *pvUser)
557{
558 RT_NOREF2(pCore, pvUser);
559 /* Nothing to do here as we will destroy IOTLB entries wholesale later when required. */
560 return VINF_SUCCESS;
561}
562
563
564/**
565 * Constructs the key for an IOTLB entry suitable for using as part of the IOTLB
566 * cache.
567 *
568 * @returns The key for an IOTLB entry.
569 * @param uDomainId The domain ID.
570 * @param uIova The I/O virtual address.
571 */
572DECL_FORCE_INLINE(uint64_t) iommuAmdIotlbConstructKey(uint16_t uDomainId, uint64_t uIova)
573{
574 /*
575 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
576 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
577 * so bottom 12 bits are free.
578 *
579 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
580 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
581 */
582 uIova &= IOMMU_IOTLB_DOMAIN_ID_MASK;
583 uIova >>= X86_PAGE_4K_SHIFT;
584 return ((uint64_t)uDomainId << IOMMU_IOTLB_DOMAIN_ID_SHIFT) | uIova;
585}
586
587
588/**
589 * Deconstructs the key of an IOTLB entry into the domain ID and IOVA.
590 *
591 * @param uKey The key for the IOTLB entry.
592 * @param puDomainId Where to store the domain ID.
593 * @param puIova Where to store the I/O virtual address.
594 */
595DECL_FORCE_INLINE(void) iommuAmdIotlbDeconstructKey(uint64_t uKey, uint16_t *puDomainId, uint64_t *puIova)
596{
597 *puDomainId = (uKey & IOMMU_IOTLB_DOMAIN_ID_MASK) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT;
598 *puIova = (uKey & ~IOMMU_IOTLB_DOMAIN_ID_MASK) << X86_PAGE_4K_SHIFT;
599}
600
601
602/**
603 * Looks up an IOTLB entry from the IOTLB cache.
604 *
605 * @returns Pointer to the I/O walk result or NULL if the entry is not found.
606 * @param pThis The IOMMU device state.
607 * @param uDomainId The domain ID.
608 * @param uIova The I/O virtual address.
609 */
610static PIOWALKRESULT iommuAmdIotlbLookup(PIOMMU pThis, uint64_t uDomainId, uint64_t uIova)
611{
612 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
613
614 uint64_t const uKey = iommuAmdIotlbConstructKey(uDomainId, uIova);
615 PIOTLBE pIotlbe = (PIOTLBE)RTAvlrU64RangeGet(&pThis->TreeIotlbe, uKey);
616 if (pIotlbe)
617 {
618 /* Mark the entry as the most recently used one. */
619 RTListNodeRemove(&pIotlbe->NdLru);
620 RTListAppend(&pThis->LstLruIotlbe, &pIotlbe->NdLru);
621 return &pIotlbe->WalkResult;
622 }
623 return NULL;
624}
625
626
627/**
628 * Adds an IOTLB entry corresponding to the given I/O page walk result.
629 *
630 * @param pThis The IOMMU device state.
631 * @param uDomainId The domain ID.
632 * @param uIova The I/O virtual address being accessed.
633 * @param pWalkResult The I/O page walk result of the access.
634 */
635static void iommuAmdIotlbAdd(PIOMMU pThis, uint16_t uDomainId, uint64_t uIova, PCIOWALKRESULT pWalkResult)
636{
637 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
638 Assert(pWalkResult);
639 Assert(pWalkResult->cShift < 63);
640 Assert(pWalkResult->fIoPerm != IOMMU_IO_PERM_NONE);
641
642 /*
643 * If the cache is full, evict the last recently used entry.
644 * Otherwise, get a new IOTLB entry from the pre-allocated list.
645 */
646 PIOTLBE pIotlbe;
647 if (pThis->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
648 {
649 pIotlbe = RTListRemoveFirst(&pThis->LstLruIotlbe, IOTLBE, NdLru);
650 Assert(pIotlbe);
651 RTAvlrU64Remove(&pThis->TreeIotlbe, pIotlbe->Core.Key);
652 Assert(pThis->cCachedIotlbes > 0);
653 --pThis->cCachedIotlbes;
654 }
655 else
656 {
657 pIotlbe = &pThis->paIotlbes[pThis->idxUnusedIotlbe];
658 ++pThis->idxUnusedIotlbe;
659 }
660
661 /* Zero out IOTLB entry before reuse. */
662 Assert(pIotlbe);
663 RT_ZERO(*pIotlbe);
664
665 /* Update the entry with the result of the page walk. */
666 pIotlbe->Core.Key = iommuAmdIotlbConstructKey(uDomainId, uIova);
667 pIotlbe->Core.KeyLast = iommuAmdIotlbConstructKey(uDomainId, uIova + RT_BIT_64(pWalkResult->cShift) - 1);
668 pIotlbe->WalkResult = *pWalkResult;
669
670 /* Add the entry to the cache. */
671 RTAvlrU64Insert(&pThis->TreeIotlbe, &pIotlbe->Core);
672 ++pThis->cCachedIotlbes;
673
674 /* Mark the entry as the most recently used one. */
675 RTListAppend(&pThis->LstLruIotlbe, &pIotlbe->NdLru);
676}
677
678
679/**
680 * Removes all IOTLB entries from the cache.
681 *
682 * @param pThis The IOMMU device state.
683 */
684static void iommuAmdIotlbRemoveAll(PIOMMU pThis)
685{
686 RTListInit(&pThis->LstLruIotlbe);
687 RTAvlrU64Destroy(&pThis->TreeIotlbe, iommuAmdDestroyIotlbe, NULL /* pvParam */);
688 pThis->cCachedIotlbes = 0;
689 pThis->idxUnusedIotlbe = 0;
690 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
691 RT_BZERO(pThis->paIotlbes, cbIotlbes);
692}
693
694
695/**
696 * Removes a set of IOTLB entries from the cache given the domain ID, I/O virtual
697 * address and size.
698 *
699 * @param pThis The IOMMU device state.
700 * @param uDomainId The domain ID.
701 * @param uIova The I/O virtual address.
702 * @param cShift The number of bits to shift to get the size of the range
703 * being removed.
704 */
705static void iommuAmdIotlbRemoveRange(PIOMMU pThis, uint16_t uDomainId, uint64_t uIova, uint8_t cShift)
706{
707 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
708
709 /*
710 * Validate invalidation size.
711 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
712 */
713 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
714 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
715 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
716 {
717 /*
718 * We remove all ranges (in our tree) containing the range of I/O virtual addresses requesting
719 * to be invalidated. E.g., if the guest is using 1M pages but requests to invalidate only 8K
720 * we must invalidate the entire 1M page. On the other hand, we must handle cross-boundary
721 * requests that spans multiple pages. E.g., if the guest is using 4K pages but requests to
722 * invalid 8K, we would need to invalid two 4K pages.
723 */
724 uint64_t const uIovaLast = uIova + RT_BIT_64(cShift) - 1;
725 for (;;)
726 {
727 uint64_t const uKey = iommuAmdIotlbConstructKey(uDomainId, uIova);
728 PIOTLBE pIotlbe = (PIOTLBE)RTAvlrU64RangeRemove(&pThis->TreeIotlbe, uKey);
729 if (pIotlbe)
730 {
731 --pThis->cCachedIotlbes;
732 uint64_t const uRangeIovaLast = pIotlbe->Core.KeyLast;
733 RTListNodeRemove(&pIotlbe->NdLru);
734 RTListPrepend(&pThis->LstLruIotlbe, &pIotlbe->NdLru);
735 RT_ZERO(*pIotlbe);
736 if (uIovaLast > uRangeIovaLast)
737 uIova = uRangeIovaLast + 1;
738 else
739 break;
740 }
741 else
742 break;
743 }
744 }
745 else
746 {
747 /*
748 * The guest provided size is either invalid or exceeds the largest, meaningful page size.
749 * In such situations, we flush the entire cache.
750 */
751 iommuAmdIotlbRemoveAll(pThis);
752 }
753}
754#endif /* IOMMU_WITH_IOTLBE_CACHE */
755
756
757DECL_FORCE_INLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
758{
759 IOMMU_STATUS_T Status;
760 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
761 return Status;
762}
763
764
765DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
766{
767 IOMMU_CTRL_T Ctrl;
768 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
769 return Ctrl;
770}
771
772
773/**
774 * Returns whether MSI is enabled for the IOMMU.
775 *
776 * @returns Whether MSI is enabled.
777 * @param pDevIns The IOMMU device instance.
778 *
779 * @note There should be a PCIDevXxx function for this.
780 */
781static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
782{
783 MSI_CAP_HDR_T MsiCapHdr;
784 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
785 return MsiCapHdr.n.u1MsiEnable;
786}
787
788
789/**
790 * Signals a PCI target abort.
791 *
792 * @param pDevIns The IOMMU device instance.
793 */
794static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
795{
796 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
797 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
798 PDMPciDevSetStatus(pPciDev, u16Status);
799}
800
801
802/**
803 * Wakes up the command thread if there are commands to be processed or if
804 * processing is requested to be stopped by software.
805 *
806 * @param pDevIns The IOMMU device instance.
807 */
808static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
809{
810 IOMMU_ASSERT_LOCKED(pDevIns);
811 Log4Func(("\n"));
812
813 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
814 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
815 if (Status.n.u1CmdBufRunning)
816 {
817 Log4Func(("Signaling command thread\n"));
818 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
819 }
820}
821
822
823/**
824 * Reads the Device Table Base Address Register.
825 */
826static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
827{
828 RT_NOREF(pDevIns, offReg);
829 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
830 return VINF_SUCCESS;
831}
832
833
834/**
835 * Reads the Command Buffer Base Address Register.
836 */
837static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
838{
839 RT_NOREF(pDevIns, offReg);
840 *pu64Value = pThis->CmdBufBaseAddr.u64;
841 return VINF_SUCCESS;
842}
843
844
845/**
846 * Reads the Event Log Base Address Register.
847 */
848static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
849{
850 RT_NOREF(pDevIns, offReg);
851 *pu64Value = pThis->EvtLogBaseAddr.u64;
852 return VINF_SUCCESS;
853}
854
855
856/**
857 * Reads the Control Register.
858 */
859static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
860{
861 RT_NOREF(pDevIns, offReg);
862 *pu64Value = pThis->Ctrl.u64;
863 return VINF_SUCCESS;
864}
865
866
867/**
868 * Reads the Exclusion Range Base Address Register.
869 */
870static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
871{
872 RT_NOREF(pDevIns, offReg);
873 *pu64Value = pThis->ExclRangeBaseAddr.u64;
874 return VINF_SUCCESS;
875}
876
877
878/**
879 * Reads to the Exclusion Range Limit Register.
880 */
881static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
882{
883 RT_NOREF(pDevIns, offReg);
884 *pu64Value = pThis->ExclRangeLimit.u64;
885 return VINF_SUCCESS;
886}
887
888
889/**
890 * Reads to the Extended Feature Register.
891 */
892static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
893{
894 RT_NOREF(pDevIns, offReg);
895 *pu64Value = pThis->ExtFeat.u64;
896 return VINF_SUCCESS;
897}
898
899
900/**
901 * Reads to the PPR Log Base Address Register.
902 */
903static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
904{
905 RT_NOREF(pDevIns, offReg);
906 *pu64Value = pThis->PprLogBaseAddr.u64;
907 return VINF_SUCCESS;
908}
909
910
911/**
912 * Writes the Hardware Event Register (Hi).
913 */
914static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
915{
916 RT_NOREF(pDevIns, offReg);
917 *pu64Value = pThis->HwEvtHi.u64;
918 return VINF_SUCCESS;
919}
920
921
922/**
923 * Reads the Hardware Event Register (Lo).
924 */
925static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
926{
927 RT_NOREF(pDevIns, offReg);
928 *pu64Value = pThis->HwEvtLo;
929 return VINF_SUCCESS;
930}
931
932
933/**
934 * Reads the Hardware Event Status Register.
935 */
936static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
937{
938 RT_NOREF(pDevIns, offReg);
939 *pu64Value = pThis->HwEvtStatus.u64;
940 return VINF_SUCCESS;
941}
942
943
944/**
945 * Reads to the GA Log Base Address Register.
946 */
947static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
948{
949 RT_NOREF(pDevIns, offReg);
950 *pu64Value = pThis->GALogBaseAddr.u64;
951 return VINF_SUCCESS;
952}
953
954
955/**
956 * Reads to the PPR Log B Base Address Register.
957 */
958static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
959{
960 RT_NOREF(pDevIns, offReg);
961 *pu64Value = pThis->PprLogBBaseAddr.u64;
962 return VINF_SUCCESS;
963}
964
965
966/**
967 * Reads to the Event Log B Base Address Register.
968 */
969static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
970{
971 RT_NOREF(pDevIns, offReg);
972 *pu64Value = pThis->EvtLogBBaseAddr.u64;
973 return VINF_SUCCESS;
974}
975
976
977/**
978 * Reads the Device Table Segment Base Address Register.
979 */
980static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
981{
982 RT_NOREF(pDevIns);
983
984 /* Figure out which segment is being written. */
985 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
986 uint8_t const idxSegment = offSegment + 1;
987 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
988
989 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
990 return VINF_SUCCESS;
991}
992
993
994/**
995 * Reads the Device Specific Feature Extension (DSFX) Register.
996 */
997static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
998{
999 RT_NOREF(pDevIns, offReg);
1000 *pu64Value = pThis->DevSpecificFeat.u64;
1001 return VINF_SUCCESS;
1002}
1003
1004/**
1005 * Reads the Device Specific Control Extension (DSCX) Register.
1006 */
1007static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1008{
1009 RT_NOREF(pDevIns, offReg);
1010 *pu64Value = pThis->DevSpecificCtrl.u64;
1011 return VINF_SUCCESS;
1012}
1013
1014
1015/**
1016 * Reads the Device Specific Status Extension (DSSX) Register.
1017 */
1018static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1019{
1020 RT_NOREF(pDevIns, offReg);
1021 *pu64Value = pThis->DevSpecificStatus.u64;
1022 return VINF_SUCCESS;
1023}
1024
1025
1026/**
1027 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1028 */
1029static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1030{
1031 RT_NOREF(pDevIns, offReg);
1032 uint32_t const uLo = pThis->MiscInfo.au32[0];
1033 uint32_t const uHi = pThis->MiscInfo.au32[1];
1034 *pu64Value = RT_MAKE_U64(uLo, uHi);
1035 return VINF_SUCCESS;
1036}
1037
1038
1039/**
1040 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1041 * Register (32-bit).
1042 */
1043static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1044{
1045 RT_NOREF(pThis, offReg);
1046 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1047 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1048 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1049 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1050 *pu64Value = RT_MAKE_U64(uLo, uHi);
1051 return VINF_SUCCESS;
1052}
1053
1054
1055/**
1056 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1057 */
1058static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1059{
1060 RT_NOREF(pThis, offReg);
1061 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1062 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1063 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1064 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1065 *pu64Value = RT_MAKE_U64(uLo, uHi);
1066 return VINF_SUCCESS;
1067}
1068
1069
1070/**
1071 * Reads the Command Buffer Head Pointer Register.
1072 */
1073static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1074{
1075 RT_NOREF(pDevIns, offReg);
1076 *pu64Value = pThis->CmdBufHeadPtr.u64;
1077 return VINF_SUCCESS;
1078}
1079
1080
1081/**
1082 * Reads the Command Buffer Tail Pointer Register.
1083 */
1084static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1085{
1086 RT_NOREF(pDevIns, offReg);
1087 *pu64Value = pThis->CmdBufTailPtr.u64;
1088 return VINF_SUCCESS;
1089}
1090
1091
1092/**
1093 * Reads the Event Log Head Pointer Register.
1094 */
1095static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1096{
1097 RT_NOREF(pDevIns, offReg);
1098 *pu64Value = pThis->EvtLogHeadPtr.u64;
1099 return VINF_SUCCESS;
1100}
1101
1102
1103/**
1104 * Reads the Event Log Tail Pointer Register.
1105 */
1106static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1107{
1108 RT_NOREF(pDevIns, offReg);
1109 *pu64Value = pThis->EvtLogTailPtr.u64;
1110 return VINF_SUCCESS;
1111}
1112
1113
1114/**
1115 * Reads the Status Register.
1116 */
1117static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1118{
1119 RT_NOREF(pDevIns, offReg);
1120 *pu64Value = pThis->Status.u64;
1121 return VINF_SUCCESS;
1122}
1123
1124
1125/**
1126 * Writes the Device Table Base Address Register.
1127 */
1128static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1129{
1130 RT_NOREF(pDevIns, offReg);
1131
1132 /* Mask out all unrecognized bits. */
1133 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
1134
1135 /* Update the register. */
1136 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
1137
1138 /* Paranoia. */
1139 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
1140 return VINF_SUCCESS;
1141}
1142
1143
1144/**
1145 * Writes the Command Buffer Base Address Register.
1146 */
1147static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1148{
1149 RT_NOREF(pDevIns, offReg);
1150
1151 /*
1152 * While this is not explicitly specified like the event log base address register,
1153 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
1154 * Inconsistent specs :/
1155 */
1156 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1157 if (Status.n.u1CmdBufRunning)
1158 {
1159 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1160 return VINF_SUCCESS;
1161 }
1162
1163 /* Mask out all unrecognized bits. */
1164 CMD_BUF_BAR_T CmdBufBaseAddr;
1165 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
1166
1167 /* Validate the length. */
1168 if (CmdBufBaseAddr.n.u4Len >= 8)
1169 {
1170 /* Update the register. */
1171 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
1172
1173 /*
1174 * Writing the command buffer base address, clears the command buffer head and tail pointers.
1175 * See AMD IOMMU spec. 2.4 "Commands".
1176 */
1177 pThis->CmdBufHeadPtr.u64 = 0;
1178 pThis->CmdBufTailPtr.u64 = 0;
1179 }
1180 else
1181 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
1182
1183 return VINF_SUCCESS;
1184}
1185
1186
1187/**
1188 * Writes the Event Log Base Address Register.
1189 */
1190static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1191{
1192 RT_NOREF(pDevIns, offReg);
1193
1194 /*
1195 * IOMMU behavior is undefined when software writes this register when event logging is running.
1196 * In our emulation, we ignore the write entirely.
1197 * See AMD IOMMU spec. "Event Log Base Address Register".
1198 */
1199 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1200 if (Status.n.u1EvtLogRunning)
1201 {
1202 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
1203 return VINF_SUCCESS;
1204 }
1205
1206 /* Mask out all unrecognized bits. */
1207 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
1208 EVT_LOG_BAR_T EvtLogBaseAddr;
1209 EvtLogBaseAddr.u64 = u64Value;
1210
1211 /* Validate the length. */
1212 if (EvtLogBaseAddr.n.u4Len >= 8)
1213 {
1214 /* Update the register. */
1215 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
1216
1217 /*
1218 * Writing the event log base address, clears the event log head and tail pointers.
1219 * See AMD IOMMU spec. 2.5 "Event Logging".
1220 */
1221 pThis->EvtLogHeadPtr.u64 = 0;
1222 pThis->EvtLogTailPtr.u64 = 0;
1223 }
1224 else
1225 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
1226
1227 return VINF_SUCCESS;
1228}
1229
1230
1231/**
1232 * Writes the Control Register.
1233 */
1234static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1235{
1236 RT_NOREF(pDevIns, offReg);
1237
1238 /* Mask out all unrecognized bits. */
1239 u64Value &= IOMMU_CTRL_VALID_MASK;
1240 IOMMU_CTRL_T NewCtrl;
1241 NewCtrl.u64 = u64Value;
1242
1243 /* Ensure the device table segments are within limits. */
1244 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
1245 {
1246 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
1247
1248 /* Update the register. */
1249 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
1250
1251 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
1252 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
1253
1254 /* Enable or disable event logging when the bit transitions. */
1255 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
1256 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1257 if ( fOldEvtLogEn != fNewEvtLogEn
1258 || fOldIommuEn != fNewIommuEn)
1259 {
1260 if ( fNewIommuEn
1261 && fNewEvtLogEn)
1262 {
1263 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1264 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1265 }
1266 else
1267 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1268 }
1269
1270 /* Enable or disable command buffer processing when the bit transitions. */
1271 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1272 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1273 if ( fOldCmdBufEn != fNewCmdBufEn
1274 || fOldIommuEn != fNewIommuEn)
1275 {
1276 if ( fNewCmdBufEn
1277 && fNewIommuEn)
1278 {
1279 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1280 LogFunc(("Command buffer enabled\n"));
1281
1282 /* Wake up the command thread to start processing commands. */
1283 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1284 }
1285 else
1286 {
1287 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1288 LogFunc(("Command buffer disabled\n"));
1289 }
1290 }
1291 }
1292 else
1293 {
1294 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1295 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1296 }
1297
1298 return VINF_SUCCESS;
1299}
1300
1301
1302/**
1303 * Writes to the Exclusion Range Base Address Register.
1304 */
1305static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1306{
1307 RT_NOREF(pDevIns, offReg);
1308 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1309 return VINF_SUCCESS;
1310}
1311
1312
1313/**
1314 * Writes to the Exclusion Range Limit Register.
1315 */
1316static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1317{
1318 RT_NOREF(pDevIns, offReg);
1319 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1320 u64Value |= UINT64_C(0xfff);
1321 pThis->ExclRangeLimit.u64 = u64Value;
1322 return VINF_SUCCESS;
1323}
1324
1325
1326/**
1327 * Writes the Hardware Event Register (Hi).
1328 */
1329static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1330{
1331 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1332 RT_NOREF(pDevIns, offReg);
1333 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1334 pThis->HwEvtHi.u64 = u64Value;
1335 return VINF_SUCCESS;
1336}
1337
1338
1339/**
1340 * Writes the Hardware Event Register (Lo).
1341 */
1342static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1343{
1344 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1345 RT_NOREF(pDevIns, offReg);
1346 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1347 pThis->HwEvtLo = u64Value;
1348 return VINF_SUCCESS;
1349}
1350
1351
1352/**
1353 * Writes the Hardware Event Status Register.
1354 */
1355static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1356{
1357 RT_NOREF(pDevIns, offReg);
1358
1359 /* Mask out all unrecognized bits. */
1360 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1361
1362 /*
1363 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1364 * If the current status bits or the bits being written are both 0, we've nothing to do.
1365 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1366 */
1367 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1368 if (!(HwStatus & RT_BIT(0)))
1369 return VINF_SUCCESS;
1370 if (u64Value & HwStatus & RT_BIT_64(0))
1371 HwStatus &= ~RT_BIT_64(0);
1372 if (u64Value & HwStatus & RT_BIT_64(1))
1373 HwStatus &= ~RT_BIT_64(1);
1374
1375 /* Update the register. */
1376 pThis->HwEvtStatus.u64 = HwStatus;
1377 return VINF_SUCCESS;
1378}
1379
1380
1381/**
1382 * Writes the Device Table Segment Base Address Register.
1383 */
1384static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1385{
1386 RT_NOREF(pDevIns);
1387
1388 /* Figure out which segment is being written. */
1389 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1390 uint8_t const idxSegment = offSegment + 1;
1391 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1392
1393 /* Mask out all unrecognized bits. */
1394 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1395 DEV_TAB_BAR_T DevTabSegBar;
1396 DevTabSegBar.u64 = u64Value;
1397
1398 /* Validate the size. */
1399 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1400 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1401 if (uSegSize <= uMaxSegSize)
1402 {
1403 /* Update the register. */
1404 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1405 }
1406 else
1407 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1408
1409 return VINF_SUCCESS;
1410}
1411
1412
1413/**
1414 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1415 */
1416static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1417{
1418 RT_NOREF(pDevIns, offReg);
1419
1420 /* MSI Vector Register 0 is read-only. */
1421 /* MSI Vector Register 1. */
1422 uint32_t const uReg = u64Value >> 32;
1423 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
1424 return VINF_SUCCESS;
1425}
1426
1427
1428/**
1429 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1430 * Register (32-bit).
1431 */
1432static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1433{
1434 RT_NOREF(pThis, offReg);
1435 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1436 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1437
1438 /* MSI capability header. */
1439 {
1440 uint32_t const uReg = u64Value;
1441 MSI_CAP_HDR_T MsiCapHdr;
1442 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1443 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1444 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1445 }
1446
1447 /* MSI Address Lo. */
1448 {
1449 uint32_t const uReg = u64Value >> 32;
1450 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
1451 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1452 }
1453
1454 return VINF_SUCCESS;
1455}
1456
1457
1458/**
1459 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1460 */
1461static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1462{
1463 RT_NOREF(pThis, offReg);
1464 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1465 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1466
1467 /* MSI Address Hi. */
1468 {
1469 uint32_t const uReg = u64Value;
1470 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
1471 }
1472
1473 /* MSI Data. */
1474 {
1475 uint32_t const uReg = u64Value >> 32;
1476 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
1477 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1478 }
1479
1480 return VINF_SUCCESS;
1481}
1482
1483
1484/**
1485 * Writes the Command Buffer Head Pointer Register.
1486 */
1487static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1488{
1489 RT_NOREF(pDevIns, offReg);
1490
1491 /*
1492 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1493 * In our emulation, we ignore the write entirely.
1494 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1495 */
1496 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1497 if (Status.n.u1CmdBufRunning)
1498 {
1499 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1500 return VINF_SUCCESS;
1501 }
1502
1503 /*
1504 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1505 * In our emulation, we ignore the write entirely.
1506 */
1507 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1508 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1509 Assert(cbBuf <= _512K);
1510 if (offBuf >= cbBuf)
1511 {
1512 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1513 return VINF_SUCCESS;
1514 }
1515
1516 /* Update the register. */
1517 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1518
1519 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1520
1521 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1522 return VINF_SUCCESS;
1523}
1524
1525
1526/**
1527 * Writes the Command Buffer Tail Pointer Register.
1528 */
1529static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1530{
1531 RT_NOREF(pDevIns, offReg);
1532
1533 /*
1534 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1535 * In our emulation, we ignore the write entirely.
1536 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1537 */
1538 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
1539 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1540 Assert(cbBuf <= _512K);
1541 if (offBuf >= cbBuf)
1542 {
1543 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1544 return VINF_SUCCESS;
1545 }
1546
1547 /*
1548 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
1549 * head pointer after adding one or more commands to the buffer.
1550 *
1551 * However, we cannot enforce this strictly because it's legal for software to shrink the
1552 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
1553 * at 0). Software might even make the queue empty by making head and tail equal which is
1554 * allowed. I don't think we can or should try too hard to prevent software shooting itself
1555 * in the foot here. As long as we make sure the offset value is within the circular buffer
1556 * bounds (which we do by masking bits above) it should be sufficient.
1557 */
1558 pThis->CmdBufTailPtr.au32[0] = offBuf;
1559
1560 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1561
1562 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
1563 return VINF_SUCCESS;
1564}
1565
1566
1567/**
1568 * Writes the Event Log Head Pointer Register.
1569 */
1570static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1571{
1572 RT_NOREF(pDevIns, offReg);
1573
1574 /*
1575 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1576 * In our emulation, we ignore the write entirely.
1577 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1578 */
1579 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
1580 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1581 Assert(cbBuf <= _512K);
1582 if (offBuf >= cbBuf)
1583 {
1584 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1585 return VINF_SUCCESS;
1586 }
1587
1588 /* Update the register. */
1589 pThis->EvtLogHeadPtr.au32[0] = offBuf;
1590
1591 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
1592 return VINF_SUCCESS;
1593}
1594
1595
1596/**
1597 * Writes the Event Log Tail Pointer Register.
1598 */
1599static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1600{
1601 RT_NOREF(pDevIns, offReg);
1602 NOREF(pThis);
1603
1604 /*
1605 * IOMMU behavior is undefined when software writes this register when the event log is running.
1606 * In our emulation, we ignore the write entirely.
1607 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1608 */
1609 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1610 if (Status.n.u1EvtLogRunning)
1611 {
1612 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
1613 return VINF_SUCCESS;
1614 }
1615
1616 /*
1617 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1618 * In our emulation, we ignore the write entirely.
1619 */
1620 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
1621 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
1622 Assert(cbBuf <= _512K);
1623 if (offBuf >= cbBuf)
1624 {
1625 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
1626 return VINF_SUCCESS;
1627 }
1628
1629 /* Update the register. */
1630 pThis->EvtLogTailPtr.au32[0] = offBuf;
1631
1632 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
1633 return VINF_SUCCESS;
1634}
1635
1636
1637/**
1638 * Writes the Status Register.
1639 */
1640static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1641{
1642 RT_NOREF(pDevIns, offReg);
1643
1644 /* Mask out all unrecognized bits. */
1645 u64Value &= IOMMU_STATUS_VALID_MASK;
1646
1647 /*
1648 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
1649 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
1650 */
1651 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
1652 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
1653 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
1654 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
1655
1656 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
1657
1658 /* Update the register. */
1659 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
1660 return VINF_SUCCESS;
1661}
1662
1663
1664/**
1665 * Register access table 0.
1666 * The MMIO offset of each entry must be a multiple of 8!
1667 */
1668static const IOMMUREGACC g_aRegAccess0[] =
1669{
1670 /* MMIO off. Register name Read function Write function */
1671 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
1672 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
1673 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
1674 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
1675 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
1676 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
1677 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
1678 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
1679 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
1680 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
1681 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
1682 { /* 0x58 */ NULL, NULL, NULL },
1683
1684 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
1685 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
1686 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
1687 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
1688 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
1689 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
1690 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
1691 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
1692 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
1693 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
1694 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
1695 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
1696 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
1697 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
1698 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
1699 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
1700
1701 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
1702 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
1703 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
1704 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
1705
1706 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1707 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1708 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1709 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1710 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1711 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1712 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
1713
1714 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
1715 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
1716 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
1717
1718 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
1719 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
1720 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
1721 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
1722
1723 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
1724 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
1725 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
1726};
1727AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
1728
1729/**
1730 * Register access table 1.
1731 * The MMIO offset of each entry must be a multiple of 8!
1732 */
1733static const IOMMUREGACC g_aRegAccess1[] =
1734{
1735 /* MMIO offset Register name Read function Write function */
1736 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
1737 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
1738 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
1739 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
1740 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
1741 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
1742 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
1743 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
1744 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
1745 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
1746 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
1747 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
1748};
1749AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
1750
1751/**
1752 * Register access table 2.
1753 * The MMIO offset of each entry must be a multiple of 8!
1754 */
1755static const IOMMUREGACC g_aRegAccess2[] =
1756{
1757 /* MMIO offset Register name Read Function Write function */
1758 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
1759
1760 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
1761 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
1762 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
1763 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
1764
1765 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
1766 { /* 0x2028 */ NULL, NULL, NULL },
1767
1768 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
1769 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
1770
1771 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
1772 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
1773
1774 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
1775 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
1776
1777 { /* 0x2060 */ NULL, NULL, NULL },
1778 { /* 0x2068 */ NULL, NULL, NULL },
1779
1780 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
1781 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
1782
1783 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
1784 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
1785 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
1786};
1787AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
1788
1789
1790/**
1791 * Gets the register access structure given its MMIO offset.
1792 *
1793 * @returns The register access structure, or NULL if the offset is invalid.
1794 * @param off The MMIO offset of the register being accessed.
1795 */
1796static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
1797{
1798 /* Figure out which table the register belongs to and validate its index. */
1799 PCIOMMUREGACC pReg;
1800 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
1801 {
1802 uint32_t const idxReg = off >> 3;
1803 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
1804 pReg = &g_aRegAccess0[idxReg];
1805 }
1806 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
1807 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
1808 {
1809 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
1810 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
1811 pReg = &g_aRegAccess1[idxReg];
1812 }
1813 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
1814 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
1815 {
1816 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
1817 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
1818 pReg = &g_aRegAccess2[idxReg];
1819 }
1820 else
1821 return NULL;
1822 return pReg;
1823}
1824
1825
1826/**
1827 * Writes an IOMMU register (32-bit and 64-bit).
1828 *
1829 * @returns Strict VBox status code.
1830 * @param pDevIns The IOMMU device instance.
1831 * @param off MMIO byte offset to the register.
1832 * @param cb The size of the write access.
1833 * @param uValue The value being written.
1834 *
1835 * @thread EMT.
1836 */
1837static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
1838{
1839 /*
1840 * Validate the access in case of IOM bug or incorrect assumption.
1841 */
1842 Assert(off < IOMMU_MMIO_REGION_SIZE);
1843 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
1844 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
1845
1846 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
1847
1848 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1849 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
1850 if (pReg)
1851 { /* likely */ }
1852 else
1853 {
1854 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
1855 return VINF_SUCCESS;
1856 }
1857
1858 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
1859 if (pReg->pfnWrite)
1860 { /* likely */ }
1861 else
1862 {
1863 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1864 return VINF_SUCCESS;
1865 }
1866
1867 /*
1868 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
1869 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
1870 * consecutive 32-bit registers.
1871 */
1872 if (cb == 8)
1873 {
1874 if (!(off & 7))
1875 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1876
1877 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
1878 return VINF_SUCCESS;
1879 }
1880
1881 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
1882 Assert(cb == 4);
1883 if (!(off & 7))
1884 {
1885 /*
1886 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
1887 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1888 */
1889 uint64_t u64Read;
1890 if (pReg->pfnRead)
1891 {
1892 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
1893 if (RT_FAILURE(rcStrict))
1894 {
1895 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1896 return rcStrict;
1897 }
1898 }
1899 else
1900 u64Read = 0;
1901
1902 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
1903 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
1904 }
1905
1906 /*
1907 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
1908 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
1909 */
1910 Assert(!(off & 3));
1911 Assert(off & 7);
1912 Assert(off >= 4);
1913 uint64_t u64Read;
1914 if (pReg->pfnRead)
1915 {
1916 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
1917 if (RT_FAILURE(rcStrict))
1918 {
1919 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1920 return rcStrict;
1921 }
1922 }
1923 else
1924 u64Read = 0;
1925
1926 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
1927 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
1928}
1929
1930
1931/**
1932 * Reads an IOMMU register (64-bit) given its MMIO offset.
1933 *
1934 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
1935 * boundary include the lower half of the subsequent register.
1936 *
1937 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
1938 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
1939 * software will only perform 32-bit reads on those 32-bit registers that are
1940 * aligned on 8-byte boundaries.
1941 *
1942 * @returns Strict VBox status code.
1943 * @param pDevIns The IOMMU device instance.
1944 * @param off The MMIO offset of the register in bytes.
1945 * @param puResult Where to store the value being read.
1946 *
1947 * @thread EMT.
1948 */
1949static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
1950{
1951 Assert(off < IOMMU_MMIO_REGION_SIZE);
1952 Assert(!(off & 7) || !(off & 3));
1953
1954 Log4Func(("off=%#x\n", off));
1955
1956 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1957 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1958 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
1959
1960 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
1961 if (pReg)
1962 { /* likely */ }
1963 else
1964 {
1965 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
1966 return VINF_IOM_MMIO_UNUSED_FF;
1967 }
1968
1969 /* If a read handler doesn't exist, it's a reserved or unknown register. */
1970 if (pReg->pfnRead)
1971 { /* likely */ }
1972 else
1973 {
1974 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
1975 return VINF_IOM_MMIO_UNUSED_00;
1976 }
1977
1978 /*
1979 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
1980 * The caller takes care of truncating upper 32 bits for 32-bit reads.
1981 */
1982 if (!(off & 7))
1983 return pReg->pfnRead(pDevIns, pThis, off, puResult);
1984
1985 /*
1986 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
1987 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
1988 */
1989 Assert(!(off & 3));
1990 Assert(off & 7);
1991 Assert(off >= 4);
1992 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
1993 if (RT_SUCCESS(rcStrict))
1994 *puResult >>= 32;
1995 else
1996 {
1997 *puResult = 0;
1998 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
1999 }
2000
2001 return rcStrict;
2002}
2003
2004
2005/**
2006 * Raises the MSI interrupt for the IOMMU device.
2007 *
2008 * @param pDevIns The IOMMU device instance.
2009 *
2010 * @thread Any.
2011 * @remarks The IOMMU lock may or may not be held.
2012 */
2013static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2014{
2015 LogFlowFunc(("\n"));
2016 if (iommuAmdIsMsiEnabled(pDevIns))
2017 {
2018 LogFunc(("Raising MSI\n"));
2019 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2020 }
2021}
2022
2023#if 0
2024/**
2025 * Clears the MSI interrupt for the IOMMU device.
2026 *
2027 * @param pDevIns The IOMMU device instance.
2028 *
2029 * @thread Any.
2030 * @remarks The IOMMU lock may or may not be held.
2031 */
2032static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2033{
2034 if (iommuAmdIsMsiEnabled(pDevIns))
2035 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2036}
2037#endif
2038
2039/**
2040 * Writes an entry to the event log in memory.
2041 *
2042 * @returns VBox status code.
2043 * @param pDevIns The IOMMU device instance.
2044 * @param pEvent The event to log.
2045 *
2046 * @thread Any.
2047 */
2048static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2049{
2050 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2051
2052 IOMMU_ASSERT_LOCKED(pDevIns);
2053
2054 /* Check if event logging is active and the log has not overflowed. */
2055 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2056 if ( Status.n.u1EvtLogRunning
2057 && !Status.n.u1EvtOverflow)
2058 {
2059 uint32_t const cbEvt = sizeof(*pEvent);
2060
2061 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2062 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2063 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2064
2065 /* Ensure we have space in the event log. */
2066 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2067 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2068 if (cEvts + 1 < cMaxEvts)
2069 {
2070 /* Write the event log entry to memory. */
2071 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2072 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2073 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2074 if (RT_FAILURE(rc))
2075 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2076
2077 /* Increment the event log tail pointer. */
2078 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2079 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2080
2081 /* Indicate that an event log entry was written. */
2082 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2083
2084 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2085 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2086 if (Ctrl.n.u1EvtIntrEn)
2087 iommuAmdMsiInterruptRaise(pDevIns);
2088 }
2089 else
2090 {
2091 /* Indicate that the event log has overflowed. */
2092 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2093
2094 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2095 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2096 if (Ctrl.n.u1EvtIntrEn)
2097 iommuAmdMsiInterruptRaise(pDevIns);
2098 }
2099 }
2100
2101 return VINF_SUCCESS;
2102}
2103
2104
2105/**
2106 * Sets an event in the hardware error registers.
2107 *
2108 * @param pDevIns The IOMMU device instance.
2109 * @param pEvent The event.
2110 *
2111 * @thread Any.
2112 */
2113static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2114{
2115 IOMMU_ASSERT_LOCKED(pDevIns);
2116
2117 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2118 if (pThis->ExtFeat.n.u1HwErrorSup)
2119 {
2120 if (pThis->HwEvtStatus.n.u1Valid)
2121 pThis->HwEvtStatus.n.u1Overflow = 1;
2122 pThis->HwEvtStatus.n.u1Valid = 1;
2123 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2124 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2125 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2126 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2127 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2128 }
2129}
2130
2131
2132/**
2133 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2134 *
2135 * @param uDevId The device ID.
2136 * @param uDomainId The domain ID.
2137 * @param GCPhysPtEntity The system physical address of the page table
2138 * entity.
2139 * @param enmOp The IOMMU operation being performed.
2140 * @param pEvtPageTabHwErr Where to store the initialized event.
2141 */
2142static void iommuAmdPageTabHwErrorEventInit(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2143 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2144{
2145 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2146 pEvtPageTabHwErr->n.u16DevId = uDevId;
2147 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
2148 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
2149 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2150 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2151 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2152 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2153 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
2154 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
2155}
2156
2157
2158/**
2159 * Raises a PAGE_TAB_HARDWARE_ERROR event.
2160 *
2161 * @param pDevIns The IOMMU device instance.
2162 * @param enmOp The IOMMU operation being performed.
2163 * @param pEvtPageTabHwErr The page table hardware error event.
2164 *
2165 * @thread Any.
2166 */
2167static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2168{
2169 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
2170 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
2171
2172 IOMMU_LOCK_NORET(pDevIns);
2173
2174 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
2175 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
2176 if (enmOp != IOMMUOP_CMD)
2177 iommuAmdSetPciTargetAbort(pDevIns);
2178
2179 IOMMU_UNLOCK(pDevIns);
2180
2181 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
2182 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
2183 pEvtPageTabHwErr->n.u2Type));
2184}
2185
2186
2187#ifdef IN_RING3
2188/**
2189 * Initializes a COMMAND_HARDWARE_ERROR event.
2190 *
2191 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
2192 * @param pEvtCmdHwErr Where to store the initialized event.
2193 */
2194static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2195{
2196 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
2197 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
2198 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
2199 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
2200}
2201
2202
2203/**
2204 * Raises a COMMAND_HARDWARE_ERROR event.
2205 *
2206 * @param pDevIns The IOMMU device instance.
2207 * @param pEvtCmdHwErr The command hardware error event.
2208 *
2209 * @thread Any.
2210 */
2211static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2212{
2213 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
2214 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
2215 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2216
2217 IOMMU_LOCK_NORET(pDevIns);
2218
2219 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
2220 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
2221 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2222
2223 IOMMU_UNLOCK(pDevIns);
2224
2225 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
2226}
2227#endif /* IN_RING3 */
2228
2229
2230/**
2231 * Initializes a DEV_TAB_HARDWARE_ERROR event.
2232 *
2233 * @param uDevId The device ID.
2234 * @param GCPhysDte The system physical address of the failed device table
2235 * access.
2236 * @param enmOp The IOMMU operation being performed.
2237 * @param pEvtDevTabHwErr Where to store the initialized event.
2238 */
2239static void iommuAmdDevTabHwErrorEventInit(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
2240 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2241{
2242 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
2243 pEvtDevTabHwErr->n.u16DevId = uDevId;
2244 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2245 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
2246 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2247 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2248 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2249 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
2250 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
2251}
2252
2253
2254/**
2255 * Raises a DEV_TAB_HARDWARE_ERROR event.
2256 *
2257 * @param pDevIns The IOMMU device instance.
2258 * @param enmOp The IOMMU operation being performed.
2259 * @param pEvtDevTabHwErr The device table hardware error event.
2260 *
2261 * @thread Any.
2262 */
2263static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2264{
2265 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2266 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2267
2268 IOMMU_LOCK_NORET(pDevIns);
2269
2270 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
2271 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
2272 if (enmOp != IOMMUOP_CMD)
2273 iommuAmdSetPciTargetAbort(pDevIns);
2274
2275 IOMMU_UNLOCK(pDevIns);
2276
2277 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2278 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2279}
2280
2281
2282#ifdef IN_RING3
2283/**
2284 * Initializes an ILLEGAL_COMMAND_ERROR event.
2285 *
2286 * @param GCPhysCmd The system physical address of the failed command
2287 * access.
2288 * @param pEvtIllegalCmd Where to store the initialized event.
2289 */
2290static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2291{
2292 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2293 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2294 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2295 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2296}
2297
2298
2299/**
2300 * Raises an ILLEGAL_COMMAND_ERROR event.
2301 *
2302 * @param pDevIns The IOMMU device instance.
2303 * @param pEvtIllegalCmd The illegal command error event.
2304 */
2305static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2306{
2307 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2308 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2309 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2310
2311 IOMMU_LOCK_NORET(pDevIns);
2312
2313 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2314 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2315
2316 IOMMU_UNLOCK(pDevIns);
2317
2318 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2319}
2320#endif /* IN_RING3 */
2321
2322
2323/**
2324 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2325 *
2326 * @param uDevId The device ID.
2327 * @param uIova The I/O virtual address.
2328 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2329 * event was caused by an invalid level encoding in the
2330 * DTE.
2331 * @param enmOp The IOMMU operation being performed.
2332 * @param pEvtIllegalDte Where to store the initialized event.
2333 */
2334static void iommuAmdIllegalDteEventInit(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2335 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2336{
2337 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2338 pEvtIllegalDte->n.u16DevId = uDevId;
2339 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2340 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2341 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2342 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2343 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2344 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2345 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2346 * IOMMU spec here but not for this field for I/O page fault event. */
2347 Assert(!(uIova & UINT64_C(0x3)));
2348}
2349
2350
2351/**
2352 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2353 *
2354 * @param pDevIns The IOMMU instance data.
2355 * @param enmOp The IOMMU operation being performed.
2356 * @param pEvtIllegalDte The illegal device table entry event.
2357 * @param enmEvtType The illegal device table entry event type.
2358 *
2359 * @thread Any.
2360 */
2361static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2362 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2363{
2364 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2365 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2366
2367 IOMMU_LOCK_NORET(pDevIns);
2368
2369 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2370 if (enmOp != IOMMUOP_CMD)
2371 iommuAmdSetPciTargetAbort(pDevIns);
2372
2373 IOMMU_UNLOCK(pDevIns);
2374
2375 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2376 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2377 NOREF(enmEvtType);
2378}
2379
2380
2381/**
2382 * Initializes an IO_PAGE_FAULT event.
2383 *
2384 * @param uDevId The device ID.
2385 * @param uDomainId The domain ID.
2386 * @param uIova The I/O virtual address being accessed.
2387 * @param fPresent Transaction to a page marked as present (including
2388 * DTE.V=1) or interrupt marked as remapped
2389 * (IRTE.RemapEn=1).
2390 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2391 * the I/O page fault was caused by invalid level
2392 * encoding.
2393 * @param fPermDenied Permission denied for the address being accessed.
2394 * @param enmOp The IOMMU operation being performed.
2395 * @param pEvtIoPageFault Where to store the initialized event.
2396 */
2397static void iommuAmdIoPageFaultEventInit(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2398 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2399{
2400 Assert(!fPermDenied || fPresent);
2401 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2402 pEvtIoPageFault->n.u16DevId = uDevId;
2403 //pEvtIoPageFault->n.u4PasidHi = 0;
2404 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2405 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2406 //pEvtIoPageFault->n.u1NoExecute = 0;
2407 //pEvtIoPageFault->n.u1User = 0;
2408 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2409 pEvtIoPageFault->n.u1Present = fPresent;
2410 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2411 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2412 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2413 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2414 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2415 pEvtIoPageFault->n.u64Addr = uIova;
2416}
2417
2418
2419/**
2420 * Raises an IO_PAGE_FAULT event.
2421 *
2422 * @param pDevIns The IOMMU instance data.
2423 * @param pDte The device table entry. Optional, can be NULL
2424 * depending on @a enmOp.
2425 * @param pIrte The interrupt remapping table entry. Optional, can
2426 * be NULL depending on @a enmOp.
2427 * @param enmOp The IOMMU operation being performed.
2428 * @param pEvtIoPageFault The I/O page fault event.
2429 * @param enmEvtType The I/O page fault event type.
2430 *
2431 * @thread Any.
2432 */
2433static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
2434 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2435{
2436 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2437 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2438
2439 IOMMU_LOCK_NORET(pDevIns);
2440
2441 bool fSuppressEvtLogging = false;
2442 if ( enmOp == IOMMUOP_MEM_READ
2443 || enmOp == IOMMUOP_MEM_WRITE)
2444 {
2445 if ( pDte
2446 && pDte->n.u1Valid)
2447 {
2448 fSuppressEvtLogging = pDte->n.u1SuppressAllPfEvents;
2449 /** @todo IOMMU: Implement DTE.SE bit, i.e. device ID specific I/O page fault
2450 * suppression. Perhaps will be possible when we complete IOTLB/cache
2451 * handling. */
2452 }
2453 }
2454 else if (enmOp == IOMMUOP_INTR_REQ)
2455 {
2456 if ( pDte
2457 && pDte->n.u1IntrMapValid)
2458 fSuppressEvtLogging = !pDte->n.u1IgnoreUnmappedIntrs;
2459
2460 if ( !fSuppressEvtLogging
2461 && pIrte)
2462 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2463 }
2464 /* else: Events are never suppressed for commands. */
2465
2466 switch (enmEvtType)
2467 {
2468 case kIoPageFaultType_PermDenied:
2469 {
2470 /* Cannot be triggered by a command. */
2471 Assert(enmOp != IOMMUOP_CMD);
2472 RT_FALL_THRU();
2473 }
2474 case kIoPageFaultType_DteRsvdPagingMode:
2475 case kIoPageFaultType_PteInvalidPageSize:
2476 case kIoPageFaultType_PteInvalidLvlEncoding:
2477 case kIoPageFaultType_SkippedLevelIovaNotZero:
2478 case kIoPageFaultType_PteRsvdNotZero:
2479 case kIoPageFaultType_PteValidNotSet:
2480 case kIoPageFaultType_DteTranslationDisabled:
2481 case kIoPageFaultType_PasidInvalidRange:
2482 {
2483 /*
2484 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2485 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
2486 */
2487 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2488 {
2489 if (!fSuppressEvtLogging)
2490 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2491 if (enmOp != IOMMUOP_CMD)
2492 iommuAmdSetPciTargetAbort(pDevIns);
2493 }
2494 break;
2495 }
2496
2497 case kIoPageFaultType_UserSupervisor:
2498 {
2499 /* Access is blocked and only creates an event log entry. */
2500 if (!fSuppressEvtLogging)
2501 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2502 break;
2503 }
2504
2505 case kIoPageFaultType_IrteAddrInvalid:
2506 case kIoPageFaultType_IrteRsvdNotZero:
2507 case kIoPageFaultType_IrteRemapEn:
2508 case kIoPageFaultType_IrteRsvdIntType:
2509 case kIoPageFaultType_IntrReqAborted:
2510 case kIoPageFaultType_IntrWithPasid:
2511 {
2512 /* Only trigerred by interrupt requests. */
2513 Assert(enmOp == IOMMUOP_INTR_REQ);
2514 if (!fSuppressEvtLogging)
2515 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2516 iommuAmdSetPciTargetAbort(pDevIns);
2517 break;
2518 }
2519
2520 case kIoPageFaultType_SmiFilterMismatch:
2521 {
2522 /* Not supported and probably will never be, assert. */
2523 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
2524 break;
2525 }
2526
2527 case kIoPageFaultType_DevId_Invalid:
2528 {
2529 /* Cannot be triggered by a command. */
2530 Assert(enmOp != IOMMUOP_CMD);
2531 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
2532 if (!fSuppressEvtLogging)
2533 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2534 if ( enmOp == IOMMUOP_MEM_READ
2535 || enmOp == IOMMUOP_MEM_WRITE)
2536 iommuAmdSetPciTargetAbort(pDevIns);
2537 break;
2538 }
2539 }
2540
2541 IOMMU_UNLOCK(pDevIns);
2542}
2543
2544
2545/**
2546 * Returns whether the I/O virtual address is to be excluded from translation and
2547 * permission checks.
2548 *
2549 * @returns @c true if the DVA is excluded, @c false otherwise.
2550 * @param pThis The IOMMU device state.
2551 * @param pDte The device table entry.
2552 * @param uIova The I/O virtual address.
2553 *
2554 * @remarks Ensure the exclusion range is enabled prior to calling this function.
2555 *
2556 * @thread Any.
2557 */
2558static bool iommuAmdIsDvaInExclRange(PCIOMMU pThis, PCDTE_T pDte, uint64_t uIova)
2559{
2560 /* Ensure the exclusion range is enabled. */
2561 Assert(pThis->ExclRangeBaseAddr.n.u1ExclEnable);
2562
2563 /* Check if the IOVA falls within the exclusion range. */
2564 uint64_t const uIovaExclFirst = pThis->ExclRangeBaseAddr.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT;
2565 uint64_t const uIovaExclLast = pThis->ExclRangeLimit.n.u52ExclLimit;
2566 if (uIovaExclLast - uIova >= uIovaExclFirst)
2567 {
2568 /* Check if device access to addresses in the exclusion range can be forwarded untranslated. */
2569 if ( pThis->ExclRangeBaseAddr.n.u1AllowAll
2570 || pDte->n.u1AllowExclusion)
2571 return true;
2572 }
2573 return false;
2574}
2575
2576
2577/**
2578 * Reads a device table entry for the given the device ID.
2579 *
2580 * @returns VBox status code.
2581 * @param pDevIns The IOMMU device instance.
2582 * @param uDevId The device ID.
2583 * @param enmOp The IOMMU operation being performed.
2584 * @param pDte Where to store the device table entry.
2585 *
2586 * @thread Any.
2587 */
2588static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
2589{
2590 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2591 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2592
2593 /* Figure out which device table segment is being accessed. */
2594 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
2595 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
2596
2597 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
2598 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2599 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
2600
2601 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
2602 uint32_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
2603 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
2604
2605 /* Ensure the DTE falls completely within the device table segment. */
2606 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
2607 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
2608 {
2609 /* Read the device table entry from guest memory. */
2610 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
2611 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
2612 if (RT_SUCCESS(rc))
2613 return rc;
2614
2615 /* Raise a device table hardware error. */
2616 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
2617
2618 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
2619 iommuAmdDevTabHwErrorEventInit(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
2620 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
2621 return VERR_IOMMU_DTE_READ_FAILED;
2622 }
2623
2624 /* Raise an I/O page fault for out-of-bounds acccess. */
2625 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2626 iommuAmdIoPageFaultEventInit(uDevId, 0 /* uDomainId */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
2627 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2628 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_DevId_Invalid);
2629 return VERR_IOMMU_DTE_BAD_OFFSET;
2630}
2631
2632
2633/**
2634 * Performs pre-translation checks for the given device table entry.
2635 *
2636 * @returns VBox status code.
2637 * @param pDevIns The IOMMU device instance.
2638 * @param uIova The I/O virtual address to translate.
2639 * @param uDevId The device ID.
2640 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2641 * permissions for the access being made.
2642 * @param pDte The device table entry.
2643 * @param enmOp The IOMMU operation being performed.
2644 * @param pWalkResult Where to store the results of the I/O page walk. This is
2645 * only updated when VINF_SUCCESS is returned.
2646 *
2647 * @thread Any.
2648 */
2649static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2650 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2651{
2652 /*
2653 * Check if the translation is valid, otherwise raise an I/O page fault.
2654 */
2655 if (pDte->n.u1TranslationValid)
2656 { /* likely */ }
2657 else
2658 {
2659 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
2660 * doesn't explicitly say whether an I/O page fault is raised. From other
2661 * places in the spec. it seems early page walk terminations (starting with
2662 * the DTE) return the state computed so far and raises an I/O page fault. So
2663 * returning an invalid translation rather than skipping translation. */
2664 LogFunc(("Translation valid bit not set -> IOPF\n"));
2665 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2666 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2667 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2668 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2669 kIoPageFaultType_DteTranslationDisabled);
2670 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2671 }
2672
2673 /*
2674 * Check permissions bits in the DTE.
2675 * Note: This MUST be checked prior to checking the root page table level below!
2676 */
2677 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2678 if ((fAccess & fDtePerm) == fAccess)
2679 { /* likely */ }
2680 else
2681 {
2682 LogFunc(("Permission denied by DTE (fAccess=%#x fDtePerm=%#x) -> IOPF\n", fAccess, fDtePerm));
2683 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2684 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2685 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2686 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2687 return VERR_IOMMU_ADDR_ACCESS_DENIED;
2688 }
2689
2690 /*
2691 * If the root page table level is 0, translation is disabled and GPA=SPA and
2692 * the DTE.IR and DTE.IW bits control permissions (verified above).
2693 */
2694 uint8_t const uMaxLevel = pDte->n.u3Mode;
2695 if (uMaxLevel != 0)
2696 { /* likely */ }
2697 else
2698 {
2699 Assert((fAccess & fDtePerm) == fAccess); /* Verify we've checked permissions. */
2700 pWalkResult->GCPhysSpa = uIova;
2701 pWalkResult->cShift = 0;
2702 pWalkResult->fIoPerm = fDtePerm;
2703 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
2704 }
2705
2706 /*
2707 * If the root page table level exceeds the allowed host-address translation level,
2708 * page walk is terminated and translation fails.
2709 */
2710 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2711 { /* likely */ }
2712 else
2713 {
2714 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
2715 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
2716 * I'm just going with I/O page fault. */
2717 LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
2718 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2719 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2720 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2721 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2722 kIoPageFaultType_PteInvalidLvlEncoding);
2723 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2724 }
2725
2726 /* The DTE allows translations for this device. */
2727 return VINF_SUCCESS;
2728}
2729
2730
2731/**
2732 * Walks the I/O page table to translate the I/O virtual address to a system
2733 * physical address.
2734 *
2735 * @returns VBox status code.
2736 * @param pDevIns The IOMMU device instance.
2737 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
2738 * @param uDevId The device ID.
2739 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2740 * permissions for the access being made.
2741 * @param pDte The device table entry.
2742 * @param enmOp The IOMMU operation being performed.
2743 * @param pWalkResult Where to store the results of the I/O page walk. This is
2744 * only updated when VINF_SUCCESS is returned.
2745 *
2746 * @thread Any.
2747 */
2748static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fAccess, PCDTE_T pDte,
2749 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
2750{
2751 Assert(pDte->n.u1Valid);
2752 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
2753
2754 /* The virtual address bits indexing table. */
2755 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
2756 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
2757 UINT64_C(0x00000000001ff000),
2758 UINT64_C(0x000000003fe00000),
2759 UINT64_C(0x0000007fc0000000),
2760 UINT64_C(0x0000ff8000000000),
2761 UINT64_C(0x01ff000000000000),
2762 UINT64_C(0xfe00000000000000),
2763 UINT64_C(0x0000000000000000) };
2764 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
2765 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
2766
2767 /* Traverse the I/O page table starting with the page directory in the DTE. */
2768 IOPTENTITY_T PtEntity;
2769 PtEntity.u64 = pDte->au64[0];
2770 for (;;)
2771 {
2772 /* Figure out the system physical address of the page table at the current level. */
2773 uint8_t const uLevel = PtEntity.n.u3NextLevel;
2774
2775 /* Read the page table entity at the current level. */
2776 {
2777 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
2778 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2779 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
2780 uint64_t const offPte = idxPte << 3;
2781 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
2782 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
2783 if (RT_FAILURE(rc))
2784 {
2785 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
2786 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
2787 iommuAmdPageTabHwErrorEventInit(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
2788 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
2789 return VERR_IOMMU_IPE_2;
2790 }
2791 }
2792
2793 /* Check present bit. */
2794 if (PtEntity.n.u1Present)
2795 { /* likely */ }
2796 else
2797 {
2798 LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
2799 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2800 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
2801 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2802 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2803 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2804 }
2805
2806 /* Check permission bits. */
2807 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
2808 if ((fAccess & fPtePerm) == fAccess)
2809 { /* likely */ }
2810 else
2811 {
2812 LogFunc(("Page table entry access denied (uDevId=%#x fAccess=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fAccess, fPtePerm));
2813 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2814 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2815 true /* fPermDenied */, enmOp, &EvtIoPageFault);
2816 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_PermDenied);
2817 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2818 }
2819
2820 /* If this is a PTE, we're at the final level and we're done. */
2821 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
2822 if (uNextLevel == 0)
2823 {
2824 /* The page size of the translation is the default (4K). */
2825 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2826 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
2827 pWalkResult->fIoPerm = fPtePerm;
2828 return VINF_SUCCESS;
2829 }
2830 if (uNextLevel == 7)
2831 {
2832 /* The default page size of the translation is overridden. */
2833 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
2834 uint8_t cShift = X86_PAGE_4K_SHIFT;
2835 while (GCPhysPte & RT_BIT_64(cShift++))
2836 ;
2837
2838 /* The page size must be larger than the default size and lower than the default size of the higher level. */
2839 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
2840 if ( cShift > s_acIovaLevelShifts[uLevel]
2841 && cShift < s_acIovaLevelShifts[uLevel + 1])
2842 {
2843 pWalkResult->GCPhysSpa = GCPhysPte;
2844 pWalkResult->cShift = cShift;
2845 pWalkResult->fIoPerm = fPtePerm;
2846 return VINF_SUCCESS;
2847 }
2848
2849 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
2850 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2851 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2852 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2853 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2854 kIoPageFaultType_PteInvalidPageSize);
2855 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2856 }
2857
2858 /* Validate the next level encoding of the PDE. */
2859#if IOMMU_MAX_HOST_PT_LEVEL < 6
2860 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
2861 { /* likely */ }
2862 else
2863 {
2864 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
2865 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2866 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2867 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2868 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2869 kIoPageFaultType_PteInvalidLvlEncoding);
2870 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2871 }
2872#else
2873 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
2874#endif
2875
2876 /* Validate level transition. */
2877 if (uNextLevel < uLevel)
2878 { /* likely */ }
2879 else
2880 {
2881 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
2882 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2883 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2884 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2885 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2886 kIoPageFaultType_PteInvalidLvlEncoding);
2887 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2888 }
2889
2890 /* Ensure IOVA bits of skipped levels are zero. */
2891 Assert(uLevel > 0);
2892 uint64_t uIovaSkipMask = 0;
2893 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
2894 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
2895 if (!(uIova & uIovaSkipMask))
2896 { /* likely */ }
2897 else
2898 {
2899 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
2900 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
2901 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
2902 false /* fPermDenied */, enmOp, &EvtIoPageFault);
2903 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
2904 kIoPageFaultType_SkippedLevelIovaNotZero);
2905 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2906 }
2907
2908 /* Continue with traversing the page directory at this level. */
2909 }
2910}
2911
2912
2913/**
2914 * Looks up an I/O virtual address from the device table.
2915 *
2916 * @returns VBox status code.
2917 * @param pDevIns The IOMMU instance data.
2918 * @param uDevId The device ID.
2919 * @param uIova The I/O virtual address to lookup.
2920 * @param cbAccess The size of the access.
2921 * @param fAccess The access permissions (IOMMU_IO_PERM_XXX). This is the
2922 * permissions for the access being made.
2923 * @param enmOp The IOMMU operation being performed.
2924 * @param pGCPhysSpa Where to store the translated system physical address.
2925 * @param pcbContiguous Where to store the number of contiguous bytes translated
2926 * and permission-checked.
2927 *
2928 * @thread Any.
2929 */
2930static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fAccess,
2931 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2932{
2933 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2934 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
2935 size_t cbContiguous = 0;
2936
2937 STAM_PROFILE_ADV_START(&pThis->StatDteLookup, a);
2938
2939 /* Read the device table entry from memory. */
2940 DTE_T Dte;
2941 int rc = iommuAmdDteRead(pDevIns, uDevId, enmOp, &Dte);
2942 if (RT_SUCCESS(rc))
2943 {
2944 /* If the DTE is not valid, addresses are forwarded without translation */
2945 if (Dte.n.u1Valid)
2946 {
2947 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
2948 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
2949 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
2950 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
2951 {
2952 /* If the IOVA is subject to address exclusion, addresses are forwarded without translation. */
2953 if ( !pThis->ExclRangeBaseAddr.n.u1ExclEnable /** @todo lock or make atomic read! */
2954 || !iommuAmdIsDvaInExclRange(pThis, &Dte, uIova))
2955 {
2956 IOWALKRESULT WalkResult;
2957 RT_ZERO(WalkResult);
2958 rc = iommuAmdPreTranslateChecks(pDevIns, uDevId, uIova, fAccess, &Dte, enmOp, &WalkResult);
2959 if (rc == VINF_SUCCESS)
2960 {
2961 /* Walk the I/O page tables to translate the IOVA and check permissions for the
2962 remaining pages in the access. */
2963 size_t cbRemaining = cbAccess;
2964 uint64_t uIovaPage = uIova & X86_PAGE_4K_BASE_MASK;
2965 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
2966 uint64_t cbPages = 0;
2967#ifdef IOMMU_WITH_IOTLBE_CACHE
2968 IOWALKRESULT WalkResultPrev;
2969 RT_ZERO(WalkResultPrev);
2970#endif
2971 for (;;)
2972 {
2973 rc = iommuAmdIoPageTableWalk(pDevIns, uDevId, uIovaPage, fAccess, &Dte, enmOp, &WalkResult);
2974 if (RT_SUCCESS(rc))
2975 {
2976 /* Store the translated address before continuing to access more pages. */
2977 Assert(WalkResult.cShift >= X86_PAGE_4K_SHIFT);
2978 if (cbRemaining == cbAccess)
2979 {
2980 uint64_t const offMask = ~(UINT64_C(0xffffffffffffffff) << WalkResult.cShift);
2981 uint64_t const offSpa = uIova & offMask;
2982 GCPhysSpa = WalkResult.GCPhysSpa | offSpa;
2983#ifdef IOMMU_WITH_IOTLBE_CACHE
2984 /* Store the walk result from the first page. */
2985 WalkResultPrev = WalkResult;
2986#endif
2987 }
2988#ifdef IOMMU_WITH_IOTLBE_CACHE
2989 /* Check if addresses translated so far result in a physically contiguous region
2990 and that permissions and page sizes are identical for all pages in the access. */
2991 else if ( (GCPhysSpa & X86_PAGE_4K_BASE_MASK) + cbPages == WalkResult.GCPhysSpa
2992 && WalkResultPrev.cShift == WalkResult.cShift
2993 && WalkResultPrev.fIoPerm == WalkResult.fIoPerm)
2994 {
2995 /* Paranoia. */
2996 Assert((WalkResultPrev.GCPhysSpa & X86_PAGE_4K_BASE_MASK)
2997 + RT_BIT_64(WalkResultPrev.cShift) == WalkResult.GCPhysSpa);
2998 /* Store the walk result before moving on to the next page. */
2999 WalkResultPrev = WalkResult;
3000 }
3001#else
3002 /* Check if addresses translated so far result in a physically contiguous region. */
3003 else if ( (GCPhysSpa & X86_PAGE_4K_BASE_MASK) + cbPages == WalkResult.GCPhysSpa)
3004 { /* likely */ }
3005#endif
3006 else
3007 {
3008 STAM_COUNTER_INC(&pThis->StatDteLookupNonContig);
3009 break;
3010 }
3011
3012 /* Check if we need to access more pages. */
3013 uint64_t const cbPage = RT_BIT_64(WalkResult.cShift);
3014 if (cbRemaining > cbPage - offIova)
3015 {
3016 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3017 cbPages += cbPage; /* Update size of all pages read thus far. */
3018 uIovaPage += cbPage; /* Update address of the next access. */
3019 offIova = 0; /* After first page, all pages are accessed from off 0. */
3020 }
3021 else
3022 {
3023 cbRemaining = 0;
3024 break;
3025 }
3026 }
3027 else
3028 {
3029 /* Translation failed. */
3030 GCPhysSpa = NIL_RTGCPHYS;
3031 cbRemaining = cbAccess;
3032 break;
3033 }
3034 }
3035
3036 /* Update how much contiguous memory was accessed. */
3037 cbContiguous = cbAccess - cbRemaining;
3038 }
3039 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
3040 {
3041 /* Translation is disabled for this device (root paging mode is 0). */
3042 GCPhysSpa = uIova;
3043 cbContiguous = cbAccess;
3044 rc = VINF_SUCCESS;
3045
3046 /* Paranoia. */
3047 Assert(WalkResult.cShift == 0);
3048 Assert(WalkResult.GCPhysSpa == uIova);
3049 Assert((WalkResult.fIoPerm & fAccess) == fAccess);
3050 /** @todo IOMMU: Add to IOLTB cache. */
3051 }
3052 else
3053 {
3054 /* Translation failed or access is denied. */
3055 GCPhysSpa = NIL_RTGCPHYS;
3056 cbContiguous = 0;
3057 Assert(RT_FAILURE(rc));
3058 }
3059 }
3060 else
3061 {
3062 /* The IOVA is subject to address exclusion, forward untranslated. */
3063 /** @todo IOMMU: Add to IOLTB cache. */
3064 GCPhysSpa = uIova;
3065 cbContiguous = cbAccess;
3066 }
3067 }
3068 else
3069 {
3070 /* Invalid reserved bits in the DTE, raise an error event. */
3071 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
3072 EVT_ILLEGAL_DTE_T Event;
3073 iommuAmdIllegalDteEventInit(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
3074 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3075 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3076 }
3077 }
3078 else
3079 {
3080 /*
3081 * The DTE is not valid, forward addresses untranslated.
3082 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
3083 */
3084 /** @todo IOMMU: Add to IOLTB cache. */
3085 GCPhysSpa = uIova;
3086 cbContiguous = cbAccess;
3087 }
3088 }
3089 else
3090 {
3091 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3092 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3093 }
3094
3095 *pGCPhysSpa = GCPhysSpa;
3096 *pcbContiguous = cbContiguous;
3097 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
3098
3099 STAM_PROFILE_ADV_STOP(&pThis->StatDteLookup, a);
3100 return rc;
3101}
3102
3103
3104/**
3105 * Memory access transaction from a device.
3106 *
3107 * @returns VBox status code.
3108 * @param pDevIns The IOMMU device instance.
3109 * @param uDevId The device ID (bus, device, function).
3110 * @param uIova The I/O virtual address being accessed.
3111 * @param cbAccess The number of bytes being accessed.
3112 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3113 * @param pGCPhysSpa Where to store the translated system physical address.
3114 * @param pcbContiguous Where to store the number of contiguous bytes translated
3115 * and permission-checked.
3116 *
3117 * @thread Any.
3118 */
3119static DECLCALLBACK(int) iommuAmdDeviceMemAccess(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess,
3120 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3121{
3122 /* Validate. */
3123 AssertPtr(pDevIns);
3124 AssertPtr(pGCPhysSpa);
3125 Assert(cbAccess > 0);
3126 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3127
3128 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3129 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3130 if (Ctrl.n.u1IommuEn)
3131 {
3132 IOMMUOP enmOp;
3133 uint8_t fAccess;
3134 if (fFlags & PDMIOMMU_MEM_F_READ)
3135 {
3136 enmOp = IOMMUOP_MEM_READ;
3137 fAccess = IOMMU_IO_PERM_READ;
3138 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
3139 }
3140 else
3141 {
3142 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
3143 enmOp = IOMMUOP_MEM_WRITE;
3144 fAccess = IOMMU_IO_PERM_WRITE;
3145 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
3146 }
3147
3148#ifdef VBOX_STRICT
3149 static const char * const s_apszAccess[] = { "none", "read", "write" };
3150 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
3151 const char *pszAccess = s_apszAccess[fAccess];
3152 LogFlowFunc(("uDevId=%#x uIova=%#RX64 szAccess=%s cbAccess=%zu\n", uDevId, uIova, pszAccess, cbAccess));
3153#endif
3154
3155 /** @todo IOMMU: IOTLB cache lookup. */
3156
3157 /* Lookup the IOVA from the device table. */
3158 int rc = iommuAmdDteLookup(pDevIns, uDevId, uIova, cbAccess, fAccess, enmOp, pGCPhysSpa, pcbContiguous);
3159 if (RT_SUCCESS(rc))
3160 { /* likely */ }
3161 else
3162 LogFunc(("DTE lookup failed! uDevId=%#x uIova=%#RX64 fAccess=%u cbAccess=%zu rc=%#Rrc\n", uDevId, uIova, fAccess,
3163 cbAccess, rc));
3164 return rc;
3165 }
3166
3167 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3168 *pGCPhysSpa = uIova;
3169 *pcbContiguous = cbAccess;
3170 return VINF_SUCCESS;
3171}
3172
3173
3174/**
3175 * Memory access bulk (one or more 4K pages) request from a device.
3176 *
3177 * @returns VBox status code.
3178 * @param pDevIns The IOMMU device instance.
3179 * @param uDevId The device ID (bus, device, function).
3180 * @param cIovas The number of addresses being accessed.
3181 * @param pauIovas The I/O virtual addresses for each page being accessed.
3182 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3183 * @param paGCPhysSpa Where to store the translated physical addresses.
3184 *
3185 * @thread Any.
3186 */
3187static DECLCALLBACK(int) iommuAmdDeviceMemBulkAccess(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas,
3188 uint64_t const *pauIovas, uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
3189{
3190 /* Validate. */
3191 AssertPtr(pDevIns);
3192 Assert(cIovas > 0);
3193 AssertPtr(pauIovas);
3194 AssertPtr(paGCPhysSpa);
3195 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3196
3197 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3198 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3199 if (Ctrl.n.u1IommuEn)
3200 {
3201 IOMMUOP enmOp;
3202 uint8_t fAccess;
3203 if (fFlags & PDMIOMMU_MEM_F_READ)
3204 {
3205 enmOp = IOMMUOP_MEM_READ;
3206 fAccess = IOMMU_IO_PERM_READ;
3207 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
3208 }
3209 else
3210 {
3211 Assert(fFlags & PDMIOMMU_MEM_F_WRITE);
3212 enmOp = IOMMUOP_MEM_WRITE;
3213 fAccess = IOMMU_IO_PERM_WRITE;
3214 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
3215 }
3216
3217#ifdef VBOX_STRICT
3218 static const char * const s_apszAccess[] = { "none", "read", "write" };
3219 Assert(fAccess > 0 && fAccess < RT_ELEMENTS(s_apszAccess));
3220 const char *pszAccess = s_apszAccess[fAccess];
3221 LogFlowFunc(("uDevId=%#x cIovas=%zu szAccess=%s\n", uDevId, cIovas, pszAccess));
3222#endif
3223
3224 /** @todo IOMMU: IOTLB cache lookup. */
3225
3226 /* Lookup each IOVA from the device table. */
3227 for (size_t i = 0; i < cIovas; i++)
3228 {
3229 size_t cbContig;
3230 int rc = iommuAmdDteLookup(pDevIns, uDevId, pauIovas[i], X86_PAGE_SIZE, fAccess, enmOp, &paGCPhysSpa[i], &cbContig);
3231 if (RT_SUCCESS(rc))
3232 { /* likely */ }
3233 else
3234 {
3235 LogFunc(("Failed! uDevId=%#x uIova=%#RX64 fAccess=%u rc=%Rrc\n", uDevId, pauIovas[i], fAccess, rc));
3236 return rc;
3237 }
3238 Assert(cbContig == X86_PAGE_SIZE);
3239 }
3240 }
3241 else
3242 {
3243 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3244 for (size_t i = 0; i < cIovas; i++)
3245 paGCPhysSpa[i] = pauIovas[i];
3246 }
3247
3248 return VINF_SUCCESS;
3249}
3250
3251
3252
3253/**
3254 * Reads an interrupt remapping table entry from guest memory given its DTE.
3255 *
3256 * @returns VBox status code.
3257 * @param pDevIns The IOMMU device instance.
3258 * @param uDevId The device ID.
3259 * @param pDte The device table entry.
3260 * @param GCPhysIn The source MSI address (used for reporting errors).
3261 * @param uDataIn The source MSI data.
3262 * @param enmOp The IOMMU operation being performed.
3263 * @param pIrte Where to store the interrupt remapping table entry.
3264 *
3265 * @thread Any.
3266 */
3267static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
3268 IOMMUOP enmOp, PIRTE_T pIrte)
3269{
3270 /* Ensure the IRTE length is valid. */
3271 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
3272
3273 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
3274 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
3275 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
3276 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
3277
3278 /* Ensure the IRTE falls completely within the interrupt table. */
3279 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
3280 { /* likely */ }
3281 else
3282 {
3283 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
3284 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
3285
3286 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3287 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
3288 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3289 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteAddrInvalid);
3290 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3291 }
3292
3293 /* Read the IRTE from memory. */
3294 Assert(!(GCPhysIrte & 3));
3295 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
3296 if (RT_SUCCESS(rc))
3297 return VINF_SUCCESS;
3298
3299 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
3300 * situation. Is it an I/O page fault or a device table hardware error?
3301 * There's no interrupt table hardware error event, but it's unclear what
3302 * we should do here. */
3303 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
3304 return VERR_IOMMU_IPE_4;
3305}
3306
3307
3308/**
3309 * Remaps the interrupt using the interrupt remapping table.
3310 *
3311 * @returns VBox status code.
3312 * @param pDevIns The IOMMU instance data.
3313 * @param uDevId The device ID.
3314 * @param pDte The device table entry.
3315 * @param enmOp The IOMMU operation being performed.
3316 * @param pMsiIn The source MSI.
3317 * @param pMsiOut Where to store the remapped MSI.
3318 *
3319 * @thread Any.
3320 */
3321static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
3322 PMSIMSG pMsiOut)
3323{
3324 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
3325
3326 IRTE_T Irte;
3327 int rc = iommuAmdIrteRead(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
3328 if (RT_SUCCESS(rc))
3329 {
3330 if (Irte.n.u1RemapEnable)
3331 {
3332 if (!Irte.n.u1GuestMode)
3333 {
3334 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
3335 {
3336 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
3337 *pMsiOut = *pMsiIn;
3338
3339 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
3340 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
3341
3342 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
3343 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
3344
3345 return VINF_SUCCESS;
3346 }
3347
3348 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3349 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3350 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3351 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3352 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdIntType);
3353 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3354 }
3355
3356 LogFunc(("Guest mode not supported -> IOPF\n"));
3357 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3358 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3359 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3360 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
3361 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3362 }
3363
3364 LogFunc(("Remapping disabled -> IOPF\n"));
3365 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3366 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3367 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3368 iommuAmdIoPageFaultEventRaise(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
3369 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3370 }
3371
3372 return rc;
3373}
3374
3375
3376/**
3377 * Looks up an MSI interrupt from the interrupt remapping table.
3378 *
3379 * @returns VBox status code.
3380 * @param pDevIns The IOMMU instance data.
3381 * @param uDevId The device ID.
3382 * @param enmOp The IOMMU operation being performed.
3383 * @param pMsiIn The source MSI.
3384 * @param pMsiOut Where to store the remapped MSI.
3385 *
3386 * @thread Any.
3387 */
3388static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3389{
3390 /* Read the device table entry from memory. */
3391 LogFlowFunc(("uDevId=%#x (%#x:%#x:%#x) enmOp=%u\n", uDevId,
3392 ((uDevId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
3393 ((uDevId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (uDevId & VBOX_PCI_DEVFN_FUN_MASK), enmOp));
3394
3395 DTE_T Dte;
3396 int rc = iommuAmdDteRead(pDevIns, uDevId, enmOp, &Dte);
3397 if (RT_SUCCESS(rc))
3398 {
3399 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
3400 if (Dte.n.u1IntrMapValid)
3401 {
3402 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
3403 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
3404 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
3405 if (RT_LIKELY( !fRsvd0
3406 && !fRsvd1))
3407 { /* likely */ }
3408 else
3409 {
3410 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
3411 fRsvd1));
3412 EVT_ILLEGAL_DTE_T Event;
3413 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3414 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3415 return VERR_IOMMU_INTR_REMAP_FAILED;
3416 }
3417
3418 /*
3419 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
3420 * that's connected through HyperTransport it might be possible; but for us, it
3421 * doesn't seem we need to specially handle these pins.
3422 */
3423
3424 /*
3425 * Validate the MSI source address.
3426 *
3427 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
3428 * CPU is concerned, the MSI region is fixed and we must ensure no other device
3429 * claims the region as I/O space.
3430 *
3431 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
3432 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
3433 * See Intel spec. 10.11.1 "Message Address Register Format".
3434 */
3435 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
3436 {
3437 /*
3438 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
3439 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
3440 */
3441 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
3442 bool fPassThru = false;
3443 switch (u8DeliveryMode)
3444 {
3445 case VBOX_MSI_DELIVERY_MODE_FIXED:
3446 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
3447 {
3448 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
3449 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
3450 {
3451 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
3452 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
3453 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
3454 {
3455 /*
3456 * We don't support guest interrupt remapping yet. When we do, we'll need to
3457 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
3458 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
3459 * already reads the control register, add that as a parameter when we eventually
3460 * support guest interrupt remapping. For now, just assert.
3461 */
3462 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3463 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
3464 NOREF(pThis);
3465
3466 return iommuAmdIntrRemap(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
3467 }
3468
3469 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
3470 EVT_ILLEGAL_DTE_T Event;
3471 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
3472 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
3473 return VERR_IOMMU_INTR_REMAP_FAILED;
3474 }
3475
3476 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
3477 {
3478 fPassThru = true;
3479 break;
3480 }
3481
3482 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
3483 {
3484 LogFunc(("IntCtl=0: Remapping disallowed for fixed/arbitrated interrupt (%#x) -> Target abort\n",
3485 pMsiIn->Data.n.u8Vector));
3486 iommuAmdSetPciTargetAbort(pDevIns);
3487 return VERR_IOMMU_INTR_REMAP_DENIED;
3488 }
3489
3490 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
3491 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
3492 EVT_ILLEGAL_DTE_T Event;
3493 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
3494 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
3495 return VERR_IOMMU_INTR_REMAP_FAILED;
3496 }
3497
3498 /* SMIs are passed through unmapped. We don't implement SMI filters. */
3499 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
3500 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
3501 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
3502 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
3503 default:
3504 {
3505 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
3506 iommuAmdSetPciTargetAbort(pDevIns);
3507 return VERR_IOMMU_INTR_REMAP_FAILED;
3508 }
3509 }
3510
3511 /*
3512 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
3513 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
3514 */
3515 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
3516 || !pMsiIn->Addr.n.u1DestMode)
3517 {
3518 if (fPassThru)
3519 {
3520 *pMsiOut = *pMsiIn;
3521 return VINF_SUCCESS;
3522 }
3523 LogFunc(("Remapping/passthru disallowed for interrupt %#x -> Target abort\n", pMsiIn->Data.n.u8Vector));
3524 }
3525 else
3526 LogFunc(("Logical destination mode invalid for delivery mode %#x\n -> Target abort\n", u8DeliveryMode));
3527
3528 iommuAmdSetPciTargetAbort(pDevIns);
3529 return VERR_IOMMU_INTR_REMAP_DENIED;
3530 }
3531 else
3532 {
3533 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
3534 return VERR_IOMMU_INTR_REMAP_FAILED;
3535 }
3536 }
3537 else
3538 {
3539 /** @todo IOMMU: Add to interrupt remapping cache. */
3540 LogFlowFunc(("DTE interrupt map not valid\n"));
3541 *pMsiOut = *pMsiIn;
3542 return VINF_SUCCESS;
3543 }
3544 }
3545
3546 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3547 return VERR_IOMMU_INTR_REMAP_FAILED;
3548}
3549
3550
3551/**
3552 * Interrupt remap request from a device.
3553 *
3554 * @returns VBox status code.
3555 * @param pDevIns The IOMMU device instance.
3556 * @param uDevId The device ID (bus, device, function).
3557 * @param pMsiIn The source MSI.
3558 * @param pMsiOut Where to store the remapped MSI.
3559 */
3560static DECLCALLBACK(int) iommuAmdDeviceMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3561{
3562 /* Validate. */
3563 Assert(pDevIns);
3564 Assert(pMsiIn);
3565 Assert(pMsiOut);
3566
3567 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3568
3569 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
3570 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3571 if (Ctrl.n.u1IommuEn)
3572 {
3573 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
3574 /** @todo Cache? */
3575
3576 return iommuAmdIntrTableLookup(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
3577 }
3578
3579 *pMsiOut = *pMsiIn;
3580 return VINF_SUCCESS;
3581}
3582
3583
3584/**
3585 * @callback_method_impl{FNIOMMMIONEWWRITE}
3586 */
3587static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
3588{
3589 NOREF(pvUser);
3590 Assert(cb == 4 || cb == 8);
3591 Assert(!(off & (cb - 1)));
3592
3593 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3594 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
3595
3596 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
3597 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
3598}
3599
3600
3601/**
3602 * @callback_method_impl{FNIOMMMIONEWREAD}
3603 */
3604static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3605{
3606 NOREF(pvUser);
3607 Assert(cb == 4 || cb == 8);
3608 Assert(!(off & (cb - 1)));
3609
3610 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3611 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
3612
3613 uint64_t uResult;
3614 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
3615 if (cb == 8)
3616 *(uint64_t *)pv = uResult;
3617 else
3618 *(uint32_t *)pv = (uint32_t)uResult;
3619
3620 return rcStrict;
3621}
3622
3623
3624#ifdef IN_RING3
3625/**
3626 * Processes an IOMMU command.
3627 *
3628 * @returns VBox status code.
3629 * @param pDevIns The IOMMU device instance.
3630 * @param pCmd The command to process.
3631 * @param GCPhysCmd The system physical address of the command.
3632 * @param pEvtError Where to store the error event in case of failures.
3633 *
3634 * @thread Command thread.
3635 */
3636static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
3637{
3638 IOMMU_ASSERT_NOT_LOCKED(pDevIns);
3639
3640 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3641 STAM_COUNTER_INC(&pThis->StatCmd);
3642
3643 uint8_t const bCmd = pCmd->n.u4Opcode;
3644 switch (bCmd)
3645 {
3646 case IOMMU_CMD_COMPLETION_WAIT:
3647 {
3648 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
3649
3650 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
3651 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
3652
3653 /* Validate reserved bits in the command. */
3654 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
3655 {
3656 /* If Completion Store is requested, write the StoreData to the specified address. */
3657 if (pCmdComWait->n.u1Store)
3658 {
3659 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
3660 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
3661 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
3662 if (RT_FAILURE(rc))
3663 {
3664 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
3665 GCPhysStore, rc));
3666 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
3667 return VERR_IOMMU_CMD_HW_ERROR;
3668 }
3669 }
3670
3671 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
3672 if (pCmdComWait->n.u1Interrupt)
3673 {
3674 IOMMU_LOCK(pDevIns);
3675 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
3676 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3677 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
3678 IOMMU_UNLOCK(pDevIns);
3679
3680 if (fRaiseInt)
3681 iommuAmdMsiInterruptRaise(pDevIns);
3682 }
3683 return VINF_SUCCESS;
3684 }
3685 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3686 return VERR_IOMMU_CMD_INVALID_FORMAT;
3687 }
3688
3689 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
3690 {
3691 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3692 * then. */
3693 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
3694 return VINF_SUCCESS;
3695 }
3696
3697 case IOMMU_CMD_INV_IOMMU_PAGES:
3698 {
3699 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
3700#ifdef IOMMU_WITH_IOTLBE_CACHE
3701 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
3702 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
3703
3704 /* Validate reserved bits in the command. */
3705 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
3706 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
3707 {
3708 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
3709 uint16_t const uDomainId = pCmdInvPages->n.u16DomainId;
3710 uint8_t cShift;
3711 if (!pCmdInvPages->n.u1Size)
3712 cShift = X86_PAGE_4K_SHIFT;
3713 else
3714 {
3715 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
3716 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
3717 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
3718 }
3719
3720 IOMMU_LOCK(pDevIns);
3721 iommuAmdIotlbRemoveRange(pThis, uDomainId, uIova, cShift);
3722 IOMMU_UNLOCK(pDevIns);
3723 return VINF_SUCCESS;
3724 }
3725 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3726 return VERR_IOMMU_CMD_INVALID_FORMAT;
3727#else
3728 return VINF_SUCCESS;
3729#endif
3730 }
3731
3732 case IOMMU_CMD_INV_IOTLB_PAGES:
3733 {
3734 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
3735
3736 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
3737 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
3738 {
3739 /** @todo IOMMU: Implement remote IOTLB invalidation. */
3740 return VERR_NOT_IMPLEMENTED;
3741 }
3742 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3743 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3744 }
3745
3746 case IOMMU_CMD_INV_INTR_TABLE:
3747 {
3748 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
3749 * then. */
3750 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
3751 return VINF_SUCCESS;
3752 }
3753
3754 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
3755 {
3756 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
3757 if (pThis->ExtFeat.n.u1PrefetchSup)
3758 {
3759 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
3760 return VINF_SUCCESS;
3761 }
3762 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3763 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3764 }
3765
3766 case IOMMU_CMD_COMPLETE_PPR_REQ:
3767 {
3768 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
3769
3770 /* We don't support PPR requests yet. */
3771 Assert(!pThis->ExtFeat.n.u1PprSup);
3772 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3773 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3774 }
3775
3776 case IOMMU_CMD_INV_IOMMU_ALL:
3777 {
3778 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
3779
3780 if (pThis->ExtFeat.n.u1InvAllSup)
3781 {
3782 /** @todo IOMMU: Invalidate all. Pretend success until then. */
3783 return VINF_SUCCESS;
3784 }
3785 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3786 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3787 }
3788 }
3789
3790 STAM_COUNTER_DEC(&pThis->StatCmd);
3791 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
3792 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
3793 return VERR_IOMMU_CMD_NOT_SUPPORTED;
3794}
3795
3796
3797/**
3798 * The IOMMU command thread.
3799 *
3800 * @returns VBox status code.
3801 * @param pDevIns The IOMMU device instance.
3802 * @param pThread The command thread.
3803 */
3804static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3805{
3806 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3807
3808 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3809 return VINF_SUCCESS;
3810
3811 /*
3812 * Pre-allocate the maximum command buffer size supported by the IOMMU.
3813 * This avoid trashing the heap as well as not wasting time allocating
3814 * and freeing buffers while processing commands.
3815 */
3816 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
3817 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
3818 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
3819
3820 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3821 {
3822 /*
3823 * Sleep perpetually until we are woken up to process commands.
3824 */
3825 {
3826 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
3827 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
3828 if (!fSignaled)
3829 {
3830 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
3831 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
3832 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3833 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3834 break;
3835 Log4Func(("Woken up with rc=%Rrc\n", rc));
3836 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
3837 }
3838 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
3839 }
3840
3841 /*
3842 * Fetch and process IOMMU commands.
3843 */
3844 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
3845 * temporary host buffer before processing them as a batch. If we want to
3846 * save on host memory a bit, we could (once PGM has the necessary APIs)
3847 * lock the page mappings page mappings and access them directly. */
3848 IOMMU_LOCK(pDevIns);
3849
3850 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
3851 if (Status.n.u1CmdBufRunning)
3852 {
3853 /* Get the offsets we need to read commands from memory (circular buffer offset). */
3854 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
3855 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
3856 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
3857
3858 /* Validate. */
3859 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
3860 Assert(offHead < cbCmdBuf);
3861 Assert(cbCmdBuf <= cbMaxCmdBuf);
3862
3863 if (offHead != offTail)
3864 {
3865 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
3866 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
3867 int rc = PDMDevHlpPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
3868 if (RT_SUCCESS(rc))
3869 {
3870 /* Indicate to software we've fetched all commands from the buffer. */
3871 pThis->CmdBufHeadPtr.n.off = offTail;
3872
3873 /* Allow IOMMU to do other work while we process commands. */
3874 IOMMU_UNLOCK(pDevIns);
3875
3876 /* Process the fetched commands. */
3877 EVT_GENERIC_T EvtError;
3878 do
3879 {
3880 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
3881 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
3882 if (RT_FAILURE(rc))
3883 {
3884 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
3885 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
3886 {
3887 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
3888 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
3889 }
3890 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
3891 {
3892 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3893 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
3894 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
3895 }
3896 break;
3897 }
3898
3899 /* Move to the next command in the circular buffer. */
3900 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
3901 } while (offHead != offTail);
3902 }
3903 else
3904 {
3905 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
3906 EVT_CMD_HW_ERR_T EvtCmdHwErr;
3907 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
3908 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
3909
3910 IOMMU_UNLOCK(pDevIns);
3911 }
3912 }
3913 else
3914 IOMMU_UNLOCK(pDevIns);
3915 }
3916 else
3917 IOMMU_UNLOCK(pDevIns);
3918 }
3919
3920 RTMemFree(pvCmds);
3921 LogFlowFunc(("Command thread terminating\n"));
3922 return VINF_SUCCESS;
3923}
3924
3925
3926/**
3927 * Wakes up the command thread so it can respond to a state change.
3928 *
3929 * @returns VBox status code.
3930 * @param pDevIns The IOMMU device instance.
3931 * @param pThread The command thread.
3932 */
3933static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3934{
3935 RT_NOREF(pThread);
3936 LogFlowFunc(("\n"));
3937 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3938 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
3939}
3940
3941
3942/**
3943 * @callback_method_impl{FNPCICONFIGREAD}
3944 */
3945static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3946 unsigned cb, uint32_t *pu32Value)
3947{
3948 /** @todo IOMMU: PCI config read stat counter. */
3949 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
3950 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
3951 return rcStrict;
3952}
3953
3954
3955/**
3956 * @callback_method_impl{FNPCICONFIGWRITE}
3957 */
3958static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
3959 unsigned cb, uint32_t u32Value)
3960{
3961 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3962
3963 /*
3964 * Discard writes to read-only registers that are specific to the IOMMU.
3965 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
3966 * See PCI spec. 6.1. "Configuration Space Organization".
3967 */
3968 switch (uAddress)
3969 {
3970 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
3971 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
3972 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
3973 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
3974 {
3975 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
3976 return VINF_SUCCESS;
3977 }
3978 }
3979
3980 IOMMU_LOCK(pDevIns);
3981
3982 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
3983 switch (uAddress)
3984 {
3985 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
3986 {
3987 if (pThis->IommuBar.n.u1Enable)
3988 {
3989 rcStrict = VINF_SUCCESS;
3990 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
3991 break;
3992 }
3993
3994 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
3995 if (pThis->IommuBar.n.u1Enable)
3996 {
3997 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
3998 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
3999 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
4000 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
4001
4002 /* If the MMIO region is already mapped at the specified address, we're done. */
4003 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
4004 if (GCPhysMmioBasePrev == GCPhysMmioBase)
4005 {
4006 rcStrict = VINF_SUCCESS;
4007 break;
4008 }
4009
4010 /* Unmap the previous MMIO region (which is at a different address). */
4011 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
4012 {
4013 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
4014 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
4015 if (RT_FAILURE(rcStrict))
4016 {
4017 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4018 break;
4019 }
4020 }
4021
4022 /* Map the newly specified MMIO region. */
4023 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
4024 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
4025 if (RT_FAILURE(rcStrict))
4026 {
4027 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4028 break;
4029 }
4030 }
4031 else
4032 rcStrict = VINF_SUCCESS;
4033 break;
4034 }
4035
4036 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
4037 {
4038 if (!pThis->IommuBar.n.u1Enable)
4039 pThis->IommuBar.au32[1] = u32Value;
4040 else
4041 {
4042 rcStrict = VINF_SUCCESS;
4043 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
4044 }
4045 break;
4046 }
4047
4048 case IOMMU_PCI_OFF_MSI_CAP_HDR:
4049 {
4050 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
4051 RT_FALL_THRU();
4052 }
4053 default:
4054 {
4055 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4056 break;
4057 }
4058 }
4059
4060 IOMMU_UNLOCK(pDevIns);
4061
4062 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
4063 return rcStrict;
4064}
4065
4066
4067/**
4068 * @callback_method_impl{FNDBGFHANDLERDEV}
4069 */
4070static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4071{
4072 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4073 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4074 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4075
4076 bool fVerbose;
4077 if ( pszArgs
4078 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
4079 fVerbose = true;
4080 else
4081 fVerbose = false;
4082
4083 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
4084 /* Device Table Base Addresses (all segments). */
4085 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4086 {
4087 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
4088 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
4089 if (fVerbose)
4090 {
4091 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
4092 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
4093 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
4094 }
4095 }
4096 /* Command Buffer Base Address Register. */
4097 {
4098 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
4099 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
4100 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4101 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4102 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
4103 if (fVerbose)
4104 {
4105 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
4106 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4107 cEntries, cbBuffer);
4108 }
4109 }
4110 /* Event Log Base Address Register. */
4111 {
4112 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
4113 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
4114 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4115 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4116 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
4117 if (fVerbose)
4118 {
4119 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4120 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4121 cEntries, cbBuffer);
4122 }
4123 }
4124 /* IOMMU Control Register. */
4125 {
4126 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
4127 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
4128 if (fVerbose)
4129 {
4130 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
4131 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
4132 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
4133 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4134 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4135 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
4136 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
4137 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
4138 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
4139 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
4140 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
4141 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
4142 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
4143 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
4144 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
4145 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
4146 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
4147 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
4148 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
4149 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
4150 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
4151 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
4152 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
4153 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
4154 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
4155 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
4156 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
4157 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
4158 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
4159 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
4160 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
4161 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
4162 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
4163 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
4164 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
4165 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
4166 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
4167 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
4168 }
4169 }
4170 /* Exclusion Base Address Register. */
4171 {
4172 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
4173 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
4174 if (fVerbose)
4175 {
4176 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
4177 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
4178 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
4179 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
4180 }
4181 }
4182 /* Exclusion Range Limit Register. */
4183 {
4184 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
4185 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
4186 if (fVerbose)
4187 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n", ExclRangeLimit.n.u52ExclLimit);
4188 }
4189 /* Extended Feature Register. */
4190 {
4191 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
4192 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
4193 if (fVerbose)
4194 {
4195 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
4196 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
4197 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
4198 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
4199 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
4200 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
4201 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
4202 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
4203 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
4204 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
4205 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
4206 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
4207 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
4208 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
4209 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
4210 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
4211 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
4212 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
4213 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
4214 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
4215 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
4216 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
4217 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
4218 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
4219 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
4220 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
4221 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
4222 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
4223 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
4224 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
4225 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
4226 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
4227 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
4228 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
4229 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
4230 }
4231 }
4232 /* PPR Log Base Address Register. */
4233 {
4234 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
4235 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
4236 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4237 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4238 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
4239 if (fVerbose)
4240 {
4241 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4242 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4243 cEntries, cbBuffer);
4244 }
4245 }
4246 /* Hardware Event (Hi) Register. */
4247 {
4248 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4249 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4250 if (fVerbose)
4251 {
4252 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4253 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4254 }
4255 }
4256 /* Hardware Event (Lo) Register. */
4257 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4258 /* Hardware Event Status. */
4259 {
4260 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4261 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4262 if (fVerbose)
4263 {
4264 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4265 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4266 }
4267 }
4268 /* Guest Virtual-APIC Log Base Address Register. */
4269 {
4270 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4271 uint8_t const uEncodedLen = GALogBar.n.u4Len;
4272 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4273 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4274 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4275 if (fVerbose)
4276 {
4277 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4278 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4279 cEntries, cbBuffer);
4280 }
4281 }
4282 /* Guest Virtual-APIC Log Tail Address Register. */
4283 {
4284 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4285 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4286 if (fVerbose)
4287 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4288 }
4289 /* PPR Log B Base Address Register. */
4290 {
4291 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4292 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4293 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4294 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4295 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4296 if (fVerbose)
4297 {
4298 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4299 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4300 cEntries, cbBuffer);
4301 }
4302 }
4303 /* Event Log B Base Address Register. */
4304 {
4305 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
4306 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
4307 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4308 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4309 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
4310 if (fVerbose)
4311 {
4312 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
4313 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4314 cEntries, cbBuffer);
4315 }
4316 }
4317 /* Device-Specific Feature Extension Register. */
4318 {
4319 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
4320 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
4321 if (fVerbose)
4322 {
4323 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
4324 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
4325 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
4326 }
4327 }
4328 /* Device-Specific Control Extension Register. */
4329 {
4330 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
4331 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
4332 if (fVerbose)
4333 {
4334 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
4335 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
4336 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
4337 }
4338 }
4339 /* Device-Specific Status Extension Register. */
4340 {
4341 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
4342 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
4343 if (fVerbose)
4344 {
4345 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
4346 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
4347 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
4348 }
4349 }
4350 /* Miscellaneous Information Register (Lo and Hi). */
4351 {
4352 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
4353 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
4354 if (fVerbose)
4355 {
4356 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
4357 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
4358 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
4359 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
4360 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
4361 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
4362 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
4363 }
4364 }
4365 /* MSI Capability Header. */
4366 {
4367 MSI_CAP_HDR_T MsiCapHdr;
4368 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
4369 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
4370 if (fVerbose)
4371 {
4372 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
4373 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
4374 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
4375 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
4376 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
4377 }
4378 }
4379 /* MSI Address Register (Lo and Hi). */
4380 {
4381 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
4382 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
4383 MSIADDR MsiAddr;
4384 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
4385 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
4386 if (fVerbose)
4387 {
4388 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
4389 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
4390 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
4391 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
4392 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
4393 }
4394 }
4395 /* MSI Data. */
4396 {
4397 MSIDATA MsiData;
4398 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
4399 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
4400 if (fVerbose)
4401 {
4402 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
4403 MsiData.n.u8Vector);
4404 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
4405 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
4406 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
4407 "level" : "edge");
4408 }
4409 }
4410 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
4411 {
4412 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
4413 MsiMapCapHdr.u32 = 0;
4414 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
4415 if (fVerbose)
4416 {
4417 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
4418 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
4419 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
4420 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
4421 }
4422 }
4423 /* Performance Optimization Control Register. */
4424 {
4425 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
4426 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
4427 if (fVerbose)
4428 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
4429 }
4430 /* XT (x2APIC) General Interrupt Control Register. */
4431 {
4432 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
4433 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
4434 if (fVerbose)
4435 {
4436 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4437 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4438 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4439 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
4440 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
4441 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4442 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4443 }
4444 }
4445 /* XT (x2APIC) PPR Interrupt Control Register. */
4446 {
4447 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
4448 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
4449 if (fVerbose)
4450 {
4451 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4452 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4453 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4454 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
4455 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
4456 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4457 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4458 }
4459 }
4460 /* XT (X2APIC) GA Log Interrupt Control Register. */
4461 {
4462 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
4463 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
4464 if (fVerbose)
4465 {
4466 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
4467 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
4468 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
4469 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
4470 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
4471 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
4472 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
4473 }
4474 }
4475 /* MARC Registers. */
4476 {
4477 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
4478 {
4479 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
4480 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
4481 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
4482
4483 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
4484 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
4485 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
4486 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
4487
4488 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
4489 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
4490 }
4491 }
4492 /* Reserved Register. */
4493 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
4494 /* Command Buffer Head Pointer Register. */
4495 {
4496 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
4497 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
4498 CmdBufHeadPtr.n.off);
4499 }
4500 /* Command Buffer Tail Pointer Register. */
4501 {
4502 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
4503 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
4504 CmdBufTailPtr.n.off);
4505 }
4506 /* Event Log Head Pointer Register. */
4507 {
4508 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
4509 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
4510 EvtLogHeadPtr.n.off);
4511 }
4512 /* Event Log Tail Pointer Register. */
4513 {
4514 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
4515 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
4516 EvtLogTailPtr.n.off);
4517 }
4518 /* Status Register. */
4519 {
4520 IOMMU_STATUS_T const Status = pThis->Status;
4521 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
4522 if (fVerbose)
4523 {
4524 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
4525 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
4526 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
4527 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
4528 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
4529 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
4530 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
4531 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
4532 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
4533 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
4534 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
4535 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
4536 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
4537 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
4538 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
4539 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
4540 }
4541 }
4542 /* PPR Log Head Pointer. */
4543 {
4544 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
4545 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
4546 PprLogHeadPtr.n.off);
4547 }
4548 /* PPR Log Tail Pointer. */
4549 {
4550 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
4551 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
4552 PprLogTailPtr.n.off);
4553 }
4554 /* Guest Virtual-APIC Log Head Pointer. */
4555 {
4556 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
4557 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
4558 GALogHeadPtr.n.u12GALogPtr);
4559 }
4560 /* Guest Virtual-APIC Log Tail Pointer. */
4561 {
4562 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
4563 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
4564 GALogTailPtr.n.u12GALogPtr);
4565 }
4566 /* PPR Log B Head Pointer. */
4567 {
4568 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
4569 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
4570 PprLogBHeadPtr.n.off);
4571 }
4572 /* PPR Log B Tail Pointer. */
4573 {
4574 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
4575 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
4576 PprLogBTailPtr.n.off);
4577 }
4578 /* Event Log B Head Pointer. */
4579 {
4580 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
4581 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
4582 EvtLogBHeadPtr.n.off);
4583 }
4584 /* Event Log B Tail Pointer. */
4585 {
4586 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
4587 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
4588 EvtLogBTailPtr.n.off);
4589 }
4590 /* PPR Log Auto Response Register. */
4591 {
4592 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
4593 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
4594 if (fVerbose)
4595 {
4596 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
4597 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
4598 }
4599 }
4600 /* PPR Log Overflow Early Warning Indicator Register. */
4601 {
4602 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
4603 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
4604 if (fVerbose)
4605 {
4606 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
4607 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
4608 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
4609 }
4610 }
4611 /* PPR Log Overflow Early Warning Indicator Register. */
4612 {
4613 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
4614 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
4615 if (fVerbose)
4616 {
4617 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
4618 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
4619 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
4620 }
4621 }
4622}
4623
4624
4625/**
4626 * Dumps the DTE via the info callback helper.
4627 *
4628 * @param pHlp The info helper.
4629 * @param pDte The device table entry.
4630 * @param pszPrefix The string prefix.
4631 */
4632static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
4633{
4634 AssertReturnVoid(pHlp);
4635 AssertReturnVoid(pDte);
4636 AssertReturnVoid(pszPrefix);
4637
4638 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
4639 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
4640 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
4641 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
4642 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
4643 pDte->n.u40PageTableRootPtrLo << 12);
4644 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
4645 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
4646 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
4647 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
4648 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
4649 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
4650 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
4651 (pDte->n.u21GstCr3TableRootPtrHi << 31)
4652 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
4653 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
4654 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
4655 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
4656 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
4657 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
4658 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
4659 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
4660 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
4661 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
4662 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
4663 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
4664 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
4665 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
4666 pHlp->pfnPrintf(pHlp, "\n");
4667
4668 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
4669 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
4670 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4671 {
4672 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
4673 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
4674 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
4675 cbIntrTable);
4676 }
4677 else
4678 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
4679 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
4680 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
4681 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
4682 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
4683 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
4684 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
4685 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
4686 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
4687 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
4688 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
4689 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
4690 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
4691 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
4692 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
4693 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
4694 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
4695}
4696
4697
4698/**
4699 * @callback_method_impl{FNDBGFHANDLERDEV}
4700 */
4701static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4702{
4703 if (pszArgs)
4704 {
4705 uint16_t uDevId = 0;
4706 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
4707 if (RT_SUCCESS(rc))
4708 {
4709 DTE_T Dte;
4710 rc = iommuAmdDteRead(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
4711 if (RT_SUCCESS(rc))
4712 {
4713 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", uDevId);
4714 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
4715 return;
4716 }
4717
4718 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
4719 }
4720 else
4721 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
4722 }
4723 else
4724 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
4725}
4726
4727
4728#if 0
4729/**
4730 * @callback_method_impl{FNDBGFHANDLERDEV}
4731 */
4732static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4733{
4734 RT_NOREF(pszArgs);
4735
4736 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4737 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4738 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4739
4740 uint8_t cTables = 0;
4741 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4742 {
4743 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4744 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4745 if (GCPhysDevTab)
4746 ++cTables;
4747 }
4748
4749 pHlp->pfnPrintf(pHlp, "AMD-IOMMU Device Tables:\n");
4750 pHlp->pfnPrintf(pHlp, " Tables active: %u\n", cTables);
4751 if (!cTables)
4752 return;
4753
4754 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4755 {
4756 DEV_TAB_BAR_T DevTabBar = pThis->aDevTabBaseAddrs[i];
4757 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
4758 if (GCPhysDevTab)
4759 {
4760 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
4761 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
4762 pHlp->pfnPrintf(pHlp, " Table %u (base=%#RGp size=%u bytes entries=%u):\n", i, GCPhysDevTab, cbDevTab, cDtes);
4763
4764 void *pvDevTab = RTMemAllocZ(cbDevTab);
4765 if (RT_LIKELY(pvDevTab))
4766 {
4767 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
4768 if (RT_SUCCESS(rc))
4769 {
4770 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
4771 {
4772 PCDTE_T pDte = (PCDTE_T)((char *)pvDevTab + idxDte * sizeof(DTE_T));
4773 if ( pDte->n.u1Valid
4774 || pDte->n.u1IntrMapValid)
4775 {
4776 pHlp->pfnPrintf(pHlp, " DTE %u:\n", idxDte);
4777 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
4778 }
4779 }
4780 pHlp->pfnPrintf(pHlp, "\n");
4781 }
4782 else
4783 {
4784 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %u bytes. rc=%Rrc!\n", GCPhysDevTab,
4785 cbDevTab, rc);
4786 }
4787
4788 RTMemFree(pvDevTab);
4789 }
4790 else
4791 {
4792 pHlp->pfnPrintf(pHlp, " Allocating %u bytes for reading the device table failed!\n", cbDevTab);
4793 return;
4794 }
4795 }
4796 }
4797}
4798#endif
4799
4800
4801/**
4802 * @callback_method_impl{FNSSMDEVSAVEEXEC}
4803 */
4804static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4805{
4806 /** @todo IOMMU: Save state. */
4807 RT_NOREF2(pDevIns, pSSM);
4808 LogFlowFunc(("\n"));
4809 return VERR_NOT_IMPLEMENTED;
4810}
4811
4812
4813/**
4814 * @callback_method_impl{FNSSMDEVLOADEXEC}
4815 */
4816static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4817{
4818 /** @todo IOMMU: Load state. */
4819 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
4820 LogFlowFunc(("\n"));
4821 return VERR_NOT_IMPLEMENTED;
4822}
4823
4824
4825/**
4826 * @interface_method_impl{PDMDEVREG,pfnReset}
4827 */
4828static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
4829{
4830 /*
4831 * Resets read-write portion of the IOMMU state.
4832 *
4833 * NOTE! State not initialized here is expected to be initialized during
4834 * device construction and remain read-only through the lifetime of the VM.
4835 */
4836 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4837 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4838 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4839
4840 IOMMU_LOCK_NORET(pDevIns);
4841
4842 LogFlowFunc(("\n"));
4843
4844 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
4845
4846 pThis->CmdBufBaseAddr.u64 = 0;
4847 pThis->CmdBufBaseAddr.n.u4Len = 8;
4848
4849 pThis->EvtLogBaseAddr.u64 = 0;
4850 pThis->EvtLogBaseAddr.n.u4Len = 8;
4851
4852 pThis->Ctrl.u64 = 0;
4853 pThis->Ctrl.n.u1Coherent = 1;
4854 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
4855
4856 pThis->ExclRangeBaseAddr.u64 = 0;
4857 pThis->ExclRangeLimit.u64 = 0;
4858
4859 pThis->PprLogBaseAddr.u64 = 0;
4860 pThis->PprLogBaseAddr.n.u4Len = 8;
4861
4862 pThis->HwEvtHi.u64 = 0;
4863 pThis->HwEvtLo = 0;
4864 pThis->HwEvtStatus.u64 = 0;
4865
4866 pThis->GALogBaseAddr.u64 = 0;
4867 pThis->GALogBaseAddr.n.u4Len = 8;
4868 pThis->GALogTailAddr.u64 = 0;
4869
4870 pThis->PprLogBBaseAddr.u64 = 0;
4871 pThis->PprLogBBaseAddr.n.u4Len = 8;
4872
4873 pThis->EvtLogBBaseAddr.u64 = 0;
4874 pThis->EvtLogBBaseAddr.n.u4Len = 8;
4875
4876 pThis->PerfOptCtrl.u32 = 0;
4877
4878 pThis->XtGenIntrCtrl.u64 = 0;
4879 pThis->XtPprIntrCtrl.u64 = 0;
4880 pThis->XtGALogIntrCtrl.u64 = 0;
4881
4882 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
4883
4884 pThis->CmdBufHeadPtr.u64 = 0;
4885 pThis->CmdBufTailPtr.u64 = 0;
4886 pThis->EvtLogHeadPtr.u64 = 0;
4887 pThis->EvtLogTailPtr.u64 = 0;
4888
4889 pThis->Status.u64 = 0;
4890
4891 pThis->PprLogHeadPtr.u64 = 0;
4892 pThis->PprLogTailPtr.u64 = 0;
4893
4894 pThis->GALogHeadPtr.u64 = 0;
4895 pThis->GALogTailPtr.u64 = 0;
4896
4897 pThis->PprLogBHeadPtr.u64 = 0;
4898 pThis->PprLogBTailPtr.u64 = 0;
4899
4900 pThis->EvtLogBHeadPtr.u64 = 0;
4901 pThis->EvtLogBTailPtr.u64 = 0;
4902
4903 pThis->PprLogAutoResp.u64 = 0;
4904 pThis->PprLogOverflowEarly.u64 = 0;
4905 pThis->PprLogBOverflowEarly.u64 = 0;
4906
4907 pThis->IommuBar.u64 = 0;
4908 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
4909 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
4910
4911 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
4912
4913 IOMMU_UNLOCK(pDevIns);
4914}
4915
4916
4917/**
4918 * @interface_method_impl{PDMDEVREG,pfnDestruct}
4919 */
4920static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
4921{
4922 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
4923 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4924 LogFlowFunc(("\n"));
4925
4926 /* Close the command thread semaphore. */
4927 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
4928 {
4929 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
4930 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
4931 }
4932
4933#ifdef IOMMU_WITH_IOTLBE_CACHE
4934 /* Destroy level 1 cache. */
4935 if (pThis->paDomainIds)
4936 {
4937 PDMDevHlpMMHeapFree(pDevIns, pThis->paDomainIds);
4938 pThis->paDomainIds = NULL;
4939 }
4940
4941 /* Destroy level 2 cache. */
4942 if (pThis->paIotlbes)
4943 {
4944 iommuAmdIotlbRemoveAll(pThis);
4945 PDMDevHlpMMHeapFree(pDevIns, pThis->paIotlbes);
4946 pThis->paIotlbes = NULL;
4947 }
4948#endif
4949
4950 return VINF_SUCCESS;
4951}
4952
4953
4954/**
4955 * @interface_method_impl{PDMDEVREG,pfnConstruct}
4956 */
4957static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4958{
4959 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4960 RT_NOREF(pCfg);
4961
4962 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4963 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4964 pThis->u32Magic = IOMMU_MAGIC;
4965 pThisCC->pDevInsR3 = pDevIns;
4966
4967 LogFlowFunc(("iInstance=%d\n", iInstance));
4968
4969 /*
4970 * Register the IOMMU with PDM.
4971 */
4972 PDMIOMMUREGR3 IommuReg;
4973 RT_ZERO(IommuReg);
4974 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4975 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
4976 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
4977 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
4978 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4979 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4980 if (RT_FAILURE(rc))
4981 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4982 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4983 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4984 N_("IOMMU helper version mismatch; got %#x expected %#x"),
4985 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4986 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4987 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4988 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4989 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4990
4991 /*
4992 * Initialize read-only PCI configuration space.
4993 */
4994 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4995 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4996
4997 /* Header. */
4998 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
4999 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
5000 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
5001 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
5002 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
5003 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
5004 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
5005 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
5006 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
5007 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
5008 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
5009 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
5010 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
5011 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
5012
5013 /* Capability Header. */
5014 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
5015 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
5016 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
5017 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
5018 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
5019 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
5020 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
5021 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
5022 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
5023 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
5024 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
5025
5026 /* Base Address Register. */
5027 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
5028 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
5029
5030 /* IOMMU Range Register. */
5031 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
5032
5033 /* Misc. Information Register. */
5034 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
5035 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
5036 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
5037 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
5038 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
5039 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
5040 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
5041 uint32_t const uMiscInfoReg1 = 0;
5042 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
5043 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
5044
5045 /* MSI Capability Header register. */
5046 PDMMSIREG MsiReg;
5047 RT_ZERO(MsiReg);
5048 MsiReg.cMsiVectors = 1;
5049 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
5050 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
5051 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
5052
5053 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
5054#if 0
5055 /* MSI Address Lo. */
5056 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
5057 /* MSI Address Hi. */
5058 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
5059 /* MSI Data. */
5060 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
5061#endif
5062
5063#if 0
5064 /** @todo IOMMU: I don't know if we need to support this, enable later if
5065 * required. */
5066 /* MSI Mapping Capability Header register. */
5067 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
5068 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
5069 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
5070 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
5071 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
5072 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
5073 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
5074#endif
5075
5076 /*
5077 * Register the PCI function with PDM.
5078 */
5079 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
5080 AssertLogRelRCReturn(rc, rc);
5081
5082 /*
5083 * Register MSI support for the PCI device.
5084 * This must be done -after- register it as a PCI device!
5085 */
5086 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5087 AssertRCReturn(rc, rc);
5088
5089 /*
5090 * Intercept PCI config. space accesses.
5091 */
5092 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
5093 AssertLogRelRCReturn(rc, rc);
5094
5095 /*
5096 * Create the MMIO region.
5097 * Mapping of the region is done when software configures it via PCI config space.
5098 */
5099 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
5100 NULL /* pvUser */,
5101 IOMMMIO_FLAGS_READ_DWORD_QWORD
5102 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
5103 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
5104 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
5105 "AMD-IOMMU", &pThis->hMmio);
5106 AssertLogRelRCReturn(rc, rc);
5107
5108 /*
5109 * Register saved state.
5110 */
5111 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
5112 NULL, NULL, NULL,
5113 NULL, iommuAmdR3SaveExec, NULL,
5114 NULL, iommuAmdR3LoadExec, NULL);
5115 AssertLogRelRCReturn(rc, rc);
5116
5117 /*
5118 * Register debugger info items.
5119 */
5120 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
5121 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
5122#if 0
5123 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
5124#endif
5125
5126# ifdef VBOX_WITH_STATISTICS
5127 /*
5128 * Statistics.
5129 */
5130 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
5131 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
5132
5133 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
5134 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
5135
5136 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
5137 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
5138
5139 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
5140 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
5141
5142 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
5143 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
5144
5145 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
5146 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
5147
5148 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
5149 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
5150
5151 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
5152 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
5153 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
5154 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
5155 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
5156 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
5157 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
5158 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
5159 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
5160
5161 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDteLookupNonContig, STAMTYPE_COUNTER, "DteLookupNonContig", STAMUNIT_OCCURENCES, "Number of non-contiguous translated regions.");
5162
5163 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDteLookup, STAMTYPE_PROFILE, "DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling device table entry lookup (uncached).");
5164# endif
5165
5166 /*
5167 * Create the command thread and its event semaphore.
5168 */
5169 char szDevIommu[64];
5170 RT_ZERO(szDevIommu);
5171 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
5172 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5173 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
5174 AssertLogRelRCReturn(rc, rc);
5175
5176 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5177 AssertLogRelRCReturn(rc, rc);
5178
5179#ifdef IOMMU_WITH_IOTLBE_CACHE
5180 /*
5181 * Allocate the level 1 cache (device ID to domain ID mapping).
5182 * PCI devices are hotpluggable, plus we don't have a way of querying the bus for all
5183 * assigned PCI BDF slots. So while this wastes some memory, it should work regardless
5184 * of how code, features and devices around the IOMMU changes.
5185 */
5186 size_t const cbDomains = sizeof(IODOMAIN) * UINT16_MAX;
5187 pThis->paDomainIds = (PIODOMAIN)PDMDevHlpMMHeapAllocZ(pDevIns, cbDomains);
5188 if (!pThis->paDomainIds)
5189 {
5190 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
5191 N_("Failed to allocate %zu bytes from the hyperheap for the IOMMU level 1 cache."),
5192 cbDomains);
5193 }
5194
5195 /*
5196 * Allocate the level 2 cache (IOTLB entries).
5197 * This is allocated upfront since we expect a relatively small number of entries,
5198 * is more cache-line efficient and easier to track least recently used entries for
5199 * eviction when the cache is full. This also prevents unpredictable behavior during
5200 * the lifetime of the VM if the hyperheap gets full as allocation would fail upfront
5201 * or not at all.
5202 */
5203 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
5204 pThis->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
5205 if (!pThis->paIotlbes)
5206 {
5207 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
5208 N_("Failed to allocate %zu bytes from the hyperheap for the IOMMU level 2 cache."),
5209 cbIotlbes);
5210 }
5211 RTListInit(&pThis->LstLruIotlbe);
5212
5213 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbDomains + cbIotlbes));
5214#endif
5215
5216 /*
5217 * Initialize read-only registers.
5218 * NOTE! Fields here must match their corresponding field in the ACPI tables.
5219 */
5220 /* Don't remove the commented lines below as it lets us see all features at a glance. */
5221 pThis->ExtFeat.u64 = 0;
5222 //pThis->ExtFeat.n.u1PrefetchSup = 0;
5223 //pThis->ExtFeat.n.u1PprSup = 0;
5224 //pThis->ExtFeat.n.u1X2ApicSup = 0;
5225 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
5226 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
5227 pThis->ExtFeat.n.u1InvAllSup = 1;
5228 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5229 pThis->ExtFeat.n.u1HwErrorSup = 1;
5230 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
5231 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
5232 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
5233 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
5234 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
5235 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
5236 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
5237 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
5238 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
5239 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
5240 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
5241 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
5242 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
5243 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
5244 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
5245 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
5246 //pThis->ExtFeat.n.u2MarcSup = 0;
5247 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
5248 //pThis->ExtFeat.n.u1PerfOptSup = 0;
5249 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
5250 //pThis->ExtFeat.n.u1GstIoSup = 0;
5251 //pThis->ExtFeat.n.u1HostAccessSup = 0;
5252 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
5253 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
5254 //pThis->ExtFeat.n.u1HostDirtySup = 0;
5255 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
5256 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
5257 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
5258
5259 pThis->RsvdReg = 0;
5260
5261 pThis->DevSpecificFeat.u64 = 0;
5262 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
5263 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
5264
5265 pThis->DevSpecificCtrl.u64 = 0;
5266 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
5267 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
5268
5269 pThis->DevSpecificStatus.u64 = 0;
5270 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
5271 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
5272
5273 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
5274
5275 /*
5276 * Initialize parts of the IOMMU state as it would during reset.
5277 * Must be called -after- initializing PCI config. space registers.
5278 */
5279 iommuAmdR3Reset(pDevIns);
5280
5281 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
5282 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
5283 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
5284 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
5285 pThis->ExtFeat.u64));
5286 return VINF_SUCCESS;
5287}
5288
5289#else
5290
5291/**
5292 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5293 */
5294static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
5295{
5296 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5297 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5298 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5299
5300 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
5301
5302 /* Set up the MMIO RZ handlers. */
5303 int rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
5304 AssertRCReturn(rc, rc);
5305
5306 /* Set up the IOMMU RZ callbacks. */
5307 PDMIOMMUREGCC IommuReg;
5308 RT_ZERO(IommuReg);
5309 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5310 IommuReg.idxIommu = pThis->idxIommu;
5311 IommuReg.pfnMemAccess = iommuAmdDeviceMemAccess;
5312 IommuReg.pfnMemBulkAccess = iommuAmdDeviceMemBulkAccess;
5313 IommuReg.pfnMsiRemap = iommuAmdDeviceMsiRemap;
5314 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5315 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
5316 AssertRCReturn(rc, rc);
5317
5318 return VINF_SUCCESS;
5319}
5320#endif
5321
5322
5323/**
5324 * The device registration structure.
5325 */
5326const PDMDEVREG g_DeviceIommuAmd =
5327{
5328 /* .u32Version = */ PDM_DEVREG_VERSION,
5329 /* .uReserved0 = */ 0,
5330 /* .szName = */ "iommu-amd",
5331 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
5332 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
5333 /* .cMaxInstances = */ ~0U,
5334 /* .uSharedVersion = */ 42,
5335 /* .cbInstanceShared = */ sizeof(IOMMU),
5336 /* .cbInstanceCC = */ sizeof(IOMMUCC),
5337 /* .cbInstanceRC = */ sizeof(IOMMURC),
5338 /* .cMaxPciDevices = */ 1,
5339 /* .cMaxMsixVectors = */ 0,
5340 /* .pszDescription = */ "IOMMU (AMD)",
5341#if defined(IN_RING3)
5342 /* .pszRCMod = */ "VBoxDDRC.rc",
5343 /* .pszR0Mod = */ "VBoxDDR0.r0",
5344 /* .pfnConstruct = */ iommuAmdR3Construct,
5345 /* .pfnDestruct = */ iommuAmdR3Destruct,
5346 /* .pfnRelocate = */ NULL,
5347 /* .pfnMemSetup = */ NULL,
5348 /* .pfnPowerOn = */ NULL,
5349 /* .pfnReset = */ iommuAmdR3Reset,
5350 /* .pfnSuspend = */ NULL,
5351 /* .pfnResume = */ NULL,
5352 /* .pfnAttach = */ NULL,
5353 /* .pfnDetach = */ NULL,
5354 /* .pfnQueryInterface = */ NULL,
5355 /* .pfnInitComplete = */ NULL,
5356 /* .pfnPowerOff = */ NULL,
5357 /* .pfnSoftReset = */ NULL,
5358 /* .pfnReserved0 = */ NULL,
5359 /* .pfnReserved1 = */ NULL,
5360 /* .pfnReserved2 = */ NULL,
5361 /* .pfnReserved3 = */ NULL,
5362 /* .pfnReserved4 = */ NULL,
5363 /* .pfnReserved5 = */ NULL,
5364 /* .pfnReserved6 = */ NULL,
5365 /* .pfnReserved7 = */ NULL,
5366#elif defined(IN_RING0)
5367 /* .pfnEarlyConstruct = */ NULL,
5368 /* .pfnConstruct = */ iommuAmdRZConstruct,
5369 /* .pfnDestruct = */ NULL,
5370 /* .pfnFinalDestruct = */ NULL,
5371 /* .pfnRequest = */ NULL,
5372 /* .pfnReserved0 = */ NULL,
5373 /* .pfnReserved1 = */ NULL,
5374 /* .pfnReserved2 = */ NULL,
5375 /* .pfnReserved3 = */ NULL,
5376 /* .pfnReserved4 = */ NULL,
5377 /* .pfnReserved5 = */ NULL,
5378 /* .pfnReserved6 = */ NULL,
5379 /* .pfnReserved7 = */ NULL,
5380#elif defined(IN_RC)
5381 /* .pfnConstruct = */ iommuAmdRZConstruct,
5382 /* .pfnReserved0 = */ NULL,
5383 /* .pfnReserved1 = */ NULL,
5384 /* .pfnReserved2 = */ NULL,
5385 /* .pfnReserved3 = */ NULL,
5386 /* .pfnReserved4 = */ NULL,
5387 /* .pfnReserved5 = */ NULL,
5388 /* .pfnReserved6 = */ NULL,
5389 /* .pfnReserved7 = */ NULL,
5390#else
5391# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5392#endif
5393 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
5394};
5395
5396#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5397
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