VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 87691

Last change on this file since 87691 was 87691, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Replace IOMMU device lock with the PDM lock and use a separate lock for the IOTLB/DTE cache.
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1/* $Id: DevIommuAmd.cpp 87691 2021-02-10 16:20:11Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26#include <VBox/AssertGuest.h>
27
28#include <iprt/x86.h>
29#include <iprt/string.h>
30#include <iprt/avl.h>
31#ifdef IN_RING3
32# include <iprt/mem.h>
33#endif
34
35#include "VBoxDD.h"
36#include "DevIommuAmd.h"
37
38
39/*********************************************************************************************************************************
40* Defined Constants And Macros *
41*********************************************************************************************************************************/
42/** Release log prefix string. */
43#define IOMMU_LOG_PFX "AMD-IOMMU"
44/** The current saved state version. */
45#define IOMMU_SAVED_STATE_VERSION 1
46/** The IOMMU device instance magic. */
47#define IOMMU_MAGIC 0x10acce55
48/** Enable the IOTLBE cache. */
49#define IOMMU_WITH_IOTLBE_CACHE
50
51#ifdef IOMMU_WITH_IOTLBE_CACHE
52/** The maximum number of DTE entries. */
53# define IOMMU_DTE_CACHE_MAX UINT16_MAX
54/** The maximum number of IOTLB entries. */
55# define IOMMU_IOTLBE_MAX 128
56/** The mask of bits covering the domain ID in the IOTLBE key. */
57# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
58/** The mask of bits covering the IOVA in the IOTLBE key. */
59# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
60/** The number of bits to shift for the domain ID of the IOTLBE key. */
61# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
62/** The mask of bits for the domain ID of the IOTLBE key. */
63# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
64/** Gets the domain ID from an IOTLB entry key. */
65# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
66/** Gets the IOVA from the IOTLB entry key. */
67# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
68/** Makes an IOTLB entry key.
69 *
70 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
71 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
72 * so bottom 12 bits are free.
73 *
74 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
75 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
76 */
77# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
78 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
79
80/** Acquires the cache lock. */
81# define IOMMU_LOCK_CACHE(a_pDevIns, a_pThis) \
82 do { \
83 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
84 if (rcLock == VINF_SUCCESS) \
85 { /* likely */ } \
86 else \
87 { \
88 AssertRC(rcLock); \
89 return rcLock; \
90 } \
91 } while (0)
92
93/** Acquires the cache lock (asserts on failure). */
94# define IOMMU_LOCK_CACHE_NORET(a_pDevIns, a_pThis) \
95 do { \
96 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
97 AssertRC(rcLock); \
98 } while (0)
99
100/** Releases the cache lock. */
101# define IOMMU_UNLOCK_CACHE(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
102#endif
103
104/** @name IOMMU_DEV_F_XXX: I/O device flags.
105 *
106 * Some of these flags are "basic" i.e. they correspond directly to their bits in
107 * the DTE. The rest of the flags are based on checks or operations on several DTE
108 * bits.
109 *
110 * The basic flags are:
111 * - VALID (DTE.V)
112 * - IO_PERM_READ (DTE.IR)
113 * - IO_PERM_WRITE (DTE.IW)
114 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
115 * masking consistent)
116 * - SUPPRESS_ALL_IOPF (DTE.SA)
117 * - SUPPRESS_IOPF (DTE.SE)
118 * - INTR_MAP_VALID (DTE.IV)
119 * - IGNORE_UNMAPPED_INTR (DTE.IG)
120 *
121 * @sa iommuAmdGetBasicDevFlags()
122 * @{ */
123/** The DTE is present. */
124#define IOMMU_DEV_F_PRESENT RT_BIT(0)
125/** The DTE is valid. */
126#define IOMMU_DEV_F_VALID RT_BIT(1)
127/** DTE permissions apply for address translations. */
128#define IOMMU_DEV_F_IO_PERM RT_BIT(2)
129/** DTE permission - I/O read allowed. */
130#define IOMMU_DEV_F_IO_PERM_READ RT_BIT(3)
131/** DTE permission - I/O write allowed. */
132#define IOMMU_DEV_F_IO_PERM_WRITE RT_BIT(4)
133/** DTE permission - reserved. */
134#define IOMMU_DEV_F_IO_PERM_RSVD RT_BIT(5)
135/** Address translation required. */
136#define IOMMU_DEV_F_ADDR_TRANSLATE RT_BIT(6)
137/** Suppress all I/O page faults. */
138#define IOMMU_DEV_F_SUPPRESS_ALL_IOPF RT_BIT(7)
139/** Suppress I/O page faults. */
140#define IOMMU_DEV_F_SUPPRESS_IOPF RT_BIT(8)
141/** Interrupt map valid. */
142#define IOMMU_DEV_F_INTR_MAP_VALID RT_BIT(9)
143/** Ignore unmapped interrupts. */
144#define IOMMU_DEV_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
145/** An I/O page fault has been raised for this device. */
146#define IOMMU_DEV_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
147/** @} */
148/** The number of bits to shift I/O device flags for DTE permissions. */
149#define IOMMU_DEV_F_IO_PERM_SHIFT 3
150/** The mask of DTE permissions in I/O device flags. */
151#define IOMMU_DEV_F_IO_PERM_MASK 0x3
152
153/** Gets the page offset mask given the number of bits to shift. */
154#define IOMMU_GET_PAGE_OFF_MASK(a_cShift) (~(UINT64_C(0xffffffffffffffff) << (a_cShift)))
155
156/** Acquires the PDM lock. */
157#define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
158 do { \
159 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
160 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
161 { /* likely */ } \
162 else \
163 return rcLock; \
164 } while (0)
165
166/** Acquires the PDM lock (asserts on failure). */
167#define IOMMU_LOCK_NORET(a_pDevIns, a_pThisCC) \
168 do { \
169 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
170 AssertRC(rcLock); \
171 } while (0)
172
173/** Releases the PDM lock. */
174# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
175
176/** Asserts that the lock is owned by this thread. */
177#define IOMMU_ASSERT_LOCKED(a_pDevIns) do { } while (0)
178
179/** Asserts that the lock isn't owned by this thread. */
180#define IOMMU_ASSERT_NOT_LOCKED(a_pDevIns) do { } while (0)
181
182
183/*********************************************************************************************************************************
184* Structures and Typedefs *
185*********************************************************************************************************************************/
186/**
187 * IOMMU operation (transaction).
188 */
189typedef enum IOMMUOP
190{
191 /** Address translation request. */
192 IOMMUOP_TRANSLATE_REQ = 0,
193 /** Memory read request. */
194 IOMMUOP_MEM_READ,
195 /** Memory write request. */
196 IOMMUOP_MEM_WRITE,
197 /** Interrupt request. */
198 IOMMUOP_INTR_REQ,
199 /** Command. */
200 IOMMUOP_CMD
201} IOMMUOP;
202/** Pointer to a IOMMU operation. */
203typedef IOMMUOP *PIOMMUOP;
204
205/**
206 * I/O page walk result.
207 */
208typedef struct IOWALKRESULT
209{
210 /** The translated system physical address. */
211 RTGCPHYS GCPhysSpa;
212 /** The number of offset bits in the system physical address. */
213 uint8_t cShift;
214 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
215 uint8_t fPerm;
216} IOWALKRESULT;
217/** Pointer to an I/O walk result struct. */
218typedef IOWALKRESULT *PIOWALKRESULT;
219/** Pointer to a const I/O walk result struct. */
220typedef IOWALKRESULT const *PCIOWALKRESULT;
221
222/**
223 * IOMMU I/O Device.
224 * Used for caching as well as passing flags to events.
225 */
226typedef struct IODEVICE
227{
228 /** This device's flags, see IOMMU_DEV_F_XXX. */
229 uint16_t fFlags;
230 /** The domain ID assigned for this device by software. */
231 uint16_t uDomainId;
232} IODEVICE;
233/** Pointer to an I/O device struct. */
234typedef IODEVICE *PIODEVICE;
235/** Pointer to a const I/O device struct. */
236typedef IODEVICE *PCIODEVICE;
237AssertCompileSize(IODEVICE, 4);
238
239#ifdef IOMMU_WITH_IOTLBE_CACHE
240/**
241 * IOMMU I/O TLB Entry.
242 * Keep this as small and aligned as possible.
243 */
244typedef struct IOTLBE
245{
246 /** The AVL tree node. */
247 AVLU64NODECORE Core;
248 /** The least recently used (LRU) list node. */
249 RTLISTNODE NdLru;
250 /** The I/O walk result of the translation. */
251 IOWALKRESULT WalkResult;
252 /** Whether the entry needs to be evicted from the cache. */
253 bool fEvictPending;
254} IOTLBE;
255/** Pointer to an IOMMU I/O TLB entry struct. */
256typedef IOTLBE *PIOTLBE;
257/** Pointer to a const IOMMU I/O TLB entry struct. */
258typedef IOTLBE const *PCIOTLBE;
259AssertCompileSizeAlignment(IOTLBE, 8);
260AssertCompileMemberOffset(IOTLBE, Core, 0);
261#endif /* IOMMU_WITH_IOTLBE_CACHE */
262
263/**
264 * The shared IOMMU device state.
265 */
266typedef struct IOMMU
267{
268 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
269 uint32_t idxIommu;
270 /** IOMMU magic. */
271 uint32_t u32Magic;
272
273 /** Whether the command thread is sleeping. */
274 bool volatile fCmdThreadSleeping;
275 /** Alignment padding. */
276 uint8_t afPadding0[3];
277 /** Whether the command thread has been signaled for wake up. */
278 bool volatile fCmdThreadSignaled;
279 /** Alignment padding. */
280 uint8_t afPadding1[3];
281
282 /** The event semaphore the command thread waits on. */
283 SUPSEMEVENT hEvtCmdThread;
284 /** The MMIO handle. */
285 IOMMMIOHANDLE hMmio;
286
287#ifdef IOMMU_WITH_IOTLBE_CACHE
288 /** The critsect that protects the cache from concurrent access. */
289 PDMCRITSECT CritSectCache;
290 /** L1 Cache - Maps [DeviceId] to [DomainId]. */
291 PIODEVICE paDevices;
292 /** Pointer to array of pre-allocated IOTLBEs. */
293 PIOTLBE paIotlbes;
294 /** L2 Cache - Maps [DomainId,Iova] to [IOTLBE]. */
295 AVLU64TREE TreeIotlbe;
296 /** LRU list anchor for IOTLB entries. */
297 RTLISTANCHOR LstLruIotlbe;
298 /** Index of the next unused IOTLB. */
299 uint32_t idxUnusedIotlbe;
300 /** Number of cached IOTLB entries in the tree. */
301 uint32_t cCachedIotlbes;
302#endif
303
304 /** @name PCI: Base capability block registers.
305 * @{ */
306 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
307 /** @} */
308
309 /** @name MMIO: Control and status registers.
310 * @{ */
311 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
312 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
313 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
314 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
315 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
316 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
317 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
318 /** @} */
319
320 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
321 * @{ */
322 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
323 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
324 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
325 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
326 /** @} */
327
328 /** @todo IOMMU: SMI filter. */
329
330 /** @name MMIO: Guest Virtual-APIC Log registers.
331 * @{ */
332 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
333 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
334 /** @} */
335
336 /** @name MMIO: Alternate PPR and Event Log registers.
337 * @{ */
338 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
339 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
340 /** @} */
341
342 /** @name MMIO: Device-specific feature registers.
343 * @{ */
344 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
345 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
346 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
347 /** @} */
348
349 /** @name MMIO: MSI Capability Block registers.
350 * @{ */
351 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
352 /** @} */
353
354 /** @name MMIO: Performance Optimization Control registers.
355 * @{ */
356 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
357 /** @} */
358
359 /** @name MMIO: x2APIC Control registers.
360 * @{ */
361 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
362 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
363 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
364 /** @} */
365
366 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
367 * @{ */
368 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
369 /** @} */
370
371 /** @name MMIO: Reserved register.
372 * @{ */
373 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
374 /** @} */
375
376 /** @name MMIO: Command and Event Log pointer registers.
377 * @{ */
378 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
379 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
380 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
381 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
382 /** @} */
383
384 /** @name MMIO: Command and Event Status register.
385 * @{ */
386 IOMMU_STATUS_T Status; /**< IOMMU status register. */
387 /** @} */
388
389 /** @name MMIO: PPR Log Head and Tail pointer registers.
390 * @{ */
391 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
392 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
393 /** @} */
394
395 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
396 * @{ */
397 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
398 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
399 /** @} */
400
401 /** @name MMIO: PPR Log B Head and Tail pointer registers.
402 * @{ */
403 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
404 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
405 /** @} */
406
407 /** @name MMIO: Event Log B Head and Tail pointer registers.
408 * @{ */
409 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
410 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
411 /** @} */
412
413 /** @name MMIO: PPR Log Overflow protection registers.
414 * @{ */
415 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
416 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
417 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
418 /** @} */
419
420 /** @todo IOMMU: IOMMU Event counter registers. */
421
422#ifdef VBOX_WITH_STATISTICS
423 /** @name IOMMU: Stat counters.
424 * @{ */
425 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
426 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
427 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
428 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
429
430 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
431 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
432
433 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
434 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
435 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
436 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
437
438 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
439 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
440 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
441 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
442
443 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
444 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
445 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
446 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
447 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
448 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
449 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
450 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
451 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
452
453 STAMCOUNTER StatIotlbeLookupNonContig; /**< Number of IOTLB lookups that result in non-contiguous regions. */
454 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
455 STAMCOUNTER StatIotlbeCacheHit; /**< Number of IOTLB cache hits. */
456 STAMCOUNTER StatIotlbeCacheMiss; /**< Number of IOTLB cache misses. */
457 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
458 STAMPROFILEADV StatIotlbeLookup; /**< Profiling of IOTLB entry lookup (cached). */
459
460 STAMCOUNTER StatDteLookupNonContig; /**< Number of DTE lookups that result in non-contiguous regions. */
461 STAMPROFILEADV StatIoPageWalkLookup; /**< Profiling of I/O page walk (uncached). */
462 /** @} */
463#endif
464} IOMMU;
465/** Pointer to the IOMMU device state. */
466typedef struct IOMMU *PIOMMU;
467/** Pointer to the const IOMMU device state. */
468typedef const struct IOMMU *PCIOMMU;
469AssertCompileMemberAlignment(IOMMU, fCmdThreadSleeping, 4);
470AssertCompileMemberAlignment(IOMMU, fCmdThreadSignaled, 4);
471AssertCompileMemberAlignment(IOMMU, hEvtCmdThread, 8);
472AssertCompileMemberAlignment(IOMMU, hMmio, 8);
473#ifdef IOMMU_WITH_IOTLBE_CACHE
474AssertCompileMemberAlignment(IOMMU, paDevices, 8);
475AssertCompileMemberAlignment(IOMMU, paIotlbes, 8);
476AssertCompileMemberAlignment(IOMMU, TreeIotlbe, 8);
477AssertCompileMemberAlignment(IOMMU, LstLruIotlbe, 8);
478#endif
479AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
480AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
481AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
482AssertCompileMemberAlignment(IOMMU, Status, 8);
483
484/**
485 * The ring-3 IOMMU device state.
486 */
487typedef struct IOMMUR3
488{
489 /** Device instance. */
490 PPDMDEVINSR3 pDevInsR3;
491 /** The IOMMU helpers. */
492 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
493 /** The command thread handle. */
494 R3PTRTYPE(PPDMTHREAD) pCmdThread;
495} IOMMUR3;
496/** Pointer to the ring-3 IOMMU device state. */
497typedef IOMMUR3 *PIOMMUR3;
498
499/**
500 * The ring-0 IOMMU device state.
501 */
502typedef struct IOMMUR0
503{
504 /** Device instance. */
505 PPDMDEVINSR0 pDevInsR0;
506 /** The IOMMU helpers. */
507 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
508} IOMMUR0;
509/** Pointer to the ring-0 IOMMU device state. */
510typedef IOMMUR0 *PIOMMUR0;
511
512/**
513 * The raw-mode IOMMU device state.
514 */
515typedef struct IOMMURC
516{
517 /** Device instance. */
518 PPDMDEVINSRC pDevInsRC;
519 /** The IOMMU helpers. */
520 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
521} IOMMURC;
522/** Pointer to the raw-mode IOMMU device state. */
523typedef IOMMURC *PIOMMURC;
524
525/** The IOMMU device state for the current context. */
526typedef CTX_SUFF(IOMMU) IOMMUCC;
527/** Pointer to the IOMMU device state for the current context. */
528typedef CTX_SUFF(PIOMMU) PIOMMUCC;
529
530/**
531 * IOMMU register access.
532 */
533typedef struct IOMMUREGACC
534{
535 const char *pszName;
536 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
537 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
538} IOMMUREGACC;
539/** Pointer to an IOMMU register access. */
540typedef IOMMUREGACC *PIOMMUREGACC;
541/** Pointer to a const IOMMU register access. */
542typedef IOMMUREGACC const *PCIOMMUREGACC;
543
544#ifdef IOMMU_WITH_IOTLBE_CACHE
545/**
546 * IOTLBE flush argument.
547 */
548typedef struct IOTLBEFLUSHARG
549{
550 /** The IOMMU device state. */
551 PIOMMU pIommu;
552 /** The domain ID to flush. */
553 uint16_t uDomainId;
554} IOTLBEFLUSHARG;
555/** Pointer to an IOTLBE flush argument. */
556typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
557/** Pointer to a const IOTLBE flush argument. */
558typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
559
560/**
561 * IOTLBE Info. argument.
562 */
563typedef struct IOTLBEINFOARG
564{
565 /** The IOMMU device state. */
566 PIOMMU pIommu;
567 /** The info helper. */
568 PCDBGFINFOHLP pHlp;
569 /** The domain ID to dump IOTLB entry. */
570 uint16_t uDomainId;
571} IOTLBEINFOARG;
572/** Pointer to an IOTLBE flush argument. */
573typedef IOTLBEINFOARG *PIOTLBEINFOARG;
574/** Pointer to a const IOTLBE flush argument. */
575typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
576#endif
577
578
579/*********************************************************************************************************************************
580* Global Variables *
581*********************************************************************************************************************************/
582/**
583 * An array of the number of device table segments supported.
584 * Indexed by u2DevTabSegSup.
585 */
586static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
587
588/**
589 * An array of the masks to select the device table segment index from a device ID.
590 */
591static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
592
593/**
594 * An array of the shift values to select the device table segment index from a
595 * device ID.
596 */
597static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
598
599/**
600 * The maximum size (inclusive) of each device table segment (0 to 7).
601 * Indexed by the device table segment index.
602 */
603static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
604
605/**
606 * The IOMMU I/O permission names.
607 */
608static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
609
610
611#ifndef VBOX_DEVICE_STRUCT_TESTCASE
612/**
613 * Gets the maximum number of buffer entries for the given buffer length.
614 *
615 * @returns Number of buffer entries.
616 * @param uEncodedLen The length (power-of-2 encoded).
617 */
618DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
619{
620 Assert(uEncodedLen > 7);
621 Assert(uEncodedLen < 16);
622 return 2 << (uEncodedLen - 1);
623}
624
625
626/**
627 * Gets the total length of the buffer given a base register's encoded length.
628 *
629 * @returns The length of the buffer in bytes.
630 * @param uEncodedLen The length (power-of-2 encoded).
631 */
632DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
633{
634 Assert(uEncodedLen > 7);
635 Assert(uEncodedLen < 16);
636 return (2 << (uEncodedLen - 1)) << 4;
637}
638
639
640/**
641 * Gets the number of (unconsumed) entries in the event log.
642 *
643 * @returns The number of entries in the event log.
644 * @param pThis The IOMMU device state.
645 */
646static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
647{
648 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
649 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
650 if (idxTail >= idxHead)
651 return idxTail - idxHead;
652
653 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
654 return cMaxEvts - idxHead + idxTail;
655}
656
657
658/**
659 * Gets the descriptive I/O permission name for a memory access.
660 *
661 * @returns The I/O permission name.
662 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
663 */
664static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
665{
666 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
667 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
668 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
669}
670
671
672#if 0
673/**
674 * Gets the number of (unconsumed) commands in the command buffer.
675 *
676 * @returns The number of commands in the command buffer.
677 * @param pThis The IOMMU device state.
678 */
679static uint32_t iommuAmdGetCmdBufEntryCount(PIOMMU pThis)
680{
681 uint32_t const idxTail = pThis->CmdBufTailPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
682 uint32_t const idxHead = pThis->CmdBufHeadPtr.n.off >> IOMMU_CMD_GENERIC_SHIFT;
683 if (idxTail >= idxHead)
684 return idxTail - idxHead;
685
686 uint32_t const cMaxCmds = iommuAmdGetBufMaxEntries(pThis->CmdBufBaseAddr.n.u4Len);
687 return cMaxCmds - idxHead + idxTail;
688}
689#endif
690
691
692/**
693 * Checks whether two consecutive I/O page walk results translates to a physically
694 * contiguous region.
695 *
696 * @returns @c true if they are contiguous, @c false otherwise.
697 * @param pWalkResultPrev The I/O walk result of the previous page.
698 * @param pWalkResult The I/O walk result of the current page.
699 */
700static bool iommuAmdLookupIsAccessContig(PCIOWALKRESULT pWalkResultPrev, PCIOWALKRESULT pWalkResult)
701{
702 Assert(pWalkResultPrev->fPerm == pWalkResult->fPerm);
703 size_t const cbPrev = RT_BIT_64(pWalkResultPrev->cShift);
704 RTGCPHYS const GCPhysPrev = pWalkResultPrev->GCPhysSpa;
705 RTGCPHYS const GCPhys = pWalkResult->GCPhysSpa;
706 uint64_t const offMaskPrev = IOMMU_GET_PAGE_OFF_MASK(pWalkResultPrev->cShift);
707 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(pWalkResult->cShift);
708
709 /* Paranoia: Ensure offset bits are 0. */
710 Assert(!(GCPhysPrev & offMaskPrev));
711 Assert(!(GCPhys & offMask));
712
713 if ((GCPhysPrev & ~offMaskPrev) + cbPrev == (GCPhys & ~offMask))
714 return true;
715 return false;
716}
717
718
719/**
720 * Gets the basic I/O device flags for the given device table entry.
721 *
722 * @returns The basic I/O device flags.
723 * @param pDte The device table entry.
724 */
725static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
726{
727 /* Extract basic flags from bits 127:0 of the DTE. */
728 uint16_t fFlags = 0;
729 if (pDte->n.u1Valid)
730 {
731 fFlags |= IOMMU_DEV_F_VALID;
732
733 if (pDte->n.u1SuppressAllPfEvents)
734 fFlags |= IOMMU_DEV_F_SUPPRESS_ALL_IOPF;
735 if (pDte->n.u1SuppressPfEvents)
736 fFlags |= IOMMU_DEV_F_SUPPRESS_IOPF;
737
738 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
739 AssertCompile(IOMMU_DEV_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
740 fFlags |= fDtePerm << IOMMU_DEV_F_IO_PERM_SHIFT;
741 }
742
743 /* Extract basic flags from bits 255:128 of the DTE. */
744 if (pDte->n.u1IntrMapValid)
745 {
746 fFlags |= IOMMU_DEV_F_INTR_MAP_VALID;
747 if (pDte->n.u1IgnoreUnmappedIntrs)
748 fFlags |= IOMMU_DEV_F_IGNORE_UNMAPPED_INTR;
749 }
750 return fFlags;
751}
752
753
754#ifdef IOMMU_WITH_IOTLBE_CACHE
755/**
756 * Moves the IOTLB entry to the least recently used slot.
757 *
758 * @param pThis The IOMMU device state.
759 * @param pIotlbe The IOTLB entry.
760 */
761static void iommuAmdIotlbEntryMoveToLru(PIOMMU pThis, PIOTLBE pIotlbe)
762{
763 if (!RTListNodeIsFirst(&pThis->LstLruIotlbe, &pIotlbe->NdLru))
764 {
765 RTListNodeRemove(&pIotlbe->NdLru);
766 RTListPrepend(&pThis->LstLruIotlbe, &pIotlbe->NdLru);
767 }
768}
769
770
771/**
772 * Moves the IOTLB entry to the most recently used slot.
773 *
774 * @param pThis The IOMMU device state.
775 * @param pIotlbe The IOTLB entry.
776 */
777static void iommuAmdIotlbEntryMoveToMru(PIOMMU pThis, PIOTLBE pIotlbe)
778{
779 if (!RTListNodeIsLast(&pThis->LstLruIotlbe, &pIotlbe->NdLru))
780 {
781 RTListNodeRemove(&pIotlbe->NdLru);
782 RTListAppend(&pThis->LstLruIotlbe, &pIotlbe->NdLru);
783 }
784}
785
786
787#ifdef IN_RING3
788/**
789 * Dumps the IOTLB entry via the debug info helper.
790 *
791 * @returns VINF_SUCCESS.
792 * @param pNode Pointer to an IOTLBE.
793 * @param pvUser Pointer to an IOTLBEINFOARG.
794 */
795static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
796{
797 /* Validate. */
798 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
799 AssertPtr(pArgs);
800 AssertPtr(pArgs->pIommu);
801 AssertPtr(pArgs->pHlp);
802 Assert(pArgs->pIommu->u32Magic == IOMMU_MAGIC);
803
804 uint16_t const uDomainId = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
805 if (uDomainId == pArgs->uDomainId)
806 {
807 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
808 AVLU64KEY const uKey = pIotlbe->Core.Key;
809 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
810 RTGCPHYS const GCPhysSpa = pIotlbe->WalkResult.GCPhysSpa;
811 uint8_t const cShift = pIotlbe->WalkResult.cShift;
812 size_t const cbPage = RT_BIT_64(cShift);
813 uint8_t const fPerm = pIotlbe->WalkResult.fPerm;
814 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
815 bool const fEvictPending = pIotlbe->fEvictPending;
816
817 PCDBGFINFOHLP pHlp = pArgs->pHlp;
818 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
819 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
820 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
821 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
822 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
823 }
824
825 return VINF_SUCCESS;
826}
827#endif /* IN_RING3 */
828
829
830/**
831 * Removes the IOTLB entry if it's associated with the specified domain ID.
832 *
833 * @returns VINF_SUCCESS.
834 * @param pNode Pointer to an IOTLBE.
835 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
836 */
837static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
838{
839 /* Validate. */
840 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
841 AssertPtr(pArgs);
842 AssertPtr(pArgs->pIommu);
843 Assert(pArgs->pIommu->u32Magic == IOMMU_MAGIC);
844
845 uint16_t const uDomainId = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
846 if (uDomainId == pArgs->uDomainId)
847 {
848 /* Mark this entry is as invalidated and needs to be evicted later. */
849 PIOTLBE pIotlbe = (PIOTLBE)pNode;
850 pIotlbe->fEvictPending = true;
851 iommuAmdIotlbEntryMoveToLru(pArgs->pIommu, (PIOTLBE)pNode);
852 }
853 return VINF_SUCCESS;
854}
855
856
857/**
858 * Inserts an IOTLB entry into the cache.
859 *
860 * @param pThis The IOMMU device state.
861 * @param pIotlbe The IOTLB entry to initialize and insert.
862 * @param uDomainId The domain ID.
863 * @param uIova The I/O virtual address.
864 * @param pWalkResult The I/O page walk result of the access.
865 */
866static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOTLBE pIotlbe, uint16_t uDomainId, uint64_t uIova,
867 PCIOWALKRESULT pWalkResult)
868{
869 /* Initialize the IOTLB entry with results of the I/O page walk. */
870 pIotlbe->Core.Key = IOMMU_IOTLB_KEY_MAKE(uDomainId, uIova);
871 pIotlbe->WalkResult = *pWalkResult;
872
873 /* Validate. */
874 Assert(pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL);
875 Assert(!pIotlbe->fEvictPending);
876
877 /* Check if the entry already exists. */
878 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThis->TreeIotlbe, pIotlbe->Core.Key);
879 if (!pFound)
880 {
881 /* Insert the entry into the cache. */
882 bool const fInserted = RTAvlU64Insert(&pThis->TreeIotlbe, &pIotlbe->Core);
883 Assert(fInserted); NOREF(fInserted);
884 Assert(pThis->cCachedIotlbes < IOMMU_IOTLBE_MAX);
885 ++pThis->cCachedIotlbes;
886 STAM_COUNTER_INC(&pThis->StatIotlbeCached);
887 }
888 else
889 {
890 /* Update the existing entry. */
891 if (pFound->fEvictPending)
892 {
893 pFound->fEvictPending = false;
894 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
895 }
896 Assert(pFound->WalkResult.cShift == pWalkResult->cShift);
897 pFound->WalkResult.fPerm = pWalkResult->fPerm;
898 pFound->WalkResult.GCPhysSpa = pWalkResult->GCPhysSpa;
899 }
900}
901
902
903/**
904 * Removes an IOTLB entry from the cache for the given key.
905 *
906 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
907 * the tree.
908 * @param pThis The IOMMU device state.
909 * @param uKey The key of the IOTLB entry to remove.
910 */
911static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, AVLU64KEY uKey)
912{
913 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThis->TreeIotlbe, uKey);
914 if (pIotlbe)
915 {
916 Assert(pThis->cCachedIotlbes > 0);
917 --pThis->cCachedIotlbes;
918 STAM_COUNTER_DEC(&pThis->StatIotlbeCached);
919 }
920 return pIotlbe;
921}
922
923
924/**
925 * Destroys an IOTLB entry.
926 *
927 * @param pIotlbe The IOTLB entry to destroy.
928 * @remarks An entry must only be destroyed if it's not in the cache!
929 */
930static void iommuAmdIotlbEntryDestroy(PIOTLBE pIotlbe)
931{
932 /* We must not erase the LRU node connections here! */
933 RT_ZERO(pIotlbe->Core);
934 RT_ZERO(pIotlbe->WalkResult);
935 pIotlbe->fEvictPending = false;
936 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
937}
938
939
940/**
941 * Looks up an IOTLB from the cache.
942 *
943 * @returns Pointer to IOTLB entry if found, NULL otherwise.
944 * @param pThis The IOMMU device state.
945 * @param uDomainId The domain ID.
946 * @param uIova The I/O virtual address.
947 */
948static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, uint64_t uDomainId, uint64_t uIova)
949{
950 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(uDomainId, uIova);
951 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThis->TreeIotlbe, uKey);
952 if ( pIotlbe
953 && pIotlbe->fEvictPending)
954 {
955 /*
956 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
957 * them from the cache immediately. Here we found one such entry, so remove it and move it to
958 * the LRU list and return that the lookup failed as it should.
959 */
960 iommuAmdIotlbEntryRemove(pThis, pIotlbe->Core.Key);
961 iommuAmdIotlbEntryDestroy(pIotlbe);
962 Assert(!pIotlbe->fEvictPending);
963 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
964 iommuAmdIotlbEntryMoveToLru(pThis, pIotlbe);
965 return NULL;
966 }
967 return pIotlbe;
968}
969
970
971/**
972 * Adds an IOTLB entry to the cache.
973 *
974 * @param pThis The IOMMU device state.
975 * @param uDomainId The domain ID.
976 * @param uIova The I/O virtual address.
977 * @param pWalkResult The I/O page walk result of the access.
978 */
979static void iommuAmdIotlbAdd(PIOMMU pThis, uint16_t uDomainId, uint64_t uIova, PCIOWALKRESULT pWalkResult)
980{
981 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
982 Assert(pWalkResult);
983 Assert(pWalkResult->cShift <= 31);
984 Assert(pWalkResult->fPerm != IOMMU_IO_PERM_NONE);
985
986 /*
987 * If there are no unused IOTLB entries, evict the LRU entry.
988 * Otherwise, get a new IOTLB entry from the pre-allocated list.
989 */
990 if (pThis->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
991 {
992 /* Grab the least recently used entry. */
993 PIOTLBE pIotlbe = RTListGetFirst(&pThis->LstLruIotlbe, IOTLBE, NdLru);
994 Assert(pIotlbe);
995
996 /* If the entry is in the cache, remove it. */
997 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
998 {
999 if (pIotlbe->fEvictPending)
1000 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1001 iommuAmdIotlbEntryRemove(pThis, pIotlbe->Core.Key);
1002 iommuAmdIotlbEntryDestroy(pIotlbe);
1003 }
1004
1005 /* Initialize and insert the IOTLB entry into the cache. */
1006 iommuAmdIotlbEntryInsert(pThis, pIotlbe, uDomainId, uIova, pWalkResult);
1007
1008 /* Move the entry to the most recently used slot. */
1009 iommuAmdIotlbEntryMoveToMru(pThis, pIotlbe);
1010 }
1011 else
1012 {
1013 /* Grab an unused IOTLB entry from the pre-allocated list. */
1014 PIOTLBE pIotlbe = &pThis->paIotlbes[pThis->idxUnusedIotlbe];
1015 ++pThis->idxUnusedIotlbe;
1016
1017 /* Initialize and insert the IOTLB entry into the cache. */
1018 iommuAmdIotlbEntryInsert(pThis, pIotlbe, uDomainId, uIova, pWalkResult);
1019
1020 /* Add the entry to the most recently used slot. */
1021 RTListAppend(&pThis->LstLruIotlbe, &pIotlbe->NdLru);
1022 }
1023}
1024
1025
1026/**
1027 * Removes all IOTLB entries from the cache.
1028 *
1029 * @param pDevIns The IOMMU instance data.
1030 */
1031static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1032{
1033 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1034 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1035
1036 if (pThis->cCachedIotlbes > 0)
1037 {
1038 pThis->idxUnusedIotlbe = 0;
1039 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
1040 RT_BZERO(pThis->paIotlbes, cbIotlbes);
1041 pThis->cCachedIotlbes = 0;
1042 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1043 RTListInit(&pThis->LstLruIotlbe);
1044 }
1045
1046 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1047}
1048
1049
1050/**
1051 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1052 * domain ID from the cache.
1053 *
1054 * @param pDevIns The IOMMU instance data.
1055 * @param uDomainId The domain ID.
1056 * @param uIova The I/O virtual address to invalidate.
1057 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1058 */
1059static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t uDomainId, uint64_t uIova, size_t cbInvalidate)
1060{
1061 /* Validate. */
1062 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1063 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1064 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1065
1066 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1067 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1068
1069 do
1070 {
1071 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(uDomainId, uIova);
1072 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, uKey);
1073 if (pIotlbe)
1074 {
1075 iommuAmdIotlbEntryDestroy(pIotlbe);
1076 iommuAmdIotlbEntryMoveToLru(pThis, pIotlbe);
1077 }
1078 uIova += X86_PAGE_4K_SIZE;
1079 cbInvalidate -= X86_PAGE_4K_SIZE;
1080 } while (cbInvalidate > 0);
1081
1082 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1083}
1084
1085
1086/**
1087 * Removes all IOTLB entries for the specified domain ID.
1088 *
1089 * @param pDevIns The IOMMU instance data.
1090 * @param uDomainId The domain ID.
1091 */
1092static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t uDomainId)
1093{
1094 /*
1095 * We need to iterate the tree and search based on the domain ID.
1096 * But it seems we cannot remove items while iterating the tree.
1097 * Thus, we simply mark entries for eviction later but move them to the LRU
1098 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1099 */
1100 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1101 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1102
1103 IOTLBEFLUSHARG Args;
1104 Args.pIommu = pThis;
1105 Args.uDomainId = uDomainId;
1106 RTAvlU64DoWithAll(&pThis->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1107
1108 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1109}
1110
1111
1112/**
1113 * Adds or updates an IOTLB entry for the given I/O page walk result.
1114 *
1115 * @param pDevIns The IOMMU instance data.
1116 * @param uDomainId The domain ID.
1117 * @param uIova The I/O virtual address.
1118 * @param cbAccess The size of the access (must be 4K aligned).
1119 * @param GCPhysSpa The translated system-physical address.
1120 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
1121 */
1122static void iommuAmdIotlbUpdate(PPDMDEVINS pDevIns, uint16_t uDomainId, uint64_t uIova, size_t cbAccess, RTGCPHYS GCPhysSpa,
1123 uint8_t fPerm)
1124{
1125 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1126 Assert(!(GCPhysSpa & X86_PAGE_4K_OFFSET_MASK));
1127 Assert(!(cbAccess & X86_PAGE_4K_OFFSET_MASK));
1128 Assert(cbAccess >= X86_PAGE_4K_SIZE);
1129
1130 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1131
1132 /* Add IOTLB entries for every page in the access. */
1133 IOWALKRESULT WalkResult;
1134 RT_ZERO(WalkResult);
1135 WalkResult.cShift = X86_PAGE_4K_SHIFT;
1136 WalkResult.fPerm = fPerm;
1137 WalkResult.GCPhysSpa = GCPhysSpa;
1138
1139 size_t cPages = cbAccess / X86_PAGE_4K_SIZE;
1140 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1141
1142 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1143 do
1144 {
1145 iommuAmdIotlbAdd(pThis, uDomainId, uIova, &WalkResult);
1146 uIova += X86_PAGE_4K_SIZE;
1147 WalkResult.GCPhysSpa += X86_PAGE_4K_SIZE;
1148 --cPages;
1149 } while (cPages > 0);
1150 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1151}
1152
1153
1154/**
1155 * Updates the I/O device flags for the given device ID.
1156 *
1157 * @param pDevIns The IOMMU instance data.
1158 * @param uDevId The device ID (bus, device, function).
1159 * @param pDte The device table entry. Can be NULL only when @a fFlags is
1160 * 0.
1161 * @param fOrMask The device flags (usually compound flags) to OR in with the
1162 * basic flags, see IOMMU_DEV_F_XXX. Pass 0 to flush the DTE
1163 * from the cache.
1164 */
1165static void iommuAmdDteCacheUpdate(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, uint16_t fOrMask)
1166{
1167 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1168 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1169
1170 if (fOrMask & IOMMU_DEV_F_PRESENT)
1171 {
1172 Assert(pDte);
1173 pThis->paDevices[uDevId].fFlags = iommuAmdGetBasicDevFlags(pDte) | fOrMask;
1174 pThis->paDevices[uDevId].uDomainId = pDte->n.u16DomainId;
1175 }
1176 else
1177 {
1178 pThis->paDevices[uDevId].fFlags = 0;
1179 pThis->paDevices[uDevId].uDomainId = 0;
1180 }
1181
1182 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1183}
1184
1185
1186/**
1187 * Sets one or more I/O device flags if the device is present in the cache.
1188 *
1189 * @param pDevIns The IOMMU instance data.
1190 * @param uDevId The device ID (bus, device, function).
1191 * @param fDevIoFlags The device flags to set.
1192 */
1193static void iommuAmdDteCacheSetFlags(PPDMDEVINS pDevIns, uint16_t uDevId, uint16_t fDevIoFlags)
1194{
1195 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1196 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1197
1198 if (fDevIoFlags & IOMMU_DEV_F_PRESENT)
1199 pThis->paDevices[uDevId].fFlags |= fDevIoFlags;
1200
1201 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1202}
1203
1204
1205/**
1206 * Removes all entries in the device table entry cache.
1207 *
1208 * @param pDevIns The IOMMU instance data.
1209 */
1210static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1211{
1212 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1213 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1214
1215 size_t const cbDevices = sizeof(IODEVICE) * IOMMU_DTE_CACHE_MAX;
1216 RT_BZERO(pThis->paDevices, cbDevices);
1217
1218 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1219}
1220#endif /* IOMMU_WITH_IOTLBE_CACHE */
1221
1222
1223DECLINLINE(IOMMU_STATUS_T) iommuAmdGetStatus(PCIOMMU pThis)
1224{
1225 IOMMU_STATUS_T Status;
1226 Status.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Status.u64);
1227 return Status;
1228}
1229
1230
1231DECLINLINE(IOMMU_CTRL_T) iommuAmdGetCtrl(PCIOMMU pThis)
1232{
1233 IOMMU_CTRL_T Ctrl;
1234 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1235 return Ctrl;
1236}
1237
1238
1239/**
1240 * Returns whether MSI is enabled for the IOMMU.
1241 *
1242 * @returns Whether MSI is enabled.
1243 * @param pDevIns The IOMMU device instance.
1244 *
1245 * @note There should be a PCIDevXxx function for this.
1246 */
1247static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1248{
1249 MSI_CAP_HDR_T MsiCapHdr;
1250 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1251 return MsiCapHdr.n.u1MsiEnable;
1252}
1253
1254
1255/**
1256 * Signals a PCI target abort.
1257 *
1258 * @param pDevIns The IOMMU device instance.
1259 */
1260static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1261{
1262 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1263 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1264 PDMPciDevSetStatus(pPciDev, u16Status);
1265}
1266
1267
1268/**
1269 * Wakes up the command thread if there are commands to be processed or if
1270 * processing is requested to be stopped by software.
1271 *
1272 * @param pDevIns The IOMMU device instance.
1273 *
1274 * @remarks The IOMMU lock must be held.
1275 */
1276static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1277{
1278 IOMMU_ASSERT_LOCKED(pDevIns);
1279 Log4Func(("\n"));
1280
1281 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1282 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1283 if (Status.n.u1CmdBufRunning)
1284 {
1285 Log4Func(("Signaling command thread\n"));
1286 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1287 }
1288}
1289
1290
1291/**
1292 * Reads the Device Table Base Address Register.
1293 */
1294static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1295{
1296 RT_NOREF(pDevIns, offReg);
1297 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1298 return VINF_SUCCESS;
1299}
1300
1301
1302/**
1303 * Reads the Command Buffer Base Address Register.
1304 */
1305static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1306{
1307 RT_NOREF(pDevIns, offReg);
1308 *pu64Value = pThis->CmdBufBaseAddr.u64;
1309 return VINF_SUCCESS;
1310}
1311
1312
1313/**
1314 * Reads the Event Log Base Address Register.
1315 */
1316static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1317{
1318 RT_NOREF(pDevIns, offReg);
1319 *pu64Value = pThis->EvtLogBaseAddr.u64;
1320 return VINF_SUCCESS;
1321}
1322
1323
1324/**
1325 * Reads the Control Register.
1326 */
1327static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1328{
1329 RT_NOREF(pDevIns, offReg);
1330 *pu64Value = pThis->Ctrl.u64;
1331 return VINF_SUCCESS;
1332}
1333
1334
1335/**
1336 * Reads the Exclusion Range Base Address Register.
1337 */
1338static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1339{
1340 RT_NOREF(pDevIns, offReg);
1341 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1342 return VINF_SUCCESS;
1343}
1344
1345
1346/**
1347 * Reads to the Exclusion Range Limit Register.
1348 */
1349static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1350{
1351 RT_NOREF(pDevIns, offReg);
1352 *pu64Value = pThis->ExclRangeLimit.u64;
1353 return VINF_SUCCESS;
1354}
1355
1356
1357/**
1358 * Reads to the Extended Feature Register.
1359 */
1360static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1361{
1362 RT_NOREF(pDevIns, offReg);
1363 *pu64Value = pThis->ExtFeat.u64;
1364 return VINF_SUCCESS;
1365}
1366
1367
1368/**
1369 * Reads to the PPR Log Base Address Register.
1370 */
1371static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1372{
1373 RT_NOREF(pDevIns, offReg);
1374 *pu64Value = pThis->PprLogBaseAddr.u64;
1375 return VINF_SUCCESS;
1376}
1377
1378
1379/**
1380 * Writes the Hardware Event Register (Hi).
1381 */
1382static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1383{
1384 RT_NOREF(pDevIns, offReg);
1385 *pu64Value = pThis->HwEvtHi.u64;
1386 return VINF_SUCCESS;
1387}
1388
1389
1390/**
1391 * Reads the Hardware Event Register (Lo).
1392 */
1393static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1394{
1395 RT_NOREF(pDevIns, offReg);
1396 *pu64Value = pThis->HwEvtLo;
1397 return VINF_SUCCESS;
1398}
1399
1400
1401/**
1402 * Reads the Hardware Event Status Register.
1403 */
1404static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1405{
1406 RT_NOREF(pDevIns, offReg);
1407 *pu64Value = pThis->HwEvtStatus.u64;
1408 return VINF_SUCCESS;
1409}
1410
1411
1412/**
1413 * Reads to the GA Log Base Address Register.
1414 */
1415static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1416{
1417 RT_NOREF(pDevIns, offReg);
1418 *pu64Value = pThis->GALogBaseAddr.u64;
1419 return VINF_SUCCESS;
1420}
1421
1422
1423/**
1424 * Reads to the PPR Log B Base Address Register.
1425 */
1426static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1427{
1428 RT_NOREF(pDevIns, offReg);
1429 *pu64Value = pThis->PprLogBBaseAddr.u64;
1430 return VINF_SUCCESS;
1431}
1432
1433
1434/**
1435 * Reads to the Event Log B Base Address Register.
1436 */
1437static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1438{
1439 RT_NOREF(pDevIns, offReg);
1440 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1441 return VINF_SUCCESS;
1442}
1443
1444
1445/**
1446 * Reads the Device Table Segment Base Address Register.
1447 */
1448static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1449{
1450 RT_NOREF(pDevIns);
1451
1452 /* Figure out which segment is being written. */
1453 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1454 uint8_t const idxSegment = offSegment + 1;
1455 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1456
1457 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1458 return VINF_SUCCESS;
1459}
1460
1461
1462/**
1463 * Reads the Device Specific Feature Extension (DSFX) Register.
1464 */
1465static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1466{
1467 RT_NOREF(pDevIns, offReg);
1468 *pu64Value = pThis->DevSpecificFeat.u64;
1469 return VINF_SUCCESS;
1470}
1471
1472/**
1473 * Reads the Device Specific Control Extension (DSCX) Register.
1474 */
1475static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1476{
1477 RT_NOREF(pDevIns, offReg);
1478 *pu64Value = pThis->DevSpecificCtrl.u64;
1479 return VINF_SUCCESS;
1480}
1481
1482
1483/**
1484 * Reads the Device Specific Status Extension (DSSX) Register.
1485 */
1486static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1487{
1488 RT_NOREF(pDevIns, offReg);
1489 *pu64Value = pThis->DevSpecificStatus.u64;
1490 return VINF_SUCCESS;
1491}
1492
1493
1494/**
1495 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1496 */
1497static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1498{
1499 RT_NOREF(pDevIns, offReg);
1500 uint32_t const uLo = pThis->MiscInfo.au32[0];
1501 uint32_t const uHi = pThis->MiscInfo.au32[1];
1502 *pu64Value = RT_MAKE_U64(uLo, uHi);
1503 return VINF_SUCCESS;
1504}
1505
1506
1507/**
1508 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1509 * Register (32-bit).
1510 */
1511static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1512{
1513 RT_NOREF(pThis, offReg);
1514 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1515 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1516 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1517 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1518 *pu64Value = RT_MAKE_U64(uLo, uHi);
1519 return VINF_SUCCESS;
1520}
1521
1522
1523/**
1524 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1525 */
1526static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1527{
1528 RT_NOREF(pThis, offReg);
1529 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1530 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1531 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1532 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1533 *pu64Value = RT_MAKE_U64(uLo, uHi);
1534 return VINF_SUCCESS;
1535}
1536
1537
1538/**
1539 * Reads the Command Buffer Head Pointer Register.
1540 */
1541static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1542{
1543 RT_NOREF(pDevIns, offReg);
1544 *pu64Value = pThis->CmdBufHeadPtr.u64;
1545 return VINF_SUCCESS;
1546}
1547
1548
1549/**
1550 * Reads the Command Buffer Tail Pointer Register.
1551 */
1552static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1553{
1554 RT_NOREF(pDevIns, offReg);
1555 *pu64Value = pThis->CmdBufTailPtr.u64;
1556 return VINF_SUCCESS;
1557}
1558
1559
1560/**
1561 * Reads the Event Log Head Pointer Register.
1562 */
1563static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1564{
1565 RT_NOREF(pDevIns, offReg);
1566 *pu64Value = pThis->EvtLogHeadPtr.u64;
1567 return VINF_SUCCESS;
1568}
1569
1570
1571/**
1572 * Reads the Event Log Tail Pointer Register.
1573 */
1574static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1575{
1576 RT_NOREF(pDevIns, offReg);
1577 *pu64Value = pThis->EvtLogTailPtr.u64;
1578 return VINF_SUCCESS;
1579}
1580
1581
1582/**
1583 * Reads the Status Register.
1584 */
1585static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1586{
1587 RT_NOREF(pDevIns, offReg);
1588 *pu64Value = pThis->Status.u64;
1589 return VINF_SUCCESS;
1590}
1591
1592
1593/**
1594 * Writes the Device Table Base Address Register.
1595 */
1596static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1597{
1598 RT_NOREF(pDevIns, offReg);
1599
1600 /* Mask out all unrecognized bits. */
1601 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
1602
1603 /* Update the register. */
1604 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
1605
1606 /* Paranoia. */
1607 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
1608 return VINF_SUCCESS;
1609}
1610
1611
1612/**
1613 * Writes the Command Buffer Base Address Register.
1614 */
1615static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1616{
1617 RT_NOREF(pDevIns, offReg);
1618
1619 /*
1620 * While this is not explicitly specified like the event log base address register,
1621 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
1622 * Inconsistent specs :/
1623 */
1624 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1625 if (Status.n.u1CmdBufRunning)
1626 {
1627 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1628 return VINF_SUCCESS;
1629 }
1630
1631 /* Mask out all unrecognized bits. */
1632 CMD_BUF_BAR_T CmdBufBaseAddr;
1633 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
1634
1635 /* Validate the length. */
1636 if (CmdBufBaseAddr.n.u4Len >= 8)
1637 {
1638 /* Update the register. */
1639 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
1640
1641 /*
1642 * Writing the command buffer base address, clears the command buffer head and tail pointers.
1643 * See AMD IOMMU spec. 2.4 "Commands".
1644 */
1645 pThis->CmdBufHeadPtr.u64 = 0;
1646 pThis->CmdBufTailPtr.u64 = 0;
1647 }
1648 else
1649 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
1650
1651 return VINF_SUCCESS;
1652}
1653
1654
1655/**
1656 * Writes the Event Log Base Address Register.
1657 */
1658static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1659{
1660 RT_NOREF(pDevIns, offReg);
1661
1662 /*
1663 * IOMMU behavior is undefined when software writes this register when event logging is running.
1664 * In our emulation, we ignore the write entirely.
1665 * See AMD IOMMU spec. "Event Log Base Address Register".
1666 */
1667 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1668 if (Status.n.u1EvtLogRunning)
1669 {
1670 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
1671 return VINF_SUCCESS;
1672 }
1673
1674 /* Mask out all unrecognized bits. */
1675 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
1676 EVT_LOG_BAR_T EvtLogBaseAddr;
1677 EvtLogBaseAddr.u64 = u64Value;
1678
1679 /* Validate the length. */
1680 if (EvtLogBaseAddr.n.u4Len >= 8)
1681 {
1682 /* Update the register. */
1683 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
1684
1685 /*
1686 * Writing the event log base address, clears the event log head and tail pointers.
1687 * See AMD IOMMU spec. 2.5 "Event Logging".
1688 */
1689 pThis->EvtLogHeadPtr.u64 = 0;
1690 pThis->EvtLogTailPtr.u64 = 0;
1691 }
1692 else
1693 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
1694
1695 return VINF_SUCCESS;
1696}
1697
1698
1699/**
1700 * Writes the Control Register.
1701 */
1702static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1703{
1704 RT_NOREF(pDevIns, offReg);
1705
1706 /* Mask out all unrecognized bits. */
1707 u64Value &= IOMMU_CTRL_VALID_MASK;
1708 IOMMU_CTRL_T NewCtrl;
1709 NewCtrl.u64 = u64Value;
1710
1711 /* Ensure the device table segments are within limits. */
1712 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
1713 {
1714 IOMMU_CTRL_T const OldCtrl = iommuAmdGetCtrl(pThis);
1715
1716 /* Update the register. */
1717 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
1718
1719 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
1720 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
1721
1722 /* Enable or disable event logging when the bit transitions. */
1723 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
1724 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
1725 if ( fOldEvtLogEn != fNewEvtLogEn
1726 || fOldIommuEn != fNewIommuEn)
1727 {
1728 if ( fNewIommuEn
1729 && fNewEvtLogEn)
1730 {
1731 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
1732 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
1733 }
1734 else
1735 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
1736 }
1737
1738 /* Enable or disable command buffer processing when the bit transitions. */
1739 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
1740 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
1741 if ( fOldCmdBufEn != fNewCmdBufEn
1742 || fOldIommuEn != fNewIommuEn)
1743 {
1744 if ( fNewCmdBufEn
1745 && fNewIommuEn)
1746 {
1747 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
1748 LogFunc(("Command buffer enabled\n"));
1749
1750 /* Wake up the command thread to start processing commands. */
1751 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1752 }
1753 else
1754 {
1755 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
1756 LogFunc(("Command buffer disabled\n"));
1757 }
1758 }
1759 }
1760 else
1761 {
1762 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
1763 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
1764 }
1765
1766 return VINF_SUCCESS;
1767}
1768
1769
1770/**
1771 * Writes to the Exclusion Range Base Address Register.
1772 */
1773static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1774{
1775 RT_NOREF(pDevIns, offReg);
1776 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
1777 return VINF_SUCCESS;
1778}
1779
1780
1781/**
1782 * Writes to the Exclusion Range Limit Register.
1783 */
1784static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1785{
1786 RT_NOREF(pDevIns, offReg);
1787 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
1788 u64Value |= UINT64_C(0xfff);
1789 pThis->ExclRangeLimit.u64 = u64Value;
1790 return VINF_SUCCESS;
1791}
1792
1793
1794/**
1795 * Writes the Hardware Event Register (Hi).
1796 */
1797static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1798{
1799 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1800 RT_NOREF(pDevIns, offReg);
1801 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
1802 pThis->HwEvtHi.u64 = u64Value;
1803 return VINF_SUCCESS;
1804}
1805
1806
1807/**
1808 * Writes the Hardware Event Register (Lo).
1809 */
1810static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1811{
1812 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
1813 RT_NOREF(pDevIns, offReg);
1814 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
1815 pThis->HwEvtLo = u64Value;
1816 return VINF_SUCCESS;
1817}
1818
1819
1820/**
1821 * Writes the Hardware Event Status Register.
1822 */
1823static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1824{
1825 RT_NOREF(pDevIns, offReg);
1826
1827 /* Mask out all unrecognized bits. */
1828 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
1829
1830 /*
1831 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
1832 * If the current status bits or the bits being written are both 0, we've nothing to do.
1833 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
1834 */
1835 uint64_t HwStatus = pThis->HwEvtStatus.u64;
1836 if (!(HwStatus & RT_BIT(0)))
1837 return VINF_SUCCESS;
1838 if (u64Value & HwStatus & RT_BIT_64(0))
1839 HwStatus &= ~RT_BIT_64(0);
1840 if (u64Value & HwStatus & RT_BIT_64(1))
1841 HwStatus &= ~RT_BIT_64(1);
1842
1843 /* Update the register. */
1844 pThis->HwEvtStatus.u64 = HwStatus;
1845 return VINF_SUCCESS;
1846}
1847
1848
1849/**
1850 * Writes the Device Table Segment Base Address Register.
1851 */
1852static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1853{
1854 RT_NOREF(pDevIns);
1855
1856 /* Figure out which segment is being written. */
1857 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1858 uint8_t const idxSegment = offSegment + 1;
1859 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1860
1861 /* Mask out all unrecognized bits. */
1862 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
1863 DEV_TAB_BAR_T DevTabSegBar;
1864 DevTabSegBar.u64 = u64Value;
1865
1866 /* Validate the size. */
1867 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
1868 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
1869 if (uSegSize <= uMaxSegSize)
1870 {
1871 /* Update the register. */
1872 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
1873 }
1874 else
1875 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
1876
1877 return VINF_SUCCESS;
1878}
1879
1880
1881/**
1882 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1883 */
1884static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1885{
1886 RT_NOREF(pDevIns, offReg);
1887
1888 /* MSI Vector Register 0 is read-only. */
1889 /* MSI Vector Register 1. */
1890 uint32_t const uReg = u64Value >> 32;
1891 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
1892 return VINF_SUCCESS;
1893}
1894
1895
1896/**
1897 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
1898 * Register (32-bit).
1899 */
1900static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1901{
1902 RT_NOREF(pThis, offReg);
1903 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1904 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1905
1906 /* MSI capability header. */
1907 {
1908 uint32_t const uReg = u64Value;
1909 MSI_CAP_HDR_T MsiCapHdr;
1910 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1911 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
1912 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
1913 }
1914
1915 /* MSI Address Lo. */
1916 {
1917 uint32_t const uReg = u64Value >> 32;
1918 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
1919 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
1920 }
1921
1922 return VINF_SUCCESS;
1923}
1924
1925
1926/**
1927 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
1928 */
1929static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1930{
1931 RT_NOREF(pThis, offReg);
1932 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1933 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1934
1935 /* MSI Address Hi. */
1936 {
1937 uint32_t const uReg = u64Value;
1938 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
1939 }
1940
1941 /* MSI Data. */
1942 {
1943 uint32_t const uReg = u64Value >> 32;
1944 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
1945 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
1946 }
1947
1948 return VINF_SUCCESS;
1949}
1950
1951
1952/**
1953 * Writes the Command Buffer Head Pointer Register.
1954 */
1955static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1956{
1957 RT_NOREF(pDevIns, offReg);
1958
1959 /*
1960 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
1961 * In our emulation, we ignore the write entirely.
1962 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
1963 */
1964 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
1965 if (Status.n.u1CmdBufRunning)
1966 {
1967 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
1968 return VINF_SUCCESS;
1969 }
1970
1971 /*
1972 * IOMMU behavior is undefined when software writes a value outside the buffer length.
1973 * In our emulation, we ignore the write entirely.
1974 */
1975 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
1976 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
1977 Assert(cbBuf <= _512K);
1978 if (offBuf >= cbBuf)
1979 {
1980 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
1981 return VINF_SUCCESS;
1982 }
1983
1984 /* Update the register. */
1985 pThis->CmdBufHeadPtr.au32[0] = offBuf;
1986
1987 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
1988
1989 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
1990 return VINF_SUCCESS;
1991}
1992
1993
1994/**
1995 * Writes the Command Buffer Tail Pointer Register.
1996 */
1997static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1998{
1999 RT_NOREF(pDevIns, offReg);
2000
2001 /*
2002 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2003 * In our emulation, we ignore the write entirely.
2004 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2005 */
2006 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2007 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2008 Assert(cbBuf <= _512K);
2009 if (offBuf >= cbBuf)
2010 {
2011 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2012 return VINF_SUCCESS;
2013 }
2014
2015 /*
2016 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2017 * head pointer after adding one or more commands to the buffer.
2018 *
2019 * However, we cannot enforce this strictly because it's legal for software to shrink the
2020 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2021 * at 0). Software might even make the queue empty by making head and tail equal which is
2022 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2023 * in the foot here. As long as we make sure the offset value is within the circular buffer
2024 * bounds (which we do by masking bits above) it should be sufficient.
2025 */
2026 pThis->CmdBufTailPtr.au32[0] = offBuf;
2027
2028 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2029
2030 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2031 return VINF_SUCCESS;
2032}
2033
2034
2035/**
2036 * Writes the Event Log Head Pointer Register.
2037 */
2038static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2039{
2040 RT_NOREF(pDevIns, offReg);
2041
2042 /*
2043 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2044 * In our emulation, we ignore the write entirely.
2045 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2046 */
2047 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2048 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2049 Assert(cbBuf <= _512K);
2050 if (offBuf >= cbBuf)
2051 {
2052 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2053 return VINF_SUCCESS;
2054 }
2055
2056 /* Update the register. */
2057 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2058
2059 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2060 return VINF_SUCCESS;
2061}
2062
2063
2064/**
2065 * Writes the Event Log Tail Pointer Register.
2066 */
2067static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2068{
2069 RT_NOREF(pDevIns, offReg);
2070 NOREF(pThis);
2071
2072 /*
2073 * IOMMU behavior is undefined when software writes this register when the event log is running.
2074 * In our emulation, we ignore the write entirely.
2075 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2076 */
2077 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2078 if (Status.n.u1EvtLogRunning)
2079 {
2080 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2081 return VINF_SUCCESS;
2082 }
2083
2084 /*
2085 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2086 * In our emulation, we ignore the write entirely.
2087 */
2088 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2089 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2090 Assert(cbBuf <= _512K);
2091 if (offBuf >= cbBuf)
2092 {
2093 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2094 return VINF_SUCCESS;
2095 }
2096
2097 /* Update the register. */
2098 pThis->EvtLogTailPtr.au32[0] = offBuf;
2099
2100 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2101 return VINF_SUCCESS;
2102}
2103
2104
2105/**
2106 * Writes the Status Register.
2107 */
2108static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2109{
2110 RT_NOREF(pDevIns, offReg);
2111
2112 /* Mask out all unrecognized bits. */
2113 u64Value &= IOMMU_STATUS_VALID_MASK;
2114
2115 /*
2116 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2117 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2118 */
2119 IOMMU_STATUS_T const OldStatus = iommuAmdGetStatus(pThis);
2120 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2121 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2122 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2123
2124 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2125
2126 /* Update the register. */
2127 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2128 return VINF_SUCCESS;
2129}
2130
2131
2132/**
2133 * Register access table 0.
2134 * The MMIO offset of each entry must be a multiple of 8!
2135 */
2136static const IOMMUREGACC g_aRegAccess0[] =
2137{
2138 /* MMIO off. Register name Read function Write function */
2139 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2140 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2141 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2142 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2143 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2144 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2145 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2146 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2147 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2148 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2149 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2150 { /* 0x58 */ NULL, NULL, NULL },
2151
2152 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2153 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2154 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2155 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2156 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2157 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2158 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2159 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2160 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2161 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2162 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2163 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2164 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2165 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2166 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2167 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2168
2169 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2170 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2171 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2172 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2173
2174 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2175 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2176 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2177 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2178 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2179 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2180 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2181
2182 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2183 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2184 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2185
2186 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2187 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2188 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2189 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2190
2191 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2192 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2193 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2194};
2195AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2196
2197/**
2198 * Register access table 1.
2199 * The MMIO offset of each entry must be a multiple of 8!
2200 */
2201static const IOMMUREGACC g_aRegAccess1[] =
2202{
2203 /* MMIO offset Register name Read function Write function */
2204 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2205 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2206 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2207 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2208 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2209 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2210 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2211 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2212 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2213 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2214 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2215 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2216};
2217AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2218
2219/**
2220 * Register access table 2.
2221 * The MMIO offset of each entry must be a multiple of 8!
2222 */
2223static const IOMMUREGACC g_aRegAccess2[] =
2224{
2225 /* MMIO offset Register name Read Function Write function */
2226 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2227
2228 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2229 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2230 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2231 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2232
2233 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2234 { /* 0x2028 */ NULL, NULL, NULL },
2235
2236 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2237 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2238
2239 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2240 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2241
2242 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2243 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2244
2245 { /* 0x2060 */ NULL, NULL, NULL },
2246 { /* 0x2068 */ NULL, NULL, NULL },
2247
2248 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2249 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2250
2251 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2252 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2253 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2254};
2255AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2256
2257
2258/**
2259 * Gets the register access structure given its MMIO offset.
2260 *
2261 * @returns The register access structure, or NULL if the offset is invalid.
2262 * @param off The MMIO offset of the register being accessed.
2263 */
2264static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2265{
2266 /* Figure out which table the register belongs to and validate its index. */
2267 PCIOMMUREGACC pReg;
2268 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2269 {
2270 uint32_t const idxReg = off >> 3;
2271 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2272 pReg = &g_aRegAccess0[idxReg];
2273 }
2274 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2275 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2276 {
2277 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2278 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2279 pReg = &g_aRegAccess1[idxReg];
2280 }
2281 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2282 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2283 {
2284 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2285 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2286 pReg = &g_aRegAccess2[idxReg];
2287 }
2288 else
2289 return NULL;
2290 return pReg;
2291}
2292
2293
2294/**
2295 * Writes an IOMMU register (32-bit and 64-bit).
2296 *
2297 * @returns Strict VBox status code.
2298 * @param pDevIns The IOMMU device instance.
2299 * @param off MMIO byte offset to the register.
2300 * @param cb The size of the write access.
2301 * @param uValue The value being written.
2302 *
2303 * @thread EMT.
2304 */
2305static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2306{
2307 /*
2308 * Validate the access in case of IOM bug or incorrect assumption.
2309 */
2310 Assert(off < IOMMU_MMIO_REGION_SIZE);
2311 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2312 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2313
2314 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2315
2316 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2317 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2318 if (pReg)
2319 { /* likely */ }
2320 else
2321 {
2322 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2323 return VINF_SUCCESS;
2324 }
2325
2326 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2327 if (pReg->pfnWrite)
2328 { /* likely */ }
2329 else
2330 {
2331 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2332 return VINF_SUCCESS;
2333 }
2334
2335 /*
2336 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2337 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2338 * consecutive 32-bit registers.
2339 */
2340 if (cb == 8)
2341 {
2342 if (!(off & 7))
2343 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
2344
2345 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2346 return VINF_SUCCESS;
2347 }
2348
2349 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2350 Assert(cb == 4);
2351 if (!(off & 7))
2352 {
2353 /*
2354 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2355 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2356 */
2357 uint64_t u64Read;
2358 if (pReg->pfnRead)
2359 {
2360 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2361 if (RT_FAILURE(rcStrict))
2362 {
2363 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2364 return rcStrict;
2365 }
2366 }
2367 else
2368 u64Read = 0;
2369
2370 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2371 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
2372 }
2373
2374 /*
2375 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2376 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2377 */
2378 Assert(!(off & 3));
2379 Assert(off & 7);
2380 Assert(off >= 4);
2381 uint64_t u64Read;
2382 if (pReg->pfnRead)
2383 {
2384 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2385 if (RT_FAILURE(rcStrict))
2386 {
2387 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2388 return rcStrict;
2389 }
2390 }
2391 else
2392 u64Read = 0;
2393
2394 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2395 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2396}
2397
2398
2399/**
2400 * Reads an IOMMU register (64-bit) given its MMIO offset.
2401 *
2402 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2403 * boundary include the lower half of the subsequent register.
2404 *
2405 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2406 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2407 * software will only perform 32-bit reads on those 32-bit registers that are
2408 * aligned on 8-byte boundaries.
2409 *
2410 * @returns Strict VBox status code.
2411 * @param pDevIns The IOMMU device instance.
2412 * @param off The MMIO offset of the register in bytes.
2413 * @param puResult Where to store the value being read.
2414 *
2415 * @thread EMT.
2416 */
2417static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2418{
2419 Assert(off < IOMMU_MMIO_REGION_SIZE);
2420 Assert(!(off & 7) || !(off & 3));
2421
2422 Log4Func(("off=%#x\n", off));
2423
2424 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2425 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2426 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2427
2428 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2429 if (pReg)
2430 { /* likely */ }
2431 else
2432 {
2433 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2434 return VINF_IOM_MMIO_UNUSED_FF;
2435 }
2436
2437 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2438 if (pReg->pfnRead)
2439 { /* likely */ }
2440 else
2441 {
2442 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2443 return VINF_IOM_MMIO_UNUSED_00;
2444 }
2445
2446 /*
2447 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2448 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2449 */
2450 if (!(off & 7))
2451 return pReg->pfnRead(pDevIns, pThis, off, puResult);
2452
2453 /*
2454 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2455 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2456 */
2457 Assert(!(off & 3));
2458 Assert(off & 7);
2459 Assert(off >= 4);
2460 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2461 if (RT_SUCCESS(rcStrict))
2462 *puResult >>= 32;
2463 else
2464 {
2465 *puResult = 0;
2466 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2467 }
2468
2469 return rcStrict;
2470}
2471
2472
2473/**
2474 * Raises the MSI interrupt for the IOMMU device.
2475 *
2476 * @param pDevIns The IOMMU device instance.
2477 *
2478 * @thread Any.
2479 * @remarks The IOMMU lock may or may not be held.
2480 */
2481static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2482{
2483 LogFlowFunc(("\n"));
2484 if (iommuAmdIsMsiEnabled(pDevIns))
2485 {
2486 LogFunc(("Raising MSI\n"));
2487 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2488 }
2489}
2490
2491#if 0
2492/**
2493 * Clears the MSI interrupt for the IOMMU device.
2494 *
2495 * @param pDevIns The IOMMU device instance.
2496 *
2497 * @thread Any.
2498 * @remarks The IOMMU lock may or may not be held.
2499 */
2500static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2501{
2502 if (iommuAmdIsMsiEnabled(pDevIns))
2503 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2504}
2505#endif
2506
2507/**
2508 * Writes an entry to the event log in memory.
2509 *
2510 * @returns VBox status code.
2511 * @param pDevIns The IOMMU device instance.
2512 * @param pEvent The event to log.
2513 *
2514 * @thread Any.
2515 * @remarks The IOMMU lock must be held while calling this function.
2516 */
2517static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2518{
2519 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2520 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2521
2522 IOMMU_LOCK_NORET(pDevIns, pThisCC);
2523
2524 /* Check if event logging is active and the log has not overflowed. */
2525 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
2526 if ( Status.n.u1EvtLogRunning
2527 && !Status.n.u1EvtOverflow)
2528 {
2529 uint32_t const cbEvt = sizeof(*pEvent);
2530
2531 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2532 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2533 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2534
2535 /* Ensure we have space in the event log. */
2536 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2537 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2538 if (cEvts + 1 < cMaxEvts)
2539 {
2540 /* Write the event log entry to memory. */
2541 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2542 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2543 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2544 if (RT_FAILURE(rc))
2545 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2546
2547 /* Increment the event log tail pointer. */
2548 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2549 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2550
2551 /* Indicate that an event log entry was written. */
2552 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2553
2554 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2555 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2556 if (Ctrl.n.u1EvtIntrEn)
2557 iommuAmdMsiInterruptRaise(pDevIns);
2558 }
2559 else
2560 {
2561 /* Indicate that the event log has overflowed. */
2562 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2563
2564 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2565 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
2566 if (Ctrl.n.u1EvtIntrEn)
2567 iommuAmdMsiInterruptRaise(pDevIns);
2568 }
2569 }
2570
2571 IOMMU_UNLOCK(pDevIns, pThisCC);
2572
2573 return VINF_SUCCESS;
2574}
2575
2576
2577/**
2578 * Sets an event in the hardware error registers.
2579 *
2580 * @param pDevIns The IOMMU device instance.
2581 * @param pEvent The event.
2582 *
2583 * @thread Any.
2584 */
2585static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2586{
2587 IOMMU_ASSERT_LOCKED(pDevIns);
2588
2589 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2590 if (pThis->ExtFeat.n.u1HwErrorSup)
2591 {
2592 if (pThis->HwEvtStatus.n.u1Valid)
2593 pThis->HwEvtStatus.n.u1Overflow = 1;
2594 pThis->HwEvtStatus.n.u1Valid = 1;
2595 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2596 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2597 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2598 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2599 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2600 }
2601}
2602
2603
2604/**
2605 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2606 *
2607 * @param uDevId The device ID (bus, device, function).
2608 * @param uDomainId The domain ID.
2609 * @param GCPhysPtEntity The system physical address of the page table
2610 * entity.
2611 * @param enmOp The IOMMU operation being performed.
2612 * @param pEvtPageTabHwErr Where to store the initialized event.
2613 */
2614static void iommuAmdPageTabHwErrorEventInit(uint16_t uDevId, uint16_t uDomainId, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2615 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2616{
2617 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2618 pEvtPageTabHwErr->n.u16DevId = uDevId;
2619 pEvtPageTabHwErr->n.u16DomainOrPasidLo = uDomainId;
2620 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
2621 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2622 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2623 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2624 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2625 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
2626 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
2627}
2628
2629
2630/**
2631 * Raises a PAGE_TAB_HARDWARE_ERROR event.
2632 *
2633 * @param pDevIns The IOMMU device instance.
2634 * @param enmOp The IOMMU operation being performed.
2635 * @param pEvtPageTabHwErr The page table hardware error event.
2636 *
2637 * @thread Any.
2638 */
2639static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2640{
2641 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
2642 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
2643
2644 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2645 IOMMU_LOCK_NORET(pDevIns, pThisCC);
2646
2647 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
2648 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
2649 if (enmOp != IOMMUOP_CMD)
2650 iommuAmdSetPciTargetAbort(pDevIns);
2651
2652 IOMMU_UNLOCK(pDevIns, pThisCC);
2653
2654 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. uDevId=%#x uDomainId=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
2655 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
2656 pEvtPageTabHwErr->n.u2Type));
2657}
2658
2659
2660#ifdef IN_RING3
2661/**
2662 * Initializes a COMMAND_HARDWARE_ERROR event.
2663 *
2664 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
2665 * @param pEvtCmdHwErr Where to store the initialized event.
2666 */
2667static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2668{
2669 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
2670 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
2671 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
2672 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
2673}
2674
2675
2676/**
2677 * Raises a COMMAND_HARDWARE_ERROR event.
2678 *
2679 * @param pDevIns The IOMMU device instance.
2680 * @param pEvtCmdHwErr The command hardware error event.
2681 *
2682 * @thread Any.
2683 */
2684static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
2685{
2686 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
2687 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
2688 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2689
2690 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2691 IOMMU_LOCK_NORET(pDevIns, pThisCC);
2692
2693 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
2694 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
2695 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2696
2697 IOMMU_UNLOCK(pDevIns, pThisCC);
2698
2699 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
2700}
2701#endif /* IN_RING3 */
2702
2703
2704/**
2705 * Initializes a DEV_TAB_HARDWARE_ERROR event.
2706 *
2707 * @param uDevId The device ID (bus, device, function).
2708 * @param GCPhysDte The system physical address of the failed device table
2709 * access.
2710 * @param enmOp The IOMMU operation being performed.
2711 * @param pEvtDevTabHwErr Where to store the initialized event.
2712 */
2713static void iommuAmdDevTabHwErrorEventInit(uint16_t uDevId, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
2714 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2715{
2716 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
2717 pEvtDevTabHwErr->n.u16DevId = uDevId;
2718 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2719 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
2720 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2721 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2722 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
2723 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
2724 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
2725}
2726
2727
2728/**
2729 * Raises a DEV_TAB_HARDWARE_ERROR event.
2730 *
2731 * @param pDevIns The IOMMU device instance.
2732 * @param enmOp The IOMMU operation being performed.
2733 * @param pEvtDevTabHwErr The device table hardware error event.
2734 *
2735 * @thread Any.
2736 */
2737static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
2738{
2739 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
2740 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
2741
2742 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2743 IOMMU_LOCK_NORET(pDevIns, pThisCC);
2744
2745 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
2746 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
2747 if (enmOp != IOMMUOP_CMD)
2748 iommuAmdSetPciTargetAbort(pDevIns);
2749
2750 IOMMU_UNLOCK(pDevIns, pThisCC);
2751
2752 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. uDevId=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
2753 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
2754}
2755
2756
2757#ifdef IN_RING3
2758/**
2759 * Initializes an ILLEGAL_COMMAND_ERROR event.
2760 *
2761 * @param GCPhysCmd The system physical address of the failed command
2762 * access.
2763 * @param pEvtIllegalCmd Where to store the initialized event.
2764 */
2765static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2766{
2767 Assert(!(GCPhysCmd & UINT64_C(0xf)));
2768 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
2769 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
2770 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
2771}
2772
2773
2774/**
2775 * Raises an ILLEGAL_COMMAND_ERROR event.
2776 *
2777 * @param pDevIns The IOMMU device instance.
2778 * @param pEvtIllegalCmd The illegal command error event.
2779 */
2780static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
2781{
2782 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2783 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
2784 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2785
2786 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2787 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2788
2789 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
2790}
2791#endif /* IN_RING3 */
2792
2793
2794/**
2795 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
2796 *
2797 * @param uDevId The device ID (bus, device, function).
2798 * @param uIova The I/O virtual address.
2799 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
2800 * event was caused by an invalid level encoding in the
2801 * DTE.
2802 * @param enmOp The IOMMU operation being performed.
2803 * @param pEvtIllegalDte Where to store the initialized event.
2804 */
2805static void iommuAmdIllegalDteEventInit(uint16_t uDevId, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
2806 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
2807{
2808 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
2809 pEvtIllegalDte->n.u16DevId = uDevId;
2810 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2811 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2812 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
2813 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2814 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
2815 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
2816 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
2817 * IOMMU spec here but not for this field for I/O page fault event. */
2818 Assert(!(uIova & UINT64_C(0x3)));
2819}
2820
2821
2822/**
2823 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
2824 *
2825 * @param pDevIns The IOMMU instance data.
2826 * @param enmOp The IOMMU operation being performed.
2827 * @param pEvtIllegalDte The illegal device table entry event.
2828 * @param enmEvtType The illegal device table entry event type.
2829 *
2830 * @thread Any.
2831 */
2832static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
2833 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
2834{
2835 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
2836 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
2837
2838 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2839 if (enmOp != IOMMUOP_CMD)
2840 iommuAmdSetPciTargetAbort(pDevIns);
2841
2842 LogFunc(("Raised ILLEGAL_DTE_EVENT. uDevId=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
2843 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
2844 NOREF(enmEvtType);
2845}
2846
2847
2848/**
2849 * Initializes an IO_PAGE_FAULT event.
2850 *
2851 * @param uDevId The device ID (bus, device, function).
2852 * @param uDomainId The domain ID.
2853 * @param uIova The I/O virtual address being accessed.
2854 * @param fPresent Transaction to a page marked as present (including
2855 * DTE.V=1) or interrupt marked as remapped
2856 * (IRTE.RemapEn=1).
2857 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
2858 * the I/O page fault was caused by invalid level
2859 * encoding.
2860 * @param fPermDenied Permission denied for the address being accessed.
2861 * @param enmOp The IOMMU operation being performed.
2862 * @param pEvtIoPageFault Where to store the initialized event.
2863 */
2864static void iommuAmdIoPageFaultEventInit(uint16_t uDevId, uint16_t uDomainId, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
2865 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
2866{
2867 Assert(!fPermDenied || fPresent);
2868 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
2869 pEvtIoPageFault->n.u16DevId = uDevId;
2870 //pEvtIoPageFault->n.u4PasidHi = 0;
2871 pEvtIoPageFault->n.u16DomainOrPasidLo = uDomainId;
2872 //pEvtIoPageFault->n.u1GuestOrNested = 0;
2873 //pEvtIoPageFault->n.u1NoExecute = 0;
2874 //pEvtIoPageFault->n.u1User = 0;
2875 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
2876 pEvtIoPageFault->n.u1Present = fPresent;
2877 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
2878 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
2879 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
2880 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
2881 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
2882 pEvtIoPageFault->n.u64Addr = uIova;
2883}
2884
2885
2886/**
2887 * Raises an IO_PAGE_FAULT event.
2888 *
2889 * @param pDevIns The IOMMU instance data.
2890 * @param fIoDevFlags The I/O device flags, see IOMMU_DEV_F_XXX.
2891 * @param pIrte The interrupt remapping table entry, can be NULL.
2892 * @param enmOp The IOMMU operation being performed.
2893 * @param pEvtIoPageFault The I/O page fault event.
2894 * @param enmEvtType The I/O page fault event type.
2895 *
2896 * @thread Any.
2897 */
2898static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
2899 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
2900{
2901 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
2902 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
2903
2904#ifdef IOMMU_WITH_IOTLBE_CACHE
2905# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheSetFlags((a_pDevIns), (a_DevId), \
2906 IOMMU_DEV_F_IO_PAGE_FAULT_RAISED)
2907#else
2908# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
2909#endif
2910
2911 bool fSuppressEvtLogging = false;
2912 if ( enmOp == IOMMUOP_MEM_READ
2913 || enmOp == IOMMUOP_MEM_WRITE)
2914 {
2915 uint16_t const fSuppressIopf = IOMMU_DEV_F_VALID | IOMMU_DEV_F_SUPPRESS_IOPF | IOMMU_DEV_F_IO_PAGE_FAULT_RAISED;
2916 uint16_t const fSuppressAllIopf = IOMMU_DEV_F_VALID | IOMMU_DEV_F_SUPPRESS_ALL_IOPF;
2917 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
2918 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
2919 {
2920 fSuppressEvtLogging = true;
2921 }
2922 }
2923 else if (enmOp == IOMMUOP_INTR_REQ)
2924 {
2925 uint16_t const fSuppressIopf = IOMMU_DEV_F_VALID | IOMMU_DEV_F_INTR_MAP_VALID | IOMMU_DEV_F_IGNORE_UNMAPPED_INTR;
2926 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
2927 fSuppressEvtLogging = true;
2928 else if (pIrte)
2929 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
2930 }
2931 /* else: Events are never suppressed for commands. */
2932
2933 switch (enmEvtType)
2934 {
2935 case kIoPageFaultType_PermDenied:
2936 {
2937 /* Cannot be triggered by a command. */
2938 Assert(enmOp != IOMMUOP_CMD);
2939 RT_FALL_THRU();
2940 }
2941 case kIoPageFaultType_DteRsvdPagingMode:
2942 case kIoPageFaultType_PteInvalidPageSize:
2943 case kIoPageFaultType_PteInvalidLvlEncoding:
2944 case kIoPageFaultType_SkippedLevelIovaNotZero:
2945 case kIoPageFaultType_PteRsvdNotZero:
2946 case kIoPageFaultType_PteValidNotSet:
2947 case kIoPageFaultType_DteTranslationDisabled:
2948 case kIoPageFaultType_PasidInvalidRange:
2949 {
2950 /*
2951 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
2952 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
2953 */
2954 if (enmOp != IOMMUOP_TRANSLATE_REQ)
2955 {
2956 if (!fSuppressEvtLogging)
2957 {
2958 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2959 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
2960 }
2961 if (enmOp != IOMMUOP_CMD)
2962 iommuAmdSetPciTargetAbort(pDevIns);
2963 }
2964 break;
2965 }
2966
2967 case kIoPageFaultType_UserSupervisor:
2968 {
2969 /* Access is blocked and only creates an event log entry. */
2970 if (!fSuppressEvtLogging)
2971 {
2972 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2973 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
2974 }
2975 break;
2976 }
2977
2978 case kIoPageFaultType_IrteAddrInvalid:
2979 case kIoPageFaultType_IrteRsvdNotZero:
2980 case kIoPageFaultType_IrteRemapEn:
2981 case kIoPageFaultType_IrteRsvdIntType:
2982 case kIoPageFaultType_IntrReqAborted:
2983 case kIoPageFaultType_IntrWithPasid:
2984 {
2985 /* Only trigerred by interrupt requests. */
2986 Assert(enmOp == IOMMUOP_INTR_REQ);
2987 if (!fSuppressEvtLogging)
2988 {
2989 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
2990 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
2991 }
2992 iommuAmdSetPciTargetAbort(pDevIns);
2993 break;
2994 }
2995
2996 case kIoPageFaultType_SmiFilterMismatch:
2997 {
2998 /* Not supported and probably will never be, assert. */
2999 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3000 break;
3001 }
3002
3003 case kIoPageFaultType_DevId_Invalid:
3004 {
3005 /* Cannot be triggered by a command. */
3006 Assert(enmOp != IOMMUOP_CMD);
3007 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3008 if (!fSuppressEvtLogging)
3009 {
3010 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3011 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3012 }
3013 if ( enmOp == IOMMUOP_MEM_READ
3014 || enmOp == IOMMUOP_MEM_WRITE)
3015 iommuAmdSetPciTargetAbort(pDevIns);
3016 break;
3017 }
3018 }
3019
3020#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3021}
3022
3023
3024/**
3025 * Raises an IO_PAGE_FAULT event given the DTE.
3026 *
3027 * @param pDevIns The IOMMU instance data.
3028 * @param pDte The device table entry.
3029 * @param pIrte The interrupt remapping table entry, can be NULL.
3030 * @param enmOp The IOMMU operation being performed.
3031 * @param pEvtIoPageFault The I/O page fault event.
3032 * @param enmEvtType The I/O page fault event type.
3033 *
3034 * @thread Any.
3035 */
3036static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3037 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3038{
3039 Assert(pDte);
3040 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3041 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3042}
3043
3044
3045/**
3046 * Reads a device table entry for the given the device ID.
3047 *
3048 * @returns VBox status code.
3049 * @param pDevIns The IOMMU device instance.
3050 * @param uDevId The device ID (bus, device, function).
3051 * @param enmOp The IOMMU operation being performed.
3052 * @param pDte Where to store the device table entry.
3053 *
3054 * @thread Any.
3055 */
3056static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PDTE_T pDte)
3057{
3058 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3059 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3060
3061 IOMMU_LOCK(pDevIns, pThisCC);
3062
3063 /* Figure out which device table segment is being accessed. */
3064 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3065 uint8_t const idxSegsEn = Ctrl.n.u3DevTabSegEn;
3066 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3067
3068 uint8_t const idxSeg = (uDevId & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3069 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3070 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3071
3072 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3073 uint32_t const offDte = (uDevId & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3074 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3075
3076 /* Ensure the DTE falls completely within the device table segment. */
3077 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3078
3079 IOMMU_UNLOCK(pDevIns, pThisCC);
3080
3081 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3082 {
3083 /* Read the device table entry from guest memory. */
3084 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3085 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3086 if (RT_SUCCESS(rc))
3087 return rc;
3088
3089 /* Raise a device table hardware error. */
3090 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3091
3092 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3093 iommuAmdDevTabHwErrorEventInit(uDevId, GCPhysDte, enmOp, &EvtDevTabHwErr);
3094 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3095 return VERR_IOMMU_DTE_READ_FAILED;
3096 }
3097
3098 /* Raise an I/O page fault for out-of-bounds acccess. */
3099 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3100 iommuAmdIoPageFaultEventInit(uDevId, 0 /* uDomainId */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3101 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3102 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3103 kIoPageFaultType_DevId_Invalid);
3104 return VERR_IOMMU_DTE_BAD_OFFSET;
3105}
3106
3107
3108/**
3109 * Performs pre-translation checks for the given device table entry.
3110 *
3111 * @returns VBox status code.
3112 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3113 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3114 * translation is disabled.
3115 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3116 * corresponding event was raised.
3117 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3118 * permissions.
3119 *
3120 * @param pDevIns The IOMMU device instance.
3121 * @param uIova The I/O virtual address to translate.
3122 * @param uDevId The device ID (bus, device, function).
3123 * @param fPerm The I/O permissions for this access, see
3124 * IOMMU_IO_PERM_XXX.
3125 * @param pDte The device table entry.
3126 * @param enmOp The IOMMU operation being performed.
3127 *
3128 * @thread Any.
3129 */
3130static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3131 IOMMUOP enmOp)
3132{
3133 /*
3134 * Check if the translation is valid, otherwise raise an I/O page fault.
3135 */
3136 if (pDte->n.u1TranslationValid)
3137 { /* likely */ }
3138 else
3139 {
3140 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3141 * doesn't explicitly say whether an I/O page fault is raised. From other
3142 * places in the spec. it seems early page walk terminations (starting with
3143 * the DTE) return the state computed so far and raises an I/O page fault. So
3144 * returning an invalid translation rather than skipping translation. */
3145 LogFunc(("Translation valid bit not set -> IOPF\n"));
3146 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3147 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3148 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3149 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3150 kIoPageFaultType_DteTranslationDisabled);
3151 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3152 }
3153
3154 /*
3155 * Check permissions bits in the DTE.
3156 * Note: This MUST be checked prior to checking the root page table level below!
3157 */
3158 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3159 if ((fPerm & fDtePerm) == fPerm)
3160 { /* likely */ }
3161 else
3162 {
3163 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3164 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3165 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3166 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3167 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3168 kIoPageFaultType_PermDenied);
3169 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3170 }
3171
3172 /*
3173 * If the root page table level is 0, translation is disabled and GPA=SPA and
3174 * the DTE.IR and DTE.IW bits control permissions (verified above).
3175 */
3176 uint8_t const uMaxLevel = pDte->n.u3Mode;
3177 if (uMaxLevel != 0)
3178 { /* likely */ }
3179 else
3180 {
3181 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3182 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3183 }
3184
3185 /*
3186 * If the root page table level exceeds the allowed host-address translation level,
3187 * page walk is terminated and translation fails.
3188 */
3189 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3190 { /* likely */ }
3191 else
3192 {
3193 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3194 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3195 * I'm just going with I/O page fault. */
3196 LogFunc(("Invalid root page table level %#x (uDevId=%#x) -> IOPF\n", uMaxLevel, uDevId));
3197 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3198 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3199 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3200 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3201 kIoPageFaultType_PteInvalidLvlEncoding);
3202 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3203 }
3204
3205 /* The DTE allows translations for this device. */
3206 return VINF_SUCCESS;
3207}
3208
3209
3210/**
3211 * Walks the I/O page table to translate the I/O virtual address to a system
3212 * physical address.
3213 *
3214 * @returns VBox status code.
3215 * @param pDevIns The IOMMU device instance.
3216 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3217 * @param uDevId The device ID (bus, device, function).
3218 * @param fPerm The I/O permissions for this access, see
3219 * IOMMU_IO_PERM_XXX.
3220 * @param pDte The device table entry.
3221 * @param enmOp The IOMMU operation being performed.
3222 * @param pWalkResult Where to store the results of the I/O page walk. This is
3223 * only updated when VINF_SUCCESS is returned.
3224 *
3225 * @thread Any.
3226 */
3227static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3228 IOMMUOP enmOp, PIOWALKRESULT pWalkResult)
3229{
3230 Assert(pDte->n.u1Valid);
3231 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3232
3233 /* The virtual address bits indexing table. */
3234 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3235 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
3236 UINT64_C(0x00000000001ff000),
3237 UINT64_C(0x000000003fe00000),
3238 UINT64_C(0x0000007fc0000000),
3239 UINT64_C(0x0000ff8000000000),
3240 UINT64_C(0x01ff000000000000),
3241 UINT64_C(0xfe00000000000000),
3242 UINT64_C(0x0000000000000000) };
3243 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
3244 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3245
3246 /* Traverse the I/O page table starting with the page directory in the DTE. */
3247 IOPTENTITY_T PtEntity;
3248 PtEntity.u64 = pDte->au64[0];
3249 for (;;)
3250 {
3251 /* Figure out the system physical address of the page table at the current level. */
3252 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3253
3254 /* Read the page table entity at the current level. */
3255 {
3256 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3257 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3258 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3259 uint64_t const offPte = idxPte << 3;
3260 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3261 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3262 if (RT_FAILURE(rc))
3263 {
3264 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3265 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3266 iommuAmdPageTabHwErrorEventInit(uDevId, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3267 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3268 return VERR_IOMMU_IPE_2;
3269 }
3270 }
3271
3272 /* Check present bit. */
3273 if (PtEntity.n.u1Present)
3274 { /* likely */ }
3275 else
3276 {
3277 LogFunc(("Page table entry not present (uDevId=%#x) -> IOPF\n", uDevId));
3278 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3279 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3280 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3281 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3282 kIoPageFaultType_PermDenied);
3283 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3284 }
3285
3286 /* Check permission bits. */
3287 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3288 if ((fPerm & fPtePerm) == fPerm)
3289 { /* likely */ }
3290 else
3291 {
3292 LogFunc(("Page table entry access denied (uDevId=%#x fPerm=%#x fPtePerm=%#x) -> IOPF\n", uDevId, fPerm, fPtePerm));
3293 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3294 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3295 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3296 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3297 kIoPageFaultType_PermDenied);
3298 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3299 }
3300
3301 /* If this is a PTE, we're at the final level and we're done. */
3302 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3303 if (uNextLevel == 0)
3304 {
3305 /* The page size of the translation is the default (4K). */
3306 pWalkResult->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3307 pWalkResult->cShift = X86_PAGE_4K_SHIFT;
3308 pWalkResult->fPerm = fPtePerm;
3309 return VINF_SUCCESS;
3310 }
3311 if (uNextLevel == 7)
3312 {
3313 /* The default page size of the translation is overridden. */
3314 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3315 uint8_t cShift = X86_PAGE_4K_SHIFT;
3316 while (GCPhysPte & RT_BIT_64(cShift++))
3317 ;
3318
3319 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3320 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
3321 if ( cShift > s_acIovaLevelShifts[uLevel]
3322 && cShift < s_acIovaLevelShifts[uLevel + 1])
3323 {
3324 pWalkResult->GCPhysSpa = GCPhysPte;
3325 pWalkResult->cShift = cShift;
3326 pWalkResult->fPerm = fPtePerm;
3327 return VINF_SUCCESS;
3328 }
3329
3330 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
3331 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3332 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3333 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3334 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3335 kIoPageFaultType_PteInvalidPageSize);
3336 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3337 }
3338
3339 /* Validate the next level encoding of the PDE. */
3340#if IOMMU_MAX_HOST_PT_LEVEL < 6
3341 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3342 { /* likely */ }
3343 else
3344 {
3345 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
3346 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3347 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3348 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3349 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3350 kIoPageFaultType_PteInvalidLvlEncoding);
3351 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3352 }
3353#else
3354 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3355#endif
3356
3357 /* Validate level transition. */
3358 if (uNextLevel < uLevel)
3359 { /* likely */ }
3360 else
3361 {
3362 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3363 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3364 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3365 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3366 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3367 kIoPageFaultType_PteInvalidLvlEncoding);
3368 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3369 }
3370
3371 /* Ensure IOVA bits of skipped levels are zero. */
3372 Assert(uLevel > 0);
3373 uint64_t uIovaSkipMask = 0;
3374 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
3375 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
3376 if (!(uIova & uIovaSkipMask))
3377 { /* likely */ }
3378 else
3379 {
3380 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
3381 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3382 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3383 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3384 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3385 kIoPageFaultType_SkippedLevelIovaNotZero);
3386 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3387 }
3388
3389 /* Continue with traversing the page directory at this level. */
3390 }
3391}
3392
3393
3394/**
3395 * Looks up an I/O virtual address from the device table.
3396 *
3397 * @returns VBox status code.
3398 * @param pDevIns The IOMMU instance data.
3399 * @param uDevId The device ID (bus, device, function).
3400 * @param uIova The I/O virtual address to lookup.
3401 * @param cbAccess The size of the access.
3402 * @param fPerm The I/O permissions for this access, see
3403 * IOMMU_IO_PERM_XXX.
3404 * @param enmOp The IOMMU operation being performed.
3405 * @param pGCPhysSpa Where to store the translated system physical address.
3406 * @param pcbContiguous Where to store the number of contiguous bytes translated
3407 * and permission-checked.
3408 *
3409 * @thread Any.
3410 */
3411static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fPerm, IOMMUOP enmOp,
3412 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3413{
3414 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3415 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3416 size_t cbContiguous = 0;
3417
3418 /* Read the device table entry from memory. */
3419 DTE_T Dte;
3420 int rc = iommuAmdDteRead(pDevIns, uDevId, enmOp, &Dte);
3421 if (RT_SUCCESS(rc))
3422 {
3423 if (Dte.n.u1Valid)
3424 {
3425 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3426 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3427 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3428 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
3429 {
3430 /* Note: Addresses are not subject to exclusion as we do -not- support remote IOTLBs. */
3431 rc = iommuAmdPreTranslateChecks(pDevIns, uDevId, uIova, fPerm, &Dte, enmOp);
3432 if (rc == VINF_SUCCESS)
3433 {
3434 /* Walk the I/O page tables to translate the IOVA and check permissions for the
3435 remaining pages in the access. */
3436 size_t cbRemaining = cbAccess;
3437 uint64_t uIovaPage = uIova & X86_PAGE_4K_BASE_MASK;
3438 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
3439 uint64_t cbPages = 0;
3440 IOWALKRESULT WalkResultPrev;
3441 RT_ZERO(WalkResultPrev);
3442 for (;;)
3443 {
3444 /** @todo split this into a separate function and reuse from
3445 * iommuAmdCacheLookup(). */
3446 IOWALKRESULT WalkResult;
3447 RT_ZERO(WalkResult);
3448 STAM_PROFILE_ADV_START(&pThis->StatIoPageWalkLookup, a);
3449 rc = iommuAmdIoPageTableWalk(pDevIns, uDevId, uIovaPage, fPerm, &Dte, enmOp, &WalkResult);
3450 STAM_PROFILE_ADV_STOP(&pThis->StatIoPageWalkLookup, a);
3451 if (RT_SUCCESS(rc))
3452 {
3453 /* Store the translated address before continuing to access more pages. */
3454 Assert(WalkResult.cShift >= X86_PAGE_4K_SHIFT);
3455 if (cbRemaining == cbAccess)
3456 {
3457 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(WalkResult.cShift);
3458 uint64_t const offSpa = uIova & offMask;
3459 Assert(!(WalkResult.GCPhysSpa & offMask));
3460 GCPhysSpa = WalkResult.GCPhysSpa | offSpa;
3461 }
3462 /* Check if addresses translated so far result in a physically contiguous region. */
3463 else if (!iommuAmdLookupIsAccessContig(&WalkResultPrev, &WalkResult))
3464 {
3465 STAM_COUNTER_INC(&pThis->StatDteLookupNonContig);
3466 break;
3467 }
3468
3469 /* Store the walk result from the first/previous page. */
3470 WalkResultPrev = WalkResult;
3471
3472 /* Update size of all pages read thus far. */
3473 uint64_t const cbPage = RT_BIT_64(WalkResult.cShift);
3474 cbPages += cbPage;
3475
3476 /* Check if we need to access more pages. */
3477 if (cbRemaining > cbPage - offIova)
3478 {
3479 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3480 uIovaPage += cbPage; /* Update address of the next access. */
3481 offIova = 0; /* After first page, all pages are accessed from off 0. */
3482 }
3483 else
3484 {
3485 cbRemaining = 0;
3486 break;
3487 }
3488 }
3489 else
3490 {
3491 /* Translation failed. */
3492 GCPhysSpa = NIL_RTGCPHYS;
3493 cbRemaining = cbAccess;
3494 break;
3495 }
3496 }
3497
3498 /* Update how much contiguous memory was accessed. */
3499 cbContiguous = cbAccess - cbRemaining;
3500
3501#if defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)
3502 if (RT_SUCCESS(rc))
3503 {
3504 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
3505 iommuAmdDteCacheUpdate(pDevIns, uDevId, &Dte, IOMMU_DEV_F_PRESENT | IOMMU_DEV_F_ADDR_TRANSLATE);
3506
3507 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
3508 iommuAmdIotlbUpdate(pDevIns, Dte.n.u16DomainId, uIova & X86_PAGE_4K_BASE_MASK, cbPages,
3509 GCPhysSpa & X86_PAGE_4K_BASE_MASK, WalkResultPrev.fPerm);
3510 }
3511#endif
3512 }
3513 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
3514 {
3515 /*
3516 * Translation is disabled for this device (root paging mode is 0).
3517 * GPA=SPA, but the permission bits are important and controls accesses.
3518 */
3519 GCPhysSpa = uIova;
3520 cbContiguous = cbAccess;
3521 rc = VINF_SUCCESS;
3522
3523#if defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)
3524 /* Update that addresses permissions of DTE apply (but omit address translation). */
3525 iommuAmdDteCacheUpdate(pDevIns, uDevId, &Dte, IOMMU_DEV_F_PRESENT | IOMMU_DEV_F_IO_PERM);
3526#endif
3527 }
3528 else
3529 {
3530 /* Address translation failed or access is denied. */
3531 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
3532 GCPhysSpa = NIL_RTGCPHYS;
3533 cbContiguous = 0;
3534 }
3535 }
3536 else
3537 {
3538 /* Invalid reserved bits in the DTE, raise an error event. */
3539 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
3540 EVT_ILLEGAL_DTE_T Event;
3541 iommuAmdIllegalDteEventInit(uDevId, uIova, true /* fRsvdNotZero */, enmOp, &Event);
3542 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
3543 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3544 }
3545 }
3546 else
3547 {
3548 /*
3549 * The DTE is not valid, forward addresses untranslated.
3550 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
3551 */
3552 GCPhysSpa = uIova;
3553 cbContiguous = cbAccess;
3554
3555#if defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)
3556 /* Update that addresses don't require translation (nor permission checks) but a DTE is present. */
3557 iommuAmdDteCacheUpdate(pDevIns, uDevId, &Dte, IOMMU_DEV_F_PRESENT);
3558#endif
3559 }
3560 }
3561 else
3562 {
3563 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
3564 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3565 }
3566
3567 *pGCPhysSpa = GCPhysSpa;
3568 *pcbContiguous = cbContiguous;
3569 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
3570
3571 return rc;
3572}
3573
3574
3575#ifdef IOMMU_WITH_IOTLBE_CACHE
3576/**
3577 * Lookups a memory access from the IOMMU cache.
3578 *
3579 * @returns VBox status code.
3580 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
3581 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
3582 * address region.
3583 * @retval VERR_NOT_FOUND if the access was not cached.
3584 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
3585 * are insufficient.
3586 *
3587 * @param pDevIns The IOMMU instance data.
3588 * @param uDevId The device ID (bus, device, function).
3589 * @param uIova The I/O virtual address to lookup.
3590 * @param cbAccess The size of the access.
3591 * @param fPerm The I/O permissions for this access, see
3592 * IOMMU_IO_PERM_XXX.
3593 * @param enmOp The IOMMU operation being performed.
3594 * @param pGCPhysSpa Where to store the translated system physical address.
3595 * @param pcbContiguous Where to store the number of contiguous bytes translated
3596 * and permission-checked.
3597 */
3598static int iommuAmdCacheLookup(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint8_t fPerm, IOMMUOP enmOp,
3599 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3600{
3601 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3602 IOMMU_LOCK_CACHE(pDevIns, pThis);
3603
3604 /* Lookup the device from the level 1 cache. */
3605 int rc = VERR_NOT_FOUND;
3606 PCIODEVICE pDevice = &pThis->paDevices[uDevId];
3607 if ((pDevice->fFlags & (IOMMU_DEV_F_PRESENT | IOMMU_DEV_F_VALID | IOMMU_DEV_F_ADDR_TRANSLATE))
3608 == (IOMMU_DEV_F_PRESENT | IOMMU_DEV_F_VALID | IOMMU_DEV_F_ADDR_TRANSLATE))
3609 {
3610 /* Lookup the IOTLB entries from the level 2 cache. */
3611 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3612 size_t cbContiguous = 0;
3613 size_t cbRemaining = cbAccess;
3614 uint64_t uIovaPage = uIova & X86_PAGE_4K_BASE_MASK;
3615 uint64_t offIova = uIova & X86_PAGE_4K_OFFSET_MASK;
3616 IOWALKRESULT WalkResultPrev;
3617 RT_ZERO(WalkResultPrev);
3618 for (;;)
3619 {
3620 STAM_PROFILE_ADV_START(&pThis->StatIotlbeLookup, b);
3621 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pDevice->uDomainId, uIovaPage);
3622 STAM_PROFILE_ADV_STOP(&pThis->StatIotlbeLookup, b);
3623 if (pIotlbe)
3624 {
3625 PCIOWALKRESULT pWalkResult = &pIotlbe->WalkResult;
3626 if ((pWalkResult->fPerm & fPerm) == fPerm)
3627 { /* likely */ }
3628 else
3629 {
3630 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3631 iommuAmdIoPageFaultEventInit(uDevId, pDevice->uDomainId, uIova, true /* fPresent */,
3632 false /* fRsvdNotZero */, true /* fPermDenied */, enmOp, &EvtIoPageFault);
3633 iommuAmdIoPageFaultEventRaise(pDevIns, pDevice->fFlags, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3634 kIoPageFaultType_PermDenied);
3635 rc = VERR_IOMMU_ADDR_ACCESS_DENIED;
3636 break;
3637 }
3638
3639 /* Store the translated address before continuing to translate more pages. */
3640 Assert(pWalkResult->cShift >= X86_PAGE_4K_SHIFT);
3641 if (cbRemaining == cbAccess)
3642 {
3643 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(pWalkResult->cShift);
3644 uint64_t const offSpa = uIova & offMask;
3645 Assert(!(pWalkResult->GCPhysSpa & offMask));
3646 GCPhysSpa = pWalkResult->GCPhysSpa | offSpa;
3647 }
3648 /* Check if addresses translated so far result in a physically contiguous region. */
3649 else if (!iommuAmdLookupIsAccessContig(&WalkResultPrev, pWalkResult))
3650 {
3651 STAM_COUNTER_INC(&pThis->StatIotlbeLookupNonContig);
3652 rc = VERR_OUT_OF_RANGE;
3653 break;
3654 }
3655
3656 /* Store the walk result from the first/previous page. */
3657 WalkResultPrev = *pWalkResult;
3658
3659 /* Check if we need to access more pages. */
3660 uint64_t const cbPage = RT_BIT_64(pWalkResult->cShift);
3661 if (cbRemaining > cbPage - offIova)
3662 {
3663 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3664 uIovaPage += cbPage; /* Update address of the next access. */
3665 offIova = 0; /* After first page, all pages are accessed from off 0. */
3666 }
3667 else
3668 {
3669 cbRemaining = 0;
3670 rc = VINF_SUCCESS;
3671 break;
3672 }
3673 }
3674 else
3675 {
3676 /*
3677 * No IOTLB entry was found for this I/O virtual address.
3678 * Fallback to walking the I/O page tables from the beginning of the access.
3679 * We currently don't support partial lookups.
3680 */
3681 Assert(rc == VERR_NOT_FOUND);
3682 break;
3683 }
3684 }
3685
3686 /* Update how much contiguous memory was accessed. */
3687 cbContiguous = cbAccess - cbRemaining;
3688
3689 *pGCPhysSpa = GCPhysSpa;
3690 *pcbContiguous = cbContiguous;
3691 }
3692 else if ((pDevice->fFlags & (IOMMU_DEV_F_PRESENT | IOMMU_DEV_F_VALID | IOMMU_DEV_F_IO_PERM))
3693 == (IOMMU_DEV_F_PRESENT | IOMMU_DEV_F_VALID | IOMMU_DEV_F_IO_PERM))
3694 {
3695 /* Address translation is disabled, but DTE permissions apply. */
3696 Assert(!(pDevice->fFlags & IOMMU_DEV_F_ADDR_TRANSLATE));
3697 uint8_t const fDtePerm = (pDevice->fFlags >> IOMMU_DEV_F_IO_PERM_SHIFT) & IOMMU_DEV_F_IO_PERM_MASK;
3698 if ((fDtePerm & fPerm) == fPerm)
3699 {
3700 *pGCPhysSpa = uIova;
3701 *pcbContiguous = cbAccess;
3702 rc = VINF_SUCCESS;
3703 }
3704 else
3705 {
3706 *pGCPhysSpa = NIL_RTGCPHYS;
3707 *pcbContiguous = 0;
3708 rc = VERR_IOMMU_ADDR_ACCESS_DENIED;
3709 }
3710 }
3711 else if (pDevice->fFlags & IOMMU_DEV_F_PRESENT)
3712 {
3713 /* Forward addresses untranslated, without checking permissions. */
3714 *pGCPhysSpa = uIova;
3715 *pcbContiguous = cbAccess;
3716 rc = VINF_SUCCESS;
3717 }
3718
3719 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
3720 return rc;
3721}
3722#endif /* IOMMU_WITH_IOTLBE_CACHE */
3723
3724
3725/**
3726 * Gets the I/O permission and IOMMU operation type for the given access flags.
3727 *
3728 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
3729 * @param penmOp Where to store the IOMMU operation.
3730 * @param pfPerm Where to store the IOMMU I/O permission.
3731 * @param pStatRead The stat counter to increment for a read operation.
3732 * @param pStatWrite The stat counter to increment for a write operation.
3733 */
3734DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, PSTAMCOUNTER pStatRead,
3735 PSTAMCOUNTER pStatWrite)
3736{
3737 if (fFlags & PDMIOMMU_MEM_F_WRITE)
3738 {
3739 *penmOp = IOMMUOP_MEM_WRITE;
3740 *pfPerm = IOMMU_IO_PERM_WRITE;
3741 STAM_COUNTER_INC(pStatWrite);
3742 }
3743 else
3744 {
3745 Assert(fFlags & PDMIOMMU_MEM_F_READ);
3746 *penmOp = IOMMUOP_MEM_READ;
3747 *pfPerm = IOMMU_IO_PERM_READ;
3748 STAM_COUNTER_INC(pStatRead);
3749 }
3750}
3751
3752
3753/**
3754 * Memory access transaction from a device.
3755 *
3756 * @returns VBox status code.
3757 * @param pDevIns The IOMMU device instance.
3758 * @param uDevId The device ID (bus, device, function).
3759 * @param uIova The I/O virtual address being accessed.
3760 * @param cbAccess The number of bytes being accessed.
3761 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3762 * @param pGCPhysSpa Where to store the translated system physical address.
3763 * @param pcbContiguous Where to store the number of contiguous bytes translated
3764 * and permission-checked.
3765 *
3766 * @thread Any.
3767 */
3768static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uIova, size_t cbAccess, uint32_t fFlags,
3769 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3770{
3771 /* Validate. */
3772 AssertPtr(pDevIns);
3773 AssertPtr(pGCPhysSpa);
3774 Assert(cbAccess > 0);
3775 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3776
3777 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3778 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3779 if (Ctrl.n.u1IommuEn)
3780 {
3781 IOMMUOP enmOp;
3782 uint8_t fPerm;
3783 iommuAmdMemAccessGetPermAndOp(fFlags, &enmOp, &fPerm, &pThis->CTX_SUFF_Z(StatMemRead), &pThis->CTX_SUFF_Z(StatMemWrite));
3784 LogFlowFunc(("%s: uDevId=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), uDevId, uIova, cbAccess));
3785
3786 int rc;
3787#if defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)
3788 /* Lookup the IOVA from the cache. */
3789 rc = iommuAmdCacheLookup(pDevIns, uDevId, uIova, cbAccess, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
3790 if (rc == VINF_SUCCESS)
3791 {
3792 STAM_COUNTER_INC(&pThis->StatIotlbeCacheHit);
3793 Assert(*pcbContiguous == cbAccess);
3794 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
3795 return rc;
3796 }
3797 if (rc == VERR_OUT_OF_RANGE)
3798 {
3799 Assert(*pcbContiguous > 0 && *pcbContiguous < cbAccess);
3800 return VINF_SUCCESS;
3801 }
3802 if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
3803 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3804 AssertMsg(rc == VERR_NOT_FOUND, ("Cache lokoup failed: %Rrc\n", rc));
3805 STAM_COUNTER_INC(&pThis->StatIotlbeCacheMiss);
3806 /** @todo r=ramshankar: WARNING! when implementing continuing of lookups because
3807 * some entries weren't in the IOTLB, make sure to keep the lock held or to
3808 * re-lookup the level 1 cache again because the DTE might be invalidated
3809 * in-between! */
3810#endif
3811
3812 /* Lookup the IOVA from the device table. */
3813 rc = iommuAmdDteLookup(pDevIns, uDevId, uIova, cbAccess, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
3814 if (RT_SUCCESS(rc))
3815 { /* likely */ }
3816 else
3817 LogFunc(("DTE lookup failed! uDevId=%#x uIova=%#RX64 fPerm=%u cbAccess=%zu rc=%#Rrc\n", uDevId, uIova, fPerm,
3818 cbAccess, rc));
3819
3820 return rc;
3821 }
3822
3823 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3824 *pGCPhysSpa = uIova;
3825 *pcbContiguous = cbAccess;
3826 return VINF_SUCCESS;
3827}
3828
3829
3830/**
3831 * Memory access bulk (one or more 4K pages) request from a device.
3832 *
3833 * @returns VBox status code.
3834 * @param pDevIns The IOMMU device instance.
3835 * @param uDevId The device ID (bus, device, function).
3836 * @param cIovas The number of addresses being accessed.
3837 * @param pauIovas The I/O virtual addresses for each page being accessed.
3838 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
3839 * @param paGCPhysSpa Where to store the translated physical addresses.
3840 *
3841 * @thread Any.
3842 */
3843static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
3844 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
3845{
3846 /* Validate. */
3847 AssertPtr(pDevIns);
3848 Assert(cIovas > 0);
3849 AssertPtr(pauIovas);
3850 AssertPtr(paGCPhysSpa);
3851 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
3852
3853 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3854 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
3855 if (Ctrl.n.u1IommuEn)
3856 {
3857 IOMMUOP enmOp;
3858 uint8_t fPerm;
3859 iommuAmdMemAccessGetPermAndOp(fFlags, &enmOp, &fPerm, &pThis->CTX_SUFF_Z(StatMemBulkRead),
3860 &pThis->CTX_SUFF_Z(StatMemBulkWrite));
3861 LogFlowFunc(("%s: uDevId=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), uDevId, cIovas));
3862
3863 /** @todo IOMMU: IOTLB cache lookup. */
3864
3865 /* Lookup each IOVA from the device table. */
3866 for (size_t i = 0; i < cIovas; i++)
3867 {
3868 size_t cbContig;
3869 int rc = iommuAmdDteLookup(pDevIns, uDevId, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
3870 if (RT_SUCCESS(rc))
3871 { /* likely */ }
3872 else
3873 {
3874 LogFunc(("Failed! uDevId=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", uDevId, pauIovas[i], fPerm, rc));
3875 return rc;
3876 }
3877 Assert(cbContig == X86_PAGE_SIZE);
3878 }
3879 }
3880 else
3881 {
3882 /* Addresses are forwarded without translation when the IOMMU is disabled. */
3883 for (size_t i = 0; i < cIovas; i++)
3884 paGCPhysSpa[i] = pauIovas[i];
3885 }
3886
3887 return VINF_SUCCESS;
3888}
3889
3890
3891/**
3892 * Reads an interrupt remapping table entry from guest memory given its DTE.
3893 *
3894 * @returns VBox status code.
3895 * @param pDevIns The IOMMU device instance.
3896 * @param uDevId The device ID (bus, device, function).
3897 * @param pDte The device table entry.
3898 * @param GCPhysIn The source MSI address (used for reporting errors).
3899 * @param uDataIn The source MSI data.
3900 * @param enmOp The IOMMU operation being performed.
3901 * @param pIrte Where to store the interrupt remapping table entry.
3902 *
3903 * @thread Any.
3904 */
3905static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
3906 IOMMUOP enmOp, PIRTE_T pIrte)
3907{
3908 /* Ensure the IRTE length is valid. */
3909 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
3910
3911 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
3912 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
3913 uint16_t const offIrte = (uDataIn & IOMMU_MSI_DATA_IRTE_OFFSET_MASK) * sizeof(IRTE_T);
3914 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
3915
3916 /* Ensure the IRTE falls completely within the interrupt table. */
3917 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
3918 { /* likely */ }
3919 else
3920 {
3921 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
3922 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
3923
3924 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3925 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
3926 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3927 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3928 kIoPageFaultType_IrteAddrInvalid);
3929 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3930 }
3931
3932 /* Read the IRTE from memory. */
3933 Assert(!(GCPhysIrte & 3));
3934 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
3935 if (RT_SUCCESS(rc))
3936 return VINF_SUCCESS;
3937
3938 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
3939 * situation. Is it an I/O page fault or a device table hardware error?
3940 * There's no interrupt table hardware error event, but it's unclear what
3941 * we should do here. */
3942 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
3943 return VERR_IOMMU_IPE_4;
3944}
3945
3946
3947/**
3948 * Remaps the interrupt using the interrupt remapping table.
3949 *
3950 * @returns VBox status code.
3951 * @param pDevIns The IOMMU instance data.
3952 * @param uDevId The device ID (bus, device, function).
3953 * @param pDte The device table entry.
3954 * @param enmOp The IOMMU operation being performed.
3955 * @param pMsiIn The source MSI.
3956 * @param pMsiOut Where to store the remapped MSI.
3957 *
3958 * @thread Any.
3959 */
3960static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
3961 PMSIMSG pMsiOut)
3962{
3963 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
3964
3965 IRTE_T Irte;
3966 int rc = iommuAmdIrteRead(pDevIns, uDevId, pDte, pMsiIn->Addr.u64, pMsiIn->Data.u32, enmOp, &Irte);
3967 if (RT_SUCCESS(rc))
3968 {
3969 if (Irte.n.u1RemapEnable)
3970 {
3971 if (!Irte.n.u1GuestMode)
3972 {
3973 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
3974 {
3975 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
3976 *pMsiOut = *pMsiIn;
3977
3978 pMsiOut->Addr.n.u1DestMode = Irte.n.u1DestMode;
3979 pMsiOut->Addr.n.u8DestId = Irte.n.u8Dest;
3980
3981 pMsiOut->Data.n.u8Vector = Irte.n.u8Vector;
3982 pMsiOut->Data.n.u3DeliveryMode = Irte.n.u3IntrType;
3983 return VINF_SUCCESS;
3984 }
3985
3986 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
3987 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3988 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3989 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3990 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
3991 kIoPageFaultType_IrteRsvdIntType);
3992 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3993 }
3994
3995 LogFunc(("Guest mode not supported -> IOPF\n"));
3996 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3997 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
3998 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
3999 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4000 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4001 }
4002
4003 LogFunc(("Remapping disabled -> IOPF\n"));
4004 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4005 iommuAmdIoPageFaultEventInit(uDevId, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4006 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4007 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4008 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4009 }
4010
4011 return rc;
4012}
4013
4014
4015/**
4016 * Looks up an MSI interrupt from the interrupt remapping table.
4017 *
4018 * @returns VBox status code.
4019 * @param pDevIns The IOMMU instance data.
4020 * @param uDevId The device ID (bus, device, function).
4021 * @param enmOp The IOMMU operation being performed.
4022 * @param pMsiIn The source MSI.
4023 * @param pMsiOut Where to store the remapped MSI.
4024 *
4025 * @thread Any.
4026 */
4027static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t uDevId, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4028{
4029 /* Read the device table entry from memory. */
4030 LogFlowFunc(("uDevId=%#x (%#x:%#x:%#x) enmOp=%u\n", uDevId,
4031 ((uDevId >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4032 ((uDevId >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (uDevId & VBOX_PCI_DEVFN_FUN_MASK), enmOp));
4033
4034 DTE_T Dte;
4035 int rc = iommuAmdDteRead(pDevIns, uDevId, enmOp, &Dte);
4036 if (RT_SUCCESS(rc))
4037 {
4038 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4039 if (Dte.n.u1IntrMapValid)
4040 {
4041 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4042 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4043 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4044 if (RT_LIKELY( !fRsvd0
4045 && !fRsvd1))
4046 { /* likely */ }
4047 else
4048 {
4049 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0,
4050 fRsvd1));
4051 EVT_ILLEGAL_DTE_T Event;
4052 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4053 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4054 return VERR_IOMMU_INTR_REMAP_FAILED;
4055 }
4056
4057 /*
4058 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4059 * that's connected through HyperTransport it might be possible; but for us, it
4060 * doesn't seem we need to specially handle these pins.
4061 */
4062
4063 /*
4064 * Validate the MSI source address.
4065 *
4066 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4067 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4068 * claims the region as I/O space.
4069 *
4070 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4071 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4072 * See Intel spec. 10.11.1 "Message Address Register Format".
4073 */
4074 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4075 {
4076 /*
4077 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4078 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4079 */
4080 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4081 bool fPassThru = false;
4082 switch (u8DeliveryMode)
4083 {
4084 case VBOX_MSI_DELIVERY_MODE_FIXED:
4085 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4086 {
4087 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4088 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4089 {
4090 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4091 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4092 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4093 {
4094 /*
4095 * We don't support guest interrupt remapping yet. When we do, we'll need to
4096 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4097 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4098 * already reads the control register, add that as a parameter when we eventually
4099 * support guest interrupt remapping. For now, just assert.
4100 */
4101 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4102 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4103 NOREF(pThis);
4104
4105 return iommuAmdIntrRemap(pDevIns, uDevId, &Dte, enmOp, pMsiIn, pMsiOut);
4106 }
4107
4108 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4109 EVT_ILLEGAL_DTE_T Event;
4110 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4111 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4112 return VERR_IOMMU_INTR_REMAP_FAILED;
4113 }
4114
4115 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4116 {
4117 fPassThru = true;
4118 break;
4119 }
4120
4121 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4122 {
4123 LogFunc(("IntCtl=0: Remapping disallowed for fixed/arbitrated interrupt (%#x) -> Target abort\n",
4124 pMsiIn->Data.n.u8Vector));
4125 iommuAmdSetPciTargetAbort(pDevIns);
4126 return VERR_IOMMU_INTR_REMAP_DENIED;
4127 }
4128
4129 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4130 LogFunc(("IntCtl mode invalid %#x -> Illegal DTE\n", uIntrCtrl));
4131 EVT_ILLEGAL_DTE_T Event;
4132 iommuAmdIllegalDteEventInit(uDevId, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4133 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4134 return VERR_IOMMU_INTR_REMAP_FAILED;
4135 }
4136
4137 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4138 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4139 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4140 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4141 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4142 default:
4143 {
4144 LogFunc(("MSI data delivery mode invalid %#x -> Target abort\n", u8DeliveryMode));
4145 iommuAmdSetPciTargetAbort(pDevIns);
4146 return VERR_IOMMU_INTR_REMAP_FAILED;
4147 }
4148 }
4149
4150 /*
4151 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4152 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4153 */
4154 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4155 || !pMsiIn->Addr.n.u1DestMode)
4156 {
4157 if (fPassThru)
4158 {
4159 *pMsiOut = *pMsiIn;
4160 return VINF_SUCCESS;
4161 }
4162 LogFunc(("Remapping/passthru disallowed for interrupt %#x -> Target abort\n", pMsiIn->Data.n.u8Vector));
4163 }
4164 else
4165 LogFunc(("Logical destination mode invalid for delivery mode %#x\n -> Target abort\n", u8DeliveryMode));
4166
4167 iommuAmdSetPciTargetAbort(pDevIns);
4168 return VERR_IOMMU_INTR_REMAP_DENIED;
4169 }
4170 else
4171 {
4172 LogFunc(("MSI address region invalid %#RX64\n", pMsiIn->Addr.u64));
4173 return VERR_IOMMU_INTR_REMAP_FAILED;
4174 }
4175 }
4176 else
4177 {
4178 /** @todo IOMMU: Add to interrupt remapping cache. */
4179 LogFlowFunc(("DTE interrupt map not valid\n"));
4180 *pMsiOut = *pMsiIn;
4181 return VINF_SUCCESS;
4182 }
4183 }
4184
4185 LogFunc(("Failed to read device table entry. uDevId=%#x rc=%Rrc\n", uDevId, rc));
4186 return VERR_IOMMU_INTR_REMAP_FAILED;
4187}
4188
4189
4190/**
4191 * Interrupt remap request from a device.
4192 *
4193 * @returns VBox status code.
4194 * @param pDevIns The IOMMU device instance.
4195 * @param uDevId The device ID (bus, device, function).
4196 * @param pMsiIn The source MSI.
4197 * @param pMsiOut Where to store the remapped MSI.
4198 */
4199static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4200{
4201 /* Validate. */
4202 Assert(pDevIns);
4203 Assert(pMsiIn);
4204 Assert(pMsiOut);
4205
4206 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4207
4208 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4209 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4210 if (Ctrl.n.u1IommuEn)
4211 {
4212 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4213 /** @todo Cache? */
4214
4215 return iommuAmdIntrTableLookup(pDevIns, uDevId, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4216 }
4217
4218 *pMsiOut = *pMsiIn;
4219 return VINF_SUCCESS;
4220}
4221
4222
4223/**
4224 * @callback_method_impl{FNIOMMMIONEWWRITE}
4225 */
4226static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4227{
4228 NOREF(pvUser);
4229 Assert(cb == 4 || cb == 8);
4230 Assert(!(off & (cb - 1)));
4231
4232 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4233 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4234
4235 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4236 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4237}
4238
4239
4240/**
4241 * @callback_method_impl{FNIOMMMIONEWREAD}
4242 */
4243static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4244{
4245 NOREF(pvUser);
4246 Assert(cb == 4 || cb == 8);
4247 Assert(!(off & (cb - 1)));
4248
4249 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4250 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4251
4252 uint64_t uResult;
4253 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4254 if (cb == 8)
4255 *(uint64_t *)pv = uResult;
4256 else
4257 *(uint32_t *)pv = (uint32_t)uResult;
4258
4259 return rcStrict;
4260}
4261
4262
4263#ifdef IN_RING3
4264/**
4265 * Processes an IOMMU command.
4266 *
4267 * @returns VBox status code.
4268 * @param pDevIns The IOMMU device instance.
4269 * @param pCmd The command to process.
4270 * @param GCPhysCmd The system physical address of the command.
4271 * @param pEvtError Where to store the error event in case of failures.
4272 *
4273 * @thread Command thread.
4274 */
4275static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4276{
4277 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4278 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4279
4280 STAM_COUNTER_INC(&pThis->StatCmd);
4281
4282 uint8_t const bCmd = pCmd->n.u4Opcode;
4283 switch (bCmd)
4284 {
4285 case IOMMU_CMD_COMPLETION_WAIT:
4286 {
4287 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4288
4289 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4290 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4291
4292 /* Validate reserved bits in the command. */
4293 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4294 {
4295 /* If Completion Store is requested, write the StoreData to the specified address. */
4296 if (pCmdComWait->n.u1Store)
4297 {
4298 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4299 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4300 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4301 if (RT_FAILURE(rc))
4302 {
4303 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4304 GCPhysStore, rc));
4305 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4306 return VERR_IOMMU_CMD_HW_ERROR;
4307 }
4308 }
4309
4310 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4311 if (pCmdComWait->n.u1Interrupt)
4312 {
4313 IOMMU_LOCK(pDevIns, pThisCC);
4314 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4315 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrl(pThis);
4316 bool const fRaiseInt = Ctrl.n.u1CompWaitIntrEn;
4317 IOMMU_UNLOCK(pDevIns, pThisCC);
4318
4319 if (fRaiseInt)
4320 iommuAmdMsiInterruptRaise(pDevIns);
4321 }
4322 return VINF_SUCCESS;
4323 }
4324 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4325 return VERR_IOMMU_CMD_INVALID_FORMAT;
4326 }
4327
4328 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4329 {
4330 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4331#ifdef IOMMU_WITH_IOTLBE_CACHE
4332 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4333 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4334
4335 /* Validate reserved bits in the command. */
4336 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4337 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4338 {
4339 iommuAmdDteCacheUpdate(pDevIns, pCmdInvDte->n.u16DevId, NULL /* pDte */, 0 /* fFlags */);
4340 return VINF_SUCCESS;
4341 }
4342 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4343 return VERR_IOMMU_CMD_INVALID_FORMAT;
4344#else
4345 return VINF_SUCCESS;
4346#endif
4347 }
4348
4349 case IOMMU_CMD_INV_IOMMU_PAGES:
4350 {
4351 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4352#ifdef IOMMU_WITH_IOTLBE_CACHE
4353 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4354 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4355
4356 /* Validate reserved bits in the command. */
4357 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4358 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4359 {
4360 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4361 uint16_t const uDomainId = pCmdInvPages->n.u16DomainId;
4362 bool const fFlushPde = pCmdInvPages->n.u1PageDirEntries;
4363 uint8_t cShift;
4364 if (!pCmdInvPages->n.u1Size)
4365 cShift = X86_PAGE_4K_SHIFT;
4366 else
4367 {
4368 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4369 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4370 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4371
4372 /*
4373 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4374 * would do the right thing by clearing the entire cache for the specified domain ID.
4375 *
4376 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4377 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4378 * A debug-time assert is in place here to let us know if any software tries this.
4379 *
4380 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4381 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4382 */
4383 Assert(uIova != UINT64_C(0xfffffffffffff000));
4384 }
4385
4386 /*
4387 * Validate invalidation size.
4388 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4389 */
4390 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4391 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4392 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4393 {
4394 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4395 size_t const cbAccess = RT_BIT_64(cShift);
4396 iommuAmdIotlbRemoveRange(pDevIns, uDomainId, uIova, cbAccess);
4397 }
4398 else
4399 {
4400 /*
4401 * The guest provided size is invalid or exceeds the largest, meaningful page size.
4402 * In such situations we must remove all ranges for the specified domain ID.
4403 */
4404 iommuAmdIotlbRemoveDomainId(pDevIns, uDomainId);
4405 }
4406
4407 return VINF_SUCCESS;
4408 }
4409 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4410 return VERR_IOMMU_CMD_INVALID_FORMAT;
4411#else
4412 return VINF_SUCCESS;
4413#endif
4414 }
4415
4416 case IOMMU_CMD_INV_IOTLB_PAGES:
4417 {
4418 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
4419
4420 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4421 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4422 {
4423 /** @todo IOMMU: Implement remote IOTLB invalidation. */
4424 return VERR_NOT_IMPLEMENTED;
4425 }
4426 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4427 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4428 }
4429
4430 case IOMMU_CMD_INV_INTR_TABLE:
4431 {
4432 /** @todo IOMMU: Implement this once we implement IOTLB. Pretend success until
4433 * then. */
4434 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
4435 return VINF_SUCCESS;
4436 }
4437
4438 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
4439 {
4440 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
4441 if (pThis->ExtFeat.n.u1PrefetchSup)
4442 {
4443 /** @todo IOMMU: Implement prefetch. Pretend success until then. */
4444 return VINF_SUCCESS;
4445 }
4446 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4447 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4448 }
4449
4450 case IOMMU_CMD_COMPLETE_PPR_REQ:
4451 {
4452 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
4453
4454 /* We don't support PPR requests yet. */
4455 Assert(!pThis->ExtFeat.n.u1PprSup);
4456 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4457 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4458 }
4459
4460 case IOMMU_CMD_INV_IOMMU_ALL:
4461 {
4462 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
4463 if (pThis->ExtFeat.n.u1InvAllSup)
4464 {
4465#ifdef IOMMU_WITH_IOTLBE_CACHE
4466 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
4467 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
4468
4469 /* Validate reserved bits in the command. */
4470 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
4471 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
4472 {
4473 iommuAmdDteCacheRemoveAll(pDevIns);
4474 iommuAmdIotlbRemoveAll(pDevIns);
4475 return VINF_SUCCESS;
4476 }
4477 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4478 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4479#else
4480 return VINF_SUCCESS;
4481#endif
4482 }
4483 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4484 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4485 }
4486 }
4487
4488 STAM_COUNTER_DEC(&pThis->StatCmd);
4489 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
4490 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4491 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4492}
4493
4494
4495/**
4496 * The IOMMU command thread.
4497 *
4498 * @returns VBox status code.
4499 * @param pDevIns The IOMMU device instance.
4500 * @param pThread The command thread.
4501 */
4502static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4503{
4504 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4505 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4506
4507 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
4508 return VINF_SUCCESS;
4509
4510 /*
4511 * Pre-allocate the maximum command buffer size supported by the IOMMU.
4512 * This avoid trashing the heap as well as not wasting time allocating
4513 * and freeing buffers while processing commands.
4514 */
4515 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
4516 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
4517 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
4518
4519 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
4520 {
4521 /*
4522 * Sleep perpetually until we are woken up to process commands.
4523 */
4524 {
4525 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, true);
4526 bool fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
4527 if (!fSignaled)
4528 {
4529 Assert(ASMAtomicReadBool(&pThis->fCmdThreadSleeping));
4530 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
4531 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
4532 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
4533 break;
4534 Log4Func(("Woken up with rc=%Rrc\n", rc));
4535 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
4536 }
4537 ASMAtomicWriteBool(&pThis->fCmdThreadSleeping, false);
4538 }
4539
4540 /*
4541 * Fetch and process IOMMU commands.
4542 */
4543 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
4544 * temporary host buffer before processing them as a batch. If we want to
4545 * save on host memory a bit, we could (once PGM has the necessary APIs)
4546 * lock the page mappings page mappings and access them directly. */
4547 IOMMU_LOCK(pDevIns, pThisCC);
4548
4549 IOMMU_STATUS_T const Status = iommuAmdGetStatus(pThis);
4550 if (Status.n.u1CmdBufRunning)
4551 {
4552 /* Get the offsets we need to read commands from memory (circular buffer offset). */
4553 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
4554 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
4555 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
4556
4557 /* Validate. */
4558 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
4559 Assert(offHead < cbCmdBuf);
4560 Assert(cbCmdBuf <= cbMaxCmdBuf);
4561
4562 if (offHead != offTail)
4563 {
4564 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
4565 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
4566 int rc = PDMDevHlpPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
4567 if (RT_SUCCESS(rc))
4568 {
4569 /* Indicate to software we've fetched all commands from the buffer. */
4570 pThis->CmdBufHeadPtr.n.off = offTail;
4571
4572 /* Allow IOMMU to do other work while we process commands. */
4573 IOMMU_UNLOCK(pDevIns, pThisCC);
4574
4575 /* Process the fetched commands. */
4576 EVT_GENERIC_T EvtError;
4577 do
4578 {
4579 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
4580 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
4581 if (RT_FAILURE(rc))
4582 {
4583 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
4584 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
4585 {
4586 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
4587 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
4588 }
4589 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
4590 {
4591 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
4592 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
4593 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
4594 }
4595 break;
4596 }
4597
4598 /* Move to the next command in the circular buffer. */
4599 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
4600 } while (offHead != offTail);
4601 }
4602 else
4603 {
4604 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
4605 EVT_CMD_HW_ERR_T EvtCmdHwErr;
4606 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
4607 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
4608
4609 IOMMU_UNLOCK(pDevIns, pThisCC);
4610 }
4611 }
4612 else
4613 IOMMU_UNLOCK(pDevIns, pThisCC);
4614 }
4615 else
4616 IOMMU_UNLOCK(pDevIns, pThisCC);
4617 }
4618
4619 RTMemFree(pvCmds);
4620 LogFlowFunc(("Command thread terminating\n"));
4621 return VINF_SUCCESS;
4622}
4623
4624
4625/**
4626 * Wakes up the command thread so it can respond to a state change.
4627 *
4628 * @returns VBox status code.
4629 * @param pDevIns The IOMMU device instance.
4630 * @param pThread The command thread.
4631 */
4632static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
4633{
4634 RT_NOREF(pThread);
4635 LogFlowFunc(("\n"));
4636 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4637 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
4638}
4639
4640
4641/**
4642 * @callback_method_impl{FNPCICONFIGREAD}
4643 */
4644static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4645 unsigned cb, uint32_t *pu32Value)
4646{
4647 /** @todo IOMMU: PCI config read stat counter. */
4648 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
4649 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
4650 return rcStrict;
4651}
4652
4653
4654/**
4655 * @callback_method_impl{FNPCICONFIGWRITE}
4656 */
4657static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
4658 unsigned cb, uint32_t u32Value)
4659{
4660 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4661
4662 /*
4663 * Discard writes to read-only registers that are specific to the IOMMU.
4664 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
4665 * See PCI spec. 6.1. "Configuration Space Organization".
4666 */
4667 switch (uAddress)
4668 {
4669 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
4670 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
4671 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
4672 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
4673 {
4674 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
4675 return VINF_SUCCESS;
4676 }
4677 }
4678
4679 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
4680 IOMMU_LOCK(pDevIns, pThisCC);
4681
4682 VBOXSTRICTRC rcStrict = VERR_IOMMU_IPE_3;
4683 switch (uAddress)
4684 {
4685 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
4686 {
4687 if (pThis->IommuBar.n.u1Enable)
4688 {
4689 rcStrict = VINF_SUCCESS;
4690 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
4691 break;
4692 }
4693
4694 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
4695 if (pThis->IommuBar.n.u1Enable)
4696 {
4697 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
4698 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
4699 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
4700 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
4701
4702 /* If the MMIO region is already mapped at the specified address, we're done. */
4703 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
4704 if (GCPhysMmioBasePrev == GCPhysMmioBase)
4705 {
4706 rcStrict = VINF_SUCCESS;
4707 break;
4708 }
4709
4710 /* Unmap the previous MMIO region (which is at a different address). */
4711 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
4712 {
4713 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
4714 rcStrict = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
4715 if (RT_FAILURE(rcStrict))
4716 {
4717 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4718 break;
4719 }
4720 }
4721
4722 /* Map the newly specified MMIO region. */
4723 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
4724 rcStrict = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
4725 if (RT_FAILURE(rcStrict))
4726 {
4727 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
4728 break;
4729 }
4730 }
4731 else
4732 rcStrict = VINF_SUCCESS;
4733 break;
4734 }
4735
4736 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
4737 {
4738 if (!pThis->IommuBar.n.u1Enable)
4739 pThis->IommuBar.au32[1] = u32Value;
4740 else
4741 {
4742 rcStrict = VINF_SUCCESS;
4743 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
4744 }
4745 break;
4746 }
4747
4748 case IOMMU_PCI_OFF_MSI_CAP_HDR:
4749 {
4750 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
4751 RT_FALL_THRU();
4752 }
4753 default:
4754 {
4755 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
4756 break;
4757 }
4758 }
4759
4760 IOMMU_UNLOCK(pDevIns, pThisCC);
4761
4762 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
4763 return rcStrict;
4764}
4765
4766
4767/**
4768 * @callback_method_impl{FNDBGFHANDLERDEV}
4769 */
4770static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4771{
4772 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4773 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4774 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4775
4776 bool fVerbose;
4777 if ( pszArgs
4778 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
4779 fVerbose = true;
4780 else
4781 fVerbose = false;
4782
4783 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
4784 /* Device Table Base Addresses (all segments). */
4785 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
4786 {
4787 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
4788 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
4789 if (fVerbose)
4790 {
4791 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
4792 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
4793 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
4794 }
4795 }
4796 /* Command Buffer Base Address Register. */
4797 {
4798 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
4799 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
4800 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4801 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4802 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
4803 if (fVerbose)
4804 {
4805 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
4806 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4807 cEntries, cbBuffer);
4808 }
4809 }
4810 /* Event Log Base Address Register. */
4811 {
4812 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
4813 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
4814 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4815 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4816 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
4817 if (fVerbose)
4818 {
4819 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4820 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4821 cEntries, cbBuffer);
4822 }
4823 }
4824 /* IOMMU Control Register. */
4825 {
4826 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
4827 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
4828 if (fVerbose)
4829 {
4830 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
4831 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
4832 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
4833 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4834 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
4835 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
4836 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
4837 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
4838 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
4839 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
4840 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
4841 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
4842 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
4843 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
4844 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
4845 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
4846 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
4847 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
4848 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
4849 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
4850 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
4851 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
4852 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
4853 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
4854 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
4855 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
4856 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
4857 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
4858 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
4859 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
4860 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
4861 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
4862 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
4863 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
4864 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
4865 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
4866 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
4867 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
4868 }
4869 }
4870 /* Exclusion Base Address Register. */
4871 {
4872 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
4873 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
4874 if (fVerbose)
4875 {
4876 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
4877 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
4878 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
4879 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
4880 }
4881 }
4882 /* Exclusion Range Limit Register. */
4883 {
4884 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
4885 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
4886 if (fVerbose)
4887 {
4888 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
4889 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
4890 }
4891 }
4892 /* Extended Feature Register. */
4893 {
4894 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
4895 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
4896 if (fVerbose)
4897 {
4898 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
4899 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
4900 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
4901 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
4902 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
4903 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
4904 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
4905 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
4906 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
4907 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
4908 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
4909 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
4910 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
4911 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
4912 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
4913 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
4914 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
4915 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
4916 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
4917 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
4918 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
4919 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
4920 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
4921 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
4922 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
4923 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
4924 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
4925 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
4926 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
4927 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
4928 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
4929 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
4930 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
4931 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
4932 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
4933 }
4934 }
4935 /* PPR Log Base Address Register. */
4936 {
4937 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
4938 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
4939 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4940 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4941 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
4942 if (fVerbose)
4943 {
4944 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4945 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4946 cEntries, cbBuffer);
4947 }
4948 }
4949 /* Hardware Event (Hi) Register. */
4950 {
4951 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
4952 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
4953 if (fVerbose)
4954 {
4955 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
4956 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
4957 }
4958 }
4959 /* Hardware Event (Lo) Register. */
4960 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
4961 /* Hardware Event Status. */
4962 {
4963 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
4964 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
4965 if (fVerbose)
4966 {
4967 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
4968 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
4969 }
4970 }
4971 /* Guest Virtual-APIC Log Base Address Register. */
4972 {
4973 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
4974 uint8_t const uEncodedLen = GALogBar.n.u4Len;
4975 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4976 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4977 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
4978 if (fVerbose)
4979 {
4980 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
4981 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
4982 cEntries, cbBuffer);
4983 }
4984 }
4985 /* Guest Virtual-APIC Log Tail Address Register. */
4986 {
4987 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
4988 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
4989 if (fVerbose)
4990 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
4991 }
4992 /* PPR Log B Base Address Register. */
4993 {
4994 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
4995 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
4996 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
4997 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
4998 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
4999 if (fVerbose)
5000 {
5001 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5002 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5003 cEntries, cbBuffer);
5004 }
5005 }
5006 /* Event Log B Base Address Register. */
5007 {
5008 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5009 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5010 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5011 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5012 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5013 if (fVerbose)
5014 {
5015 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n", EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5016 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5017 cEntries, cbBuffer);
5018 }
5019 }
5020 /* Device-Specific Feature Extension Register. */
5021 {
5022 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5023 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5024 if (fVerbose)
5025 {
5026 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5027 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5028 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5029 }
5030 }
5031 /* Device-Specific Control Extension Register. */
5032 {
5033 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5034 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5035 if (fVerbose)
5036 {
5037 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5038 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5039 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5040 }
5041 }
5042 /* Device-Specific Status Extension Register. */
5043 {
5044 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5045 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5046 if (fVerbose)
5047 {
5048 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5049 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5050 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5051 }
5052 }
5053 /* Miscellaneous Information Register (Lo and Hi). */
5054 {
5055 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5056 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5057 if (fVerbose)
5058 {
5059 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5060 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5061 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5062 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5063 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5064 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5065 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5066 }
5067 }
5068 /* MSI Capability Header. */
5069 {
5070 MSI_CAP_HDR_T MsiCapHdr;
5071 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5072 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5073 if (fVerbose)
5074 {
5075 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5076 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5077 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5078 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5079 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5080 }
5081 }
5082 /* MSI Address Register (Lo and Hi). */
5083 {
5084 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5085 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5086 MSIADDR MsiAddr;
5087 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5088 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5089 if (fVerbose)
5090 {
5091 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5092 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5093 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5094 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5095 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5096 }
5097 }
5098 /* MSI Data. */
5099 {
5100 MSIDATA MsiData;
5101 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5102 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5103 if (fVerbose)
5104 {
5105 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5106 MsiData.n.u8Vector);
5107 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5108 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5109 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5110 "level" : "edge");
5111 }
5112 }
5113 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5114 {
5115 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5116 MsiMapCapHdr.u32 = 0;
5117 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5118 if (fVerbose)
5119 {
5120 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5121 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5122 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5123 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5124 }
5125 }
5126 /* Performance Optimization Control Register. */
5127 {
5128 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5129 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5130 if (fVerbose)
5131 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5132 }
5133 /* XT (x2APIC) General Interrupt Control Register. */
5134 {
5135 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5136 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5137 if (fVerbose)
5138 {
5139 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5140 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5141 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5142 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5143 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5144 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5145 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5146 }
5147 }
5148 /* XT (x2APIC) PPR Interrupt Control Register. */
5149 {
5150 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5151 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5152 if (fVerbose)
5153 {
5154 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5155 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5156 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5157 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5158 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5159 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5160 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5161 }
5162 }
5163 /* XT (X2APIC) GA Log Interrupt Control Register. */
5164 {
5165 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5166 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5167 if (fVerbose)
5168 {
5169 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5170 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5171 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5172 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5173 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5174 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5175 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5176 }
5177 }
5178 /* MARC Registers. */
5179 {
5180 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5181 {
5182 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5183 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5184 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5185
5186 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5187 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5188 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5189 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5190
5191 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5192 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5193 }
5194 }
5195 /* Reserved Register. */
5196 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5197 /* Command Buffer Head Pointer Register. */
5198 {
5199 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5200 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5201 CmdBufHeadPtr.n.off);
5202 }
5203 /* Command Buffer Tail Pointer Register. */
5204 {
5205 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5206 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5207 CmdBufTailPtr.n.off);
5208 }
5209 /* Event Log Head Pointer Register. */
5210 {
5211 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5212 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5213 EvtLogHeadPtr.n.off);
5214 }
5215 /* Event Log Tail Pointer Register. */
5216 {
5217 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5218 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5219 EvtLogTailPtr.n.off);
5220 }
5221 /* Status Register. */
5222 {
5223 IOMMU_STATUS_T const Status = pThis->Status;
5224 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5225 if (fVerbose)
5226 {
5227 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5228 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5229 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5230 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5231 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5232 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5233 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5234 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5235 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5236 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5237 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5238 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5239 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5240 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5241 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5242 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5243 }
5244 }
5245 /* PPR Log Head Pointer. */
5246 {
5247 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5248 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5249 PprLogHeadPtr.n.off);
5250 }
5251 /* PPR Log Tail Pointer. */
5252 {
5253 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5254 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5255 PprLogTailPtr.n.off);
5256 }
5257 /* Guest Virtual-APIC Log Head Pointer. */
5258 {
5259 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5260 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5261 GALogHeadPtr.n.u12GALogPtr);
5262 }
5263 /* Guest Virtual-APIC Log Tail Pointer. */
5264 {
5265 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5266 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5267 GALogTailPtr.n.u12GALogPtr);
5268 }
5269 /* PPR Log B Head Pointer. */
5270 {
5271 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5272 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5273 PprLogBHeadPtr.n.off);
5274 }
5275 /* PPR Log B Tail Pointer. */
5276 {
5277 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5278 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5279 PprLogBTailPtr.n.off);
5280 }
5281 /* Event Log B Head Pointer. */
5282 {
5283 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5284 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5285 EvtLogBHeadPtr.n.off);
5286 }
5287 /* Event Log B Tail Pointer. */
5288 {
5289 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5290 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5291 EvtLogBTailPtr.n.off);
5292 }
5293 /* PPR Log Auto Response Register. */
5294 {
5295 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5296 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5297 if (fVerbose)
5298 {
5299 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5300 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5301 }
5302 }
5303 /* PPR Log Overflow Early Warning Indicator Register. */
5304 {
5305 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5306 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5307 if (fVerbose)
5308 {
5309 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5310 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5311 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5312 }
5313 }
5314 /* PPR Log Overflow Early Warning Indicator Register. */
5315 {
5316 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5317 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5318 if (fVerbose)
5319 {
5320 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5321 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5322 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5323 }
5324 }
5325}
5326
5327
5328/**
5329 * Dumps the DTE via the info callback helper.
5330 *
5331 * @param pHlp The info helper.
5332 * @param pDte The device table entry.
5333 * @param pszPrefix The string prefix.
5334 */
5335static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5336{
5337 AssertReturnVoid(pHlp);
5338 AssertReturnVoid(pDte);
5339 AssertReturnVoid(pszPrefix);
5340
5341 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5342 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5343 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5344 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5345 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5346 pDte->n.u40PageTableRootPtrLo << 12);
5347 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5348 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5349 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5350 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5351 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5352 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5353 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5354 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5355 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5356 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5357 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5358 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5359 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5360 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5361 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5362 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5363 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5364 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5365 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5366 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5367 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5368 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5369 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5370 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5371 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5372 {
5373 uint16_t const cEntries = IOMMU_GET_INTR_TAB_ENTRIES(pDte);
5374 uint16_t const cbIntrTable = IOMMU_GET_INTR_TAB_LEN(pDte);
5375 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
5376 cbIntrTable);
5377 }
5378 else
5379 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
5380 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
5381 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
5382 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
5383 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
5384 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
5385 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
5386 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
5387 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
5388 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
5389 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
5390 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
5391 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
5392 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
5393 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
5394 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
5395 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
5396 pHlp->pfnPrintf(pHlp, "\n");
5397}
5398
5399
5400/**
5401 * @callback_method_impl{FNDBGFHANDLERDEV}
5402 */
5403static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5404{
5405 if (pszArgs)
5406 {
5407 uint16_t uDevId = 0;
5408 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDevId);
5409 if (RT_SUCCESS(rc))
5410 {
5411 DTE_T Dte;
5412 rc = iommuAmdDteRead(pDevIns, uDevId, IOMMUOP_TRANSLATE_REQ, &Dte);
5413 if (RT_SUCCESS(rc))
5414 {
5415 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", uDevId);
5416 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
5417 return;
5418 }
5419 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", uDevId, uDevId, rc);
5420 }
5421 else
5422 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
5423 }
5424 else
5425 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
5426}
5427
5428
5429#if defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)
5430/**
5431 * @callback_method_impl{FNDBGFHANDLERDEV}
5432 */
5433static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5434{
5435 if (pszArgs)
5436 {
5437 uint16_t uDomainId = 0;
5438 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &uDomainId);
5439 if (RT_SUCCESS(rc))
5440 {
5441 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", uDomainId, uDomainId);
5442 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5443 IOTLBEINFOARG Args;
5444 Args.pIommu = pThis;
5445 Args.pHlp = pHlp;
5446 Args.uDomainId = uDomainId;
5447
5448 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
5449 RTAvlU64DoWithAll(&pThis->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
5450 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
5451 }
5452 else
5453 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
5454 }
5455 else
5456 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
5457}
5458#endif
5459
5460
5461/**
5462 * @callback_method_impl{FNDBGFHANDLERDEV}
5463 */
5464static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5465{
5466 RT_NOREF(pszArgs);
5467
5468 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5469 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5470 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5471 NOREF(pPciDev);
5472
5473 uint8_t cSegments = 0;
5474 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5475 {
5476 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5477 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
5478 if (GCPhysDevTab)
5479 ++cSegments;
5480 }
5481
5482 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
5483 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
5484 if (!cSegments)
5485 return;
5486
5487 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5488 {
5489 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5490 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
5491 if (GCPhysDevTab)
5492 {
5493 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
5494 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
5495
5496 void *pvDevTab = RTMemAllocZ(cbDevTab);
5497 if (RT_LIKELY(pvDevTab))
5498 {
5499 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
5500 if (RT_SUCCESS(rc))
5501 {
5502 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
5503 {
5504 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
5505 if ( pDte->n.u1Valid
5506 && pDte->n.u1TranslationValid
5507 && pDte->n.u3Mode != 0)
5508 {
5509 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
5510 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
5511 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
5512 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
5513 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
5514 pHlp->pfnPrintf(pHlp, "\n");
5515 }
5516 }
5517 pHlp->pfnPrintf(pHlp, "\n");
5518 }
5519 else
5520 {
5521 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
5522 cbDevTab, rc);
5523 }
5524
5525 RTMemFree(pvDevTab);
5526 }
5527 else
5528 {
5529 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
5530 return;
5531 }
5532 }
5533 }
5534}
5535
5536
5537/**
5538 * @callback_method_impl{FNSSMDEVSAVEEXEC}
5539 */
5540static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5541{
5542 /** @todo IOMMU: Save state. */
5543 RT_NOREF2(pDevIns, pSSM);
5544 LogFlowFunc(("\n"));
5545 return VERR_NOT_IMPLEMENTED;
5546}
5547
5548
5549/**
5550 * @callback_method_impl{FNSSMDEVLOADEXEC}
5551 */
5552static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5553{
5554 /** @todo IOMMU: Load state. */
5555 RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
5556 LogFlowFunc(("\n"));
5557 return VERR_NOT_IMPLEMENTED;
5558}
5559
5560
5561/**
5562 * @interface_method_impl{PDMDEVREG,pfnReset}
5563 */
5564static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
5565{
5566 /*
5567 * Resets read-write portion of the IOMMU state.
5568 *
5569 * NOTE! State not initialized here is expected to be initialized during
5570 * device construction and remain read-only through the lifetime of the VM.
5571 */
5572 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5573 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5574 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5575 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5576
5577 IOMMU_LOCK_NORET(pDevIns, pThisCC);
5578
5579 LogFlowFunc(("\n"));
5580
5581 memset(&pThis->aDevTabBaseAddrs[0], 0, sizeof(pThis->aDevTabBaseAddrs));
5582
5583 pThis->CmdBufBaseAddr.u64 = 0;
5584 pThis->CmdBufBaseAddr.n.u4Len = 8;
5585
5586 pThis->EvtLogBaseAddr.u64 = 0;
5587 pThis->EvtLogBaseAddr.n.u4Len = 8;
5588
5589 pThis->Ctrl.u64 = 0;
5590 pThis->Ctrl.n.u1Coherent = 1;
5591 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
5592
5593 pThis->ExclRangeBaseAddr.u64 = 0;
5594 pThis->ExclRangeLimit.u64 = 0;
5595
5596 pThis->PprLogBaseAddr.u64 = 0;
5597 pThis->PprLogBaseAddr.n.u4Len = 8;
5598
5599 pThis->HwEvtHi.u64 = 0;
5600 pThis->HwEvtLo = 0;
5601 pThis->HwEvtStatus.u64 = 0;
5602
5603 pThis->GALogBaseAddr.u64 = 0;
5604 pThis->GALogBaseAddr.n.u4Len = 8;
5605 pThis->GALogTailAddr.u64 = 0;
5606
5607 pThis->PprLogBBaseAddr.u64 = 0;
5608 pThis->PprLogBBaseAddr.n.u4Len = 8;
5609
5610 pThis->EvtLogBBaseAddr.u64 = 0;
5611 pThis->EvtLogBBaseAddr.n.u4Len = 8;
5612
5613 pThis->PerfOptCtrl.u32 = 0;
5614
5615 pThis->XtGenIntrCtrl.u64 = 0;
5616 pThis->XtPprIntrCtrl.u64 = 0;
5617 pThis->XtGALogIntrCtrl.u64 = 0;
5618
5619 memset(&pThis->aMarcApers[0], 0, sizeof(pThis->aMarcApers));
5620
5621 pThis->CmdBufHeadPtr.u64 = 0;
5622 pThis->CmdBufTailPtr.u64 = 0;
5623 pThis->EvtLogHeadPtr.u64 = 0;
5624 pThis->EvtLogTailPtr.u64 = 0;
5625
5626 pThis->Status.u64 = 0;
5627
5628 pThis->PprLogHeadPtr.u64 = 0;
5629 pThis->PprLogTailPtr.u64 = 0;
5630
5631 pThis->GALogHeadPtr.u64 = 0;
5632 pThis->GALogTailPtr.u64 = 0;
5633
5634 pThis->PprLogBHeadPtr.u64 = 0;
5635 pThis->PprLogBTailPtr.u64 = 0;
5636
5637 pThis->EvtLogBHeadPtr.u64 = 0;
5638 pThis->EvtLogBTailPtr.u64 = 0;
5639
5640 pThis->PprLogAutoResp.u64 = 0;
5641 pThis->PprLogOverflowEarly.u64 = 0;
5642 pThis->PprLogBOverflowEarly.u64 = 0;
5643
5644 pThis->IommuBar.u64 = 0;
5645 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
5646 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
5647
5648 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
5649
5650 IOMMU_UNLOCK(pDevIns, pThisCC);
5651
5652#ifdef IOMMU_WITH_IOTLBE_CACHE
5653 iommuAmdDteCacheRemoveAll(pDevIns);
5654 iommuAmdIotlbRemoveAll(pDevIns);
5655#endif
5656}
5657
5658
5659/**
5660 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5661 */
5662static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
5663{
5664 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
5665 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5666 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5667 LogFlowFunc(("\n"));
5668
5669 IOMMU_LOCK_NORET(pDevIns, pThisCC);
5670
5671 /* Close the command thread semaphore. */
5672 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
5673 {
5674 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
5675 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
5676 }
5677
5678#ifdef IOMMU_WITH_IOTLBE_CACHE
5679 /* Destroy level 1 cache. */
5680 if (pThis->paDevices)
5681 {
5682 PDMDevHlpMMHeapFree(pDevIns, pThis->paDevices);
5683 pThis->paDevices = NULL;
5684 }
5685
5686 /* Destroy level 2 cache. */
5687 if (pThis->paIotlbes)
5688 {
5689 PDMDevHlpMMHeapFree(pDevIns, pThis->paIotlbes);
5690 pThis->paIotlbes = NULL;
5691 }
5692#endif
5693
5694 IOMMU_UNLOCK(pDevIns, pThisCC);
5695 return VINF_SUCCESS;
5696}
5697
5698
5699/**
5700 * @interface_method_impl{PDMDEVREG,pfnConstruct}
5701 */
5702static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
5703{
5704 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
5705 RT_NOREF(pCfg);
5706
5707 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5708 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
5709 pThis->u32Magic = IOMMU_MAGIC;
5710 pThisCC->pDevInsR3 = pDevIns;
5711
5712 LogFlowFunc(("iInstance=%d\n", iInstance));
5713
5714 /*
5715 * Register the IOMMU with PDM.
5716 */
5717 PDMIOMMUREGR3 IommuReg;
5718 RT_ZERO(IommuReg);
5719 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
5720 IommuReg.pfnMemAccess = iommuAmdMemAccess;
5721 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
5722 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
5723 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
5724 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
5725 if (RT_FAILURE(rc))
5726 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
5727 if (pThisCC->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
5728 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5729 N_("IOMMU helper version mismatch; got %#x expected %#x"),
5730 pThisCC->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
5731 if (pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
5732 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
5733 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
5734 pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
5735
5736 /*
5737 * We will use PDM's critical section (via helpers) for the IOMMU device.
5738 */
5739 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
5740 AssertRCReturn(rc, rc);
5741
5742 /*
5743 * Initialize read-only PCI configuration space.
5744 */
5745 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5746 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5747
5748 /* Header. */
5749 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
5750 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
5751 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
5752 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
5753 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
5754 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
5755 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
5756 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
5757 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
5758 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
5759 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
5760 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
5761 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
5762 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
5763
5764 /* Capability Header. */
5765 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
5766 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
5767 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
5768 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
5769 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
5770 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
5771 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
5772 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
5773 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
5774 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
5775 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
5776
5777 /* Base Address Register. */
5778 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
5779 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
5780
5781 /* IOMMU Range Register. */
5782 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
5783
5784 /* Misc. Information Register. */
5785 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
5786 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
5787 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
5788 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
5789 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
5790 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
5791 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
5792 uint32_t const uMiscInfoReg1 = 0;
5793 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
5794 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
5795
5796 /* MSI Capability Header register. */
5797 PDMMSIREG MsiReg;
5798 RT_ZERO(MsiReg);
5799 MsiReg.cMsiVectors = 1;
5800 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
5801 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
5802 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
5803
5804 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
5805#if 0
5806 /* MSI Address Lo. */
5807 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
5808 /* MSI Address Hi. */
5809 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
5810 /* MSI Data. */
5811 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
5812#endif
5813
5814#if 0
5815 /** @todo IOMMU: I don't know if we need to support this, enable later if
5816 * required. */
5817 /* MSI Mapping Capability Header register. */
5818 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
5819 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
5820 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
5821 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
5822 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
5823 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
5824 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
5825#endif
5826
5827 /*
5828 * Register the PCI function with PDM.
5829 */
5830 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
5831 AssertLogRelRCReturn(rc, rc);
5832
5833 /*
5834 * Register MSI support for the PCI device.
5835 * This must be done -after- register it as a PCI device!
5836 */
5837 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5838 AssertRCReturn(rc, rc);
5839
5840 /*
5841 * Intercept PCI config. space accesses.
5842 */
5843 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
5844 AssertLogRelRCReturn(rc, rc);
5845
5846 /*
5847 * Create the MMIO region.
5848 * Mapping of the region is done when software configures it via PCI config space.
5849 */
5850 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
5851 NULL /* pvUser */,
5852 IOMMMIO_FLAGS_READ_DWORD_QWORD
5853 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
5854 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
5855 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
5856 "AMD-IOMMU", &pThis->hMmio);
5857 AssertLogRelRCReturn(rc, rc);
5858
5859 /*
5860 * Register saved state.
5861 */
5862 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL,
5863 NULL, NULL, NULL,
5864 NULL, iommuAmdR3SaveExec, NULL,
5865 NULL, iommuAmdR3LoadExec, NULL);
5866 AssertLogRelRCReturn(rc, rc);
5867
5868 /*
5869 * Register debugger info items.
5870 */
5871 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
5872 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device. Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
5873 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display active IOMMU device tables.", iommuAmdR3DbgInfoDevTabs);
5874#ifdef IOMMU_WITH_IOTLBE_CACHE
5875 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
5876#endif
5877
5878# ifdef VBOX_WITH_STATISTICS
5879 /*
5880 * Statistics.
5881 */
5882 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
5883 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
5884
5885 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
5886 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
5887
5888 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
5889 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
5890
5891 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
5892 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
5893
5894 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
5895 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
5896
5897 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
5898 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
5899
5900 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
5901 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
5902
5903 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
5904 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
5905 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
5906 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
5907 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
5908 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
5909 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
5910 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
5911 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
5912
5913 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLookupNonContig, STAMTYPE_COUNTER, "IOTLB/LookupNonContig", STAMUNIT_OCCURENCES, "IOTLB lookups that resulted in non-contiguous translated regions.");
5914 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
5915 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCacheHit, STAMTYPE_COUNTER, "IOTLB/CacheHit", STAMUNIT_OCCURENCES, "Number of IOTLB cache hits.");
5916 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCacheMiss, STAMTYPE_COUNTER, "IOTLB/CacheMiss", STAMUNIT_OCCURENCES, "Number of IOTLB cache misses.");
5917 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
5918 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLookup, STAMTYPE_PROFILE, "IOTLB/Lookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLB entry lookup.");
5919
5920 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDteLookupNonContig, STAMTYPE_COUNTER, "DTE/LookupNonContig", STAMUNIT_OCCURENCES, "DTE lookups that resulted in non-contiguous translated regions.");
5921 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIoPageWalkLookup, STAMTYPE_PROFILE, "DTE/Lookup", STAMUNIT_TICKS_PER_CALL, "Profiling I/O page walk lookup.");
5922# endif
5923
5924 /*
5925 * Create the command thread and its event semaphore.
5926 */
5927 char szDevIommu[64];
5928 RT_ZERO(szDevIommu);
5929 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
5930 rc = PDMDevHlpThreadCreate(pDevIns, &pThisCC->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
5931 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
5932 AssertLogRelRCReturn(rc, rc);
5933
5934 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
5935 AssertLogRelRCReturn(rc, rc);
5936
5937#ifdef IOMMU_WITH_IOTLBE_CACHE
5938 /*
5939 * Initialize the critsect of the cache.
5940 */
5941 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
5942 AssertLogRelRCReturn(rc, rc);
5943
5944 /*
5945 * Allocate the level 1 cache (device ID to domain ID mapping).
5946 * PCI devices are hotpluggable, plus we don't have a way of querying the bus for all
5947 * assigned PCI BDF slots. So while this wastes some memory, it should work regardless
5948 * of how code, features and devices around the IOMMU changes.
5949 */
5950 size_t const cbDevices = sizeof(IODEVICE) * IOMMU_DTE_CACHE_MAX;
5951 AssertCompile(IOMMU_DTE_CACHE_MAX >= UINT16_MAX);
5952 pThis->paDevices = (PIODEVICE)PDMDevHlpMMHeapAllocZ(pDevIns, cbDevices);
5953 if (!pThis->paDevices)
5954 {
5955 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
5956 N_("Failed to allocate %zu bytes from the hyperheap for the IOMMU level 1 cache."), cbDevices);
5957 }
5958
5959 /*
5960 * Allocate the level 2 cache (IOTLB entries).
5961 * This is allocated upfront since we expect a relatively small number of entries,
5962 * is more cache-line efficient and easier to track least recently used entries for
5963 * eviction when the cache is full. This also prevents unpredictable behavior during
5964 * the lifetime of the VM if the hyperheap gets full as allocation would fail upfront
5965 * or not at all.
5966 */
5967 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
5968 pThis->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
5969 if (!pThis->paIotlbes)
5970 {
5971 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
5972 N_("Failed to allocate %zu bytes from the hyperheap for the IOMMU level 2 cache."),
5973 cbIotlbes);
5974 }
5975 RTListInit(&pThis->LstLruIotlbe);
5976
5977 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbDevices + cbIotlbes));
5978#endif
5979
5980 /*
5981 * Initialize read-only registers.
5982 * NOTE! Fields here must match their corresponding field in the ACPI tables.
5983 */
5984 /* Don't remove the commented lines below as it lets us see all features at a glance. */
5985 pThis->ExtFeat.u64 = 0;
5986 //pThis->ExtFeat.n.u1PrefetchSup = 0;
5987 //pThis->ExtFeat.n.u1PprSup = 0;
5988 //pThis->ExtFeat.n.u1X2ApicSup = 0;
5989 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
5990 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
5991 pThis->ExtFeat.n.u1InvAllSup = 1;
5992 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
5993 pThis->ExtFeat.n.u1HwErrorSup = 1;
5994 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
5995 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
5996 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
5997 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
5998 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
5999 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
6000 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
6001 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
6002 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
6003 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
6004 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
6005 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
6006 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
6007 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
6008 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
6009 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
6010 //pThis->ExtFeat.n.u2MarcSup = 0;
6011 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
6012 //pThis->ExtFeat.n.u1PerfOptSup = 0;
6013 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
6014 //pThis->ExtFeat.n.u1GstIoSup = 0;
6015 //pThis->ExtFeat.n.u1HostAccessSup = 0;
6016 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
6017 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
6018 //pThis->ExtFeat.n.u1HostDirtySup = 0;
6019 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
6020 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
6021 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
6022
6023 pThis->RsvdReg = 0;
6024
6025 pThis->DevSpecificFeat.u64 = 0;
6026 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
6027 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
6028
6029 pThis->DevSpecificCtrl.u64 = 0;
6030 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
6031 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
6032
6033 pThis->DevSpecificStatus.u64 = 0;
6034 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
6035 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
6036
6037 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
6038
6039 /*
6040 * Initialize parts of the IOMMU state as it would during reset.
6041 * Must be called -after- initializing PCI config. space registers.
6042 */
6043 iommuAmdR3Reset(pDevIns);
6044
6045 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6046 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6047 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6048 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6049 pThis->ExtFeat.u64));
6050 return VINF_SUCCESS;
6051}
6052
6053#else
6054
6055/**
6056 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
6057 */
6058static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
6059{
6060 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6061 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6062 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
6063 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
6064
6065 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
6066 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6067 AssertRCReturn(rc, rc);
6068
6069 /* Set up the MMIO RZ handlers. */
6070 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
6071 AssertRCReturn(rc, rc);
6072
6073 /* Set up the IOMMU RZ callbacks. */
6074 PDMIOMMUREGCC IommuReg;
6075 RT_ZERO(IommuReg);
6076 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6077 IommuReg.idxIommu = pThis->idxIommu;
6078 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6079 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6080 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6081 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6082 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
6083 AssertRCReturn(rc, rc);
6084 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
6085 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
6086 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
6087 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
6088 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
6089 return VINF_SUCCESS;
6090}
6091#endif
6092
6093
6094/**
6095 * The device registration structure.
6096 */
6097const PDMDEVREG g_DeviceIommuAmd =
6098{
6099 /* .u32Version = */ PDM_DEVREG_VERSION,
6100 /* .uReserved0 = */ 0,
6101 /* .szName = */ "iommu-amd",
6102 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
6103 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
6104 /* .cMaxInstances = */ ~0U,
6105 /* .uSharedVersion = */ 42,
6106 /* .cbInstanceShared = */ sizeof(IOMMU),
6107 /* .cbInstanceCC = */ sizeof(IOMMUCC),
6108 /* .cbInstanceRC = */ sizeof(IOMMURC),
6109 /* .cMaxPciDevices = */ 1,
6110 /* .cMaxMsixVectors = */ 0,
6111 /* .pszDescription = */ "IOMMU (AMD)",
6112#if defined(IN_RING3)
6113 /* .pszRCMod = */ "VBoxDDRC.rc",
6114 /* .pszR0Mod = */ "VBoxDDR0.r0",
6115 /* .pfnConstruct = */ iommuAmdR3Construct,
6116 /* .pfnDestruct = */ iommuAmdR3Destruct,
6117 /* .pfnRelocate = */ NULL,
6118 /* .pfnMemSetup = */ NULL,
6119 /* .pfnPowerOn = */ NULL,
6120 /* .pfnReset = */ iommuAmdR3Reset,
6121 /* .pfnSuspend = */ NULL,
6122 /* .pfnResume = */ NULL,
6123 /* .pfnAttach = */ NULL,
6124 /* .pfnDetach = */ NULL,
6125 /* .pfnQueryInterface = */ NULL,
6126 /* .pfnInitComplete = */ NULL,
6127 /* .pfnPowerOff = */ NULL,
6128 /* .pfnSoftReset = */ NULL,
6129 /* .pfnReserved0 = */ NULL,
6130 /* .pfnReserved1 = */ NULL,
6131 /* .pfnReserved2 = */ NULL,
6132 /* .pfnReserved3 = */ NULL,
6133 /* .pfnReserved4 = */ NULL,
6134 /* .pfnReserved5 = */ NULL,
6135 /* .pfnReserved6 = */ NULL,
6136 /* .pfnReserved7 = */ NULL,
6137#elif defined(IN_RING0)
6138 /* .pfnEarlyConstruct = */ NULL,
6139 /* .pfnConstruct = */ iommuAmdRZConstruct,
6140 /* .pfnDestruct = */ NULL,
6141 /* .pfnFinalDestruct = */ NULL,
6142 /* .pfnRequest = */ NULL,
6143 /* .pfnReserved0 = */ NULL,
6144 /* .pfnReserved1 = */ NULL,
6145 /* .pfnReserved2 = */ NULL,
6146 /* .pfnReserved3 = */ NULL,
6147 /* .pfnReserved4 = */ NULL,
6148 /* .pfnReserved5 = */ NULL,
6149 /* .pfnReserved6 = */ NULL,
6150 /* .pfnReserved7 = */ NULL,
6151#elif defined(IN_RC)
6152 /* .pfnConstruct = */ iommuAmdRZConstruct,
6153 /* .pfnReserved0 = */ NULL,
6154 /* .pfnReserved1 = */ NULL,
6155 /* .pfnReserved2 = */ NULL,
6156 /* .pfnReserved3 = */ NULL,
6157 /* .pfnReserved4 = */ NULL,
6158 /* .pfnReserved5 = */ NULL,
6159 /* .pfnReserved6 = */ NULL,
6160 /* .pfnReserved7 = */ NULL,
6161#else
6162# error "Not in IN_RING3, IN_RING0 or IN_RC!"
6163#endif
6164 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
6165};
6166
6167#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
6168
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