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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 88614

Last change on this file since 88614 was 88614, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Build fix.
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1/* $Id: DevIommuAmd.cpp 88614 2021-04-21 02:45:05Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26
27#include <iprt/x86.h>
28#include <iprt/string.h>
29#include <iprt/avl.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47
48/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
49#ifdef IN_RING3
50# define IOMMU_WITH_IOTLBE_CACHE
51#endif
52/** Enable the interrupt cache. */
53#define IOMMU_WITH_IRTE_CACHE
54
55/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
56#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
57# define IOMMU_WITH_DTE_CACHE
58/** The maximum number of device IDs in the cache. */
59# define IOMMU_DEV_CACHE_COUNT 16
60/** An empty device ID. */
61# define IOMMU_DTE_CACHE_KEY_NIL 0
62#endif
63
64#ifdef IOMMU_WITH_IRTE_CACHE
65/** The maximum number of IRTE cache entries. */
66# define IOMMU_IRTE_CACHE_COUNT 32
67/** A NIL IRTE cache entry key. */
68# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
69/** Gets the device ID from an IRTE cache entry key. */
70#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
71/** Gets the IOVA from the IOTLB entry key. */
72# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
73/** Makes an IRTE cache entry key.
74 *
75 * Bits 31:16 is the device ID (Bus, Device, Function).
76 * Bits 15:0 is the the offset into the IRTE table.
77 */
78# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
79#endif /* IOMMU_WITH_IRTE_CACHE */
80
81#ifdef IOMMU_WITH_IOTLBE_CACHE
82/** The maximum number of IOTLB entries. */
83# define IOMMU_IOTLBE_MAX 96
84/** The mask of bits covering the domain ID in the IOTLBE key. */
85# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
86/** The mask of bits covering the IOVA in the IOTLBE key. */
87# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
88/** The number of bits to shift for the domain ID of the IOTLBE key. */
89# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
90/** A NIL IOTLB key. */
91# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
92/** Gets the domain ID from an IOTLB entry key. */
93# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
94/** Gets the IOVA from the IOTLB entry key. */
95# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
96/** Makes an IOTLB entry key.
97 *
98 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
99 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
100 * so bottom 12 bits are free.
101 *
102 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
103 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
104 */
105# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
106 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
107#endif /* IOMMU_WITH_IOTLBE_CACHE */
108
109#ifdef IOMMU_WITH_DTE_CACHE
110/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
111 *
112 * Some of these flags are "basic" i.e. they correspond directly to their bits in
113 * the DTE. The rest of the flags are based on checks or operations on several DTE
114 * bits.
115 *
116 * The basic flags are:
117 * - VALID (DTE.V)
118 * - IO_PERM_READ (DTE.IR)
119 * - IO_PERM_WRITE (DTE.IW)
120 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
121 * masking consistent)
122 * - SUPPRESS_ALL_IOPF (DTE.SA)
123 * - SUPPRESS_IOPF (DTE.SE)
124 * - INTR_MAP_VALID (DTE.IV)
125 * - IGNORE_UNMAPPED_INTR (DTE.IG)
126 *
127 * @see iommuAmdGetBasicDevFlags()
128 * @{ */
129/** The DTE is present. */
130# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
131/** The DTE is valid. */
132# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
133/** The DTE permissions apply for address translations. */
134# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
135/** DTE permission - I/O read allowed. */
136# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
137/** DTE permission - I/O write allowed. */
138# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
139/** DTE permission - reserved. */
140# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
141/** Address translation required. */
142# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
143/** Suppress all I/O page faults. */
144# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
145/** Suppress I/O page faults. */
146# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
147/** Interrupt map valid. */
148# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
149/** Ignore unmapped interrupts. */
150# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
151/** An I/O page fault has been raised for this device. */
152# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
153/** Fixed and arbitrary interrupt control: Target Abort. */
154# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
155/** Fixed and arbitrary interrupt control: Forward unmapped. */
156# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
157/** Fixed and arbitrary interrupt control: Remapped. */
158# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
159/** Fixed and arbitrary interrupt control: Reserved. */
160# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
161/** @} */
162
163/** The number of bits to shift I/O device flags for DTE permissions. */
164# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
165/** The mask of DTE permissions in I/O device flags. */
166# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
167/** The number of bits to shift I/O device flags for interrupt control bits. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
169/** The mask of interrupt control bits in I/O device flags. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
171/** The number of bits to shift for ignore-unmapped interrupts bit. */
172# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
173
174/** Acquires the cache lock. */
175# define IOMMU_LOCK_CACHE(a_pDevIns, a_pThis) \
176 do { \
177 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
178 if (rcLock == VINF_SUCCESS) \
179 { /* likely */ } \
180 else \
181 { \
182 AssertRC(rcLock); \
183 return rcLock; \
184 } \
185 } while (0)
186
187/** Acquires the cache lock (asserts on failure). */
188# define IOMMU_LOCK_CACHE_NORET(a_pDevIns, a_pThis) \
189 do { \
190 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
191 AssertRC(rcLock); \
192 } while (0)
193
194/** Releases the cache lock. */
195# define IOMMU_UNLOCK_CACHE(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
196#endif /* IOMMU_WITH_DTE_CACHE */
197
198/** Gets the page offset mask given the number of bits to shift. */
199#define IOMMU_GET_PAGE_OFF_MASK(a_cShift) (~(UINT64_C(0xffffffffffffffff) << (a_cShift)))
200
201/** Acquires the PDM lock. */
202#define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
203 do { \
204 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
205 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
206 { /* likely */ } \
207 else \
208 return rcLock; \
209 } while (0)
210
211/** Acquires the PDM lock (asserts on failure). */
212#define IOMMU_LOCK_NORET(a_pDevIns, a_pThisCC) \
213 do { \
214 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
215 AssertRC(rcLock); \
216 } while (0)
217
218/** Releases the PDM lock. */
219# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
220
221
222/*********************************************************************************************************************************
223* Structures and Typedefs *
224*********************************************************************************************************************************/
225/**
226 * IOMMU operation (transaction).
227 */
228typedef enum IOMMUOP
229{
230 /** Address translation request. */
231 IOMMUOP_TRANSLATE_REQ = 0,
232 /** Memory read request. */
233 IOMMUOP_MEM_READ,
234 /** Memory write request. */
235 IOMMUOP_MEM_WRITE,
236 /** Interrupt request. */
237 IOMMUOP_INTR_REQ,
238 /** Command. */
239 IOMMUOP_CMD
240} IOMMUOP;
241/** Pointer to a IOMMU operation. */
242typedef IOMMUOP *PIOMMUOP;
243
244/**
245 * I/O page lookup.
246 */
247typedef struct IOPAGELOOKUP
248{
249 /** The translated system physical address. */
250 RTGCPHYS GCPhysSpa;
251 /** The number of offset bits in the system physical address. */
252 uint8_t cShift;
253 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
254 uint8_t fPerm;
255} IOPAGELOOKUP;
256/** Pointer to an I/O page lookup. */
257typedef IOPAGELOOKUP *PIOPAGELOOKUP;
258/** Pointer to a const I/O page lookup. */
259typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
260
261/**
262 * I/O address range.
263 */
264typedef struct IOADDRRANGE
265{
266 /** The address (virtual or physical). */
267 uint64_t uAddr;
268 /** The size of the access in bytes. */
269 size_t cb;
270 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
271 uint8_t fPerm;
272} IOADDRRANGE;
273/** Pointer to an I/O address range. */
274typedef IOADDRRANGE *PIOADDRRANGE;
275/** Pointer to a const I/O address range. */
276typedef IOADDRRANGE const *PCIOADDRRANGE;
277
278#ifdef IOMMU_WITH_DTE_CACHE
279/**
280 * Device Table Entry Cache.
281 */
282typedef struct DTECACHE
283{
284 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
285 uint16_t fFlags;
286 /** The domain ID assigned for this device by software. */
287 uint16_t idDomain;
288} DTECACHE;
289/** Pointer to an I/O device struct. */
290typedef DTECACHE *PDTECACHE;
291/** Pointer to a const I/O device struct. */
292typedef DTECACHE *PCDTECACHE;
293AssertCompileSize(DTECACHE, 4);
294#endif /* IOMMU_WITH_DTE_CACHE */
295
296#ifdef IOMMU_WITH_IOTLBE_CACHE
297/**
298 * I/O TLB Entry.
299 * Keep this as small and aligned as possible.
300 */
301typedef struct IOTLBE
302{
303 /** The AVL tree node. */
304 AVLU64NODECORE Core;
305 /** The least recently used (LRU) list node. */
306 RTLISTNODE NdLru;
307 /** The I/O page lookup results of the translation. */
308 IOPAGELOOKUP PageLookup;
309 /** Whether the entry needs to be evicted from the cache. */
310 bool fEvictPending;
311} IOTLBE;
312/** Pointer to an IOMMU I/O TLB entry struct. */
313typedef IOTLBE *PIOTLBE;
314/** Pointer to a const IOMMU I/O TLB entry struct. */
315typedef IOTLBE const *PCIOTLBE;
316AssertCompileSizeAlignment(IOTLBE, 8);
317AssertCompileMemberOffset(IOTLBE, Core, 0);
318#endif /* IOMMU_WITH_IOTLBE_CACHE */
319
320#ifdef IOMMU_WITH_IRTE_CACHE
321/**
322 * Interrupt Remap Table Entry Cache.
323 */
324typedef struct IRTECACHE
325{
326 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
327 uint32_t uKey;
328 /** The IRTE. */
329 IRTE_T Irte;
330} IRTECACHE;
331/** Pointer to an IRTE cache struct. */
332typedef IRTECACHE *PIRTECACHE;
333/** Pointer to a const IRTE cache struct. */
334typedef IRTECACHE const *PCIRTECACHE;
335AssertCompileSizeAlignment(IRTECACHE, 4);
336#endif /* IOMMU_WITH_IRTE_CACHE */
337
338/**
339 * The shared IOMMU device state.
340 */
341typedef struct IOMMU
342{
343 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
344 uint32_t idxIommu;
345 /** IOMMU magic. */
346 uint32_t u32Magic;
347
348 /** The MMIO handle. */
349 IOMMMIOHANDLE hMmio;
350 /** The event semaphore the command thread waits on. */
351 SUPSEMEVENT hEvtCmdThread;
352 /** Whether the command thread has been signaled for wake up. */
353 bool volatile fCmdThreadSignaled;
354 /** Padding. */
355 bool afPadding0[7];
356
357#ifdef IOMMU_WITH_DTE_CACHE
358 /** The critsect that protects the cache from concurrent access. */
359 PDMCRITSECT CritSectCache;
360 /** Array of device IDs. */
361 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
362 /** Array of DTE cache entries. */
363 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
364#endif
365#ifdef IOMMU_WITH_IRTE_CACHE
366 /** Array of IRTE cache entries. */
367 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
368#endif
369
370 /** @name PCI: Base capability block registers.
371 * @{ */
372 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
373 /** @} */
374
375 /** @name MMIO: Control and status registers.
376 * @{ */
377 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
378 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
379 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
380 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
381 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
382 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
383 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
384 /** @} */
385
386 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
387 * @{ */
388 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
389 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
390 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
391 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
392 /** @} */
393
394 /** @todo IOMMU: SMI filter. */
395
396 /** @name MMIO: Guest Virtual-APIC Log registers.
397 * @{ */
398 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
399 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
400 /** @} */
401
402 /** @name MMIO: Alternate PPR and Event Log registers.
403 * @{ */
404 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
405 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
406 /** @} */
407
408 /** @name MMIO: Device-specific feature registers.
409 * @{ */
410 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
411 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
412 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
413 /** @} */
414
415 /** @name MMIO: MSI Capability Block registers.
416 * @{ */
417 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
418 /** @} */
419
420 /** @name MMIO: Performance Optimization Control registers.
421 * @{ */
422 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
423 /** @} */
424
425 /** @name MMIO: x2APIC Control registers.
426 * @{ */
427 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
428 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
429 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
430 /** @} */
431
432 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
433 * @{ */
434 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
435 /** @} */
436
437 /** @name MMIO: Reserved register.
438 * @{ */
439 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
440 /** @} */
441
442 /** @name MMIO: Command and Event Log pointer registers.
443 * @{ */
444 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
445 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
446 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
447 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
448 /** @} */
449
450 /** @name MMIO: Command and Event Status register.
451 * @{ */
452 IOMMU_STATUS_T Status; /**< IOMMU status register. */
453 /** @} */
454
455 /** @name MMIO: PPR Log Head and Tail pointer registers.
456 * @{ */
457 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
458 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
459 /** @} */
460
461 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
462 * @{ */
463 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
464 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
465 /** @} */
466
467 /** @name MMIO: PPR Log B Head and Tail pointer registers.
468 * @{ */
469 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
470 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
471 /** @} */
472
473 /** @name MMIO: Event Log B Head and Tail pointer registers.
474 * @{ */
475 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
476 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
477 /** @} */
478
479 /** @name MMIO: PPR Log Overflow protection registers.
480 * @{ */
481 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
482 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
483 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
484 /** @} */
485
486 /** @todo IOMMU: IOMMU Event counter registers. */
487
488#ifdef VBOX_WITH_STATISTICS
489 /** @name IOMMU: Stat counters.
490 * @{ */
491 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
492 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
493 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
494 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
495
496 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
497 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
498
499 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
500 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
501 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
502 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
503
504 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
505 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
506 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
507 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
508
509 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
510 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
511 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
512 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
513 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
514 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
515 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
516 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
517 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
518
519 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
520 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
521
522 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
523 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
524
525 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
526 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
527
528 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
529 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
530 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
531 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
532 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
533 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
534 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
535
536 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
537 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
538 /** @} */
539#endif
540} IOMMU;
541/** Pointer to the IOMMU device state. */
542typedef IOMMU *PIOMMU;
543/** Pointer to the const IOMMU device state. */
544typedef const IOMMU *PCIOMMU;
545AssertCompileMemberAlignment(IOMMU, hMmio, 8);
546#ifdef IOMMU_WITH_DTE_CACHE
547AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
548AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
549AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
550#endif
551#ifdef IOMMU_WITH_IRTE_CACHE
552AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
553#endif
554AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
555AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
556AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
557AssertCompileMemberAlignment(IOMMU, Status, 8);
558
559/**
560 * The ring-3 IOMMU device state.
561 */
562typedef struct IOMMUR3
563{
564 /** Device instance. */
565 PPDMDEVINSR3 pDevInsR3;
566 /** The IOMMU helpers. */
567 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
568 /** The command thread handle. */
569 R3PTRTYPE(PPDMTHREAD) pCmdThread;
570#ifdef IOMMU_WITH_IOTLBE_CACHE
571 /** Pointer to array of pre-allocated IOTLBEs. */
572 PIOTLBE paIotlbes;
573 /** Maps [DomainId,Iova] to [IOTLBE]. */
574 AVLU64TREE TreeIotlbe;
575 /** LRU list anchor for IOTLB entries. */
576 RTLISTANCHOR LstLruIotlbe;
577 /** Index of the next unused IOTLB. */
578 uint32_t idxUnusedIotlbe;
579 /** Number of cached IOTLB entries in the tree. */
580 uint32_t cCachedIotlbes;
581#endif
582} IOMMUR3;
583/** Pointer to the ring-3 IOMMU device state. */
584typedef IOMMUR3 *PIOMMUR3;
585/** Pointer to the const ring-3 IOMMU device state. */
586typedef const IOMMUR3 *PCIOMMUR3;
587#ifdef IOMMU_WITH_IOTLBE_CACHE
588AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
589AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
590AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
591#endif
592
593/**
594 * The ring-0 IOMMU device state.
595 */
596typedef struct IOMMUR0
597{
598 /** Device instance. */
599 PPDMDEVINSR0 pDevInsR0;
600 /** The IOMMU helpers. */
601 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
602} IOMMUR0;
603/** Pointer to the ring-0 IOMMU device state. */
604typedef IOMMUR0 *PIOMMUR0;
605
606/**
607 * The raw-mode IOMMU device state.
608 */
609typedef struct IOMMURC
610{
611 /** Device instance. */
612 PPDMDEVINSRC pDevInsRC;
613 /** The IOMMU helpers. */
614 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
615} IOMMURC;
616/** Pointer to the raw-mode IOMMU device state. */
617typedef IOMMURC *PIOMMURC;
618
619/** The IOMMU device state for the current context. */
620typedef CTX_SUFF(IOMMU) IOMMUCC;
621/** Pointer to the IOMMU device state for the current context. */
622typedef CTX_SUFF(PIOMMU) PIOMMUCC;
623
624/**
625 * IOMMU register access.
626 */
627typedef struct IOMMUREGACC
628{
629 const char *pszName;
630 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
631 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
632} IOMMUREGACC;
633/** Pointer to an IOMMU register access. */
634typedef IOMMUREGACC *PIOMMUREGACC;
635/** Pointer to a const IOMMU register access. */
636typedef IOMMUREGACC const *PCIOMMUREGACC;
637
638#ifdef IOMMU_WITH_IOTLBE_CACHE
639/**
640 * IOTLBE flush argument.
641 */
642typedef struct IOTLBEFLUSHARG
643{
644 /** The ring-3 IOMMU device state. */
645 PIOMMUR3 pIommuR3;
646 /** The domain ID to flush. */
647 uint16_t idDomain;
648} IOTLBEFLUSHARG;
649/** Pointer to an IOTLBE flush argument. */
650typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
651/** Pointer to a const IOTLBE flush argument. */
652typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
653
654/**
655 * IOTLBE Info. argument.
656 */
657typedef struct IOTLBEINFOARG
658{
659 /** The ring-3 IOMMU device state. */
660 PIOMMUR3 pIommuR3;
661 /** The info helper. */
662 PCDBGFINFOHLP pHlp;
663 /** The domain ID to dump IOTLB entry. */
664 uint16_t idDomain;
665} IOTLBEINFOARG;
666/** Pointer to an IOTLBE flush argument. */
667typedef IOTLBEINFOARG *PIOTLBEINFOARG;
668/** Pointer to a const IOTLBE flush argument. */
669typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
670#endif
671
672/**
673 * IOMMU operation auxiliary info.
674 */
675typedef struct IOMMUOPAUX
676{
677 /** The IOMMU operation being performed. */
678 IOMMUOP enmOp;
679 /** The device table entry (can be NULL). */
680 PCDTE_T pDte;
681 /** The device ID (bus, device, function). */
682 uint16_t idDevice;
683 /** The domain ID (when the DTE isn't provided). */
684 uint16_t idDomain;
685} IOMMUOPAUX;
686/** Pointer to an I/O address lookup struct. */
687typedef IOMMUOPAUX *PIOMMUOPAUX;
688/** Pointer to a const I/O address lookup struct. */
689typedef IOMMUOPAUX const *PCIOMMUOPAUX;
690
691typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
692 PIOPAGELOOKUP pPageLookup));
693typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
694
695
696/*********************************************************************************************************************************
697* Global Variables *
698*********************************************************************************************************************************/
699/**
700 * An array of the number of device table segments supported.
701 * Indexed by u2DevTabSegSup.
702 */
703static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
704
705/**
706 * An array of the masks to select the device table segment index from a device ID.
707 */
708static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
709
710/**
711 * An array of the shift values to select the device table segment index from a
712 * device ID.
713 */
714static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
715
716/**
717 * The maximum size (inclusive) of each device table segment (0 to 7).
718 * Indexed by the device table segment index.
719 */
720static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
721
722/**
723 * The IOMMU I/O permission names.
724 */
725static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
726
727
728#ifndef VBOX_DEVICE_STRUCT_TESTCASE
729/**
730 * Gets the maximum number of buffer entries for the given buffer length.
731 *
732 * @returns Number of buffer entries.
733 * @param uEncodedLen The length (power-of-2 encoded).
734 */
735DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
736{
737 Assert(uEncodedLen > 7);
738 Assert(uEncodedLen < 16);
739 return 2 << (uEncodedLen - 1);
740}
741
742
743/**
744 * Gets the total length of the buffer given a base register's encoded length.
745 *
746 * @returns The length of the buffer in bytes.
747 * @param uEncodedLen The length (power-of-2 encoded).
748 */
749DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
750{
751 Assert(uEncodedLen > 7);
752 Assert(uEncodedLen < 16);
753 return (2 << (uEncodedLen - 1)) << 4;
754}
755
756
757/**
758 * Gets the number of (unconsumed) entries in the event log.
759 *
760 * @returns The number of entries in the event log.
761 * @param pThis The shared IOMMU device state.
762 */
763static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
764{
765 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
766 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
767 if (idxTail >= idxHead)
768 return idxTail - idxHead;
769
770 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
771 return cMaxEvts - idxHead + idxTail;
772}
773
774
775/**
776 * Gets the descriptive I/O permission name for a memory access.
777 *
778 * @returns The I/O permission name.
779 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
780 */
781static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
782{
783 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
784 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
785 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
786}
787
788
789/**
790 * Checks whether two consecutive I/O page lookup results translates to a physically
791 * contiguous region.
792 *
793 * @returns @c true if they are contiguous, @c false otherwise.
794 * @param pPageLookupPrev The I/O page lookup result of the previous page.
795 * @param pPageLookup The I/O page lookup result of the current page.
796 */
797static bool iommuAmdLookupIsAccessContig(PCIOPAGELOOKUP pPageLookupPrev, PCIOPAGELOOKUP pPageLookup)
798{
799 Assert(pPageLookupPrev->fPerm == pPageLookup->fPerm);
800 size_t const cbPrev = RT_BIT_64(pPageLookupPrev->cShift);
801 RTGCPHYS const GCPhysPrev = pPageLookupPrev->GCPhysSpa;
802 RTGCPHYS const GCPhys = pPageLookup->GCPhysSpa;
803 uint64_t const offMaskPrev = IOMMU_GET_PAGE_OFF_MASK(pPageLookupPrev->cShift);
804 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(pPageLookup->cShift);
805
806 /* Paranoia: Ensure offset bits are 0. */
807 Assert(!(GCPhysPrev & offMaskPrev));
808 Assert(!(GCPhys & offMask));
809
810 if ((GCPhysPrev & ~offMaskPrev) + cbPrev == (GCPhys & ~offMask))
811 return true;
812 return false;
813}
814
815
816/**
817 * Gets the basic I/O device flags for the given device table entry.
818 *
819 * @returns The basic I/O device flags.
820 * @param pDte The device table entry.
821 */
822static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
823{
824 /* Extract basic flags from bits 127:0 of the DTE. */
825 uint16_t fFlags = 0;
826 if (pDte->n.u1Valid)
827 {
828 fFlags |= IOMMU_DTE_CACHE_F_VALID;
829
830 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
831 if (pDte->n.u1SuppressAllPfEvents)
832 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
833 if (pDte->n.u1SuppressPfEvents)
834 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
835
836 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
837 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
838 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
839 }
840
841 /* Extract basic flags from bits 255:128 of the DTE. */
842 if (pDte->n.u1IntrMapValid)
843 {
844 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
845
846 /** @todo Skip the if check here (shift/mask the relevant bit over). */
847 if (pDte->n.u1IgnoreUnmappedIntrs)
848 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
849
850 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
851 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
852 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
853 }
854 return fFlags;
855}
856
857
858/**
859 * Remaps the source MSI to the destination MSI given the IRTE.
860 *
861 * @param pMsiIn The source MSI.
862 * @param pMsiOut Where to store the remapped MSI.
863 * @param pIrte The IRTE used for the remapping.
864 */
865static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
866{
867 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
868 *pMsiOut = *pMsiIn;
869
870 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
871 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
872
873 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
874 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
875}
876
877
878#ifdef IOMMU_WITH_DTE_CACHE
879/**
880 * Looks up an entry in the DTE cache for the given device ID.
881 *
882 * @returns The index of the entry, or the cache capacity if no entry was found.
883 * @param pThis The shared IOMMU device state.
884 * @param idDevice The device ID (bus, device, function).
885 */
886DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
887{
888 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
889 for (uint16_t i = 0; i < cDeviceIds; i++)
890 {
891 if (pThis->aDeviceIds[i] == idDevice)
892 return i;
893 }
894 return cDeviceIds;
895}
896
897
898/**
899 * Gets an free/unused DTE cache entry.
900 *
901 * @returns The index of an unused entry, or cache capacity if the cache is full.
902 * @param pThis The shared IOMMU device state.
903 */
904DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
905{
906 /*
907 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
908 * (the latter being an ugly hack) and cannot be a valid device ID.
909 */
910 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
911 for (uint16_t i = 0; i < cDeviceIds; i++)
912 {
913 if (!pThis->aDeviceIds[i])
914 return i;
915 }
916 return cDeviceIds;
917}
918
919
920/**
921 * Adds or updates the I/O device flags for the given device ID.
922 *
923 * @returns VBox status code.
924 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
925 *
926 * @param pDevIns The IOMMU instance data.
927 * @param idDevice The device ID (bus, device, function).
928 * @param pDte The device table entry.
929 * @param fOrMask The device flags (usually compound flags) to OR in with the
930 * basic flags, see IOMMU_DTE_CACHE_F_XXX.
931 */
932static int iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, uint16_t fOrMask)
933{
934 Assert(pDte);
935 Assert(idDevice);
936
937 int rc = VINF_SUCCESS;
938 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask;
939 uint16_t const idDomain = pDte->n.u16DomainId;
940
941 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
942 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
943
944 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
945 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
946 if (idxDte < cDteCache)
947 {
948 pThis->aDteCache[idxDte].fFlags = fFlags;
949 pThis->aDteCache[idxDte].idDomain = idDomain;
950 }
951 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
952 {
953 pThis->aDeviceIds[idxDte] = idDevice;
954 pThis->aDteCache[idxDte].fFlags = fFlags;
955 pThis->aDteCache[idxDte].idDomain = idDomain;
956 }
957 else
958 rc = VERR_OUT_OF_RESOURCES;
959
960 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
961 return rc;
962}
963
964
965/**
966 * Adds one or more I/O device flags if the device is already present in the cache.
967 *
968 * @param pDevIns The IOMMU instance data.
969 * @param idDevice The device ID (bus, device, function).
970 * @param fFlags Additional device flags to OR with existing flags, see
971 * IOMMU_DTE_CACHE_F_XXX.
972 */
973static void iommuAmdDteCacheAddFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fFlags)
974{
975 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
976 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
977
978 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
979 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
980 if ( idxDte < cDteCache
981 && (pThis->aDteCache[idxDte].fFlags & IOMMU_DTE_CACHE_F_PRESENT))
982 pThis->aDteCache[idxDte].fFlags |= fFlags;
983
984 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
985}
986
987
988/**
989 * Removes a DTE cache entry.
990 *
991 * @param pDevIns The IOMMU instance data.
992 * @param idDevice The device ID to remove cache entries for.
993 */
994static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
995{
996 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
997 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
998
999 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1000 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1001 if (idxDte < cDteCache)
1002 {
1003 pThis->aDteCache[idxDte].fFlags = 0;
1004 pThis->aDteCache[idxDte].idDomain = 0;
1005 }
1006
1007 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1008}
1009
1010
1011/**
1012 * Removes all entries in the device table entry cache.
1013 *
1014 * @param pDevIns The IOMMU instance data.
1015 */
1016static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1017{
1018 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1019 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1020 RT_ZERO(pThis->aDeviceIds);
1021 RT_ZERO(pThis->aDteCache);
1022 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1023}
1024#endif /* IOMMU_WITH_DTE_CACHE */
1025
1026
1027#ifdef IOMMU_WITH_IOTLBE_CACHE
1028/**
1029 * Moves the IOTLB entry to the least recently used slot.
1030 *
1031 * @param pThisR3 The ring-3 IOMMU device state.
1032 * @param pIotlbe The IOTLB entry to move.
1033 */
1034DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1035{
1036 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1037 {
1038 RTListNodeRemove(&pIotlbe->NdLru);
1039 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1040 }
1041}
1042
1043
1044/**
1045 * Moves the IOTLB entry to the most recently used slot.
1046 *
1047 * @param pThisR3 The ring-3 IOMMU device state.
1048 * @param pIotlbe The IOTLB entry to move.
1049 */
1050DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1051{
1052 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1053 {
1054 RTListNodeRemove(&pIotlbe->NdLru);
1055 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1056 }
1057}
1058
1059
1060# ifdef IN_RING3
1061/**
1062 * Dumps the IOTLB entry via the debug info helper.
1063 *
1064 * @returns VINF_SUCCESS.
1065 * @param pNode Pointer to an IOTLB entry to dump info.
1066 * @param pvUser Pointer to an IOTLBEINFOARG.
1067 */
1068static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1069{
1070 /* Validate. */
1071 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1072 AssertPtr(pArgs);
1073 AssertPtr(pArgs->pIommuR3);
1074 AssertPtr(pArgs->pHlp);
1075 //Assert(pArgs->pIommuCC->u32Magic == IOMMU_MAGIC);
1076
1077 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1078 if (idDomain == pArgs->idDomain)
1079 {
1080 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1081 AVLU64KEY const uKey = pIotlbe->Core.Key;
1082 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1083 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1084 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1085 size_t const cbPage = RT_BIT_64(cShift);
1086 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1087 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1088 bool const fEvictPending = pIotlbe->fEvictPending;
1089
1090 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1091 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1092 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1093 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1094 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1095 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1096 }
1097
1098 return VINF_SUCCESS;
1099}
1100# endif /* IN_RING3 */
1101
1102
1103/**
1104 * Removes the IOTLB entry if it's associated with the specified domain ID.
1105 *
1106 * @returns VINF_SUCCESS.
1107 * @param pNode Pointer to an IOTLBE.
1108 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1109 */
1110static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1111{
1112 /* Validate. */
1113 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1114 AssertPtr(pArgs);
1115 AssertPtr(pArgs->pIommuR3);
1116 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1117
1118 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1119 if (idDomain == pArgs->idDomain)
1120 {
1121 /* Mark this entry is as invalidated and needs to be evicted later. */
1122 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1123 pIotlbe->fEvictPending = true;
1124 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1125 }
1126 return VINF_SUCCESS;
1127}
1128
1129
1130/**
1131 * Inserts an IOTLB entry into the cache.
1132 *
1133 * @param pThis The shared IOMMU device state.
1134 * @param pThisR3 The ring-3 IOMMU device state.
1135 * @param pIotlbe The IOTLB entry to initialize and insert.
1136 * @param idDomain The domain ID.
1137 * @param uIova The I/O virtual address.
1138 * @param pPageLookup The I/O page lookup result of the access.
1139 */
1140static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1141 PCIOPAGELOOKUP pPageLookup)
1142{
1143 /* Initialize the IOTLB entry with results of the I/O page walk. */
1144 pIotlbe->Core.Key = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1145 pIotlbe->PageLookup = *pPageLookup;
1146
1147 /* Validate. */
1148 Assert(pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL);
1149 Assert(!pIotlbe->fEvictPending);
1150
1151 /* Check if the entry already exists. */
1152 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, pIotlbe->Core.Key);
1153 if (!pFound)
1154 {
1155 /* Insert the entry into the cache. */
1156 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1157 Assert(fInserted); NOREF(fInserted);
1158 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1159 ++pThisR3->cCachedIotlbes;
1160 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1161 }
1162 else
1163 {
1164 /* Update the existing entry. */
1165 if (pFound->fEvictPending)
1166 {
1167 pFound->fEvictPending = false;
1168 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1169 }
1170 Assert(pFound->PageLookup.cShift == pPageLookup->cShift);
1171 pFound->PageLookup.fPerm = pPageLookup->fPerm;
1172 pFound->PageLookup.GCPhysSpa = pPageLookup->GCPhysSpa;
1173 }
1174}
1175
1176
1177/**
1178 * Removes an IOTLB entry from the cache for the given key.
1179 *
1180 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1181 * the tree.
1182 * @param pThis The shared IOMMU device state.
1183 * @param pThisR3 The ring-3 IOMMU device state.
1184 * @param uKey The key of the IOTLB entry to remove.
1185 */
1186static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1187{
1188 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1189 if (pIotlbe)
1190 {
1191 if (pIotlbe->fEvictPending)
1192 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1193
1194 RT_ZERO(pIotlbe->Core);
1195 RT_ZERO(pIotlbe->PageLookup);
1196 /* We must not erase the LRU node connections here! */
1197 pIotlbe->fEvictPending = false;
1198 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1199
1200 Assert(pThisR3->cCachedIotlbes > 0);
1201 --pThisR3->cCachedIotlbes;
1202 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1203 }
1204 return pIotlbe;
1205}
1206
1207
1208/**
1209 * Looks up an IOTLB from the cache.
1210 *
1211 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1212 * @param pThis The shared IOMMU device state.
1213 * @param pThisR3 The ring-3 IOMMU device state.
1214 * @param idDomain The domain ID.
1215 * @param uIova The I/O virtual address.
1216 */
1217static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1218{
1219 RT_NOREF(pThis);
1220
1221 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1222 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1223 if ( pIotlbe
1224 && !pIotlbe->fEvictPending)
1225 return pIotlbe;
1226
1227 /*
1228 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1229 * them from the cache immediately. We found an entry pending eviction, just return that
1230 * nothing was found (rather than evicting now).
1231 */
1232 return NULL;
1233}
1234
1235
1236/**
1237 * Adds an IOTLB entry to the cache.
1238 *
1239 * @param pThis The shared IOMMU device state.
1240 * @param pThisR3 The ring-3 IOMMU device state.
1241 * @param idDomain The domain ID.
1242 * @param uIova The I/O virtual address.
1243 * @param pPageLookup The I/O page lookup result of the access.
1244 */
1245static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIova, PCIOPAGELOOKUP pPageLookup)
1246{
1247 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1248 Assert(pPageLookup);
1249 Assert(pPageLookup->cShift <= 31);
1250 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1251
1252 /*
1253 * If there are no unused IOTLB entries, evict the LRU entry.
1254 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1255 */
1256 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1257 {
1258 /* Grab the least recently used entry. */
1259 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1260 Assert(pIotlbe);
1261
1262 /* If the entry is in the cache, remove it. */
1263 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1264 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1265
1266 /* Initialize and insert the IOTLB entry into the cache. */
1267 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1268
1269 /* Move the entry to the most recently used slot. */
1270 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1271 }
1272 else
1273 {
1274 /* Grab an unused IOTLB entry from the pre-allocated list. */
1275 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1276 ++pThisR3->idxUnusedIotlbe;
1277
1278 /* Initialize and insert the IOTLB entry into the cache. */
1279 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1280
1281 /* Add the entry to the most recently used slot. */
1282 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1283 }
1284}
1285
1286
1287/**
1288 * Removes all IOTLB entries from the cache.
1289 *
1290 * @param pDevIns The IOMMU instance data.
1291 */
1292static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1293{
1294 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1295 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1296 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1297
1298 if (pThisR3->cCachedIotlbes > 0)
1299 {
1300 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
1301 RT_BZERO(pThisR3->paIotlbes, cbIotlbes);
1302 pThisR3->idxUnusedIotlbe = 0;
1303 pThisR3->cCachedIotlbes = 0;
1304 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1305 RTListInit(&pThisR3->LstLruIotlbe);
1306 }
1307
1308 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1309}
1310
1311
1312/**
1313 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1314 * domain ID from the cache.
1315 *
1316 * @param pDevIns The IOMMU instance data.
1317 * @param idDomain The domain ID.
1318 * @param uIova The I/O virtual address to invalidate.
1319 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1320 */
1321static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1322{
1323 /* Validate. */
1324 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1325 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1326 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1327
1328 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1329 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1330 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1331
1332 do
1333 {
1334 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1335 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1336 if (pIotlbe)
1337 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1338 uIova += X86_PAGE_4K_SIZE;
1339 cbInvalidate -= X86_PAGE_4K_SIZE;
1340 } while (cbInvalidate > 0);
1341
1342 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1343}
1344
1345
1346/**
1347 * Removes all IOTLB entries for the specified domain ID.
1348 *
1349 * @param pDevIns The IOMMU instance data.
1350 * @param idDomain The domain ID.
1351 */
1352static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1353{
1354 /*
1355 * We need to iterate the tree and search based on the domain ID.
1356 * But it seems we cannot remove items while iterating the tree.
1357 * Thus, we simply mark entries for eviction later but move them to the LRU
1358 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1359 */
1360 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1361 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1362 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1363
1364 IOTLBEFLUSHARG Args;
1365 Args.pIommuR3 = pThisR3;
1366 Args.idDomain = idDomain;
1367 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1368
1369 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1370}
1371
1372
1373/**
1374 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1375 *
1376 * @param pDevIns The IOMMU instance data.
1377 * @param idDomain The domain ID.
1378 * @param uIova The I/O virtual address.
1379 * @param cbIova The size of the access (must be 4K aligned).
1380 * @param GCPhysSpa The translated system-physical address.
1381 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
1382 */
1383static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbIova, RTGCPHYS GCPhysSpa,
1384 uint8_t fPerm)
1385{
1386 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1387 Assert(!(GCPhysSpa & X86_PAGE_4K_OFFSET_MASK));
1388 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1389 Assert(cbIova >= X86_PAGE_4K_SIZE);
1390
1391 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1392 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1393
1394 /* Add IOTLB entries for every page in the access. */
1395 IOPAGELOOKUP PageLookup;
1396 RT_ZERO(PageLookup);
1397 PageLookup.cShift = X86_PAGE_4K_SHIFT;
1398 PageLookup.fPerm = fPerm;
1399 PageLookup.GCPhysSpa = GCPhysSpa;
1400
1401 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1402 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1403
1404 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1405 /** @todo Re-check DTE cache? */
1406 do
1407 {
1408 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIova, &PageLookup);
1409 uIova += X86_PAGE_4K_SIZE;
1410 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1411 --cPages;
1412 } while (cPages > 0);
1413 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1414}
1415#endif /* IOMMU_WITH_IOTLBE_CACHE */
1416
1417
1418#ifdef IOMMU_WITH_IRTE_CACHE
1419/**
1420 * Looks up an IRTE cache entry.
1421 *
1422 * @returns Index of the found entry, or cache capacity if not found.
1423 * @param pThis The shared IOMMU device state.
1424 * @param idDevice The device ID (bus, device, function).
1425 * @param offIrte The offset into the interrupt remap table.
1426 */
1427static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1428{
1429 /** @todo Consider sorting and binary search when the cache capacity grows.
1430 * For the IRTE cache this should be okay since typically guests do not alter the
1431 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1432 * often. */
1433 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1434 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1435 for (uint16_t i = 0; i < cIrteCache; i++)
1436 if (pThis->aIrteCache[i].uKey == uKey)
1437 return i;
1438 return cIrteCache;
1439}
1440
1441
1442/**
1443 * Gets a free/unused IRTE cache entry.
1444 *
1445 * @returns The index of an unused entry, or cache capacity if the cache is full.
1446 * @param pThis The shared IOMMU device state.
1447 */
1448static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1449{
1450 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1451 for (uint16_t i = 0; i < cIrteCache; i++)
1452 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1453 {
1454 Assert(!pThis->aIrteCache[i].Irte.u32);
1455 return i;
1456 }
1457 return cIrteCache;
1458}
1459
1460
1461/**
1462 * Looks up the IRTE cache for the given MSI.
1463 *
1464 * @returns VBox status code.
1465 * @param pDevIns The IOMMU instance data.
1466 * @param idDevice The device ID (bus, device, function).
1467 * @param enmOp The IOMMU operation being performed.
1468 * @param pMsiIn The source MSI.
1469 * @param pMsiOut Where to store the remapped MSI.
1470 */
1471static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1472{
1473 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1474
1475 int rc = VERR_NOT_FOUND;
1476 /* Deal with such cases in the slower/fallback path. */
1477 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1478 { /* likely */ }
1479 else
1480 return rc;
1481
1482 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1483 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1484
1485 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1486 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1487 {
1488 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1489 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1490 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1491 {
1492 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1493
1494 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1495 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1496 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1497 {
1498 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1499 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1500 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1501 {
1502 /* Interrupt table length has been verified prior to adding entries to the cache. */
1503 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1504 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1505 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1506 {
1507 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1508 Assert(pIrte->n.u1RemapEnable);
1509 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1510 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1511 rc = VINF_SUCCESS;
1512 }
1513 }
1514 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1515 {
1516 *pMsiOut = *pMsiIn;
1517 rc = VINF_SUCCESS;
1518 }
1519 }
1520 }
1521 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1522 {
1523 *pMsiOut = *pMsiIn;
1524 rc = VINF_SUCCESS;
1525 }
1526 }
1527
1528 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1529 return rc;
1530}
1531
1532
1533/**
1534 * Adds or updates the IRTE cache for the given IRTE.
1535 *
1536 * @returns VBox status code.
1537 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1538 *
1539 * @param pDevIns The IOMMU instance data.
1540 * @param idDevice The device ID (bus, device, function).
1541 * @param offIrte The offset into the interrupt remap table.
1542 * @param pIrte The IRTE to cache.
1543 */
1544static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1545{
1546 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1547
1548 int rc = VINF_SUCCESS;
1549 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1550 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1551
1552 /* Find an existing entry or get an unused slot. */
1553 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1554 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1555 if ( idxIrteCache < cIrteCache
1556 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1557 {
1558 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1559 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1560 }
1561 else
1562 rc = VERR_OUT_OF_RESOURCES;
1563
1564 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1565 return rc;
1566}
1567
1568
1569/**
1570 * Removes IRTE cache entries for the given device ID.
1571 *
1572 * @param pDevIns The IOMMU instance data.
1573 * @param idDevice The device ID (bus, device, function).
1574 */
1575static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1576{
1577 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1578 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1579 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1580 for (uint16_t i = 0; i < cIrteCache; i++)
1581 {
1582 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1583 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1584 {
1585 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1586 pIrteCache->Irte.u32 = 0;
1587 /* There could multiple IRTE entries for a device ID, continue searching. */
1588 }
1589 }
1590 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1591}
1592
1593
1594/**
1595 * Removes all IRTE cache entries.
1596 *
1597 * @param pDevIns The IOMMU instance data.
1598 */
1599static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1600{
1601 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1602 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1603 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1604 for (uint16_t i = 0; i < cIrteCache; i++)
1605 {
1606 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1607 pThis->aIrteCache[i].Irte.u32 = 0;
1608 }
1609 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1610}
1611#endif /* IOMMU_WITH_IRTE_CACHE */
1612
1613
1614/**
1615 * Atomically reads the control register without locking the IOMMU device.
1616 *
1617 * @returns The control register.
1618 * @param pThis The shared IOMMU device state.
1619 */
1620DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1621{
1622 IOMMU_CTRL_T Ctrl;
1623 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1624 return Ctrl;
1625}
1626
1627
1628/**
1629 * Returns whether MSI is enabled for the IOMMU.
1630 *
1631 * @returns Whether MSI is enabled.
1632 * @param pDevIns The IOMMU device instance.
1633 *
1634 * @note There should be a PCIDevXxx function for this.
1635 */
1636static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1637{
1638 MSI_CAP_HDR_T MsiCapHdr;
1639 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1640 return MsiCapHdr.n.u1MsiEnable;
1641}
1642
1643
1644/**
1645 * Signals a PCI target abort.
1646 *
1647 * @param pDevIns The IOMMU device instance.
1648 */
1649static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1650{
1651 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1652 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1653 PDMPciDevSetStatus(pPciDev, u16Status);
1654}
1655
1656
1657/**
1658 * Wakes up the command thread if there are commands to be processed.
1659 *
1660 * @param pDevIns The IOMMU device instance.
1661 *
1662 * @remarks The IOMMU lock must be held while calling this!
1663 */
1664static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1665{
1666 Log4Func(("\n"));
1667
1668 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1669 if ( pThis->Status.n.u1CmdBufRunning
1670 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1671 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1672 {
1673 Log4Func(("Signaling command thread\n"));
1674 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1675 }
1676}
1677
1678
1679/**
1680 * Reads the Device Table Base Address Register.
1681 */
1682static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1683{
1684 RT_NOREF(pDevIns, offReg);
1685 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1686 return VINF_SUCCESS;
1687}
1688
1689
1690/**
1691 * Reads the Command Buffer Base Address Register.
1692 */
1693static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1694{
1695 RT_NOREF(pDevIns, offReg);
1696 *pu64Value = pThis->CmdBufBaseAddr.u64;
1697 return VINF_SUCCESS;
1698}
1699
1700
1701/**
1702 * Reads the Event Log Base Address Register.
1703 */
1704static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1705{
1706 RT_NOREF(pDevIns, offReg);
1707 *pu64Value = pThis->EvtLogBaseAddr.u64;
1708 return VINF_SUCCESS;
1709}
1710
1711
1712/**
1713 * Reads the Control Register.
1714 */
1715static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1716{
1717 RT_NOREF(pDevIns, offReg);
1718 *pu64Value = pThis->Ctrl.u64;
1719 return VINF_SUCCESS;
1720}
1721
1722
1723/**
1724 * Reads the Exclusion Range Base Address Register.
1725 */
1726static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1727{
1728 RT_NOREF(pDevIns, offReg);
1729 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1730 return VINF_SUCCESS;
1731}
1732
1733
1734/**
1735 * Reads to the Exclusion Range Limit Register.
1736 */
1737static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1738{
1739 RT_NOREF(pDevIns, offReg);
1740 *pu64Value = pThis->ExclRangeLimit.u64;
1741 return VINF_SUCCESS;
1742}
1743
1744
1745/**
1746 * Reads to the Extended Feature Register.
1747 */
1748static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1749{
1750 RT_NOREF(pDevIns, offReg);
1751 *pu64Value = pThis->ExtFeat.u64;
1752 return VINF_SUCCESS;
1753}
1754
1755
1756/**
1757 * Reads to the PPR Log Base Address Register.
1758 */
1759static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1760{
1761 RT_NOREF(pDevIns, offReg);
1762 *pu64Value = pThis->PprLogBaseAddr.u64;
1763 return VINF_SUCCESS;
1764}
1765
1766
1767/**
1768 * Writes the Hardware Event Register (Hi).
1769 */
1770static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1771{
1772 RT_NOREF(pDevIns, offReg);
1773 *pu64Value = pThis->HwEvtHi.u64;
1774 return VINF_SUCCESS;
1775}
1776
1777
1778/**
1779 * Reads the Hardware Event Register (Lo).
1780 */
1781static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1782{
1783 RT_NOREF(pDevIns, offReg);
1784 *pu64Value = pThis->HwEvtLo;
1785 return VINF_SUCCESS;
1786}
1787
1788
1789/**
1790 * Reads the Hardware Event Status Register.
1791 */
1792static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1793{
1794 RT_NOREF(pDevIns, offReg);
1795 *pu64Value = pThis->HwEvtStatus.u64;
1796 return VINF_SUCCESS;
1797}
1798
1799
1800/**
1801 * Reads to the GA Log Base Address Register.
1802 */
1803static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1804{
1805 RT_NOREF(pDevIns, offReg);
1806 *pu64Value = pThis->GALogBaseAddr.u64;
1807 return VINF_SUCCESS;
1808}
1809
1810
1811/**
1812 * Reads to the PPR Log B Base Address Register.
1813 */
1814static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1815{
1816 RT_NOREF(pDevIns, offReg);
1817 *pu64Value = pThis->PprLogBBaseAddr.u64;
1818 return VINF_SUCCESS;
1819}
1820
1821
1822/**
1823 * Reads to the Event Log B Base Address Register.
1824 */
1825static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1826{
1827 RT_NOREF(pDevIns, offReg);
1828 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1829 return VINF_SUCCESS;
1830}
1831
1832
1833/**
1834 * Reads the Device Table Segment Base Address Register.
1835 */
1836static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1837{
1838 RT_NOREF(pDevIns);
1839
1840 /* Figure out which segment is being written. */
1841 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1842 uint8_t const idxSegment = offSegment + 1;
1843 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1844
1845 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1846 return VINF_SUCCESS;
1847}
1848
1849
1850/**
1851 * Reads the Device Specific Feature Extension (DSFX) Register.
1852 */
1853static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1854{
1855 RT_NOREF(pDevIns, offReg);
1856 *pu64Value = pThis->DevSpecificFeat.u64;
1857 return VINF_SUCCESS;
1858}
1859
1860/**
1861 * Reads the Device Specific Control Extension (DSCX) Register.
1862 */
1863static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1864{
1865 RT_NOREF(pDevIns, offReg);
1866 *pu64Value = pThis->DevSpecificCtrl.u64;
1867 return VINF_SUCCESS;
1868}
1869
1870
1871/**
1872 * Reads the Device Specific Status Extension (DSSX) Register.
1873 */
1874static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1875{
1876 RT_NOREF(pDevIns, offReg);
1877 *pu64Value = pThis->DevSpecificStatus.u64;
1878 return VINF_SUCCESS;
1879}
1880
1881
1882/**
1883 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1884 */
1885static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1886{
1887 RT_NOREF(pDevIns, offReg);
1888 uint32_t const uLo = pThis->MiscInfo.au32[0];
1889 uint32_t const uHi = pThis->MiscInfo.au32[1];
1890 *pu64Value = RT_MAKE_U64(uLo, uHi);
1891 return VINF_SUCCESS;
1892}
1893
1894
1895/**
1896 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1897 * Register (32-bit).
1898 */
1899static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1900{
1901 RT_NOREF(pThis, offReg);
1902 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1903 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1904 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1905 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1906 *pu64Value = RT_MAKE_U64(uLo, uHi);
1907 return VINF_SUCCESS;
1908}
1909
1910
1911/**
1912 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1913 */
1914static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1915{
1916 RT_NOREF(pThis, offReg);
1917 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1918 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1919 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1920 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1921 *pu64Value = RT_MAKE_U64(uLo, uHi);
1922 return VINF_SUCCESS;
1923}
1924
1925
1926/**
1927 * Reads the Command Buffer Head Pointer Register.
1928 */
1929static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1930{
1931 RT_NOREF(pDevIns, offReg);
1932 *pu64Value = pThis->CmdBufHeadPtr.u64;
1933 return VINF_SUCCESS;
1934}
1935
1936
1937/**
1938 * Reads the Command Buffer Tail Pointer Register.
1939 */
1940static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1941{
1942 RT_NOREF(pDevIns, offReg);
1943 *pu64Value = pThis->CmdBufTailPtr.u64;
1944 return VINF_SUCCESS;
1945}
1946
1947
1948/**
1949 * Reads the Event Log Head Pointer Register.
1950 */
1951static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1952{
1953 RT_NOREF(pDevIns, offReg);
1954 *pu64Value = pThis->EvtLogHeadPtr.u64;
1955 return VINF_SUCCESS;
1956}
1957
1958
1959/**
1960 * Reads the Event Log Tail Pointer Register.
1961 */
1962static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1963{
1964 RT_NOREF(pDevIns, offReg);
1965 *pu64Value = pThis->EvtLogTailPtr.u64;
1966 return VINF_SUCCESS;
1967}
1968
1969
1970/**
1971 * Reads the Status Register.
1972 */
1973static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1974{
1975 RT_NOREF(pDevIns, offReg);
1976 *pu64Value = pThis->Status.u64;
1977 return VINF_SUCCESS;
1978}
1979
1980
1981/**
1982 * Writes the Device Table Base Address Register.
1983 */
1984static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1985{
1986 RT_NOREF(pDevIns, offReg);
1987
1988 /* Mask out all unrecognized bits. */
1989 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
1990
1991 /* Update the register. */
1992 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
1993
1994 /* Paranoia. */
1995 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
1996 return VINF_SUCCESS;
1997}
1998
1999
2000/**
2001 * Writes the Command Buffer Base Address Register.
2002 */
2003static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2004{
2005 RT_NOREF(pDevIns, offReg);
2006
2007 /*
2008 * While this is not explicitly specified like the event log base address register,
2009 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2010 * Inconsistent specs :/
2011 */
2012 if (pThis->Status.n.u1CmdBufRunning)
2013 {
2014 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2015 return VINF_SUCCESS;
2016 }
2017
2018 /* Mask out all unrecognized bits. */
2019 CMD_BUF_BAR_T CmdBufBaseAddr;
2020 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2021
2022 /* Validate the length. */
2023 if (CmdBufBaseAddr.n.u4Len >= 8)
2024 {
2025 /* Update the register. */
2026 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2027
2028 /*
2029 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2030 * See AMD IOMMU spec. 2.4 "Commands".
2031 */
2032 pThis->CmdBufHeadPtr.u64 = 0;
2033 pThis->CmdBufTailPtr.u64 = 0;
2034 }
2035 else
2036 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2037
2038 return VINF_SUCCESS;
2039}
2040
2041
2042/**
2043 * Writes the Event Log Base Address Register.
2044 */
2045static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2046{
2047 RT_NOREF(pDevIns, offReg);
2048
2049 /*
2050 * IOMMU behavior is undefined when software writes this register when event logging is running.
2051 * In our emulation, we ignore the write entirely.
2052 * See AMD IOMMU spec. "Event Log Base Address Register".
2053 */
2054 if (pThis->Status.n.u1EvtLogRunning)
2055 {
2056 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2057 return VINF_SUCCESS;
2058 }
2059
2060 /* Mask out all unrecognized bits. */
2061 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2062 EVT_LOG_BAR_T EvtLogBaseAddr;
2063 EvtLogBaseAddr.u64 = u64Value;
2064
2065 /* Validate the length. */
2066 if (EvtLogBaseAddr.n.u4Len >= 8)
2067 {
2068 /* Update the register. */
2069 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2070
2071 /*
2072 * Writing the event log base address, clears the event log head and tail pointers.
2073 * See AMD IOMMU spec. 2.5 "Event Logging".
2074 */
2075 pThis->EvtLogHeadPtr.u64 = 0;
2076 pThis->EvtLogTailPtr.u64 = 0;
2077 }
2078 else
2079 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2080
2081 return VINF_SUCCESS;
2082}
2083
2084
2085/**
2086 * Writes the Control Register.
2087 */
2088static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2089{
2090 RT_NOREF(pDevIns, offReg);
2091
2092 /* Mask out all unrecognized bits. */
2093 u64Value &= IOMMU_CTRL_VALID_MASK;
2094 IOMMU_CTRL_T NewCtrl;
2095 NewCtrl.u64 = u64Value;
2096
2097 /* Ensure the device table segments are within limits. */
2098 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2099 {
2100 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2101
2102 /* Update the register. */
2103 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2104
2105 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2106 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2107
2108 /* Enable or disable event logging when the bit transitions. */
2109 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2110 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2111 if ( fOldEvtLogEn != fNewEvtLogEn
2112 || fOldIommuEn != fNewIommuEn)
2113 {
2114 if ( fNewIommuEn
2115 && fNewEvtLogEn)
2116 {
2117 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2118 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2119 }
2120 else
2121 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2122 }
2123
2124 /* Enable or disable command buffer processing when the bit transitions. */
2125 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2126 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2127 if ( fOldCmdBufEn != fNewCmdBufEn
2128 || fOldIommuEn != fNewIommuEn)
2129 {
2130 if ( fNewCmdBufEn
2131 && fNewIommuEn)
2132 {
2133 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2134 LogFunc(("Command buffer enabled\n"));
2135
2136 /* Wake up the command thread to start processing commands if any. */
2137 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2138 }
2139 else
2140 {
2141 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2142 LogFunc(("Command buffer disabled\n"));
2143 }
2144 }
2145 }
2146 else
2147 {
2148 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2149 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2150 }
2151
2152 return VINF_SUCCESS;
2153}
2154
2155
2156/**
2157 * Writes to the Exclusion Range Base Address Register.
2158 */
2159static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2160{
2161 RT_NOREF(pDevIns, offReg);
2162 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2163 return VINF_SUCCESS;
2164}
2165
2166
2167/**
2168 * Writes to the Exclusion Range Limit Register.
2169 */
2170static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2171{
2172 RT_NOREF(pDevIns, offReg);
2173 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2174 u64Value |= UINT64_C(0xfff);
2175 pThis->ExclRangeLimit.u64 = u64Value;
2176 return VINF_SUCCESS;
2177}
2178
2179
2180/**
2181 * Writes the Hardware Event Register (Hi).
2182 */
2183static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2184{
2185 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2186 RT_NOREF(pDevIns, offReg);
2187 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2188 pThis->HwEvtHi.u64 = u64Value;
2189 return VINF_SUCCESS;
2190}
2191
2192
2193/**
2194 * Writes the Hardware Event Register (Lo).
2195 */
2196static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2197{
2198 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2199 RT_NOREF(pDevIns, offReg);
2200 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2201 pThis->HwEvtLo = u64Value;
2202 return VINF_SUCCESS;
2203}
2204
2205
2206/**
2207 * Writes the Hardware Event Status Register.
2208 */
2209static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2210{
2211 RT_NOREF(pDevIns, offReg);
2212
2213 /* Mask out all unrecognized bits. */
2214 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2215
2216 /*
2217 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2218 * If the current status bits or the bits being written are both 0, we've nothing to do.
2219 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2220 */
2221 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2222 if (!(HwStatus & RT_BIT(0)))
2223 return VINF_SUCCESS;
2224 if (u64Value & HwStatus & RT_BIT_64(0))
2225 HwStatus &= ~RT_BIT_64(0);
2226 if (u64Value & HwStatus & RT_BIT_64(1))
2227 HwStatus &= ~RT_BIT_64(1);
2228
2229 /* Update the register. */
2230 pThis->HwEvtStatus.u64 = HwStatus;
2231 return VINF_SUCCESS;
2232}
2233
2234
2235/**
2236 * Writes the Device Table Segment Base Address Register.
2237 */
2238static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2239{
2240 RT_NOREF(pDevIns);
2241
2242 /* Figure out which segment is being written. */
2243 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2244 uint8_t const idxSegment = offSegment + 1;
2245 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2246
2247 /* Mask out all unrecognized bits. */
2248 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2249 DEV_TAB_BAR_T DevTabSegBar;
2250 DevTabSegBar.u64 = u64Value;
2251
2252 /* Validate the size. */
2253 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2254 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2255 if (uSegSize <= uMaxSegSize)
2256 {
2257 /* Update the register. */
2258 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2259 }
2260 else
2261 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2262
2263 return VINF_SUCCESS;
2264}
2265
2266
2267/**
2268 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2269 */
2270static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2271{
2272 RT_NOREF(pDevIns, offReg);
2273
2274 /* MSI Vector Register 0 is read-only. */
2275 /* MSI Vector Register 1. */
2276 uint32_t const uReg = u64Value >> 32;
2277 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/**
2283 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2284 * Register (32-bit).
2285 */
2286static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2287{
2288 RT_NOREF(pThis, offReg);
2289 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2290 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2291
2292 /* MSI capability header. */
2293 {
2294 uint32_t const uReg = u64Value;
2295 MSI_CAP_HDR_T MsiCapHdr;
2296 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2297 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2298 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2299 }
2300
2301 /* MSI Address Lo. */
2302 {
2303 uint32_t const uReg = u64Value >> 32;
2304 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2305 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2306 }
2307
2308 return VINF_SUCCESS;
2309}
2310
2311
2312/**
2313 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2314 */
2315static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2316{
2317 RT_NOREF(pThis, offReg);
2318 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2319 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2320
2321 /* MSI Address Hi. */
2322 {
2323 uint32_t const uReg = u64Value;
2324 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2325 }
2326
2327 /* MSI Data. */
2328 {
2329 uint32_t const uReg = u64Value >> 32;
2330 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2331 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2332 }
2333
2334 return VINF_SUCCESS;
2335}
2336
2337
2338/**
2339 * Writes the Command Buffer Head Pointer Register.
2340 */
2341static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2342{
2343 RT_NOREF(pDevIns, offReg);
2344
2345 /*
2346 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2347 * In our emulation, we ignore the write entirely.
2348 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2349 */
2350 if (pThis->Status.n.u1CmdBufRunning)
2351 {
2352 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2353 return VINF_SUCCESS;
2354 }
2355
2356 /*
2357 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2358 * In our emulation, we ignore the write entirely.
2359 */
2360 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2361 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2362 Assert(cbBuf <= _512K);
2363 if (offBuf >= cbBuf)
2364 {
2365 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2366 return VINF_SUCCESS;
2367 }
2368
2369 /* Update the register. */
2370 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2371
2372 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2373
2374 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2375 return VINF_SUCCESS;
2376}
2377
2378
2379/**
2380 * Writes the Command Buffer Tail Pointer Register.
2381 */
2382static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2383{
2384 RT_NOREF(pDevIns, offReg);
2385
2386 /*
2387 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2388 * In our emulation, we ignore the write entirely.
2389 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2390 */
2391 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2392 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2393 Assert(cbBuf <= _512K);
2394 if (offBuf >= cbBuf)
2395 {
2396 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2397 return VINF_SUCCESS;
2398 }
2399
2400 /*
2401 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2402 * head pointer after adding one or more commands to the buffer.
2403 *
2404 * However, we cannot enforce this strictly because it's legal for software to shrink the
2405 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2406 * at 0). Software might even make the queue empty by making head and tail equal which is
2407 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2408 * in the foot here. As long as we make sure the offset value is within the circular buffer
2409 * bounds (which we do by masking bits above) it should be sufficient.
2410 */
2411 pThis->CmdBufTailPtr.au32[0] = offBuf;
2412
2413 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2414
2415 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2416 return VINF_SUCCESS;
2417}
2418
2419
2420/**
2421 * Writes the Event Log Head Pointer Register.
2422 */
2423static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2424{
2425 RT_NOREF(pDevIns, offReg);
2426
2427 /*
2428 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2429 * In our emulation, we ignore the write entirely.
2430 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2431 */
2432 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2433 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2434 Assert(cbBuf <= _512K);
2435 if (offBuf >= cbBuf)
2436 {
2437 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2438 return VINF_SUCCESS;
2439 }
2440
2441 /* Update the register. */
2442 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2443
2444 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2445 return VINF_SUCCESS;
2446}
2447
2448
2449/**
2450 * Writes the Event Log Tail Pointer Register.
2451 */
2452static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2453{
2454 RT_NOREF(pDevIns, offReg);
2455 NOREF(pThis);
2456
2457 /*
2458 * IOMMU behavior is undefined when software writes this register when the event log is running.
2459 * In our emulation, we ignore the write entirely.
2460 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2461 */
2462 if (pThis->Status.n.u1EvtLogRunning)
2463 {
2464 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2465 return VINF_SUCCESS;
2466 }
2467
2468 /*
2469 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2470 * In our emulation, we ignore the write entirely.
2471 */
2472 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2473 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2474 Assert(cbBuf <= _512K);
2475 if (offBuf >= cbBuf)
2476 {
2477 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2478 return VINF_SUCCESS;
2479 }
2480
2481 /* Update the register. */
2482 pThis->EvtLogTailPtr.au32[0] = offBuf;
2483
2484 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2485 return VINF_SUCCESS;
2486}
2487
2488
2489/**
2490 * Writes the Status Register.
2491 */
2492static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2493{
2494 RT_NOREF(pDevIns, offReg);
2495
2496 /* Mask out all unrecognized bits. */
2497 u64Value &= IOMMU_STATUS_VALID_MASK;
2498
2499 /*
2500 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2501 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2502 */
2503 IOMMU_STATUS_T const OldStatus = pThis->Status;
2504 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2505 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2506 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2507
2508 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2509
2510 /* Update the register. */
2511 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2512 return VINF_SUCCESS;
2513}
2514
2515
2516/**
2517 * Register access table 0.
2518 * The MMIO offset of each entry must be a multiple of 8!
2519 */
2520static const IOMMUREGACC g_aRegAccess0[] =
2521{
2522 /* MMIO off. Register name Read function Write function */
2523 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2524 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2525 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2526 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2527 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2528 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2529 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2530 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2531 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2532 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2533 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2534 { /* 0x58 */ NULL, NULL, NULL },
2535
2536 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2537 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2538 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2539 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2540 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2541 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2542 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2543 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2544 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2545 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2546 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2547 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2548 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2549 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2550 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2551 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2552
2553 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2554 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2555 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2556 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2557
2558 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2559 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2560 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2561 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2562 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2563 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2564 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2565
2566 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2567 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2568 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2569
2570 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2571 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2572 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2573 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2574
2575 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2576 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2577 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2578};
2579AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2580
2581/**
2582 * Register access table 1.
2583 * The MMIO offset of each entry must be a multiple of 8!
2584 */
2585static const IOMMUREGACC g_aRegAccess1[] =
2586{
2587 /* MMIO offset Register name Read function Write function */
2588 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2589 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2590 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2591 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2592 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2593 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2594 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2595 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2596 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2597 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2598 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2599 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2600};
2601AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2602
2603/**
2604 * Register access table 2.
2605 * The MMIO offset of each entry must be a multiple of 8!
2606 */
2607static const IOMMUREGACC g_aRegAccess2[] =
2608{
2609 /* MMIO offset Register name Read Function Write function */
2610 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2611
2612 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2613 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2614 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2615 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2616
2617 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2618 { /* 0x2028 */ NULL, NULL, NULL },
2619
2620 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2621 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2622
2623 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2624 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2625
2626 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2627 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2628
2629 { /* 0x2060 */ NULL, NULL, NULL },
2630 { /* 0x2068 */ NULL, NULL, NULL },
2631
2632 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2633 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2634
2635 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2636 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2637 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2638};
2639AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2640
2641
2642/**
2643 * Gets the register access structure given its MMIO offset.
2644 *
2645 * @returns The register access structure, or NULL if the offset is invalid.
2646 * @param off The MMIO offset of the register being accessed.
2647 */
2648static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2649{
2650 /* Figure out which table the register belongs to and validate its index. */
2651 PCIOMMUREGACC pReg;
2652 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2653 {
2654 uint32_t const idxReg = off >> 3;
2655 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2656 pReg = &g_aRegAccess0[idxReg];
2657 }
2658 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2659 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2660 {
2661 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2662 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2663 pReg = &g_aRegAccess1[idxReg];
2664 }
2665 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2666 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2667 {
2668 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2669 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2670 pReg = &g_aRegAccess2[idxReg];
2671 }
2672 else
2673 pReg = NULL;
2674 return pReg;
2675}
2676
2677
2678/**
2679 * Writes an IOMMU register (32-bit and 64-bit).
2680 *
2681 * @returns Strict VBox status code.
2682 * @param pDevIns The IOMMU device instance.
2683 * @param off MMIO byte offset to the register.
2684 * @param cb The size of the write access.
2685 * @param uValue The value being written.
2686 *
2687 * @thread EMT.
2688 */
2689static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2690{
2691 /*
2692 * Validate the access in case of IOM bug or incorrect assumption.
2693 */
2694 Assert(off < IOMMU_MMIO_REGION_SIZE);
2695 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2696 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2697
2698 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2699
2700 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2701 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2702 if (pReg)
2703 { /* likely */ }
2704 else
2705 {
2706 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2707 return VINF_SUCCESS;
2708 }
2709
2710 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2711 if (pReg->pfnWrite)
2712 { /* likely */ }
2713 else
2714 {
2715 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2716 return VINF_SUCCESS;
2717 }
2718
2719 /*
2720 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2721 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2722 * consecutive 32-bit registers.
2723 */
2724 if (cb == 8)
2725 {
2726 if (!(off & 7))
2727 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
2728
2729 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2730 return VINF_SUCCESS;
2731 }
2732
2733 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2734 Assert(cb == 4);
2735 if (!(off & 7))
2736 {
2737 /*
2738 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2739 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2740 */
2741 uint64_t u64Read;
2742 if (pReg->pfnRead)
2743 {
2744 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2745 if (RT_FAILURE(rcStrict))
2746 {
2747 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2748 return rcStrict;
2749 }
2750 }
2751 else
2752 u64Read = 0;
2753
2754 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2755 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
2756 }
2757
2758 /*
2759 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2760 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2761 */
2762 Assert(!(off & 3));
2763 Assert(off & 7);
2764 Assert(off >= 4);
2765 uint64_t u64Read;
2766 if (pReg->pfnRead)
2767 {
2768 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2769 if (RT_FAILURE(rcStrict))
2770 {
2771 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2772 return rcStrict;
2773 }
2774 }
2775 else
2776 u64Read = 0;
2777
2778 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2779 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2780}
2781
2782
2783/**
2784 * Reads an IOMMU register (64-bit) given its MMIO offset.
2785 *
2786 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2787 * boundary include the lower half of the subsequent register.
2788 *
2789 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2790 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2791 * software will only perform 32-bit reads on those 32-bit registers that are
2792 * aligned on 8-byte boundaries.
2793 *
2794 * @returns Strict VBox status code.
2795 * @param pDevIns The IOMMU device instance.
2796 * @param off The MMIO offset of the register in bytes.
2797 * @param puResult Where to store the value being read.
2798 *
2799 * @thread EMT.
2800 */
2801static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2802{
2803 Assert(off < IOMMU_MMIO_REGION_SIZE);
2804 Assert(!(off & 7) || !(off & 3));
2805
2806 Log4Func(("off=%#x\n", off));
2807
2808 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2809 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2810 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2811
2812 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2813 if (pReg)
2814 { /* likely */ }
2815 else
2816 {
2817 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2818 return VINF_IOM_MMIO_UNUSED_FF;
2819 }
2820
2821 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2822 if (pReg->pfnRead)
2823 { /* likely */ }
2824 else
2825 {
2826 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2827 return VINF_IOM_MMIO_UNUSED_00;
2828 }
2829
2830 /*
2831 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2832 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2833 */
2834 if (!(off & 7))
2835 return pReg->pfnRead(pDevIns, pThis, off, puResult);
2836
2837 /*
2838 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2839 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2840 */
2841 Assert(!(off & 3));
2842 Assert(off & 7);
2843 Assert(off >= 4);
2844 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2845 if (RT_SUCCESS(rcStrict))
2846 *puResult >>= 32;
2847 else
2848 {
2849 *puResult = 0;
2850 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2851 }
2852
2853 return rcStrict;
2854}
2855
2856
2857/**
2858 * Raises the MSI interrupt for the IOMMU device.
2859 *
2860 * @param pDevIns The IOMMU device instance.
2861 *
2862 * @thread Any.
2863 * @remarks The IOMMU lock may or may not be held.
2864 */
2865static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2866{
2867 LogFlowFunc(("\n"));
2868 if (iommuAmdIsMsiEnabled(pDevIns))
2869 {
2870 LogFunc(("Raising MSI\n"));
2871 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2872 }
2873}
2874
2875#if 0
2876/**
2877 * Clears the MSI interrupt for the IOMMU device.
2878 *
2879 * @param pDevIns The IOMMU device instance.
2880 *
2881 * @thread Any.
2882 * @remarks The IOMMU lock may or may not be held.
2883 */
2884static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2885{
2886 if (iommuAmdIsMsiEnabled(pDevIns))
2887 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2888}
2889#endif
2890
2891/**
2892 * Writes an entry to the event log in memory.
2893 *
2894 * @returns VBox status code.
2895 * @param pDevIns The IOMMU device instance.
2896 * @param pEvent The event to log.
2897 *
2898 * @thread Any.
2899 * @remarks The IOMMU lock must be held while calling this function.
2900 */
2901static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2902{
2903 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2904 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2905
2906 IOMMU_LOCK_NORET(pDevIns, pThisCC);
2907
2908 /* Check if event logging is active and the log has not overflowed. */
2909 IOMMU_STATUS_T const Status = pThis->Status;
2910 if ( Status.n.u1EvtLogRunning
2911 && !Status.n.u1EvtOverflow)
2912 {
2913 uint32_t const cbEvt = sizeof(*pEvent);
2914
2915 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2916 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2917 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2918
2919 /* Ensure we have space in the event log. */
2920 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2921 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2922 if (cEvts + 1 < cMaxEvts)
2923 {
2924 /* Write the event log entry to memory. */
2925 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2926 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2927 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2928 if (RT_FAILURE(rc))
2929 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2930
2931 /* Increment the event log tail pointer. */
2932 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2933 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2934
2935 /* Indicate that an event log entry was written. */
2936 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2937
2938 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2939 if (pThis->Ctrl.n.u1EvtIntrEn)
2940 iommuAmdMsiInterruptRaise(pDevIns);
2941 }
2942 else
2943 {
2944 /* Indicate that the event log has overflowed. */
2945 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2946
2947 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2948 if (pThis->Ctrl.n.u1EvtIntrEn)
2949 iommuAmdMsiInterruptRaise(pDevIns);
2950 }
2951 }
2952
2953 IOMMU_UNLOCK(pDevIns, pThisCC);
2954
2955 return VINF_SUCCESS;
2956}
2957
2958
2959/**
2960 * Sets an event in the hardware error registers.
2961 *
2962 * @param pDevIns The IOMMU device instance.
2963 * @param pEvent The event.
2964 *
2965 * @thread Any.
2966 */
2967static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2968{
2969 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2970 if (pThis->ExtFeat.n.u1HwErrorSup)
2971 {
2972 if (pThis->HwEvtStatus.n.u1Valid)
2973 pThis->HwEvtStatus.n.u1Overflow = 1;
2974 pThis->HwEvtStatus.n.u1Valid = 1;
2975 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2976 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2977 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2978 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2979 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2980 }
2981}
2982
2983
2984/**
2985 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2986 *
2987 * @param idDevice The device ID (bus, device, function).
2988 * @param idDomain The domain ID.
2989 * @param GCPhysPtEntity The system physical address of the page table
2990 * entity.
2991 * @param enmOp The IOMMU operation being performed.
2992 * @param pEvtPageTabHwErr Where to store the initialized event.
2993 */
2994static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
2995 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
2996{
2997 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
2998 pEvtPageTabHwErr->n.u16DevId = idDevice;
2999 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3000 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3001 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3002 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3003 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3004 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3005 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3006 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3007}
3008
3009
3010/**
3011 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3012 *
3013 * @param pDevIns The IOMMU device instance.
3014 * @param enmOp The IOMMU operation being performed.
3015 * @param pEvtPageTabHwErr The page table hardware error event.
3016 *
3017 * @thread Any.
3018 */
3019static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3020{
3021 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3022 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3023
3024 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3025 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3026
3027 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3028 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3029 if (enmOp != IOMMUOP_CMD)
3030 iommuAmdSetPciTargetAbort(pDevIns);
3031
3032 IOMMU_UNLOCK(pDevIns, pThisCC);
3033
3034 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3035 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3036 pEvtPageTabHwErr->n.u2Type));
3037}
3038
3039
3040#ifdef IN_RING3
3041/**
3042 * Initializes a COMMAND_HARDWARE_ERROR event.
3043 *
3044 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3045 * @param pEvtCmdHwErr Where to store the initialized event.
3046 */
3047static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3048{
3049 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3050 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3051 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3052 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3053}
3054
3055
3056/**
3057 * Raises a COMMAND_HARDWARE_ERROR event.
3058 *
3059 * @param pDevIns The IOMMU device instance.
3060 * @param pEvtCmdHwErr The command hardware error event.
3061 *
3062 * @thread Any.
3063 */
3064static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3065{
3066 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3067 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3068 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3069
3070 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3071 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3072
3073 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3074 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3075 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3076
3077 IOMMU_UNLOCK(pDevIns, pThisCC);
3078
3079 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3080}
3081#endif /* IN_RING3 */
3082
3083
3084/**
3085 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3086 *
3087 * @param idDevice The device ID (bus, device, function).
3088 * @param GCPhysDte The system physical address of the failed device table
3089 * access.
3090 * @param enmOp The IOMMU operation being performed.
3091 * @param pEvtDevTabHwErr Where to store the initialized event.
3092 */
3093static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3094 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3095{
3096 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3097 pEvtDevTabHwErr->n.u16DevId = idDevice;
3098 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3099 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3100 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3101 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3102 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3103 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3104 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3105}
3106
3107
3108/**
3109 * Raises a DEV_TAB_HARDWARE_ERROR event.
3110 *
3111 * @param pDevIns The IOMMU device instance.
3112 * @param enmOp The IOMMU operation being performed.
3113 * @param pEvtDevTabHwErr The device table hardware error event.
3114 *
3115 * @thread Any.
3116 */
3117static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3118{
3119 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3120 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3121
3122 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3123 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3124
3125 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3126 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3127 if (enmOp != IOMMUOP_CMD)
3128 iommuAmdSetPciTargetAbort(pDevIns);
3129
3130 IOMMU_UNLOCK(pDevIns, pThisCC);
3131
3132 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3133 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3134}
3135
3136
3137#ifdef IN_RING3
3138/**
3139 * Initializes an ILLEGAL_COMMAND_ERROR event.
3140 *
3141 * @param GCPhysCmd The system physical address of the failed command
3142 * access.
3143 * @param pEvtIllegalCmd Where to store the initialized event.
3144 */
3145static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3146{
3147 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3148 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3149 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3150 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3151}
3152
3153
3154/**
3155 * Raises an ILLEGAL_COMMAND_ERROR event.
3156 *
3157 * @param pDevIns The IOMMU device instance.
3158 * @param pEvtIllegalCmd The illegal command error event.
3159 */
3160static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3161{
3162 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3163 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3164 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3165
3166 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3167 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3168
3169 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3170}
3171#endif /* IN_RING3 */
3172
3173
3174/**
3175 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3176 *
3177 * @param idDevice The device ID (bus, device, function).
3178 * @param uIova The I/O virtual address.
3179 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3180 * event was caused by an invalid level encoding in the
3181 * DTE.
3182 * @param enmOp The IOMMU operation being performed.
3183 * @param pEvtIllegalDte Where to store the initialized event.
3184 */
3185static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3186 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3187{
3188 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3189 pEvtIllegalDte->n.u16DevId = idDevice;
3190 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3191 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3192 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3193 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3194 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3195 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3196 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3197 * IOMMU spec here but not for this field for I/O page fault event. */
3198 Assert(!(uIova & UINT64_C(0x3)));
3199}
3200
3201
3202/**
3203 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3204 *
3205 * @param pDevIns The IOMMU instance data.
3206 * @param enmOp The IOMMU operation being performed.
3207 * @param pEvtIllegalDte The illegal device table entry event.
3208 * @param enmEvtType The illegal device table entry event type.
3209 *
3210 * @thread Any.
3211 */
3212static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3213 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3214{
3215 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3216 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3217
3218 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3219 if (enmOp != IOMMUOP_CMD)
3220 iommuAmdSetPciTargetAbort(pDevIns);
3221
3222 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3223 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3224 NOREF(enmEvtType);
3225}
3226
3227
3228/**
3229 * Initializes an IO_PAGE_FAULT event.
3230 *
3231 * @param idDevice The device ID (bus, device, function).
3232 * @param idDomain The domain ID.
3233 * @param uIova The I/O virtual address being accessed.
3234 * @param fPresent Transaction to a page marked as present (including
3235 * DTE.V=1) or interrupt marked as remapped
3236 * (IRTE.RemapEn=1).
3237 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3238 * the I/O page fault was caused by invalid level
3239 * encoding.
3240 * @param fPermDenied Permission denied for the address being accessed.
3241 * @param enmOp The IOMMU operation being performed.
3242 * @param pEvtIoPageFault Where to store the initialized event.
3243 */
3244static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3245 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3246{
3247 Assert(!fPermDenied || fPresent);
3248 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3249 pEvtIoPageFault->n.u16DevId = idDevice;
3250 //pEvtIoPageFault->n.u4PasidHi = 0;
3251 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3252 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3253 //pEvtIoPageFault->n.u1NoExecute = 0;
3254 //pEvtIoPageFault->n.u1User = 0;
3255 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3256 pEvtIoPageFault->n.u1Present = fPresent;
3257 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3258 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3259 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3260 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3261 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3262 pEvtIoPageFault->n.u64Addr = uIova;
3263}
3264
3265
3266/**
3267 * Raises an IO_PAGE_FAULT event.
3268 *
3269 * @param pDevIns The IOMMU instance data.
3270 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3271 * @param pIrte The interrupt remapping table entry, can be NULL.
3272 * @param enmOp The IOMMU operation being performed.
3273 * @param pEvtIoPageFault The I/O page fault event.
3274 * @param enmEvtType The I/O page fault event type.
3275 *
3276 * @thread Any.
3277 */
3278static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3279 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3280{
3281 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3282 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3283
3284#ifdef IOMMU_WITH_DTE_CACHE
3285# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheAddFlags((a_pDevIns), (a_DevId), \
3286 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED)
3287#else
3288# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3289#endif
3290
3291 bool fSuppressEvtLogging = false;
3292 if ( enmOp == IOMMUOP_MEM_READ
3293 || enmOp == IOMMUOP_MEM_WRITE)
3294 {
3295 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3296 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3297 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3298 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3299 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3300 {
3301 fSuppressEvtLogging = true;
3302 }
3303 }
3304 else if (enmOp == IOMMUOP_INTR_REQ)
3305 {
3306 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3307 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3308 fSuppressEvtLogging = true;
3309 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3310 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3311 }
3312 /* else: Events are never suppressed for commands. */
3313
3314 switch (enmEvtType)
3315 {
3316 case kIoPageFaultType_PermDenied:
3317 {
3318 /* Cannot be triggered by a command. */
3319 Assert(enmOp != IOMMUOP_CMD);
3320 RT_FALL_THRU();
3321 }
3322 case kIoPageFaultType_DteRsvdPagingMode:
3323 case kIoPageFaultType_PteInvalidPageSize:
3324 case kIoPageFaultType_PteInvalidLvlEncoding:
3325 case kIoPageFaultType_SkippedLevelIovaNotZero:
3326 case kIoPageFaultType_PteRsvdNotZero:
3327 case kIoPageFaultType_PteValidNotSet:
3328 case kIoPageFaultType_DteTranslationDisabled:
3329 case kIoPageFaultType_PasidInvalidRange:
3330 {
3331 /*
3332 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3333 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3334 */
3335 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3336 {
3337 if (!fSuppressEvtLogging)
3338 {
3339 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3340 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3341 }
3342 if (enmOp != IOMMUOP_CMD)
3343 iommuAmdSetPciTargetAbort(pDevIns);
3344 }
3345 break;
3346 }
3347
3348 case kIoPageFaultType_UserSupervisor:
3349 {
3350 /* Access is blocked and only creates an event log entry. */
3351 if (!fSuppressEvtLogging)
3352 {
3353 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3354 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3355 }
3356 break;
3357 }
3358
3359 case kIoPageFaultType_IrteAddrInvalid:
3360 case kIoPageFaultType_IrteRsvdNotZero:
3361 case kIoPageFaultType_IrteRemapEn:
3362 case kIoPageFaultType_IrteRsvdIntType:
3363 case kIoPageFaultType_IntrReqAborted:
3364 case kIoPageFaultType_IntrWithPasid:
3365 {
3366 /* Only trigerred by interrupt requests. */
3367 Assert(enmOp == IOMMUOP_INTR_REQ);
3368 if (!fSuppressEvtLogging)
3369 {
3370 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3371 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3372 }
3373 iommuAmdSetPciTargetAbort(pDevIns);
3374 break;
3375 }
3376
3377 case kIoPageFaultType_SmiFilterMismatch:
3378 {
3379 /* Not supported and probably will never be, assert. */
3380 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3381 break;
3382 }
3383
3384 case kIoPageFaultType_DevId_Invalid:
3385 {
3386 /* Cannot be triggered by a command. */
3387 Assert(enmOp != IOMMUOP_CMD);
3388 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3389 if (!fSuppressEvtLogging)
3390 {
3391 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3392 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3393 }
3394 if ( enmOp == IOMMUOP_MEM_READ
3395 || enmOp == IOMMUOP_MEM_WRITE)
3396 iommuAmdSetPciTargetAbort(pDevIns);
3397 break;
3398 }
3399 }
3400
3401#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3402}
3403
3404
3405/**
3406 * Raises an IO_PAGE_FAULT event given the DTE.
3407 *
3408 * @param pDevIns The IOMMU instance data.
3409 * @param pDte The device table entry.
3410 * @param pIrte The interrupt remapping table entry, can be NULL.
3411 * @param enmOp The IOMMU operation being performed.
3412 * @param pEvtIoPageFault The I/O page fault event.
3413 * @param enmEvtType The I/O page fault event type.
3414 *
3415 * @thread Any.
3416 */
3417static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3418 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3419{
3420 Assert(pDte);
3421 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3422 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3423}
3424
3425
3426/**
3427 * Reads a device table entry for the given the device ID.
3428 *
3429 * @returns VBox status code.
3430 * @param pDevIns The IOMMU device instance.
3431 * @param idDevice The device ID (bus, device, function).
3432 * @param enmOp The IOMMU operation being performed.
3433 * @param pDte Where to store the device table entry.
3434 *
3435 * @thread Any.
3436 */
3437static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3438{
3439 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3440 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3441
3442 IOMMU_LOCK(pDevIns, pThisCC);
3443
3444 /* Figure out which device table segment is being accessed. */
3445 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3446 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3447
3448 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3449 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3450 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3451
3452 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3453 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3454 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3455
3456 /* Ensure the DTE falls completely within the device table segment. */
3457 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3458
3459 IOMMU_UNLOCK(pDevIns, pThisCC);
3460
3461 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3462 {
3463 /* Read the device table entry from guest memory. */
3464 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3465 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3466 if (RT_SUCCESS(rc))
3467 return rc;
3468
3469 /* Raise a device table hardware error. */
3470 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3471
3472 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3473 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3474 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3475 return VERR_IOMMU_DTE_READ_FAILED;
3476 }
3477
3478 /* Raise an I/O page fault for out-of-bounds acccess. */
3479 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3480 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3481 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3482 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3483 kIoPageFaultType_DevId_Invalid);
3484 return VERR_IOMMU_DTE_BAD_OFFSET;
3485}
3486
3487
3488/**
3489 * Performs pre-translation checks for the given device table entry.
3490 *
3491 * @returns VBox status code.
3492 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3493 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3494 * translation is disabled.
3495 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3496 * corresponding event was raised.
3497 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3498 * permissions.
3499 *
3500 * @param pDevIns The IOMMU device instance.
3501 * @param uIova The I/O virtual address to translate.
3502 * @param idDevice The device ID (bus, device, function).
3503 * @param fPerm The I/O permissions for this access, see
3504 * IOMMU_IO_PERM_XXX.
3505 * @param pDte The device table entry.
3506 * @param enmOp The IOMMU operation being performed.
3507 *
3508 * @thread Any.
3509 */
3510static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3511 IOMMUOP enmOp)
3512{
3513 /*
3514 * Check if the translation is valid, otherwise raise an I/O page fault.
3515 */
3516 if (pDte->n.u1TranslationValid)
3517 { /* likely */ }
3518 else
3519 {
3520 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3521 * doesn't explicitly say whether an I/O page fault is raised. From other
3522 * places in the spec. it seems early page walk terminations (starting with
3523 * the DTE) return the state computed so far and raises an I/O page fault. So
3524 * returning an invalid translation rather than skipping translation. */
3525 LogFunc(("Translation valid bit not set -> IOPF\n"));
3526 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3527 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3528 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3529 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3530 kIoPageFaultType_DteTranslationDisabled);
3531 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3532 }
3533
3534 /*
3535 * Check permissions bits in the DTE.
3536 * Note: This MUST be checked prior to checking the root page table level below!
3537 */
3538 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3539 if ((fPerm & fDtePerm) == fPerm)
3540 { /* likely */ }
3541 else
3542 {
3543 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3544 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3545 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3546 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3547 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3548 kIoPageFaultType_PermDenied);
3549 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3550 }
3551
3552 /*
3553 * If the root page table level is 0, translation is disabled and GPA=SPA and
3554 * the DTE.IR and DTE.IW bits control permissions (verified above).
3555 */
3556 uint8_t const uMaxLevel = pDte->n.u3Mode;
3557 if (uMaxLevel != 0)
3558 { /* likely */ }
3559 else
3560 {
3561 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3562 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3563 }
3564
3565 /*
3566 * If the root page table level exceeds the allowed host-address translation level,
3567 * page walk is terminated and translation fails.
3568 */
3569 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3570 { /* likely */ }
3571 else
3572 {
3573 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3574 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3575 * I'm just going with I/O page fault. */
3576 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3577 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3578 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3579 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3580 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3581 kIoPageFaultType_PteInvalidLvlEncoding);
3582 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3583 }
3584
3585 /* The DTE allows translations for this device. */
3586 return VINF_SUCCESS;
3587}
3588
3589
3590/**
3591 * Walks the I/O page table to translate the I/O virtual address to a system
3592 * physical address.
3593 *
3594 * @returns VBox status code.
3595 * @param pDevIns The IOMMU device instance.
3596 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3597 * @param fPerm The I/O permissions for this access, see
3598 * IOMMU_IO_PERM_XXX.
3599 * @param idDevice The device ID (bus, device, function).
3600 * @param pDte The device table entry.
3601 * @param enmOp The IOMMU operation being performed.
3602 * @param pPageLookup Where to store the results of the I/O page lookup. This
3603 * is only updated when VINF_SUCCESS is returned.
3604 *
3605 * @thread Any.
3606 */
3607static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3608 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3609{
3610 Assert(pDte->n.u1Valid);
3611 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3612
3613 /* The virtual address bits indexing table. */
3614 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3615 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
3616 UINT64_C(0x00000000001ff000),
3617 UINT64_C(0x000000003fe00000),
3618 UINT64_C(0x0000007fc0000000),
3619 UINT64_C(0x0000ff8000000000),
3620 UINT64_C(0x01ff000000000000),
3621 UINT64_C(0xfe00000000000000),
3622 UINT64_C(0x0000000000000000) };
3623 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
3624 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3625
3626 /* Traverse the I/O page table starting with the page directory in the DTE. */
3627 IOPTENTITY_T PtEntity;
3628 PtEntity.u64 = pDte->au64[0];
3629 for (;;)
3630 {
3631 /* Figure out the system physical address of the page table at the current level. */
3632 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3633
3634 /* Read the page table entity at the current level. */
3635 {
3636 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3637 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3638 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3639 uint64_t const offPte = idxPte << 3;
3640 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3641 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3642 if (RT_FAILURE(rc))
3643 {
3644 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3645 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3646 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3647 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3648 return VERR_IOMMU_IPE_2;
3649 }
3650 }
3651
3652 /* Check present bit. */
3653 if (PtEntity.n.u1Present)
3654 { /* likely */ }
3655 else
3656 {
3657 LogFunc(("Page table entry not present (idDevice=%#x) -> IOPF\n", idDevice));
3658 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3659 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3660 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3661 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3662 kIoPageFaultType_PermDenied);
3663 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3664 }
3665
3666 /* Check permission bits. */
3667 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3668 if ((fPerm & fPtePerm) == fPerm)
3669 { /* likely */ }
3670 else
3671 {
3672 LogFunc(("Page table entry access denied (idDevice=%#x fPerm=%#x fPtePerm=%#x) -> IOPF\n", idDevice, fPerm, fPtePerm));
3673 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3674 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3675 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3676 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3677 kIoPageFaultType_PermDenied);
3678 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3679 }
3680
3681 /* If this is a PTE, we're at the final level and we're done. */
3682 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3683 if (uNextLevel == 0)
3684 {
3685 /* The page size of the translation is the default (4K). */
3686 pPageLookup->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3687 pPageLookup->cShift = X86_PAGE_4K_SHIFT;
3688 pPageLookup->fPerm = fPtePerm;
3689 return VINF_SUCCESS;
3690 }
3691 if (uNextLevel == 7)
3692 {
3693 /* The default page size of the translation is overridden. */
3694 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3695 uint8_t cShift = X86_PAGE_4K_SHIFT;
3696 while (GCPhysPte & RT_BIT_64(cShift++))
3697 ;
3698
3699 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3700 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
3701 if ( cShift > s_acIovaLevelShifts[uLevel]
3702 && cShift < s_acIovaLevelShifts[uLevel + 1])
3703 {
3704 pPageLookup->GCPhysSpa = GCPhysPte;
3705 pPageLookup->cShift = cShift;
3706 pPageLookup->fPerm = fPtePerm;
3707 return VINF_SUCCESS;
3708 }
3709
3710 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
3711 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3712 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3713 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3714 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3715 kIoPageFaultType_PteInvalidPageSize);
3716 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3717 }
3718
3719 /* Validate the next level encoding of the PDE. */
3720#if IOMMU_MAX_HOST_PT_LEVEL < 6
3721 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3722 { /* likely */ }
3723 else
3724 {
3725 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
3726 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3727 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3728 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3729 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3730 kIoPageFaultType_PteInvalidLvlEncoding);
3731 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3732 }
3733#else
3734 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3735#endif
3736
3737 /* Validate level transition. */
3738 if (uNextLevel < uLevel)
3739 { /* likely */ }
3740 else
3741 {
3742 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3743 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3744 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3745 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3746 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3747 kIoPageFaultType_PteInvalidLvlEncoding);
3748 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3749 }
3750
3751 /* Ensure IOVA bits of skipped levels are zero. */
3752 Assert(uLevel > 0);
3753 uint64_t uIovaSkipMask = 0;
3754 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
3755 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
3756 if (!(uIova & uIovaSkipMask))
3757 { /* likely */ }
3758 else
3759 {
3760 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
3761 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3762 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3763 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3764 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3765 kIoPageFaultType_SkippedLevelIovaNotZero);
3766 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3767 }
3768
3769 /* Continue with traversing the page directory at this level. */
3770 }
3771}
3772
3773
3774/**
3775 * Page lookup callback for finding an I/O page from guest memory.
3776 *
3777 * @returns VBox status code.
3778 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3779 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3780 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3781 * insufficient to what is requested.
3782 *
3783 * @param pDevIns The IOMMU instance data.
3784 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3785 * 4K aligned).
3786 * @param fPerm The I/O permissions for this access, see
3787 * IOMMU_IO_PERM_XXX.
3788 * @param pAux The auxiliary information required during lookup.
3789 * @param pPageLookup Where to store the looked up I/O page.
3790 */
3791static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3792 PIOPAGELOOKUP pPageLookup)
3793{
3794 AssertPtr(pAux);
3795 AssertPtr(pPageLookup);
3796 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3797
3798 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3799 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3800 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3801 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3802 return rc;
3803}
3804
3805
3806/**
3807 * Looks up a range of I/O virtual addresses.
3808 *
3809 * @returns VBox status code.
3810 * @param pDevIns The IOMMU instance data.
3811 * @param pfnIoPageLookup The lookup function to use.
3812 * @param pAddrIn The I/O address range to lookup.
3813 * @param pAux The auxiliary information required by the lookup
3814 * function.
3815 * @param pAddrOut Where to store the translated I/O address range.
3816 * @param pcbPages Where to store the size of the access (round up to
3817 * the page size). Optional, can be NULL.
3818 */
3819static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3820 PCIOMMUOPAUX pAux, PIOADDRRANGE pAddrOut, size_t *pcbPages)
3821{
3822 AssertPtr(pfnIoPageLookup);
3823 AssertPtr(pAddrIn);
3824 AssertPtr(pAddrOut);
3825
3826 int rc;
3827 size_t const cbIova = pAddrIn->cb;
3828 uint8_t const fPerm = pAddrIn->fPerm;
3829 uint64_t const uIova = pAddrIn->uAddr;
3830 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3831 size_t cbRemaining = cbIova;
3832 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3833 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3834 uint64_t cbPages = 0;
3835
3836 IOPAGELOOKUP PageLookupPrev;
3837 RT_ZERO(PageLookupPrev);
3838 for (;;)
3839 {
3840 IOPAGELOOKUP PageLookup;
3841 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3842 if (RT_SUCCESS(rc))
3843 {
3844 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT);
3845
3846 /* Store the translated address before continuing to access more pages. */
3847 if (cbRemaining == cbIova)
3848 {
3849 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(PageLookup.cShift);
3850 uint64_t const offSpa = uIova & offMask;
3851 Assert(!(PageLookup.GCPhysSpa & offMask));
3852 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3853 }
3854 /* Check if addresses translated so far result in a physically contiguous region. */
3855 else if (!iommuAmdLookupIsAccessContig(&PageLookupPrev, &PageLookup))
3856 {
3857 rc = VERR_OUT_OF_RANGE;
3858 break;
3859 }
3860
3861 /* Store the page lookup result from the first/previous page. */
3862 PageLookupPrev = PageLookup;
3863
3864 /* Update size of all pages read thus far. */
3865 uint64_t const cbPage = RT_BIT_64(PageLookup.cShift);
3866 cbPages += cbPage;
3867
3868 /* Check if we need to access more pages. */
3869 if (cbRemaining > cbPage - offIova)
3870 {
3871 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3872 uIovaPage += cbPage; /* Update address of the next access. */
3873 offIova = 0; /* After first page, all pages are accessed from off 0. */
3874 }
3875 else
3876 {
3877 cbRemaining = 0;
3878 break;
3879 }
3880 }
3881 else
3882 break;
3883 }
3884
3885 pAddrOut->uAddr = GCPhysSpa; /* Update the translated address. */
3886 pAddrOut->cb = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
3887 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
3888 if (pcbPages)
3889 *pcbPages = cbPages; /* Update the size of the pages accessed. */
3890 return rc;
3891}
3892
3893
3894/**
3895 * Looks up an I/O virtual address from the device table.
3896 *
3897 * @returns VBox status code.
3898 * @param pDevIns The IOMMU instance data.
3899 * @param idDevice The device ID (bus, device, function).
3900 * @param uIova The I/O virtual address to lookup.
3901 * @param cbIova The size of the access.
3902 * @param fPerm The I/O permissions for this access, see
3903 * IOMMU_IO_PERM_XXX.
3904 * @param enmOp The IOMMU operation being performed.
3905 * @param pGCPhysSpa Where to store the translated system physical address.
3906 * @param pcbContiguous Where to store the number of contiguous bytes translated
3907 * and permission-checked.
3908 *
3909 * @thread Any.
3910 */
3911static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
3912 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3913{
3914 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3915 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3916 size_t cbContiguous = 0;
3917
3918 /* Read the device table entry from memory. */
3919 DTE_T Dte;
3920 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
3921 if (RT_SUCCESS(rc))
3922 {
3923 if (Dte.n.u1Valid)
3924 {
3925 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3926 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3927 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3928 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
3929 {
3930 /*
3931 * Check if the DTE is configured for translating addresses.
3932 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
3933 * so there's no need to check the address exclusion base/limit here.
3934 */
3935 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
3936 if (rc == VINF_SUCCESS)
3937 {
3938 IOADDRRANGE AddrIn;
3939 AddrIn.uAddr = uIova;
3940 AddrIn.cb = cbIova;
3941 AddrIn.fPerm = fPerm;
3942
3943 IOMMUOPAUX Aux;
3944 Aux.enmOp = enmOp;
3945 Aux.pDte = &Dte;
3946 Aux.idDevice = idDevice;
3947 Aux.idDomain = Dte.n.u16DomainId;
3948
3949 IOADDRRANGE AddrOut;
3950
3951 /* Lookup the address from the DTE and I/O page tables.*/
3952 size_t cbPages = 0;
3953 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbPages);
3954 GCPhysSpa = AddrOut.uAddr;
3955 cbContiguous = AddrOut.cb;
3956
3957 /* If we stopped since translation resulted in non-contiguous physical addresses,
3958 what we translated so far is still valid. */
3959 if (rc == VERR_OUT_OF_RANGE)
3960 {
3961 Assert(cbContiguous > 0 && cbContiguous < cbIova);
3962 rc = VINF_SUCCESS;
3963 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
3964 }
3965
3966 if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
3967 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
3968
3969#ifdef IOMMU_WITH_IOTLBE_CACHE
3970 if (RT_SUCCESS(rc))
3971 {
3972 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
3973 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
3974 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
3975 iommuAmdIotlbAddRange(pDevIns, Dte.n.u16DomainId, uIova & X86_PAGE_4K_BASE_MASK, cbPages,
3976 GCPhysSpa & X86_PAGE_4K_BASE_MASK, AddrOut.fPerm);
3977 }
3978#endif
3979 }
3980 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
3981 {
3982 /*
3983 * Translation is disabled for this device (root paging mode is 0).
3984 * GPA=SPA, but the permission bits are important and controls accesses.
3985 */
3986 GCPhysSpa = uIova;
3987 cbContiguous = cbIova;
3988 rc = VINF_SUCCESS;
3989
3990#ifdef IOMMU_WITH_IOTLBE_CACHE
3991 /* Update that addresses permissions of DTE apply (but omit address translation). */
3992 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_IO_PERM);
3993#endif
3994 }
3995 else
3996 {
3997 /* Address translation failed or access is denied. */
3998 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
3999 GCPhysSpa = NIL_RTGCPHYS;
4000 cbContiguous = 0;
4001 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4002 }
4003 }
4004 else
4005 {
4006 /* Invalid reserved bits in the DTE, raise an error event. */
4007 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4008 EVT_ILLEGAL_DTE_T Event;
4009 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4010 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4011 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4012 }
4013 }
4014 else
4015 {
4016 /*
4017 * The DTE is not valid, forward addresses untranslated.
4018 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4019 */
4020 GCPhysSpa = uIova;
4021 cbContiguous = cbIova;
4022
4023#ifdef IOMMU_WITH_IOTLBE_CACHE
4024 /* Update that addresses don't require translation (nor permission checks) but a DTE is present. */
4025 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4026#endif
4027 }
4028 }
4029 else
4030 {
4031 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4032 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4033 }
4034
4035 *pGCPhysSpa = GCPhysSpa;
4036 *pcbContiguous = cbContiguous;
4037 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4038 return rc;
4039}
4040
4041
4042#ifdef IOMMU_WITH_IOTLBE_CACHE
4043/**
4044 * I/O page lookup callback for finding an I/O page from the IOTLB.
4045 *
4046 * @returns VBox status code.
4047 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4048 * @retval VERR_NOT_FOUND when the page is not found.
4049 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4050 * insufficient to what is requested.
4051 *
4052 * @param pDevIns The IOMMU instance data.
4053 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4054 * 4K aligned).
4055 * @param fPerm The I/O permissions for this access, see
4056 * IOMMU_IO_PERM_XXX.
4057 * @param pAux The auxiliary information required during lookup.
4058 * @param pPageLookup Where to store the looked up I/O page.
4059 */
4060static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4061 PIOPAGELOOKUP pPageLookup)
4062{
4063 Assert(pAux);
4064 Assert(pPageLookup);
4065 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4066
4067 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4068 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4069
4070 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4071 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4072 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4073 if (pIotlbe)
4074 {
4075 *pPageLookup = pIotlbe->PageLookup;
4076 if ((pPageLookup->fPerm & fPerm) == fPerm)
4077 {
4078 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4079 return VINF_SUCCESS;
4080 }
4081 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4082 }
4083 return VERR_NOT_FOUND;
4084}
4085
4086
4087/**
4088 * Lookups a memory access from the IOTLB cache.
4089 *
4090 * @returns VBox status code.
4091 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4092 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4093 * address region.
4094 * @retval VERR_NOT_FOUND if the access was not cached.
4095 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4096 * are insufficient.
4097 *
4098 * @param pDevIns The IOMMU instance data.
4099 * @param idDevice The device ID (bus, device, function).
4100 * @param uIova The I/O virtual address to lookup.
4101 * @param cbIova The size of the access.
4102 * @param fPerm The I/O permissions for this access, see
4103 * IOMMU_IO_PERM_XXX.
4104 * @param enmOp The IOMMU operation being performed.
4105 * @param pGCPhysSpa Where to store the translated system physical address.
4106 * @param pcbContiguous Where to store the number of contiguous bytes translated
4107 * and permission-checked.
4108 */
4109static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4110 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4111{
4112 int rc;
4113 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4114
4115#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4116 do { \
4117 *pGCPhysSpa = NIL_RTGCPHYS; \
4118 *pcbContiguous = 0; \
4119 rc = (a_rc); \
4120 } while (0)
4121
4122 /*
4123 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4124 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4125 */
4126 IOMMU_LOCK_CACHE(pDevIns, pThis);
4127
4128 /* Lookup the DTE cache entry. */
4129 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4130 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4131 {
4132 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4133 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4134 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4135 {
4136 /* Lookup IOTLB entries. */
4137 IOADDRRANGE AddrIn;
4138 AddrIn.uAddr = uIova;
4139 AddrIn.cb = cbIova;
4140 AddrIn.fPerm = fPerm;
4141
4142 IOMMUOPAUX Aux;
4143 Aux.enmOp = enmOp;
4144 Aux.pDte = NULL;
4145 Aux.idDevice = idDevice;
4146 Aux.idDomain = pDteCache->idDomain;
4147
4148 IOADDRRANGE AddrOut;
4149 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, NULL /* pcbPages */);
4150 Assert(AddrOut.cb <= cbIova);
4151 *pGCPhysSpa = AddrOut.uAddr;
4152 *pcbContiguous = AddrOut.cb;
4153 }
4154 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4155 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4156 {
4157 /* Address translation is disabled, but DTE permissions apply. */
4158 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4159 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4160 if ((fDtePerm & fPerm) == fPerm)
4161 {
4162 *pGCPhysSpa = uIova;
4163 *pcbContiguous = cbIova;
4164 rc = VINF_SUCCESS;
4165 }
4166 else
4167 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4168 }
4169 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4170 {
4171 /* Forward addresses untranslated, without checking permissions. */
4172 *pGCPhysSpa = uIova;
4173 *pcbContiguous = cbIova;
4174 rc = VINF_SUCCESS;
4175 }
4176 else
4177 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4178 }
4179 else
4180 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4181
4182 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
4183
4184 return rc;
4185
4186#undef IOMMU_IOTLB_LOOKUP_FAILED
4187}
4188#endif /* IOMMU_WITH_IOTLBE_CACHE */
4189
4190
4191/**
4192 * Gets the I/O permission and IOMMU operation type for the given access flags.
4193 *
4194 * @param pThis The shared IOMMU device state.
4195 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4196 * @param penmOp Where to store the IOMMU operation.
4197 * @param pfPerm Where to store the IOMMU I/O permission.
4198 * @param fBulk Whether this is a bulk read or write.
4199 */
4200DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4201{
4202 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4203 {
4204 *penmOp = IOMMUOP_MEM_WRITE;
4205 *pfPerm = IOMMU_IO_PERM_WRITE;
4206#ifdef VBOX_WITH_STATISTICS
4207 if (!fBulk)
4208 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4209 else
4210 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4211#else
4212 RT_NOREF2(pThis, fBulk);
4213#endif
4214 }
4215 else
4216 {
4217 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4218 *penmOp = IOMMUOP_MEM_READ;
4219 *pfPerm = IOMMU_IO_PERM_READ;
4220#ifdef VBOX_WITH_STATISTICS
4221 if (!fBulk)
4222 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4223 else
4224 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4225#else
4226 RT_NOREF2(pThis, fBulk);
4227#endif
4228 }
4229}
4230
4231
4232/**
4233 * Memory access transaction from a device.
4234 *
4235 * @returns VBox status code.
4236 * @param pDevIns The IOMMU device instance.
4237 * @param idDevice The device ID (bus, device, function).
4238 * @param uIova The I/O virtual address being accessed.
4239 * @param cbIova The size of the access.
4240 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4241 * @param pGCPhysSpa Where to store the translated system physical address.
4242 * @param pcbContiguous Where to store the number of contiguous bytes translated
4243 * and permission-checked.
4244 *
4245 * @thread Any.
4246 */
4247static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4248 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4249{
4250 /* Validate. */
4251 AssertPtr(pDevIns);
4252 AssertPtr(pGCPhysSpa);
4253 Assert(cbIova > 0);
4254 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4255
4256 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4257 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4258 if (Ctrl.n.u1IommuEn)
4259 {
4260 IOMMUOP enmOp;
4261 uint8_t fPerm;
4262 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4263 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4264
4265 int rc;
4266#ifdef IOMMU_WITH_IOTLBE_CACHE
4267 /* Lookup the IOVA from the cache. */
4268 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4269 if (rc == VINF_SUCCESS)
4270 {
4271 /* All pages in the access were found in the cache with sufficient permissions. */
4272 Assert(*pcbContiguous == cbIova);
4273 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4274 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4275 return VINF_SUCCESS;
4276 }
4277 if (rc != VERR_OUT_OF_RANGE)
4278 { /* likely */ }
4279 else
4280 {
4281 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4282 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4283 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4284 return VINF_SUCCESS;
4285 }
4286
4287 /*
4288 * Access incomplete as not all pages were in the cache.
4289 * Or permissions were denied for the access (which typically doesn't happen)
4290 * so go through the slower path and raise the required event.
4291 */
4292 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4293 uIova += *pcbContiguous;
4294 cbIova -= *pcbContiguous;
4295 /* We currently are including any permission denied pages as cache misses too.*/
4296 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4297#endif
4298
4299 /* Lookup the IOVA from the device table. */
4300 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4301 if (RT_SUCCESS(rc))
4302 { /* likely */ }
4303 else
4304 {
4305 Assert(rc != VERR_OUT_OF_RANGE);
4306 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4307 cbIova, rc));
4308 }
4309
4310 return rc;
4311 }
4312
4313 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4314 *pGCPhysSpa = uIova;
4315 *pcbContiguous = cbIova;
4316 return VINF_SUCCESS;
4317}
4318
4319
4320/**
4321 * Memory access bulk (one or more 4K pages) request from a device.
4322 *
4323 * @returns VBox status code.
4324 * @param pDevIns The IOMMU device instance.
4325 * @param idDevice The device ID (bus, device, function).
4326 * @param cIovas The number of addresses being accessed.
4327 * @param pauIovas The I/O virtual addresses for each page being accessed.
4328 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4329 * @param paGCPhysSpa Where to store the translated physical addresses.
4330 *
4331 * @thread Any.
4332 */
4333static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4334 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4335{
4336 /* Validate. */
4337 AssertPtr(pDevIns);
4338 Assert(cIovas > 0);
4339 AssertPtr(pauIovas);
4340 AssertPtr(paGCPhysSpa);
4341 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4342
4343 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4344 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4345 if (Ctrl.n.u1IommuEn)
4346 {
4347 IOMMUOP enmOp;
4348 uint8_t fPerm;
4349 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4350 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4351
4352 for (size_t i = 0; i < cIovas; i++)
4353 {
4354 int rc;
4355 size_t cbContig;
4356
4357#ifdef IOMMU_WITH_IOTLBE_CACHE
4358 /* Lookup the IOVA from the IOTLB cache. */
4359 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4360 &cbContig);
4361 if (rc == VINF_SUCCESS)
4362 {
4363 Assert(cbContig == X86_PAGE_SIZE);
4364 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4365 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4366 continue;
4367 }
4368 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4369 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4370#endif
4371
4372 /* Lookup the IOVA from the device table. */
4373 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4374 if (RT_SUCCESS(rc))
4375 { /* likely */ }
4376 else
4377 {
4378 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4379 return rc;
4380 }
4381 Assert(cbContig == X86_PAGE_SIZE);
4382 }
4383 }
4384 else
4385 {
4386 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4387 for (size_t i = 0; i < cIovas; i++)
4388 paGCPhysSpa[i] = pauIovas[i];
4389 }
4390
4391 return VINF_SUCCESS;
4392}
4393
4394
4395/**
4396 * Reads an interrupt remapping table entry from guest memory given its DTE.
4397 *
4398 * @returns VBox status code.
4399 * @param pDevIns The IOMMU device instance.
4400 * @param idDevice The device ID (bus, device, function).
4401 * @param pDte The device table entry.
4402 * @param GCPhysIn The source MSI address (used for reporting errors).
4403 * @param uDataIn The source MSI data.
4404 * @param enmOp The IOMMU operation being performed.
4405 * @param pIrte Where to store the interrupt remapping table entry.
4406 *
4407 * @thread Any.
4408 */
4409static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4410 IOMMUOP enmOp, PIRTE_T pIrte)
4411{
4412 /* Ensure the IRTE length is valid. */
4413 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4414
4415 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4416 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4417 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4418 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4419
4420 /* Ensure the IRTE falls completely within the interrupt table. */
4421 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4422 { /* likely */ }
4423 else
4424 {
4425 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4426 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4427
4428 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4429 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4430 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4431 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4432 kIoPageFaultType_IrteAddrInvalid);
4433 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4434 }
4435
4436 /* Read the IRTE from memory. */
4437 Assert(!(GCPhysIrte & 3));
4438 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4439 if (RT_SUCCESS(rc))
4440 return VINF_SUCCESS;
4441
4442 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4443 * situation. Is it an I/O page fault or a device table hardware error?
4444 * There's no interrupt table hardware error event, but it's unclear what
4445 * we should do here. */
4446 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4447 return VERR_IOMMU_IPE_4;
4448}
4449
4450
4451/**
4452 * Remaps the interrupt using the interrupt remapping table.
4453 *
4454 * @returns VBox status code.
4455 * @param pDevIns The IOMMU instance data.
4456 * @param idDevice The device ID (bus, device, function).
4457 * @param pDte The device table entry.
4458 * @param enmOp The IOMMU operation being performed.
4459 * @param pMsiIn The source MSI.
4460 * @param pMsiOut Where to store the remapped MSI.
4461 *
4462 * @thread Any.
4463 */
4464static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4465 PMSIMSG pMsiOut)
4466{
4467 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4468
4469 IRTE_T Irte;
4470 uint32_t const uMsiInData = pMsiIn->Data.u32;
4471 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4472 if (RT_SUCCESS(rc))
4473 {
4474 if (Irte.n.u1RemapEnable)
4475 {
4476 if (!Irte.n.u1GuestMode)
4477 {
4478 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4479 {
4480 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4481#ifdef IOMMU_WITH_IRTE_CACHE
4482 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4483#endif
4484 return VINF_SUCCESS;
4485 }
4486
4487 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4488 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4489 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4490 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4491 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4492 kIoPageFaultType_IrteRsvdIntType);
4493 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4494 }
4495
4496 LogFunc(("Guest mode not supported -> IOPF\n"));
4497 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4498 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4499 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4500 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4501 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4502 }
4503
4504 LogFunc(("Remapping disabled -> IOPF\n"));
4505 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4506 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4507 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4508 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4509 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4510 }
4511
4512 return rc;
4513}
4514
4515
4516/**
4517 * Looks up an MSI interrupt from the interrupt remapping table.
4518 *
4519 * @returns VBox status code.
4520 * @param pDevIns The IOMMU instance data.
4521 * @param idDevice The device ID (bus, device, function).
4522 * @param enmOp The IOMMU operation being performed.
4523 * @param pMsiIn The source MSI.
4524 * @param pMsiOut Where to store the remapped MSI.
4525 *
4526 * @thread Any.
4527 */
4528static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4529{
4530 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4531 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4532 enmOp));
4533
4534 /* Read the device table entry from memory. */
4535 DTE_T Dte;
4536 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4537 if (RT_SUCCESS(rc))
4538 {
4539#ifdef IOMMU_WITH_IRTE_CACHE
4540 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4541#endif
4542 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4543 if (Dte.n.u1IntrMapValid)
4544 {
4545 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4546 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4547 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4548 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4549 { /* likely */ }
4550 else
4551 {
4552 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4553 EVT_ILLEGAL_DTE_T Event;
4554 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4555 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4556 return VERR_IOMMU_INTR_REMAP_FAILED;
4557 }
4558
4559 /*
4560 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4561 * that's connected through HyperTransport it might be possible; but for us, it
4562 * doesn't seem we need to specially handle these pins.
4563 */
4564
4565 /*
4566 * Validate the MSI source address.
4567 *
4568 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4569 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4570 * claims the region as I/O space.
4571 *
4572 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4573 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4574 * See Intel spec. 10.11.1 "Message Address Register Format".
4575 */
4576 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4577 {
4578 /*
4579 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4580 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4581 */
4582 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4583 bool fPassThru = false;
4584 switch (u8DeliveryMode)
4585 {
4586 case VBOX_MSI_DELIVERY_MODE_FIXED:
4587 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4588 {
4589 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4590 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4591 {
4592 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4593 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4594 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4595 {
4596 /*
4597 * We don't support guest interrupt remapping yet. When we do, we'll need to
4598 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4599 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4600 * already reads the control register, add that as a parameter when we eventually
4601 * support guest interrupt remapping. For now, just assert.
4602 */
4603 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4604 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4605 NOREF(pThis);
4606
4607 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4608 }
4609
4610 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4611 EVT_ILLEGAL_DTE_T Event;
4612 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4613 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4614 return VERR_IOMMU_INTR_REMAP_FAILED;
4615 }
4616
4617 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4618 {
4619 fPassThru = true;
4620 break;
4621 }
4622
4623 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4624 {
4625 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4626 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4627 iommuAmdSetPciTargetAbort(pDevIns);
4628 return VERR_IOMMU_INTR_REMAP_DENIED;
4629 }
4630
4631 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4632 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4633 EVT_ILLEGAL_DTE_T Event;
4634 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4635 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4636 return VERR_IOMMU_INTR_REMAP_FAILED;
4637 }
4638
4639 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4640 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4641 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4642 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4643 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4644 default:
4645 {
4646 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4647 u8DeliveryMode));
4648 iommuAmdSetPciTargetAbort(pDevIns);
4649 return VERR_IOMMU_INTR_REMAP_FAILED;
4650 }
4651 }
4652
4653 /*
4654 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4655 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4656 */
4657 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4658 || !pMsiIn->Addr.n.u1DestMode)
4659 {
4660 if (fPassThru)
4661 {
4662 *pMsiOut = *pMsiIn;
4663 return VINF_SUCCESS;
4664 }
4665 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4666 pMsiIn->Data.n.u8Vector));
4667 }
4668 else
4669 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4670 IOMMU_LOG_PFX, u8DeliveryMode));
4671
4672 iommuAmdSetPciTargetAbort(pDevIns);
4673 return VERR_IOMMU_INTR_REMAP_DENIED;
4674 }
4675 else
4676 {
4677 /** @todo should be cause a PCI target abort here? */
4678 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4679 return VERR_IOMMU_INTR_REMAP_FAILED;
4680 }
4681 }
4682 else
4683 {
4684 LogFlowFunc(("DTE interrupt map not valid\n"));
4685 *pMsiOut = *pMsiIn;
4686 return VINF_SUCCESS;
4687 }
4688 }
4689
4690 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4691 return VERR_IOMMU_INTR_REMAP_FAILED;
4692}
4693
4694
4695/**
4696 * Interrupt remap request from a device.
4697 *
4698 * @returns VBox status code.
4699 * @param pDevIns The IOMMU device instance.
4700 * @param idDevice The device ID (bus, device, function).
4701 * @param pMsiIn The source MSI.
4702 * @param pMsiOut Where to store the remapped MSI.
4703 */
4704static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4705{
4706 /* Validate. */
4707 Assert(pDevIns);
4708 Assert(pMsiIn);
4709 Assert(pMsiOut);
4710
4711 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4712
4713 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4714 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4715 if (Ctrl.n.u1IommuEn)
4716 {
4717 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4718
4719 int rc;
4720#ifdef IOMMU_WITH_IRTE_CACHE
4721 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4722 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4723 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4724 if (RT_SUCCESS(rc))
4725 {
4726 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4727 return VINF_SUCCESS;
4728 }
4729 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4730#endif
4731
4732 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4733 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4734 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4735 return rc;
4736 }
4737
4738 *pMsiOut = *pMsiIn;
4739 return VINF_SUCCESS;
4740}
4741
4742
4743/**
4744 * @callback_method_impl{FNIOMMMIONEWWRITE}
4745 */
4746static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4747{
4748 NOREF(pvUser);
4749 Assert(cb == 4 || cb == 8);
4750 Assert(!(off & (cb - 1)));
4751
4752 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4753 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4754
4755 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4756 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4757}
4758
4759
4760/**
4761 * @callback_method_impl{FNIOMMMIONEWREAD}
4762 */
4763static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4764{
4765 NOREF(pvUser);
4766 Assert(cb == 4 || cb == 8);
4767 Assert(!(off & (cb - 1)));
4768
4769 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4770 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4771
4772 uint64_t uResult;
4773 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4774 if (cb == 8)
4775 *(uint64_t *)pv = uResult;
4776 else
4777 *(uint32_t *)pv = (uint32_t)uResult;
4778
4779 return rcStrict;
4780}
4781
4782
4783#ifdef IN_RING3
4784/**
4785 * Processes an IOMMU command.
4786 *
4787 * @returns VBox status code.
4788 * @param pDevIns The IOMMU device instance.
4789 * @param pCmd The command to process.
4790 * @param GCPhysCmd The system physical address of the command.
4791 * @param pEvtError Where to store the error event in case of failures.
4792 *
4793 * @thread Command thread.
4794 */
4795static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4796{
4797 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4798 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4799
4800 STAM_COUNTER_INC(&pThis->StatCmd);
4801
4802 uint8_t const bCmd = pCmd->n.u4Opcode;
4803 switch (bCmd)
4804 {
4805 case IOMMU_CMD_COMPLETION_WAIT:
4806 {
4807 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4808
4809 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4810 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4811
4812 /* Validate reserved bits in the command. */
4813 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4814 {
4815 /* If Completion Store is requested, write the StoreData to the specified address. */
4816 if (pCmdComWait->n.u1Store)
4817 {
4818 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4819 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4820 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4821 if (RT_FAILURE(rc))
4822 {
4823 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4824 GCPhysStore, rc));
4825 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4826 return VERR_IOMMU_CMD_HW_ERROR;
4827 }
4828 }
4829
4830 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4831 if (pCmdComWait->n.u1Interrupt)
4832 {
4833 IOMMU_LOCK(pDevIns, pThisR3);
4834 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4835 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4836 IOMMU_UNLOCK(pDevIns, pThisR3);
4837
4838 if (fRaiseInt)
4839 iommuAmdMsiInterruptRaise(pDevIns);
4840 }
4841 return VINF_SUCCESS;
4842 }
4843 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4844 return VERR_IOMMU_CMD_INVALID_FORMAT;
4845 }
4846
4847 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4848 {
4849 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4850 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4851 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4852
4853 /* Validate reserved bits in the command. */
4854 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4855 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4856 {
4857#ifdef IOMMU_WITH_DTE_CACHE
4858 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4859#endif
4860 return VINF_SUCCESS;
4861 }
4862 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4863 return VERR_IOMMU_CMD_INVALID_FORMAT;
4864 }
4865
4866 case IOMMU_CMD_INV_IOMMU_PAGES:
4867 {
4868 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4869 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4870 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4871
4872 /* Validate reserved bits in the command. */
4873 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4874 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4875 {
4876#ifdef IOMMU_WITH_IOTLBE_CACHE
4877 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4878 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
4879 uint8_t cShift;
4880 if (!pCmdInvPages->n.u1Size)
4881 cShift = X86_PAGE_4K_SHIFT;
4882 else
4883 {
4884 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4885 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4886 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4887
4888 /*
4889 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4890 * would do the right thing by clearing the entire cache for the specified domain ID.
4891 *
4892 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4893 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4894 * A debug-time assert is in place here to let us know if any software tries this.
4895 *
4896 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4897 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4898 */
4899 Assert(uIova != UINT64_C(0xfffffffffffff000));
4900 }
4901
4902 /*
4903 * Validate invalidation size.
4904 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4905 */
4906 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4907 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4908 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4909 {
4910 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4911 size_t const cbIova = RT_BIT_64(cShift);
4912 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
4913 }
4914 else
4915 {
4916 /*
4917 * The guest provided size is invalid or exceeds the largest, meaningful page size.
4918 * In such situations we must remove all ranges for the specified domain ID.
4919 */
4920 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
4921 }
4922#endif
4923 return VINF_SUCCESS;
4924 }
4925 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4926 return VERR_IOMMU_CMD_INVALID_FORMAT;
4927 }
4928
4929 case IOMMU_CMD_INV_IOTLB_PAGES:
4930 {
4931 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
4932
4933 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4934 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4935 {
4936 /** @todo IOMMU: Implement remote IOTLB invalidation. */
4937 return VERR_NOT_IMPLEMENTED;
4938 }
4939 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4940 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4941 }
4942
4943 case IOMMU_CMD_INV_INTR_TABLE:
4944 {
4945 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
4946
4947 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
4948 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
4949
4950 /* Validate reserved bits in the command. */
4951 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
4952 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
4953 {
4954#ifdef IOMMU_WITH_IRTE_CACHE
4955 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
4956#endif
4957 return VINF_SUCCESS;
4958 }
4959 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4960 return VERR_IOMMU_CMD_INVALID_FORMAT;
4961 }
4962
4963 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
4964 {
4965 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
4966 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
4967 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
4968 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4969 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4970 }
4971
4972 case IOMMU_CMD_COMPLETE_PPR_REQ:
4973 {
4974 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
4975
4976 /* We don't support PPR requests yet. */
4977 Assert(!pThis->ExtFeat.n.u1PprSup);
4978 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4979 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4980 }
4981
4982 case IOMMU_CMD_INV_IOMMU_ALL:
4983 {
4984 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
4985 if (pThis->ExtFeat.n.u1InvAllSup)
4986 {
4987 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
4988 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
4989
4990 /* Validate reserved bits in the command. */
4991 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
4992 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
4993 {
4994#ifdef IOMMU_WITH_DTE_CACHE
4995 iommuAmdDteCacheRemoveAll(pDevIns);
4996#endif
4997#ifdef IOMMU_WITH_IOTLBE_CACHE
4998 iommuAmdIotlbRemoveAll(pDevIns);
4999#endif
5000 return VINF_SUCCESS;
5001 }
5002 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5003 return VERR_IOMMU_CMD_INVALID_FORMAT;
5004 }
5005 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5006 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5007 }
5008 }
5009
5010 STAM_COUNTER_DEC(&pThis->StatCmd);
5011 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5012 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5013 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5014}
5015
5016
5017/**
5018 * The IOMMU command thread.
5019 *
5020 * @returns VBox status code.
5021 * @param pDevIns The IOMMU device instance.
5022 * @param pThread The command thread.
5023 */
5024static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5025{
5026 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5027 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5028
5029 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5030 return VINF_SUCCESS;
5031
5032 /*
5033 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5034 * This avoid trashing the heap as well as not wasting time allocating
5035 * and freeing buffers while processing commands.
5036 */
5037 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5038 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5039 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5040
5041 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5042 {
5043 /*
5044 * Sleep perpetually until we are woken up to process commands.
5045 */
5046 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5047 if (!fSignaled)
5048 {
5049 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5050 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5051 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5052 break;
5053 Log4Func(("Woken up with rc=%Rrc\n", rc));
5054 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5055 }
5056
5057 /*
5058 * Fetch and process IOMMU commands.
5059 */
5060 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5061 * temporary host buffer before processing them as a batch. If we want to
5062 * save on host memory a bit, we could (once PGM has the necessary APIs)
5063 * lock the page mappings page mappings and access them directly. */
5064 IOMMU_LOCK(pDevIns, pThisR3);
5065
5066 if (pThis->Status.n.u1CmdBufRunning)
5067 {
5068 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5069 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5070 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5071 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5072
5073 /* Validate. */
5074 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5075 Assert(offHead < cbCmdBuf);
5076 Assert(cbCmdBuf <= cbMaxCmdBuf);
5077
5078 if (offHead != offTail)
5079 {
5080 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5081 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5082
5083 IOMMU_UNLOCK(pDevIns, pThisR3);
5084 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5085 IOMMU_LOCK(pDevIns, pThisR3);
5086
5087 if (RT_SUCCESS(rc))
5088 {
5089 /* Indicate to software we've fetched all commands from the buffer. */
5090 pThis->CmdBufHeadPtr.n.off = offTail;
5091
5092 /* Allow IOMMU to do other work while we process commands. */
5093 IOMMU_UNLOCK(pDevIns, pThisR3);
5094
5095 /* Process the fetched commands. */
5096 EVT_GENERIC_T EvtError;
5097 do
5098 {
5099 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5100 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5101 if (RT_FAILURE(rc))
5102 {
5103 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5104 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5105 {
5106 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5107 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5108 }
5109 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5110 {
5111 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5112 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5113 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5114 }
5115 break;
5116 }
5117
5118 /* Move to the next command in the circular buffer. */
5119 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5120 } while (offHead != offTail);
5121 }
5122 else
5123 {
5124 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5125 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5126 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5127 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5128
5129 IOMMU_UNLOCK(pDevIns, pThisR3);
5130 }
5131 }
5132 else
5133 IOMMU_UNLOCK(pDevIns, pThisR3);
5134 }
5135 else
5136 IOMMU_UNLOCK(pDevIns, pThisR3);
5137 }
5138
5139 RTMemFree(pvCmds);
5140 LogFlowFunc(("Command thread terminating\n"));
5141 return VINF_SUCCESS;
5142}
5143
5144
5145/**
5146 * Wakes up the command thread so it can respond to a state change.
5147 *
5148 * @returns VBox status code.
5149 * @param pDevIns The IOMMU device instance.
5150 * @param pThread The command thread.
5151 */
5152static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5153{
5154 RT_NOREF(pThread);
5155 LogFlowFunc(("\n"));
5156 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5157 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5158}
5159
5160
5161/**
5162 * @callback_method_impl{FNPCICONFIGREAD}
5163 */
5164static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5165 unsigned cb, uint32_t *pu32Value)
5166{
5167 /** @todo IOMMU: PCI config read stat counter. */
5168 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5169 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5170 return rcStrict;
5171}
5172
5173
5174/**
5175 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5176 * register write).
5177 *
5178 * @returns VBox status code.
5179 * @param pDevIns The IOMMU instance data.
5180 *
5181 * @remarks Call this function only when the IOMMU BAR is enabled.
5182 */
5183static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5184{
5185 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5186 Assert(pThis->IommuBar.n.u1Enable);
5187 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5188 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5189 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5190 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5191
5192 /* If the MMIO region is already mapped at the specified address, we're done. */
5193 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5194 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5195 return VINF_SUCCESS;
5196
5197 /* Unmap the previous MMIO region (which is at a different address). */
5198 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5199 {
5200 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5201 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5202 if (RT_FAILURE(rc))
5203 {
5204 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5205 return rc;
5206 }
5207 }
5208
5209 /* Map the newly specified MMIO region. */
5210 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5211 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5212 if (RT_FAILURE(rc))
5213 {
5214 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5215 return rc;
5216 }
5217
5218 return VINF_SUCCESS;
5219}
5220
5221
5222/**
5223 * @callback_method_impl{FNPCICONFIGWRITE}
5224 */
5225static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5226 unsigned cb, uint32_t u32Value)
5227{
5228 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5229
5230 /*
5231 * Discard writes to read-only registers that are specific to the IOMMU.
5232 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5233 * See PCI spec. 6.1. "Configuration Space Organization".
5234 */
5235 switch (uAddress)
5236 {
5237 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5238 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5239 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5240 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5241 {
5242 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5243 return VINF_SUCCESS;
5244 }
5245 }
5246
5247 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5248 IOMMU_LOCK(pDevIns, pThisR3);
5249
5250 VBOXSTRICTRC rcStrict;
5251 switch (uAddress)
5252 {
5253 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5254 {
5255 if (!pThis->IommuBar.n.u1Enable)
5256 {
5257 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5258 if (pThis->IommuBar.n.u1Enable)
5259 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5260 else
5261 rcStrict = VINF_SUCCESS;
5262 }
5263 else
5264 {
5265 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5266 rcStrict = VINF_SUCCESS;
5267 }
5268 break;
5269 }
5270
5271 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5272 {
5273 if (!pThis->IommuBar.n.u1Enable)
5274 {
5275 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5276 pThis->IommuBar.au32[1] = u32Value;
5277 }
5278 else
5279 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5280 rcStrict = VINF_SUCCESS;
5281 break;
5282 }
5283
5284 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5285 {
5286 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5287 RT_FALL_THRU();
5288 }
5289 default:
5290 {
5291 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5292 break;
5293 }
5294 }
5295
5296 IOMMU_UNLOCK(pDevIns, pThisR3);
5297
5298 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5299 return rcStrict;
5300}
5301
5302
5303/**
5304 * @callback_method_impl{FNDBGFHANDLERDEV}
5305 */
5306static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5307{
5308 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5309 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5310 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5311
5312 bool fVerbose;
5313 if ( pszArgs
5314 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
5315 fVerbose = true;
5316 else
5317 fVerbose = false;
5318
5319 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5320 /* Device Table Base Addresses (all segments). */
5321 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5322 {
5323 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5324 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5325 if (fVerbose)
5326 {
5327 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5328 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5329 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5330 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5331 }
5332 }
5333 /* Command Buffer Base Address Register. */
5334 {
5335 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5336 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5337 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5338 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5339 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5340 if (fVerbose)
5341 {
5342 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5343 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5344 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5345 cEntries, cbBuffer);
5346 }
5347 }
5348 /* Event Log Base Address Register. */
5349 {
5350 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5351 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5352 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5353 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5354 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5355 if (fVerbose)
5356 {
5357 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5358 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5359 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5360 cEntries, cbBuffer);
5361 }
5362 }
5363 /* IOMMU Control Register. */
5364 {
5365 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5366 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5367 if (fVerbose)
5368 {
5369 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5370 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5371 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5372 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5373 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5374 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5375 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5376 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5377 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5378 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5379 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5380 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5381 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5382 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5383 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5384 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5385 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5386 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5387 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5388 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5389 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5390 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5391 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5392 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5393 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5394 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5395 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5396 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5397 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5398 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5399 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5400 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5401 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5402 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5403 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5404 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5405 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5406 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5407 }
5408 }
5409 /* Exclusion Base Address Register. */
5410 {
5411 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5412 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5413 if (fVerbose)
5414 {
5415 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5416 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5417 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5418 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5419 }
5420 }
5421 /* Exclusion Range Limit Register. */
5422 {
5423 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5424 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5425 if (fVerbose)
5426 {
5427 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5428 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5429 }
5430 }
5431 /* Extended Feature Register. */
5432 {
5433 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5434 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5435 if (fVerbose)
5436 {
5437 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5438 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5439 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5440 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5441 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5442 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5443 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5444 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5445 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5446 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5447 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5448 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5449 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5450 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5451 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5452 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5453 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5454 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5455 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5456 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5457 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5458 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5459 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5460 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5461 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5462 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5463 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5464 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5465 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5466 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5467 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5468 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5469 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5470 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5471 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5472 }
5473 }
5474 /* PPR Log Base Address Register. */
5475 {
5476 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5477 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5478 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5479 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5480 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5481 if (fVerbose)
5482 {
5483 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5484 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5485 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5486 cEntries, cbBuffer);
5487 }
5488 }
5489 /* Hardware Event (Hi) Register. */
5490 {
5491 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5492 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5493 if (fVerbose)
5494 {
5495 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5496 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5497 }
5498 }
5499 /* Hardware Event (Lo) Register. */
5500 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5501 /* Hardware Event Status. */
5502 {
5503 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5504 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5505 if (fVerbose)
5506 {
5507 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5508 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5509 }
5510 }
5511 /* Guest Virtual-APIC Log Base Address Register. */
5512 {
5513 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5514 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5515 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5516 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5517 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5518 if (fVerbose)
5519 {
5520 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5521 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5522 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5523 cEntries, cbBuffer);
5524 }
5525 }
5526 /* Guest Virtual-APIC Log Tail Address Register. */
5527 {
5528 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5529 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5530 if (fVerbose)
5531 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5532 }
5533 /* PPR Log B Base Address Register. */
5534 {
5535 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5536 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5537 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5538 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5539 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5540 if (fVerbose)
5541 {
5542 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5543 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5544 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5545 cEntries, cbBuffer);
5546 }
5547 }
5548 /* Event Log B Base Address Register. */
5549 {
5550 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5551 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5552 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5553 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5554 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5555 if (fVerbose)
5556 {
5557 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5558 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5559 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5560 cEntries, cbBuffer);
5561 }
5562 }
5563 /* Device-Specific Feature Extension Register. */
5564 {
5565 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5566 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5567 if (fVerbose)
5568 {
5569 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5570 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5571 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5572 }
5573 }
5574 /* Device-Specific Control Extension Register. */
5575 {
5576 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5577 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5578 if (fVerbose)
5579 {
5580 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5581 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5582 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5583 }
5584 }
5585 /* Device-Specific Status Extension Register. */
5586 {
5587 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5588 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5589 if (fVerbose)
5590 {
5591 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5592 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5593 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5594 }
5595 }
5596 /* Miscellaneous Information Register (Lo and Hi). */
5597 {
5598 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5599 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5600 if (fVerbose)
5601 {
5602 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5603 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5604 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5605 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5606 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5607 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5608 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5609 }
5610 }
5611 /* MSI Capability Header. */
5612 {
5613 MSI_CAP_HDR_T MsiCapHdr;
5614 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5615 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5616 if (fVerbose)
5617 {
5618 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5619 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5620 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5621 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5622 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5623 }
5624 }
5625 /* MSI Address Register (Lo and Hi). */
5626 {
5627 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5628 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5629 MSIADDR MsiAddr;
5630 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5631 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5632 if (fVerbose)
5633 {
5634 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5635 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5636 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5637 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5638 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5639 }
5640 }
5641 /* MSI Data. */
5642 {
5643 MSIDATA MsiData;
5644 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5645 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5646 if (fVerbose)
5647 {
5648 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5649 MsiData.n.u8Vector);
5650 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5651 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5652 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5653 "level" : "edge");
5654 }
5655 }
5656 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5657 {
5658 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5659 MsiMapCapHdr.u32 = 0;
5660 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5661 if (fVerbose)
5662 {
5663 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5664 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5665 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5666 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5667 }
5668 }
5669 /* Performance Optimization Control Register. */
5670 {
5671 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5672 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5673 if (fVerbose)
5674 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5675 }
5676 /* XT (x2APIC) General Interrupt Control Register. */
5677 {
5678 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5679 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5680 if (fVerbose)
5681 {
5682 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5683 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5684 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5685 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5686 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5687 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5688 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5689 }
5690 }
5691 /* XT (x2APIC) PPR Interrupt Control Register. */
5692 {
5693 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5694 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5695 if (fVerbose)
5696 {
5697 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5698 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5699 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5700 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5701 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5702 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5703 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5704 }
5705 }
5706 /* XT (X2APIC) GA Log Interrupt Control Register. */
5707 {
5708 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5709 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5710 if (fVerbose)
5711 {
5712 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5713 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5714 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5715 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5716 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5717 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5718 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5719 }
5720 }
5721 /* MARC Registers. */
5722 {
5723 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5724 {
5725 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5726 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5727 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5728
5729 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5730 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5731 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5732 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5733
5734 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5735 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5736 }
5737 }
5738 /* Reserved Register. */
5739 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5740 /* Command Buffer Head Pointer Register. */
5741 {
5742 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5743 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5744 CmdBufHeadPtr.n.off);
5745 }
5746 /* Command Buffer Tail Pointer Register. */
5747 {
5748 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5749 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5750 CmdBufTailPtr.n.off);
5751 }
5752 /* Event Log Head Pointer Register. */
5753 {
5754 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5755 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5756 EvtLogHeadPtr.n.off);
5757 }
5758 /* Event Log Tail Pointer Register. */
5759 {
5760 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5761 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5762 EvtLogTailPtr.n.off);
5763 }
5764 /* Status Register. */
5765 {
5766 IOMMU_STATUS_T const Status = pThis->Status;
5767 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5768 if (fVerbose)
5769 {
5770 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5771 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5772 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5773 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5774 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5775 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5776 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5777 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5778 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5779 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5780 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5781 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5782 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5783 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5784 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5785 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5786 }
5787 }
5788 /* PPR Log Head Pointer. */
5789 {
5790 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5791 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5792 PprLogHeadPtr.n.off);
5793 }
5794 /* PPR Log Tail Pointer. */
5795 {
5796 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5797 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5798 PprLogTailPtr.n.off);
5799 }
5800 /* Guest Virtual-APIC Log Head Pointer. */
5801 {
5802 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5803 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5804 GALogHeadPtr.n.u12GALogPtr);
5805 }
5806 /* Guest Virtual-APIC Log Tail Pointer. */
5807 {
5808 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5809 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5810 GALogTailPtr.n.u12GALogPtr);
5811 }
5812 /* PPR Log B Head Pointer. */
5813 {
5814 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5815 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5816 PprLogBHeadPtr.n.off);
5817 }
5818 /* PPR Log B Tail Pointer. */
5819 {
5820 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5821 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5822 PprLogBTailPtr.n.off);
5823 }
5824 /* Event Log B Head Pointer. */
5825 {
5826 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5827 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5828 EvtLogBHeadPtr.n.off);
5829 }
5830 /* Event Log B Tail Pointer. */
5831 {
5832 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5833 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5834 EvtLogBTailPtr.n.off);
5835 }
5836 /* PPR Log Auto Response Register. */
5837 {
5838 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5839 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5840 if (fVerbose)
5841 {
5842 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5843 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5844 }
5845 }
5846 /* PPR Log Overflow Early Warning Indicator Register. */
5847 {
5848 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5849 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5850 if (fVerbose)
5851 {
5852 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5853 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5854 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5855 }
5856 }
5857 /* PPR Log Overflow Early Warning Indicator Register. */
5858 {
5859 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5860 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5861 if (fVerbose)
5862 {
5863 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5864 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5865 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5866 }
5867 }
5868}
5869
5870
5871/**
5872 * Dumps the DTE via the info callback helper.
5873 *
5874 * @param pHlp The info helper.
5875 * @param pDte The device table entry.
5876 * @param pszPrefix The string prefix.
5877 */
5878static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5879{
5880 AssertReturnVoid(pHlp);
5881 AssertReturnVoid(pDte);
5882 AssertReturnVoid(pszPrefix);
5883
5884 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5885 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5886 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5887 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5888 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5889 pDte->n.u40PageTableRootPtrLo << 12);
5890 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5891 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5892 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5893 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5894 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5895 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5896 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5897 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5898 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5899 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5900 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5901 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5902 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5903 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5904 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5905 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5906 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5907 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5908 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5909 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5910 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5911 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5912 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5913 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5914 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5915 {
5916 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
5917 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
5918 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
5919 cbIntrTable);
5920 }
5921 else
5922 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
5923 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
5924 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
5925 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
5926 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
5927 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
5928 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
5929 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
5930 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
5931 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
5932 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
5933 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
5934 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
5935 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
5936 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
5937 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
5938 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
5939 pHlp->pfnPrintf(pHlp, "\n");
5940}
5941
5942
5943/**
5944 * @callback_method_impl{FNDBGFHANDLERDEV}
5945 */
5946static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5947{
5948 if (pszArgs)
5949 {
5950 uint16_t idDevice = 0;
5951 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
5952 if (RT_SUCCESS(rc))
5953 {
5954 DTE_T Dte;
5955 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
5956 if (RT_SUCCESS(rc))
5957 {
5958 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
5959 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
5960 return;
5961 }
5962 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
5963 }
5964 else
5965 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
5966 }
5967 else
5968 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
5969}
5970
5971
5972# ifdef IOMMU_WITH_DTE_CACHE
5973/**
5974 * @callback_method_impl{FNDBGFHANDLERDEV}
5975 */
5976static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5977{
5978 RT_NOREF(pszArgs);
5979 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5980 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
5981
5982 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
5983 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
5984 for (uint16_t i = 0; i < cDteCache; i++)
5985 {
5986 uint16_t const idDevice = pThis->aDeviceIds[i];
5987 if (idDevice)
5988 {
5989 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
5990 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
5991 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
5992 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
5993
5994 PCDTECACHE pDteCache = &pThis->aDteCache[i];
5995 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
5996 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
5997 pHlp->pfnPrintf(pHlp, "\n");
5998 }
5999 }
6000 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6001}
6002# endif /* IOMMU_WITH_DTE_CACHE */
6003
6004
6005# ifdef IOMMU_WITH_IOTLBE_CACHE
6006/**
6007 * @callback_method_impl{FNDBGFHANDLERDEV}
6008 */
6009static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6010{
6011 if (pszArgs)
6012 {
6013 uint16_t idDomain = 0;
6014 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6015 if (RT_SUCCESS(rc))
6016 {
6017 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6018 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6019 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6020 IOTLBEINFOARG Args;
6021 Args.pIommuR3 = pThisR3;
6022 Args.pHlp = pHlp;
6023 Args.idDomain = idDomain;
6024
6025 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6026 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6027 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6028 }
6029 else
6030 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6031 }
6032 else
6033 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6034}
6035# endif /* IOMMU_WITH_IOTLBE_CACHE */
6036
6037
6038# ifdef IOMMU_WITH_IRTE_CACHE
6039/**
6040 * Gets the interrupt type name for an interrupt type in the IRTE.
6041 *
6042 * @returns The interrupt type name.
6043 * @param uIntrType The interrupt type (as specified in the IRTE).
6044 */
6045static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6046{
6047 switch (uIntrType)
6048 {
6049 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6050 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6051 default: return "<Reserved>";
6052 }
6053}
6054
6055
6056/**
6057 * @callback_method_impl{FNDBGFHANDLERDEV}
6058 */
6059static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6060{
6061 RT_NOREF(pszArgs);
6062
6063 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6064 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6065
6066 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6067 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6068 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6069 {
6070 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6071 uint32_t const uKey = pIrteCache->uKey;
6072 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6073 {
6074 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6075 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6076 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6077 idxIrte, offIrte, idDevice,
6078 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6079 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6080 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6081
6082 PCIRTE_T pIrte = &pIrteCache->Irte;
6083 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6084 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6085 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6086 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6087 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6088 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6089 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6090 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6091 pHlp->pfnPrintf(pHlp, "\n");
6092 }
6093 }
6094 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6095}
6096# endif /* IOMMU_WITH_IRTE_CACHE */
6097
6098
6099/**
6100 * @callback_method_impl{FNDBGFHANDLERDEV}
6101 */
6102static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6103{
6104 RT_NOREF(pszArgs);
6105
6106 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6107 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6108 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6109 NOREF(pPciDev);
6110
6111 uint8_t cSegments = 0;
6112 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6113 {
6114 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6115 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6116 if (GCPhysDevTab)
6117 ++cSegments;
6118 }
6119
6120 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6121 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6122 if (!cSegments)
6123 return;
6124
6125 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6126 {
6127 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6128 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6129 if (GCPhysDevTab)
6130 {
6131 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6132 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6133
6134 void *pvDevTab = RTMemAllocZ(cbDevTab);
6135 if (RT_LIKELY(pvDevTab))
6136 {
6137 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6138 if (RT_SUCCESS(rc))
6139 {
6140 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6141 {
6142 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6143 if ( pDte->n.u1Valid
6144 && pDte->n.u1TranslationValid
6145 && pDte->n.u3Mode != 0)
6146 {
6147 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6148 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6149 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6150 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6151 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6152 pHlp->pfnPrintf(pHlp, "\n");
6153 }
6154 }
6155 pHlp->pfnPrintf(pHlp, "\n");
6156 }
6157 else
6158 {
6159 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6160 cbDevTab, rc);
6161 }
6162
6163 RTMemFree(pvDevTab);
6164 }
6165 else
6166 {
6167 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6168 return;
6169 }
6170 }
6171 }
6172}
6173
6174
6175/**
6176 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6177 */
6178static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6179{
6180 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6181 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6182 LogFlowFunc(("\n"));
6183
6184 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6185 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6186 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6187 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6188 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6189 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6190 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6191
6192 /* Next, save all registers that can be modified by the guest. */
6193 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6194
6195 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6196 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6197 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6198 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6199
6200 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6201 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6202 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6203 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6204 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6205 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6206#if 0
6207 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6208#endif
6209
6210 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6211 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6212 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6213 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6214
6215 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6216 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6217
6218 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6219 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6220
6221#if 0
6222 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6223 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6224 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6225
6226 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6227#endif
6228 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6229
6230 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6231 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6232 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6233
6234 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6235 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6236 for (size_t i = 0; i < cMarcApers; i++)
6237 {
6238 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6239 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6240 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6241 }
6242
6243#if 0
6244 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6245#endif
6246
6247 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6248 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6249 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6250 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6251
6252 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6253
6254 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6255 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6256
6257 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6258 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6259
6260 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6261 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6262
6263 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6264 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6265
6266 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6267 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6268 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6269
6270 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6271}
6272
6273
6274/**
6275 * @callback_method_impl{FNSSMDEVLOADEXEC}
6276 */
6277static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6278{
6279 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6280 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6281 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6282 LogFlowFunc(("\n"));
6283
6284 /* Validate. */
6285 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6286 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6287 {
6288 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6289 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6290 }
6291
6292 /* Load ExtFeat and other read-only registers first. */
6293 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6294 AssertRCReturn(rc, rc);
6295 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6296 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6297 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6298 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6299 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6300 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6301 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6302
6303 /* IOMMU base address register. */
6304 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6305 AssertRCReturn(rc, rc);
6306 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6307
6308 /* Device table base address registers. */
6309 uint8_t cDevTabBaseAddrs;
6310 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6311 AssertRCReturn(rc, rc);
6312 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6313 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6314 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6315 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6316 {
6317 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6318 AssertRCReturn(rc, rc);
6319 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6320 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6321 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6322 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6323 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6324 }
6325
6326 /* Command buffer base address register. */
6327 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6328 AssertRCReturn(rc, rc);
6329 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6330 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6331 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6332
6333 /* Event log base address register. */
6334 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6335 AssertRCReturn(rc, rc);
6336 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6337 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6338 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6339
6340 /* Control register. */
6341 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6342 AssertRCReturn(rc, rc);
6343 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6344 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6345 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6346
6347 /* Exclusion range base address register. */
6348 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6349 AssertRCReturn(rc, rc);
6350 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6351
6352 /* Exclusion range limit register. */
6353 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6354 AssertRCReturn(rc, rc);
6355 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6356 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6357
6358#if 0
6359 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6360#endif
6361
6362 /* PPR log base address register. */
6363 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6364 AssertRCReturn(rc, rc);
6365 Assert(!pThis->ExtFeat.n.u1PprSup);
6366
6367 /* Hardware event (Hi) register. */
6368 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6369 AssertRCReturn(rc, rc);
6370
6371 /* Hardware event (Lo) register. */
6372 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6373 AssertRCReturn(rc, rc);
6374
6375 /* Hardware event status register. */
6376 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6377 AssertRCReturn(rc, rc);
6378 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6379
6380 /* Guest Virtual-APIC log base address register. */
6381 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6382 AssertRCReturn(rc, rc);
6383 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6384
6385 /* Guest Virtual-APIC log tail address register. */
6386 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6387 AssertRCReturn(rc, rc);
6388 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6389
6390 /* PPR log-B base address register. */
6391 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6392 AssertRCReturn(rc, rc);
6393 Assert(!pThis->ExtFeat.n.u1PprSup);
6394
6395 /* Event log-B base address register. */
6396 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6397 AssertRCReturn(rc, rc);
6398 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6399
6400#if 0
6401 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6402 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6403 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6404
6405 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6406#endif
6407
6408 /* Performance optimization control register. */
6409 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6410 AssertRCReturn(rc, rc);
6411 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6412
6413 /* x2APIC registers. */
6414 {
6415 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6416
6417 /* x2APIC general interrupt control register. */
6418 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6419 AssertRCReturn(rc, rc);
6420
6421 /* x2APIC PPR interrupt control register. */
6422 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6423 AssertRCReturn(rc, rc);
6424
6425 /* x2APIC GA log interrupt control register. */
6426 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6427 AssertRCReturn(rc, rc);
6428 }
6429
6430 /* MARC (Memory Access and Routing) registers. */
6431 {
6432 uint8_t cMarcApers;
6433 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6434 AssertRCReturn(rc, rc);
6435 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6436 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6437 for (uint8_t i = 0; i < cMarcApers; i++)
6438 {
6439 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6440 AssertRCReturn(rc, rc);
6441
6442 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6443 AssertRCReturn(rc, rc);
6444
6445 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6446 AssertRCReturn(rc, rc);
6447 }
6448 Assert(!pThis->ExtFeat.n.u2MarcSup);
6449 }
6450
6451#if 0
6452 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6453#endif
6454
6455 /* Command buffer head pointer register. */
6456 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6457 AssertRCReturn(rc, rc);
6458 {
6459 /*
6460 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6461 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6462 * we shouldn't see such values in the saved state.
6463 */
6464 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6465 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6466 Assert(cbBuf <= _512K);
6467 AssertLogRelMsgReturn(offBuf < cbBuf,
6468 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6469 }
6470
6471 /* Command buffer tail pointer register. */
6472 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6473 AssertRCReturn(rc, rc);
6474 {
6475 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6476 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6477 Assert(cbBuf <= _512K);
6478 AssertLogRelMsgReturn(offBuf < cbBuf,
6479 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6480 }
6481
6482 /* Event log head pointer register. */
6483 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6484 AssertRCReturn(rc, rc);
6485 {
6486 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6487 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6488 Assert(cbBuf <= _512K);
6489 AssertLogRelMsgReturn(offBuf < cbBuf,
6490 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6491 }
6492
6493 /* Event log tail pointer register. */
6494 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6495 AssertRCReturn(rc, rc);
6496 {
6497 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6498 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6499 Assert(cbBuf <= _512K);
6500 AssertLogRelMsgReturn(offBuf < cbBuf,
6501 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6502 }
6503
6504 /* Status register. */
6505 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6506 AssertRCReturn(rc, rc);
6507 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6508
6509 /* PPR log head pointer register. */
6510 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6511 AssertRCReturn(rc, rc);
6512 Assert(!pThis->ExtFeat.n.u1PprSup);
6513
6514 /* PPR log tail pointer register. */
6515 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6516 AssertRCReturn(rc, rc);
6517 Assert(!pThis->ExtFeat.n.u1PprSup);
6518
6519 /* Guest Virtual-APIC log head pointer register. */
6520 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6521 AssertRCReturn(rc, rc);
6522 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6523
6524 /* Guest Virtual-APIC log tail pointer register. */
6525 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6526 AssertRCReturn(rc, rc);
6527 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6528
6529 /* PPR log-B head pointer register. */
6530 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6531 AssertRCReturn(rc, rc);
6532 Assert(!pThis->ExtFeat.n.u1PprSup);
6533
6534 /* PPR log-B head pointer register. */
6535 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6536 AssertRCReturn(rc, rc);
6537 Assert(!pThis->ExtFeat.n.u1PprSup);
6538
6539 /* Event log-B head pointer register. */
6540 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6541 AssertRCReturn(rc, rc);
6542 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6543
6544 /* Event log-B tail pointer register. */
6545 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6546 AssertRCReturn(rc, rc);
6547 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6548
6549 /* PPR log auto response register. */
6550 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6551 AssertRCReturn(rc, rc);
6552 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6553
6554 /* PPR log overflow early indicator register. */
6555 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6556 AssertRCReturn(rc, rc);
6557 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6558
6559 /* PPR log-B overflow early indicator register. */
6560 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6561 AssertRCReturn(rc, rc);
6562 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6563
6564 /* End marker. */
6565 {
6566 uint32_t uEndMarker;
6567 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6568 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6569 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6570 rcErr);
6571 }
6572
6573 return rc;
6574}
6575
6576
6577/**
6578 * @callback_method_impl{FNSSMDEVLOADDONE}
6579 */
6580static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6581{
6582 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6583 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6584 RT_NOREF(pSSM);
6585 LogFlowFunc(("\n"));
6586
6587 /* Sanity. */
6588 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6589 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6590
6591 int rc;
6592 IOMMU_LOCK(pDevIns, pThisR3);
6593
6594 /* Map MMIO regions if the IOMMU BAR is enabled. */
6595 if (pThis->IommuBar.n.u1Enable)
6596 rc = iommuAmdR3MmioSetup(pDevIns);
6597 else
6598 rc = VINF_SUCCESS;
6599
6600 /* Wake up the command thread if commands need processing. */
6601 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6602
6603 IOMMU_UNLOCK(pDevIns, pThisR3);
6604
6605 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6606 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6607 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6608 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6609 pThis->ExtFeat.u64));
6610 return rc;
6611}
6612
6613
6614/**
6615 * @interface_method_impl{PDMDEVREG,pfnReset}
6616 */
6617static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6618{
6619 /*
6620 * Resets read-write portion of the IOMMU state.
6621 *
6622 * NOTE! State not initialized here is expected to be initialized during
6623 * device construction and remain read-only through the lifetime of the VM.
6624 */
6625 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6626 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6627 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6628 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6629 LogFlowFunc(("\n"));
6630
6631 IOMMU_LOCK_NORET(pDevIns, pThisR3);
6632
6633 RT_ZERO(pThis->aDevTabBaseAddrs);
6634
6635 pThis->CmdBufBaseAddr.u64 = 0;
6636 pThis->CmdBufBaseAddr.n.u4Len = 8;
6637
6638 pThis->EvtLogBaseAddr.u64 = 0;
6639 pThis->EvtLogBaseAddr.n.u4Len = 8;
6640
6641 pThis->Ctrl.u64 = 0;
6642 pThis->Ctrl.n.u1Coherent = 1;
6643 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6644
6645 pThis->ExclRangeBaseAddr.u64 = 0;
6646 pThis->ExclRangeLimit.u64 = 0;
6647
6648 pThis->PprLogBaseAddr.u64 = 0;
6649 pThis->PprLogBaseAddr.n.u4Len = 8;
6650
6651 pThis->HwEvtHi.u64 = 0;
6652 pThis->HwEvtLo = 0;
6653 pThis->HwEvtStatus.u64 = 0;
6654
6655 pThis->GALogBaseAddr.u64 = 0;
6656 pThis->GALogBaseAddr.n.u4Len = 8;
6657 pThis->GALogTailAddr.u64 = 0;
6658
6659 pThis->PprLogBBaseAddr.u64 = 0;
6660 pThis->PprLogBBaseAddr.n.u4Len = 8;
6661
6662 pThis->EvtLogBBaseAddr.u64 = 0;
6663 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6664
6665 pThis->PerfOptCtrl.u32 = 0;
6666
6667 pThis->XtGenIntrCtrl.u64 = 0;
6668 pThis->XtPprIntrCtrl.u64 = 0;
6669 pThis->XtGALogIntrCtrl.u64 = 0;
6670
6671 RT_ZERO(pThis->aMarcApers);
6672
6673 pThis->CmdBufHeadPtr.u64 = 0;
6674 pThis->CmdBufTailPtr.u64 = 0;
6675 pThis->EvtLogHeadPtr.u64 = 0;
6676 pThis->EvtLogTailPtr.u64 = 0;
6677
6678 pThis->Status.u64 = 0;
6679
6680 pThis->PprLogHeadPtr.u64 = 0;
6681 pThis->PprLogTailPtr.u64 = 0;
6682
6683 pThis->GALogHeadPtr.u64 = 0;
6684 pThis->GALogTailPtr.u64 = 0;
6685
6686 pThis->PprLogBHeadPtr.u64 = 0;
6687 pThis->PprLogBTailPtr.u64 = 0;
6688
6689 pThis->EvtLogBHeadPtr.u64 = 0;
6690 pThis->EvtLogBTailPtr.u64 = 0;
6691
6692 pThis->PprLogAutoResp.u64 = 0;
6693 pThis->PprLogOverflowEarly.u64 = 0;
6694 pThis->PprLogBOverflowEarly.u64 = 0;
6695
6696 pThis->IommuBar.u64 = 0;
6697 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6698 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6699
6700 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6701
6702 IOMMU_UNLOCK(pDevIns, pThisR3);
6703
6704#ifdef IOMMU_WITH_DTE_CACHE
6705 iommuAmdDteCacheRemoveAll(pDevIns);
6706#endif
6707#ifdef IOMMU_WITH_IOTLBE_CACHE
6708 iommuAmdIotlbRemoveAll(pDevIns);
6709#endif
6710#ifdef IOMMU_WITH_IRTE_CACHE
6711 iommuAmdIrteCacheRemoveAll(pDevIns);
6712#endif
6713}
6714
6715
6716/**
6717 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6718 */
6719static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6720{
6721 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6722 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6723 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6724 LogFlowFunc(("\n"));
6725
6726 IOMMU_LOCK_NORET(pDevIns, pThisR3);
6727
6728 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6729 {
6730 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6731 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6732 }
6733
6734#ifdef IOMMU_WITH_IOTLBE_CACHE
6735 if (pThisR3->paIotlbes)
6736 {
6737 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6738 pThisR3->paIotlbes = NULL;
6739 pThisR3->idxUnusedIotlbe = 0;
6740 }
6741#endif
6742
6743 IOMMU_UNLOCK(pDevIns, pThisR3);
6744 return VINF_SUCCESS;
6745}
6746
6747
6748/**
6749 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6750 */
6751static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6752{
6753 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6754 RT_NOREF(pCfg);
6755
6756 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6757 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6758 pThis->u32Magic = IOMMU_MAGIC;
6759 pThisR3->pDevInsR3 = pDevIns;
6760
6761 LogFlowFunc(("iInstance=%d\n", iInstance));
6762
6763 /*
6764 * Register the IOMMU with PDM.
6765 */
6766 PDMIOMMUREGR3 IommuReg;
6767 RT_ZERO(IommuReg);
6768 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6769 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6770 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6771 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6772 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6773 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6774 if (RT_FAILURE(rc))
6775 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6776 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6777 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6778 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6779 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6780 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6781 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6782 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6783 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6784
6785 /*
6786 * We will use PDM's critical section (via helpers) for the IOMMU device.
6787 */
6788 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6789 AssertRCReturn(rc, rc);
6790
6791 /*
6792 * Initialize read-only PCI configuration space.
6793 */
6794 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6795 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6796
6797 /* Header. */
6798 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6799 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6800 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6801 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6802 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6803 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6804 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6805 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6806 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6807 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6808 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6809 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6810 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6811 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6812
6813 /* Capability Header. */
6814 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6815 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6816 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6817 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6818 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6819 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6820 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6821 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6822 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6823 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6824 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6825
6826 /* Base Address Register. */
6827 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6828 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6829
6830 /* IOMMU Range Register. */
6831 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6832
6833 /* Misc. Information Register. */
6834 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6835 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6836 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6837 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6838 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6839 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6840 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6841 uint32_t const uMiscInfoReg1 = 0;
6842 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6843 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6844
6845 /* MSI Capability Header register. */
6846 PDMMSIREG MsiReg;
6847 RT_ZERO(MsiReg);
6848 MsiReg.cMsiVectors = 1;
6849 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6850 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6851 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6852
6853 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6854#if 0
6855 /* MSI Address Lo. */
6856 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6857 /* MSI Address Hi. */
6858 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6859 /* MSI Data. */
6860 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6861#endif
6862
6863#if 0
6864 /** @todo IOMMU: I don't know if we need to support this, enable later if
6865 * required. */
6866 /* MSI Mapping Capability Header register. */
6867 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6868 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6869 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6870 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6871 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6872 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6873 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6874#endif
6875
6876 /*
6877 * Register the PCI function with PDM.
6878 */
6879 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6880 AssertLogRelRCReturn(rc, rc);
6881
6882 /*
6883 * Register MSI support for the PCI device.
6884 * This must be done -after- registering it as a PCI device!
6885 */
6886 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6887 AssertRCReturn(rc, rc);
6888
6889 /*
6890 * Intercept PCI config. space accesses.
6891 */
6892 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6893 AssertLogRelRCReturn(rc, rc);
6894
6895 /*
6896 * Create the MMIO region.
6897 * Mapping of the region is done when software configures it via PCI config space.
6898 */
6899 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6900 NULL /* pvUser */,
6901 IOMMMIO_FLAGS_READ_DWORD_QWORD
6902 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
6903 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
6904 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
6905 "AMD-IOMMU", &pThis->hMmio);
6906 AssertLogRelRCReturn(rc, rc);
6907
6908 /*
6909 * Register saved state handlers.
6910 */
6911 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
6912 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
6913 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
6914 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
6915 AssertLogRelRCReturn(rc, rc);
6916
6917 /*
6918 * Register debugger info items.
6919 */
6920 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6921 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
6922 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
6923#ifdef IOMMU_WITH_IOTLBE_CACHE
6924 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
6925#endif
6926#ifdef IOMMU_WITH_DTE_CACHE
6927 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
6928#endif
6929#ifdef IOMMU_WITH_IRTE_CACHE
6930 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
6931#endif
6932
6933# ifdef VBOX_WITH_STATISTICS
6934 /*
6935 * Statistics.
6936 */
6937 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
6938 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
6939
6940 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
6941 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
6942
6943 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
6944 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
6945
6946 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
6947 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
6948
6949 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
6950 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
6951
6952 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
6953 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
6954
6955 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
6956 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
6957
6958 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
6959 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
6960 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
6961 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
6962 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
6963 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
6964 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
6965 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
6966 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
6967
6968
6969 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
6970 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
6971
6972 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
6973 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
6974
6975 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
6976 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
6977
6978 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
6979 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
6980 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
6981 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
6982 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
6983 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
6984 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
6985
6986 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
6987 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
6988# endif
6989
6990 /*
6991 * Create the command thread and its event semaphore.
6992 */
6993 char szDevIommu[64];
6994 RT_ZERO(szDevIommu);
6995 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
6996 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
6997 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
6998 AssertLogRelRCReturn(rc, rc);
6999
7000 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7001 AssertLogRelRCReturn(rc, rc);
7002
7003#ifdef IOMMU_WITH_DTE_CACHE
7004 /*
7005 * Initialize the critsect of the cache.
7006 */
7007 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7008 AssertLogRelRCReturn(rc, rc);
7009
7010 /* Several places in this code relies on this basic assumption - assert it! */
7011 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7012#endif
7013
7014#ifdef IOMMU_WITH_IOTLBE_CACHE
7015 /*
7016 * Allocate IOTLB entries.
7017 * This is allocated upfront since we expect a relatively small number of entries,
7018 * is more cache-line efficient and easier to track least recently used entries for
7019 * eviction when the cache is full. This also avoids unpredictable behavior during
7020 * the lifetime of the VM if the hyperheap gets full.
7021 */
7022 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7023 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7024 if (!pThisR3->paIotlbes)
7025 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7026 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7027 RTListInit(&pThisR3->LstLruIotlbe);
7028 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7029#endif
7030
7031 /*
7032 * Initialize read-only registers.
7033 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7034 */
7035 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7036 pThis->ExtFeat.u64 = 0;
7037 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7038 //pThis->ExtFeat.n.u1PprSup = 0;
7039 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7040 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7041 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7042 pThis->ExtFeat.n.u1InvAllSup = 1;
7043 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7044 pThis->ExtFeat.n.u1HwErrorSup = 1;
7045 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7046 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7047 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7048 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7049 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7050 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7051 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7052 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7053 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7054 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7055 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7056 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7057 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7058 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7059 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7060 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7061 //pThis->ExtFeat.n.u2MarcSup = 0;
7062 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7063 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7064 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7065 //pThis->ExtFeat.n.u1GstIoSup = 0;
7066 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7067 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7068 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7069 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7070 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7071 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7072 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7073
7074 pThis->DevSpecificFeat.u64 = 0;
7075 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7076 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7077
7078 pThis->DevSpecificCtrl.u64 = 0;
7079 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7080 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7081
7082 pThis->DevSpecificStatus.u64 = 0;
7083 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7084 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7085
7086 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7087
7088 pThis->RsvdReg = 0;
7089
7090 /*
7091 * Initialize parts of the IOMMU state as it would during reset.
7092 * Also initializes non-zero initial values like IRTE cache keys.
7093 * Must be called -after- initializing PCI config. space registers.
7094 */
7095 iommuAmdR3Reset(pDevIns);
7096
7097 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7098 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7099 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7100 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7101 pThis->ExtFeat.u64));
7102 return VINF_SUCCESS;
7103}
7104
7105#else
7106
7107/**
7108 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7109 */
7110static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7111{
7112 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7113 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7114 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7115 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7116
7117 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7118 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7119 AssertRCReturn(rc, rc);
7120
7121 /* Set up the MMIO RZ handlers. */
7122 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7123 AssertRCReturn(rc, rc);
7124
7125 /* Set up the IOMMU RZ callbacks. */
7126 PDMIOMMUREGCC IommuReg;
7127 RT_ZERO(IommuReg);
7128 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7129 IommuReg.idxIommu = pThis->idxIommu;
7130 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7131 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7132 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7133 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7134 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7135 AssertRCReturn(rc, rc);
7136 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7137 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
7138 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
7139 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
7140 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
7141 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
7142 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
7143 return VINF_SUCCESS;
7144}
7145#endif
7146
7147
7148/**
7149 * The device registration structure.
7150 */
7151const PDMDEVREG g_DeviceIommuAmd =
7152{
7153 /* .u32Version = */ PDM_DEVREG_VERSION,
7154 /* .uReserved0 = */ 0,
7155 /* .szName = */ "iommu-amd",
7156 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7157 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7158 /* .cMaxInstances = */ 1,
7159 /* .uSharedVersion = */ 42,
7160 /* .cbInstanceShared = */ sizeof(IOMMU),
7161 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7162 /* .cbInstanceRC = */ sizeof(IOMMURC),
7163 /* .cMaxPciDevices = */ 1,
7164 /* .cMaxMsixVectors = */ 0,
7165 /* .pszDescription = */ "IOMMU (AMD)",
7166#if defined(IN_RING3)
7167 /* .pszRCMod = */ "VBoxDDRC.rc",
7168 /* .pszR0Mod = */ "VBoxDDR0.r0",
7169 /* .pfnConstruct = */ iommuAmdR3Construct,
7170 /* .pfnDestruct = */ iommuAmdR3Destruct,
7171 /* .pfnRelocate = */ NULL,
7172 /* .pfnMemSetup = */ NULL,
7173 /* .pfnPowerOn = */ NULL,
7174 /* .pfnReset = */ iommuAmdR3Reset,
7175 /* .pfnSuspend = */ NULL,
7176 /* .pfnResume = */ NULL,
7177 /* .pfnAttach = */ NULL,
7178 /* .pfnDetach = */ NULL,
7179 /* .pfnQueryInterface = */ NULL,
7180 /* .pfnInitComplete = */ NULL,
7181 /* .pfnPowerOff = */ NULL,
7182 /* .pfnSoftReset = */ NULL,
7183 /* .pfnReserved0 = */ NULL,
7184 /* .pfnReserved1 = */ NULL,
7185 /* .pfnReserved2 = */ NULL,
7186 /* .pfnReserved3 = */ NULL,
7187 /* .pfnReserved4 = */ NULL,
7188 /* .pfnReserved5 = */ NULL,
7189 /* .pfnReserved6 = */ NULL,
7190 /* .pfnReserved7 = */ NULL,
7191#elif defined(IN_RING0)
7192 /* .pfnEarlyConstruct = */ NULL,
7193 /* .pfnConstruct = */ iommuAmdRZConstruct,
7194 /* .pfnDestruct = */ NULL,
7195 /* .pfnFinalDestruct = */ NULL,
7196 /* .pfnRequest = */ NULL,
7197 /* .pfnReserved0 = */ NULL,
7198 /* .pfnReserved1 = */ NULL,
7199 /* .pfnReserved2 = */ NULL,
7200 /* .pfnReserved3 = */ NULL,
7201 /* .pfnReserved4 = */ NULL,
7202 /* .pfnReserved5 = */ NULL,
7203 /* .pfnReserved6 = */ NULL,
7204 /* .pfnReserved7 = */ NULL,
7205#elif defined(IN_RC)
7206 /* .pfnConstruct = */ iommuAmdRZConstruct,
7207 /* .pfnReserved0 = */ NULL,
7208 /* .pfnReserved1 = */ NULL,
7209 /* .pfnReserved2 = */ NULL,
7210 /* .pfnReserved3 = */ NULL,
7211 /* .pfnReserved4 = */ NULL,
7212 /* .pfnReserved5 = */ NULL,
7213 /* .pfnReserved6 = */ NULL,
7214 /* .pfnReserved7 = */ NULL,
7215#else
7216# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7217#endif
7218 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7219};
7220
7221#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7222
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