VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 88621

Last change on this file since 88621 was 88621, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Build fix.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 304.9 KB
Line 
1/* $Id: DevIommuAmd.cpp 88621 2021-04-21 03:19:56Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26
27#include <iprt/x86.h>
28#include <iprt/string.h>
29#include <iprt/avl.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47
48/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
49#ifdef IN_RING3
50# define IOMMU_WITH_IOTLBE_CACHE
51#endif
52/** Enable the interrupt cache. */
53#define IOMMU_WITH_IRTE_CACHE
54
55/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
56#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
57# define IOMMU_WITH_DTE_CACHE
58/** The maximum number of device IDs in the cache. */
59# define IOMMU_DEV_CACHE_COUNT 16
60/** An empty device ID. */
61# define IOMMU_DTE_CACHE_KEY_NIL 0
62#endif
63
64#ifdef IOMMU_WITH_IRTE_CACHE
65/** The maximum number of IRTE cache entries. */
66# define IOMMU_IRTE_CACHE_COUNT 32
67/** A NIL IRTE cache entry key. */
68# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
69/** Gets the device ID from an IRTE cache entry key. */
70#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
71/** Gets the IOVA from the IOTLB entry key. */
72# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
73/** Makes an IRTE cache entry key.
74 *
75 * Bits 31:16 is the device ID (Bus, Device, Function).
76 * Bits 15:0 is the the offset into the IRTE table.
77 */
78# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
79#endif /* IOMMU_WITH_IRTE_CACHE */
80
81#ifdef IOMMU_WITH_IOTLBE_CACHE
82/** The maximum number of IOTLB entries. */
83# define IOMMU_IOTLBE_MAX 96
84/** The mask of bits covering the domain ID in the IOTLBE key. */
85# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
86/** The mask of bits covering the IOVA in the IOTLBE key. */
87# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
88/** The number of bits to shift for the domain ID of the IOTLBE key. */
89# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
90/** A NIL IOTLB key. */
91# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
92/** Gets the domain ID from an IOTLB entry key. */
93# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
94/** Gets the IOVA from the IOTLB entry key. */
95# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
96/** Makes an IOTLB entry key.
97 *
98 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
99 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
100 * so bottom 12 bits are free.
101 *
102 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
103 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
104 */
105# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
106 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
107#endif /* IOMMU_WITH_IOTLBE_CACHE */
108
109#ifdef IOMMU_WITH_DTE_CACHE
110/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
111 *
112 * Some of these flags are "basic" i.e. they correspond directly to their bits in
113 * the DTE. The rest of the flags are based on checks or operations on several DTE
114 * bits.
115 *
116 * The basic flags are:
117 * - VALID (DTE.V)
118 * - IO_PERM_READ (DTE.IR)
119 * - IO_PERM_WRITE (DTE.IW)
120 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
121 * masking consistent)
122 * - SUPPRESS_ALL_IOPF (DTE.SA)
123 * - SUPPRESS_IOPF (DTE.SE)
124 * - INTR_MAP_VALID (DTE.IV)
125 * - IGNORE_UNMAPPED_INTR (DTE.IG)
126 *
127 * @see iommuAmdGetBasicDevFlags()
128 * @{ */
129/** The DTE is present. */
130# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
131/** The DTE is valid. */
132# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
133/** The DTE permissions apply for address translations. */
134# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
135/** DTE permission - I/O read allowed. */
136# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
137/** DTE permission - I/O write allowed. */
138# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
139/** DTE permission - reserved. */
140# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
141/** Address translation required. */
142# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
143/** Suppress all I/O page faults. */
144# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
145/** Suppress I/O page faults. */
146# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
147/** Interrupt map valid. */
148# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
149/** Ignore unmapped interrupts. */
150# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
151/** An I/O page fault has been raised for this device. */
152# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
153/** Fixed and arbitrary interrupt control: Target Abort. */
154# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
155/** Fixed and arbitrary interrupt control: Forward unmapped. */
156# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
157/** Fixed and arbitrary interrupt control: Remapped. */
158# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
159/** Fixed and arbitrary interrupt control: Reserved. */
160# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
161/** @} */
162
163/** The number of bits to shift I/O device flags for DTE permissions. */
164# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
165/** The mask of DTE permissions in I/O device flags. */
166# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
167/** The number of bits to shift I/O device flags for interrupt control bits. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
169/** The mask of interrupt control bits in I/O device flags. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
171/** The number of bits to shift for ignore-unmapped interrupts bit. */
172# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
173
174/** Acquires the cache lock. */
175# define IOMMU_LOCK_CACHE(a_pDevIns, a_pThis) \
176 do { \
177 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
178 if (rcLock == VINF_SUCCESS) \
179 { /* likely */ } \
180 else \
181 { \
182 AssertRC(rcLock); \
183 return rcLock; \
184 } \
185 } while (0)
186
187/** Acquires the cache lock (asserts on failure). */
188# define IOMMU_LOCK_CACHE_NORET(a_pDevIns, a_pThis) \
189 do { \
190 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
191 AssertRC(rcLock); \
192 } while (0)
193
194/** Releases the cache lock. */
195# define IOMMU_UNLOCK_CACHE(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
196#endif /* IOMMU_WITH_DTE_CACHE */
197
198/** Gets the page offset mask given the number of bits to shift. */
199#define IOMMU_GET_PAGE_OFF_MASK(a_cShift) (~(UINT64_C(0xffffffffffffffff) << (a_cShift)))
200
201/** Acquires the PDM lock. */
202#define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
203 do { \
204 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
205 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
206 { /* likely */ } \
207 else \
208 return rcLock; \
209 } while (0)
210
211/** Acquires the PDM lock (asserts on failure). */
212#define IOMMU_LOCK_NORET(a_pDevIns, a_pThisCC) \
213 do { \
214 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
215 AssertRC(rcLock); \
216 } while (0)
217
218/** Releases the PDM lock. */
219# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
220
221
222/*********************************************************************************************************************************
223* Structures and Typedefs *
224*********************************************************************************************************************************/
225/**
226 * IOMMU operation (transaction).
227 */
228typedef enum IOMMUOP
229{
230 /** Address translation request. */
231 IOMMUOP_TRANSLATE_REQ = 0,
232 /** Memory read request. */
233 IOMMUOP_MEM_READ,
234 /** Memory write request. */
235 IOMMUOP_MEM_WRITE,
236 /** Interrupt request. */
237 IOMMUOP_INTR_REQ,
238 /** Command. */
239 IOMMUOP_CMD
240} IOMMUOP;
241/** Pointer to a IOMMU operation. */
242typedef IOMMUOP *PIOMMUOP;
243
244/**
245 * I/O page lookup.
246 */
247typedef struct IOPAGELOOKUP
248{
249 /** The translated system physical address. */
250 RTGCPHYS GCPhysSpa;
251 /** The number of offset bits in the system physical address. */
252 uint8_t cShift;
253 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
254 uint8_t fPerm;
255} IOPAGELOOKUP;
256/** Pointer to an I/O page lookup. */
257typedef IOPAGELOOKUP *PIOPAGELOOKUP;
258/** Pointer to a const I/O page lookup. */
259typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
260
261/**
262 * I/O address range.
263 */
264typedef struct IOADDRRANGE
265{
266 /** The address (virtual or physical). */
267 uint64_t uAddr;
268 /** The size of the access in bytes. */
269 size_t cb;
270 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
271 uint8_t fPerm;
272} IOADDRRANGE;
273/** Pointer to an I/O address range. */
274typedef IOADDRRANGE *PIOADDRRANGE;
275/** Pointer to a const I/O address range. */
276typedef IOADDRRANGE const *PCIOADDRRANGE;
277
278#ifdef IOMMU_WITH_DTE_CACHE
279/**
280 * Device Table Entry Cache.
281 */
282typedef struct DTECACHE
283{
284 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
285 uint16_t fFlags;
286 /** The domain ID assigned for this device by software. */
287 uint16_t idDomain;
288} DTECACHE;
289/** Pointer to an I/O device struct. */
290typedef DTECACHE *PDTECACHE;
291/** Pointer to a const I/O device struct. */
292typedef DTECACHE *PCDTECACHE;
293AssertCompileSize(DTECACHE, 4);
294#endif /* IOMMU_WITH_DTE_CACHE */
295
296#ifdef IOMMU_WITH_IOTLBE_CACHE
297/**
298 * I/O TLB Entry.
299 * Keep this as small and aligned as possible.
300 */
301typedef struct IOTLBE
302{
303 /** The AVL tree node. */
304 AVLU64NODECORE Core;
305 /** The least recently used (LRU) list node. */
306 RTLISTNODE NdLru;
307 /** The I/O page lookup results of the translation. */
308 IOPAGELOOKUP PageLookup;
309 /** Whether the entry needs to be evicted from the cache. */
310 bool fEvictPending;
311} IOTLBE;
312/** Pointer to an IOMMU I/O TLB entry struct. */
313typedef IOTLBE *PIOTLBE;
314/** Pointer to a const IOMMU I/O TLB entry struct. */
315typedef IOTLBE const *PCIOTLBE;
316AssertCompileSizeAlignment(IOTLBE, 8);
317AssertCompileMemberOffset(IOTLBE, Core, 0);
318#endif /* IOMMU_WITH_IOTLBE_CACHE */
319
320#ifdef IOMMU_WITH_IRTE_CACHE
321/**
322 * Interrupt Remap Table Entry Cache.
323 */
324typedef struct IRTECACHE
325{
326 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
327 uint32_t uKey;
328 /** The IRTE. */
329 IRTE_T Irte;
330} IRTECACHE;
331/** Pointer to an IRTE cache struct. */
332typedef IRTECACHE *PIRTECACHE;
333/** Pointer to a const IRTE cache struct. */
334typedef IRTECACHE const *PCIRTECACHE;
335AssertCompileSizeAlignment(IRTECACHE, 4);
336#endif /* IOMMU_WITH_IRTE_CACHE */
337
338/**
339 * The shared IOMMU device state.
340 */
341typedef struct IOMMU
342{
343 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
344 uint32_t idxIommu;
345 /** IOMMU magic. */
346 uint32_t u32Magic;
347
348 /** The MMIO handle. */
349 IOMMMIOHANDLE hMmio;
350 /** The event semaphore the command thread waits on. */
351 SUPSEMEVENT hEvtCmdThread;
352 /** Whether the command thread has been signaled for wake up. */
353 bool volatile fCmdThreadSignaled;
354 /** Padding. */
355 bool afPadding0[7];
356
357#ifdef IOMMU_WITH_DTE_CACHE
358 /** The critsect that protects the cache from concurrent access. */
359 PDMCRITSECT CritSectCache;
360 /** Array of device IDs. */
361 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
362 /** Array of DTE cache entries. */
363 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
364#endif
365#ifdef IOMMU_WITH_IRTE_CACHE
366 /** Array of IRTE cache entries. */
367 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
368#endif
369
370 /** @name PCI: Base capability block registers.
371 * @{ */
372 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
373 /** @} */
374
375 /** @name MMIO: Control and status registers.
376 * @{ */
377 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
378 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
379 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
380 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
381 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
382 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
383 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
384 /** @} */
385
386 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
387 * @{ */
388 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
389 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
390 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
391 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
392 /** @} */
393
394 /** @todo IOMMU: SMI filter. */
395
396 /** @name MMIO: Guest Virtual-APIC Log registers.
397 * @{ */
398 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
399 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
400 /** @} */
401
402 /** @name MMIO: Alternate PPR and Event Log registers.
403 * @{ */
404 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
405 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
406 /** @} */
407
408 /** @name MMIO: Device-specific feature registers.
409 * @{ */
410 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
411 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
412 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
413 /** @} */
414
415 /** @name MMIO: MSI Capability Block registers.
416 * @{ */
417 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
418 /** @} */
419
420 /** @name MMIO: Performance Optimization Control registers.
421 * @{ */
422 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
423 /** @} */
424
425 /** @name MMIO: x2APIC Control registers.
426 * @{ */
427 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
428 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
429 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
430 /** @} */
431
432 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
433 * @{ */
434 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
435 /** @} */
436
437 /** @name MMIO: Reserved register.
438 * @{ */
439 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
440 /** @} */
441
442 /** @name MMIO: Command and Event Log pointer registers.
443 * @{ */
444 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
445 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
446 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
447 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
448 /** @} */
449
450 /** @name MMIO: Command and Event Status register.
451 * @{ */
452 IOMMU_STATUS_T Status; /**< IOMMU status register. */
453 /** @} */
454
455 /** @name MMIO: PPR Log Head and Tail pointer registers.
456 * @{ */
457 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
458 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
459 /** @} */
460
461 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
462 * @{ */
463 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
464 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
465 /** @} */
466
467 /** @name MMIO: PPR Log B Head and Tail pointer registers.
468 * @{ */
469 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
470 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
471 /** @} */
472
473 /** @name MMIO: Event Log B Head and Tail pointer registers.
474 * @{ */
475 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
476 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
477 /** @} */
478
479 /** @name MMIO: PPR Log Overflow protection registers.
480 * @{ */
481 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
482 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
483 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
484 /** @} */
485
486 /** @todo IOMMU: IOMMU Event counter registers. */
487
488#ifdef VBOX_WITH_STATISTICS
489 /** @name IOMMU: Stat counters.
490 * @{ */
491 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
492 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
493 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
494 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
495
496 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
497 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
498
499 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
500 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
501 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
502 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
503
504 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
505 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
506 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
507 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
508
509 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
510 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
511 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
512 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
513 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
514 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
515 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
516 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
517 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
518
519 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
520 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
521
522 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
523 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
524
525 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
526 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
527
528 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
529 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
530 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
531 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
532 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
533 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
534 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
535
536 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
537 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
538 /** @} */
539#endif
540} IOMMU;
541/** Pointer to the IOMMU device state. */
542typedef IOMMU *PIOMMU;
543/** Pointer to the const IOMMU device state. */
544typedef const IOMMU *PCIOMMU;
545AssertCompileMemberAlignment(IOMMU, hMmio, 8);
546#ifdef IOMMU_WITH_DTE_CACHE
547AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
548AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
549AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
550#endif
551#ifdef IOMMU_WITH_IRTE_CACHE
552AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
553#endif
554AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
555AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
556AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
557AssertCompileMemberAlignment(IOMMU, Status, 8);
558
559/**
560 * The ring-3 IOMMU device state.
561 */
562typedef struct IOMMUR3
563{
564 /** Device instance. */
565 PPDMDEVINSR3 pDevInsR3;
566 /** The IOMMU helpers. */
567 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
568 /** The command thread handle. */
569 R3PTRTYPE(PPDMTHREAD) pCmdThread;
570#ifdef IOMMU_WITH_IOTLBE_CACHE
571 /** Pointer to array of pre-allocated IOTLBEs. */
572 PIOTLBE paIotlbes;
573 /** Maps [DomainId,Iova] to [IOTLBE]. */
574 AVLU64TREE TreeIotlbe;
575 /** LRU list anchor for IOTLB entries. */
576 RTLISTANCHOR LstLruIotlbe;
577 /** Index of the next unused IOTLB. */
578 uint32_t idxUnusedIotlbe;
579 /** Number of cached IOTLB entries in the tree. */
580 uint32_t cCachedIotlbes;
581#endif
582} IOMMUR3;
583/** Pointer to the ring-3 IOMMU device state. */
584typedef IOMMUR3 *PIOMMUR3;
585/** Pointer to the const ring-3 IOMMU device state. */
586typedef const IOMMUR3 *PCIOMMUR3;
587#ifdef IOMMU_WITH_IOTLBE_CACHE
588AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
589AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
590AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
591#endif
592
593/**
594 * The ring-0 IOMMU device state.
595 */
596typedef struct IOMMUR0
597{
598 /** Device instance. */
599 PPDMDEVINSR0 pDevInsR0;
600 /** The IOMMU helpers. */
601 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
602} IOMMUR0;
603/** Pointer to the ring-0 IOMMU device state. */
604typedef IOMMUR0 *PIOMMUR0;
605
606/**
607 * The raw-mode IOMMU device state.
608 */
609typedef struct IOMMURC
610{
611 /** Device instance. */
612 PPDMDEVINSRC pDevInsRC;
613 /** The IOMMU helpers. */
614 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
615} IOMMURC;
616/** Pointer to the raw-mode IOMMU device state. */
617typedef IOMMURC *PIOMMURC;
618
619/** The IOMMU device state for the current context. */
620typedef CTX_SUFF(IOMMU) IOMMUCC;
621/** Pointer to the IOMMU device state for the current context. */
622typedef CTX_SUFF(PIOMMU) PIOMMUCC;
623
624/**
625 * IOMMU register access.
626 */
627typedef struct IOMMUREGACC
628{
629 const char *pszName;
630 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
631 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
632} IOMMUREGACC;
633/** Pointer to an IOMMU register access. */
634typedef IOMMUREGACC *PIOMMUREGACC;
635/** Pointer to a const IOMMU register access. */
636typedef IOMMUREGACC const *PCIOMMUREGACC;
637
638#ifdef IOMMU_WITH_IOTLBE_CACHE
639/**
640 * IOTLBE flush argument.
641 */
642typedef struct IOTLBEFLUSHARG
643{
644 /** The ring-3 IOMMU device state. */
645 PIOMMUR3 pIommuR3;
646 /** The domain ID to flush. */
647 uint16_t idDomain;
648} IOTLBEFLUSHARG;
649/** Pointer to an IOTLBE flush argument. */
650typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
651/** Pointer to a const IOTLBE flush argument. */
652typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
653
654/**
655 * IOTLBE Info. argument.
656 */
657typedef struct IOTLBEINFOARG
658{
659 /** The ring-3 IOMMU device state. */
660 PIOMMUR3 pIommuR3;
661 /** The info helper. */
662 PCDBGFINFOHLP pHlp;
663 /** The domain ID to dump IOTLB entry. */
664 uint16_t idDomain;
665} IOTLBEINFOARG;
666/** Pointer to an IOTLBE flush argument. */
667typedef IOTLBEINFOARG *PIOTLBEINFOARG;
668/** Pointer to a const IOTLBE flush argument. */
669typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
670#endif
671
672/**
673 * IOMMU operation auxiliary info.
674 */
675typedef struct IOMMUOPAUX
676{
677 /** The IOMMU operation being performed. */
678 IOMMUOP enmOp;
679 /** The device table entry (can be NULL). */
680 PCDTE_T pDte;
681 /** The device ID (bus, device, function). */
682 uint16_t idDevice;
683 /** The domain ID (when the DTE isn't provided). */
684 uint16_t idDomain;
685} IOMMUOPAUX;
686/** Pointer to an I/O address lookup struct. */
687typedef IOMMUOPAUX *PIOMMUOPAUX;
688/** Pointer to a const I/O address lookup struct. */
689typedef IOMMUOPAUX const *PCIOMMUOPAUX;
690
691typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
692 PIOPAGELOOKUP pPageLookup));
693typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
694
695
696/*********************************************************************************************************************************
697* Global Variables *
698*********************************************************************************************************************************/
699#if defined(IN_RING3) || defined(LOG_ENABLED)
700/**
701 * The IOMMU I/O permission names.
702 */
703static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
704
705/**
706 * An array of the number of device table segments supported.
707 * Indexed by u2DevTabSegSup.
708 */
709static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
710#endif
711
712/**
713 * An array of the masks to select the device table segment index from a device ID.
714 */
715static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
716
717/**
718 * An array of the shift values to select the device table segment index from a
719 * device ID.
720 */
721static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
722
723/**
724 * The maximum size (inclusive) of each device table segment (0 to 7).
725 * Indexed by the device table segment index.
726 */
727static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
728
729
730#ifndef VBOX_DEVICE_STRUCT_TESTCASE
731/**
732 * Gets the maximum number of buffer entries for the given buffer length.
733 *
734 * @returns Number of buffer entries.
735 * @param uEncodedLen The length (power-of-2 encoded).
736 */
737DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
738{
739 Assert(uEncodedLen > 7);
740 Assert(uEncodedLen < 16);
741 return 2 << (uEncodedLen - 1);
742}
743
744
745/**
746 * Gets the total length of the buffer given a base register's encoded length.
747 *
748 * @returns The length of the buffer in bytes.
749 * @param uEncodedLen The length (power-of-2 encoded).
750 */
751DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
752{
753 Assert(uEncodedLen > 7);
754 Assert(uEncodedLen < 16);
755 return (2 << (uEncodedLen - 1)) << 4;
756}
757
758
759/**
760 * Gets the number of (unconsumed) entries in the event log.
761 *
762 * @returns The number of entries in the event log.
763 * @param pThis The shared IOMMU device state.
764 */
765static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
766{
767 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
768 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
769 if (idxTail >= idxHead)
770 return idxTail - idxHead;
771
772 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
773 return cMaxEvts - idxHead + idxTail;
774}
775
776
777#if defined(IN_RING3) || defined(LOG_ENABLED)
778/**
779 * Gets the descriptive I/O permission name for a memory access.
780 *
781 * @returns The I/O permission name.
782 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
783 */
784static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
785{
786 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
787 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
788 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
789}
790#endif
791
792
793/**
794 * Checks whether two consecutive I/O page lookup results translates to a physically
795 * contiguous region.
796 *
797 * @returns @c true if they are contiguous, @c false otherwise.
798 * @param pPageLookupPrev The I/O page lookup result of the previous page.
799 * @param pPageLookup The I/O page lookup result of the current page.
800 */
801static bool iommuAmdLookupIsAccessContig(PCIOPAGELOOKUP pPageLookupPrev, PCIOPAGELOOKUP pPageLookup)
802{
803 Assert(pPageLookupPrev->fPerm == pPageLookup->fPerm);
804 size_t const cbPrev = RT_BIT_64(pPageLookupPrev->cShift);
805 RTGCPHYS const GCPhysPrev = pPageLookupPrev->GCPhysSpa;
806 RTGCPHYS const GCPhys = pPageLookup->GCPhysSpa;
807 uint64_t const offMaskPrev = IOMMU_GET_PAGE_OFF_MASK(pPageLookupPrev->cShift);
808 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(pPageLookup->cShift);
809
810 /* Paranoia: Ensure offset bits are 0. */
811 Assert(!(GCPhysPrev & offMaskPrev));
812 Assert(!(GCPhys & offMask));
813
814 if ((GCPhysPrev & ~offMaskPrev) + cbPrev == (GCPhys & ~offMask))
815 return true;
816 return false;
817}
818
819
820/**
821 * Gets the basic I/O device flags for the given device table entry.
822 *
823 * @returns The basic I/O device flags.
824 * @param pDte The device table entry.
825 */
826static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
827{
828 /* Extract basic flags from bits 127:0 of the DTE. */
829 uint16_t fFlags = 0;
830 if (pDte->n.u1Valid)
831 {
832 fFlags |= IOMMU_DTE_CACHE_F_VALID;
833
834 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
835 if (pDte->n.u1SuppressAllPfEvents)
836 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
837 if (pDte->n.u1SuppressPfEvents)
838 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
839
840 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
841 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
842 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
843 }
844
845 /* Extract basic flags from bits 255:128 of the DTE. */
846 if (pDte->n.u1IntrMapValid)
847 {
848 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
849
850 /** @todo Skip the if check here (shift/mask the relevant bit over). */
851 if (pDte->n.u1IgnoreUnmappedIntrs)
852 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
853
854 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
855 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
856 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
857 }
858 return fFlags;
859}
860
861
862/**
863 * Remaps the source MSI to the destination MSI given the IRTE.
864 *
865 * @param pMsiIn The source MSI.
866 * @param pMsiOut Where to store the remapped MSI.
867 * @param pIrte The IRTE used for the remapping.
868 */
869static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
870{
871 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
872 *pMsiOut = *pMsiIn;
873
874 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
875 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
876
877 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
878 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
879}
880
881
882#ifdef IOMMU_WITH_DTE_CACHE
883/**
884 * Looks up an entry in the DTE cache for the given device ID.
885 *
886 * @returns The index of the entry, or the cache capacity if no entry was found.
887 * @param pThis The shared IOMMU device state.
888 * @param idDevice The device ID (bus, device, function).
889 */
890DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
891{
892 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
893 for (uint16_t i = 0; i < cDeviceIds; i++)
894 {
895 if (pThis->aDeviceIds[i] == idDevice)
896 return i;
897 }
898 return cDeviceIds;
899}
900
901
902/**
903 * Gets an free/unused DTE cache entry.
904 *
905 * @returns The index of an unused entry, or cache capacity if the cache is full.
906 * @param pThis The shared IOMMU device state.
907 */
908DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
909{
910 /*
911 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
912 * (the latter being an ugly hack) and cannot be a valid device ID.
913 */
914 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
915 for (uint16_t i = 0; i < cDeviceIds; i++)
916 {
917 if (!pThis->aDeviceIds[i])
918 return i;
919 }
920 return cDeviceIds;
921}
922
923
924/**
925 * Adds or updates the I/O device flags for the given device ID.
926 *
927 * @returns VBox status code.
928 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
929 *
930 * @param pDevIns The IOMMU instance data.
931 * @param idDevice The device ID (bus, device, function).
932 * @param pDte The device table entry.
933 * @param fOrMask The device flags (usually compound flags) to OR in with the
934 * basic flags, see IOMMU_DTE_CACHE_F_XXX.
935 */
936static int iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, uint16_t fOrMask)
937{
938 Assert(pDte);
939 Assert(idDevice);
940
941 int rc = VINF_SUCCESS;
942 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask;
943 uint16_t const idDomain = pDte->n.u16DomainId;
944
945 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
946 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
947
948 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
949 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
950 if (idxDte < cDteCache)
951 {
952 pThis->aDteCache[idxDte].fFlags = fFlags;
953 pThis->aDteCache[idxDte].idDomain = idDomain;
954 }
955 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
956 {
957 pThis->aDeviceIds[idxDte] = idDevice;
958 pThis->aDteCache[idxDte].fFlags = fFlags;
959 pThis->aDteCache[idxDte].idDomain = idDomain;
960 }
961 else
962 rc = VERR_OUT_OF_RESOURCES;
963
964 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
965 return rc;
966}
967
968
969/**
970 * Adds one or more I/O device flags if the device is already present in the cache.
971 *
972 * @param pDevIns The IOMMU instance data.
973 * @param idDevice The device ID (bus, device, function).
974 * @param fFlags Additional device flags to OR with existing flags, see
975 * IOMMU_DTE_CACHE_F_XXX.
976 */
977static void iommuAmdDteCacheAddFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fFlags)
978{
979 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
980 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
981
982 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
983 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
984 if ( idxDte < cDteCache
985 && (pThis->aDteCache[idxDte].fFlags & IOMMU_DTE_CACHE_F_PRESENT))
986 pThis->aDteCache[idxDte].fFlags |= fFlags;
987
988 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
989}
990
991
992# ifdef IN_RING3
993/**
994 * Removes a DTE cache entry.
995 *
996 * @param pDevIns The IOMMU instance data.
997 * @param idDevice The device ID to remove cache entries for.
998 */
999static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1000{
1001 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1002 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1003
1004 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1005 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1006 if (idxDte < cDteCache)
1007 {
1008 pThis->aDteCache[idxDte].fFlags = 0;
1009 pThis->aDteCache[idxDte].idDomain = 0;
1010 }
1011
1012 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1013}
1014
1015
1016/**
1017 * Removes all entries in the device table entry cache.
1018 *
1019 * @param pDevIns The IOMMU instance data.
1020 */
1021static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1022{
1023 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1024 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1025 RT_ZERO(pThis->aDeviceIds);
1026 RT_ZERO(pThis->aDteCache);
1027 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1028}
1029# endif /* IN_RING3 */
1030#endif /* IOMMU_WITH_DTE_CACHE */
1031
1032
1033#ifdef IOMMU_WITH_IOTLBE_CACHE
1034/**
1035 * Moves the IOTLB entry to the least recently used slot.
1036 *
1037 * @param pThisR3 The ring-3 IOMMU device state.
1038 * @param pIotlbe The IOTLB entry to move.
1039 */
1040DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1041{
1042 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1043 {
1044 RTListNodeRemove(&pIotlbe->NdLru);
1045 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1046 }
1047}
1048
1049
1050/**
1051 * Moves the IOTLB entry to the most recently used slot.
1052 *
1053 * @param pThisR3 The ring-3 IOMMU device state.
1054 * @param pIotlbe The IOTLB entry to move.
1055 */
1056DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1057{
1058 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1059 {
1060 RTListNodeRemove(&pIotlbe->NdLru);
1061 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1062 }
1063}
1064
1065
1066# ifdef IN_RING3
1067/**
1068 * Dumps the IOTLB entry via the debug info helper.
1069 *
1070 * @returns VINF_SUCCESS.
1071 * @param pNode Pointer to an IOTLB entry to dump info.
1072 * @param pvUser Pointer to an IOTLBEINFOARG.
1073 */
1074static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1075{
1076 /* Validate. */
1077 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1078 AssertPtr(pArgs);
1079 AssertPtr(pArgs->pIommuR3);
1080 AssertPtr(pArgs->pHlp);
1081 //Assert(pArgs->pIommuCC->u32Magic == IOMMU_MAGIC);
1082
1083 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1084 if (idDomain == pArgs->idDomain)
1085 {
1086 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1087 AVLU64KEY const uKey = pIotlbe->Core.Key;
1088 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1089 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1090 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1091 size_t const cbPage = RT_BIT_64(cShift);
1092 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1093 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1094 bool const fEvictPending = pIotlbe->fEvictPending;
1095
1096 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1097 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1098 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1099 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1100 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1101 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1102 }
1103
1104 return VINF_SUCCESS;
1105}
1106# endif /* IN_RING3 */
1107
1108
1109/**
1110 * Removes the IOTLB entry if it's associated with the specified domain ID.
1111 *
1112 * @returns VINF_SUCCESS.
1113 * @param pNode Pointer to an IOTLBE.
1114 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1115 */
1116static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1117{
1118 /* Validate. */
1119 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1120 AssertPtr(pArgs);
1121 AssertPtr(pArgs->pIommuR3);
1122 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1123
1124 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1125 if (idDomain == pArgs->idDomain)
1126 {
1127 /* Mark this entry is as invalidated and needs to be evicted later. */
1128 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1129 pIotlbe->fEvictPending = true;
1130 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1131 }
1132 return VINF_SUCCESS;
1133}
1134
1135
1136/**
1137 * Inserts an IOTLB entry into the cache.
1138 *
1139 * @param pThis The shared IOMMU device state.
1140 * @param pThisR3 The ring-3 IOMMU device state.
1141 * @param pIotlbe The IOTLB entry to initialize and insert.
1142 * @param idDomain The domain ID.
1143 * @param uIova The I/O virtual address.
1144 * @param pPageLookup The I/O page lookup result of the access.
1145 */
1146static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1147 PCIOPAGELOOKUP pPageLookup)
1148{
1149 /* Initialize the IOTLB entry with results of the I/O page walk. */
1150 pIotlbe->Core.Key = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1151 pIotlbe->PageLookup = *pPageLookup;
1152
1153 /* Validate. */
1154 Assert(pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL);
1155 Assert(!pIotlbe->fEvictPending);
1156
1157 /* Check if the entry already exists. */
1158 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, pIotlbe->Core.Key);
1159 if (!pFound)
1160 {
1161 /* Insert the entry into the cache. */
1162 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1163 Assert(fInserted); NOREF(fInserted);
1164 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1165 ++pThisR3->cCachedIotlbes;
1166 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1167 }
1168 else
1169 {
1170 /* Update the existing entry. */
1171 if (pFound->fEvictPending)
1172 {
1173 pFound->fEvictPending = false;
1174 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1175 }
1176 Assert(pFound->PageLookup.cShift == pPageLookup->cShift);
1177 pFound->PageLookup.fPerm = pPageLookup->fPerm;
1178 pFound->PageLookup.GCPhysSpa = pPageLookup->GCPhysSpa;
1179 }
1180}
1181
1182
1183/**
1184 * Removes an IOTLB entry from the cache for the given key.
1185 *
1186 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1187 * the tree.
1188 * @param pThis The shared IOMMU device state.
1189 * @param pThisR3 The ring-3 IOMMU device state.
1190 * @param uKey The key of the IOTLB entry to remove.
1191 */
1192static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1193{
1194 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1195 if (pIotlbe)
1196 {
1197 if (pIotlbe->fEvictPending)
1198 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1199
1200 RT_ZERO(pIotlbe->Core);
1201 RT_ZERO(pIotlbe->PageLookup);
1202 /* We must not erase the LRU node connections here! */
1203 pIotlbe->fEvictPending = false;
1204 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1205
1206 Assert(pThisR3->cCachedIotlbes > 0);
1207 --pThisR3->cCachedIotlbes;
1208 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1209 }
1210 return pIotlbe;
1211}
1212
1213
1214/**
1215 * Looks up an IOTLB from the cache.
1216 *
1217 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1218 * @param pThis The shared IOMMU device state.
1219 * @param pThisR3 The ring-3 IOMMU device state.
1220 * @param idDomain The domain ID.
1221 * @param uIova The I/O virtual address.
1222 */
1223static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1224{
1225 RT_NOREF(pThis);
1226
1227 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1228 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1229 if ( pIotlbe
1230 && !pIotlbe->fEvictPending)
1231 return pIotlbe;
1232
1233 /*
1234 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1235 * them from the cache immediately. We found an entry pending eviction, just return that
1236 * nothing was found (rather than evicting now).
1237 */
1238 return NULL;
1239}
1240
1241
1242/**
1243 * Adds an IOTLB entry to the cache.
1244 *
1245 * @param pThis The shared IOMMU device state.
1246 * @param pThisR3 The ring-3 IOMMU device state.
1247 * @param idDomain The domain ID.
1248 * @param uIova The I/O virtual address.
1249 * @param pPageLookup The I/O page lookup result of the access.
1250 */
1251static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIova, PCIOPAGELOOKUP pPageLookup)
1252{
1253 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1254 Assert(pPageLookup);
1255 Assert(pPageLookup->cShift <= 31);
1256 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1257
1258 /*
1259 * If there are no unused IOTLB entries, evict the LRU entry.
1260 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1261 */
1262 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1263 {
1264 /* Grab the least recently used entry. */
1265 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1266 Assert(pIotlbe);
1267
1268 /* If the entry is in the cache, remove it. */
1269 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1270 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1271
1272 /* Initialize and insert the IOTLB entry into the cache. */
1273 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1274
1275 /* Move the entry to the most recently used slot. */
1276 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1277 }
1278 else
1279 {
1280 /* Grab an unused IOTLB entry from the pre-allocated list. */
1281 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1282 ++pThisR3->idxUnusedIotlbe;
1283
1284 /* Initialize and insert the IOTLB entry into the cache. */
1285 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1286
1287 /* Add the entry to the most recently used slot. */
1288 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1289 }
1290}
1291
1292
1293/**
1294 * Removes all IOTLB entries from the cache.
1295 *
1296 * @param pDevIns The IOMMU instance data.
1297 */
1298static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1299{
1300 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1301 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1302 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1303
1304 if (pThisR3->cCachedIotlbes > 0)
1305 {
1306 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
1307 RT_BZERO(pThisR3->paIotlbes, cbIotlbes);
1308 pThisR3->idxUnusedIotlbe = 0;
1309 pThisR3->cCachedIotlbes = 0;
1310 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1311 RTListInit(&pThisR3->LstLruIotlbe);
1312 }
1313
1314 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1315}
1316
1317
1318/**
1319 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1320 * domain ID from the cache.
1321 *
1322 * @param pDevIns The IOMMU instance data.
1323 * @param idDomain The domain ID.
1324 * @param uIova The I/O virtual address to invalidate.
1325 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1326 */
1327static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1328{
1329 /* Validate. */
1330 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1331 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1332 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1333
1334 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1335 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1336 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1337
1338 do
1339 {
1340 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1341 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1342 if (pIotlbe)
1343 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1344 uIova += X86_PAGE_4K_SIZE;
1345 cbInvalidate -= X86_PAGE_4K_SIZE;
1346 } while (cbInvalidate > 0);
1347
1348 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1349}
1350
1351
1352/**
1353 * Removes all IOTLB entries for the specified domain ID.
1354 *
1355 * @param pDevIns The IOMMU instance data.
1356 * @param idDomain The domain ID.
1357 */
1358static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1359{
1360 /*
1361 * We need to iterate the tree and search based on the domain ID.
1362 * But it seems we cannot remove items while iterating the tree.
1363 * Thus, we simply mark entries for eviction later but move them to the LRU
1364 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1365 */
1366 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1367 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1368 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1369
1370 IOTLBEFLUSHARG Args;
1371 Args.pIommuR3 = pThisR3;
1372 Args.idDomain = idDomain;
1373 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1374
1375 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1376}
1377
1378
1379/**
1380 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1381 *
1382 * @param pDevIns The IOMMU instance data.
1383 * @param idDomain The domain ID.
1384 * @param uIova The I/O virtual address.
1385 * @param cbIova The size of the access (must be 4K aligned).
1386 * @param GCPhysSpa The translated system-physical address.
1387 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
1388 */
1389static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbIova, RTGCPHYS GCPhysSpa,
1390 uint8_t fPerm)
1391{
1392 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1393 Assert(!(GCPhysSpa & X86_PAGE_4K_OFFSET_MASK));
1394 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1395 Assert(cbIova >= X86_PAGE_4K_SIZE);
1396
1397 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1398 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1399
1400 /* Add IOTLB entries for every page in the access. */
1401 IOPAGELOOKUP PageLookup;
1402 RT_ZERO(PageLookup);
1403 PageLookup.cShift = X86_PAGE_4K_SHIFT;
1404 PageLookup.fPerm = fPerm;
1405 PageLookup.GCPhysSpa = GCPhysSpa;
1406
1407 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1408 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1409
1410 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1411 /** @todo Re-check DTE cache? */
1412 do
1413 {
1414 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIova, &PageLookup);
1415 uIova += X86_PAGE_4K_SIZE;
1416 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1417 --cPages;
1418 } while (cPages > 0);
1419 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1420}
1421#endif /* IOMMU_WITH_IOTLBE_CACHE */
1422
1423
1424#ifdef IOMMU_WITH_IRTE_CACHE
1425/**
1426 * Looks up an IRTE cache entry.
1427 *
1428 * @returns Index of the found entry, or cache capacity if not found.
1429 * @param pThis The shared IOMMU device state.
1430 * @param idDevice The device ID (bus, device, function).
1431 * @param offIrte The offset into the interrupt remap table.
1432 */
1433static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1434{
1435 /** @todo Consider sorting and binary search when the cache capacity grows.
1436 * For the IRTE cache this should be okay since typically guests do not alter the
1437 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1438 * often. */
1439 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1440 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1441 for (uint16_t i = 0; i < cIrteCache; i++)
1442 if (pThis->aIrteCache[i].uKey == uKey)
1443 return i;
1444 return cIrteCache;
1445}
1446
1447
1448/**
1449 * Gets a free/unused IRTE cache entry.
1450 *
1451 * @returns The index of an unused entry, or cache capacity if the cache is full.
1452 * @param pThis The shared IOMMU device state.
1453 */
1454static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1455{
1456 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1457 for (uint16_t i = 0; i < cIrteCache; i++)
1458 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1459 {
1460 Assert(!pThis->aIrteCache[i].Irte.u32);
1461 return i;
1462 }
1463 return cIrteCache;
1464}
1465
1466
1467/**
1468 * Looks up the IRTE cache for the given MSI.
1469 *
1470 * @returns VBox status code.
1471 * @param pDevIns The IOMMU instance data.
1472 * @param idDevice The device ID (bus, device, function).
1473 * @param enmOp The IOMMU operation being performed.
1474 * @param pMsiIn The source MSI.
1475 * @param pMsiOut Where to store the remapped MSI.
1476 */
1477static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1478{
1479 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1480
1481 int rc = VERR_NOT_FOUND;
1482 /* Deal with such cases in the slower/fallback path. */
1483 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1484 { /* likely */ }
1485 else
1486 return rc;
1487
1488 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1489 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1490
1491 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1492 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1493 {
1494 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1495 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1496 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1497 {
1498 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1499
1500 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1501 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1502 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1503 {
1504 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1505 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1506 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1507 {
1508 /* Interrupt table length has been verified prior to adding entries to the cache. */
1509 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1510 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1511 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1512 {
1513 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1514 Assert(pIrte->n.u1RemapEnable);
1515 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1516 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1517 rc = VINF_SUCCESS;
1518 }
1519 }
1520 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1521 {
1522 *pMsiOut = *pMsiIn;
1523 rc = VINF_SUCCESS;
1524 }
1525 }
1526 }
1527 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1528 {
1529 *pMsiOut = *pMsiIn;
1530 rc = VINF_SUCCESS;
1531 }
1532 }
1533
1534 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1535 return rc;
1536}
1537
1538
1539/**
1540 * Adds or updates the IRTE cache for the given IRTE.
1541 *
1542 * @returns VBox status code.
1543 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1544 *
1545 * @param pDevIns The IOMMU instance data.
1546 * @param idDevice The device ID (bus, device, function).
1547 * @param offIrte The offset into the interrupt remap table.
1548 * @param pIrte The IRTE to cache.
1549 */
1550static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1551{
1552 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1553
1554 int rc = VINF_SUCCESS;
1555 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1556 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1557
1558 /* Find an existing entry or get an unused slot. */
1559 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1560 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1561 if ( idxIrteCache < cIrteCache
1562 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1563 {
1564 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1565 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1566 }
1567 else
1568 rc = VERR_OUT_OF_RESOURCES;
1569
1570 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1571 return rc;
1572}
1573
1574
1575# ifdef IN_RING3
1576/**
1577 * Removes IRTE cache entries for the given device ID.
1578 *
1579 * @param pDevIns The IOMMU instance data.
1580 * @param idDevice The device ID (bus, device, function).
1581 */
1582static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1583{
1584 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1585 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1586 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1587 for (uint16_t i = 0; i < cIrteCache; i++)
1588 {
1589 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1590 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1591 {
1592 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1593 pIrteCache->Irte.u32 = 0;
1594 /* There could multiple IRTE entries for a device ID, continue searching. */
1595 }
1596 }
1597 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1598}
1599
1600
1601/**
1602 * Removes all IRTE cache entries.
1603 *
1604 * @param pDevIns The IOMMU instance data.
1605 */
1606static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1607{
1608 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1609 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1610 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1611 for (uint16_t i = 0; i < cIrteCache; i++)
1612 {
1613 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1614 pThis->aIrteCache[i].Irte.u32 = 0;
1615 }
1616 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1617}
1618# endif /* IN_RING3 */
1619#endif /* IOMMU_WITH_IRTE_CACHE */
1620
1621
1622/**
1623 * Atomically reads the control register without locking the IOMMU device.
1624 *
1625 * @returns The control register.
1626 * @param pThis The shared IOMMU device state.
1627 */
1628DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1629{
1630 IOMMU_CTRL_T Ctrl;
1631 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1632 return Ctrl;
1633}
1634
1635
1636/**
1637 * Returns whether MSI is enabled for the IOMMU.
1638 *
1639 * @returns Whether MSI is enabled.
1640 * @param pDevIns The IOMMU device instance.
1641 *
1642 * @note There should be a PCIDevXxx function for this.
1643 */
1644static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1645{
1646 MSI_CAP_HDR_T MsiCapHdr;
1647 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1648 return MsiCapHdr.n.u1MsiEnable;
1649}
1650
1651
1652/**
1653 * Signals a PCI target abort.
1654 *
1655 * @param pDevIns The IOMMU device instance.
1656 */
1657static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1658{
1659 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1660 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1661 PDMPciDevSetStatus(pPciDev, u16Status);
1662}
1663
1664
1665/**
1666 * Wakes up the command thread if there are commands to be processed.
1667 *
1668 * @param pDevIns The IOMMU device instance.
1669 *
1670 * @remarks The IOMMU lock must be held while calling this!
1671 */
1672static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1673{
1674 Log4Func(("\n"));
1675
1676 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1677 if ( pThis->Status.n.u1CmdBufRunning
1678 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1679 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1680 {
1681 Log4Func(("Signaling command thread\n"));
1682 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1683 }
1684}
1685
1686
1687/**
1688 * Reads the Device Table Base Address Register.
1689 */
1690static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1691{
1692 RT_NOREF(pDevIns, offReg);
1693 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1694 return VINF_SUCCESS;
1695}
1696
1697
1698/**
1699 * Reads the Command Buffer Base Address Register.
1700 */
1701static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1702{
1703 RT_NOREF(pDevIns, offReg);
1704 *pu64Value = pThis->CmdBufBaseAddr.u64;
1705 return VINF_SUCCESS;
1706}
1707
1708
1709/**
1710 * Reads the Event Log Base Address Register.
1711 */
1712static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1713{
1714 RT_NOREF(pDevIns, offReg);
1715 *pu64Value = pThis->EvtLogBaseAddr.u64;
1716 return VINF_SUCCESS;
1717}
1718
1719
1720/**
1721 * Reads the Control Register.
1722 */
1723static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1724{
1725 RT_NOREF(pDevIns, offReg);
1726 *pu64Value = pThis->Ctrl.u64;
1727 return VINF_SUCCESS;
1728}
1729
1730
1731/**
1732 * Reads the Exclusion Range Base Address Register.
1733 */
1734static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1735{
1736 RT_NOREF(pDevIns, offReg);
1737 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1738 return VINF_SUCCESS;
1739}
1740
1741
1742/**
1743 * Reads to the Exclusion Range Limit Register.
1744 */
1745static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1746{
1747 RT_NOREF(pDevIns, offReg);
1748 *pu64Value = pThis->ExclRangeLimit.u64;
1749 return VINF_SUCCESS;
1750}
1751
1752
1753/**
1754 * Reads to the Extended Feature Register.
1755 */
1756static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1757{
1758 RT_NOREF(pDevIns, offReg);
1759 *pu64Value = pThis->ExtFeat.u64;
1760 return VINF_SUCCESS;
1761}
1762
1763
1764/**
1765 * Reads to the PPR Log Base Address Register.
1766 */
1767static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1768{
1769 RT_NOREF(pDevIns, offReg);
1770 *pu64Value = pThis->PprLogBaseAddr.u64;
1771 return VINF_SUCCESS;
1772}
1773
1774
1775/**
1776 * Writes the Hardware Event Register (Hi).
1777 */
1778static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1779{
1780 RT_NOREF(pDevIns, offReg);
1781 *pu64Value = pThis->HwEvtHi.u64;
1782 return VINF_SUCCESS;
1783}
1784
1785
1786/**
1787 * Reads the Hardware Event Register (Lo).
1788 */
1789static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1790{
1791 RT_NOREF(pDevIns, offReg);
1792 *pu64Value = pThis->HwEvtLo;
1793 return VINF_SUCCESS;
1794}
1795
1796
1797/**
1798 * Reads the Hardware Event Status Register.
1799 */
1800static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1801{
1802 RT_NOREF(pDevIns, offReg);
1803 *pu64Value = pThis->HwEvtStatus.u64;
1804 return VINF_SUCCESS;
1805}
1806
1807
1808/**
1809 * Reads to the GA Log Base Address Register.
1810 */
1811static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1812{
1813 RT_NOREF(pDevIns, offReg);
1814 *pu64Value = pThis->GALogBaseAddr.u64;
1815 return VINF_SUCCESS;
1816}
1817
1818
1819/**
1820 * Reads to the PPR Log B Base Address Register.
1821 */
1822static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1823{
1824 RT_NOREF(pDevIns, offReg);
1825 *pu64Value = pThis->PprLogBBaseAddr.u64;
1826 return VINF_SUCCESS;
1827}
1828
1829
1830/**
1831 * Reads to the Event Log B Base Address Register.
1832 */
1833static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1834{
1835 RT_NOREF(pDevIns, offReg);
1836 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1837 return VINF_SUCCESS;
1838}
1839
1840
1841/**
1842 * Reads the Device Table Segment Base Address Register.
1843 */
1844static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1845{
1846 RT_NOREF(pDevIns);
1847
1848 /* Figure out which segment is being written. */
1849 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1850 uint8_t const idxSegment = offSegment + 1;
1851 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1852
1853 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1854 return VINF_SUCCESS;
1855}
1856
1857
1858/**
1859 * Reads the Device Specific Feature Extension (DSFX) Register.
1860 */
1861static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1862{
1863 RT_NOREF(pDevIns, offReg);
1864 *pu64Value = pThis->DevSpecificFeat.u64;
1865 return VINF_SUCCESS;
1866}
1867
1868/**
1869 * Reads the Device Specific Control Extension (DSCX) Register.
1870 */
1871static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1872{
1873 RT_NOREF(pDevIns, offReg);
1874 *pu64Value = pThis->DevSpecificCtrl.u64;
1875 return VINF_SUCCESS;
1876}
1877
1878
1879/**
1880 * Reads the Device Specific Status Extension (DSSX) Register.
1881 */
1882static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1883{
1884 RT_NOREF(pDevIns, offReg);
1885 *pu64Value = pThis->DevSpecificStatus.u64;
1886 return VINF_SUCCESS;
1887}
1888
1889
1890/**
1891 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1892 */
1893static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1894{
1895 RT_NOREF(pDevIns, offReg);
1896 uint32_t const uLo = pThis->MiscInfo.au32[0];
1897 uint32_t const uHi = pThis->MiscInfo.au32[1];
1898 *pu64Value = RT_MAKE_U64(uLo, uHi);
1899 return VINF_SUCCESS;
1900}
1901
1902
1903/**
1904 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1905 * Register (32-bit).
1906 */
1907static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1908{
1909 RT_NOREF(pThis, offReg);
1910 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1911 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1912 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1913 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1914 *pu64Value = RT_MAKE_U64(uLo, uHi);
1915 return VINF_SUCCESS;
1916}
1917
1918
1919/**
1920 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1921 */
1922static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1923{
1924 RT_NOREF(pThis, offReg);
1925 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1926 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1927 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1928 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1929 *pu64Value = RT_MAKE_U64(uLo, uHi);
1930 return VINF_SUCCESS;
1931}
1932
1933
1934/**
1935 * Reads the Command Buffer Head Pointer Register.
1936 */
1937static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1938{
1939 RT_NOREF(pDevIns, offReg);
1940 *pu64Value = pThis->CmdBufHeadPtr.u64;
1941 return VINF_SUCCESS;
1942}
1943
1944
1945/**
1946 * Reads the Command Buffer Tail Pointer Register.
1947 */
1948static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1949{
1950 RT_NOREF(pDevIns, offReg);
1951 *pu64Value = pThis->CmdBufTailPtr.u64;
1952 return VINF_SUCCESS;
1953}
1954
1955
1956/**
1957 * Reads the Event Log Head Pointer Register.
1958 */
1959static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1960{
1961 RT_NOREF(pDevIns, offReg);
1962 *pu64Value = pThis->EvtLogHeadPtr.u64;
1963 return VINF_SUCCESS;
1964}
1965
1966
1967/**
1968 * Reads the Event Log Tail Pointer Register.
1969 */
1970static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1971{
1972 RT_NOREF(pDevIns, offReg);
1973 *pu64Value = pThis->EvtLogTailPtr.u64;
1974 return VINF_SUCCESS;
1975}
1976
1977
1978/**
1979 * Reads the Status Register.
1980 */
1981static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1982{
1983 RT_NOREF(pDevIns, offReg);
1984 *pu64Value = pThis->Status.u64;
1985 return VINF_SUCCESS;
1986}
1987
1988
1989/**
1990 * Writes the Device Table Base Address Register.
1991 */
1992static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1993{
1994 RT_NOREF(pDevIns, offReg);
1995
1996 /* Mask out all unrecognized bits. */
1997 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
1998
1999 /* Update the register. */
2000 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2001
2002 /* Paranoia. */
2003 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
2004 return VINF_SUCCESS;
2005}
2006
2007
2008/**
2009 * Writes the Command Buffer Base Address Register.
2010 */
2011static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2012{
2013 RT_NOREF(pDevIns, offReg);
2014
2015 /*
2016 * While this is not explicitly specified like the event log base address register,
2017 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2018 * Inconsistent specs :/
2019 */
2020 if (pThis->Status.n.u1CmdBufRunning)
2021 {
2022 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2023 return VINF_SUCCESS;
2024 }
2025
2026 /* Mask out all unrecognized bits. */
2027 CMD_BUF_BAR_T CmdBufBaseAddr;
2028 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2029
2030 /* Validate the length. */
2031 if (CmdBufBaseAddr.n.u4Len >= 8)
2032 {
2033 /* Update the register. */
2034 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2035
2036 /*
2037 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2038 * See AMD IOMMU spec. 2.4 "Commands".
2039 */
2040 pThis->CmdBufHeadPtr.u64 = 0;
2041 pThis->CmdBufTailPtr.u64 = 0;
2042 }
2043 else
2044 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2045
2046 return VINF_SUCCESS;
2047}
2048
2049
2050/**
2051 * Writes the Event Log Base Address Register.
2052 */
2053static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2054{
2055 RT_NOREF(pDevIns, offReg);
2056
2057 /*
2058 * IOMMU behavior is undefined when software writes this register when event logging is running.
2059 * In our emulation, we ignore the write entirely.
2060 * See AMD IOMMU spec. "Event Log Base Address Register".
2061 */
2062 if (pThis->Status.n.u1EvtLogRunning)
2063 {
2064 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2065 return VINF_SUCCESS;
2066 }
2067
2068 /* Mask out all unrecognized bits. */
2069 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2070 EVT_LOG_BAR_T EvtLogBaseAddr;
2071 EvtLogBaseAddr.u64 = u64Value;
2072
2073 /* Validate the length. */
2074 if (EvtLogBaseAddr.n.u4Len >= 8)
2075 {
2076 /* Update the register. */
2077 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2078
2079 /*
2080 * Writing the event log base address, clears the event log head and tail pointers.
2081 * See AMD IOMMU spec. 2.5 "Event Logging".
2082 */
2083 pThis->EvtLogHeadPtr.u64 = 0;
2084 pThis->EvtLogTailPtr.u64 = 0;
2085 }
2086 else
2087 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2088
2089 return VINF_SUCCESS;
2090}
2091
2092
2093/**
2094 * Writes the Control Register.
2095 */
2096static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2097{
2098 RT_NOREF(pDevIns, offReg);
2099
2100 /* Mask out all unrecognized bits. */
2101 u64Value &= IOMMU_CTRL_VALID_MASK;
2102 IOMMU_CTRL_T NewCtrl;
2103 NewCtrl.u64 = u64Value;
2104
2105 /* Ensure the device table segments are within limits. */
2106 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2107 {
2108 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2109
2110 /* Update the register. */
2111 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2112
2113 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2114 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2115
2116 /* Enable or disable event logging when the bit transitions. */
2117 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2118 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2119 if ( fOldEvtLogEn != fNewEvtLogEn
2120 || fOldIommuEn != fNewIommuEn)
2121 {
2122 if ( fNewIommuEn
2123 && fNewEvtLogEn)
2124 {
2125 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2126 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2127 }
2128 else
2129 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2130 }
2131
2132 /* Enable or disable command buffer processing when the bit transitions. */
2133 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2134 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2135 if ( fOldCmdBufEn != fNewCmdBufEn
2136 || fOldIommuEn != fNewIommuEn)
2137 {
2138 if ( fNewCmdBufEn
2139 && fNewIommuEn)
2140 {
2141 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2142 LogFunc(("Command buffer enabled\n"));
2143
2144 /* Wake up the command thread to start processing commands if any. */
2145 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2146 }
2147 else
2148 {
2149 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2150 LogFunc(("Command buffer disabled\n"));
2151 }
2152 }
2153 }
2154 else
2155 {
2156 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2157 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2158 }
2159
2160 return VINF_SUCCESS;
2161}
2162
2163
2164/**
2165 * Writes to the Exclusion Range Base Address Register.
2166 */
2167static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2168{
2169 RT_NOREF(pDevIns, offReg);
2170 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2171 return VINF_SUCCESS;
2172}
2173
2174
2175/**
2176 * Writes to the Exclusion Range Limit Register.
2177 */
2178static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2179{
2180 RT_NOREF(pDevIns, offReg);
2181 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2182 u64Value |= UINT64_C(0xfff);
2183 pThis->ExclRangeLimit.u64 = u64Value;
2184 return VINF_SUCCESS;
2185}
2186
2187
2188/**
2189 * Writes the Hardware Event Register (Hi).
2190 */
2191static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2192{
2193 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2194 RT_NOREF(pDevIns, offReg);
2195 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2196 pThis->HwEvtHi.u64 = u64Value;
2197 return VINF_SUCCESS;
2198}
2199
2200
2201/**
2202 * Writes the Hardware Event Register (Lo).
2203 */
2204static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2205{
2206 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2207 RT_NOREF(pDevIns, offReg);
2208 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2209 pThis->HwEvtLo = u64Value;
2210 return VINF_SUCCESS;
2211}
2212
2213
2214/**
2215 * Writes the Hardware Event Status Register.
2216 */
2217static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2218{
2219 RT_NOREF(pDevIns, offReg);
2220
2221 /* Mask out all unrecognized bits. */
2222 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2223
2224 /*
2225 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2226 * If the current status bits or the bits being written are both 0, we've nothing to do.
2227 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2228 */
2229 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2230 if (!(HwStatus & RT_BIT(0)))
2231 return VINF_SUCCESS;
2232 if (u64Value & HwStatus & RT_BIT_64(0))
2233 HwStatus &= ~RT_BIT_64(0);
2234 if (u64Value & HwStatus & RT_BIT_64(1))
2235 HwStatus &= ~RT_BIT_64(1);
2236
2237 /* Update the register. */
2238 pThis->HwEvtStatus.u64 = HwStatus;
2239 return VINF_SUCCESS;
2240}
2241
2242
2243/**
2244 * Writes the Device Table Segment Base Address Register.
2245 */
2246static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2247{
2248 RT_NOREF(pDevIns);
2249
2250 /* Figure out which segment is being written. */
2251 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2252 uint8_t const idxSegment = offSegment + 1;
2253 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2254
2255 /* Mask out all unrecognized bits. */
2256 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2257 DEV_TAB_BAR_T DevTabSegBar;
2258 DevTabSegBar.u64 = u64Value;
2259
2260 /* Validate the size. */
2261 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2262 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2263 if (uSegSize <= uMaxSegSize)
2264 {
2265 /* Update the register. */
2266 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2267 }
2268 else
2269 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2270
2271 return VINF_SUCCESS;
2272}
2273
2274
2275/**
2276 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2277 */
2278static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2279{
2280 RT_NOREF(pDevIns, offReg);
2281
2282 /* MSI Vector Register 0 is read-only. */
2283 /* MSI Vector Register 1. */
2284 uint32_t const uReg = u64Value >> 32;
2285 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2286 return VINF_SUCCESS;
2287}
2288
2289
2290/**
2291 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2292 * Register (32-bit).
2293 */
2294static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2295{
2296 RT_NOREF(pThis, offReg);
2297 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2298 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2299
2300 /* MSI capability header. */
2301 {
2302 uint32_t const uReg = u64Value;
2303 MSI_CAP_HDR_T MsiCapHdr;
2304 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2305 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2306 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2307 }
2308
2309 /* MSI Address Lo. */
2310 {
2311 uint32_t const uReg = u64Value >> 32;
2312 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2313 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2314 }
2315
2316 return VINF_SUCCESS;
2317}
2318
2319
2320/**
2321 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2322 */
2323static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2324{
2325 RT_NOREF(pThis, offReg);
2326 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2327 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2328
2329 /* MSI Address Hi. */
2330 {
2331 uint32_t const uReg = u64Value;
2332 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2333 }
2334
2335 /* MSI Data. */
2336 {
2337 uint32_t const uReg = u64Value >> 32;
2338 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2339 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2340 }
2341
2342 return VINF_SUCCESS;
2343}
2344
2345
2346/**
2347 * Writes the Command Buffer Head Pointer Register.
2348 */
2349static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2350{
2351 RT_NOREF(pDevIns, offReg);
2352
2353 /*
2354 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2355 * In our emulation, we ignore the write entirely.
2356 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2357 */
2358 if (pThis->Status.n.u1CmdBufRunning)
2359 {
2360 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2361 return VINF_SUCCESS;
2362 }
2363
2364 /*
2365 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2366 * In our emulation, we ignore the write entirely.
2367 */
2368 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2369 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2370 Assert(cbBuf <= _512K);
2371 if (offBuf >= cbBuf)
2372 {
2373 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2374 return VINF_SUCCESS;
2375 }
2376
2377 /* Update the register. */
2378 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2379
2380 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2381
2382 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2383 return VINF_SUCCESS;
2384}
2385
2386
2387/**
2388 * Writes the Command Buffer Tail Pointer Register.
2389 */
2390static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2391{
2392 RT_NOREF(pDevIns, offReg);
2393
2394 /*
2395 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2396 * In our emulation, we ignore the write entirely.
2397 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2398 */
2399 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2400 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2401 Assert(cbBuf <= _512K);
2402 if (offBuf >= cbBuf)
2403 {
2404 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2405 return VINF_SUCCESS;
2406 }
2407
2408 /*
2409 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2410 * head pointer after adding one or more commands to the buffer.
2411 *
2412 * However, we cannot enforce this strictly because it's legal for software to shrink the
2413 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2414 * at 0). Software might even make the queue empty by making head and tail equal which is
2415 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2416 * in the foot here. As long as we make sure the offset value is within the circular buffer
2417 * bounds (which we do by masking bits above) it should be sufficient.
2418 */
2419 pThis->CmdBufTailPtr.au32[0] = offBuf;
2420
2421 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2422
2423 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2424 return VINF_SUCCESS;
2425}
2426
2427
2428/**
2429 * Writes the Event Log Head Pointer Register.
2430 */
2431static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2432{
2433 RT_NOREF(pDevIns, offReg);
2434
2435 /*
2436 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2437 * In our emulation, we ignore the write entirely.
2438 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2439 */
2440 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2441 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2442 Assert(cbBuf <= _512K);
2443 if (offBuf >= cbBuf)
2444 {
2445 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2446 return VINF_SUCCESS;
2447 }
2448
2449 /* Update the register. */
2450 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2451
2452 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2453 return VINF_SUCCESS;
2454}
2455
2456
2457/**
2458 * Writes the Event Log Tail Pointer Register.
2459 */
2460static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2461{
2462 RT_NOREF(pDevIns, offReg);
2463 NOREF(pThis);
2464
2465 /*
2466 * IOMMU behavior is undefined when software writes this register when the event log is running.
2467 * In our emulation, we ignore the write entirely.
2468 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2469 */
2470 if (pThis->Status.n.u1EvtLogRunning)
2471 {
2472 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2473 return VINF_SUCCESS;
2474 }
2475
2476 /*
2477 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2478 * In our emulation, we ignore the write entirely.
2479 */
2480 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2481 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2482 Assert(cbBuf <= _512K);
2483 if (offBuf >= cbBuf)
2484 {
2485 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2486 return VINF_SUCCESS;
2487 }
2488
2489 /* Update the register. */
2490 pThis->EvtLogTailPtr.au32[0] = offBuf;
2491
2492 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2493 return VINF_SUCCESS;
2494}
2495
2496
2497/**
2498 * Writes the Status Register.
2499 */
2500static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2501{
2502 RT_NOREF(pDevIns, offReg);
2503
2504 /* Mask out all unrecognized bits. */
2505 u64Value &= IOMMU_STATUS_VALID_MASK;
2506
2507 /*
2508 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2509 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2510 */
2511 IOMMU_STATUS_T const OldStatus = pThis->Status;
2512 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2513 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2514 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2515
2516 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2517
2518 /* Update the register. */
2519 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2520 return VINF_SUCCESS;
2521}
2522
2523
2524/**
2525 * Register access table 0.
2526 * The MMIO offset of each entry must be a multiple of 8!
2527 */
2528static const IOMMUREGACC g_aRegAccess0[] =
2529{
2530 /* MMIO off. Register name Read function Write function */
2531 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2532 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2533 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2534 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2535 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2536 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2537 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2538 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2539 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2540 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2541 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2542 { /* 0x58 */ NULL, NULL, NULL },
2543
2544 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2545 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2546 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2547 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2548 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2549 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2550 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2551 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2552 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2553 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2554 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2555 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2556 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2557 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2558 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2559 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2560
2561 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2562 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2563 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2564 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2565
2566 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2567 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2568 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2569 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2570 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2571 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2572 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2573
2574 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2575 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2576 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2577
2578 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2579 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2580 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2581 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2582
2583 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2584 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2585 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2586};
2587AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2588
2589/**
2590 * Register access table 1.
2591 * The MMIO offset of each entry must be a multiple of 8!
2592 */
2593static const IOMMUREGACC g_aRegAccess1[] =
2594{
2595 /* MMIO offset Register name Read function Write function */
2596 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2597 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2598 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2599 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2600 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2601 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2602 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2603 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2604 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2605 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2606 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2607 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2608};
2609AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2610
2611/**
2612 * Register access table 2.
2613 * The MMIO offset of each entry must be a multiple of 8!
2614 */
2615static const IOMMUREGACC g_aRegAccess2[] =
2616{
2617 /* MMIO offset Register name Read Function Write function */
2618 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2619
2620 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2621 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2622 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2623 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2624
2625 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2626 { /* 0x2028 */ NULL, NULL, NULL },
2627
2628 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2629 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2630
2631 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2632 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2633
2634 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2635 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2636
2637 { /* 0x2060 */ NULL, NULL, NULL },
2638 { /* 0x2068 */ NULL, NULL, NULL },
2639
2640 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2641 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2642
2643 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2644 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2645 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2646};
2647AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2648
2649
2650/**
2651 * Gets the register access structure given its MMIO offset.
2652 *
2653 * @returns The register access structure, or NULL if the offset is invalid.
2654 * @param off The MMIO offset of the register being accessed.
2655 */
2656static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2657{
2658 /* Figure out which table the register belongs to and validate its index. */
2659 PCIOMMUREGACC pReg;
2660 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2661 {
2662 uint32_t const idxReg = off >> 3;
2663 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2664 pReg = &g_aRegAccess0[idxReg];
2665 }
2666 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2667 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2668 {
2669 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2670 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2671 pReg = &g_aRegAccess1[idxReg];
2672 }
2673 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2674 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2675 {
2676 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2677 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2678 pReg = &g_aRegAccess2[idxReg];
2679 }
2680 else
2681 pReg = NULL;
2682 return pReg;
2683}
2684
2685
2686/**
2687 * Writes an IOMMU register (32-bit and 64-bit).
2688 *
2689 * @returns Strict VBox status code.
2690 * @param pDevIns The IOMMU device instance.
2691 * @param off MMIO byte offset to the register.
2692 * @param cb The size of the write access.
2693 * @param uValue The value being written.
2694 *
2695 * @thread EMT.
2696 */
2697static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2698{
2699 /*
2700 * Validate the access in case of IOM bug or incorrect assumption.
2701 */
2702 Assert(off < IOMMU_MMIO_REGION_SIZE);
2703 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2704 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2705
2706 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2707
2708 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2709 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2710 if (pReg)
2711 { /* likely */ }
2712 else
2713 {
2714 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2715 return VINF_SUCCESS;
2716 }
2717
2718 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2719 if (pReg->pfnWrite)
2720 { /* likely */ }
2721 else
2722 {
2723 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2724 return VINF_SUCCESS;
2725 }
2726
2727 /*
2728 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2729 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2730 * consecutive 32-bit registers.
2731 */
2732 if (cb == 8)
2733 {
2734 if (!(off & 7))
2735 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
2736
2737 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2738 return VINF_SUCCESS;
2739 }
2740
2741 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2742 Assert(cb == 4);
2743 if (!(off & 7))
2744 {
2745 /*
2746 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2747 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2748 */
2749 uint64_t u64Read;
2750 if (pReg->pfnRead)
2751 {
2752 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2753 if (RT_FAILURE(rcStrict))
2754 {
2755 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2756 return rcStrict;
2757 }
2758 }
2759 else
2760 u64Read = 0;
2761
2762 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2763 return pReg->pfnWrite(pDevIns, pThis, off, uValue);
2764 }
2765
2766 /*
2767 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2768 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2769 */
2770 Assert(!(off & 3));
2771 Assert(off & 7);
2772 Assert(off >= 4);
2773 uint64_t u64Read;
2774 if (pReg->pfnRead)
2775 {
2776 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2777 if (RT_FAILURE(rcStrict))
2778 {
2779 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2780 return rcStrict;
2781 }
2782 }
2783 else
2784 u64Read = 0;
2785
2786 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2787 return pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2788}
2789
2790
2791/**
2792 * Reads an IOMMU register (64-bit) given its MMIO offset.
2793 *
2794 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2795 * boundary include the lower half of the subsequent register.
2796 *
2797 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2798 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2799 * software will only perform 32-bit reads on those 32-bit registers that are
2800 * aligned on 8-byte boundaries.
2801 *
2802 * @returns Strict VBox status code.
2803 * @param pDevIns The IOMMU device instance.
2804 * @param off The MMIO offset of the register in bytes.
2805 * @param puResult Where to store the value being read.
2806 *
2807 * @thread EMT.
2808 */
2809static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2810{
2811 Assert(off < IOMMU_MMIO_REGION_SIZE);
2812 Assert(!(off & 7) || !(off & 3));
2813
2814 Log4Func(("off=%#x\n", off));
2815
2816 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2817 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2818 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2819
2820 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2821 if (pReg)
2822 { /* likely */ }
2823 else
2824 {
2825 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2826 return VINF_IOM_MMIO_UNUSED_FF;
2827 }
2828
2829 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2830 if (pReg->pfnRead)
2831 { /* likely */ }
2832 else
2833 {
2834 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2835 return VINF_IOM_MMIO_UNUSED_00;
2836 }
2837
2838 /*
2839 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2840 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2841 */
2842 if (!(off & 7))
2843 return pReg->pfnRead(pDevIns, pThis, off, puResult);
2844
2845 /*
2846 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2847 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2848 */
2849 Assert(!(off & 3));
2850 Assert(off & 7);
2851 Assert(off >= 4);
2852 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2853 if (RT_SUCCESS(rcStrict))
2854 *puResult >>= 32;
2855 else
2856 {
2857 *puResult = 0;
2858 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2859 }
2860
2861 return rcStrict;
2862}
2863
2864
2865/**
2866 * Raises the MSI interrupt for the IOMMU device.
2867 *
2868 * @param pDevIns The IOMMU device instance.
2869 *
2870 * @thread Any.
2871 * @remarks The IOMMU lock may or may not be held.
2872 */
2873static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2874{
2875 LogFlowFunc(("\n"));
2876 if (iommuAmdIsMsiEnabled(pDevIns))
2877 {
2878 LogFunc(("Raising MSI\n"));
2879 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2880 }
2881}
2882
2883#if 0
2884/**
2885 * Clears the MSI interrupt for the IOMMU device.
2886 *
2887 * @param pDevIns The IOMMU device instance.
2888 *
2889 * @thread Any.
2890 * @remarks The IOMMU lock may or may not be held.
2891 */
2892static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2893{
2894 if (iommuAmdIsMsiEnabled(pDevIns))
2895 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2896}
2897#endif
2898
2899/**
2900 * Writes an entry to the event log in memory.
2901 *
2902 * @returns VBox status code.
2903 * @param pDevIns The IOMMU device instance.
2904 * @param pEvent The event to log.
2905 *
2906 * @thread Any.
2907 * @remarks The IOMMU lock must be held while calling this function.
2908 */
2909static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2910{
2911 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2912 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2913
2914 IOMMU_LOCK_NORET(pDevIns, pThisCC);
2915
2916 /* Check if event logging is active and the log has not overflowed. */
2917 IOMMU_STATUS_T const Status = pThis->Status;
2918 if ( Status.n.u1EvtLogRunning
2919 && !Status.n.u1EvtOverflow)
2920 {
2921 uint32_t const cbEvt = sizeof(*pEvent);
2922
2923 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2924 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2925 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2926
2927 /* Ensure we have space in the event log. */
2928 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2929 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2930 if (cEvts + 1 < cMaxEvts)
2931 {
2932 /* Write the event log entry to memory. */
2933 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2934 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2935 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2936 if (RT_FAILURE(rc))
2937 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2938
2939 /* Increment the event log tail pointer. */
2940 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2941 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2942
2943 /* Indicate that an event log entry was written. */
2944 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2945
2946 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2947 if (pThis->Ctrl.n.u1EvtIntrEn)
2948 iommuAmdMsiInterruptRaise(pDevIns);
2949 }
2950 else
2951 {
2952 /* Indicate that the event log has overflowed. */
2953 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2954
2955 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2956 if (pThis->Ctrl.n.u1EvtIntrEn)
2957 iommuAmdMsiInterruptRaise(pDevIns);
2958 }
2959 }
2960
2961 IOMMU_UNLOCK(pDevIns, pThisCC);
2962
2963 return VINF_SUCCESS;
2964}
2965
2966
2967/**
2968 * Sets an event in the hardware error registers.
2969 *
2970 * @param pDevIns The IOMMU device instance.
2971 * @param pEvent The event.
2972 *
2973 * @thread Any.
2974 */
2975static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2976{
2977 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2978 if (pThis->ExtFeat.n.u1HwErrorSup)
2979 {
2980 if (pThis->HwEvtStatus.n.u1Valid)
2981 pThis->HwEvtStatus.n.u1Overflow = 1;
2982 pThis->HwEvtStatus.n.u1Valid = 1;
2983 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
2984 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
2985 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
2986 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
2987 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
2988 }
2989}
2990
2991
2992/**
2993 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
2994 *
2995 * @param idDevice The device ID (bus, device, function).
2996 * @param idDomain The domain ID.
2997 * @param GCPhysPtEntity The system physical address of the page table
2998 * entity.
2999 * @param enmOp The IOMMU operation being performed.
3000 * @param pEvtPageTabHwErr Where to store the initialized event.
3001 */
3002static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3003 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3004{
3005 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3006 pEvtPageTabHwErr->n.u16DevId = idDevice;
3007 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3008 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3009 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3010 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3011 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3012 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3013 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3014 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3015}
3016
3017
3018/**
3019 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3020 *
3021 * @param pDevIns The IOMMU device instance.
3022 * @param enmOp The IOMMU operation being performed.
3023 * @param pEvtPageTabHwErr The page table hardware error event.
3024 *
3025 * @thread Any.
3026 */
3027static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3028{
3029 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3030 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3031
3032 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3033 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3034
3035 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3036 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3037 if (enmOp != IOMMUOP_CMD)
3038 iommuAmdSetPciTargetAbort(pDevIns);
3039
3040 IOMMU_UNLOCK(pDevIns, pThisCC);
3041
3042 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3043 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3044 pEvtPageTabHwErr->n.u2Type));
3045}
3046
3047
3048#ifdef IN_RING3
3049/**
3050 * Initializes a COMMAND_HARDWARE_ERROR event.
3051 *
3052 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3053 * @param pEvtCmdHwErr Where to store the initialized event.
3054 */
3055static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3056{
3057 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3058 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3059 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3060 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3061}
3062
3063
3064/**
3065 * Raises a COMMAND_HARDWARE_ERROR event.
3066 *
3067 * @param pDevIns The IOMMU device instance.
3068 * @param pEvtCmdHwErr The command hardware error event.
3069 *
3070 * @thread Any.
3071 */
3072static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3073{
3074 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3075 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3076 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3077
3078 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3079 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3080
3081 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3082 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3083 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3084
3085 IOMMU_UNLOCK(pDevIns, pThisCC);
3086
3087 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3088}
3089#endif /* IN_RING3 */
3090
3091
3092/**
3093 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3094 *
3095 * @param idDevice The device ID (bus, device, function).
3096 * @param GCPhysDte The system physical address of the failed device table
3097 * access.
3098 * @param enmOp The IOMMU operation being performed.
3099 * @param pEvtDevTabHwErr Where to store the initialized event.
3100 */
3101static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3102 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3103{
3104 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3105 pEvtDevTabHwErr->n.u16DevId = idDevice;
3106 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3107 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3108 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3109 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3110 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3111 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3112 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3113}
3114
3115
3116/**
3117 * Raises a DEV_TAB_HARDWARE_ERROR event.
3118 *
3119 * @param pDevIns The IOMMU device instance.
3120 * @param enmOp The IOMMU operation being performed.
3121 * @param pEvtDevTabHwErr The device table hardware error event.
3122 *
3123 * @thread Any.
3124 */
3125static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3126{
3127 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3128 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3129
3130 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3131 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3132
3133 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3134 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3135 if (enmOp != IOMMUOP_CMD)
3136 iommuAmdSetPciTargetAbort(pDevIns);
3137
3138 IOMMU_UNLOCK(pDevIns, pThisCC);
3139
3140 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3141 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3142}
3143
3144
3145#ifdef IN_RING3
3146/**
3147 * Initializes an ILLEGAL_COMMAND_ERROR event.
3148 *
3149 * @param GCPhysCmd The system physical address of the failed command
3150 * access.
3151 * @param pEvtIllegalCmd Where to store the initialized event.
3152 */
3153static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3154{
3155 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3156 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3157 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3158 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3159}
3160
3161
3162/**
3163 * Raises an ILLEGAL_COMMAND_ERROR event.
3164 *
3165 * @param pDevIns The IOMMU device instance.
3166 * @param pEvtIllegalCmd The illegal command error event.
3167 */
3168static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3169{
3170 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3171 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3172 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3173
3174 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3175 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3176
3177 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3178}
3179#endif /* IN_RING3 */
3180
3181
3182/**
3183 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3184 *
3185 * @param idDevice The device ID (bus, device, function).
3186 * @param uIova The I/O virtual address.
3187 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3188 * event was caused by an invalid level encoding in the
3189 * DTE.
3190 * @param enmOp The IOMMU operation being performed.
3191 * @param pEvtIllegalDte Where to store the initialized event.
3192 */
3193static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3194 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3195{
3196 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3197 pEvtIllegalDte->n.u16DevId = idDevice;
3198 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3199 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3200 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3201 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3202 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3203 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3204 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3205 * IOMMU spec here but not for this field for I/O page fault event. */
3206 Assert(!(uIova & UINT64_C(0x3)));
3207}
3208
3209
3210/**
3211 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3212 *
3213 * @param pDevIns The IOMMU instance data.
3214 * @param enmOp The IOMMU operation being performed.
3215 * @param pEvtIllegalDte The illegal device table entry event.
3216 * @param enmEvtType The illegal device table entry event type.
3217 *
3218 * @thread Any.
3219 */
3220static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3221 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3222{
3223 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3224 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3225
3226 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3227 if (enmOp != IOMMUOP_CMD)
3228 iommuAmdSetPciTargetAbort(pDevIns);
3229
3230 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3231 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3232 NOREF(enmEvtType);
3233}
3234
3235
3236/**
3237 * Initializes an IO_PAGE_FAULT event.
3238 *
3239 * @param idDevice The device ID (bus, device, function).
3240 * @param idDomain The domain ID.
3241 * @param uIova The I/O virtual address being accessed.
3242 * @param fPresent Transaction to a page marked as present (including
3243 * DTE.V=1) or interrupt marked as remapped
3244 * (IRTE.RemapEn=1).
3245 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3246 * the I/O page fault was caused by invalid level
3247 * encoding.
3248 * @param fPermDenied Permission denied for the address being accessed.
3249 * @param enmOp The IOMMU operation being performed.
3250 * @param pEvtIoPageFault Where to store the initialized event.
3251 */
3252static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3253 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3254{
3255 Assert(!fPermDenied || fPresent);
3256 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3257 pEvtIoPageFault->n.u16DevId = idDevice;
3258 //pEvtIoPageFault->n.u4PasidHi = 0;
3259 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3260 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3261 //pEvtIoPageFault->n.u1NoExecute = 0;
3262 //pEvtIoPageFault->n.u1User = 0;
3263 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3264 pEvtIoPageFault->n.u1Present = fPresent;
3265 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3266 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3267 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3268 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3269 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3270 pEvtIoPageFault->n.u64Addr = uIova;
3271}
3272
3273
3274/**
3275 * Raises an IO_PAGE_FAULT event.
3276 *
3277 * @param pDevIns The IOMMU instance data.
3278 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3279 * @param pIrte The interrupt remapping table entry, can be NULL.
3280 * @param enmOp The IOMMU operation being performed.
3281 * @param pEvtIoPageFault The I/O page fault event.
3282 * @param enmEvtType The I/O page fault event type.
3283 *
3284 * @thread Any.
3285 */
3286static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3287 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3288{
3289 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3290 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3291
3292#ifdef IOMMU_WITH_DTE_CACHE
3293# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheAddFlags((a_pDevIns), (a_DevId), \
3294 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED)
3295#else
3296# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3297#endif
3298
3299 bool fSuppressEvtLogging = false;
3300 if ( enmOp == IOMMUOP_MEM_READ
3301 || enmOp == IOMMUOP_MEM_WRITE)
3302 {
3303 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3304 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3305 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3306 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3307 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3308 {
3309 fSuppressEvtLogging = true;
3310 }
3311 }
3312 else if (enmOp == IOMMUOP_INTR_REQ)
3313 {
3314 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3315 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3316 fSuppressEvtLogging = true;
3317 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3318 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3319 }
3320 /* else: Events are never suppressed for commands. */
3321
3322 switch (enmEvtType)
3323 {
3324 case kIoPageFaultType_PermDenied:
3325 {
3326 /* Cannot be triggered by a command. */
3327 Assert(enmOp != IOMMUOP_CMD);
3328 RT_FALL_THRU();
3329 }
3330 case kIoPageFaultType_DteRsvdPagingMode:
3331 case kIoPageFaultType_PteInvalidPageSize:
3332 case kIoPageFaultType_PteInvalidLvlEncoding:
3333 case kIoPageFaultType_SkippedLevelIovaNotZero:
3334 case kIoPageFaultType_PteRsvdNotZero:
3335 case kIoPageFaultType_PteValidNotSet:
3336 case kIoPageFaultType_DteTranslationDisabled:
3337 case kIoPageFaultType_PasidInvalidRange:
3338 {
3339 /*
3340 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3341 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3342 */
3343 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3344 {
3345 if (!fSuppressEvtLogging)
3346 {
3347 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3348 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3349 }
3350 if (enmOp != IOMMUOP_CMD)
3351 iommuAmdSetPciTargetAbort(pDevIns);
3352 }
3353 break;
3354 }
3355
3356 case kIoPageFaultType_UserSupervisor:
3357 {
3358 /* Access is blocked and only creates an event log entry. */
3359 if (!fSuppressEvtLogging)
3360 {
3361 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3362 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3363 }
3364 break;
3365 }
3366
3367 case kIoPageFaultType_IrteAddrInvalid:
3368 case kIoPageFaultType_IrteRsvdNotZero:
3369 case kIoPageFaultType_IrteRemapEn:
3370 case kIoPageFaultType_IrteRsvdIntType:
3371 case kIoPageFaultType_IntrReqAborted:
3372 case kIoPageFaultType_IntrWithPasid:
3373 {
3374 /* Only trigerred by interrupt requests. */
3375 Assert(enmOp == IOMMUOP_INTR_REQ);
3376 if (!fSuppressEvtLogging)
3377 {
3378 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3379 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3380 }
3381 iommuAmdSetPciTargetAbort(pDevIns);
3382 break;
3383 }
3384
3385 case kIoPageFaultType_SmiFilterMismatch:
3386 {
3387 /* Not supported and probably will never be, assert. */
3388 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3389 break;
3390 }
3391
3392 case kIoPageFaultType_DevId_Invalid:
3393 {
3394 /* Cannot be triggered by a command. */
3395 Assert(enmOp != IOMMUOP_CMD);
3396 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3397 if (!fSuppressEvtLogging)
3398 {
3399 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3400 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3401 }
3402 if ( enmOp == IOMMUOP_MEM_READ
3403 || enmOp == IOMMUOP_MEM_WRITE)
3404 iommuAmdSetPciTargetAbort(pDevIns);
3405 break;
3406 }
3407 }
3408
3409#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3410}
3411
3412
3413/**
3414 * Raises an IO_PAGE_FAULT event given the DTE.
3415 *
3416 * @param pDevIns The IOMMU instance data.
3417 * @param pDte The device table entry.
3418 * @param pIrte The interrupt remapping table entry, can be NULL.
3419 * @param enmOp The IOMMU operation being performed.
3420 * @param pEvtIoPageFault The I/O page fault event.
3421 * @param enmEvtType The I/O page fault event type.
3422 *
3423 * @thread Any.
3424 */
3425static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3426 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3427{
3428 Assert(pDte);
3429 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3430 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3431}
3432
3433
3434/**
3435 * Reads a device table entry for the given the device ID.
3436 *
3437 * @returns VBox status code.
3438 * @param pDevIns The IOMMU device instance.
3439 * @param idDevice The device ID (bus, device, function).
3440 * @param enmOp The IOMMU operation being performed.
3441 * @param pDte Where to store the device table entry.
3442 *
3443 * @thread Any.
3444 */
3445static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3446{
3447 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3448 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3449
3450 IOMMU_LOCK(pDevIns, pThisCC);
3451
3452 /* Figure out which device table segment is being accessed. */
3453 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3454 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3455
3456 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3457 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3458 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3459
3460 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3461 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3462 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3463
3464 /* Ensure the DTE falls completely within the device table segment. */
3465 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3466
3467 IOMMU_UNLOCK(pDevIns, pThisCC);
3468
3469 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3470 {
3471 /* Read the device table entry from guest memory. */
3472 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3473 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3474 if (RT_SUCCESS(rc))
3475 return rc;
3476
3477 /* Raise a device table hardware error. */
3478 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3479
3480 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3481 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3482 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3483 return VERR_IOMMU_DTE_READ_FAILED;
3484 }
3485
3486 /* Raise an I/O page fault for out-of-bounds acccess. */
3487 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3488 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3489 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3490 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3491 kIoPageFaultType_DevId_Invalid);
3492 return VERR_IOMMU_DTE_BAD_OFFSET;
3493}
3494
3495
3496/**
3497 * Performs pre-translation checks for the given device table entry.
3498 *
3499 * @returns VBox status code.
3500 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3501 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3502 * translation is disabled.
3503 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3504 * corresponding event was raised.
3505 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3506 * permissions.
3507 *
3508 * @param pDevIns The IOMMU device instance.
3509 * @param uIova The I/O virtual address to translate.
3510 * @param idDevice The device ID (bus, device, function).
3511 * @param fPerm The I/O permissions for this access, see
3512 * IOMMU_IO_PERM_XXX.
3513 * @param pDte The device table entry.
3514 * @param enmOp The IOMMU operation being performed.
3515 *
3516 * @thread Any.
3517 */
3518static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3519 IOMMUOP enmOp)
3520{
3521 /*
3522 * Check if the translation is valid, otherwise raise an I/O page fault.
3523 */
3524 if (pDte->n.u1TranslationValid)
3525 { /* likely */ }
3526 else
3527 {
3528 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3529 * doesn't explicitly say whether an I/O page fault is raised. From other
3530 * places in the spec. it seems early page walk terminations (starting with
3531 * the DTE) return the state computed so far and raises an I/O page fault. So
3532 * returning an invalid translation rather than skipping translation. */
3533 LogFunc(("Translation valid bit not set -> IOPF\n"));
3534 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3535 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3536 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3537 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3538 kIoPageFaultType_DteTranslationDisabled);
3539 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3540 }
3541
3542 /*
3543 * Check permissions bits in the DTE.
3544 * Note: This MUST be checked prior to checking the root page table level below!
3545 */
3546 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3547 if ((fPerm & fDtePerm) == fPerm)
3548 { /* likely */ }
3549 else
3550 {
3551 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3552 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3553 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3554 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3555 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3556 kIoPageFaultType_PermDenied);
3557 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3558 }
3559
3560 /*
3561 * If the root page table level is 0, translation is disabled and GPA=SPA and
3562 * the DTE.IR and DTE.IW bits control permissions (verified above).
3563 */
3564 uint8_t const uMaxLevel = pDte->n.u3Mode;
3565 if (uMaxLevel != 0)
3566 { /* likely */ }
3567 else
3568 {
3569 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3570 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3571 }
3572
3573 /*
3574 * If the root page table level exceeds the allowed host-address translation level,
3575 * page walk is terminated and translation fails.
3576 */
3577 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3578 { /* likely */ }
3579 else
3580 {
3581 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3582 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3583 * I'm just going with I/O page fault. */
3584 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3585 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3586 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3587 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3588 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3589 kIoPageFaultType_PteInvalidLvlEncoding);
3590 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3591 }
3592
3593 /* The DTE allows translations for this device. */
3594 return VINF_SUCCESS;
3595}
3596
3597
3598/**
3599 * Walks the I/O page table to translate the I/O virtual address to a system
3600 * physical address.
3601 *
3602 * @returns VBox status code.
3603 * @param pDevIns The IOMMU device instance.
3604 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3605 * @param fPerm The I/O permissions for this access, see
3606 * IOMMU_IO_PERM_XXX.
3607 * @param idDevice The device ID (bus, device, function).
3608 * @param pDte The device table entry.
3609 * @param enmOp The IOMMU operation being performed.
3610 * @param pPageLookup Where to store the results of the I/O page lookup. This
3611 * is only updated when VINF_SUCCESS is returned.
3612 *
3613 * @thread Any.
3614 */
3615static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3616 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3617{
3618 Assert(pDte->n.u1Valid);
3619 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3620
3621 /* The virtual address bits indexing table. */
3622 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3623 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
3624 UINT64_C(0x00000000001ff000),
3625 UINT64_C(0x000000003fe00000),
3626 UINT64_C(0x0000007fc0000000),
3627 UINT64_C(0x0000ff8000000000),
3628 UINT64_C(0x01ff000000000000),
3629 UINT64_C(0xfe00000000000000),
3630 UINT64_C(0x0000000000000000) };
3631 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
3632 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3633
3634 /* Traverse the I/O page table starting with the page directory in the DTE. */
3635 IOPTENTITY_T PtEntity;
3636 PtEntity.u64 = pDte->au64[0];
3637 for (;;)
3638 {
3639 /* Figure out the system physical address of the page table at the current level. */
3640 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3641
3642 /* Read the page table entity at the current level. */
3643 {
3644 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3645 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3646 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3647 uint64_t const offPte = idxPte << 3;
3648 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3649 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3650 if (RT_FAILURE(rc))
3651 {
3652 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3653 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3654 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3655 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3656 return VERR_IOMMU_IPE_2;
3657 }
3658 }
3659
3660 /* Check present bit. */
3661 if (PtEntity.n.u1Present)
3662 { /* likely */ }
3663 else
3664 {
3665 LogFunc(("Page table entry not present (idDevice=%#x) -> IOPF\n", idDevice));
3666 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3667 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3668 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3669 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3670 kIoPageFaultType_PermDenied);
3671 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3672 }
3673
3674 /* Check permission bits. */
3675 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3676 if ((fPerm & fPtePerm) == fPerm)
3677 { /* likely */ }
3678 else
3679 {
3680 LogFunc(("Page table entry access denied (idDevice=%#x fPerm=%#x fPtePerm=%#x) -> IOPF\n", idDevice, fPerm, fPtePerm));
3681 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3682 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3683 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3684 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3685 kIoPageFaultType_PermDenied);
3686 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3687 }
3688
3689 /* If this is a PTE, we're at the final level and we're done. */
3690 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3691 if (uNextLevel == 0)
3692 {
3693 /* The page size of the translation is the default (4K). */
3694 pPageLookup->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3695 pPageLookup->cShift = X86_PAGE_4K_SHIFT;
3696 pPageLookup->fPerm = fPtePerm;
3697 return VINF_SUCCESS;
3698 }
3699 if (uNextLevel == 7)
3700 {
3701 /* The default page size of the translation is overridden. */
3702 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3703 uint8_t cShift = X86_PAGE_4K_SHIFT;
3704 while (GCPhysPte & RT_BIT_64(cShift++))
3705 ;
3706
3707 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3708 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
3709 if ( cShift > s_acIovaLevelShifts[uLevel]
3710 && cShift < s_acIovaLevelShifts[uLevel + 1])
3711 {
3712 pPageLookup->GCPhysSpa = GCPhysPte;
3713 pPageLookup->cShift = cShift;
3714 pPageLookup->fPerm = fPtePerm;
3715 return VINF_SUCCESS;
3716 }
3717
3718 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
3719 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3720 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3721 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3722 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3723 kIoPageFaultType_PteInvalidPageSize);
3724 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3725 }
3726
3727 /* Validate the next level encoding of the PDE. */
3728#if IOMMU_MAX_HOST_PT_LEVEL < 6
3729 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3730 { /* likely */ }
3731 else
3732 {
3733 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
3734 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3735 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3736 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3737 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3738 kIoPageFaultType_PteInvalidLvlEncoding);
3739 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3740 }
3741#else
3742 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3743#endif
3744
3745 /* Validate level transition. */
3746 if (uNextLevel < uLevel)
3747 { /* likely */ }
3748 else
3749 {
3750 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3751 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3752 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3753 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3754 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3755 kIoPageFaultType_PteInvalidLvlEncoding);
3756 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3757 }
3758
3759 /* Ensure IOVA bits of skipped levels are zero. */
3760 Assert(uLevel > 0);
3761 uint64_t uIovaSkipMask = 0;
3762 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
3763 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
3764 if (!(uIova & uIovaSkipMask))
3765 { /* likely */ }
3766 else
3767 {
3768 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
3769 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3770 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3771 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3772 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3773 kIoPageFaultType_SkippedLevelIovaNotZero);
3774 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3775 }
3776
3777 /* Continue with traversing the page directory at this level. */
3778 }
3779}
3780
3781
3782/**
3783 * Page lookup callback for finding an I/O page from guest memory.
3784 *
3785 * @returns VBox status code.
3786 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3787 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3788 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3789 * insufficient to what is requested.
3790 *
3791 * @param pDevIns The IOMMU instance data.
3792 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3793 * 4K aligned).
3794 * @param fPerm The I/O permissions for this access, see
3795 * IOMMU_IO_PERM_XXX.
3796 * @param pAux The auxiliary information required during lookup.
3797 * @param pPageLookup Where to store the looked up I/O page.
3798 */
3799static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3800 PIOPAGELOOKUP pPageLookup)
3801{
3802 AssertPtr(pAux);
3803 AssertPtr(pPageLookup);
3804 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3805
3806 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3807 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3808 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3809 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3810 return rc;
3811}
3812
3813
3814/**
3815 * Looks up a range of I/O virtual addresses.
3816 *
3817 * @returns VBox status code.
3818 * @param pDevIns The IOMMU instance data.
3819 * @param pfnIoPageLookup The lookup function to use.
3820 * @param pAddrIn The I/O address range to lookup.
3821 * @param pAux The auxiliary information required by the lookup
3822 * function.
3823 * @param pAddrOut Where to store the translated I/O address range.
3824 * @param pcbPages Where to store the size of the access (round up to
3825 * the page size). Optional, can be NULL.
3826 */
3827static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3828 PCIOMMUOPAUX pAux, PIOADDRRANGE pAddrOut, size_t *pcbPages)
3829{
3830 AssertPtr(pfnIoPageLookup);
3831 AssertPtr(pAddrIn);
3832 AssertPtr(pAddrOut);
3833
3834 int rc;
3835 size_t const cbIova = pAddrIn->cb;
3836 uint8_t const fPerm = pAddrIn->fPerm;
3837 uint64_t const uIova = pAddrIn->uAddr;
3838 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3839 size_t cbRemaining = cbIova;
3840 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3841 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3842 uint64_t cbPages = 0;
3843
3844 IOPAGELOOKUP PageLookupPrev;
3845 RT_ZERO(PageLookupPrev);
3846 for (;;)
3847 {
3848 IOPAGELOOKUP PageLookup;
3849 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3850 if (RT_SUCCESS(rc))
3851 {
3852 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT);
3853
3854 /* Store the translated address before continuing to access more pages. */
3855 if (cbRemaining == cbIova)
3856 {
3857 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(PageLookup.cShift);
3858 uint64_t const offSpa = uIova & offMask;
3859 Assert(!(PageLookup.GCPhysSpa & offMask));
3860 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3861 }
3862 /* Check if addresses translated so far result in a physically contiguous region. */
3863 else if (!iommuAmdLookupIsAccessContig(&PageLookupPrev, &PageLookup))
3864 {
3865 rc = VERR_OUT_OF_RANGE;
3866 break;
3867 }
3868
3869 /* Store the page lookup result from the first/previous page. */
3870 PageLookupPrev = PageLookup;
3871
3872 /* Update size of all pages read thus far. */
3873 uint64_t const cbPage = RT_BIT_64(PageLookup.cShift);
3874 cbPages += cbPage;
3875
3876 /* Check if we need to access more pages. */
3877 if (cbRemaining > cbPage - offIova)
3878 {
3879 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3880 uIovaPage += cbPage; /* Update address of the next access. */
3881 offIova = 0; /* After first page, all pages are accessed from off 0. */
3882 }
3883 else
3884 {
3885 cbRemaining = 0;
3886 break;
3887 }
3888 }
3889 else
3890 break;
3891 }
3892
3893 pAddrOut->uAddr = GCPhysSpa; /* Update the translated address. */
3894 pAddrOut->cb = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
3895 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
3896 if (pcbPages)
3897 *pcbPages = cbPages; /* Update the size of the pages accessed. */
3898 return rc;
3899}
3900
3901
3902/**
3903 * Looks up an I/O virtual address from the device table.
3904 *
3905 * @returns VBox status code.
3906 * @param pDevIns The IOMMU instance data.
3907 * @param idDevice The device ID (bus, device, function).
3908 * @param uIova The I/O virtual address to lookup.
3909 * @param cbIova The size of the access.
3910 * @param fPerm The I/O permissions for this access, see
3911 * IOMMU_IO_PERM_XXX.
3912 * @param enmOp The IOMMU operation being performed.
3913 * @param pGCPhysSpa Where to store the translated system physical address.
3914 * @param pcbContiguous Where to store the number of contiguous bytes translated
3915 * and permission-checked.
3916 *
3917 * @thread Any.
3918 */
3919static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
3920 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3921{
3922 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3923 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3924 size_t cbContiguous = 0;
3925
3926 /* Read the device table entry from memory. */
3927 DTE_T Dte;
3928 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
3929 if (RT_SUCCESS(rc))
3930 {
3931 if (Dte.n.u1Valid)
3932 {
3933 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3934 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3935 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3936 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
3937 {
3938 /*
3939 * Check if the DTE is configured for translating addresses.
3940 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
3941 * so there's no need to check the address exclusion base/limit here.
3942 */
3943 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
3944 if (rc == VINF_SUCCESS)
3945 {
3946 IOADDRRANGE AddrIn;
3947 AddrIn.uAddr = uIova;
3948 AddrIn.cb = cbIova;
3949 AddrIn.fPerm = fPerm;
3950
3951 IOMMUOPAUX Aux;
3952 Aux.enmOp = enmOp;
3953 Aux.pDte = &Dte;
3954 Aux.idDevice = idDevice;
3955 Aux.idDomain = Dte.n.u16DomainId;
3956
3957 IOADDRRANGE AddrOut;
3958
3959 /* Lookup the address from the DTE and I/O page tables.*/
3960 size_t cbPages = 0;
3961 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbPages);
3962 GCPhysSpa = AddrOut.uAddr;
3963 cbContiguous = AddrOut.cb;
3964
3965 /* If we stopped since translation resulted in non-contiguous physical addresses,
3966 what we translated so far is still valid. */
3967 if (rc == VERR_OUT_OF_RANGE)
3968 {
3969 Assert(cbContiguous > 0 && cbContiguous < cbIova);
3970 rc = VINF_SUCCESS;
3971 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
3972 }
3973
3974 if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
3975 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
3976
3977#ifdef IOMMU_WITH_IOTLBE_CACHE
3978 if (RT_SUCCESS(rc))
3979 {
3980 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
3981 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
3982 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
3983 iommuAmdIotlbAddRange(pDevIns, Dte.n.u16DomainId, uIova & X86_PAGE_4K_BASE_MASK, cbPages,
3984 GCPhysSpa & X86_PAGE_4K_BASE_MASK, AddrOut.fPerm);
3985 }
3986#endif
3987 }
3988 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
3989 {
3990 /*
3991 * Translation is disabled for this device (root paging mode is 0).
3992 * GPA=SPA, but the permission bits are important and controls accesses.
3993 */
3994 GCPhysSpa = uIova;
3995 cbContiguous = cbIova;
3996 rc = VINF_SUCCESS;
3997
3998#ifdef IOMMU_WITH_IOTLBE_CACHE
3999 /* Update that addresses permissions of DTE apply (but omit address translation). */
4000 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_IO_PERM);
4001#endif
4002 }
4003 else
4004 {
4005 /* Address translation failed or access is denied. */
4006 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4007 GCPhysSpa = NIL_RTGCPHYS;
4008 cbContiguous = 0;
4009 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4010 }
4011 }
4012 else
4013 {
4014 /* Invalid reserved bits in the DTE, raise an error event. */
4015 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4016 EVT_ILLEGAL_DTE_T Event;
4017 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4018 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4019 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4020 }
4021 }
4022 else
4023 {
4024 /*
4025 * The DTE is not valid, forward addresses untranslated.
4026 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4027 */
4028 GCPhysSpa = uIova;
4029 cbContiguous = cbIova;
4030
4031#ifdef IOMMU_WITH_IOTLBE_CACHE
4032 /* Update that addresses don't require translation (nor permission checks) but a DTE is present. */
4033 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4034#endif
4035 }
4036 }
4037 else
4038 {
4039 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4040 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4041 }
4042
4043 *pGCPhysSpa = GCPhysSpa;
4044 *pcbContiguous = cbContiguous;
4045 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4046 return rc;
4047}
4048
4049
4050#ifdef IOMMU_WITH_IOTLBE_CACHE
4051/**
4052 * I/O page lookup callback for finding an I/O page from the IOTLB.
4053 *
4054 * @returns VBox status code.
4055 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4056 * @retval VERR_NOT_FOUND when the page is not found.
4057 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4058 * insufficient to what is requested.
4059 *
4060 * @param pDevIns The IOMMU instance data.
4061 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4062 * 4K aligned).
4063 * @param fPerm The I/O permissions for this access, see
4064 * IOMMU_IO_PERM_XXX.
4065 * @param pAux The auxiliary information required during lookup.
4066 * @param pPageLookup Where to store the looked up I/O page.
4067 */
4068static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4069 PIOPAGELOOKUP pPageLookup)
4070{
4071 Assert(pAux);
4072 Assert(pPageLookup);
4073 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4074
4075 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4076 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4077
4078 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4079 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4080 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4081 if (pIotlbe)
4082 {
4083 *pPageLookup = pIotlbe->PageLookup;
4084 if ((pPageLookup->fPerm & fPerm) == fPerm)
4085 {
4086 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4087 return VINF_SUCCESS;
4088 }
4089 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4090 }
4091 return VERR_NOT_FOUND;
4092}
4093
4094
4095/**
4096 * Lookups a memory access from the IOTLB cache.
4097 *
4098 * @returns VBox status code.
4099 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4100 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4101 * address region.
4102 * @retval VERR_NOT_FOUND if the access was not cached.
4103 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4104 * are insufficient.
4105 *
4106 * @param pDevIns The IOMMU instance data.
4107 * @param idDevice The device ID (bus, device, function).
4108 * @param uIova The I/O virtual address to lookup.
4109 * @param cbIova The size of the access.
4110 * @param fPerm The I/O permissions for this access, see
4111 * IOMMU_IO_PERM_XXX.
4112 * @param enmOp The IOMMU operation being performed.
4113 * @param pGCPhysSpa Where to store the translated system physical address.
4114 * @param pcbContiguous Where to store the number of contiguous bytes translated
4115 * and permission-checked.
4116 */
4117static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4118 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4119{
4120 int rc;
4121 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4122
4123#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4124 do { \
4125 *pGCPhysSpa = NIL_RTGCPHYS; \
4126 *pcbContiguous = 0; \
4127 rc = (a_rc); \
4128 } while (0)
4129
4130 /*
4131 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4132 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4133 */
4134 IOMMU_LOCK_CACHE(pDevIns, pThis);
4135
4136 /* Lookup the DTE cache entry. */
4137 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4138 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4139 {
4140 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4141 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4142 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4143 {
4144 /* Lookup IOTLB entries. */
4145 IOADDRRANGE AddrIn;
4146 AddrIn.uAddr = uIova;
4147 AddrIn.cb = cbIova;
4148 AddrIn.fPerm = fPerm;
4149
4150 IOMMUOPAUX Aux;
4151 Aux.enmOp = enmOp;
4152 Aux.pDte = NULL;
4153 Aux.idDevice = idDevice;
4154 Aux.idDomain = pDteCache->idDomain;
4155
4156 IOADDRRANGE AddrOut;
4157 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, NULL /* pcbPages */);
4158 Assert(AddrOut.cb <= cbIova);
4159 *pGCPhysSpa = AddrOut.uAddr;
4160 *pcbContiguous = AddrOut.cb;
4161 }
4162 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4163 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4164 {
4165 /* Address translation is disabled, but DTE permissions apply. */
4166 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4167 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4168 if ((fDtePerm & fPerm) == fPerm)
4169 {
4170 *pGCPhysSpa = uIova;
4171 *pcbContiguous = cbIova;
4172 rc = VINF_SUCCESS;
4173 }
4174 else
4175 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4176 }
4177 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4178 {
4179 /* Forward addresses untranslated, without checking permissions. */
4180 *pGCPhysSpa = uIova;
4181 *pcbContiguous = cbIova;
4182 rc = VINF_SUCCESS;
4183 }
4184 else
4185 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4186 }
4187 else
4188 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4189
4190 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
4191
4192 return rc;
4193
4194#undef IOMMU_IOTLB_LOOKUP_FAILED
4195}
4196#endif /* IOMMU_WITH_IOTLBE_CACHE */
4197
4198
4199/**
4200 * Gets the I/O permission and IOMMU operation type for the given access flags.
4201 *
4202 * @param pThis The shared IOMMU device state.
4203 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4204 * @param penmOp Where to store the IOMMU operation.
4205 * @param pfPerm Where to store the IOMMU I/O permission.
4206 * @param fBulk Whether this is a bulk read or write.
4207 */
4208DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4209{
4210 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4211 {
4212 *penmOp = IOMMUOP_MEM_WRITE;
4213 *pfPerm = IOMMU_IO_PERM_WRITE;
4214#ifdef VBOX_WITH_STATISTICS
4215 if (!fBulk)
4216 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4217 else
4218 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4219#else
4220 RT_NOREF2(pThis, fBulk);
4221#endif
4222 }
4223 else
4224 {
4225 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4226 *penmOp = IOMMUOP_MEM_READ;
4227 *pfPerm = IOMMU_IO_PERM_READ;
4228#ifdef VBOX_WITH_STATISTICS
4229 if (!fBulk)
4230 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4231 else
4232 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4233#else
4234 RT_NOREF2(pThis, fBulk);
4235#endif
4236 }
4237}
4238
4239
4240/**
4241 * Memory access transaction from a device.
4242 *
4243 * @returns VBox status code.
4244 * @param pDevIns The IOMMU device instance.
4245 * @param idDevice The device ID (bus, device, function).
4246 * @param uIova The I/O virtual address being accessed.
4247 * @param cbIova The size of the access.
4248 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4249 * @param pGCPhysSpa Where to store the translated system physical address.
4250 * @param pcbContiguous Where to store the number of contiguous bytes translated
4251 * and permission-checked.
4252 *
4253 * @thread Any.
4254 */
4255static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4256 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4257{
4258 /* Validate. */
4259 AssertPtr(pDevIns);
4260 AssertPtr(pGCPhysSpa);
4261 Assert(cbIova > 0);
4262 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4263
4264 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4265 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4266 if (Ctrl.n.u1IommuEn)
4267 {
4268 IOMMUOP enmOp;
4269 uint8_t fPerm;
4270 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4271 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4272
4273 int rc;
4274#ifdef IOMMU_WITH_IOTLBE_CACHE
4275 /* Lookup the IOVA from the cache. */
4276 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4277 if (rc == VINF_SUCCESS)
4278 {
4279 /* All pages in the access were found in the cache with sufficient permissions. */
4280 Assert(*pcbContiguous == cbIova);
4281 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4282 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4283 return VINF_SUCCESS;
4284 }
4285 if (rc != VERR_OUT_OF_RANGE)
4286 { /* likely */ }
4287 else
4288 {
4289 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4290 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4291 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4292 return VINF_SUCCESS;
4293 }
4294
4295 /*
4296 * Access incomplete as not all pages were in the cache.
4297 * Or permissions were denied for the access (which typically doesn't happen)
4298 * so go through the slower path and raise the required event.
4299 */
4300 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4301 uIova += *pcbContiguous;
4302 cbIova -= *pcbContiguous;
4303 /* We currently are including any permission denied pages as cache misses too.*/
4304 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4305#endif
4306
4307 /* Lookup the IOVA from the device table. */
4308 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4309 if (RT_SUCCESS(rc))
4310 { /* likely */ }
4311 else
4312 {
4313 Assert(rc != VERR_OUT_OF_RANGE);
4314 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4315 cbIova, rc));
4316 }
4317
4318 return rc;
4319 }
4320
4321 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4322 *pGCPhysSpa = uIova;
4323 *pcbContiguous = cbIova;
4324 return VINF_SUCCESS;
4325}
4326
4327
4328/**
4329 * Memory access bulk (one or more 4K pages) request from a device.
4330 *
4331 * @returns VBox status code.
4332 * @param pDevIns The IOMMU device instance.
4333 * @param idDevice The device ID (bus, device, function).
4334 * @param cIovas The number of addresses being accessed.
4335 * @param pauIovas The I/O virtual addresses for each page being accessed.
4336 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4337 * @param paGCPhysSpa Where to store the translated physical addresses.
4338 *
4339 * @thread Any.
4340 */
4341static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4342 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4343{
4344 /* Validate. */
4345 AssertPtr(pDevIns);
4346 Assert(cIovas > 0);
4347 AssertPtr(pauIovas);
4348 AssertPtr(paGCPhysSpa);
4349 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4350
4351 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4352 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4353 if (Ctrl.n.u1IommuEn)
4354 {
4355 IOMMUOP enmOp;
4356 uint8_t fPerm;
4357 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4358 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4359
4360 for (size_t i = 0; i < cIovas; i++)
4361 {
4362 int rc;
4363 size_t cbContig;
4364
4365#ifdef IOMMU_WITH_IOTLBE_CACHE
4366 /* Lookup the IOVA from the IOTLB cache. */
4367 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4368 &cbContig);
4369 if (rc == VINF_SUCCESS)
4370 {
4371 Assert(cbContig == X86_PAGE_SIZE);
4372 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4373 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4374 continue;
4375 }
4376 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4377 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4378#endif
4379
4380 /* Lookup the IOVA from the device table. */
4381 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4382 if (RT_SUCCESS(rc))
4383 { /* likely */ }
4384 else
4385 {
4386 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4387 return rc;
4388 }
4389 Assert(cbContig == X86_PAGE_SIZE);
4390 }
4391 }
4392 else
4393 {
4394 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4395 for (size_t i = 0; i < cIovas; i++)
4396 paGCPhysSpa[i] = pauIovas[i];
4397 }
4398
4399 return VINF_SUCCESS;
4400}
4401
4402
4403/**
4404 * Reads an interrupt remapping table entry from guest memory given its DTE.
4405 *
4406 * @returns VBox status code.
4407 * @param pDevIns The IOMMU device instance.
4408 * @param idDevice The device ID (bus, device, function).
4409 * @param pDte The device table entry.
4410 * @param GCPhysIn The source MSI address (used for reporting errors).
4411 * @param uDataIn The source MSI data.
4412 * @param enmOp The IOMMU operation being performed.
4413 * @param pIrte Where to store the interrupt remapping table entry.
4414 *
4415 * @thread Any.
4416 */
4417static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4418 IOMMUOP enmOp, PIRTE_T pIrte)
4419{
4420 /* Ensure the IRTE length is valid. */
4421 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4422
4423 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4424 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4425 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4426 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4427
4428 /* Ensure the IRTE falls completely within the interrupt table. */
4429 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4430 { /* likely */ }
4431 else
4432 {
4433 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4434 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4435
4436 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4437 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4438 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4439 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4440 kIoPageFaultType_IrteAddrInvalid);
4441 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4442 }
4443
4444 /* Read the IRTE from memory. */
4445 Assert(!(GCPhysIrte & 3));
4446 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4447 if (RT_SUCCESS(rc))
4448 return VINF_SUCCESS;
4449
4450 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4451 * situation. Is it an I/O page fault or a device table hardware error?
4452 * There's no interrupt table hardware error event, but it's unclear what
4453 * we should do here. */
4454 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4455 return VERR_IOMMU_IPE_4;
4456}
4457
4458
4459/**
4460 * Remaps the interrupt using the interrupt remapping table.
4461 *
4462 * @returns VBox status code.
4463 * @param pDevIns The IOMMU instance data.
4464 * @param idDevice The device ID (bus, device, function).
4465 * @param pDte The device table entry.
4466 * @param enmOp The IOMMU operation being performed.
4467 * @param pMsiIn The source MSI.
4468 * @param pMsiOut Where to store the remapped MSI.
4469 *
4470 * @thread Any.
4471 */
4472static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4473 PMSIMSG pMsiOut)
4474{
4475 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4476
4477 IRTE_T Irte;
4478 uint32_t const uMsiInData = pMsiIn->Data.u32;
4479 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4480 if (RT_SUCCESS(rc))
4481 {
4482 if (Irte.n.u1RemapEnable)
4483 {
4484 if (!Irte.n.u1GuestMode)
4485 {
4486 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4487 {
4488 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4489#ifdef IOMMU_WITH_IRTE_CACHE
4490 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4491#endif
4492 return VINF_SUCCESS;
4493 }
4494
4495 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4496 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4497 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4498 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4499 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4500 kIoPageFaultType_IrteRsvdIntType);
4501 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4502 }
4503
4504 LogFunc(("Guest mode not supported -> IOPF\n"));
4505 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4506 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4507 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4508 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4509 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4510 }
4511
4512 LogFunc(("Remapping disabled -> IOPF\n"));
4513 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4514 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4515 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4516 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4517 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4518 }
4519
4520 return rc;
4521}
4522
4523
4524/**
4525 * Looks up an MSI interrupt from the interrupt remapping table.
4526 *
4527 * @returns VBox status code.
4528 * @param pDevIns The IOMMU instance data.
4529 * @param idDevice The device ID (bus, device, function).
4530 * @param enmOp The IOMMU operation being performed.
4531 * @param pMsiIn The source MSI.
4532 * @param pMsiOut Where to store the remapped MSI.
4533 *
4534 * @thread Any.
4535 */
4536static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4537{
4538 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4539 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4540 enmOp));
4541
4542 /* Read the device table entry from memory. */
4543 DTE_T Dte;
4544 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4545 if (RT_SUCCESS(rc))
4546 {
4547#ifdef IOMMU_WITH_IRTE_CACHE
4548 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4549#endif
4550 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4551 if (Dte.n.u1IntrMapValid)
4552 {
4553 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4554 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4555 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4556 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4557 { /* likely */ }
4558 else
4559 {
4560 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4561 EVT_ILLEGAL_DTE_T Event;
4562 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4563 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4564 return VERR_IOMMU_INTR_REMAP_FAILED;
4565 }
4566
4567 /*
4568 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4569 * that's connected through HyperTransport it might be possible; but for us, it
4570 * doesn't seem we need to specially handle these pins.
4571 */
4572
4573 /*
4574 * Validate the MSI source address.
4575 *
4576 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4577 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4578 * claims the region as I/O space.
4579 *
4580 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4581 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4582 * See Intel spec. 10.11.1 "Message Address Register Format".
4583 */
4584 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4585 {
4586 /*
4587 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4588 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4589 */
4590 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4591 bool fPassThru = false;
4592 switch (u8DeliveryMode)
4593 {
4594 case VBOX_MSI_DELIVERY_MODE_FIXED:
4595 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4596 {
4597 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4598 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4599 {
4600 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4601 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4602 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4603 {
4604 /*
4605 * We don't support guest interrupt remapping yet. When we do, we'll need to
4606 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4607 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4608 * already reads the control register, add that as a parameter when we eventually
4609 * support guest interrupt remapping. For now, just assert.
4610 */
4611 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4612 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4613 NOREF(pThis);
4614
4615 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4616 }
4617
4618 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4619 EVT_ILLEGAL_DTE_T Event;
4620 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4621 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4622 return VERR_IOMMU_INTR_REMAP_FAILED;
4623 }
4624
4625 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4626 {
4627 fPassThru = true;
4628 break;
4629 }
4630
4631 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4632 {
4633 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4634 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4635 iommuAmdSetPciTargetAbort(pDevIns);
4636 return VERR_IOMMU_INTR_REMAP_DENIED;
4637 }
4638
4639 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4640 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4641 EVT_ILLEGAL_DTE_T Event;
4642 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4643 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4644 return VERR_IOMMU_INTR_REMAP_FAILED;
4645 }
4646
4647 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4648 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4649 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4650 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4651 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4652 default:
4653 {
4654 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4655 u8DeliveryMode));
4656 iommuAmdSetPciTargetAbort(pDevIns);
4657 return VERR_IOMMU_INTR_REMAP_FAILED;
4658 }
4659 }
4660
4661 /*
4662 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4663 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4664 */
4665 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4666 || !pMsiIn->Addr.n.u1DestMode)
4667 {
4668 if (fPassThru)
4669 {
4670 *pMsiOut = *pMsiIn;
4671 return VINF_SUCCESS;
4672 }
4673 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4674 pMsiIn->Data.n.u8Vector));
4675 }
4676 else
4677 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4678 IOMMU_LOG_PFX, u8DeliveryMode));
4679
4680 iommuAmdSetPciTargetAbort(pDevIns);
4681 return VERR_IOMMU_INTR_REMAP_DENIED;
4682 }
4683 else
4684 {
4685 /** @todo should be cause a PCI target abort here? */
4686 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4687 return VERR_IOMMU_INTR_REMAP_FAILED;
4688 }
4689 }
4690 else
4691 {
4692 LogFlowFunc(("DTE interrupt map not valid\n"));
4693 *pMsiOut = *pMsiIn;
4694 return VINF_SUCCESS;
4695 }
4696 }
4697
4698 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4699 return VERR_IOMMU_INTR_REMAP_FAILED;
4700}
4701
4702
4703/**
4704 * Interrupt remap request from a device.
4705 *
4706 * @returns VBox status code.
4707 * @param pDevIns The IOMMU device instance.
4708 * @param idDevice The device ID (bus, device, function).
4709 * @param pMsiIn The source MSI.
4710 * @param pMsiOut Where to store the remapped MSI.
4711 */
4712static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4713{
4714 /* Validate. */
4715 Assert(pDevIns);
4716 Assert(pMsiIn);
4717 Assert(pMsiOut);
4718
4719 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4720
4721 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4722 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4723 if (Ctrl.n.u1IommuEn)
4724 {
4725 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4726
4727 int rc;
4728#ifdef IOMMU_WITH_IRTE_CACHE
4729 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4730 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4731 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4732 if (RT_SUCCESS(rc))
4733 {
4734 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4735 return VINF_SUCCESS;
4736 }
4737 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4738#endif
4739
4740 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4741 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4742 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4743 return rc;
4744 }
4745
4746 *pMsiOut = *pMsiIn;
4747 return VINF_SUCCESS;
4748}
4749
4750
4751/**
4752 * @callback_method_impl{FNIOMMMIONEWWRITE}
4753 */
4754static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4755{
4756 NOREF(pvUser);
4757 Assert(cb == 4 || cb == 8);
4758 Assert(!(off & (cb - 1)));
4759
4760 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4761 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4762
4763 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4764 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4765}
4766
4767
4768/**
4769 * @callback_method_impl{FNIOMMMIONEWREAD}
4770 */
4771static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4772{
4773 NOREF(pvUser);
4774 Assert(cb == 4 || cb == 8);
4775 Assert(!(off & (cb - 1)));
4776
4777 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4778 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4779
4780 uint64_t uResult;
4781 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4782 if (rcStrict == VINF_SUCCESS)
4783 {
4784 if (cb == 8)
4785 *(uint64_t *)pv = uResult;
4786 else
4787 *(uint32_t *)pv = (uint32_t)uResult;
4788 }
4789
4790 return rcStrict;
4791}
4792
4793
4794#ifdef IN_RING3
4795/**
4796 * Processes an IOMMU command.
4797 *
4798 * @returns VBox status code.
4799 * @param pDevIns The IOMMU device instance.
4800 * @param pCmd The command to process.
4801 * @param GCPhysCmd The system physical address of the command.
4802 * @param pEvtError Where to store the error event in case of failures.
4803 *
4804 * @thread Command thread.
4805 */
4806static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4807{
4808 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4809 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4810
4811 STAM_COUNTER_INC(&pThis->StatCmd);
4812
4813 uint8_t const bCmd = pCmd->n.u4Opcode;
4814 switch (bCmd)
4815 {
4816 case IOMMU_CMD_COMPLETION_WAIT:
4817 {
4818 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4819
4820 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4821 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4822
4823 /* Validate reserved bits in the command. */
4824 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4825 {
4826 /* If Completion Store is requested, write the StoreData to the specified address. */
4827 if (pCmdComWait->n.u1Store)
4828 {
4829 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4830 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4831 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4832 if (RT_FAILURE(rc))
4833 {
4834 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4835 GCPhysStore, rc));
4836 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4837 return VERR_IOMMU_CMD_HW_ERROR;
4838 }
4839 }
4840
4841 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4842 if (pCmdComWait->n.u1Interrupt)
4843 {
4844 IOMMU_LOCK(pDevIns, pThisR3);
4845 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4846 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4847 IOMMU_UNLOCK(pDevIns, pThisR3);
4848
4849 if (fRaiseInt)
4850 iommuAmdMsiInterruptRaise(pDevIns);
4851 }
4852 return VINF_SUCCESS;
4853 }
4854 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4855 return VERR_IOMMU_CMD_INVALID_FORMAT;
4856 }
4857
4858 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4859 {
4860 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4861 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4862 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4863
4864 /* Validate reserved bits in the command. */
4865 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4866 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4867 {
4868#ifdef IOMMU_WITH_DTE_CACHE
4869 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4870#endif
4871 return VINF_SUCCESS;
4872 }
4873 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4874 return VERR_IOMMU_CMD_INVALID_FORMAT;
4875 }
4876
4877 case IOMMU_CMD_INV_IOMMU_PAGES:
4878 {
4879 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4880 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4881 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4882
4883 /* Validate reserved bits in the command. */
4884 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4885 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4886 {
4887#ifdef IOMMU_WITH_IOTLBE_CACHE
4888 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4889 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
4890 uint8_t cShift;
4891 if (!pCmdInvPages->n.u1Size)
4892 cShift = X86_PAGE_4K_SHIFT;
4893 else
4894 {
4895 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4896 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4897 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4898
4899 /*
4900 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4901 * would do the right thing by clearing the entire cache for the specified domain ID.
4902 *
4903 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4904 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4905 * A debug-time assert is in place here to let us know if any software tries this.
4906 *
4907 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4908 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4909 */
4910 Assert(uIova != UINT64_C(0xfffffffffffff000));
4911 }
4912
4913 /*
4914 * Validate invalidation size.
4915 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4916 */
4917 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4918 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4919 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4920 {
4921 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4922 size_t const cbIova = RT_BIT_64(cShift);
4923 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
4924 }
4925 else
4926 {
4927 /*
4928 * The guest provided size is invalid or exceeds the largest, meaningful page size.
4929 * In such situations we must remove all ranges for the specified domain ID.
4930 */
4931 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
4932 }
4933#endif
4934 return VINF_SUCCESS;
4935 }
4936 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4937 return VERR_IOMMU_CMD_INVALID_FORMAT;
4938 }
4939
4940 case IOMMU_CMD_INV_IOTLB_PAGES:
4941 {
4942 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
4943
4944 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4945 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4946 {
4947 /** @todo IOMMU: Implement remote IOTLB invalidation. */
4948 return VERR_NOT_IMPLEMENTED;
4949 }
4950 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4951 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4952 }
4953
4954 case IOMMU_CMD_INV_INTR_TABLE:
4955 {
4956 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
4957
4958 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
4959 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
4960
4961 /* Validate reserved bits in the command. */
4962 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
4963 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
4964 {
4965#ifdef IOMMU_WITH_IRTE_CACHE
4966 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
4967#endif
4968 return VINF_SUCCESS;
4969 }
4970 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4971 return VERR_IOMMU_CMD_INVALID_FORMAT;
4972 }
4973
4974 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
4975 {
4976 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
4977 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
4978 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
4979 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4980 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4981 }
4982
4983 case IOMMU_CMD_COMPLETE_PPR_REQ:
4984 {
4985 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
4986
4987 /* We don't support PPR requests yet. */
4988 Assert(!pThis->ExtFeat.n.u1PprSup);
4989 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4990 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4991 }
4992
4993 case IOMMU_CMD_INV_IOMMU_ALL:
4994 {
4995 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
4996 if (pThis->ExtFeat.n.u1InvAllSup)
4997 {
4998 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
4999 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
5000
5001 /* Validate reserved bits in the command. */
5002 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
5003 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
5004 {
5005#ifdef IOMMU_WITH_DTE_CACHE
5006 iommuAmdDteCacheRemoveAll(pDevIns);
5007#endif
5008#ifdef IOMMU_WITH_IOTLBE_CACHE
5009 iommuAmdIotlbRemoveAll(pDevIns);
5010#endif
5011 return VINF_SUCCESS;
5012 }
5013 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5014 return VERR_IOMMU_CMD_INVALID_FORMAT;
5015 }
5016 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5017 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5018 }
5019 }
5020
5021 STAM_COUNTER_DEC(&pThis->StatCmd);
5022 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5023 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5024 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5025}
5026
5027
5028/**
5029 * The IOMMU command thread.
5030 *
5031 * @returns VBox status code.
5032 * @param pDevIns The IOMMU device instance.
5033 * @param pThread The command thread.
5034 */
5035static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5036{
5037 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5038 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5039
5040 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5041 return VINF_SUCCESS;
5042
5043 /*
5044 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5045 * This avoid trashing the heap as well as not wasting time allocating
5046 * and freeing buffers while processing commands.
5047 */
5048 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5049 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5050 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5051
5052 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5053 {
5054 /*
5055 * Sleep perpetually until we are woken up to process commands.
5056 */
5057 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5058 if (!fSignaled)
5059 {
5060 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5061 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5062 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5063 break;
5064 Log4Func(("Woken up with rc=%Rrc\n", rc));
5065 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5066 }
5067
5068 /*
5069 * Fetch and process IOMMU commands.
5070 */
5071 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5072 * temporary host buffer before processing them as a batch. If we want to
5073 * save on host memory a bit, we could (once PGM has the necessary APIs)
5074 * lock the page mappings page mappings and access them directly. */
5075 IOMMU_LOCK(pDevIns, pThisR3);
5076
5077 if (pThis->Status.n.u1CmdBufRunning)
5078 {
5079 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5080 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5081 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5082 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5083
5084 /* Validate. */
5085 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5086 Assert(offHead < cbCmdBuf);
5087 Assert(cbCmdBuf <= cbMaxCmdBuf);
5088
5089 if (offHead != offTail)
5090 {
5091 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5092 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5093
5094 IOMMU_UNLOCK(pDevIns, pThisR3);
5095 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5096 IOMMU_LOCK(pDevIns, pThisR3);
5097
5098 if (RT_SUCCESS(rc))
5099 {
5100 /* Indicate to software we've fetched all commands from the buffer. */
5101 pThis->CmdBufHeadPtr.n.off = offTail;
5102
5103 /* Allow IOMMU to do other work while we process commands. */
5104 IOMMU_UNLOCK(pDevIns, pThisR3);
5105
5106 /* Process the fetched commands. */
5107 EVT_GENERIC_T EvtError;
5108 do
5109 {
5110 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5111 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5112 if (RT_FAILURE(rc))
5113 {
5114 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5115 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5116 {
5117 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5118 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5119 }
5120 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5121 {
5122 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5123 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5124 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5125 }
5126 break;
5127 }
5128
5129 /* Move to the next command in the circular buffer. */
5130 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5131 } while (offHead != offTail);
5132 }
5133 else
5134 {
5135 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5136 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5137 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5138 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5139
5140 IOMMU_UNLOCK(pDevIns, pThisR3);
5141 }
5142 }
5143 else
5144 IOMMU_UNLOCK(pDevIns, pThisR3);
5145 }
5146 else
5147 IOMMU_UNLOCK(pDevIns, pThisR3);
5148 }
5149
5150 RTMemFree(pvCmds);
5151 LogFlowFunc(("Command thread terminating\n"));
5152 return VINF_SUCCESS;
5153}
5154
5155
5156/**
5157 * Wakes up the command thread so it can respond to a state change.
5158 *
5159 * @returns VBox status code.
5160 * @param pDevIns The IOMMU device instance.
5161 * @param pThread The command thread.
5162 */
5163static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5164{
5165 RT_NOREF(pThread);
5166 LogFlowFunc(("\n"));
5167 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5168 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5169}
5170
5171
5172/**
5173 * @callback_method_impl{FNPCICONFIGREAD}
5174 */
5175static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5176 unsigned cb, uint32_t *pu32Value)
5177{
5178 /** @todo IOMMU: PCI config read stat counter. */
5179 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5180 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5181 return rcStrict;
5182}
5183
5184
5185/**
5186 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5187 * register write).
5188 *
5189 * @returns VBox status code.
5190 * @param pDevIns The IOMMU instance data.
5191 *
5192 * @remarks Call this function only when the IOMMU BAR is enabled.
5193 */
5194static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5195{
5196 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5197 Assert(pThis->IommuBar.n.u1Enable);
5198 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5199 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5200 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5201 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5202
5203 /* If the MMIO region is already mapped at the specified address, we're done. */
5204 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5205 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5206 return VINF_SUCCESS;
5207
5208 /* Unmap the previous MMIO region (which is at a different address). */
5209 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5210 {
5211 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5212 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5213 if (RT_FAILURE(rc))
5214 {
5215 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5216 return rc;
5217 }
5218 }
5219
5220 /* Map the newly specified MMIO region. */
5221 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5222 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5223 if (RT_FAILURE(rc))
5224 {
5225 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5226 return rc;
5227 }
5228
5229 return VINF_SUCCESS;
5230}
5231
5232
5233/**
5234 * @callback_method_impl{FNPCICONFIGWRITE}
5235 */
5236static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5237 unsigned cb, uint32_t u32Value)
5238{
5239 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5240
5241 /*
5242 * Discard writes to read-only registers that are specific to the IOMMU.
5243 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5244 * See PCI spec. 6.1. "Configuration Space Organization".
5245 */
5246 switch (uAddress)
5247 {
5248 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5249 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5250 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5251 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5252 {
5253 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5254 return VINF_SUCCESS;
5255 }
5256 }
5257
5258 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5259 IOMMU_LOCK(pDevIns, pThisR3);
5260
5261 VBOXSTRICTRC rcStrict;
5262 switch (uAddress)
5263 {
5264 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5265 {
5266 if (!pThis->IommuBar.n.u1Enable)
5267 {
5268 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5269 if (pThis->IommuBar.n.u1Enable)
5270 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5271 else
5272 rcStrict = VINF_SUCCESS;
5273 }
5274 else
5275 {
5276 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5277 rcStrict = VINF_SUCCESS;
5278 }
5279 break;
5280 }
5281
5282 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5283 {
5284 if (!pThis->IommuBar.n.u1Enable)
5285 {
5286 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5287 pThis->IommuBar.au32[1] = u32Value;
5288 }
5289 else
5290 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5291 rcStrict = VINF_SUCCESS;
5292 break;
5293 }
5294
5295 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5296 {
5297 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5298 RT_FALL_THRU();
5299 }
5300 default:
5301 {
5302 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5303 break;
5304 }
5305 }
5306
5307 IOMMU_UNLOCK(pDevIns, pThisR3);
5308
5309 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5310 return rcStrict;
5311}
5312
5313
5314/**
5315 * @callback_method_impl{FNDBGFHANDLERDEV}
5316 */
5317static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5318{
5319 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5320 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5321 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5322
5323 bool fVerbose;
5324 if ( pszArgs
5325 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
5326 fVerbose = true;
5327 else
5328 fVerbose = false;
5329
5330 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5331 /* Device Table Base Addresses (all segments). */
5332 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5333 {
5334 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5335 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5336 if (fVerbose)
5337 {
5338 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5339 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5340 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5341 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5342 }
5343 }
5344 /* Command Buffer Base Address Register. */
5345 {
5346 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5347 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5348 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5349 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5350 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5351 if (fVerbose)
5352 {
5353 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5354 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5355 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5356 cEntries, cbBuffer);
5357 }
5358 }
5359 /* Event Log Base Address Register. */
5360 {
5361 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5362 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5363 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5364 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5365 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5366 if (fVerbose)
5367 {
5368 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5369 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5370 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5371 cEntries, cbBuffer);
5372 }
5373 }
5374 /* IOMMU Control Register. */
5375 {
5376 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5377 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5378 if (fVerbose)
5379 {
5380 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5381 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5382 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5383 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5384 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5385 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5386 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5387 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5388 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5389 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5390 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5391 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5392 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5393 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5394 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5395 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5396 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5397 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5398 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5399 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5400 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5401 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5402 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5403 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5404 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5405 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5406 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5407 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5408 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5409 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5410 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5411 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5412 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5413 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5414 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5415 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5416 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5417 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5418 }
5419 }
5420 /* Exclusion Base Address Register. */
5421 {
5422 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5423 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5424 if (fVerbose)
5425 {
5426 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5427 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5428 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5429 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5430 }
5431 }
5432 /* Exclusion Range Limit Register. */
5433 {
5434 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5435 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5436 if (fVerbose)
5437 {
5438 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5439 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5440 }
5441 }
5442 /* Extended Feature Register. */
5443 {
5444 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5445 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5446 if (fVerbose)
5447 {
5448 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5449 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5450 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5451 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5452 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5453 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5454 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5455 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5456 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5457 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5458 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5459 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5460 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5461 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5462 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5463 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5464 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5465 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5466 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5467 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5468 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5469 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5470 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5471 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5472 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5473 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5474 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5475 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5476 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5477 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5478 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5479 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5480 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5481 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5482 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5483 }
5484 }
5485 /* PPR Log Base Address Register. */
5486 {
5487 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5488 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5489 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5490 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5491 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5492 if (fVerbose)
5493 {
5494 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5495 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5496 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5497 cEntries, cbBuffer);
5498 }
5499 }
5500 /* Hardware Event (Hi) Register. */
5501 {
5502 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5503 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5504 if (fVerbose)
5505 {
5506 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5507 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5508 }
5509 }
5510 /* Hardware Event (Lo) Register. */
5511 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5512 /* Hardware Event Status. */
5513 {
5514 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5515 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5516 if (fVerbose)
5517 {
5518 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5519 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5520 }
5521 }
5522 /* Guest Virtual-APIC Log Base Address Register. */
5523 {
5524 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5525 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5526 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5527 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5528 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5529 if (fVerbose)
5530 {
5531 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5532 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5533 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5534 cEntries, cbBuffer);
5535 }
5536 }
5537 /* Guest Virtual-APIC Log Tail Address Register. */
5538 {
5539 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5540 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5541 if (fVerbose)
5542 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5543 }
5544 /* PPR Log B Base Address Register. */
5545 {
5546 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5547 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5548 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5549 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5550 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5551 if (fVerbose)
5552 {
5553 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5554 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5555 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5556 cEntries, cbBuffer);
5557 }
5558 }
5559 /* Event Log B Base Address Register. */
5560 {
5561 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5562 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5563 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5564 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5565 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5566 if (fVerbose)
5567 {
5568 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5569 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5570 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5571 cEntries, cbBuffer);
5572 }
5573 }
5574 /* Device-Specific Feature Extension Register. */
5575 {
5576 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5577 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5578 if (fVerbose)
5579 {
5580 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5581 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5582 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5583 }
5584 }
5585 /* Device-Specific Control Extension Register. */
5586 {
5587 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5588 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5589 if (fVerbose)
5590 {
5591 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5592 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5593 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5594 }
5595 }
5596 /* Device-Specific Status Extension Register. */
5597 {
5598 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5599 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5600 if (fVerbose)
5601 {
5602 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5603 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5604 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5605 }
5606 }
5607 /* Miscellaneous Information Register (Lo and Hi). */
5608 {
5609 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5610 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5611 if (fVerbose)
5612 {
5613 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5614 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5615 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5616 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5617 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5618 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5619 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5620 }
5621 }
5622 /* MSI Capability Header. */
5623 {
5624 MSI_CAP_HDR_T MsiCapHdr;
5625 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5626 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5627 if (fVerbose)
5628 {
5629 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5630 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5631 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5632 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5633 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5634 }
5635 }
5636 /* MSI Address Register (Lo and Hi). */
5637 {
5638 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5639 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5640 MSIADDR MsiAddr;
5641 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5642 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5643 if (fVerbose)
5644 {
5645 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5646 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5647 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5648 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5649 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5650 }
5651 }
5652 /* MSI Data. */
5653 {
5654 MSIDATA MsiData;
5655 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5656 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5657 if (fVerbose)
5658 {
5659 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5660 MsiData.n.u8Vector);
5661 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5662 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5663 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5664 "level" : "edge");
5665 }
5666 }
5667 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5668 {
5669 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5670 MsiMapCapHdr.u32 = 0;
5671 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5672 if (fVerbose)
5673 {
5674 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5675 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5676 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5677 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5678 }
5679 }
5680 /* Performance Optimization Control Register. */
5681 {
5682 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5683 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5684 if (fVerbose)
5685 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5686 }
5687 /* XT (x2APIC) General Interrupt Control Register. */
5688 {
5689 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5690 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5691 if (fVerbose)
5692 {
5693 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5694 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5695 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5696 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5697 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5698 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5699 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5700 }
5701 }
5702 /* XT (x2APIC) PPR Interrupt Control Register. */
5703 {
5704 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5705 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5706 if (fVerbose)
5707 {
5708 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5709 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5710 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5711 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5712 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5713 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5714 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5715 }
5716 }
5717 /* XT (X2APIC) GA Log Interrupt Control Register. */
5718 {
5719 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5720 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5721 if (fVerbose)
5722 {
5723 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5724 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5725 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5726 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5727 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5728 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5729 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5730 }
5731 }
5732 /* MARC Registers. */
5733 {
5734 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5735 {
5736 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5737 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5738 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5739
5740 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5741 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5742 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5743 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5744
5745 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5746 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5747 }
5748 }
5749 /* Reserved Register. */
5750 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5751 /* Command Buffer Head Pointer Register. */
5752 {
5753 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5754 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5755 CmdBufHeadPtr.n.off);
5756 }
5757 /* Command Buffer Tail Pointer Register. */
5758 {
5759 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5760 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5761 CmdBufTailPtr.n.off);
5762 }
5763 /* Event Log Head Pointer Register. */
5764 {
5765 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5766 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5767 EvtLogHeadPtr.n.off);
5768 }
5769 /* Event Log Tail Pointer Register. */
5770 {
5771 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5772 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5773 EvtLogTailPtr.n.off);
5774 }
5775 /* Status Register. */
5776 {
5777 IOMMU_STATUS_T const Status = pThis->Status;
5778 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5779 if (fVerbose)
5780 {
5781 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5782 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5783 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5784 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5785 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5786 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5787 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5788 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5789 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5790 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5791 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5792 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5793 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5794 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5795 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5796 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5797 }
5798 }
5799 /* PPR Log Head Pointer. */
5800 {
5801 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5802 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5803 PprLogHeadPtr.n.off);
5804 }
5805 /* PPR Log Tail Pointer. */
5806 {
5807 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5808 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5809 PprLogTailPtr.n.off);
5810 }
5811 /* Guest Virtual-APIC Log Head Pointer. */
5812 {
5813 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5814 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5815 GALogHeadPtr.n.u12GALogPtr);
5816 }
5817 /* Guest Virtual-APIC Log Tail Pointer. */
5818 {
5819 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5820 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5821 GALogTailPtr.n.u12GALogPtr);
5822 }
5823 /* PPR Log B Head Pointer. */
5824 {
5825 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5826 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5827 PprLogBHeadPtr.n.off);
5828 }
5829 /* PPR Log B Tail Pointer. */
5830 {
5831 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5832 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5833 PprLogBTailPtr.n.off);
5834 }
5835 /* Event Log B Head Pointer. */
5836 {
5837 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5838 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5839 EvtLogBHeadPtr.n.off);
5840 }
5841 /* Event Log B Tail Pointer. */
5842 {
5843 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5844 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5845 EvtLogBTailPtr.n.off);
5846 }
5847 /* PPR Log Auto Response Register. */
5848 {
5849 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5850 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5851 if (fVerbose)
5852 {
5853 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5854 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5855 }
5856 }
5857 /* PPR Log Overflow Early Warning Indicator Register. */
5858 {
5859 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5860 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5861 if (fVerbose)
5862 {
5863 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5864 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5865 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5866 }
5867 }
5868 /* PPR Log Overflow Early Warning Indicator Register. */
5869 {
5870 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5871 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5872 if (fVerbose)
5873 {
5874 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5875 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5876 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5877 }
5878 }
5879}
5880
5881
5882/**
5883 * Dumps the DTE via the info callback helper.
5884 *
5885 * @param pHlp The info helper.
5886 * @param pDte The device table entry.
5887 * @param pszPrefix The string prefix.
5888 */
5889static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5890{
5891 AssertReturnVoid(pHlp);
5892 AssertReturnVoid(pDte);
5893 AssertReturnVoid(pszPrefix);
5894
5895 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5896 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5897 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5898 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5899 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5900 pDte->n.u40PageTableRootPtrLo << 12);
5901 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5902 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5903 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5904 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5905 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5906 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5907 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5908 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5909 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5910 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5911 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5912 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5913 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5914 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5915 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5916 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5917 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5918 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5919 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5920 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5921 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5922 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5923 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5924 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5925 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5926 {
5927 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
5928 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
5929 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
5930 cbIntrTable);
5931 }
5932 else
5933 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
5934 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
5935 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
5936 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
5937 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
5938 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
5939 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
5940 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
5941 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
5942 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
5943 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
5944 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
5945 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
5946 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
5947 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
5948 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
5949 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
5950 pHlp->pfnPrintf(pHlp, "\n");
5951}
5952
5953
5954/**
5955 * @callback_method_impl{FNDBGFHANDLERDEV}
5956 */
5957static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5958{
5959 if (pszArgs)
5960 {
5961 uint16_t idDevice = 0;
5962 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
5963 if (RT_SUCCESS(rc))
5964 {
5965 DTE_T Dte;
5966 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
5967 if (RT_SUCCESS(rc))
5968 {
5969 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
5970 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
5971 return;
5972 }
5973 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
5974 }
5975 else
5976 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
5977 }
5978 else
5979 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
5980}
5981
5982
5983# ifdef IOMMU_WITH_DTE_CACHE
5984/**
5985 * @callback_method_impl{FNDBGFHANDLERDEV}
5986 */
5987static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5988{
5989 RT_NOREF(pszArgs);
5990 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5991 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
5992
5993 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
5994 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
5995 for (uint16_t i = 0; i < cDteCache; i++)
5996 {
5997 uint16_t const idDevice = pThis->aDeviceIds[i];
5998 if (idDevice)
5999 {
6000 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
6001 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6002 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6003 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6004
6005 PCDTECACHE pDteCache = &pThis->aDteCache[i];
6006 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
6007 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
6008 pHlp->pfnPrintf(pHlp, "\n");
6009 }
6010 }
6011 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6012}
6013# endif /* IOMMU_WITH_DTE_CACHE */
6014
6015
6016# ifdef IOMMU_WITH_IOTLBE_CACHE
6017/**
6018 * @callback_method_impl{FNDBGFHANDLERDEV}
6019 */
6020static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6021{
6022 if (pszArgs)
6023 {
6024 uint16_t idDomain = 0;
6025 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6026 if (RT_SUCCESS(rc))
6027 {
6028 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6029 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6030 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6031 IOTLBEINFOARG Args;
6032 Args.pIommuR3 = pThisR3;
6033 Args.pHlp = pHlp;
6034 Args.idDomain = idDomain;
6035
6036 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6037 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6038 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6039 }
6040 else
6041 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6042 }
6043 else
6044 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6045}
6046# endif /* IOMMU_WITH_IOTLBE_CACHE */
6047
6048
6049# ifdef IOMMU_WITH_IRTE_CACHE
6050/**
6051 * Gets the interrupt type name for an interrupt type in the IRTE.
6052 *
6053 * @returns The interrupt type name.
6054 * @param uIntrType The interrupt type (as specified in the IRTE).
6055 */
6056static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6057{
6058 switch (uIntrType)
6059 {
6060 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6061 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6062 default: return "<Reserved>";
6063 }
6064}
6065
6066
6067/**
6068 * @callback_method_impl{FNDBGFHANDLERDEV}
6069 */
6070static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6071{
6072 RT_NOREF(pszArgs);
6073
6074 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6075 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6076
6077 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6078 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6079 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6080 {
6081 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6082 uint32_t const uKey = pIrteCache->uKey;
6083 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6084 {
6085 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6086 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6087 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6088 idxIrte, offIrte, idDevice,
6089 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6090 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6091 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6092
6093 PCIRTE_T pIrte = &pIrteCache->Irte;
6094 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6095 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6096 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6097 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6098 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6099 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6100 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6101 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6102 pHlp->pfnPrintf(pHlp, "\n");
6103 }
6104 }
6105 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6106}
6107# endif /* IOMMU_WITH_IRTE_CACHE */
6108
6109
6110/**
6111 * @callback_method_impl{FNDBGFHANDLERDEV}
6112 */
6113static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6114{
6115 RT_NOREF(pszArgs);
6116
6117 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6118 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6119 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6120 NOREF(pPciDev);
6121
6122 uint8_t cSegments = 0;
6123 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6124 {
6125 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6126 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6127 if (GCPhysDevTab)
6128 ++cSegments;
6129 }
6130
6131 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6132 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6133 if (!cSegments)
6134 return;
6135
6136 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6137 {
6138 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6139 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6140 if (GCPhysDevTab)
6141 {
6142 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6143 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6144
6145 void *pvDevTab = RTMemAllocZ(cbDevTab);
6146 if (RT_LIKELY(pvDevTab))
6147 {
6148 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6149 if (RT_SUCCESS(rc))
6150 {
6151 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6152 {
6153 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6154 if ( pDte->n.u1Valid
6155 && pDte->n.u1TranslationValid
6156 && pDte->n.u3Mode != 0)
6157 {
6158 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6159 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6160 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6161 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6162 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6163 pHlp->pfnPrintf(pHlp, "\n");
6164 }
6165 }
6166 pHlp->pfnPrintf(pHlp, "\n");
6167 }
6168 else
6169 {
6170 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6171 cbDevTab, rc);
6172 }
6173
6174 RTMemFree(pvDevTab);
6175 }
6176 else
6177 {
6178 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6179 return;
6180 }
6181 }
6182 }
6183}
6184
6185
6186/**
6187 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6188 */
6189static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6190{
6191 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6192 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6193 LogFlowFunc(("\n"));
6194
6195 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6196 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6197 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6198 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6199 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6200 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6201 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6202
6203 /* Next, save all registers that can be modified by the guest. */
6204 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6205
6206 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6207 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6208 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6209 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6210
6211 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6212 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6213 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6214 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6215 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6216 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6217#if 0
6218 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6219#endif
6220
6221 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6222 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6223 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6224 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6225
6226 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6227 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6228
6229 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6230 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6231
6232#if 0
6233 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6234 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6235 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6236
6237 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6238#endif
6239 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6240
6241 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6242 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6243 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6244
6245 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6246 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6247 for (size_t i = 0; i < cMarcApers; i++)
6248 {
6249 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6250 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6251 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6252 }
6253
6254#if 0
6255 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6256#endif
6257
6258 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6259 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6260 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6261 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6262
6263 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6264
6265 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6266 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6267
6268 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6269 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6270
6271 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6272 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6273
6274 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6275 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6276
6277 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6278 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6279 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6280
6281 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6282}
6283
6284
6285/**
6286 * @callback_method_impl{FNSSMDEVLOADEXEC}
6287 */
6288static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6289{
6290 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6291 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6292 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6293 LogFlowFunc(("\n"));
6294
6295 /* Validate. */
6296 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6297 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6298 {
6299 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6300 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6301 }
6302
6303 /* Load ExtFeat and other read-only registers first. */
6304 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6305 AssertRCReturn(rc, rc);
6306 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6307 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6308 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6309 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6310 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6311 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6312 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6313
6314 /* IOMMU base address register. */
6315 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6316 AssertRCReturn(rc, rc);
6317 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6318
6319 /* Device table base address registers. */
6320 uint8_t cDevTabBaseAddrs;
6321 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6322 AssertRCReturn(rc, rc);
6323 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6324 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6325 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6326 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6327 {
6328 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6329 AssertRCReturn(rc, rc);
6330 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6331 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6332 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6333 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6334 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6335 }
6336
6337 /* Command buffer base address register. */
6338 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6339 AssertRCReturn(rc, rc);
6340 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6341 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6342 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6343
6344 /* Event log base address register. */
6345 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6346 AssertRCReturn(rc, rc);
6347 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6348 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6349 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6350
6351 /* Control register. */
6352 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6353 AssertRCReturn(rc, rc);
6354 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6355 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6356 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6357
6358 /* Exclusion range base address register. */
6359 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6360 AssertRCReturn(rc, rc);
6361 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6362
6363 /* Exclusion range limit register. */
6364 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6365 AssertRCReturn(rc, rc);
6366 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6367 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6368
6369#if 0
6370 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6371#endif
6372
6373 /* PPR log base address register. */
6374 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6375 AssertRCReturn(rc, rc);
6376 Assert(!pThis->ExtFeat.n.u1PprSup);
6377
6378 /* Hardware event (Hi) register. */
6379 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6380 AssertRCReturn(rc, rc);
6381
6382 /* Hardware event (Lo) register. */
6383 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6384 AssertRCReturn(rc, rc);
6385
6386 /* Hardware event status register. */
6387 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6388 AssertRCReturn(rc, rc);
6389 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6390
6391 /* Guest Virtual-APIC log base address register. */
6392 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6393 AssertRCReturn(rc, rc);
6394 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6395
6396 /* Guest Virtual-APIC log tail address register. */
6397 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6398 AssertRCReturn(rc, rc);
6399 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6400
6401 /* PPR log-B base address register. */
6402 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6403 AssertRCReturn(rc, rc);
6404 Assert(!pThis->ExtFeat.n.u1PprSup);
6405
6406 /* Event log-B base address register. */
6407 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6408 AssertRCReturn(rc, rc);
6409 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6410
6411#if 0
6412 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6413 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6414 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6415
6416 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6417#endif
6418
6419 /* Performance optimization control register. */
6420 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6421 AssertRCReturn(rc, rc);
6422 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6423
6424 /* x2APIC registers. */
6425 {
6426 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6427
6428 /* x2APIC general interrupt control register. */
6429 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6430 AssertRCReturn(rc, rc);
6431
6432 /* x2APIC PPR interrupt control register. */
6433 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6434 AssertRCReturn(rc, rc);
6435
6436 /* x2APIC GA log interrupt control register. */
6437 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6438 AssertRCReturn(rc, rc);
6439 }
6440
6441 /* MARC (Memory Access and Routing) registers. */
6442 {
6443 uint8_t cMarcApers;
6444 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6445 AssertRCReturn(rc, rc);
6446 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6447 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6448 for (uint8_t i = 0; i < cMarcApers; i++)
6449 {
6450 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6451 AssertRCReturn(rc, rc);
6452
6453 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6454 AssertRCReturn(rc, rc);
6455
6456 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6457 AssertRCReturn(rc, rc);
6458 }
6459 Assert(!pThis->ExtFeat.n.u2MarcSup);
6460 }
6461
6462#if 0
6463 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6464#endif
6465
6466 /* Command buffer head pointer register. */
6467 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6468 AssertRCReturn(rc, rc);
6469 {
6470 /*
6471 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6472 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6473 * we shouldn't see such values in the saved state.
6474 */
6475 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6476 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6477 Assert(cbBuf <= _512K);
6478 AssertLogRelMsgReturn(offBuf < cbBuf,
6479 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6480 }
6481
6482 /* Command buffer tail pointer register. */
6483 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6484 AssertRCReturn(rc, rc);
6485 {
6486 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6487 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6488 Assert(cbBuf <= _512K);
6489 AssertLogRelMsgReturn(offBuf < cbBuf,
6490 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6491 }
6492
6493 /* Event log head pointer register. */
6494 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6495 AssertRCReturn(rc, rc);
6496 {
6497 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6498 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6499 Assert(cbBuf <= _512K);
6500 AssertLogRelMsgReturn(offBuf < cbBuf,
6501 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6502 }
6503
6504 /* Event log tail pointer register. */
6505 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6506 AssertRCReturn(rc, rc);
6507 {
6508 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6509 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6510 Assert(cbBuf <= _512K);
6511 AssertLogRelMsgReturn(offBuf < cbBuf,
6512 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6513 }
6514
6515 /* Status register. */
6516 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6517 AssertRCReturn(rc, rc);
6518 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6519
6520 /* PPR log head pointer register. */
6521 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6522 AssertRCReturn(rc, rc);
6523 Assert(!pThis->ExtFeat.n.u1PprSup);
6524
6525 /* PPR log tail pointer register. */
6526 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6527 AssertRCReturn(rc, rc);
6528 Assert(!pThis->ExtFeat.n.u1PprSup);
6529
6530 /* Guest Virtual-APIC log head pointer register. */
6531 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6532 AssertRCReturn(rc, rc);
6533 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6534
6535 /* Guest Virtual-APIC log tail pointer register. */
6536 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6537 AssertRCReturn(rc, rc);
6538 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6539
6540 /* PPR log-B head pointer register. */
6541 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6542 AssertRCReturn(rc, rc);
6543 Assert(!pThis->ExtFeat.n.u1PprSup);
6544
6545 /* PPR log-B head pointer register. */
6546 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6547 AssertRCReturn(rc, rc);
6548 Assert(!pThis->ExtFeat.n.u1PprSup);
6549
6550 /* Event log-B head pointer register. */
6551 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6552 AssertRCReturn(rc, rc);
6553 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6554
6555 /* Event log-B tail pointer register. */
6556 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6557 AssertRCReturn(rc, rc);
6558 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6559
6560 /* PPR log auto response register. */
6561 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6562 AssertRCReturn(rc, rc);
6563 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6564
6565 /* PPR log overflow early indicator register. */
6566 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6567 AssertRCReturn(rc, rc);
6568 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6569
6570 /* PPR log-B overflow early indicator register. */
6571 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6572 AssertRCReturn(rc, rc);
6573 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6574
6575 /* End marker. */
6576 {
6577 uint32_t uEndMarker;
6578 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6579 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6580 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6581 rcErr);
6582 }
6583
6584 return rc;
6585}
6586
6587
6588/**
6589 * @callback_method_impl{FNSSMDEVLOADDONE}
6590 */
6591static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6592{
6593 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6594 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6595 RT_NOREF(pSSM);
6596 LogFlowFunc(("\n"));
6597
6598 /* Sanity. */
6599 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6600 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6601
6602 int rc;
6603 IOMMU_LOCK(pDevIns, pThisR3);
6604
6605 /* Map MMIO regions if the IOMMU BAR is enabled. */
6606 if (pThis->IommuBar.n.u1Enable)
6607 rc = iommuAmdR3MmioSetup(pDevIns);
6608 else
6609 rc = VINF_SUCCESS;
6610
6611 /* Wake up the command thread if commands need processing. */
6612 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6613
6614 IOMMU_UNLOCK(pDevIns, pThisR3);
6615
6616 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6617 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6618 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6619 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6620 pThis->ExtFeat.u64));
6621 return rc;
6622}
6623
6624
6625/**
6626 * @interface_method_impl{PDMDEVREG,pfnReset}
6627 */
6628static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6629{
6630 /*
6631 * Resets read-write portion of the IOMMU state.
6632 *
6633 * NOTE! State not initialized here is expected to be initialized during
6634 * device construction and remain read-only through the lifetime of the VM.
6635 */
6636 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6637 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6638 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6639 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6640 LogFlowFunc(("\n"));
6641
6642 IOMMU_LOCK_NORET(pDevIns, pThisR3);
6643
6644 RT_ZERO(pThis->aDevTabBaseAddrs);
6645
6646 pThis->CmdBufBaseAddr.u64 = 0;
6647 pThis->CmdBufBaseAddr.n.u4Len = 8;
6648
6649 pThis->EvtLogBaseAddr.u64 = 0;
6650 pThis->EvtLogBaseAddr.n.u4Len = 8;
6651
6652 pThis->Ctrl.u64 = 0;
6653 pThis->Ctrl.n.u1Coherent = 1;
6654 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6655
6656 pThis->ExclRangeBaseAddr.u64 = 0;
6657 pThis->ExclRangeLimit.u64 = 0;
6658
6659 pThis->PprLogBaseAddr.u64 = 0;
6660 pThis->PprLogBaseAddr.n.u4Len = 8;
6661
6662 pThis->HwEvtHi.u64 = 0;
6663 pThis->HwEvtLo = 0;
6664 pThis->HwEvtStatus.u64 = 0;
6665
6666 pThis->GALogBaseAddr.u64 = 0;
6667 pThis->GALogBaseAddr.n.u4Len = 8;
6668 pThis->GALogTailAddr.u64 = 0;
6669
6670 pThis->PprLogBBaseAddr.u64 = 0;
6671 pThis->PprLogBBaseAddr.n.u4Len = 8;
6672
6673 pThis->EvtLogBBaseAddr.u64 = 0;
6674 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6675
6676 pThis->PerfOptCtrl.u32 = 0;
6677
6678 pThis->XtGenIntrCtrl.u64 = 0;
6679 pThis->XtPprIntrCtrl.u64 = 0;
6680 pThis->XtGALogIntrCtrl.u64 = 0;
6681
6682 RT_ZERO(pThis->aMarcApers);
6683
6684 pThis->CmdBufHeadPtr.u64 = 0;
6685 pThis->CmdBufTailPtr.u64 = 0;
6686 pThis->EvtLogHeadPtr.u64 = 0;
6687 pThis->EvtLogTailPtr.u64 = 0;
6688
6689 pThis->Status.u64 = 0;
6690
6691 pThis->PprLogHeadPtr.u64 = 0;
6692 pThis->PprLogTailPtr.u64 = 0;
6693
6694 pThis->GALogHeadPtr.u64 = 0;
6695 pThis->GALogTailPtr.u64 = 0;
6696
6697 pThis->PprLogBHeadPtr.u64 = 0;
6698 pThis->PprLogBTailPtr.u64 = 0;
6699
6700 pThis->EvtLogBHeadPtr.u64 = 0;
6701 pThis->EvtLogBTailPtr.u64 = 0;
6702
6703 pThis->PprLogAutoResp.u64 = 0;
6704 pThis->PprLogOverflowEarly.u64 = 0;
6705 pThis->PprLogBOverflowEarly.u64 = 0;
6706
6707 pThis->IommuBar.u64 = 0;
6708 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6709 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6710
6711 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6712
6713 IOMMU_UNLOCK(pDevIns, pThisR3);
6714
6715#ifdef IOMMU_WITH_DTE_CACHE
6716 iommuAmdDteCacheRemoveAll(pDevIns);
6717#endif
6718#ifdef IOMMU_WITH_IOTLBE_CACHE
6719 iommuAmdIotlbRemoveAll(pDevIns);
6720#endif
6721#ifdef IOMMU_WITH_IRTE_CACHE
6722 iommuAmdIrteCacheRemoveAll(pDevIns);
6723#endif
6724}
6725
6726
6727/**
6728 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6729 */
6730static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6731{
6732 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6733 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6734 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6735 LogFlowFunc(("\n"));
6736
6737 IOMMU_LOCK_NORET(pDevIns, pThisR3);
6738
6739 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6740 {
6741 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6742 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6743 }
6744
6745#ifdef IOMMU_WITH_IOTLBE_CACHE
6746 if (pThisR3->paIotlbes)
6747 {
6748 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6749 pThisR3->paIotlbes = NULL;
6750 pThisR3->idxUnusedIotlbe = 0;
6751 }
6752#endif
6753
6754 IOMMU_UNLOCK(pDevIns, pThisR3);
6755 return VINF_SUCCESS;
6756}
6757
6758
6759/**
6760 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6761 */
6762static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6763{
6764 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6765 RT_NOREF(pCfg);
6766
6767 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6768 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6769 pThis->u32Magic = IOMMU_MAGIC;
6770 pThisR3->pDevInsR3 = pDevIns;
6771
6772 LogFlowFunc(("iInstance=%d\n", iInstance));
6773
6774 /*
6775 * Register the IOMMU with PDM.
6776 */
6777 PDMIOMMUREGR3 IommuReg;
6778 RT_ZERO(IommuReg);
6779 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6780 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6781 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6782 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6783 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6784 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6785 if (RT_FAILURE(rc))
6786 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6787 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6788 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6789 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6790 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6791 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6792 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6793 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6794 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6795
6796 /*
6797 * We will use PDM's critical section (via helpers) for the IOMMU device.
6798 */
6799 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6800 AssertRCReturn(rc, rc);
6801
6802 /*
6803 * Initialize read-only PCI configuration space.
6804 */
6805 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6806 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6807
6808 /* Header. */
6809 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6810 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6811 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6812 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6813 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6814 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6815 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6816 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6817 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6818 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6819 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6820 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6821 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6822 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6823
6824 /* Capability Header. */
6825 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6826 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6827 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6828 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6829 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6830 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6831 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6832 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6833 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6834 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6835 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6836
6837 /* Base Address Register. */
6838 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6839 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6840
6841 /* IOMMU Range Register. */
6842 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6843
6844 /* Misc. Information Register. */
6845 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6846 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6847 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6848 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6849 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6850 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6851 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6852 uint32_t const uMiscInfoReg1 = 0;
6853 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6854 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6855
6856 /* MSI Capability Header register. */
6857 PDMMSIREG MsiReg;
6858 RT_ZERO(MsiReg);
6859 MsiReg.cMsiVectors = 1;
6860 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6861 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6862 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6863
6864 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6865#if 0
6866 /* MSI Address Lo. */
6867 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6868 /* MSI Address Hi. */
6869 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6870 /* MSI Data. */
6871 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6872#endif
6873
6874#if 0
6875 /** @todo IOMMU: I don't know if we need to support this, enable later if
6876 * required. */
6877 /* MSI Mapping Capability Header register. */
6878 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6879 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6880 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6881 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6882 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6883 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6884 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6885#endif
6886
6887 /*
6888 * Register the PCI function with PDM.
6889 */
6890 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6891 AssertLogRelRCReturn(rc, rc);
6892
6893 /*
6894 * Register MSI support for the PCI device.
6895 * This must be done -after- registering it as a PCI device!
6896 */
6897 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6898 AssertRCReturn(rc, rc);
6899
6900 /*
6901 * Intercept PCI config. space accesses.
6902 */
6903 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6904 AssertLogRelRCReturn(rc, rc);
6905
6906 /*
6907 * Create the MMIO region.
6908 * Mapping of the region is done when software configures it via PCI config space.
6909 */
6910 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6911 NULL /* pvUser */,
6912 IOMMMIO_FLAGS_READ_DWORD_QWORD
6913 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
6914 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
6915 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
6916 "AMD-IOMMU", &pThis->hMmio);
6917 AssertLogRelRCReturn(rc, rc);
6918
6919 /*
6920 * Register saved state handlers.
6921 */
6922 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
6923 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
6924 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
6925 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
6926 AssertLogRelRCReturn(rc, rc);
6927
6928 /*
6929 * Register debugger info items.
6930 */
6931 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6932 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
6933 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
6934#ifdef IOMMU_WITH_IOTLBE_CACHE
6935 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
6936#endif
6937#ifdef IOMMU_WITH_DTE_CACHE
6938 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
6939#endif
6940#ifdef IOMMU_WITH_IRTE_CACHE
6941 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
6942#endif
6943
6944# ifdef VBOX_WITH_STATISTICS
6945 /*
6946 * Statistics.
6947 */
6948 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
6949 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
6950
6951 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
6952 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
6953
6954 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
6955 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
6956
6957 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
6958 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
6959
6960 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
6961 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
6962
6963 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
6964 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
6965
6966 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
6967 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
6968
6969 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
6970 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
6971 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
6972 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
6973 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
6974 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
6975 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
6976 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
6977 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
6978
6979
6980 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
6981 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
6982
6983 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
6984 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
6985
6986 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
6987 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
6988
6989 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
6990 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
6991 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
6992 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
6993 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
6994 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
6995 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
6996
6997 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
6998 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
6999# endif
7000
7001 /*
7002 * Create the command thread and its event semaphore.
7003 */
7004 char szDevIommu[64];
7005 RT_ZERO(szDevIommu);
7006 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
7007 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
7008 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
7009 AssertLogRelRCReturn(rc, rc);
7010
7011 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7012 AssertLogRelRCReturn(rc, rc);
7013
7014#ifdef IOMMU_WITH_DTE_CACHE
7015 /*
7016 * Initialize the critsect of the cache.
7017 */
7018 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7019 AssertLogRelRCReturn(rc, rc);
7020
7021 /* Several places in this code relies on this basic assumption - assert it! */
7022 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7023#endif
7024
7025#ifdef IOMMU_WITH_IOTLBE_CACHE
7026 /*
7027 * Allocate IOTLB entries.
7028 * This is allocated upfront since we expect a relatively small number of entries,
7029 * is more cache-line efficient and easier to track least recently used entries for
7030 * eviction when the cache is full. This also avoids unpredictable behavior during
7031 * the lifetime of the VM if the hyperheap gets full.
7032 */
7033 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7034 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7035 if (!pThisR3->paIotlbes)
7036 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7037 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7038 RTListInit(&pThisR3->LstLruIotlbe);
7039 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7040#endif
7041
7042 /*
7043 * Initialize read-only registers.
7044 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7045 */
7046 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7047 pThis->ExtFeat.u64 = 0;
7048 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7049 //pThis->ExtFeat.n.u1PprSup = 0;
7050 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7051 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7052 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7053 pThis->ExtFeat.n.u1InvAllSup = 1;
7054 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7055 pThis->ExtFeat.n.u1HwErrorSup = 1;
7056 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7057 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7058 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7059 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7060 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7061 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7062 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7063 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7064 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7065 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7066 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7067 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7068 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7069 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7070 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7071 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7072 //pThis->ExtFeat.n.u2MarcSup = 0;
7073 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7074 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7075 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7076 //pThis->ExtFeat.n.u1GstIoSup = 0;
7077 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7078 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7079 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7080 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7081 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7082 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7083 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7084
7085 pThis->DevSpecificFeat.u64 = 0;
7086 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7087 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7088
7089 pThis->DevSpecificCtrl.u64 = 0;
7090 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7091 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7092
7093 pThis->DevSpecificStatus.u64 = 0;
7094 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7095 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7096
7097 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7098
7099 pThis->RsvdReg = 0;
7100
7101 /*
7102 * Initialize parts of the IOMMU state as it would during reset.
7103 * Also initializes non-zero initial values like IRTE cache keys.
7104 * Must be called -after- initializing PCI config. space registers.
7105 */
7106 iommuAmdR3Reset(pDevIns);
7107
7108 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7109 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7110 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7111 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7112 pThis->ExtFeat.u64));
7113 return VINF_SUCCESS;
7114}
7115
7116#else
7117
7118/**
7119 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7120 */
7121static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7122{
7123 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7124 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7125 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7126 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7127
7128 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7129 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7130 AssertRCReturn(rc, rc);
7131
7132 /* Set up the MMIO RZ handlers. */
7133 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7134 AssertRCReturn(rc, rc);
7135
7136 /* Set up the IOMMU RZ callbacks. */
7137 PDMIOMMUREGCC IommuReg;
7138 RT_ZERO(IommuReg);
7139 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7140 IommuReg.idxIommu = pThis->idxIommu;
7141 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7142 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7143 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7144 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7145 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7146 AssertRCReturn(rc, rc);
7147 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7148 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7149 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7150 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
7151 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
7152 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
7153 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
7154 return VINF_SUCCESS;
7155}
7156#endif
7157
7158
7159/**
7160 * The device registration structure.
7161 */
7162const PDMDEVREG g_DeviceIommuAmd =
7163{
7164 /* .u32Version = */ PDM_DEVREG_VERSION,
7165 /* .uReserved0 = */ 0,
7166 /* .szName = */ "iommu-amd",
7167 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7168 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7169 /* .cMaxInstances = */ 1,
7170 /* .uSharedVersion = */ 42,
7171 /* .cbInstanceShared = */ sizeof(IOMMU),
7172 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7173 /* .cbInstanceRC = */ sizeof(IOMMURC),
7174 /* .cMaxPciDevices = */ 1,
7175 /* .cMaxMsixVectors = */ 0,
7176 /* .pszDescription = */ "IOMMU (AMD)",
7177#if defined(IN_RING3)
7178 /* .pszRCMod = */ "VBoxDDRC.rc",
7179 /* .pszR0Mod = */ "VBoxDDR0.r0",
7180 /* .pfnConstruct = */ iommuAmdR3Construct,
7181 /* .pfnDestruct = */ iommuAmdR3Destruct,
7182 /* .pfnRelocate = */ NULL,
7183 /* .pfnMemSetup = */ NULL,
7184 /* .pfnPowerOn = */ NULL,
7185 /* .pfnReset = */ iommuAmdR3Reset,
7186 /* .pfnSuspend = */ NULL,
7187 /* .pfnResume = */ NULL,
7188 /* .pfnAttach = */ NULL,
7189 /* .pfnDetach = */ NULL,
7190 /* .pfnQueryInterface = */ NULL,
7191 /* .pfnInitComplete = */ NULL,
7192 /* .pfnPowerOff = */ NULL,
7193 /* .pfnSoftReset = */ NULL,
7194 /* .pfnReserved0 = */ NULL,
7195 /* .pfnReserved1 = */ NULL,
7196 /* .pfnReserved2 = */ NULL,
7197 /* .pfnReserved3 = */ NULL,
7198 /* .pfnReserved4 = */ NULL,
7199 /* .pfnReserved5 = */ NULL,
7200 /* .pfnReserved6 = */ NULL,
7201 /* .pfnReserved7 = */ NULL,
7202#elif defined(IN_RING0)
7203 /* .pfnEarlyConstruct = */ NULL,
7204 /* .pfnConstruct = */ iommuAmdRZConstruct,
7205 /* .pfnDestruct = */ NULL,
7206 /* .pfnFinalDestruct = */ NULL,
7207 /* .pfnRequest = */ NULL,
7208 /* .pfnReserved0 = */ NULL,
7209 /* .pfnReserved1 = */ NULL,
7210 /* .pfnReserved2 = */ NULL,
7211 /* .pfnReserved3 = */ NULL,
7212 /* .pfnReserved4 = */ NULL,
7213 /* .pfnReserved5 = */ NULL,
7214 /* .pfnReserved6 = */ NULL,
7215 /* .pfnReserved7 = */ NULL,
7216#elif defined(IN_RC)
7217 /* .pfnConstruct = */ iommuAmdRZConstruct,
7218 /* .pfnReserved0 = */ NULL,
7219 /* .pfnReserved1 = */ NULL,
7220 /* .pfnReserved2 = */ NULL,
7221 /* .pfnReserved3 = */ NULL,
7222 /* .pfnReserved4 = */ NULL,
7223 /* .pfnReserved5 = */ NULL,
7224 /* .pfnReserved6 = */ NULL,
7225 /* .pfnReserved7 = */ NULL,
7226#else
7227# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7228#endif
7229 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7230};
7231
7232#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7233
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette