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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 88736

Last change on this file since 88736 was 88668, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Fix locking that got broken when the PDM lock was used instead of the device's own lock. We need to lock MMIO reads and writes.
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1/* $Id: DevIommuAmd.cpp 88668 2021-04-23 04:17:04Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26
27#include <iprt/x86.h>
28#include <iprt/string.h>
29#include <iprt/avl.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47
48/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
49#ifdef IN_RING3
50# define IOMMU_WITH_IOTLBE_CACHE
51#endif
52/** Enable the interrupt cache. */
53#define IOMMU_WITH_IRTE_CACHE
54
55/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
56#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
57# define IOMMU_WITH_DTE_CACHE
58/** The maximum number of device IDs in the cache. */
59# define IOMMU_DEV_CACHE_COUNT 16
60/** An empty device ID. */
61# define IOMMU_DTE_CACHE_KEY_NIL 0
62#endif
63
64#ifdef IOMMU_WITH_IRTE_CACHE
65/** The maximum number of IRTE cache entries. */
66# define IOMMU_IRTE_CACHE_COUNT 32
67/** A NIL IRTE cache entry key. */
68# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
69/** Gets the device ID from an IRTE cache entry key. */
70#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
71/** Gets the IOVA from the IOTLB entry key. */
72# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
73/** Makes an IRTE cache entry key.
74 *
75 * Bits 31:16 is the device ID (Bus, Device, Function).
76 * Bits 15:0 is the the offset into the IRTE table.
77 */
78# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
79#endif /* IOMMU_WITH_IRTE_CACHE */
80
81#ifdef IOMMU_WITH_IOTLBE_CACHE
82/** The maximum number of IOTLB entries. */
83# define IOMMU_IOTLBE_MAX 96
84/** The mask of bits covering the domain ID in the IOTLBE key. */
85# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
86/** The mask of bits covering the IOVA in the IOTLBE key. */
87# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
88/** The number of bits to shift for the domain ID of the IOTLBE key. */
89# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
90/** A NIL IOTLB key. */
91# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
92/** Gets the domain ID from an IOTLB entry key. */
93# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
94/** Gets the IOVA from the IOTLB entry key. */
95# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
96/** Makes an IOTLB entry key.
97 *
98 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
99 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
100 * so bottom 12 bits are free.
101 *
102 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
103 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
104 */
105# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
106 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
107#endif /* IOMMU_WITH_IOTLBE_CACHE */
108
109#ifdef IOMMU_WITH_DTE_CACHE
110/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
111 *
112 * Some of these flags are "basic" i.e. they correspond directly to their bits in
113 * the DTE. The rest of the flags are based on checks or operations on several DTE
114 * bits.
115 *
116 * The basic flags are:
117 * - VALID (DTE.V)
118 * - IO_PERM_READ (DTE.IR)
119 * - IO_PERM_WRITE (DTE.IW)
120 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
121 * masking consistent)
122 * - SUPPRESS_ALL_IOPF (DTE.SA)
123 * - SUPPRESS_IOPF (DTE.SE)
124 * - INTR_MAP_VALID (DTE.IV)
125 * - IGNORE_UNMAPPED_INTR (DTE.IG)
126 *
127 * @see iommuAmdGetBasicDevFlags()
128 * @{ */
129/** The DTE is present. */
130# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
131/** The DTE is valid. */
132# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
133/** The DTE permissions apply for address translations. */
134# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
135/** DTE permission - I/O read allowed. */
136# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
137/** DTE permission - I/O write allowed. */
138# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
139/** DTE permission - reserved. */
140# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
141/** Address translation required. */
142# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
143/** Suppress all I/O page faults. */
144# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
145/** Suppress I/O page faults. */
146# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
147/** Interrupt map valid. */
148# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
149/** Ignore unmapped interrupts. */
150# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
151/** An I/O page fault has been raised for this device. */
152# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
153/** Fixed and arbitrary interrupt control: Target Abort. */
154# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
155/** Fixed and arbitrary interrupt control: Forward unmapped. */
156# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
157/** Fixed and arbitrary interrupt control: Remapped. */
158# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
159/** Fixed and arbitrary interrupt control: Reserved. */
160# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
161/** @} */
162
163/** The number of bits to shift I/O device flags for DTE permissions. */
164# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
165/** The mask of DTE permissions in I/O device flags. */
166# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
167/** The number of bits to shift I/O device flags for interrupt control bits. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
169/** The mask of interrupt control bits in I/O device flags. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
171/** The number of bits to shift for ignore-unmapped interrupts bit. */
172# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
173
174/** Acquires the cache lock. */
175#define IOMMU_LOCK_CACHE(a_pDevIns, a_pThis) \
176 do { \
177 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
178 if (rcLock == VINF_SUCCESS) \
179 { /* likely */ } \
180 else \
181 { \
182 AssertRC(rcLock); \
183 return rcLock; \
184 } \
185 } while (0)
186
187/** Acquires the cache lock (asserts on failure). */
188# define IOMMU_LOCK_CACHE_NORET(a_pDevIns, a_pThis) \
189 do { \
190 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_SEM_BUSY); \
191 AssertRC(rcLock); \
192 } while (0)
193
194/** Releases the cache lock. */
195# define IOMMU_UNLOCK_CACHE(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
196#endif /* IOMMU_WITH_DTE_CACHE */
197
198/** Gets the page offset mask given the number of bits to shift. */
199#define IOMMU_GET_PAGE_OFF_MASK(a_cShift) (~(UINT64_C(0xffffffffffffffff) << (a_cShift)))
200
201/** Acquires the PDM lock. */
202#define IOMMU_LOCK(a_pDevIns, a_pThisCC, a_rcBusy) \
203 do { \
204 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)); \
205 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
206 { /* likely */ } \
207 else \
208 return rcLock; \
209 } while (0)
210
211/** Checks if the current thread owns the PDM lock. */
212# define IOMMU_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
213 do \
214 { \
215 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner((a_pDevIns))); \
216 NOREF(a_pThisCC); \
217 } while (0)
218
219/** Acquires the PDM lock (asserts on failure). */
220#define IOMMU_LOCK_NORET(a_pDevIns, a_pThisCC) \
221 do { \
222 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_SEM_BUSY); \
223 AssertRC(rcLock); \
224 } while (0)
225
226/** Releases the PDM lock. */
227# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
228
229
230/*********************************************************************************************************************************
231* Structures and Typedefs *
232*********************************************************************************************************************************/
233/**
234 * IOMMU operation (transaction).
235 */
236typedef enum IOMMUOP
237{
238 /** Address translation request. */
239 IOMMUOP_TRANSLATE_REQ = 0,
240 /** Memory read request. */
241 IOMMUOP_MEM_READ,
242 /** Memory write request. */
243 IOMMUOP_MEM_WRITE,
244 /** Interrupt request. */
245 IOMMUOP_INTR_REQ,
246 /** Command. */
247 IOMMUOP_CMD
248} IOMMUOP;
249/** Pointer to a IOMMU operation. */
250typedef IOMMUOP *PIOMMUOP;
251
252/**
253 * I/O page lookup.
254 */
255typedef struct IOPAGELOOKUP
256{
257 /** The translated system physical address. */
258 RTGCPHYS GCPhysSpa;
259 /** The number of offset bits in the system physical address. */
260 uint8_t cShift;
261 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
262 uint8_t fPerm;
263} IOPAGELOOKUP;
264/** Pointer to an I/O page lookup. */
265typedef IOPAGELOOKUP *PIOPAGELOOKUP;
266/** Pointer to a const I/O page lookup. */
267typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
268
269/**
270 * I/O address range.
271 */
272typedef struct IOADDRRANGE
273{
274 /** The address (virtual or physical). */
275 uint64_t uAddr;
276 /** The size of the access in bytes. */
277 size_t cb;
278 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
279 uint8_t fPerm;
280} IOADDRRANGE;
281/** Pointer to an I/O address range. */
282typedef IOADDRRANGE *PIOADDRRANGE;
283/** Pointer to a const I/O address range. */
284typedef IOADDRRANGE const *PCIOADDRRANGE;
285
286#ifdef IOMMU_WITH_DTE_CACHE
287/**
288 * Device Table Entry Cache.
289 */
290typedef struct DTECACHE
291{
292 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
293 uint16_t fFlags;
294 /** The domain ID assigned for this device by software. */
295 uint16_t idDomain;
296} DTECACHE;
297/** Pointer to an I/O device struct. */
298typedef DTECACHE *PDTECACHE;
299/** Pointer to a const I/O device struct. */
300typedef DTECACHE *PCDTECACHE;
301AssertCompileSize(DTECACHE, 4);
302#endif /* IOMMU_WITH_DTE_CACHE */
303
304#ifdef IOMMU_WITH_IOTLBE_CACHE
305/**
306 * I/O TLB Entry.
307 * Keep this as small and aligned as possible.
308 */
309typedef struct IOTLBE
310{
311 /** The AVL tree node. */
312 AVLU64NODECORE Core;
313 /** The least recently used (LRU) list node. */
314 RTLISTNODE NdLru;
315 /** The I/O page lookup results of the translation. */
316 IOPAGELOOKUP PageLookup;
317 /** Whether the entry needs to be evicted from the cache. */
318 bool fEvictPending;
319} IOTLBE;
320/** Pointer to an IOMMU I/O TLB entry struct. */
321typedef IOTLBE *PIOTLBE;
322/** Pointer to a const IOMMU I/O TLB entry struct. */
323typedef IOTLBE const *PCIOTLBE;
324AssertCompileSizeAlignment(IOTLBE, 8);
325AssertCompileMemberOffset(IOTLBE, Core, 0);
326#endif /* IOMMU_WITH_IOTLBE_CACHE */
327
328#ifdef IOMMU_WITH_IRTE_CACHE
329/**
330 * Interrupt Remap Table Entry Cache.
331 */
332typedef struct IRTECACHE
333{
334 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
335 uint32_t uKey;
336 /** The IRTE. */
337 IRTE_T Irte;
338} IRTECACHE;
339/** Pointer to an IRTE cache struct. */
340typedef IRTECACHE *PIRTECACHE;
341/** Pointer to a const IRTE cache struct. */
342typedef IRTECACHE const *PCIRTECACHE;
343AssertCompileSizeAlignment(IRTECACHE, 4);
344#endif /* IOMMU_WITH_IRTE_CACHE */
345
346/**
347 * The shared IOMMU device state.
348 */
349typedef struct IOMMU
350{
351 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
352 uint32_t idxIommu;
353 /** IOMMU magic. */
354 uint32_t u32Magic;
355
356 /** The MMIO handle. */
357 IOMMMIOHANDLE hMmio;
358 /** The event semaphore the command thread waits on. */
359 SUPSEMEVENT hEvtCmdThread;
360 /** Whether the command thread has been signaled for wake up. */
361 bool volatile fCmdThreadSignaled;
362 /** Padding. */
363 bool afPadding0[7];
364
365#ifdef IOMMU_WITH_DTE_CACHE
366 /** The critsect that protects the cache from concurrent access. */
367 PDMCRITSECT CritSectCache;
368 /** Array of device IDs. */
369 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
370 /** Array of DTE cache entries. */
371 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
372#endif
373#ifdef IOMMU_WITH_IRTE_CACHE
374 /** Array of IRTE cache entries. */
375 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
376#endif
377
378 /** @name PCI: Base capability block registers.
379 * @{ */
380 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
381 /** @} */
382
383 /** @name MMIO: Control and status registers.
384 * @{ */
385 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
386 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
387 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
388 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
389 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
390 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
391 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
392 /** @} */
393
394 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
395 * @{ */
396 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
397 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
398 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
399 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
400 /** @} */
401
402 /** @todo IOMMU: SMI filter. */
403
404 /** @name MMIO: Guest Virtual-APIC Log registers.
405 * @{ */
406 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
407 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
408 /** @} */
409
410 /** @name MMIO: Alternate PPR and Event Log registers.
411 * @{ */
412 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
413 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
414 /** @} */
415
416 /** @name MMIO: Device-specific feature registers.
417 * @{ */
418 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
419 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
420 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
421 /** @} */
422
423 /** @name MMIO: MSI Capability Block registers.
424 * @{ */
425 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
426 /** @} */
427
428 /** @name MMIO: Performance Optimization Control registers.
429 * @{ */
430 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
431 /** @} */
432
433 /** @name MMIO: x2APIC Control registers.
434 * @{ */
435 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
436 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
437 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
438 /** @} */
439
440 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
441 * @{ */
442 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
443 /** @} */
444
445 /** @name MMIO: Reserved register.
446 * @{ */
447 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
448 /** @} */
449
450 /** @name MMIO: Command and Event Log pointer registers.
451 * @{ */
452 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
453 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
454 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
455 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
456 /** @} */
457
458 /** @name MMIO: Command and Event Status register.
459 * @{ */
460 IOMMU_STATUS_T Status; /**< IOMMU status register. */
461 /** @} */
462
463 /** @name MMIO: PPR Log Head and Tail pointer registers.
464 * @{ */
465 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
466 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
467 /** @} */
468
469 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
470 * @{ */
471 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
472 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
473 /** @} */
474
475 /** @name MMIO: PPR Log B Head and Tail pointer registers.
476 * @{ */
477 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
478 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
479 /** @} */
480
481 /** @name MMIO: Event Log B Head and Tail pointer registers.
482 * @{ */
483 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
484 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
485 /** @} */
486
487 /** @name MMIO: PPR Log Overflow protection registers.
488 * @{ */
489 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
490 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
491 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
492 /** @} */
493
494 /** @todo IOMMU: IOMMU Event counter registers. */
495
496#ifdef VBOX_WITH_STATISTICS
497 /** @name IOMMU: Stat counters.
498 * @{ */
499 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
500 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
501 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
502 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
503
504 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
505 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
506
507 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
508 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
509 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
510 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
511
512 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
513 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
514 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
515 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
516
517 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
518 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
519 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
520 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
521 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
522 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
523 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
524 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
525 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
526
527 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
528 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
529
530 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
531 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
532
533 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
534 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
535
536 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
537 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
538 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
539 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
540 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
541 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
542 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
543
544 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
545 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
546 /** @} */
547#endif
548} IOMMU;
549/** Pointer to the IOMMU device state. */
550typedef IOMMU *PIOMMU;
551/** Pointer to the const IOMMU device state. */
552typedef const IOMMU *PCIOMMU;
553AssertCompileMemberAlignment(IOMMU, hMmio, 8);
554#ifdef IOMMU_WITH_DTE_CACHE
555AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
556AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
557AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
558#endif
559#ifdef IOMMU_WITH_IRTE_CACHE
560AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
561#endif
562AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
563AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
564AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
565AssertCompileMemberAlignment(IOMMU, Status, 8);
566
567/**
568 * The ring-3 IOMMU device state.
569 */
570typedef struct IOMMUR3
571{
572 /** Device instance. */
573 PPDMDEVINSR3 pDevInsR3;
574 /** The IOMMU helpers. */
575 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
576 /** The command thread handle. */
577 R3PTRTYPE(PPDMTHREAD) pCmdThread;
578#ifdef IOMMU_WITH_IOTLBE_CACHE
579 /** Pointer to array of pre-allocated IOTLBEs. */
580 PIOTLBE paIotlbes;
581 /** Maps [DomainId,Iova] to [IOTLBE]. */
582 AVLU64TREE TreeIotlbe;
583 /** LRU list anchor for IOTLB entries. */
584 RTLISTANCHOR LstLruIotlbe;
585 /** Index of the next unused IOTLB. */
586 uint32_t idxUnusedIotlbe;
587 /** Number of cached IOTLB entries in the tree. */
588 uint32_t cCachedIotlbes;
589#endif
590} IOMMUR3;
591/** Pointer to the ring-3 IOMMU device state. */
592typedef IOMMUR3 *PIOMMUR3;
593/** Pointer to the const ring-3 IOMMU device state. */
594typedef const IOMMUR3 *PCIOMMUR3;
595#ifdef IOMMU_WITH_IOTLBE_CACHE
596AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
597AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
598AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
599#endif
600
601/**
602 * The ring-0 IOMMU device state.
603 */
604typedef struct IOMMUR0
605{
606 /** Device instance. */
607 PPDMDEVINSR0 pDevInsR0;
608 /** The IOMMU helpers. */
609 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
610} IOMMUR0;
611/** Pointer to the ring-0 IOMMU device state. */
612typedef IOMMUR0 *PIOMMUR0;
613
614/**
615 * The raw-mode IOMMU device state.
616 */
617typedef struct IOMMURC
618{
619 /** Device instance. */
620 PPDMDEVINSRC pDevInsRC;
621 /** The IOMMU helpers. */
622 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
623} IOMMURC;
624/** Pointer to the raw-mode IOMMU device state. */
625typedef IOMMURC *PIOMMURC;
626
627/** The IOMMU device state for the current context. */
628typedef CTX_SUFF(IOMMU) IOMMUCC;
629/** Pointer to the IOMMU device state for the current context. */
630typedef CTX_SUFF(PIOMMU) PIOMMUCC;
631
632/**
633 * IOMMU register access.
634 */
635typedef struct IOMMUREGACC
636{
637 const char *pszName;
638 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
639 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
640} IOMMUREGACC;
641/** Pointer to an IOMMU register access. */
642typedef IOMMUREGACC *PIOMMUREGACC;
643/** Pointer to a const IOMMU register access. */
644typedef IOMMUREGACC const *PCIOMMUREGACC;
645
646#ifdef IOMMU_WITH_IOTLBE_CACHE
647/**
648 * IOTLBE flush argument.
649 */
650typedef struct IOTLBEFLUSHARG
651{
652 /** The ring-3 IOMMU device state. */
653 PIOMMUR3 pIommuR3;
654 /** The domain ID to flush. */
655 uint16_t idDomain;
656} IOTLBEFLUSHARG;
657/** Pointer to an IOTLBE flush argument. */
658typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
659/** Pointer to a const IOTLBE flush argument. */
660typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
661
662/**
663 * IOTLBE Info. argument.
664 */
665typedef struct IOTLBEINFOARG
666{
667 /** The ring-3 IOMMU device state. */
668 PIOMMUR3 pIommuR3;
669 /** The info helper. */
670 PCDBGFINFOHLP pHlp;
671 /** The domain ID to dump IOTLB entry. */
672 uint16_t idDomain;
673} IOTLBEINFOARG;
674/** Pointer to an IOTLBE flush argument. */
675typedef IOTLBEINFOARG *PIOTLBEINFOARG;
676/** Pointer to a const IOTLBE flush argument. */
677typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
678#endif
679
680/**
681 * IOMMU operation auxiliary info.
682 */
683typedef struct IOMMUOPAUX
684{
685 /** The IOMMU operation being performed. */
686 IOMMUOP enmOp;
687 /** The device table entry (can be NULL). */
688 PCDTE_T pDte;
689 /** The device ID (bus, device, function). */
690 uint16_t idDevice;
691 /** The domain ID (when the DTE isn't provided). */
692 uint16_t idDomain;
693} IOMMUOPAUX;
694/** Pointer to an I/O address lookup struct. */
695typedef IOMMUOPAUX *PIOMMUOPAUX;
696/** Pointer to a const I/O address lookup struct. */
697typedef IOMMUOPAUX const *PCIOMMUOPAUX;
698
699typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
700 PIOPAGELOOKUP pPageLookup));
701typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
702
703
704/*********************************************************************************************************************************
705* Global Variables *
706*********************************************************************************************************************************/
707#ifdef IN_RING3
708/**
709 * An array of the number of device table segments supported.
710 * Indexed by u2DevTabSegSup.
711 */
712static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
713#endif
714
715#if defined(IN_RING3) || defined(LOG_ENABLED)
716/**
717 * The IOMMU I/O permission names.
718 */
719static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
720#endif
721
722/**
723 * An array of the masks to select the device table segment index from a device ID.
724 */
725static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
726
727/**
728 * An array of the shift values to select the device table segment index from a
729 * device ID.
730 */
731static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
732
733/**
734 * The maximum size (inclusive) of each device table segment (0 to 7).
735 * Indexed by the device table segment index.
736 */
737static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
738
739
740#ifndef VBOX_DEVICE_STRUCT_TESTCASE
741/**
742 * Gets the maximum number of buffer entries for the given buffer length.
743 *
744 * @returns Number of buffer entries.
745 * @param uEncodedLen The length (power-of-2 encoded).
746 */
747DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
748{
749 Assert(uEncodedLen > 7);
750 Assert(uEncodedLen < 16);
751 return 2 << (uEncodedLen - 1);
752}
753
754
755/**
756 * Gets the total length of the buffer given a base register's encoded length.
757 *
758 * @returns The length of the buffer in bytes.
759 * @param uEncodedLen The length (power-of-2 encoded).
760 */
761DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
762{
763 Assert(uEncodedLen > 7);
764 Assert(uEncodedLen < 16);
765 return (2 << (uEncodedLen - 1)) << 4;
766}
767
768
769/**
770 * Gets the number of (unconsumed) entries in the event log.
771 *
772 * @returns The number of entries in the event log.
773 * @param pThis The shared IOMMU device state.
774 */
775static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
776{
777 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
778 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
779 if (idxTail >= idxHead)
780 return idxTail - idxHead;
781
782 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
783 return cMaxEvts - idxHead + idxTail;
784}
785
786
787#if defined(IN_RING3) || defined(LOG_ENABLED)
788/**
789 * Gets the descriptive I/O permission name for a memory access.
790 *
791 * @returns The I/O permission name.
792 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
793 */
794static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
795{
796 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
797 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
798 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
799}
800#endif
801
802
803/**
804 * Checks whether two consecutive I/O page lookup results translates to a physically
805 * contiguous region.
806 *
807 * @returns @c true if they are contiguous, @c false otherwise.
808 * @param pPageLookupPrev The I/O page lookup result of the previous page.
809 * @param pPageLookup The I/O page lookup result of the current page.
810 */
811static bool iommuAmdLookupIsAccessContig(PCIOPAGELOOKUP pPageLookupPrev, PCIOPAGELOOKUP pPageLookup)
812{
813 Assert(pPageLookupPrev->fPerm == pPageLookup->fPerm);
814 size_t const cbPrev = RT_BIT_64(pPageLookupPrev->cShift);
815 RTGCPHYS const GCPhysPrev = pPageLookupPrev->GCPhysSpa;
816 RTGCPHYS const GCPhys = pPageLookup->GCPhysSpa;
817 uint64_t const offMaskPrev = IOMMU_GET_PAGE_OFF_MASK(pPageLookupPrev->cShift);
818 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(pPageLookup->cShift);
819
820 /* Paranoia: Ensure offset bits are 0. */
821 Assert(!(GCPhysPrev & offMaskPrev));
822 Assert(!(GCPhys & offMask));
823
824 if ((GCPhysPrev & ~offMaskPrev) + cbPrev == (GCPhys & ~offMask))
825 return true;
826 return false;
827}
828
829
830/**
831 * Gets the basic I/O device flags for the given device table entry.
832 *
833 * @returns The basic I/O device flags.
834 * @param pDte The device table entry.
835 */
836static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
837{
838 /* Extract basic flags from bits 127:0 of the DTE. */
839 uint16_t fFlags = 0;
840 if (pDte->n.u1Valid)
841 {
842 fFlags |= IOMMU_DTE_CACHE_F_VALID;
843
844 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
845 if (pDte->n.u1SuppressAllPfEvents)
846 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
847 if (pDte->n.u1SuppressPfEvents)
848 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
849
850 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
851 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
852 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
853 }
854
855 /* Extract basic flags from bits 255:128 of the DTE. */
856 if (pDte->n.u1IntrMapValid)
857 {
858 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
859
860 /** @todo Skip the if check here (shift/mask the relevant bit over). */
861 if (pDte->n.u1IgnoreUnmappedIntrs)
862 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
863
864 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
865 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
866 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
867 }
868 return fFlags;
869}
870
871
872/**
873 * Remaps the source MSI to the destination MSI given the IRTE.
874 *
875 * @param pMsiIn The source MSI.
876 * @param pMsiOut Where to store the remapped MSI.
877 * @param pIrte The IRTE used for the remapping.
878 */
879static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
880{
881 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
882 *pMsiOut = *pMsiIn;
883
884 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
885 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
886
887 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
888 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
889}
890
891
892#ifdef IOMMU_WITH_DTE_CACHE
893/**
894 * Looks up an entry in the DTE cache for the given device ID.
895 *
896 * @returns The index of the entry, or the cache capacity if no entry was found.
897 * @param pThis The shared IOMMU device state.
898 * @param idDevice The device ID (bus, device, function).
899 */
900DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
901{
902 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
903 for (uint16_t i = 0; i < cDeviceIds; i++)
904 {
905 if (pThis->aDeviceIds[i] == idDevice)
906 return i;
907 }
908 return cDeviceIds;
909}
910
911
912/**
913 * Gets an free/unused DTE cache entry.
914 *
915 * @returns The index of an unused entry, or cache capacity if the cache is full.
916 * @param pThis The shared IOMMU device state.
917 */
918DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
919{
920 /*
921 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
922 * (the latter being an ugly hack) and cannot be a valid device ID.
923 */
924 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
925 for (uint16_t i = 0; i < cDeviceIds; i++)
926 {
927 if (!pThis->aDeviceIds[i])
928 return i;
929 }
930 return cDeviceIds;
931}
932
933
934/**
935 * Adds or updates the I/O device flags for the given device ID.
936 *
937 * @returns VBox status code.
938 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
939 *
940 * @param pDevIns The IOMMU instance data.
941 * @param idDevice The device ID (bus, device, function).
942 * @param pDte The device table entry.
943 * @param fOrMask The device flags (usually compound flags) to OR in with the
944 * basic flags, see IOMMU_DTE_CACHE_F_XXX.
945 */
946static int iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, uint16_t fOrMask)
947{
948 Assert(pDte);
949 Assert(idDevice);
950
951 int rc = VINF_SUCCESS;
952 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask;
953 uint16_t const idDomain = pDte->n.u16DomainId;
954
955 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
956 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
957
958 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
959 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
960 if (idxDte < cDteCache)
961 {
962 pThis->aDteCache[idxDte].fFlags = fFlags;
963 pThis->aDteCache[idxDte].idDomain = idDomain;
964 }
965 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
966 {
967 pThis->aDeviceIds[idxDte] = idDevice;
968 pThis->aDteCache[idxDte].fFlags = fFlags;
969 pThis->aDteCache[idxDte].idDomain = idDomain;
970 }
971 else
972 rc = VERR_OUT_OF_RESOURCES;
973
974 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
975 return rc;
976}
977
978
979/**
980 * Adds one or more I/O device flags if the device is already present in the cache.
981 *
982 * @param pDevIns The IOMMU instance data.
983 * @param idDevice The device ID (bus, device, function).
984 * @param fFlags Additional device flags to OR with existing flags, see
985 * IOMMU_DTE_CACHE_F_XXX.
986 */
987static void iommuAmdDteCacheAddFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fFlags)
988{
989 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
990 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
991
992 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
993 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
994 if ( idxDte < cDteCache
995 && (pThis->aDteCache[idxDte].fFlags & IOMMU_DTE_CACHE_F_PRESENT))
996 pThis->aDteCache[idxDte].fFlags |= fFlags;
997
998 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
999}
1000
1001
1002# ifdef IN_RING3
1003/**
1004 * Removes a DTE cache entry.
1005 *
1006 * @param pDevIns The IOMMU instance data.
1007 * @param idDevice The device ID to remove cache entries for.
1008 */
1009static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1010{
1011 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1012 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1013
1014 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1015 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1016 if (idxDte < cDteCache)
1017 {
1018 pThis->aDteCache[idxDte].fFlags = 0;
1019 pThis->aDteCache[idxDte].idDomain = 0;
1020 }
1021
1022 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1023}
1024
1025
1026/**
1027 * Removes all entries in the device table entry cache.
1028 *
1029 * @param pDevIns The IOMMU instance data.
1030 */
1031static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1032{
1033 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1034 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1035 RT_ZERO(pThis->aDeviceIds);
1036 RT_ZERO(pThis->aDteCache);
1037 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1038}
1039# endif /* IN_RING3 */
1040#endif /* IOMMU_WITH_DTE_CACHE */
1041
1042
1043#ifdef IOMMU_WITH_IOTLBE_CACHE
1044/**
1045 * Moves the IOTLB entry to the least recently used slot.
1046 *
1047 * @param pThisR3 The ring-3 IOMMU device state.
1048 * @param pIotlbe The IOTLB entry to move.
1049 */
1050DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1051{
1052 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1053 {
1054 RTListNodeRemove(&pIotlbe->NdLru);
1055 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1056 }
1057}
1058
1059
1060/**
1061 * Moves the IOTLB entry to the most recently used slot.
1062 *
1063 * @param pThisR3 The ring-3 IOMMU device state.
1064 * @param pIotlbe The IOTLB entry to move.
1065 */
1066DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1067{
1068 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1069 {
1070 RTListNodeRemove(&pIotlbe->NdLru);
1071 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1072 }
1073}
1074
1075
1076# ifdef IN_RING3
1077/**
1078 * Dumps the IOTLB entry via the debug info helper.
1079 *
1080 * @returns VINF_SUCCESS.
1081 * @param pNode Pointer to an IOTLB entry to dump info.
1082 * @param pvUser Pointer to an IOTLBEINFOARG.
1083 */
1084static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1085{
1086 /* Validate. */
1087 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1088 AssertPtr(pArgs);
1089 AssertPtr(pArgs->pIommuR3);
1090 AssertPtr(pArgs->pHlp);
1091 //Assert(pArgs->pIommuCC->u32Magic == IOMMU_MAGIC);
1092
1093 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1094 if (idDomain == pArgs->idDomain)
1095 {
1096 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1097 AVLU64KEY const uKey = pIotlbe->Core.Key;
1098 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1099 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1100 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1101 size_t const cbPage = RT_BIT_64(cShift);
1102 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1103 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1104 bool const fEvictPending = pIotlbe->fEvictPending;
1105
1106 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1107 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1108 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1109 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1110 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1111 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1112 }
1113
1114 return VINF_SUCCESS;
1115}
1116# endif /* IN_RING3 */
1117
1118
1119/**
1120 * Removes the IOTLB entry if it's associated with the specified domain ID.
1121 *
1122 * @returns VINF_SUCCESS.
1123 * @param pNode Pointer to an IOTLBE.
1124 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1125 */
1126static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1127{
1128 /* Validate. */
1129 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1130 AssertPtr(pArgs);
1131 AssertPtr(pArgs->pIommuR3);
1132 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1133
1134 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1135 if (idDomain == pArgs->idDomain)
1136 {
1137 /* Mark this entry is as invalidated and needs to be evicted later. */
1138 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1139 pIotlbe->fEvictPending = true;
1140 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1141 }
1142 return VINF_SUCCESS;
1143}
1144
1145
1146/**
1147 * Inserts an IOTLB entry into the cache.
1148 *
1149 * @param pThis The shared IOMMU device state.
1150 * @param pThisR3 The ring-3 IOMMU device state.
1151 * @param pIotlbe The IOTLB entry to initialize and insert.
1152 * @param idDomain The domain ID.
1153 * @param uIova The I/O virtual address.
1154 * @param pPageLookup The I/O page lookup result of the access.
1155 */
1156static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1157 PCIOPAGELOOKUP pPageLookup)
1158{
1159 /* Initialize the IOTLB entry with results of the I/O page walk. */
1160 pIotlbe->Core.Key = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1161 pIotlbe->PageLookup = *pPageLookup;
1162
1163 /* Validate. */
1164 Assert(pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL);
1165 Assert(!pIotlbe->fEvictPending);
1166
1167 /* Check if the entry already exists. */
1168 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, pIotlbe->Core.Key);
1169 if (!pFound)
1170 {
1171 /* Insert the entry into the cache. */
1172 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1173 Assert(fInserted); NOREF(fInserted);
1174 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1175 ++pThisR3->cCachedIotlbes;
1176 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1177 }
1178 else
1179 {
1180 /* Update the existing entry. */
1181 if (pFound->fEvictPending)
1182 {
1183 pFound->fEvictPending = false;
1184 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1185 }
1186 Assert(pFound->PageLookup.cShift == pPageLookup->cShift);
1187 pFound->PageLookup.fPerm = pPageLookup->fPerm;
1188 pFound->PageLookup.GCPhysSpa = pPageLookup->GCPhysSpa;
1189 }
1190}
1191
1192
1193/**
1194 * Removes an IOTLB entry from the cache for the given key.
1195 *
1196 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1197 * the tree.
1198 * @param pThis The shared IOMMU device state.
1199 * @param pThisR3 The ring-3 IOMMU device state.
1200 * @param uKey The key of the IOTLB entry to remove.
1201 */
1202static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1203{
1204 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1205 if (pIotlbe)
1206 {
1207 if (pIotlbe->fEvictPending)
1208 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1209
1210 RT_ZERO(pIotlbe->Core);
1211 RT_ZERO(pIotlbe->PageLookup);
1212 /* We must not erase the LRU node connections here! */
1213 pIotlbe->fEvictPending = false;
1214 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1215
1216 Assert(pThisR3->cCachedIotlbes > 0);
1217 --pThisR3->cCachedIotlbes;
1218 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1219 }
1220 return pIotlbe;
1221}
1222
1223
1224/**
1225 * Looks up an IOTLB from the cache.
1226 *
1227 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1228 * @param pThis The shared IOMMU device state.
1229 * @param pThisR3 The ring-3 IOMMU device state.
1230 * @param idDomain The domain ID.
1231 * @param uIova The I/O virtual address.
1232 */
1233static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1234{
1235 RT_NOREF(pThis);
1236
1237 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1238 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1239 if ( pIotlbe
1240 && !pIotlbe->fEvictPending)
1241 return pIotlbe;
1242
1243 /*
1244 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1245 * them from the cache immediately. We found an entry pending eviction, just return that
1246 * nothing was found (rather than evicting now).
1247 */
1248 return NULL;
1249}
1250
1251
1252/**
1253 * Adds an IOTLB entry to the cache.
1254 *
1255 * @param pThis The shared IOMMU device state.
1256 * @param pThisR3 The ring-3 IOMMU device state.
1257 * @param idDomain The domain ID.
1258 * @param uIova The I/O virtual address.
1259 * @param pPageLookup The I/O page lookup result of the access.
1260 */
1261static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIova, PCIOPAGELOOKUP pPageLookup)
1262{
1263 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1264 Assert(pPageLookup);
1265 Assert(pPageLookup->cShift <= 31);
1266 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1267
1268 /*
1269 * If there are no unused IOTLB entries, evict the LRU entry.
1270 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1271 */
1272 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1273 {
1274 /* Grab the least recently used entry. */
1275 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1276 Assert(pIotlbe);
1277
1278 /* If the entry is in the cache, remove it. */
1279 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1280 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1281
1282 /* Initialize and insert the IOTLB entry into the cache. */
1283 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1284
1285 /* Move the entry to the most recently used slot. */
1286 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1287 }
1288 else
1289 {
1290 /* Grab an unused IOTLB entry from the pre-allocated list. */
1291 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1292 ++pThisR3->idxUnusedIotlbe;
1293
1294 /* Initialize and insert the IOTLB entry into the cache. */
1295 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1296
1297 /* Add the entry to the most recently used slot. */
1298 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1299 }
1300}
1301
1302
1303/**
1304 * Removes all IOTLB entries from the cache.
1305 *
1306 * @param pDevIns The IOMMU instance data.
1307 */
1308static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1309{
1310 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1311 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1312 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1313
1314 if (pThisR3->cCachedIotlbes > 0)
1315 {
1316 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
1317 RT_BZERO(pThisR3->paIotlbes, cbIotlbes);
1318 pThisR3->idxUnusedIotlbe = 0;
1319 pThisR3->cCachedIotlbes = 0;
1320 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1321 RTListInit(&pThisR3->LstLruIotlbe);
1322 }
1323
1324 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1325}
1326
1327
1328/**
1329 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1330 * domain ID from the cache.
1331 *
1332 * @param pDevIns The IOMMU instance data.
1333 * @param idDomain The domain ID.
1334 * @param uIova The I/O virtual address to invalidate.
1335 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1336 */
1337static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1338{
1339 /* Validate. */
1340 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1341 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1342 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1343
1344 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1345 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1346 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1347
1348 do
1349 {
1350 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1351 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1352 if (pIotlbe)
1353 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1354 uIova += X86_PAGE_4K_SIZE;
1355 cbInvalidate -= X86_PAGE_4K_SIZE;
1356 } while (cbInvalidate > 0);
1357
1358 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1359}
1360
1361
1362/**
1363 * Removes all IOTLB entries for the specified domain ID.
1364 *
1365 * @param pDevIns The IOMMU instance data.
1366 * @param idDomain The domain ID.
1367 */
1368static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1369{
1370 /*
1371 * We need to iterate the tree and search based on the domain ID.
1372 * But it seems we cannot remove items while iterating the tree.
1373 * Thus, we simply mark entries for eviction later but move them to the LRU
1374 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1375 */
1376 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1377 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1378 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1379
1380 IOTLBEFLUSHARG Args;
1381 Args.pIommuR3 = pThisR3;
1382 Args.idDomain = idDomain;
1383 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1384
1385 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1386}
1387
1388
1389/**
1390 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1391 *
1392 * @param pDevIns The IOMMU instance data.
1393 * @param idDomain The domain ID.
1394 * @param uIova The I/O virtual address.
1395 * @param cbIova The size of the access (must be 4K aligned).
1396 * @param GCPhysSpa The translated system-physical address.
1397 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
1398 */
1399static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbIova, RTGCPHYS GCPhysSpa,
1400 uint8_t fPerm)
1401{
1402 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1403 Assert(!(GCPhysSpa & X86_PAGE_4K_OFFSET_MASK));
1404 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1405 Assert(cbIova >= X86_PAGE_4K_SIZE);
1406
1407 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1408 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1409
1410 /* Add IOTLB entries for every page in the access. */
1411 IOPAGELOOKUP PageLookup;
1412 RT_ZERO(PageLookup);
1413 PageLookup.cShift = X86_PAGE_4K_SHIFT;
1414 PageLookup.fPerm = fPerm;
1415 PageLookup.GCPhysSpa = GCPhysSpa;
1416
1417 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1418 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1419
1420 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1421 /** @todo Re-check DTE cache? */
1422 do
1423 {
1424 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIova, &PageLookup);
1425 uIova += X86_PAGE_4K_SIZE;
1426 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1427 --cPages;
1428 } while (cPages > 0);
1429 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1430}
1431#endif /* IOMMU_WITH_IOTLBE_CACHE */
1432
1433
1434#ifdef IOMMU_WITH_IRTE_CACHE
1435/**
1436 * Looks up an IRTE cache entry.
1437 *
1438 * @returns Index of the found entry, or cache capacity if not found.
1439 * @param pThis The shared IOMMU device state.
1440 * @param idDevice The device ID (bus, device, function).
1441 * @param offIrte The offset into the interrupt remap table.
1442 */
1443static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1444{
1445 /** @todo Consider sorting and binary search when the cache capacity grows.
1446 * For the IRTE cache this should be okay since typically guests do not alter the
1447 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1448 * often. */
1449 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1450 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1451 for (uint16_t i = 0; i < cIrteCache; i++)
1452 if (pThis->aIrteCache[i].uKey == uKey)
1453 return i;
1454 return cIrteCache;
1455}
1456
1457
1458/**
1459 * Gets a free/unused IRTE cache entry.
1460 *
1461 * @returns The index of an unused entry, or cache capacity if the cache is full.
1462 * @param pThis The shared IOMMU device state.
1463 */
1464static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1465{
1466 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1467 for (uint16_t i = 0; i < cIrteCache; i++)
1468 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1469 {
1470 Assert(!pThis->aIrteCache[i].Irte.u32);
1471 return i;
1472 }
1473 return cIrteCache;
1474}
1475
1476
1477/**
1478 * Looks up the IRTE cache for the given MSI.
1479 *
1480 * @returns VBox status code.
1481 * @param pDevIns The IOMMU instance data.
1482 * @param idDevice The device ID (bus, device, function).
1483 * @param enmOp The IOMMU operation being performed.
1484 * @param pMsiIn The source MSI.
1485 * @param pMsiOut Where to store the remapped MSI.
1486 */
1487static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1488{
1489 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1490
1491 int rc = VERR_NOT_FOUND;
1492 /* Deal with such cases in the slower/fallback path. */
1493 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1494 { /* likely */ }
1495 else
1496 return rc;
1497
1498 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1499 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1500
1501 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1502 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1503 {
1504 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1505 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1506 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1507 {
1508 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1509
1510 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1511 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1512 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1513 {
1514 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1515 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1516 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1517 {
1518 /* Interrupt table length has been verified prior to adding entries to the cache. */
1519 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1520 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1521 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1522 {
1523 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1524 Assert(pIrte->n.u1RemapEnable);
1525 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1526 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1527 rc = VINF_SUCCESS;
1528 }
1529 }
1530 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1531 {
1532 *pMsiOut = *pMsiIn;
1533 rc = VINF_SUCCESS;
1534 }
1535 }
1536 }
1537 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1538 {
1539 *pMsiOut = *pMsiIn;
1540 rc = VINF_SUCCESS;
1541 }
1542 }
1543
1544 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1545 return rc;
1546}
1547
1548
1549/**
1550 * Adds or updates the IRTE cache for the given IRTE.
1551 *
1552 * @returns VBox status code.
1553 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1554 *
1555 * @param pDevIns The IOMMU instance data.
1556 * @param idDevice The device ID (bus, device, function).
1557 * @param offIrte The offset into the interrupt remap table.
1558 * @param pIrte The IRTE to cache.
1559 */
1560static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1561{
1562 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1563
1564 int rc = VINF_SUCCESS;
1565 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1566 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1567
1568 /* Find an existing entry or get an unused slot. */
1569 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1570 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1571 if ( idxIrteCache < cIrteCache
1572 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1573 {
1574 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1575 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1576 }
1577 else
1578 rc = VERR_OUT_OF_RESOURCES;
1579
1580 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1581 return rc;
1582}
1583
1584
1585# ifdef IN_RING3
1586/**
1587 * Removes IRTE cache entries for the given device ID.
1588 *
1589 * @param pDevIns The IOMMU instance data.
1590 * @param idDevice The device ID (bus, device, function).
1591 */
1592static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1593{
1594 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1595 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1596 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1597 for (uint16_t i = 0; i < cIrteCache; i++)
1598 {
1599 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1600 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1601 {
1602 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1603 pIrteCache->Irte.u32 = 0;
1604 /* There could multiple IRTE entries for a device ID, continue searching. */
1605 }
1606 }
1607 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1608}
1609
1610
1611/**
1612 * Removes all IRTE cache entries.
1613 *
1614 * @param pDevIns The IOMMU instance data.
1615 */
1616static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1617{
1618 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1619 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
1620 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1621 for (uint16_t i = 0; i < cIrteCache; i++)
1622 {
1623 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1624 pThis->aIrteCache[i].Irte.u32 = 0;
1625 }
1626 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
1627}
1628# endif /* IN_RING3 */
1629#endif /* IOMMU_WITH_IRTE_CACHE */
1630
1631
1632/**
1633 * Atomically reads the control register without locking the IOMMU device.
1634 *
1635 * @returns The control register.
1636 * @param pThis The shared IOMMU device state.
1637 */
1638DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1639{
1640 IOMMU_CTRL_T Ctrl;
1641 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1642 return Ctrl;
1643}
1644
1645
1646/**
1647 * Returns whether MSI is enabled for the IOMMU.
1648 *
1649 * @returns Whether MSI is enabled.
1650 * @param pDevIns The IOMMU device instance.
1651 *
1652 * @note There should be a PCIDevXxx function for this.
1653 */
1654static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1655{
1656 MSI_CAP_HDR_T MsiCapHdr;
1657 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1658 return MsiCapHdr.n.u1MsiEnable;
1659}
1660
1661
1662/**
1663 * Signals a PCI target abort.
1664 *
1665 * @param pDevIns The IOMMU device instance.
1666 */
1667static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1668{
1669 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1670 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1671 PDMPciDevSetStatus(pPciDev, u16Status);
1672}
1673
1674
1675/**
1676 * Wakes up the command thread if there are commands to be processed.
1677 *
1678 * @param pDevIns The IOMMU device instance.
1679 *
1680 * @remarks The IOMMU lock must be held while calling this!
1681 */
1682static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1683{
1684 Log4Func(("\n"));
1685
1686 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1687 if ( pThis->Status.n.u1CmdBufRunning
1688 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1689 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1690 {
1691 Log4Func(("Signaling command thread\n"));
1692 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1693 }
1694}
1695
1696
1697/**
1698 * Reads the Device Table Base Address Register.
1699 */
1700static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1701{
1702 RT_NOREF(pDevIns, offReg);
1703 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1704 return VINF_SUCCESS;
1705}
1706
1707
1708/**
1709 * Reads the Command Buffer Base Address Register.
1710 */
1711static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1712{
1713 RT_NOREF(pDevIns, offReg);
1714 *pu64Value = pThis->CmdBufBaseAddr.u64;
1715 return VINF_SUCCESS;
1716}
1717
1718
1719/**
1720 * Reads the Event Log Base Address Register.
1721 */
1722static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1723{
1724 RT_NOREF(pDevIns, offReg);
1725 *pu64Value = pThis->EvtLogBaseAddr.u64;
1726 return VINF_SUCCESS;
1727}
1728
1729
1730/**
1731 * Reads the Control Register.
1732 */
1733static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1734{
1735 RT_NOREF(pDevIns, offReg);
1736 *pu64Value = pThis->Ctrl.u64;
1737 return VINF_SUCCESS;
1738}
1739
1740
1741/**
1742 * Reads the Exclusion Range Base Address Register.
1743 */
1744static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1745{
1746 RT_NOREF(pDevIns, offReg);
1747 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1748 return VINF_SUCCESS;
1749}
1750
1751
1752/**
1753 * Reads to the Exclusion Range Limit Register.
1754 */
1755static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1756{
1757 RT_NOREF(pDevIns, offReg);
1758 *pu64Value = pThis->ExclRangeLimit.u64;
1759 return VINF_SUCCESS;
1760}
1761
1762
1763/**
1764 * Reads to the Extended Feature Register.
1765 */
1766static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1767{
1768 RT_NOREF(pDevIns, offReg);
1769 *pu64Value = pThis->ExtFeat.u64;
1770 return VINF_SUCCESS;
1771}
1772
1773
1774/**
1775 * Reads to the PPR Log Base Address Register.
1776 */
1777static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1778{
1779 RT_NOREF(pDevIns, offReg);
1780 *pu64Value = pThis->PprLogBaseAddr.u64;
1781 return VINF_SUCCESS;
1782}
1783
1784
1785/**
1786 * Writes the Hardware Event Register (Hi).
1787 */
1788static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1789{
1790 RT_NOREF(pDevIns, offReg);
1791 *pu64Value = pThis->HwEvtHi.u64;
1792 return VINF_SUCCESS;
1793}
1794
1795
1796/**
1797 * Reads the Hardware Event Register (Lo).
1798 */
1799static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1800{
1801 RT_NOREF(pDevIns, offReg);
1802 *pu64Value = pThis->HwEvtLo;
1803 return VINF_SUCCESS;
1804}
1805
1806
1807/**
1808 * Reads the Hardware Event Status Register.
1809 */
1810static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1811{
1812 RT_NOREF(pDevIns, offReg);
1813 *pu64Value = pThis->HwEvtStatus.u64;
1814 return VINF_SUCCESS;
1815}
1816
1817
1818/**
1819 * Reads to the GA Log Base Address Register.
1820 */
1821static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1822{
1823 RT_NOREF(pDevIns, offReg);
1824 *pu64Value = pThis->GALogBaseAddr.u64;
1825 return VINF_SUCCESS;
1826}
1827
1828
1829/**
1830 * Reads to the PPR Log B Base Address Register.
1831 */
1832static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1833{
1834 RT_NOREF(pDevIns, offReg);
1835 *pu64Value = pThis->PprLogBBaseAddr.u64;
1836 return VINF_SUCCESS;
1837}
1838
1839
1840/**
1841 * Reads to the Event Log B Base Address Register.
1842 */
1843static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1844{
1845 RT_NOREF(pDevIns, offReg);
1846 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1847 return VINF_SUCCESS;
1848}
1849
1850
1851/**
1852 * Reads the Device Table Segment Base Address Register.
1853 */
1854static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1855{
1856 RT_NOREF(pDevIns);
1857
1858 /* Figure out which segment is being written. */
1859 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1860 uint8_t const idxSegment = offSegment + 1;
1861 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1862
1863 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1864 return VINF_SUCCESS;
1865}
1866
1867
1868/**
1869 * Reads the Device Specific Feature Extension (DSFX) Register.
1870 */
1871static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1872{
1873 RT_NOREF(pDevIns, offReg);
1874 *pu64Value = pThis->DevSpecificFeat.u64;
1875 return VINF_SUCCESS;
1876}
1877
1878/**
1879 * Reads the Device Specific Control Extension (DSCX) Register.
1880 */
1881static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1882{
1883 RT_NOREF(pDevIns, offReg);
1884 *pu64Value = pThis->DevSpecificCtrl.u64;
1885 return VINF_SUCCESS;
1886}
1887
1888
1889/**
1890 * Reads the Device Specific Status Extension (DSSX) Register.
1891 */
1892static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1893{
1894 RT_NOREF(pDevIns, offReg);
1895 *pu64Value = pThis->DevSpecificStatus.u64;
1896 return VINF_SUCCESS;
1897}
1898
1899
1900/**
1901 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1902 */
1903static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1904{
1905 RT_NOREF(pDevIns, offReg);
1906 uint32_t const uLo = pThis->MiscInfo.au32[0];
1907 uint32_t const uHi = pThis->MiscInfo.au32[1];
1908 *pu64Value = RT_MAKE_U64(uLo, uHi);
1909 return VINF_SUCCESS;
1910}
1911
1912
1913/**
1914 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1915 * Register (32-bit).
1916 */
1917static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1918{
1919 RT_NOREF(pThis, offReg);
1920 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1921 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1922 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1923 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1924 *pu64Value = RT_MAKE_U64(uLo, uHi);
1925 return VINF_SUCCESS;
1926}
1927
1928
1929/**
1930 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1931 */
1932static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1933{
1934 RT_NOREF(pThis, offReg);
1935 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1936 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1937 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1938 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1939 *pu64Value = RT_MAKE_U64(uLo, uHi);
1940 return VINF_SUCCESS;
1941}
1942
1943
1944/**
1945 * Reads the Command Buffer Head Pointer Register.
1946 */
1947static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1948{
1949 RT_NOREF(pDevIns, offReg);
1950 *pu64Value = pThis->CmdBufHeadPtr.u64;
1951 return VINF_SUCCESS;
1952}
1953
1954
1955/**
1956 * Reads the Command Buffer Tail Pointer Register.
1957 */
1958static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1959{
1960 RT_NOREF(pDevIns, offReg);
1961 *pu64Value = pThis->CmdBufTailPtr.u64;
1962 return VINF_SUCCESS;
1963}
1964
1965
1966/**
1967 * Reads the Event Log Head Pointer Register.
1968 */
1969static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1970{
1971 RT_NOREF(pDevIns, offReg);
1972 *pu64Value = pThis->EvtLogHeadPtr.u64;
1973 return VINF_SUCCESS;
1974}
1975
1976
1977/**
1978 * Reads the Event Log Tail Pointer Register.
1979 */
1980static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1981{
1982 RT_NOREF(pDevIns, offReg);
1983 *pu64Value = pThis->EvtLogTailPtr.u64;
1984 return VINF_SUCCESS;
1985}
1986
1987
1988/**
1989 * Reads the Status Register.
1990 */
1991static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1992{
1993 RT_NOREF(pDevIns, offReg);
1994 *pu64Value = pThis->Status.u64;
1995 return VINF_SUCCESS;
1996}
1997
1998
1999/**
2000 * Writes the Device Table Base Address Register.
2001 */
2002static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2003{
2004 RT_NOREF(pDevIns, offReg);
2005
2006 /* Mask out all unrecognized bits. */
2007 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2008
2009 /* Update the register. */
2010 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2011
2012 /* Paranoia. */
2013 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
2014 return VINF_SUCCESS;
2015}
2016
2017
2018/**
2019 * Writes the Command Buffer Base Address Register.
2020 */
2021static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2022{
2023 RT_NOREF(pDevIns, offReg);
2024
2025 /*
2026 * While this is not explicitly specified like the event log base address register,
2027 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2028 * Inconsistent specs :/
2029 */
2030 if (pThis->Status.n.u1CmdBufRunning)
2031 {
2032 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2033 return VINF_SUCCESS;
2034 }
2035
2036 /* Mask out all unrecognized bits. */
2037 CMD_BUF_BAR_T CmdBufBaseAddr;
2038 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2039
2040 /* Validate the length. */
2041 if (CmdBufBaseAddr.n.u4Len >= 8)
2042 {
2043 /* Update the register. */
2044 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2045
2046 /*
2047 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2048 * See AMD IOMMU spec. 2.4 "Commands".
2049 */
2050 pThis->CmdBufHeadPtr.u64 = 0;
2051 pThis->CmdBufTailPtr.u64 = 0;
2052 }
2053 else
2054 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2055
2056 return VINF_SUCCESS;
2057}
2058
2059
2060/**
2061 * Writes the Event Log Base Address Register.
2062 */
2063static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2064{
2065 RT_NOREF(pDevIns, offReg);
2066
2067 /*
2068 * IOMMU behavior is undefined when software writes this register when event logging is running.
2069 * In our emulation, we ignore the write entirely.
2070 * See AMD IOMMU spec. "Event Log Base Address Register".
2071 */
2072 if (pThis->Status.n.u1EvtLogRunning)
2073 {
2074 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2075 return VINF_SUCCESS;
2076 }
2077
2078 /* Mask out all unrecognized bits. */
2079 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2080 EVT_LOG_BAR_T EvtLogBaseAddr;
2081 EvtLogBaseAddr.u64 = u64Value;
2082
2083 /* Validate the length. */
2084 if (EvtLogBaseAddr.n.u4Len >= 8)
2085 {
2086 /* Update the register. */
2087 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2088
2089 /*
2090 * Writing the event log base address, clears the event log head and tail pointers.
2091 * See AMD IOMMU spec. 2.5 "Event Logging".
2092 */
2093 pThis->EvtLogHeadPtr.u64 = 0;
2094 pThis->EvtLogTailPtr.u64 = 0;
2095 }
2096 else
2097 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2098
2099 return VINF_SUCCESS;
2100}
2101
2102
2103/**
2104 * Writes the Control Register.
2105 */
2106static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2107{
2108 RT_NOREF(pDevIns, offReg);
2109
2110 /* Mask out all unrecognized bits. */
2111 u64Value &= IOMMU_CTRL_VALID_MASK;
2112 IOMMU_CTRL_T NewCtrl;
2113 NewCtrl.u64 = u64Value;
2114
2115 /* Ensure the device table segments are within limits. */
2116 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2117 {
2118 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2119
2120 /* Update the register. */
2121 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2122
2123 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2124 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2125
2126 /* Enable or disable event logging when the bit transitions. */
2127 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2128 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2129 if ( fOldEvtLogEn != fNewEvtLogEn
2130 || fOldIommuEn != fNewIommuEn)
2131 {
2132 if ( fNewIommuEn
2133 && fNewEvtLogEn)
2134 {
2135 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2136 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2137 }
2138 else
2139 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2140 }
2141
2142 /* Enable or disable command buffer processing when the bit transitions. */
2143 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2144 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2145 if ( fOldCmdBufEn != fNewCmdBufEn
2146 || fOldIommuEn != fNewIommuEn)
2147 {
2148 if ( fNewCmdBufEn
2149 && fNewIommuEn)
2150 {
2151 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2152 LogFunc(("Command buffer enabled\n"));
2153
2154 /* Wake up the command thread to start processing commands if any. */
2155 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2156 }
2157 else
2158 {
2159 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2160 LogFunc(("Command buffer disabled\n"));
2161 }
2162 }
2163 }
2164 else
2165 {
2166 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2167 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2168 }
2169
2170 return VINF_SUCCESS;
2171}
2172
2173
2174/**
2175 * Writes to the Exclusion Range Base Address Register.
2176 */
2177static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2178{
2179 RT_NOREF(pDevIns, offReg);
2180 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2181 return VINF_SUCCESS;
2182}
2183
2184
2185/**
2186 * Writes to the Exclusion Range Limit Register.
2187 */
2188static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2189{
2190 RT_NOREF(pDevIns, offReg);
2191 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2192 u64Value |= UINT64_C(0xfff);
2193 pThis->ExclRangeLimit.u64 = u64Value;
2194 return VINF_SUCCESS;
2195}
2196
2197
2198/**
2199 * Writes the Hardware Event Register (Hi).
2200 */
2201static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2202{
2203 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2204 RT_NOREF(pDevIns, offReg);
2205 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2206 pThis->HwEvtHi.u64 = u64Value;
2207 return VINF_SUCCESS;
2208}
2209
2210
2211/**
2212 * Writes the Hardware Event Register (Lo).
2213 */
2214static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2215{
2216 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2217 RT_NOREF(pDevIns, offReg);
2218 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2219 pThis->HwEvtLo = u64Value;
2220 return VINF_SUCCESS;
2221}
2222
2223
2224/**
2225 * Writes the Hardware Event Status Register.
2226 */
2227static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2228{
2229 RT_NOREF(pDevIns, offReg);
2230
2231 /* Mask out all unrecognized bits. */
2232 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2233
2234 /*
2235 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2236 * If the current status bits or the bits being written are both 0, we've nothing to do.
2237 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2238 */
2239 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2240 if (!(HwStatus & RT_BIT(0)))
2241 return VINF_SUCCESS;
2242 if (u64Value & HwStatus & RT_BIT_64(0))
2243 HwStatus &= ~RT_BIT_64(0);
2244 if (u64Value & HwStatus & RT_BIT_64(1))
2245 HwStatus &= ~RT_BIT_64(1);
2246
2247 /* Update the register. */
2248 pThis->HwEvtStatus.u64 = HwStatus;
2249 return VINF_SUCCESS;
2250}
2251
2252
2253/**
2254 * Writes the Device Table Segment Base Address Register.
2255 */
2256static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2257{
2258 RT_NOREF(pDevIns);
2259
2260 /* Figure out which segment is being written. */
2261 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2262 uint8_t const idxSegment = offSegment + 1;
2263 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2264
2265 /* Mask out all unrecognized bits. */
2266 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2267 DEV_TAB_BAR_T DevTabSegBar;
2268 DevTabSegBar.u64 = u64Value;
2269
2270 /* Validate the size. */
2271 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2272 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2273 if (uSegSize <= uMaxSegSize)
2274 {
2275 /* Update the register. */
2276 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2277 }
2278 else
2279 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2280
2281 return VINF_SUCCESS;
2282}
2283
2284
2285/**
2286 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2287 */
2288static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2289{
2290 RT_NOREF(pDevIns, offReg);
2291
2292 /* MSI Vector Register 0 is read-only. */
2293 /* MSI Vector Register 1. */
2294 uint32_t const uReg = u64Value >> 32;
2295 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2296 return VINF_SUCCESS;
2297}
2298
2299
2300/**
2301 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2302 * Register (32-bit).
2303 */
2304static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2305{
2306 RT_NOREF(pThis, offReg);
2307 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2308 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2309
2310 /* MSI capability header. */
2311 {
2312 uint32_t const uReg = u64Value;
2313 MSI_CAP_HDR_T MsiCapHdr;
2314 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2315 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2316 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2317 }
2318
2319 /* MSI Address Lo. */
2320 {
2321 uint32_t const uReg = u64Value >> 32;
2322 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2323 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2324 }
2325
2326 return VINF_SUCCESS;
2327}
2328
2329
2330/**
2331 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2332 */
2333static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2334{
2335 RT_NOREF(pThis, offReg);
2336 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2337 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2338
2339 /* MSI Address Hi. */
2340 {
2341 uint32_t const uReg = u64Value;
2342 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2343 }
2344
2345 /* MSI Data. */
2346 {
2347 uint32_t const uReg = u64Value >> 32;
2348 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2349 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2350 }
2351
2352 return VINF_SUCCESS;
2353}
2354
2355
2356/**
2357 * Writes the Command Buffer Head Pointer Register.
2358 */
2359static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2360{
2361 RT_NOREF(pDevIns, offReg);
2362
2363 /*
2364 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2365 * In our emulation, we ignore the write entirely.
2366 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2367 */
2368 if (pThis->Status.n.u1CmdBufRunning)
2369 {
2370 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2371 return VINF_SUCCESS;
2372 }
2373
2374 /*
2375 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2376 * In our emulation, we ignore the write entirely.
2377 */
2378 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2379 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2380 Assert(cbBuf <= _512K);
2381 if (offBuf >= cbBuf)
2382 {
2383 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2384 return VINF_SUCCESS;
2385 }
2386
2387 /* Update the register. */
2388 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2389
2390 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2391
2392 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2393 return VINF_SUCCESS;
2394}
2395
2396
2397/**
2398 * Writes the Command Buffer Tail Pointer Register.
2399 */
2400static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2401{
2402 RT_NOREF(pDevIns, offReg);
2403
2404 /*
2405 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2406 * In our emulation, we ignore the write entirely.
2407 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2408 */
2409 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2410 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2411 Assert(cbBuf <= _512K);
2412 if (offBuf >= cbBuf)
2413 {
2414 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2415 return VINF_SUCCESS;
2416 }
2417
2418 /*
2419 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2420 * head pointer after adding one or more commands to the buffer.
2421 *
2422 * However, we cannot enforce this strictly because it's legal for software to shrink the
2423 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2424 * at 0). Software might even make the queue empty by making head and tail equal which is
2425 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2426 * in the foot here. As long as we make sure the offset value is within the circular buffer
2427 * bounds (which we do by masking bits above) it should be sufficient.
2428 */
2429 pThis->CmdBufTailPtr.au32[0] = offBuf;
2430
2431 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2432
2433 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2434 return VINF_SUCCESS;
2435}
2436
2437
2438/**
2439 * Writes the Event Log Head Pointer Register.
2440 */
2441static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2442{
2443 RT_NOREF(pDevIns, offReg);
2444
2445 /*
2446 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2447 * In our emulation, we ignore the write entirely.
2448 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2449 */
2450 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2451 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2452 Assert(cbBuf <= _512K);
2453 if (offBuf >= cbBuf)
2454 {
2455 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2456 return VINF_SUCCESS;
2457 }
2458
2459 /* Update the register. */
2460 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2461
2462 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2463 return VINF_SUCCESS;
2464}
2465
2466
2467/**
2468 * Writes the Event Log Tail Pointer Register.
2469 */
2470static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2471{
2472 RT_NOREF(pDevIns, offReg);
2473 NOREF(pThis);
2474
2475 /*
2476 * IOMMU behavior is undefined when software writes this register when the event log is running.
2477 * In our emulation, we ignore the write entirely.
2478 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2479 */
2480 if (pThis->Status.n.u1EvtLogRunning)
2481 {
2482 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2483 return VINF_SUCCESS;
2484 }
2485
2486 /*
2487 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2488 * In our emulation, we ignore the write entirely.
2489 */
2490 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2491 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2492 Assert(cbBuf <= _512K);
2493 if (offBuf >= cbBuf)
2494 {
2495 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2496 return VINF_SUCCESS;
2497 }
2498
2499 /* Update the register. */
2500 pThis->EvtLogTailPtr.au32[0] = offBuf;
2501
2502 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2503 return VINF_SUCCESS;
2504}
2505
2506
2507/**
2508 * Writes the Status Register.
2509 */
2510static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2511{
2512 RT_NOREF(pDevIns, offReg);
2513
2514 /* Mask out all unrecognized bits. */
2515 u64Value &= IOMMU_STATUS_VALID_MASK;
2516
2517 /*
2518 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2519 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2520 */
2521 IOMMU_STATUS_T const OldStatus = pThis->Status;
2522 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2523 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2524 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2525
2526 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2527
2528 /* Update the register. */
2529 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2530 return VINF_SUCCESS;
2531}
2532
2533
2534/**
2535 * Register access table 0.
2536 * The MMIO offset of each entry must be a multiple of 8!
2537 */
2538static const IOMMUREGACC g_aRegAccess0[] =
2539{
2540 /* MMIO off. Register name Read function Write function */
2541 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2542 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2543 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2544 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2545 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2546 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2547 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2548 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2549 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2550 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2551 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2552 { /* 0x58 */ NULL, NULL, NULL },
2553
2554 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2555 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2556 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2557 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2558 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2559 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2560 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2561 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2562 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2563 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2564 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2565 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2566 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2567 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2568 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2569 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2570
2571 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2572 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2573 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2574 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2575
2576 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2577 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2578 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2579 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2580 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2581 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2582 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2583
2584 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2585 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2586 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2587
2588 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2589 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2590 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2591 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2592
2593 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2594 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2595 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2596};
2597AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2598
2599/**
2600 * Register access table 1.
2601 * The MMIO offset of each entry must be a multiple of 8!
2602 */
2603static const IOMMUREGACC g_aRegAccess1[] =
2604{
2605 /* MMIO offset Register name Read function Write function */
2606 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2607 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2608 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2609 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2610 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2611 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2612 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2613 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2614 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2615 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2616 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2617 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2618};
2619AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2620
2621/**
2622 * Register access table 2.
2623 * The MMIO offset of each entry must be a multiple of 8!
2624 */
2625static const IOMMUREGACC g_aRegAccess2[] =
2626{
2627 /* MMIO offset Register name Read Function Write function */
2628 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2629
2630 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2631 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2632 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2633 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2634
2635 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2636 { /* 0x2028 */ NULL, NULL, NULL },
2637
2638 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2639 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2640
2641 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2642 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2643
2644 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2645 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2646
2647 { /* 0x2060 */ NULL, NULL, NULL },
2648 { /* 0x2068 */ NULL, NULL, NULL },
2649
2650 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2651 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2652
2653 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2654 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2655 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2656};
2657AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2658
2659
2660/**
2661 * Gets the register access structure given its MMIO offset.
2662 *
2663 * @returns The register access structure, or NULL if the offset is invalid.
2664 * @param off The MMIO offset of the register being accessed.
2665 */
2666static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2667{
2668 /* Figure out which table the register belongs to and validate its index. */
2669 PCIOMMUREGACC pReg;
2670 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2671 {
2672 uint32_t const idxReg = off >> 3;
2673 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2674 pReg = &g_aRegAccess0[idxReg];
2675 }
2676 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2677 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2678 {
2679 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2680 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2681 pReg = &g_aRegAccess1[idxReg];
2682 }
2683 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2684 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2685 {
2686 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2687 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2688 pReg = &g_aRegAccess2[idxReg];
2689 }
2690 else
2691 pReg = NULL;
2692 return pReg;
2693}
2694
2695
2696/**
2697 * Writes an IOMMU register (32-bit and 64-bit).
2698 *
2699 * @returns Strict VBox status code.
2700 * @param pDevIns The IOMMU device instance.
2701 * @param off MMIO byte offset to the register.
2702 * @param cb The size of the write access.
2703 * @param uValue The value being written.
2704 *
2705 * @thread EMT.
2706 */
2707static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2708{
2709 /*
2710 * Validate the access in case of IOM bug or incorrect assumption.
2711 */
2712 Assert(off < IOMMU_MMIO_REGION_SIZE);
2713 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2714 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2715
2716 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2717
2718 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2719 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2720 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2721 if (pReg)
2722 { /* likely */ }
2723 else
2724 {
2725 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2726 return VINF_SUCCESS;
2727 }
2728
2729 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2730 if (pReg->pfnWrite)
2731 { /* likely */ }
2732 else
2733 {
2734 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2735 return VINF_SUCCESS;
2736 }
2737
2738 /*
2739 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2740 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2741 * consecutive 32-bit registers.
2742 */
2743 if (cb == 8)
2744 {
2745 if (!(off & 7))
2746 {
2747 IOMMU_LOCK(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2748 VBOXSTRICTRC rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2749 IOMMU_UNLOCK(pDevIns, pThisCC);
2750 return rcStrict;
2751 }
2752
2753 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2754 return VINF_SUCCESS;
2755 }
2756
2757 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2758 Assert(cb == 4);
2759 if (!(off & 7))
2760 {
2761 VBOXSTRICTRC rcStrict;
2762 IOMMU_LOCK(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2763
2764 /*
2765 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2766 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2767 */
2768 uint64_t u64Read;
2769 if (pReg->pfnRead)
2770 rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2771 else
2772 {
2773 rcStrict = VINF_SUCCESS;
2774 u64Read = 0;
2775 }
2776
2777 if (RT_SUCCESS(rcStrict))
2778 {
2779 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2780 rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2781 }
2782 else
2783 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2784
2785 IOMMU_UNLOCK(pDevIns, pThisCC);
2786 return rcStrict;
2787 }
2788
2789 /*
2790 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2791 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2792 */
2793 VBOXSTRICTRC rcStrict;
2794 Assert(!(off & 3));
2795 Assert(off & 7);
2796 Assert(off >= 4);
2797 uint64_t u64Read;
2798 if (pReg->pfnRead)
2799 rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2800 else
2801 {
2802 rcStrict = VINF_SUCCESS;
2803 u64Read = 0;
2804 }
2805
2806 if (RT_SUCCESS(rcStrict))
2807 {
2808 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2809 rcStrict = pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2810 }
2811 else
2812 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2813
2814 IOMMU_UNLOCK(pDevIns, pThisCC);
2815 return rcStrict;
2816}
2817
2818
2819/**
2820 * Reads an IOMMU register (64-bit) given its MMIO offset.
2821 *
2822 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2823 * boundary include the lower half of the subsequent register.
2824 *
2825 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2826 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2827 * software will only perform 32-bit reads on those 32-bit registers that are
2828 * aligned on 8-byte boundaries.
2829 *
2830 * @returns Strict VBox status code.
2831 * @param pDevIns The IOMMU device instance.
2832 * @param off The MMIO offset of the register in bytes.
2833 * @param puResult Where to store the value being read.
2834 *
2835 * @thread EMT.
2836 */
2837static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2838{
2839 Assert(off < IOMMU_MMIO_REGION_SIZE);
2840 Assert(!(off & 7) || !(off & 3));
2841
2842 Log4Func(("off=%#x\n", off));
2843
2844 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2845 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2846 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2847 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2848
2849 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2850 if (pReg)
2851 { /* likely */ }
2852 else
2853 {
2854 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2855 return VINF_IOM_MMIO_UNUSED_FF;
2856 }
2857
2858 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2859 if (pReg->pfnRead)
2860 { /* likely */ }
2861 else
2862 {
2863 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2864 return VINF_IOM_MMIO_UNUSED_00;
2865 }
2866
2867 /*
2868 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2869 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2870 */
2871 if (!(off & 7))
2872 {
2873 IOMMU_LOCK(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2874 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, puResult);
2875 IOMMU_UNLOCK(pDevIns, pThisCC);
2876 return rcStrict;
2877 }
2878
2879 /*
2880 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2881 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2882 */
2883 Assert(!(off & 3));
2884 Assert(off & 7);
2885 Assert(off >= 4);
2886 IOMMU_LOCK(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2887 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2888 IOMMU_UNLOCK(pDevIns, pThisCC);
2889 if (RT_SUCCESS(rcStrict))
2890 *puResult >>= 32;
2891 else
2892 {
2893 *puResult = 0;
2894 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2895 }
2896
2897 return rcStrict;
2898}
2899
2900
2901/**
2902 * Raises the MSI interrupt for the IOMMU device.
2903 *
2904 * @param pDevIns The IOMMU device instance.
2905 *
2906 * @thread Any.
2907 * @remarks The IOMMU lock may or may not be held.
2908 */
2909static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2910{
2911 LogFlowFunc(("\n"));
2912 if (iommuAmdIsMsiEnabled(pDevIns))
2913 {
2914 LogFunc(("Raising MSI\n"));
2915 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2916 }
2917}
2918
2919#if 0
2920/**
2921 * Clears the MSI interrupt for the IOMMU device.
2922 *
2923 * @param pDevIns The IOMMU device instance.
2924 *
2925 * @thread Any.
2926 * @remarks The IOMMU lock may or may not be held.
2927 */
2928static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2929{
2930 if (iommuAmdIsMsiEnabled(pDevIns))
2931 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2932}
2933#endif
2934
2935/**
2936 * Writes an entry to the event log in memory.
2937 *
2938 * @returns VBox status code.
2939 * @param pDevIns The IOMMU device instance.
2940 * @param pEvent The event to log.
2941 *
2942 * @thread Any.
2943 * @remarks The IOMMU lock must be held while calling this function.
2944 */
2945static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2946{
2947 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2948 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2949
2950 IOMMU_LOCK_NORET(pDevIns, pThisCC);
2951
2952 /* Check if event logging is active and the log has not overflowed. */
2953 IOMMU_STATUS_T const Status = pThis->Status;
2954 if ( Status.n.u1EvtLogRunning
2955 && !Status.n.u1EvtOverflow)
2956 {
2957 uint32_t const cbEvt = sizeof(*pEvent);
2958
2959 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2960 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2961 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2962
2963 /* Ensure we have space in the event log. */
2964 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2965 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2966 if (cEvts + 1 < cMaxEvts)
2967 {
2968 /* Write the event log entry to memory. */
2969 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2970 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2971 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2972 if (RT_FAILURE(rc))
2973 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2974
2975 /* Increment the event log tail pointer. */
2976 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2977 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2978
2979 /* Indicate that an event log entry was written. */
2980 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2981
2982 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2983 if (pThis->Ctrl.n.u1EvtIntrEn)
2984 iommuAmdMsiInterruptRaise(pDevIns);
2985 }
2986 else
2987 {
2988 /* Indicate that the event log has overflowed. */
2989 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2990
2991 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2992 if (pThis->Ctrl.n.u1EvtIntrEn)
2993 iommuAmdMsiInterruptRaise(pDevIns);
2994 }
2995 }
2996
2997 IOMMU_UNLOCK(pDevIns, pThisCC);
2998
2999 return VINF_SUCCESS;
3000}
3001
3002
3003/**
3004 * Sets an event in the hardware error registers.
3005 *
3006 * @param pDevIns The IOMMU device instance.
3007 * @param pEvent The event.
3008 *
3009 * @thread Any.
3010 */
3011static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3012{
3013 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3014 if (pThis->ExtFeat.n.u1HwErrorSup)
3015 {
3016 if (pThis->HwEvtStatus.n.u1Valid)
3017 pThis->HwEvtStatus.n.u1Overflow = 1;
3018 pThis->HwEvtStatus.n.u1Valid = 1;
3019 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3020 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3021 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
3022 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
3023 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3024 }
3025}
3026
3027
3028/**
3029 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
3030 *
3031 * @param idDevice The device ID (bus, device, function).
3032 * @param idDomain The domain ID.
3033 * @param GCPhysPtEntity The system physical address of the page table
3034 * entity.
3035 * @param enmOp The IOMMU operation being performed.
3036 * @param pEvtPageTabHwErr Where to store the initialized event.
3037 */
3038static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3039 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3040{
3041 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3042 pEvtPageTabHwErr->n.u16DevId = idDevice;
3043 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3044 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3045 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3046 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3047 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3048 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3049 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3050 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3051}
3052
3053
3054/**
3055 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3056 *
3057 * @param pDevIns The IOMMU device instance.
3058 * @param enmOp The IOMMU operation being performed.
3059 * @param pEvtPageTabHwErr The page table hardware error event.
3060 *
3061 * @thread Any.
3062 */
3063static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3064{
3065 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3066 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3067
3068 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3069 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3070
3071 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3072 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3073 if (enmOp != IOMMUOP_CMD)
3074 iommuAmdSetPciTargetAbort(pDevIns);
3075
3076 IOMMU_UNLOCK(pDevIns, pThisCC);
3077
3078 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3079 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3080 pEvtPageTabHwErr->n.u2Type));
3081}
3082
3083
3084#ifdef IN_RING3
3085/**
3086 * Initializes a COMMAND_HARDWARE_ERROR event.
3087 *
3088 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3089 * @param pEvtCmdHwErr Where to store the initialized event.
3090 */
3091static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3092{
3093 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3094 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3095 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3096 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3097}
3098
3099
3100/**
3101 * Raises a COMMAND_HARDWARE_ERROR event.
3102 *
3103 * @param pDevIns The IOMMU device instance.
3104 * @param pEvtCmdHwErr The command hardware error event.
3105 *
3106 * @thread Any.
3107 */
3108static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3109{
3110 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3111 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3112 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3113
3114 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3115 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3116
3117 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3118 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3119 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3120
3121 IOMMU_UNLOCK(pDevIns, pThisCC);
3122
3123 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3124}
3125#endif /* IN_RING3 */
3126
3127
3128/**
3129 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3130 *
3131 * @param idDevice The device ID (bus, device, function).
3132 * @param GCPhysDte The system physical address of the failed device table
3133 * access.
3134 * @param enmOp The IOMMU operation being performed.
3135 * @param pEvtDevTabHwErr Where to store the initialized event.
3136 */
3137static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3138 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3139{
3140 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3141 pEvtDevTabHwErr->n.u16DevId = idDevice;
3142 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3143 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3144 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3145 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3146 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3147 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3148 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3149}
3150
3151
3152/**
3153 * Raises a DEV_TAB_HARDWARE_ERROR event.
3154 *
3155 * @param pDevIns The IOMMU device instance.
3156 * @param enmOp The IOMMU operation being performed.
3157 * @param pEvtDevTabHwErr The device table hardware error event.
3158 *
3159 * @thread Any.
3160 */
3161static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3162{
3163 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3164 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3165
3166 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3167 IOMMU_LOCK_NORET(pDevIns, pThisCC);
3168
3169 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3170 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3171 if (enmOp != IOMMUOP_CMD)
3172 iommuAmdSetPciTargetAbort(pDevIns);
3173
3174 IOMMU_UNLOCK(pDevIns, pThisCC);
3175
3176 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3177 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3178}
3179
3180
3181#ifdef IN_RING3
3182/**
3183 * Initializes an ILLEGAL_COMMAND_ERROR event.
3184 *
3185 * @param GCPhysCmd The system physical address of the failed command
3186 * access.
3187 * @param pEvtIllegalCmd Where to store the initialized event.
3188 */
3189static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3190{
3191 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3192 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3193 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3194 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3195}
3196
3197
3198/**
3199 * Raises an ILLEGAL_COMMAND_ERROR event.
3200 *
3201 * @param pDevIns The IOMMU device instance.
3202 * @param pEvtIllegalCmd The illegal command error event.
3203 */
3204static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3205{
3206 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3207 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3208 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3209
3210 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3211 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3212
3213 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3214}
3215#endif /* IN_RING3 */
3216
3217
3218/**
3219 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3220 *
3221 * @param idDevice The device ID (bus, device, function).
3222 * @param uIova The I/O virtual address.
3223 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3224 * event was caused by an invalid level encoding in the
3225 * DTE.
3226 * @param enmOp The IOMMU operation being performed.
3227 * @param pEvtIllegalDte Where to store the initialized event.
3228 */
3229static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3230 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3231{
3232 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3233 pEvtIllegalDte->n.u16DevId = idDevice;
3234 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3235 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3236 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3237 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3238 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3239 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3240 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3241 * IOMMU spec here but not for this field for I/O page fault event. */
3242 Assert(!(uIova & UINT64_C(0x3)));
3243}
3244
3245
3246/**
3247 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3248 *
3249 * @param pDevIns The IOMMU instance data.
3250 * @param enmOp The IOMMU operation being performed.
3251 * @param pEvtIllegalDte The illegal device table entry event.
3252 * @param enmEvtType The illegal device table entry event type.
3253 *
3254 * @thread Any.
3255 */
3256static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3257 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3258{
3259 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3260 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3261
3262 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3263 if (enmOp != IOMMUOP_CMD)
3264 iommuAmdSetPciTargetAbort(pDevIns);
3265
3266 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3267 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3268 NOREF(enmEvtType);
3269}
3270
3271
3272/**
3273 * Initializes an IO_PAGE_FAULT event.
3274 *
3275 * @param idDevice The device ID (bus, device, function).
3276 * @param idDomain The domain ID.
3277 * @param uIova The I/O virtual address being accessed.
3278 * @param fPresent Transaction to a page marked as present (including
3279 * DTE.V=1) or interrupt marked as remapped
3280 * (IRTE.RemapEn=1).
3281 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3282 * the I/O page fault was caused by invalid level
3283 * encoding.
3284 * @param fPermDenied Permission denied for the address being accessed.
3285 * @param enmOp The IOMMU operation being performed.
3286 * @param pEvtIoPageFault Where to store the initialized event.
3287 */
3288static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3289 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3290{
3291 Assert(!fPermDenied || fPresent);
3292 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3293 pEvtIoPageFault->n.u16DevId = idDevice;
3294 //pEvtIoPageFault->n.u4PasidHi = 0;
3295 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3296 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3297 //pEvtIoPageFault->n.u1NoExecute = 0;
3298 //pEvtIoPageFault->n.u1User = 0;
3299 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3300 pEvtIoPageFault->n.u1Present = fPresent;
3301 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3302 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3303 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3304 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3305 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3306 pEvtIoPageFault->n.u64Addr = uIova;
3307}
3308
3309
3310/**
3311 * Raises an IO_PAGE_FAULT event.
3312 *
3313 * @param pDevIns The IOMMU instance data.
3314 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3315 * @param pIrte The interrupt remapping table entry, can be NULL.
3316 * @param enmOp The IOMMU operation being performed.
3317 * @param pEvtIoPageFault The I/O page fault event.
3318 * @param enmEvtType The I/O page fault event type.
3319 *
3320 * @thread Any.
3321 */
3322static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3323 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3324{
3325 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3326 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3327
3328#ifdef IOMMU_WITH_DTE_CACHE
3329# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheAddFlags((a_pDevIns), (a_DevId), \
3330 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED)
3331#else
3332# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3333#endif
3334
3335 bool fSuppressEvtLogging = false;
3336 if ( enmOp == IOMMUOP_MEM_READ
3337 || enmOp == IOMMUOP_MEM_WRITE)
3338 {
3339 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3340 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3341 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3342 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3343 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3344 {
3345 fSuppressEvtLogging = true;
3346 }
3347 }
3348 else if (enmOp == IOMMUOP_INTR_REQ)
3349 {
3350 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3351 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3352 fSuppressEvtLogging = true;
3353 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3354 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3355 }
3356 /* else: Events are never suppressed for commands. */
3357
3358 switch (enmEvtType)
3359 {
3360 case kIoPageFaultType_PermDenied:
3361 {
3362 /* Cannot be triggered by a command. */
3363 Assert(enmOp != IOMMUOP_CMD);
3364 RT_FALL_THRU();
3365 }
3366 case kIoPageFaultType_DteRsvdPagingMode:
3367 case kIoPageFaultType_PteInvalidPageSize:
3368 case kIoPageFaultType_PteInvalidLvlEncoding:
3369 case kIoPageFaultType_SkippedLevelIovaNotZero:
3370 case kIoPageFaultType_PteRsvdNotZero:
3371 case kIoPageFaultType_PteValidNotSet:
3372 case kIoPageFaultType_DteTranslationDisabled:
3373 case kIoPageFaultType_PasidInvalidRange:
3374 {
3375 /*
3376 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3377 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3378 */
3379 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3380 {
3381 if (!fSuppressEvtLogging)
3382 {
3383 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3384 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3385 }
3386 if (enmOp != IOMMUOP_CMD)
3387 iommuAmdSetPciTargetAbort(pDevIns);
3388 }
3389 break;
3390 }
3391
3392 case kIoPageFaultType_UserSupervisor:
3393 {
3394 /* Access is blocked and only creates an event log entry. */
3395 if (!fSuppressEvtLogging)
3396 {
3397 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3398 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3399 }
3400 break;
3401 }
3402
3403 case kIoPageFaultType_IrteAddrInvalid:
3404 case kIoPageFaultType_IrteRsvdNotZero:
3405 case kIoPageFaultType_IrteRemapEn:
3406 case kIoPageFaultType_IrteRsvdIntType:
3407 case kIoPageFaultType_IntrReqAborted:
3408 case kIoPageFaultType_IntrWithPasid:
3409 {
3410 /* Only trigerred by interrupt requests. */
3411 Assert(enmOp == IOMMUOP_INTR_REQ);
3412 if (!fSuppressEvtLogging)
3413 {
3414 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3415 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3416 }
3417 iommuAmdSetPciTargetAbort(pDevIns);
3418 break;
3419 }
3420
3421 case kIoPageFaultType_SmiFilterMismatch:
3422 {
3423 /* Not supported and probably will never be, assert. */
3424 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3425 break;
3426 }
3427
3428 case kIoPageFaultType_DevId_Invalid:
3429 {
3430 /* Cannot be triggered by a command. */
3431 Assert(enmOp != IOMMUOP_CMD);
3432 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3433 if (!fSuppressEvtLogging)
3434 {
3435 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3436 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3437 }
3438 if ( enmOp == IOMMUOP_MEM_READ
3439 || enmOp == IOMMUOP_MEM_WRITE)
3440 iommuAmdSetPciTargetAbort(pDevIns);
3441 break;
3442 }
3443 }
3444
3445#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3446}
3447
3448
3449/**
3450 * Raises an IO_PAGE_FAULT event given the DTE.
3451 *
3452 * @param pDevIns The IOMMU instance data.
3453 * @param pDte The device table entry.
3454 * @param pIrte The interrupt remapping table entry, can be NULL.
3455 * @param enmOp The IOMMU operation being performed.
3456 * @param pEvtIoPageFault The I/O page fault event.
3457 * @param enmEvtType The I/O page fault event type.
3458 *
3459 * @thread Any.
3460 */
3461static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3462 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3463{
3464 Assert(pDte);
3465 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3466 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3467}
3468
3469
3470/**
3471 * Reads a device table entry for the given the device ID.
3472 *
3473 * @returns VBox status code.
3474 * @param pDevIns The IOMMU device instance.
3475 * @param idDevice The device ID (bus, device, function).
3476 * @param enmOp The IOMMU operation being performed.
3477 * @param pDte Where to store the device table entry.
3478 *
3479 * @thread Any.
3480 */
3481static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3482{
3483 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3484 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3485
3486 IOMMU_LOCK(pDevIns, pThisCC, VERR_SEM_BUSY);
3487
3488 /* Figure out which device table segment is being accessed. */
3489 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3490 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3491
3492 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3493 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3494 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3495
3496 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3497 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3498 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3499
3500 /* Ensure the DTE falls completely within the device table segment. */
3501 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3502
3503 IOMMU_UNLOCK(pDevIns, pThisCC);
3504
3505 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3506 {
3507 /* Read the device table entry from guest memory. */
3508 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3509 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3510 if (RT_SUCCESS(rc))
3511 return rc;
3512
3513 /* Raise a device table hardware error. */
3514 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3515
3516 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3517 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3518 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3519 return VERR_IOMMU_DTE_READ_FAILED;
3520 }
3521
3522 /* Raise an I/O page fault for out-of-bounds acccess. */
3523 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3524 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3525 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3526 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3527 kIoPageFaultType_DevId_Invalid);
3528 return VERR_IOMMU_DTE_BAD_OFFSET;
3529}
3530
3531
3532/**
3533 * Performs pre-translation checks for the given device table entry.
3534 *
3535 * @returns VBox status code.
3536 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3537 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3538 * translation is disabled.
3539 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3540 * corresponding event was raised.
3541 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3542 * permissions.
3543 *
3544 * @param pDevIns The IOMMU device instance.
3545 * @param uIova The I/O virtual address to translate.
3546 * @param idDevice The device ID (bus, device, function).
3547 * @param fPerm The I/O permissions for this access, see
3548 * IOMMU_IO_PERM_XXX.
3549 * @param pDte The device table entry.
3550 * @param enmOp The IOMMU operation being performed.
3551 *
3552 * @thread Any.
3553 */
3554static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3555 IOMMUOP enmOp)
3556{
3557 /*
3558 * Check if the translation is valid, otherwise raise an I/O page fault.
3559 */
3560 if (pDte->n.u1TranslationValid)
3561 { /* likely */ }
3562 else
3563 {
3564 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3565 * doesn't explicitly say whether an I/O page fault is raised. From other
3566 * places in the spec. it seems early page walk terminations (starting with
3567 * the DTE) return the state computed so far and raises an I/O page fault. So
3568 * returning an invalid translation rather than skipping translation. */
3569 LogFunc(("Translation valid bit not set -> IOPF\n"));
3570 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3571 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3572 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3573 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3574 kIoPageFaultType_DteTranslationDisabled);
3575 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3576 }
3577
3578 /*
3579 * Check permissions bits in the DTE.
3580 * Note: This MUST be checked prior to checking the root page table level below!
3581 */
3582 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3583 if ((fPerm & fDtePerm) == fPerm)
3584 { /* likely */ }
3585 else
3586 {
3587 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3588 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3589 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3590 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3591 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3592 kIoPageFaultType_PermDenied);
3593 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3594 }
3595
3596 /*
3597 * If the root page table level is 0, translation is disabled and GPA=SPA and
3598 * the DTE.IR and DTE.IW bits control permissions (verified above).
3599 */
3600 uint8_t const uMaxLevel = pDte->n.u3Mode;
3601 if (uMaxLevel != 0)
3602 { /* likely */ }
3603 else
3604 {
3605 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3606 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3607 }
3608
3609 /*
3610 * If the root page table level exceeds the allowed host-address translation level,
3611 * page walk is terminated and translation fails.
3612 */
3613 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3614 { /* likely */ }
3615 else
3616 {
3617 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3618 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3619 * I'm just going with I/O page fault. */
3620 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3621 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3622 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3623 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3624 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3625 kIoPageFaultType_PteInvalidLvlEncoding);
3626 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3627 }
3628
3629 /* The DTE allows translations for this device. */
3630 return VINF_SUCCESS;
3631}
3632
3633
3634/**
3635 * Walks the I/O page table to translate the I/O virtual address to a system
3636 * physical address.
3637 *
3638 * @returns VBox status code.
3639 * @param pDevIns The IOMMU device instance.
3640 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3641 * @param fPerm The I/O permissions for this access, see
3642 * IOMMU_IO_PERM_XXX.
3643 * @param idDevice The device ID (bus, device, function).
3644 * @param pDte The device table entry.
3645 * @param enmOp The IOMMU operation being performed.
3646 * @param pPageLookup Where to store the results of the I/O page lookup. This
3647 * is only updated when VINF_SUCCESS is returned.
3648 *
3649 * @thread Any.
3650 */
3651static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3652 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3653{
3654 Assert(pDte->n.u1Valid);
3655 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3656
3657 /* The virtual address bits indexing table. */
3658 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3659 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
3660 UINT64_C(0x00000000001ff000),
3661 UINT64_C(0x000000003fe00000),
3662 UINT64_C(0x0000007fc0000000),
3663 UINT64_C(0x0000ff8000000000),
3664 UINT64_C(0x01ff000000000000),
3665 UINT64_C(0xfe00000000000000),
3666 UINT64_C(0x0000000000000000) };
3667 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
3668 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3669
3670 /* Traverse the I/O page table starting with the page directory in the DTE. */
3671 IOPTENTITY_T PtEntity;
3672 PtEntity.u64 = pDte->au64[0];
3673 for (;;)
3674 {
3675 /* Figure out the system physical address of the page table at the current level. */
3676 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3677
3678 /* Read the page table entity at the current level. */
3679 {
3680 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3681 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3682 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3683 uint64_t const offPte = idxPte << 3;
3684 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3685 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3686 if (RT_FAILURE(rc))
3687 {
3688 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3689 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3690 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3691 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3692 return VERR_IOMMU_IPE_2;
3693 }
3694 }
3695
3696 /* Check present bit. */
3697 if (PtEntity.n.u1Present)
3698 { /* likely */ }
3699 else
3700 {
3701 LogFunc(("Page table entry not present (idDevice=%#x) -> IOPF\n", idDevice));
3702 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3703 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3704 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3705 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3706 kIoPageFaultType_PermDenied);
3707 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3708 }
3709
3710 /* Check permission bits. */
3711 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3712 if ((fPerm & fPtePerm) == fPerm)
3713 { /* likely */ }
3714 else
3715 {
3716 LogFunc(("Page table entry access denied (idDevice=%#x fPerm=%#x fPtePerm=%#x) -> IOPF\n", idDevice, fPerm, fPtePerm));
3717 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3718 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3719 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3720 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3721 kIoPageFaultType_PermDenied);
3722 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3723 }
3724
3725 /* If this is a PTE, we're at the final level and we're done. */
3726 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3727 if (uNextLevel == 0)
3728 {
3729 /* The page size of the translation is the default (4K). */
3730 pPageLookup->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3731 pPageLookup->cShift = X86_PAGE_4K_SHIFT;
3732 pPageLookup->fPerm = fPtePerm;
3733 return VINF_SUCCESS;
3734 }
3735 if (uNextLevel == 7)
3736 {
3737 /* The default page size of the translation is overridden. */
3738 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3739 uint8_t cShift = X86_PAGE_4K_SHIFT;
3740 while (GCPhysPte & RT_BIT_64(cShift++))
3741 ;
3742
3743 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3744 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
3745 if ( cShift > s_acIovaLevelShifts[uLevel]
3746 && cShift < s_acIovaLevelShifts[uLevel + 1])
3747 {
3748 pPageLookup->GCPhysSpa = GCPhysPte;
3749 pPageLookup->cShift = cShift;
3750 pPageLookup->fPerm = fPtePerm;
3751 return VINF_SUCCESS;
3752 }
3753
3754 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
3755 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3756 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3757 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3758 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3759 kIoPageFaultType_PteInvalidPageSize);
3760 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3761 }
3762
3763 /* Validate the next level encoding of the PDE. */
3764#if IOMMU_MAX_HOST_PT_LEVEL < 6
3765 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3766 { /* likely */ }
3767 else
3768 {
3769 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
3770 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3771 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3772 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3773 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3774 kIoPageFaultType_PteInvalidLvlEncoding);
3775 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3776 }
3777#else
3778 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3779#endif
3780
3781 /* Validate level transition. */
3782 if (uNextLevel < uLevel)
3783 { /* likely */ }
3784 else
3785 {
3786 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3787 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3788 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3789 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3790 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3791 kIoPageFaultType_PteInvalidLvlEncoding);
3792 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3793 }
3794
3795 /* Ensure IOVA bits of skipped levels are zero. */
3796 Assert(uLevel > 0);
3797 uint64_t uIovaSkipMask = 0;
3798 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
3799 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
3800 if (!(uIova & uIovaSkipMask))
3801 { /* likely */ }
3802 else
3803 {
3804 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
3805 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3806 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3807 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3808 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3809 kIoPageFaultType_SkippedLevelIovaNotZero);
3810 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3811 }
3812
3813 /* Continue with traversing the page directory at this level. */
3814 }
3815}
3816
3817
3818/**
3819 * Page lookup callback for finding an I/O page from guest memory.
3820 *
3821 * @returns VBox status code.
3822 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3823 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3824 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3825 * insufficient to what is requested.
3826 *
3827 * @param pDevIns The IOMMU instance data.
3828 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3829 * 4K aligned).
3830 * @param fPerm The I/O permissions for this access, see
3831 * IOMMU_IO_PERM_XXX.
3832 * @param pAux The auxiliary information required during lookup.
3833 * @param pPageLookup Where to store the looked up I/O page.
3834 */
3835static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3836 PIOPAGELOOKUP pPageLookup)
3837{
3838 AssertPtr(pAux);
3839 AssertPtr(pPageLookup);
3840 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3841
3842 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3843 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3844 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3845 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3846 return rc;
3847}
3848
3849
3850/**
3851 * Looks up a range of I/O virtual addresses.
3852 *
3853 * @returns VBox status code.
3854 * @param pDevIns The IOMMU instance data.
3855 * @param pfnIoPageLookup The lookup function to use.
3856 * @param pAddrIn The I/O address range to lookup.
3857 * @param pAux The auxiliary information required by the lookup
3858 * function.
3859 * @param pAddrOut Where to store the translated I/O address range.
3860 * @param pcbPages Where to store the size of the access (round up to
3861 * the page size). Optional, can be NULL.
3862 */
3863static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3864 PCIOMMUOPAUX pAux, PIOADDRRANGE pAddrOut, size_t *pcbPages)
3865{
3866 AssertPtr(pfnIoPageLookup);
3867 AssertPtr(pAddrIn);
3868 AssertPtr(pAddrOut);
3869
3870 int rc;
3871 size_t const cbIova = pAddrIn->cb;
3872 uint8_t const fPerm = pAddrIn->fPerm;
3873 uint64_t const uIova = pAddrIn->uAddr;
3874 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3875 size_t cbRemaining = cbIova;
3876 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3877 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3878 uint64_t cbPages = 0;
3879
3880 IOPAGELOOKUP PageLookupPrev;
3881 RT_ZERO(PageLookupPrev);
3882 for (;;)
3883 {
3884 IOPAGELOOKUP PageLookup;
3885 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3886 if (RT_SUCCESS(rc))
3887 {
3888 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT);
3889
3890 /* Store the translated address before continuing to access more pages. */
3891 if (cbRemaining == cbIova)
3892 {
3893 uint64_t const offMask = IOMMU_GET_PAGE_OFF_MASK(PageLookup.cShift);
3894 uint64_t const offSpa = uIova & offMask;
3895 Assert(!(PageLookup.GCPhysSpa & offMask));
3896 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3897 }
3898 /* Check if addresses translated so far result in a physically contiguous region. */
3899 else if (!iommuAmdLookupIsAccessContig(&PageLookupPrev, &PageLookup))
3900 {
3901 rc = VERR_OUT_OF_RANGE;
3902 break;
3903 }
3904
3905 /* Store the page lookup result from the first/previous page. */
3906 PageLookupPrev = PageLookup;
3907
3908 /* Update size of all pages read thus far. */
3909 uint64_t const cbPage = RT_BIT_64(PageLookup.cShift);
3910 cbPages += cbPage;
3911
3912 /* Check if we need to access more pages. */
3913 if (cbRemaining > cbPage - offIova)
3914 {
3915 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3916 uIovaPage += cbPage; /* Update address of the next access. */
3917 offIova = 0; /* After first page, all pages are accessed from off 0. */
3918 }
3919 else
3920 {
3921 cbRemaining = 0;
3922 break;
3923 }
3924 }
3925 else
3926 break;
3927 }
3928
3929 pAddrOut->uAddr = GCPhysSpa; /* Update the translated address. */
3930 pAddrOut->cb = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
3931 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
3932 if (pcbPages)
3933 *pcbPages = cbPages; /* Update the size of the pages accessed. */
3934 return rc;
3935}
3936
3937
3938/**
3939 * Looks up an I/O virtual address from the device table.
3940 *
3941 * @returns VBox status code.
3942 * @param pDevIns The IOMMU instance data.
3943 * @param idDevice The device ID (bus, device, function).
3944 * @param uIova The I/O virtual address to lookup.
3945 * @param cbIova The size of the access.
3946 * @param fPerm The I/O permissions for this access, see
3947 * IOMMU_IO_PERM_XXX.
3948 * @param enmOp The IOMMU operation being performed.
3949 * @param pGCPhysSpa Where to store the translated system physical address.
3950 * @param pcbContiguous Where to store the number of contiguous bytes translated
3951 * and permission-checked.
3952 *
3953 * @thread Any.
3954 */
3955static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
3956 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3957{
3958 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3959 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3960 size_t cbContiguous = 0;
3961
3962 /* Read the device table entry from memory. */
3963 DTE_T Dte;
3964 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
3965 if (RT_SUCCESS(rc))
3966 {
3967 if (Dte.n.u1Valid)
3968 {
3969 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3970 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3971 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3972 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
3973 {
3974 /*
3975 * Check if the DTE is configured for translating addresses.
3976 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
3977 * so there's no need to check the address exclusion base/limit here.
3978 */
3979 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
3980 if (rc == VINF_SUCCESS)
3981 {
3982 IOADDRRANGE AddrIn;
3983 AddrIn.uAddr = uIova;
3984 AddrIn.cb = cbIova;
3985 AddrIn.fPerm = fPerm;
3986
3987 IOMMUOPAUX Aux;
3988 Aux.enmOp = enmOp;
3989 Aux.pDte = &Dte;
3990 Aux.idDevice = idDevice;
3991 Aux.idDomain = Dte.n.u16DomainId;
3992
3993 IOADDRRANGE AddrOut;
3994
3995 /* Lookup the address from the DTE and I/O page tables.*/
3996 size_t cbPages = 0;
3997 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbPages);
3998 GCPhysSpa = AddrOut.uAddr;
3999 cbContiguous = AddrOut.cb;
4000
4001 /* If we stopped since translation resulted in non-contiguous physical addresses,
4002 what we translated so far is still valid. */
4003 if (rc == VERR_OUT_OF_RANGE)
4004 {
4005 Assert(cbContiguous > 0 && cbContiguous < cbIova);
4006 rc = VINF_SUCCESS;
4007 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
4008 }
4009
4010 if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
4011 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4012
4013#ifdef IOMMU_WITH_IOTLBE_CACHE
4014 if (RT_SUCCESS(rc))
4015 {
4016 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
4017 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
4018 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
4019 iommuAmdIotlbAddRange(pDevIns, Dte.n.u16DomainId, uIova & X86_PAGE_4K_BASE_MASK, cbPages,
4020 GCPhysSpa & X86_PAGE_4K_BASE_MASK, AddrOut.fPerm);
4021 }
4022#endif
4023 }
4024 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
4025 {
4026 /*
4027 * Translation is disabled for this device (root paging mode is 0).
4028 * GPA=SPA, but the permission bits are important and controls accesses.
4029 */
4030 GCPhysSpa = uIova;
4031 cbContiguous = cbIova;
4032 rc = VINF_SUCCESS;
4033
4034#ifdef IOMMU_WITH_IOTLBE_CACHE
4035 /* Update that addresses permissions of DTE apply (but omit address translation). */
4036 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_IO_PERM);
4037#endif
4038 }
4039 else
4040 {
4041 /* Address translation failed or access is denied. */
4042 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4043 GCPhysSpa = NIL_RTGCPHYS;
4044 cbContiguous = 0;
4045 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4046 }
4047 }
4048 else
4049 {
4050 /* Invalid reserved bits in the DTE, raise an error event. */
4051 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4052 EVT_ILLEGAL_DTE_T Event;
4053 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4054 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4055 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4056 }
4057 }
4058 else
4059 {
4060 /*
4061 * The DTE is not valid, forward addresses untranslated.
4062 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4063 */
4064 GCPhysSpa = uIova;
4065 cbContiguous = cbIova;
4066
4067#ifdef IOMMU_WITH_IOTLBE_CACHE
4068 /* Update that addresses don't require translation (nor permission checks) but a DTE is present. */
4069 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4070#endif
4071 }
4072 }
4073 else
4074 {
4075 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4076 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4077 }
4078
4079 *pGCPhysSpa = GCPhysSpa;
4080 *pcbContiguous = cbContiguous;
4081 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4082 return rc;
4083}
4084
4085
4086#ifdef IOMMU_WITH_IOTLBE_CACHE
4087/**
4088 * I/O page lookup callback for finding an I/O page from the IOTLB.
4089 *
4090 * @returns VBox status code.
4091 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4092 * @retval VERR_NOT_FOUND when the page is not found.
4093 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4094 * insufficient to what is requested.
4095 *
4096 * @param pDevIns The IOMMU instance data.
4097 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4098 * 4K aligned).
4099 * @param fPerm The I/O permissions for this access, see
4100 * IOMMU_IO_PERM_XXX.
4101 * @param pAux The auxiliary information required during lookup.
4102 * @param pPageLookup Where to store the looked up I/O page.
4103 */
4104static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4105 PIOPAGELOOKUP pPageLookup)
4106{
4107 Assert(pAux);
4108 Assert(pPageLookup);
4109 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4110
4111 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4112 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4113
4114 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4115 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4116 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4117 if (pIotlbe)
4118 {
4119 *pPageLookup = pIotlbe->PageLookup;
4120 if ((pPageLookup->fPerm & fPerm) == fPerm)
4121 {
4122 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4123 return VINF_SUCCESS;
4124 }
4125 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4126 }
4127 return VERR_NOT_FOUND;
4128}
4129
4130
4131/**
4132 * Lookups a memory access from the IOTLB cache.
4133 *
4134 * @returns VBox status code.
4135 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4136 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4137 * address region.
4138 * @retval VERR_NOT_FOUND if the access was not cached.
4139 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4140 * are insufficient.
4141 *
4142 * @param pDevIns The IOMMU instance data.
4143 * @param idDevice The device ID (bus, device, function).
4144 * @param uIova The I/O virtual address to lookup.
4145 * @param cbIova The size of the access.
4146 * @param fPerm The I/O permissions for this access, see
4147 * IOMMU_IO_PERM_XXX.
4148 * @param enmOp The IOMMU operation being performed.
4149 * @param pGCPhysSpa Where to store the translated system physical address.
4150 * @param pcbContiguous Where to store the number of contiguous bytes translated
4151 * and permission-checked.
4152 */
4153static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4154 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4155{
4156 int rc;
4157 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4158
4159#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4160 do { \
4161 *pGCPhysSpa = NIL_RTGCPHYS; \
4162 *pcbContiguous = 0; \
4163 rc = (a_rc); \
4164 } while (0)
4165
4166 /*
4167 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4168 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4169 */
4170 IOMMU_LOCK_CACHE(pDevIns, pThis);
4171
4172 /* Lookup the DTE cache entry. */
4173 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4174 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4175 {
4176 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4177 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4178 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4179 {
4180 /* Lookup IOTLB entries. */
4181 IOADDRRANGE AddrIn;
4182 AddrIn.uAddr = uIova;
4183 AddrIn.cb = cbIova;
4184 AddrIn.fPerm = fPerm;
4185
4186 IOMMUOPAUX Aux;
4187 Aux.enmOp = enmOp;
4188 Aux.pDte = NULL;
4189 Aux.idDevice = idDevice;
4190 Aux.idDomain = pDteCache->idDomain;
4191
4192 IOADDRRANGE AddrOut;
4193 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, NULL /* pcbPages */);
4194 Assert(AddrOut.cb <= cbIova);
4195 *pGCPhysSpa = AddrOut.uAddr;
4196 *pcbContiguous = AddrOut.cb;
4197 }
4198 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4199 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4200 {
4201 /* Address translation is disabled, but DTE permissions apply. */
4202 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4203 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4204 if ((fDtePerm & fPerm) == fPerm)
4205 {
4206 *pGCPhysSpa = uIova;
4207 *pcbContiguous = cbIova;
4208 rc = VINF_SUCCESS;
4209 }
4210 else
4211 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4212 }
4213 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4214 {
4215 /* Forward addresses untranslated, without checking permissions. */
4216 *pGCPhysSpa = uIova;
4217 *pcbContiguous = cbIova;
4218 rc = VINF_SUCCESS;
4219 }
4220 else
4221 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4222 }
4223 else
4224 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4225
4226 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
4227
4228 return rc;
4229
4230#undef IOMMU_IOTLB_LOOKUP_FAILED
4231}
4232#endif /* IOMMU_WITH_IOTLBE_CACHE */
4233
4234
4235/**
4236 * Gets the I/O permission and IOMMU operation type for the given access flags.
4237 *
4238 * @param pThis The shared IOMMU device state.
4239 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4240 * @param penmOp Where to store the IOMMU operation.
4241 * @param pfPerm Where to store the IOMMU I/O permission.
4242 * @param fBulk Whether this is a bulk read or write.
4243 */
4244DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4245{
4246 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4247 {
4248 *penmOp = IOMMUOP_MEM_WRITE;
4249 *pfPerm = IOMMU_IO_PERM_WRITE;
4250#ifdef VBOX_WITH_STATISTICS
4251 if (!fBulk)
4252 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4253 else
4254 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4255#else
4256 RT_NOREF2(pThis, fBulk);
4257#endif
4258 }
4259 else
4260 {
4261 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4262 *penmOp = IOMMUOP_MEM_READ;
4263 *pfPerm = IOMMU_IO_PERM_READ;
4264#ifdef VBOX_WITH_STATISTICS
4265 if (!fBulk)
4266 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4267 else
4268 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4269#else
4270 RT_NOREF2(pThis, fBulk);
4271#endif
4272 }
4273}
4274
4275
4276/**
4277 * Memory access transaction from a device.
4278 *
4279 * @returns VBox status code.
4280 * @param pDevIns The IOMMU device instance.
4281 * @param idDevice The device ID (bus, device, function).
4282 * @param uIova The I/O virtual address being accessed.
4283 * @param cbIova The size of the access.
4284 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4285 * @param pGCPhysSpa Where to store the translated system physical address.
4286 * @param pcbContiguous Where to store the number of contiguous bytes translated
4287 * and permission-checked.
4288 *
4289 * @thread Any.
4290 */
4291static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4292 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4293{
4294 /* Validate. */
4295 AssertPtr(pDevIns);
4296 AssertPtr(pGCPhysSpa);
4297 Assert(cbIova > 0);
4298 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4299
4300 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4301 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4302 if (Ctrl.n.u1IommuEn)
4303 {
4304 IOMMUOP enmOp;
4305 uint8_t fPerm;
4306 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4307 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4308
4309 int rc;
4310#ifdef IOMMU_WITH_IOTLBE_CACHE
4311 /* Lookup the IOVA from the cache. */
4312 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4313 if (rc == VINF_SUCCESS)
4314 {
4315 /* All pages in the access were found in the cache with sufficient permissions. */
4316 Assert(*pcbContiguous == cbIova);
4317 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4318 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4319 return VINF_SUCCESS;
4320 }
4321 if (rc != VERR_OUT_OF_RANGE)
4322 { /* likely */ }
4323 else
4324 {
4325 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4326 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4327 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4328 return VINF_SUCCESS;
4329 }
4330
4331 /*
4332 * Access incomplete as not all pages were in the cache.
4333 * Or permissions were denied for the access (which typically doesn't happen)
4334 * so go through the slower path and raise the required event.
4335 */
4336 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4337 uIova += *pcbContiguous;
4338 cbIova -= *pcbContiguous;
4339 /* We currently are including any permission denied pages as cache misses too.*/
4340 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4341#endif
4342
4343 /* Lookup the IOVA from the device table. */
4344 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4345 if (RT_SUCCESS(rc))
4346 { /* likely */ }
4347 else
4348 {
4349 Assert(rc != VERR_OUT_OF_RANGE);
4350 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4351 cbIova, rc));
4352 }
4353
4354 return rc;
4355 }
4356
4357 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4358 *pGCPhysSpa = uIova;
4359 *pcbContiguous = cbIova;
4360 return VINF_SUCCESS;
4361}
4362
4363
4364/**
4365 * Memory access bulk (one or more 4K pages) request from a device.
4366 *
4367 * @returns VBox status code.
4368 * @param pDevIns The IOMMU device instance.
4369 * @param idDevice The device ID (bus, device, function).
4370 * @param cIovas The number of addresses being accessed.
4371 * @param pauIovas The I/O virtual addresses for each page being accessed.
4372 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4373 * @param paGCPhysSpa Where to store the translated physical addresses.
4374 *
4375 * @thread Any.
4376 */
4377static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4378 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4379{
4380 /* Validate. */
4381 AssertPtr(pDevIns);
4382 Assert(cIovas > 0);
4383 AssertPtr(pauIovas);
4384 AssertPtr(paGCPhysSpa);
4385 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4386
4387 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4388 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4389 if (Ctrl.n.u1IommuEn)
4390 {
4391 IOMMUOP enmOp;
4392 uint8_t fPerm;
4393 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4394 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4395
4396 for (size_t i = 0; i < cIovas; i++)
4397 {
4398 int rc;
4399 size_t cbContig;
4400
4401#ifdef IOMMU_WITH_IOTLBE_CACHE
4402 /* Lookup the IOVA from the IOTLB cache. */
4403 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4404 &cbContig);
4405 if (rc == VINF_SUCCESS)
4406 {
4407 Assert(cbContig == X86_PAGE_SIZE);
4408 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4409 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4410 continue;
4411 }
4412 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4413 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4414#endif
4415
4416 /* Lookup the IOVA from the device table. */
4417 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4418 if (RT_SUCCESS(rc))
4419 { /* likely */ }
4420 else
4421 {
4422 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4423 return rc;
4424 }
4425 Assert(cbContig == X86_PAGE_SIZE);
4426 }
4427 }
4428 else
4429 {
4430 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4431 for (size_t i = 0; i < cIovas; i++)
4432 paGCPhysSpa[i] = pauIovas[i];
4433 }
4434
4435 return VINF_SUCCESS;
4436}
4437
4438
4439/**
4440 * Reads an interrupt remapping table entry from guest memory given its DTE.
4441 *
4442 * @returns VBox status code.
4443 * @param pDevIns The IOMMU device instance.
4444 * @param idDevice The device ID (bus, device, function).
4445 * @param pDte The device table entry.
4446 * @param GCPhysIn The source MSI address (used for reporting errors).
4447 * @param uDataIn The source MSI data.
4448 * @param enmOp The IOMMU operation being performed.
4449 * @param pIrte Where to store the interrupt remapping table entry.
4450 *
4451 * @thread Any.
4452 */
4453static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4454 IOMMUOP enmOp, PIRTE_T pIrte)
4455{
4456 /* Ensure the IRTE length is valid. */
4457 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4458
4459 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4460 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4461 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4462 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4463
4464 /* Ensure the IRTE falls completely within the interrupt table. */
4465 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4466 { /* likely */ }
4467 else
4468 {
4469 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4470 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4471
4472 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4473 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4474 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4475 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4476 kIoPageFaultType_IrteAddrInvalid);
4477 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4478 }
4479
4480 /* Read the IRTE from memory. */
4481 Assert(!(GCPhysIrte & 3));
4482 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4483 if (RT_SUCCESS(rc))
4484 return VINF_SUCCESS;
4485
4486 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4487 * situation. Is it an I/O page fault or a device table hardware error?
4488 * There's no interrupt table hardware error event, but it's unclear what
4489 * we should do here. */
4490 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4491 return VERR_IOMMU_IPE_4;
4492}
4493
4494
4495/**
4496 * Remaps the interrupt using the interrupt remapping table.
4497 *
4498 * @returns VBox status code.
4499 * @param pDevIns The IOMMU instance data.
4500 * @param idDevice The device ID (bus, device, function).
4501 * @param pDte The device table entry.
4502 * @param enmOp The IOMMU operation being performed.
4503 * @param pMsiIn The source MSI.
4504 * @param pMsiOut Where to store the remapped MSI.
4505 *
4506 * @thread Any.
4507 */
4508static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4509 PMSIMSG pMsiOut)
4510{
4511 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4512
4513 IRTE_T Irte;
4514 uint32_t const uMsiInData = pMsiIn->Data.u32;
4515 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4516 if (RT_SUCCESS(rc))
4517 {
4518 if (Irte.n.u1RemapEnable)
4519 {
4520 if (!Irte.n.u1GuestMode)
4521 {
4522 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4523 {
4524 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4525#ifdef IOMMU_WITH_IRTE_CACHE
4526 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4527#endif
4528 return VINF_SUCCESS;
4529 }
4530
4531 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4532 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4533 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4534 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4535 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4536 kIoPageFaultType_IrteRsvdIntType);
4537 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4538 }
4539
4540 LogFunc(("Guest mode not supported -> IOPF\n"));
4541 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4542 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4543 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4544 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4545 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4546 }
4547
4548 LogFunc(("Remapping disabled -> IOPF\n"));
4549 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4550 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4551 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4552 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4553 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4554 }
4555
4556 return rc;
4557}
4558
4559
4560/**
4561 * Looks up an MSI interrupt from the interrupt remapping table.
4562 *
4563 * @returns VBox status code.
4564 * @param pDevIns The IOMMU instance data.
4565 * @param idDevice The device ID (bus, device, function).
4566 * @param enmOp The IOMMU operation being performed.
4567 * @param pMsiIn The source MSI.
4568 * @param pMsiOut Where to store the remapped MSI.
4569 *
4570 * @thread Any.
4571 */
4572static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4573{
4574 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4575 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4576 enmOp));
4577
4578 /* Read the device table entry from memory. */
4579 DTE_T Dte;
4580 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4581 if (RT_SUCCESS(rc))
4582 {
4583#ifdef IOMMU_WITH_IRTE_CACHE
4584 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4585#endif
4586 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4587 if (Dte.n.u1IntrMapValid)
4588 {
4589 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4590 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4591 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4592 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4593 { /* likely */ }
4594 else
4595 {
4596 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4597 EVT_ILLEGAL_DTE_T Event;
4598 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4599 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4600 return VERR_IOMMU_INTR_REMAP_FAILED;
4601 }
4602
4603 /*
4604 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4605 * that's connected through HyperTransport it might be possible; but for us, it
4606 * doesn't seem we need to specially handle these pins.
4607 */
4608
4609 /*
4610 * Validate the MSI source address.
4611 *
4612 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4613 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4614 * claims the region as I/O space.
4615 *
4616 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4617 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4618 * See Intel spec. 10.11.1 "Message Address Register Format".
4619 */
4620 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4621 {
4622 /*
4623 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4624 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4625 */
4626 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4627 bool fPassThru = false;
4628 switch (u8DeliveryMode)
4629 {
4630 case VBOX_MSI_DELIVERY_MODE_FIXED:
4631 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4632 {
4633 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4634 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4635 {
4636 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4637 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4638 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4639 {
4640 /*
4641 * We don't support guest interrupt remapping yet. When we do, we'll need to
4642 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4643 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4644 * already reads the control register, add that as a parameter when we eventually
4645 * support guest interrupt remapping. For now, just assert.
4646 */
4647 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4648 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4649 NOREF(pThis);
4650
4651 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4652 }
4653
4654 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4655 EVT_ILLEGAL_DTE_T Event;
4656 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4657 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4658 return VERR_IOMMU_INTR_REMAP_FAILED;
4659 }
4660
4661 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4662 {
4663 fPassThru = true;
4664 break;
4665 }
4666
4667 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4668 {
4669 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4670 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4671 iommuAmdSetPciTargetAbort(pDevIns);
4672 return VERR_IOMMU_INTR_REMAP_DENIED;
4673 }
4674
4675 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4676 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4677 EVT_ILLEGAL_DTE_T Event;
4678 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4679 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4680 return VERR_IOMMU_INTR_REMAP_FAILED;
4681 }
4682
4683 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4684 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4685 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4686 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4687 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4688 default:
4689 {
4690 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4691 u8DeliveryMode));
4692 iommuAmdSetPciTargetAbort(pDevIns);
4693 return VERR_IOMMU_INTR_REMAP_FAILED;
4694 }
4695 }
4696
4697 /*
4698 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4699 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4700 */
4701 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4702 || !pMsiIn->Addr.n.u1DestMode)
4703 {
4704 if (fPassThru)
4705 {
4706 *pMsiOut = *pMsiIn;
4707 return VINF_SUCCESS;
4708 }
4709 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4710 pMsiIn->Data.n.u8Vector));
4711 }
4712 else
4713 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4714 IOMMU_LOG_PFX, u8DeliveryMode));
4715
4716 iommuAmdSetPciTargetAbort(pDevIns);
4717 return VERR_IOMMU_INTR_REMAP_DENIED;
4718 }
4719 else
4720 {
4721 /** @todo should be cause a PCI target abort here? */
4722 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4723 return VERR_IOMMU_INTR_REMAP_FAILED;
4724 }
4725 }
4726 else
4727 {
4728 LogFlowFunc(("DTE interrupt map not valid\n"));
4729 *pMsiOut = *pMsiIn;
4730 return VINF_SUCCESS;
4731 }
4732 }
4733
4734 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4735 return VERR_IOMMU_INTR_REMAP_FAILED;
4736}
4737
4738
4739/**
4740 * Interrupt remap request from a device.
4741 *
4742 * @returns VBox status code.
4743 * @param pDevIns The IOMMU device instance.
4744 * @param idDevice The device ID (bus, device, function).
4745 * @param pMsiIn The source MSI.
4746 * @param pMsiOut Where to store the remapped MSI.
4747 */
4748static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4749{
4750 /* Validate. */
4751 Assert(pDevIns);
4752 Assert(pMsiIn);
4753 Assert(pMsiOut);
4754
4755 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4756
4757 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4758 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4759 if (Ctrl.n.u1IommuEn)
4760 {
4761 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4762
4763 int rc;
4764#ifdef IOMMU_WITH_IRTE_CACHE
4765 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4766 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4767 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4768 if (RT_SUCCESS(rc))
4769 {
4770 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4771 return VINF_SUCCESS;
4772 }
4773 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4774#endif
4775
4776 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4777 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4778 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4779 return rc;
4780 }
4781
4782 *pMsiOut = *pMsiIn;
4783 return VINF_SUCCESS;
4784}
4785
4786
4787/**
4788 * @callback_method_impl{FNIOMMMIONEWWRITE}
4789 */
4790static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4791{
4792 NOREF(pvUser);
4793 Assert(cb == 4 || cb == 8);
4794 Assert(!(off & (cb - 1)));
4795
4796 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4797 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4798
4799 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4800 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4801}
4802
4803
4804/**
4805 * @callback_method_impl{FNIOMMMIONEWREAD}
4806 */
4807static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4808{
4809 NOREF(pvUser);
4810 Assert(cb == 4 || cb == 8);
4811 Assert(!(off & (cb - 1)));
4812
4813 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4814 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4815
4816 uint64_t uResult;
4817 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4818 if (rcStrict == VINF_SUCCESS)
4819 {
4820 if (cb == 8)
4821 *(uint64_t *)pv = uResult;
4822 else
4823 *(uint32_t *)pv = (uint32_t)uResult;
4824 }
4825
4826 return rcStrict;
4827}
4828
4829
4830#ifdef IN_RING3
4831/**
4832 * Processes an IOMMU command.
4833 *
4834 * @returns VBox status code.
4835 * @param pDevIns The IOMMU device instance.
4836 * @param pCmd The command to process.
4837 * @param GCPhysCmd The system physical address of the command.
4838 * @param pEvtError Where to store the error event in case of failures.
4839 *
4840 * @thread Command thread.
4841 */
4842static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4843{
4844 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4845 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4846
4847 STAM_COUNTER_INC(&pThis->StatCmd);
4848
4849 uint8_t const bCmd = pCmd->n.u4Opcode;
4850 switch (bCmd)
4851 {
4852 case IOMMU_CMD_COMPLETION_WAIT:
4853 {
4854 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4855
4856 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4857 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4858
4859 /* Validate reserved bits in the command. */
4860 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4861 {
4862 /* If Completion Store is requested, write the StoreData to the specified address. */
4863 if (pCmdComWait->n.u1Store)
4864 {
4865 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4866 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4867 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4868 if (RT_FAILURE(rc))
4869 {
4870 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4871 GCPhysStore, rc));
4872 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4873 return VERR_IOMMU_CMD_HW_ERROR;
4874 }
4875 }
4876
4877 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4878 if (pCmdComWait->n.u1Interrupt)
4879 {
4880 IOMMU_LOCK(pDevIns, pThisR3, VERR_IGNORED);
4881 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4882 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4883 IOMMU_UNLOCK(pDevIns, pThisR3);
4884 if (fRaiseInt)
4885 iommuAmdMsiInterruptRaise(pDevIns);
4886 }
4887 return VINF_SUCCESS;
4888 }
4889 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4890 return VERR_IOMMU_CMD_INVALID_FORMAT;
4891 }
4892
4893 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4894 {
4895 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4896 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4897 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4898
4899 /* Validate reserved bits in the command. */
4900 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4901 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4902 {
4903#ifdef IOMMU_WITH_DTE_CACHE
4904 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4905#endif
4906 return VINF_SUCCESS;
4907 }
4908 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4909 return VERR_IOMMU_CMD_INVALID_FORMAT;
4910 }
4911
4912 case IOMMU_CMD_INV_IOMMU_PAGES:
4913 {
4914 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4915 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4916 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4917
4918 /* Validate reserved bits in the command. */
4919 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4920 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4921 {
4922#ifdef IOMMU_WITH_IOTLBE_CACHE
4923 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4924 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
4925 uint8_t cShift;
4926 if (!pCmdInvPages->n.u1Size)
4927 cShift = X86_PAGE_4K_SHIFT;
4928 else
4929 {
4930 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4931 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4932 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4933
4934 /*
4935 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4936 * would do the right thing by clearing the entire cache for the specified domain ID.
4937 *
4938 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4939 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4940 * A debug-time assert is in place here to let us know if any software tries this.
4941 *
4942 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4943 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4944 */
4945 Assert(uIova != UINT64_C(0xfffffffffffff000));
4946 }
4947
4948 /*
4949 * Validate invalidation size.
4950 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4951 */
4952 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4953 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4954 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4955 {
4956 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4957 size_t const cbIova = RT_BIT_64(cShift);
4958 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
4959 }
4960 else
4961 {
4962 /*
4963 * The guest provided size is invalid or exceeds the largest, meaningful page size.
4964 * In such situations we must remove all ranges for the specified domain ID.
4965 */
4966 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
4967 }
4968#endif
4969 return VINF_SUCCESS;
4970 }
4971 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4972 return VERR_IOMMU_CMD_INVALID_FORMAT;
4973 }
4974
4975 case IOMMU_CMD_INV_IOTLB_PAGES:
4976 {
4977 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
4978
4979 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4980 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4981 {
4982 /** @todo IOMMU: Implement remote IOTLB invalidation. */
4983 return VERR_NOT_IMPLEMENTED;
4984 }
4985 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4986 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4987 }
4988
4989 case IOMMU_CMD_INV_INTR_TABLE:
4990 {
4991 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
4992
4993 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
4994 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
4995
4996 /* Validate reserved bits in the command. */
4997 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
4998 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
4999 {
5000#ifdef IOMMU_WITH_IRTE_CACHE
5001 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
5002#endif
5003 return VINF_SUCCESS;
5004 }
5005 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5006 return VERR_IOMMU_CMD_INVALID_FORMAT;
5007 }
5008
5009 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
5010 {
5011 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
5012 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
5013 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
5014 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5015 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5016 }
5017
5018 case IOMMU_CMD_COMPLETE_PPR_REQ:
5019 {
5020 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
5021
5022 /* We don't support PPR requests yet. */
5023 Assert(!pThis->ExtFeat.n.u1PprSup);
5024 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5025 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5026 }
5027
5028 case IOMMU_CMD_INV_IOMMU_ALL:
5029 {
5030 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
5031 if (pThis->ExtFeat.n.u1InvAllSup)
5032 {
5033 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
5034 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
5035
5036 /* Validate reserved bits in the command. */
5037 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
5038 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
5039 {
5040#ifdef IOMMU_WITH_DTE_CACHE
5041 iommuAmdDteCacheRemoveAll(pDevIns);
5042#endif
5043#ifdef IOMMU_WITH_IOTLBE_CACHE
5044 iommuAmdIotlbRemoveAll(pDevIns);
5045#endif
5046 return VINF_SUCCESS;
5047 }
5048 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5049 return VERR_IOMMU_CMD_INVALID_FORMAT;
5050 }
5051 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5052 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5053 }
5054 }
5055
5056 STAM_COUNTER_DEC(&pThis->StatCmd);
5057 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5058 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5059 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5060}
5061
5062
5063/**
5064 * The IOMMU command thread.
5065 *
5066 * @returns VBox status code.
5067 * @param pDevIns The IOMMU device instance.
5068 * @param pThread The command thread.
5069 */
5070static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5071{
5072 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5073 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5074
5075 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5076 return VINF_SUCCESS;
5077
5078 /*
5079 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5080 * This avoid trashing the heap as well as not wasting time allocating
5081 * and freeing buffers while processing commands.
5082 */
5083 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5084 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5085 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5086
5087 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5088 {
5089 /*
5090 * Sleep perpetually until we are woken up to process commands.
5091 */
5092 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5093 if (!fSignaled)
5094 {
5095 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5096 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5097 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5098 break;
5099 Log4Func(("Woken up with rc=%Rrc\n", rc));
5100 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5101 }
5102
5103 /*
5104 * Fetch and process IOMMU commands.
5105 */
5106 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5107 * temporary host buffer before processing them as a batch. If we want to
5108 * save on host memory a bit, we could (once PGM has the necessary APIs)
5109 * lock the page mappings page mappings and access them directly. */
5110 IOMMU_LOCK(pDevIns, pThisR3, VERR_IGNORED);
5111
5112 if (pThis->Status.n.u1CmdBufRunning)
5113 {
5114 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5115 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5116 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5117 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5118
5119 /* Validate. */
5120 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5121 Assert(offHead < cbCmdBuf);
5122 Assert(cbCmdBuf <= cbMaxCmdBuf);
5123
5124 if (offHead != offTail)
5125 {
5126 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5127 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5128
5129 IOMMU_UNLOCK(pDevIns, pThisR3);
5130 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5131 IOMMU_LOCK(pDevIns, pThisR3, VERR_IGNORED);
5132
5133 if (RT_SUCCESS(rc))
5134 {
5135 /* Indicate to software we've fetched all commands from the buffer. */
5136 pThis->CmdBufHeadPtr.n.off = offTail;
5137
5138 /* Allow IOMMU to do other work while we process commands. */
5139 IOMMU_UNLOCK(pDevIns, pThisR3);
5140
5141 /* Process the fetched commands. */
5142 EVT_GENERIC_T EvtError;
5143 do
5144 {
5145 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5146 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5147 if (RT_FAILURE(rc))
5148 {
5149 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5150 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5151 {
5152 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5153 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5154 }
5155 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5156 {
5157 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5158 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5159 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5160 }
5161 break;
5162 }
5163
5164 /* Move to the next command in the circular buffer. */
5165 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5166 } while (offHead != offTail);
5167 }
5168 else
5169 {
5170 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5171 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5172 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5173 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5174
5175 IOMMU_UNLOCK(pDevIns, pThisR3);
5176 }
5177 }
5178 else
5179 IOMMU_UNLOCK(pDevIns, pThisR3);
5180 }
5181 else
5182 IOMMU_UNLOCK(pDevIns, pThisR3);
5183 }
5184
5185 RTMemFree(pvCmds);
5186 LogFlowFunc(("Command thread terminating\n"));
5187 return VINF_SUCCESS;
5188}
5189
5190
5191/**
5192 * Wakes up the command thread so it can respond to a state change.
5193 *
5194 * @returns VBox status code.
5195 * @param pDevIns The IOMMU device instance.
5196 * @param pThread The command thread.
5197 */
5198static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5199{
5200 RT_NOREF(pThread);
5201 LogFlowFunc(("\n"));
5202 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5203 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5204}
5205
5206
5207/**
5208 * @callback_method_impl{FNPCICONFIGREAD}
5209 */
5210static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5211 unsigned cb, uint32_t *pu32Value)
5212{
5213 /** @todo IOMMU: PCI config read stat counter. */
5214 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5215 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5216 return rcStrict;
5217}
5218
5219
5220/**
5221 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5222 * register write).
5223 *
5224 * @returns VBox status code.
5225 * @param pDevIns The IOMMU instance data.
5226 *
5227 * @remarks Call this function only when the IOMMU BAR is enabled.
5228 */
5229static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5230{
5231 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5232 Assert(pThis->IommuBar.n.u1Enable);
5233 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5234 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5235 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5236 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5237
5238 /* If the MMIO region is already mapped at the specified address, we're done. */
5239 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5240 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5241 return VINF_SUCCESS;
5242
5243 /* Unmap the previous MMIO region (which is at a different address). */
5244 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5245 {
5246 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5247 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5248 if (RT_FAILURE(rc))
5249 {
5250 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5251 return rc;
5252 }
5253 }
5254
5255 /* Map the newly specified MMIO region. */
5256 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5257 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5258 if (RT_FAILURE(rc))
5259 {
5260 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5261 return rc;
5262 }
5263
5264 return VINF_SUCCESS;
5265}
5266
5267
5268/**
5269 * @callback_method_impl{FNPCICONFIGWRITE}
5270 */
5271static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5272 unsigned cb, uint32_t u32Value)
5273{
5274 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5275
5276 /*
5277 * Discard writes to read-only registers that are specific to the IOMMU.
5278 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5279 * See PCI spec. 6.1. "Configuration Space Organization".
5280 */
5281 switch (uAddress)
5282 {
5283 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5284 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5285 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5286 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5287 {
5288 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5289 return VINF_SUCCESS;
5290 }
5291 }
5292
5293 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5294 IOMMU_LOCK(pDevIns, pThisR3, VERR_IGNORED);
5295
5296 VBOXSTRICTRC rcStrict;
5297 switch (uAddress)
5298 {
5299 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5300 {
5301 if (!pThis->IommuBar.n.u1Enable)
5302 {
5303 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5304 if (pThis->IommuBar.n.u1Enable)
5305 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5306 else
5307 rcStrict = VINF_SUCCESS;
5308 }
5309 else
5310 {
5311 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5312 rcStrict = VINF_SUCCESS;
5313 }
5314 break;
5315 }
5316
5317 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5318 {
5319 if (!pThis->IommuBar.n.u1Enable)
5320 {
5321 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5322 pThis->IommuBar.au32[1] = u32Value;
5323 }
5324 else
5325 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5326 rcStrict = VINF_SUCCESS;
5327 break;
5328 }
5329
5330 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5331 {
5332 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5333 RT_FALL_THRU();
5334 }
5335 default:
5336 {
5337 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5338 break;
5339 }
5340 }
5341
5342 IOMMU_UNLOCK(pDevIns, pThisR3);
5343
5344 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5345 return rcStrict;
5346}
5347
5348
5349/**
5350 * @callback_method_impl{FNDBGFHANDLERDEV}
5351 */
5352static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5353{
5354 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5355 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5356 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5357
5358 bool fVerbose;
5359 if ( pszArgs
5360 && !strncmp(pszArgs, RT_STR_TUPLE("verbose")))
5361 fVerbose = true;
5362 else
5363 fVerbose = false;
5364
5365 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5366 /* Device Table Base Addresses (all segments). */
5367 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5368 {
5369 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5370 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5371 if (fVerbose)
5372 {
5373 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5374 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5375 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5376 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5377 }
5378 }
5379 /* Command Buffer Base Address Register. */
5380 {
5381 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5382 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5383 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5384 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5385 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5386 if (fVerbose)
5387 {
5388 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5389 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5390 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5391 cEntries, cbBuffer);
5392 }
5393 }
5394 /* Event Log Base Address Register. */
5395 {
5396 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5397 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5398 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5399 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5400 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5401 if (fVerbose)
5402 {
5403 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5404 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5405 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5406 cEntries, cbBuffer);
5407 }
5408 }
5409 /* IOMMU Control Register. */
5410 {
5411 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5412 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5413 if (fVerbose)
5414 {
5415 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5416 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5417 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5418 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5419 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5420 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5421 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5422 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5423 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5424 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5425 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5426 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5427 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5428 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5429 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5430 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5431 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5432 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5433 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5434 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5435 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5436 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5437 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5438 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5439 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5440 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5441 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5442 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5443 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5444 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5445 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5446 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5447 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5448 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5449 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5450 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5451 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5452 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5453 }
5454 }
5455 /* Exclusion Base Address Register. */
5456 {
5457 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5458 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5459 if (fVerbose)
5460 {
5461 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5462 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5463 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5464 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5465 }
5466 }
5467 /* Exclusion Range Limit Register. */
5468 {
5469 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5470 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5471 if (fVerbose)
5472 {
5473 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5474 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5475 }
5476 }
5477 /* Extended Feature Register. */
5478 {
5479 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5480 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5481 if (fVerbose)
5482 {
5483 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5484 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5485 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5486 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5487 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5488 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5489 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5490 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5491 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5492 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5493 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5494 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5495 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5496 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5497 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5498 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5499 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5500 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5501 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5502 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5503 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5504 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5505 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5506 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5507 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5508 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5509 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5510 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5511 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5512 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5513 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5514 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5515 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5516 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5517 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5518 }
5519 }
5520 /* PPR Log Base Address Register. */
5521 {
5522 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5523 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5524 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5525 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5526 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5527 if (fVerbose)
5528 {
5529 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5530 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5531 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5532 cEntries, cbBuffer);
5533 }
5534 }
5535 /* Hardware Event (Hi) Register. */
5536 {
5537 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5538 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5539 if (fVerbose)
5540 {
5541 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5542 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5543 }
5544 }
5545 /* Hardware Event (Lo) Register. */
5546 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5547 /* Hardware Event Status. */
5548 {
5549 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5550 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5551 if (fVerbose)
5552 {
5553 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5554 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5555 }
5556 }
5557 /* Guest Virtual-APIC Log Base Address Register. */
5558 {
5559 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5560 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5561 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5562 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5563 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5564 if (fVerbose)
5565 {
5566 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5567 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5568 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5569 cEntries, cbBuffer);
5570 }
5571 }
5572 /* Guest Virtual-APIC Log Tail Address Register. */
5573 {
5574 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5575 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5576 if (fVerbose)
5577 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5578 }
5579 /* PPR Log B Base Address Register. */
5580 {
5581 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5582 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5583 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5584 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5585 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5586 if (fVerbose)
5587 {
5588 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5589 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5590 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5591 cEntries, cbBuffer);
5592 }
5593 }
5594 /* Event Log B Base Address Register. */
5595 {
5596 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5597 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5598 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5599 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5600 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5601 if (fVerbose)
5602 {
5603 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5604 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5605 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5606 cEntries, cbBuffer);
5607 }
5608 }
5609 /* Device-Specific Feature Extension Register. */
5610 {
5611 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5612 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5613 if (fVerbose)
5614 {
5615 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5616 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5617 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5618 }
5619 }
5620 /* Device-Specific Control Extension Register. */
5621 {
5622 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5623 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5624 if (fVerbose)
5625 {
5626 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5627 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5628 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5629 }
5630 }
5631 /* Device-Specific Status Extension Register. */
5632 {
5633 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5634 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5635 if (fVerbose)
5636 {
5637 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5638 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5639 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5640 }
5641 }
5642 /* Miscellaneous Information Register (Lo and Hi). */
5643 {
5644 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5645 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5646 if (fVerbose)
5647 {
5648 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5649 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5650 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5651 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5652 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5653 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5654 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5655 }
5656 }
5657 /* MSI Capability Header. */
5658 {
5659 MSI_CAP_HDR_T MsiCapHdr;
5660 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5661 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5662 if (fVerbose)
5663 {
5664 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5665 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5666 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5667 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5668 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5669 }
5670 }
5671 /* MSI Address Register (Lo and Hi). */
5672 {
5673 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5674 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5675 MSIADDR MsiAddr;
5676 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5677 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5678 if (fVerbose)
5679 {
5680 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5681 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5682 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5683 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5684 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5685 }
5686 }
5687 /* MSI Data. */
5688 {
5689 MSIDATA MsiData;
5690 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5691 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5692 if (fVerbose)
5693 {
5694 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5695 MsiData.n.u8Vector);
5696 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5697 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5698 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5699 "level" : "edge");
5700 }
5701 }
5702 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5703 {
5704 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5705 MsiMapCapHdr.u32 = 0;
5706 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5707 if (fVerbose)
5708 {
5709 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5710 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5711 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5712 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5713 }
5714 }
5715 /* Performance Optimization Control Register. */
5716 {
5717 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5718 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5719 if (fVerbose)
5720 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5721 }
5722 /* XT (x2APIC) General Interrupt Control Register. */
5723 {
5724 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5725 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5726 if (fVerbose)
5727 {
5728 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5729 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5730 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5731 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5732 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5733 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5734 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5735 }
5736 }
5737 /* XT (x2APIC) PPR Interrupt Control Register. */
5738 {
5739 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5740 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5741 if (fVerbose)
5742 {
5743 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5744 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5745 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5746 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5747 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5748 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5749 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5750 }
5751 }
5752 /* XT (X2APIC) GA Log Interrupt Control Register. */
5753 {
5754 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5755 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5756 if (fVerbose)
5757 {
5758 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5759 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5760 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5761 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5762 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5763 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5764 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5765 }
5766 }
5767 /* MARC Registers. */
5768 {
5769 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5770 {
5771 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5772 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5773 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5774
5775 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5776 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5777 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5778 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5779
5780 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5781 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5782 }
5783 }
5784 /* Reserved Register. */
5785 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5786 /* Command Buffer Head Pointer Register. */
5787 {
5788 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5789 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5790 CmdBufHeadPtr.n.off);
5791 }
5792 /* Command Buffer Tail Pointer Register. */
5793 {
5794 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5795 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5796 CmdBufTailPtr.n.off);
5797 }
5798 /* Event Log Head Pointer Register. */
5799 {
5800 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5801 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5802 EvtLogHeadPtr.n.off);
5803 }
5804 /* Event Log Tail Pointer Register. */
5805 {
5806 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5807 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5808 EvtLogTailPtr.n.off);
5809 }
5810 /* Status Register. */
5811 {
5812 IOMMU_STATUS_T const Status = pThis->Status;
5813 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5814 if (fVerbose)
5815 {
5816 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5817 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5818 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5819 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5820 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5821 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5822 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5823 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5824 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5825 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5826 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5827 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5828 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5829 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5830 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5831 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5832 }
5833 }
5834 /* PPR Log Head Pointer. */
5835 {
5836 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5837 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5838 PprLogHeadPtr.n.off);
5839 }
5840 /* PPR Log Tail Pointer. */
5841 {
5842 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5843 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5844 PprLogTailPtr.n.off);
5845 }
5846 /* Guest Virtual-APIC Log Head Pointer. */
5847 {
5848 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5849 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5850 GALogHeadPtr.n.u12GALogPtr);
5851 }
5852 /* Guest Virtual-APIC Log Tail Pointer. */
5853 {
5854 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5855 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5856 GALogTailPtr.n.u12GALogPtr);
5857 }
5858 /* PPR Log B Head Pointer. */
5859 {
5860 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5861 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5862 PprLogBHeadPtr.n.off);
5863 }
5864 /* PPR Log B Tail Pointer. */
5865 {
5866 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5867 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5868 PprLogBTailPtr.n.off);
5869 }
5870 /* Event Log B Head Pointer. */
5871 {
5872 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5873 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5874 EvtLogBHeadPtr.n.off);
5875 }
5876 /* Event Log B Tail Pointer. */
5877 {
5878 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5879 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5880 EvtLogBTailPtr.n.off);
5881 }
5882 /* PPR Log Auto Response Register. */
5883 {
5884 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5885 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5886 if (fVerbose)
5887 {
5888 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5889 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5890 }
5891 }
5892 /* PPR Log Overflow Early Warning Indicator Register. */
5893 {
5894 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5895 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5896 if (fVerbose)
5897 {
5898 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5899 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5900 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5901 }
5902 }
5903 /* PPR Log Overflow Early Warning Indicator Register. */
5904 {
5905 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5906 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5907 if (fVerbose)
5908 {
5909 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5910 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5911 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5912 }
5913 }
5914}
5915
5916
5917/**
5918 * Dumps the DTE via the info callback helper.
5919 *
5920 * @param pHlp The info helper.
5921 * @param pDte The device table entry.
5922 * @param pszPrefix The string prefix.
5923 */
5924static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5925{
5926 AssertReturnVoid(pHlp);
5927 AssertReturnVoid(pDte);
5928 AssertReturnVoid(pszPrefix);
5929
5930 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5931 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5932 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5933 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5934 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5935 pDte->n.u40PageTableRootPtrLo << 12);
5936 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5937 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5938 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5939 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5940 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5941 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5942 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5943 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5944 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5945 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5946 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5947 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5948 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5949 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5950 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5951 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5952 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5953 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5954 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5955 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5956 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5957 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5958 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5959 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5960 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5961 {
5962 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
5963 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
5964 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
5965 cbIntrTable);
5966 }
5967 else
5968 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
5969 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
5970 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
5971 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
5972 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
5973 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
5974 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
5975 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
5976 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
5977 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
5978 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
5979 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
5980 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
5981 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
5982 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
5983 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
5984 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
5985 pHlp->pfnPrintf(pHlp, "\n");
5986}
5987
5988
5989/**
5990 * @callback_method_impl{FNDBGFHANDLERDEV}
5991 */
5992static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5993{
5994 if (pszArgs)
5995 {
5996 uint16_t idDevice = 0;
5997 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
5998 if (RT_SUCCESS(rc))
5999 {
6000 DTE_T Dte;
6001 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
6002 if (RT_SUCCESS(rc))
6003 {
6004 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
6005 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
6006 return;
6007 }
6008 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
6009 }
6010 else
6011 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
6012 }
6013 else
6014 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
6015}
6016
6017
6018# ifdef IOMMU_WITH_DTE_CACHE
6019/**
6020 * @callback_method_impl{FNDBGFHANDLERDEV}
6021 */
6022static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6023{
6024 RT_NOREF(pszArgs);
6025 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6026 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6027
6028 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
6029 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
6030 for (uint16_t i = 0; i < cDteCache; i++)
6031 {
6032 uint16_t const idDevice = pThis->aDeviceIds[i];
6033 if (idDevice)
6034 {
6035 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
6036 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6037 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6038 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6039
6040 PCDTECACHE pDteCache = &pThis->aDteCache[i];
6041 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
6042 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
6043 pHlp->pfnPrintf(pHlp, "\n");
6044 }
6045 }
6046 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6047}
6048# endif /* IOMMU_WITH_DTE_CACHE */
6049
6050
6051# ifdef IOMMU_WITH_IOTLBE_CACHE
6052/**
6053 * @callback_method_impl{FNDBGFHANDLERDEV}
6054 */
6055static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6056{
6057 if (pszArgs)
6058 {
6059 uint16_t idDomain = 0;
6060 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6061 if (RT_SUCCESS(rc))
6062 {
6063 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6064 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6065 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6066 IOTLBEINFOARG Args;
6067 Args.pIommuR3 = pThisR3;
6068 Args.pHlp = pHlp;
6069 Args.idDomain = idDomain;
6070
6071 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6072 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6073 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6074 }
6075 else
6076 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6077 }
6078 else
6079 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6080}
6081# endif /* IOMMU_WITH_IOTLBE_CACHE */
6082
6083
6084# ifdef IOMMU_WITH_IRTE_CACHE
6085/**
6086 * Gets the interrupt type name for an interrupt type in the IRTE.
6087 *
6088 * @returns The interrupt type name.
6089 * @param uIntrType The interrupt type (as specified in the IRTE).
6090 */
6091static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6092{
6093 switch (uIntrType)
6094 {
6095 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6096 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6097 default: return "<Reserved>";
6098 }
6099}
6100
6101
6102/**
6103 * @callback_method_impl{FNDBGFHANDLERDEV}
6104 */
6105static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6106{
6107 RT_NOREF(pszArgs);
6108
6109 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6110 IOMMU_LOCK_CACHE_NORET(pDevIns, pThis);
6111
6112 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6113 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6114 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6115 {
6116 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6117 uint32_t const uKey = pIrteCache->uKey;
6118 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6119 {
6120 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6121 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6122 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6123 idxIrte, offIrte, idDevice,
6124 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6125 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6126 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6127
6128 PCIRTE_T pIrte = &pIrteCache->Irte;
6129 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6130 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6131 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6132 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6133 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6134 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6135 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6136 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6137 pHlp->pfnPrintf(pHlp, "\n");
6138 }
6139 }
6140 IOMMU_UNLOCK_CACHE(pDevIns, pThis);
6141}
6142# endif /* IOMMU_WITH_IRTE_CACHE */
6143
6144
6145/**
6146 * @callback_method_impl{FNDBGFHANDLERDEV}
6147 */
6148static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6149{
6150 RT_NOREF(pszArgs);
6151
6152 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6153 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6154 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6155 NOREF(pPciDev);
6156
6157 uint8_t cSegments = 0;
6158 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6159 {
6160 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6161 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6162 if (GCPhysDevTab)
6163 ++cSegments;
6164 }
6165
6166 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6167 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6168 if (!cSegments)
6169 return;
6170
6171 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6172 {
6173 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6174 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6175 if (GCPhysDevTab)
6176 {
6177 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6178 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6179
6180 void *pvDevTab = RTMemAllocZ(cbDevTab);
6181 if (RT_LIKELY(pvDevTab))
6182 {
6183 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6184 if (RT_SUCCESS(rc))
6185 {
6186 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6187 {
6188 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6189 if ( pDte->n.u1Valid
6190 && pDte->n.u1TranslationValid
6191 && pDte->n.u3Mode != 0)
6192 {
6193 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6194 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6195 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6196 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6197 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6198 pHlp->pfnPrintf(pHlp, "\n");
6199 }
6200 }
6201 pHlp->pfnPrintf(pHlp, "\n");
6202 }
6203 else
6204 {
6205 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6206 cbDevTab, rc);
6207 }
6208
6209 RTMemFree(pvDevTab);
6210 }
6211 else
6212 {
6213 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6214 return;
6215 }
6216 }
6217 }
6218}
6219
6220
6221/**
6222 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6223 */
6224static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6225{
6226 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6227 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6228 LogFlowFunc(("\n"));
6229
6230 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6231 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6232 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6233 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6234 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6235 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6236 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6237
6238 /* Next, save all registers that can be modified by the guest. */
6239 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6240
6241 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6242 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6243 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6244 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6245
6246 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6247 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6248 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6249 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6250 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6251 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6252#if 0
6253 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6254#endif
6255
6256 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6257 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6258 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6259 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6260
6261 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6262 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6263
6264 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6265 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6266
6267#if 0
6268 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6269 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6270 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6271
6272 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6273#endif
6274 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6275
6276 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6277 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6278 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6279
6280 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6281 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6282 for (size_t i = 0; i < cMarcApers; i++)
6283 {
6284 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6285 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6286 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6287 }
6288
6289#if 0
6290 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6291#endif
6292
6293 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6294 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6295 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6296 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6297
6298 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6299
6300 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6301 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6302
6303 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6304 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6305
6306 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6307 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6308
6309 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6310 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6311
6312 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6313 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6314 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6315
6316 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6317}
6318
6319
6320/**
6321 * @callback_method_impl{FNSSMDEVLOADEXEC}
6322 */
6323static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6324{
6325 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6326 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6327 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6328 LogFlowFunc(("\n"));
6329
6330 /* Validate. */
6331 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6332 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6333 {
6334 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6335 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6336 }
6337
6338 /* Load ExtFeat and other read-only registers first. */
6339 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6340 AssertRCReturn(rc, rc);
6341 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6342 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6343 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6344 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6345 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6346 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6347 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6348
6349 /* IOMMU base address register. */
6350 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6351 AssertRCReturn(rc, rc);
6352 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6353
6354 /* Device table base address registers. */
6355 uint8_t cDevTabBaseAddrs;
6356 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6357 AssertRCReturn(rc, rc);
6358 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6359 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6360 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6361 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6362 {
6363 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6364 AssertRCReturn(rc, rc);
6365 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6366 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6367 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6368 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6369 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6370 }
6371
6372 /* Command buffer base address register. */
6373 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6374 AssertRCReturn(rc, rc);
6375 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6376 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6377 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6378
6379 /* Event log base address register. */
6380 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6381 AssertRCReturn(rc, rc);
6382 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6383 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6384 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6385
6386 /* Control register. */
6387 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6388 AssertRCReturn(rc, rc);
6389 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6390 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6391 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6392
6393 /* Exclusion range base address register. */
6394 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6395 AssertRCReturn(rc, rc);
6396 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6397
6398 /* Exclusion range limit register. */
6399 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6400 AssertRCReturn(rc, rc);
6401 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6402 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6403
6404#if 0
6405 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6406#endif
6407
6408 /* PPR log base address register. */
6409 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6410 AssertRCReturn(rc, rc);
6411 Assert(!pThis->ExtFeat.n.u1PprSup);
6412
6413 /* Hardware event (Hi) register. */
6414 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6415 AssertRCReturn(rc, rc);
6416
6417 /* Hardware event (Lo) register. */
6418 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6419 AssertRCReturn(rc, rc);
6420
6421 /* Hardware event status register. */
6422 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6423 AssertRCReturn(rc, rc);
6424 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6425
6426 /* Guest Virtual-APIC log base address register. */
6427 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6428 AssertRCReturn(rc, rc);
6429 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6430
6431 /* Guest Virtual-APIC log tail address register. */
6432 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6433 AssertRCReturn(rc, rc);
6434 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6435
6436 /* PPR log-B base address register. */
6437 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6438 AssertRCReturn(rc, rc);
6439 Assert(!pThis->ExtFeat.n.u1PprSup);
6440
6441 /* Event log-B base address register. */
6442 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6443 AssertRCReturn(rc, rc);
6444 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6445
6446#if 0
6447 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6448 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6449 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6450
6451 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6452#endif
6453
6454 /* Performance optimization control register. */
6455 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6456 AssertRCReturn(rc, rc);
6457 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6458
6459 /* x2APIC registers. */
6460 {
6461 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6462
6463 /* x2APIC general interrupt control register. */
6464 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6465 AssertRCReturn(rc, rc);
6466
6467 /* x2APIC PPR interrupt control register. */
6468 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6469 AssertRCReturn(rc, rc);
6470
6471 /* x2APIC GA log interrupt control register. */
6472 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6473 AssertRCReturn(rc, rc);
6474 }
6475
6476 /* MARC (Memory Access and Routing) registers. */
6477 {
6478 uint8_t cMarcApers;
6479 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6480 AssertRCReturn(rc, rc);
6481 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6482 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6483 for (uint8_t i = 0; i < cMarcApers; i++)
6484 {
6485 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6486 AssertRCReturn(rc, rc);
6487
6488 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6489 AssertRCReturn(rc, rc);
6490
6491 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6492 AssertRCReturn(rc, rc);
6493 }
6494 Assert(!pThis->ExtFeat.n.u2MarcSup);
6495 }
6496
6497#if 0
6498 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6499#endif
6500
6501 /* Command buffer head pointer register. */
6502 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6503 AssertRCReturn(rc, rc);
6504 {
6505 /*
6506 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6507 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6508 * we shouldn't see such values in the saved state.
6509 */
6510 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6511 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6512 Assert(cbBuf <= _512K);
6513 AssertLogRelMsgReturn(offBuf < cbBuf,
6514 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6515 }
6516
6517 /* Command buffer tail pointer register. */
6518 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6519 AssertRCReturn(rc, rc);
6520 {
6521 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6522 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6523 Assert(cbBuf <= _512K);
6524 AssertLogRelMsgReturn(offBuf < cbBuf,
6525 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6526 }
6527
6528 /* Event log head pointer register. */
6529 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6530 AssertRCReturn(rc, rc);
6531 {
6532 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6533 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6534 Assert(cbBuf <= _512K);
6535 AssertLogRelMsgReturn(offBuf < cbBuf,
6536 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6537 }
6538
6539 /* Event log tail pointer register. */
6540 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6541 AssertRCReturn(rc, rc);
6542 {
6543 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6544 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6545 Assert(cbBuf <= _512K);
6546 AssertLogRelMsgReturn(offBuf < cbBuf,
6547 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6548 }
6549
6550 /* Status register. */
6551 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6552 AssertRCReturn(rc, rc);
6553 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6554
6555 /* PPR log head pointer register. */
6556 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6557 AssertRCReturn(rc, rc);
6558 Assert(!pThis->ExtFeat.n.u1PprSup);
6559
6560 /* PPR log tail pointer register. */
6561 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6562 AssertRCReturn(rc, rc);
6563 Assert(!pThis->ExtFeat.n.u1PprSup);
6564
6565 /* Guest Virtual-APIC log head pointer register. */
6566 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6567 AssertRCReturn(rc, rc);
6568 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6569
6570 /* Guest Virtual-APIC log tail pointer register. */
6571 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6572 AssertRCReturn(rc, rc);
6573 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6574
6575 /* PPR log-B head pointer register. */
6576 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6577 AssertRCReturn(rc, rc);
6578 Assert(!pThis->ExtFeat.n.u1PprSup);
6579
6580 /* PPR log-B head pointer register. */
6581 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6582 AssertRCReturn(rc, rc);
6583 Assert(!pThis->ExtFeat.n.u1PprSup);
6584
6585 /* Event log-B head pointer register. */
6586 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6587 AssertRCReturn(rc, rc);
6588 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6589
6590 /* Event log-B tail pointer register. */
6591 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6592 AssertRCReturn(rc, rc);
6593 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6594
6595 /* PPR log auto response register. */
6596 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6597 AssertRCReturn(rc, rc);
6598 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6599
6600 /* PPR log overflow early indicator register. */
6601 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6602 AssertRCReturn(rc, rc);
6603 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6604
6605 /* PPR log-B overflow early indicator register. */
6606 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6607 AssertRCReturn(rc, rc);
6608 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6609
6610 /* End marker. */
6611 {
6612 uint32_t uEndMarker;
6613 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6614 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6615 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6616 rcErr);
6617 }
6618
6619 return rc;
6620}
6621
6622
6623/**
6624 * @callback_method_impl{FNSSMDEVLOADDONE}
6625 */
6626static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6627{
6628 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6629 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6630 RT_NOREF(pSSM);
6631 LogFlowFunc(("\n"));
6632
6633 /* Sanity. */
6634 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6635 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6636
6637 int rc;
6638 IOMMU_LOCK(pDevIns, pThisR3, VERR_IGNORED);
6639
6640 /* Map MMIO regions if the IOMMU BAR is enabled. */
6641 if (pThis->IommuBar.n.u1Enable)
6642 rc = iommuAmdR3MmioSetup(pDevIns);
6643 else
6644 rc = VINF_SUCCESS;
6645
6646 /* Wake up the command thread if commands need processing. */
6647 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6648
6649 IOMMU_UNLOCK(pDevIns, pThisR3);
6650
6651 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6652 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6653 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6654 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6655 pThis->ExtFeat.u64));
6656 return rc;
6657}
6658
6659
6660/**
6661 * @interface_method_impl{PDMDEVREG,pfnReset}
6662 */
6663static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6664{
6665 /*
6666 * Resets read-write portion of the IOMMU state.
6667 *
6668 * NOTE! State not initialized here is expected to be initialized during
6669 * device construction and remain read-only through the lifetime of the VM.
6670 */
6671 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6672 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6673 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6674 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6675 LogFlowFunc(("\n"));
6676
6677 IOMMU_LOCK_NORET(pDevIns, pThisR3);
6678
6679 RT_ZERO(pThis->aDevTabBaseAddrs);
6680
6681 pThis->CmdBufBaseAddr.u64 = 0;
6682 pThis->CmdBufBaseAddr.n.u4Len = 8;
6683
6684 pThis->EvtLogBaseAddr.u64 = 0;
6685 pThis->EvtLogBaseAddr.n.u4Len = 8;
6686
6687 pThis->Ctrl.u64 = 0;
6688 pThis->Ctrl.n.u1Coherent = 1;
6689 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6690
6691 pThis->ExclRangeBaseAddr.u64 = 0;
6692 pThis->ExclRangeLimit.u64 = 0;
6693
6694 pThis->PprLogBaseAddr.u64 = 0;
6695 pThis->PprLogBaseAddr.n.u4Len = 8;
6696
6697 pThis->HwEvtHi.u64 = 0;
6698 pThis->HwEvtLo = 0;
6699 pThis->HwEvtStatus.u64 = 0;
6700
6701 pThis->GALogBaseAddr.u64 = 0;
6702 pThis->GALogBaseAddr.n.u4Len = 8;
6703 pThis->GALogTailAddr.u64 = 0;
6704
6705 pThis->PprLogBBaseAddr.u64 = 0;
6706 pThis->PprLogBBaseAddr.n.u4Len = 8;
6707
6708 pThis->EvtLogBBaseAddr.u64 = 0;
6709 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6710
6711 pThis->PerfOptCtrl.u32 = 0;
6712
6713 pThis->XtGenIntrCtrl.u64 = 0;
6714 pThis->XtPprIntrCtrl.u64 = 0;
6715 pThis->XtGALogIntrCtrl.u64 = 0;
6716
6717 RT_ZERO(pThis->aMarcApers);
6718
6719 pThis->CmdBufHeadPtr.u64 = 0;
6720 pThis->CmdBufTailPtr.u64 = 0;
6721 pThis->EvtLogHeadPtr.u64 = 0;
6722 pThis->EvtLogTailPtr.u64 = 0;
6723
6724 pThis->Status.u64 = 0;
6725
6726 pThis->PprLogHeadPtr.u64 = 0;
6727 pThis->PprLogTailPtr.u64 = 0;
6728
6729 pThis->GALogHeadPtr.u64 = 0;
6730 pThis->GALogTailPtr.u64 = 0;
6731
6732 pThis->PprLogBHeadPtr.u64 = 0;
6733 pThis->PprLogBTailPtr.u64 = 0;
6734
6735 pThis->EvtLogBHeadPtr.u64 = 0;
6736 pThis->EvtLogBTailPtr.u64 = 0;
6737
6738 pThis->PprLogAutoResp.u64 = 0;
6739 pThis->PprLogOverflowEarly.u64 = 0;
6740 pThis->PprLogBOverflowEarly.u64 = 0;
6741
6742 pThis->IommuBar.u64 = 0;
6743 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6744 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6745
6746 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6747
6748 IOMMU_UNLOCK(pDevIns, pThisR3);
6749
6750#ifdef IOMMU_WITH_DTE_CACHE
6751 iommuAmdDteCacheRemoveAll(pDevIns);
6752#endif
6753#ifdef IOMMU_WITH_IOTLBE_CACHE
6754 iommuAmdIotlbRemoveAll(pDevIns);
6755#endif
6756#ifdef IOMMU_WITH_IRTE_CACHE
6757 iommuAmdIrteCacheRemoveAll(pDevIns);
6758#endif
6759}
6760
6761
6762/**
6763 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6764 */
6765static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6766{
6767 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6768 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6769 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6770 LogFlowFunc(("\n"));
6771
6772 IOMMU_LOCK_NORET(pDevIns, pThisR3);
6773
6774 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6775 {
6776 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6777 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6778 }
6779
6780#ifdef IOMMU_WITH_IOTLBE_CACHE
6781 if (pThisR3->paIotlbes)
6782 {
6783 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6784 pThisR3->paIotlbes = NULL;
6785 pThisR3->idxUnusedIotlbe = 0;
6786 }
6787#endif
6788
6789 IOMMU_UNLOCK(pDevIns, pThisR3);
6790 return VINF_SUCCESS;
6791}
6792
6793
6794/**
6795 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6796 */
6797static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6798{
6799 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6800 RT_NOREF(pCfg);
6801
6802 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6803 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6804 pThis->u32Magic = IOMMU_MAGIC;
6805 pThisR3->pDevInsR3 = pDevIns;
6806
6807 LogFlowFunc(("iInstance=%d\n", iInstance));
6808
6809 /*
6810 * Register the IOMMU with PDM.
6811 */
6812 PDMIOMMUREGR3 IommuReg;
6813 RT_ZERO(IommuReg);
6814 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6815 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6816 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6817 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6818 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6819 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6820 if (RT_FAILURE(rc))
6821 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6822 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6823 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6824 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6825 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6826 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6827 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6828 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6829 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6830
6831 /*
6832 * We will use PDM's critical section (via helpers) for the IOMMU device.
6833 */
6834 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6835 AssertRCReturn(rc, rc);
6836
6837 /*
6838 * Initialize read-only PCI configuration space.
6839 */
6840 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6841 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6842
6843 /* Header. */
6844 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6845 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6846 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6847 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6848 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6849 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6850 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6851 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6852 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6853 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6854 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6855 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6856 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6857 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6858
6859 /* Capability Header. */
6860 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6861 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6862 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6863 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6864 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6865 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6866 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6867 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6868 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6869 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6870 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6871
6872 /* Base Address Register. */
6873 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6874 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6875
6876 /* IOMMU Range Register. */
6877 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6878
6879 /* Misc. Information Register. */
6880 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6881 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6882 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6883 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6884 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6885 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6886 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6887 uint32_t const uMiscInfoReg1 = 0;
6888 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6889 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6890
6891 /* MSI Capability Header register. */
6892 PDMMSIREG MsiReg;
6893 RT_ZERO(MsiReg);
6894 MsiReg.cMsiVectors = 1;
6895 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6896 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6897 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6898
6899 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6900#if 0
6901 /* MSI Address Lo. */
6902 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6903 /* MSI Address Hi. */
6904 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6905 /* MSI Data. */
6906 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6907#endif
6908
6909#if 0
6910 /** @todo IOMMU: I don't know if we need to support this, enable later if
6911 * required. */
6912 /* MSI Mapping Capability Header register. */
6913 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6914 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6915 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6916 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6917 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6918 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6919 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6920#endif
6921
6922 /*
6923 * Register the PCI function with PDM.
6924 */
6925 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6926 AssertLogRelRCReturn(rc, rc);
6927
6928 /*
6929 * Register MSI support for the PCI device.
6930 * This must be done -after- registering it as a PCI device!
6931 */
6932 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6933 AssertRCReturn(rc, rc);
6934
6935 /*
6936 * Intercept PCI config. space accesses.
6937 */
6938 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6939 AssertLogRelRCReturn(rc, rc);
6940
6941 /*
6942 * Create the MMIO region.
6943 * Mapping of the region is done when software configures it via PCI config space.
6944 */
6945 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6946 NULL /* pvUser */,
6947 IOMMMIO_FLAGS_READ_DWORD_QWORD
6948 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
6949 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
6950 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
6951 "AMD-IOMMU", &pThis->hMmio);
6952 AssertLogRelRCReturn(rc, rc);
6953
6954 /*
6955 * Register saved state handlers.
6956 */
6957 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
6958 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
6959 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
6960 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
6961 AssertLogRelRCReturn(rc, rc);
6962
6963 /*
6964 * Register debugger info items.
6965 */
6966 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6967 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
6968 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
6969#ifdef IOMMU_WITH_IOTLBE_CACHE
6970 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
6971#endif
6972#ifdef IOMMU_WITH_DTE_CACHE
6973 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
6974#endif
6975#ifdef IOMMU_WITH_IRTE_CACHE
6976 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
6977#endif
6978
6979# ifdef VBOX_WITH_STATISTICS
6980 /*
6981 * Statistics.
6982 */
6983 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
6984 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
6985
6986 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
6987 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
6988
6989 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
6990 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
6991
6992 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
6993 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
6994
6995 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
6996 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
6997
6998 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
6999 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
7000
7001 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
7002 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
7003
7004 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
7005 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
7006 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
7007 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
7008 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
7009 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
7010 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
7011 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
7012 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
7013
7014
7015 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
7016 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
7017
7018 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
7019 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
7020
7021 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
7022 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
7023
7024 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7026 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
7027 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
7028 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
7029 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
7030 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
7031
7032 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7033 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7034# endif
7035
7036 /*
7037 * Create the command thread and its event semaphore.
7038 */
7039 char szDevIommu[64];
7040 RT_ZERO(szDevIommu);
7041 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
7042 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
7043 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
7044 AssertLogRelRCReturn(rc, rc);
7045
7046 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7047 AssertLogRelRCReturn(rc, rc);
7048
7049#ifdef IOMMU_WITH_DTE_CACHE
7050 /*
7051 * Initialize the critsect of the cache.
7052 */
7053 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7054 AssertLogRelRCReturn(rc, rc);
7055
7056 /* Several places in this code relies on this basic assumption - assert it! */
7057 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7058#endif
7059
7060#ifdef IOMMU_WITH_IOTLBE_CACHE
7061 /*
7062 * Allocate IOTLB entries.
7063 * This is allocated upfront since we expect a relatively small number of entries,
7064 * is more cache-line efficient and easier to track least recently used entries for
7065 * eviction when the cache is full. This also avoids unpredictable behavior during
7066 * the lifetime of the VM if the hyperheap gets full.
7067 */
7068 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7069 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7070 if (!pThisR3->paIotlbes)
7071 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7072 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7073 RTListInit(&pThisR3->LstLruIotlbe);
7074 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7075#endif
7076
7077 /*
7078 * Initialize read-only registers.
7079 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7080 */
7081 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7082 pThis->ExtFeat.u64 = 0;
7083 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7084 //pThis->ExtFeat.n.u1PprSup = 0;
7085 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7086 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7087 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7088 pThis->ExtFeat.n.u1InvAllSup = 1;
7089 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7090 pThis->ExtFeat.n.u1HwErrorSup = 1;
7091 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7092 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7093 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7094 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7095 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7096 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7097 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7098 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7099 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7100 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7101 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7102 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7103 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7104 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7105 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7106 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7107 //pThis->ExtFeat.n.u2MarcSup = 0;
7108 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7109 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7110 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7111 //pThis->ExtFeat.n.u1GstIoSup = 0;
7112 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7113 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7114 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7115 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7116 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7117 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7118 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7119
7120 pThis->DevSpecificFeat.u64 = 0;
7121 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7122 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7123
7124 pThis->DevSpecificCtrl.u64 = 0;
7125 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7126 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7127
7128 pThis->DevSpecificStatus.u64 = 0;
7129 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7130 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7131
7132 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7133
7134 pThis->RsvdReg = 0;
7135
7136 /*
7137 * Initialize parts of the IOMMU state as it would during reset.
7138 * Also initializes non-zero initial values like IRTE cache keys.
7139 * Must be called -after- initializing PCI config. space registers.
7140 */
7141 iommuAmdR3Reset(pDevIns);
7142
7143 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7144 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7145 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7146 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7147 pThis->ExtFeat.u64));
7148 return VINF_SUCCESS;
7149}
7150
7151#else
7152
7153/**
7154 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7155 */
7156static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7157{
7158 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7159 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7160 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7161 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7162
7163 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7164 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7165 AssertRCReturn(rc, rc);
7166
7167 /* Set up the MMIO RZ handlers. */
7168 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7169 AssertRCReturn(rc, rc);
7170
7171 /* Set up the IOMMU RZ callbacks. */
7172 PDMIOMMUREGCC IommuReg;
7173 RT_ZERO(IommuReg);
7174 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7175 IommuReg.idxIommu = pThis->idxIommu;
7176 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7177 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7178 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7179 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7180 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7181 AssertRCReturn(rc, rc);
7182 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7183 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7184 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7185 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
7186 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
7187 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
7188 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
7189 return VINF_SUCCESS;
7190}
7191#endif
7192
7193
7194/**
7195 * The device registration structure.
7196 */
7197const PDMDEVREG g_DeviceIommuAmd =
7198{
7199 /* .u32Version = */ PDM_DEVREG_VERSION,
7200 /* .uReserved0 = */ 0,
7201 /* .szName = */ "iommu-amd",
7202 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7203 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7204 /* .cMaxInstances = */ 1,
7205 /* .uSharedVersion = */ 42,
7206 /* .cbInstanceShared = */ sizeof(IOMMU),
7207 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7208 /* .cbInstanceRC = */ sizeof(IOMMURC),
7209 /* .cMaxPciDevices = */ 1,
7210 /* .cMaxMsixVectors = */ 0,
7211 /* .pszDescription = */ "IOMMU (AMD)",
7212#if defined(IN_RING3)
7213 /* .pszRCMod = */ "VBoxDDRC.rc",
7214 /* .pszR0Mod = */ "VBoxDDR0.r0",
7215 /* .pfnConstruct = */ iommuAmdR3Construct,
7216 /* .pfnDestruct = */ iommuAmdR3Destruct,
7217 /* .pfnRelocate = */ NULL,
7218 /* .pfnMemSetup = */ NULL,
7219 /* .pfnPowerOn = */ NULL,
7220 /* .pfnReset = */ iommuAmdR3Reset,
7221 /* .pfnSuspend = */ NULL,
7222 /* .pfnResume = */ NULL,
7223 /* .pfnAttach = */ NULL,
7224 /* .pfnDetach = */ NULL,
7225 /* .pfnQueryInterface = */ NULL,
7226 /* .pfnInitComplete = */ NULL,
7227 /* .pfnPowerOff = */ NULL,
7228 /* .pfnSoftReset = */ NULL,
7229 /* .pfnReserved0 = */ NULL,
7230 /* .pfnReserved1 = */ NULL,
7231 /* .pfnReserved2 = */ NULL,
7232 /* .pfnReserved3 = */ NULL,
7233 /* .pfnReserved4 = */ NULL,
7234 /* .pfnReserved5 = */ NULL,
7235 /* .pfnReserved6 = */ NULL,
7236 /* .pfnReserved7 = */ NULL,
7237#elif defined(IN_RING0)
7238 /* .pfnEarlyConstruct = */ NULL,
7239 /* .pfnConstruct = */ iommuAmdRZConstruct,
7240 /* .pfnDestruct = */ NULL,
7241 /* .pfnFinalDestruct = */ NULL,
7242 /* .pfnRequest = */ NULL,
7243 /* .pfnReserved0 = */ NULL,
7244 /* .pfnReserved1 = */ NULL,
7245 /* .pfnReserved2 = */ NULL,
7246 /* .pfnReserved3 = */ NULL,
7247 /* .pfnReserved4 = */ NULL,
7248 /* .pfnReserved5 = */ NULL,
7249 /* .pfnReserved6 = */ NULL,
7250 /* .pfnReserved7 = */ NULL,
7251#elif defined(IN_RC)
7252 /* .pfnConstruct = */ iommuAmdRZConstruct,
7253 /* .pfnReserved0 = */ NULL,
7254 /* .pfnReserved1 = */ NULL,
7255 /* .pfnReserved2 = */ NULL,
7256 /* .pfnReserved3 = */ NULL,
7257 /* .pfnReserved4 = */ NULL,
7258 /* .pfnReserved5 = */ NULL,
7259 /* .pfnReserved6 = */ NULL,
7260 /* .pfnReserved7 = */ NULL,
7261#else
7262# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7263#endif
7264 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7265};
7266
7267#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7268
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