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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 89557

Last change on this file since 89557 was 89554, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 Comment.
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1/* $Id: DevIommuAmd.cpp 89554 2021-06-08 06:40:52Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26
27#include <iprt/x86.h>
28#include <iprt/string.h>
29#include <iprt/avl.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47
48/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
49#ifdef IN_RING3
50# define IOMMU_WITH_IOTLBE_CACHE
51#endif
52/** Enable the interrupt cache. */
53#define IOMMU_WITH_IRTE_CACHE
54
55/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
56#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
57# define IOMMU_WITH_DTE_CACHE
58/** The maximum number of device IDs in the cache. */
59# define IOMMU_DEV_CACHE_COUNT 16
60/** An empty device ID. */
61# define IOMMU_DTE_CACHE_KEY_NIL 0
62#endif
63
64#ifdef IOMMU_WITH_IRTE_CACHE
65/** The maximum number of IRTE cache entries. */
66# define IOMMU_IRTE_CACHE_COUNT 32
67/** A NIL IRTE cache entry key. */
68# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
69/** Gets the device ID from an IRTE cache entry key. */
70#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
71/** Gets the IOVA from the IOTLB entry key. */
72# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
73/** Makes an IRTE cache entry key.
74 *
75 * Bits 31:16 is the device ID (Bus, Device, Function).
76 * Bits 15:0 is the the offset into the IRTE table.
77 */
78# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
79#endif /* IOMMU_WITH_IRTE_CACHE */
80
81#ifdef IOMMU_WITH_IOTLBE_CACHE
82/** The maximum number of IOTLB entries. */
83# define IOMMU_IOTLBE_MAX 96
84/** The mask of bits covering the domain ID in the IOTLBE key. */
85# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
86/** The mask of bits covering the IOVA in the IOTLBE key. */
87# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
88/** The number of bits to shift for the domain ID of the IOTLBE key. */
89# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
90/** A NIL IOTLB key. */
91# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
92/** Gets the domain ID from an IOTLB entry key. */
93# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
94/** Gets the IOVA from the IOTLB entry key. */
95# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
96/** Makes an IOTLB entry key.
97 *
98 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
99 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
100 * so bottom 12 bits are free.
101 *
102 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
103 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
104 */
105# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
106 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
107#endif /* IOMMU_WITH_IOTLBE_CACHE */
108
109#ifdef IOMMU_WITH_DTE_CACHE
110/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
111 *
112 * Some of these flags are "basic" i.e. they correspond directly to their bits in
113 * the DTE. The rest of the flags are based on checks or operations on several DTE
114 * bits.
115 *
116 * The basic flags are:
117 * - VALID (DTE.V)
118 * - IO_PERM_READ (DTE.IR)
119 * - IO_PERM_WRITE (DTE.IW)
120 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
121 * masking consistent)
122 * - SUPPRESS_ALL_IOPF (DTE.SA)
123 * - SUPPRESS_IOPF (DTE.SE)
124 * - INTR_MAP_VALID (DTE.IV)
125 * - IGNORE_UNMAPPED_INTR (DTE.IG)
126 *
127 * @see iommuAmdGetBasicDevFlags()
128 * @{ */
129/** The DTE is present. */
130# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
131/** The DTE is valid. */
132# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
133/** The DTE permissions apply for address translations. */
134# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
135/** DTE permission - I/O read allowed. */
136# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
137/** DTE permission - I/O write allowed. */
138# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
139/** DTE permission - reserved. */
140# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
141/** Address translation required. */
142# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
143/** Suppress all I/O page faults. */
144# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
145/** Suppress I/O page faults. */
146# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
147/** Interrupt map valid. */
148# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
149/** Ignore unmapped interrupts. */
150# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
151/** An I/O page fault has been raised for this device. */
152# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
153/** Fixed and arbitrary interrupt control: Target Abort. */
154# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
155/** Fixed and arbitrary interrupt control: Forward unmapped. */
156# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
157/** Fixed and arbitrary interrupt control: Remapped. */
158# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
159/** Fixed and arbitrary interrupt control: Reserved. */
160# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
161/** @} */
162
163/** The number of bits to shift I/O device flags for DTE permissions. */
164# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
165/** The mask of DTE permissions in I/O device flags. */
166# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
167/** The number of bits to shift I/O device flags for interrupt control bits. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
169/** The mask of interrupt control bits in I/O device flags. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
171/** The number of bits to shift for ignore-unmapped interrupts bit. */
172# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
173
174/** Acquires the cache lock. */
175#ifdef IN_RING3
176# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_IGNORED)
177#else
178# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) \
179 do { \
180 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VINF_SUCCESS); \
181 AssertRC(rcLock); \
182 } while (0)
183#endif
184
185/** Releases the cache lock. */
186# define IOMMU_CACHE_UNLOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
187#endif /* IOMMU_WITH_DTE_CACHE */
188
189/** Acquires the PDM lock (returns a_rcBusy on contention). */
190#define IOMMU_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
191 do { \
192 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)); \
193 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
194 { /* likely */ } \
195 else \
196 return rcLock; \
197 } while (0)
198
199/** Acquires the PDM lock (shouldn't really fail). */
200#ifdef IN_RING3
201# define IOMMU_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
202#else
203# define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
204 do { \
205 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
206 AssertRC(rcLock); \
207 } while (0)
208#endif
209
210/** Checks if the current thread owns the PDM lock. */
211# define IOMMU_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
212 do \
213 { \
214 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner((a_pDevIns))); \
215 NOREF(a_pThisCC); \
216 } while (0)
217
218/** Releases the PDM lock. */
219# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
220
221
222/*********************************************************************************************************************************
223* Structures and Typedefs *
224*********************************************************************************************************************************/
225/**
226 * IOMMU operation (transaction).
227 */
228typedef enum IOMMUOP
229{
230 /** Address translation request. */
231 IOMMUOP_TRANSLATE_REQ = 0,
232 /** Memory read request. */
233 IOMMUOP_MEM_READ,
234 /** Memory write request. */
235 IOMMUOP_MEM_WRITE,
236 /** Interrupt request. */
237 IOMMUOP_INTR_REQ,
238 /** Command. */
239 IOMMUOP_CMD
240} IOMMUOP;
241/** Pointer to a IOMMU operation. */
242typedef IOMMUOP *PIOMMUOP;
243
244/**
245 * I/O page lookup.
246 */
247typedef struct IOPAGELOOKUP
248{
249 /** The translated system physical address. */
250 RTGCPHYS GCPhysSpa;
251 /** The number of offset bits in the system physical address. */
252 uint8_t cShift;
253 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
254 uint8_t fPerm;
255} IOPAGELOOKUP;
256/** Pointer to an I/O page lookup. */
257typedef IOPAGELOOKUP *PIOPAGELOOKUP;
258/** Pointer to a const I/O page lookup. */
259typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
260
261/**
262 * I/O address range.
263 */
264typedef struct IOADDRRANGE
265{
266 /** The address (virtual or physical). */
267 uint64_t uAddr;
268 /** The size of the access in bytes. */
269 size_t cb;
270 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
271 uint8_t fPerm;
272} IOADDRRANGE;
273/** Pointer to an I/O address range. */
274typedef IOADDRRANGE *PIOADDRRANGE;
275/** Pointer to a const I/O address range. */
276typedef IOADDRRANGE const *PCIOADDRRANGE;
277
278#ifdef IOMMU_WITH_DTE_CACHE
279/**
280 * Device Table Entry Cache.
281 */
282typedef struct DTECACHE
283{
284 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
285 uint16_t fFlags;
286 /** The domain ID assigned for this device by software. */
287 uint16_t idDomain;
288} DTECACHE;
289/** Pointer to an I/O device struct. */
290typedef DTECACHE *PDTECACHE;
291/** Pointer to a const I/O device struct. */
292typedef DTECACHE *PCDTECACHE;
293AssertCompileSize(DTECACHE, 4);
294#endif /* IOMMU_WITH_DTE_CACHE */
295
296#ifdef IOMMU_WITH_IOTLBE_CACHE
297/**
298 * I/O TLB Entry.
299 * Keep this as small and aligned as possible.
300 */
301typedef struct IOTLBE
302{
303 /** The AVL tree node. */
304 AVLU64NODECORE Core;
305 /** The least recently used (LRU) list node. */
306 RTLISTNODE NdLru;
307 /** The I/O page lookup results of the translation. */
308 IOPAGELOOKUP PageLookup;
309 /** Whether the entry needs to be evicted from the cache. */
310 bool fEvictPending;
311} IOTLBE;
312/** Pointer to an IOMMU I/O TLB entry struct. */
313typedef IOTLBE *PIOTLBE;
314/** Pointer to a const IOMMU I/O TLB entry struct. */
315typedef IOTLBE const *PCIOTLBE;
316AssertCompileSizeAlignment(IOTLBE, 8);
317AssertCompileMemberOffset(IOTLBE, Core, 0);
318#endif /* IOMMU_WITH_IOTLBE_CACHE */
319
320#ifdef IOMMU_WITH_IRTE_CACHE
321/**
322 * Interrupt Remap Table Entry Cache.
323 */
324typedef struct IRTECACHE
325{
326 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
327 uint32_t uKey;
328 /** The IRTE. */
329 IRTE_T Irte;
330} IRTECACHE;
331/** Pointer to an IRTE cache struct. */
332typedef IRTECACHE *PIRTECACHE;
333/** Pointer to a const IRTE cache struct. */
334typedef IRTECACHE const *PCIRTECACHE;
335AssertCompileSizeAlignment(IRTECACHE, 4);
336#endif /* IOMMU_WITH_IRTE_CACHE */
337
338/**
339 * The shared IOMMU device state.
340 */
341typedef struct IOMMU
342{
343 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
344 uint32_t idxIommu;
345 /** IOMMU magic. */
346 uint32_t u32Magic;
347
348 /** The MMIO handle. */
349 IOMMMIOHANDLE hMmio;
350 /** The event semaphore the command thread waits on. */
351 SUPSEMEVENT hEvtCmdThread;
352 /** Whether the command thread has been signaled for wake up. */
353 bool volatile fCmdThreadSignaled;
354 /** Padding. */
355 bool afPadding0[7];
356
357#ifdef IOMMU_WITH_DTE_CACHE
358 /** The critsect that protects the cache from concurrent access. */
359 PDMCRITSECT CritSectCache;
360 /** Array of device IDs. */
361 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
362 /** Array of DTE cache entries. */
363 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
364#endif
365#ifdef IOMMU_WITH_IRTE_CACHE
366 /** Array of IRTE cache entries. */
367 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
368#endif
369
370 /** @name PCI: Base capability block registers.
371 * @{ */
372 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
373 /** @} */
374
375 /** @name MMIO: Control and status registers.
376 * @{ */
377 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
378 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
379 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
380 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
381 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
382 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
383 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
384 /** @} */
385
386 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
387 * @{ */
388 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
389 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
390 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
391 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
392 /** @} */
393
394 /** @todo IOMMU: SMI filter. */
395
396 /** @name MMIO: Guest Virtual-APIC Log registers.
397 * @{ */
398 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
399 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
400 /** @} */
401
402 /** @name MMIO: Alternate PPR and Event Log registers.
403 * @{ */
404 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
405 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
406 /** @} */
407
408 /** @name MMIO: Device-specific feature registers.
409 * @{ */
410 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
411 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
412 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
413 /** @} */
414
415 /** @name MMIO: MSI Capability Block registers.
416 * @{ */
417 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
418 /** @} */
419
420 /** @name MMIO: Performance Optimization Control registers.
421 * @{ */
422 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
423 /** @} */
424
425 /** @name MMIO: x2APIC Control registers.
426 * @{ */
427 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
428 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
429 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
430 /** @} */
431
432 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
433 * @{ */
434 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
435 /** @} */
436
437 /** @name MMIO: Reserved register.
438 * @{ */
439 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
440 /** @} */
441
442 /** @name MMIO: Command and Event Log pointer registers.
443 * @{ */
444 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
445 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
446 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
447 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
448 /** @} */
449
450 /** @name MMIO: Command and Event Status register.
451 * @{ */
452 IOMMU_STATUS_T Status; /**< IOMMU status register. */
453 /** @} */
454
455 /** @name MMIO: PPR Log Head and Tail pointer registers.
456 * @{ */
457 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
458 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
459 /** @} */
460
461 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
462 * @{ */
463 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
464 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
465 /** @} */
466
467 /** @name MMIO: PPR Log B Head and Tail pointer registers.
468 * @{ */
469 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
470 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
471 /** @} */
472
473 /** @name MMIO: Event Log B Head and Tail pointer registers.
474 * @{ */
475 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
476 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
477 /** @} */
478
479 /** @name MMIO: PPR Log Overflow protection registers.
480 * @{ */
481 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
482 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
483 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
484 /** @} */
485
486 /** @todo IOMMU: IOMMU Event counter registers. */
487
488#ifdef VBOX_WITH_STATISTICS
489 /** @name IOMMU: Stat counters.
490 * @{ */
491 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
492 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
493 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
494 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
495
496 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
497 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
498
499 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
500 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
501 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
502 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
503
504 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
505 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
506 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
507 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
508
509 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
510 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
511 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
512 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
513 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
514 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
515 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
516 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
517 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
518
519 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
520 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
521
522 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
523 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
524
525 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
526 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
527
528 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
529 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
530 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
531 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
532 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
533 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
534 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
535
536 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
537 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
538 /** @} */
539#endif
540} IOMMU;
541/** Pointer to the IOMMU device state. */
542typedef IOMMU *PIOMMU;
543/** Pointer to the const IOMMU device state. */
544typedef const IOMMU *PCIOMMU;
545AssertCompileMemberAlignment(IOMMU, hMmio, 8);
546#ifdef IOMMU_WITH_DTE_CACHE
547AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
548AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
549AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
550#endif
551#ifdef IOMMU_WITH_IRTE_CACHE
552AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
553#endif
554AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
555AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
556AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
557AssertCompileMemberAlignment(IOMMU, Status, 8);
558
559/**
560 * The ring-3 IOMMU device state.
561 */
562typedef struct IOMMUR3
563{
564 /** Device instance. */
565 PPDMDEVINSR3 pDevInsR3;
566 /** The IOMMU helpers. */
567 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
568 /** The command thread handle. */
569 R3PTRTYPE(PPDMTHREAD) pCmdThread;
570#ifdef IOMMU_WITH_IOTLBE_CACHE
571 /** Pointer to array of pre-allocated IOTLBEs. */
572 PIOTLBE paIotlbes;
573 /** Maps [DomainId,Iova] to [IOTLBE]. */
574 AVLU64TREE TreeIotlbe;
575 /** LRU list anchor for IOTLB entries. */
576 RTLISTANCHOR LstLruIotlbe;
577 /** Index of the next unused IOTLB. */
578 uint32_t idxUnusedIotlbe;
579 /** Number of cached IOTLB entries in the tree. */
580 uint32_t cCachedIotlbes;
581#endif
582} IOMMUR3;
583/** Pointer to the ring-3 IOMMU device state. */
584typedef IOMMUR3 *PIOMMUR3;
585/** Pointer to the const ring-3 IOMMU device state. */
586typedef const IOMMUR3 *PCIOMMUR3;
587#ifdef IOMMU_WITH_IOTLBE_CACHE
588AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
589AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
590AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
591#endif
592
593/**
594 * The ring-0 IOMMU device state.
595 */
596typedef struct IOMMUR0
597{
598 /** Device instance. */
599 PPDMDEVINSR0 pDevInsR0;
600 /** The IOMMU helpers. */
601 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
602} IOMMUR0;
603/** Pointer to the ring-0 IOMMU device state. */
604typedef IOMMUR0 *PIOMMUR0;
605
606/**
607 * The raw-mode IOMMU device state.
608 */
609typedef struct IOMMURC
610{
611 /** Device instance. */
612 PPDMDEVINSRC pDevInsRC;
613 /** The IOMMU helpers. */
614 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
615} IOMMURC;
616/** Pointer to the raw-mode IOMMU device state. */
617typedef IOMMURC *PIOMMURC;
618
619/** The IOMMU device state for the current context. */
620typedef CTX_SUFF(IOMMU) IOMMUCC;
621/** Pointer to the IOMMU device state for the current context. */
622typedef CTX_SUFF(PIOMMU) PIOMMUCC;
623
624/**
625 * IOMMU register access.
626 */
627typedef struct IOMMUREGACC
628{
629 const char *pszName;
630 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
631 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
632} IOMMUREGACC;
633/** Pointer to an IOMMU register access. */
634typedef IOMMUREGACC *PIOMMUREGACC;
635/** Pointer to a const IOMMU register access. */
636typedef IOMMUREGACC const *PCIOMMUREGACC;
637
638#ifdef IOMMU_WITH_IOTLBE_CACHE
639/**
640 * IOTLBE flush argument.
641 */
642typedef struct IOTLBEFLUSHARG
643{
644 /** The ring-3 IOMMU device state. */
645 PIOMMUR3 pIommuR3;
646 /** The domain ID to flush. */
647 uint16_t idDomain;
648} IOTLBEFLUSHARG;
649/** Pointer to an IOTLBE flush argument. */
650typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
651/** Pointer to a const IOTLBE flush argument. */
652typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
653
654/**
655 * IOTLBE Info. argument.
656 */
657typedef struct IOTLBEINFOARG
658{
659 /** The ring-3 IOMMU device state. */
660 PIOMMUR3 pIommuR3;
661 /** The info helper. */
662 PCDBGFINFOHLP pHlp;
663 /** The domain ID to dump IOTLB entry. */
664 uint16_t idDomain;
665} IOTLBEINFOARG;
666/** Pointer to an IOTLBE flush argument. */
667typedef IOTLBEINFOARG *PIOTLBEINFOARG;
668/** Pointer to a const IOTLBE flush argument. */
669typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
670#endif
671
672/**
673 * IOMMU operation auxiliary info.
674 */
675typedef struct IOMMUOPAUX
676{
677 /** The IOMMU operation being performed. */
678 IOMMUOP enmOp;
679 /** The device table entry (can be NULL). */
680 PCDTE_T pDte;
681 /** The device ID (bus, device, function). */
682 uint16_t idDevice;
683 /** The domain ID (when the DTE isn't provided). */
684 uint16_t idDomain;
685} IOMMUOPAUX;
686/** Pointer to an I/O address lookup struct. */
687typedef IOMMUOPAUX *PIOMMUOPAUX;
688/** Pointer to a const I/O address lookup struct. */
689typedef IOMMUOPAUX const *PCIOMMUOPAUX;
690
691typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
692 PIOPAGELOOKUP pPageLookup));
693typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
694
695
696/*********************************************************************************************************************************
697* Global Variables *
698*********************************************************************************************************************************/
699#ifdef IN_RING3
700/**
701 * An array of the number of device table segments supported.
702 * Indexed by u2DevTabSegSup.
703 */
704static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
705#endif
706
707#if defined(IN_RING3) || defined(LOG_ENABLED)
708/**
709 * The IOMMU I/O permission names.
710 */
711static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
712#endif
713
714/**
715 * An array of the masks to select the device table segment index from a device ID.
716 */
717static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
718
719/**
720 * An array of the shift values to select the device table segment index from a
721 * device ID.
722 */
723static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
724
725/**
726 * The maximum size (inclusive) of each device table segment (0 to 7).
727 * Indexed by the device table segment index.
728 */
729static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
730
731
732#ifndef VBOX_DEVICE_STRUCT_TESTCASE
733/**
734 * Gets the maximum number of buffer entries for the given buffer length.
735 *
736 * @returns Number of buffer entries.
737 * @param uEncodedLen The length (power-of-2 encoded).
738 */
739DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
740{
741 Assert(uEncodedLen > 7);
742 Assert(uEncodedLen < 16);
743 return 2 << (uEncodedLen - 1);
744}
745
746
747/**
748 * Gets the total length of the buffer given a base register's encoded length.
749 *
750 * @returns The length of the buffer in bytes.
751 * @param uEncodedLen The length (power-of-2 encoded).
752 */
753DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
754{
755 Assert(uEncodedLen > 7);
756 Assert(uEncodedLen < 16);
757 return (2 << (uEncodedLen - 1)) << 4;
758}
759
760
761/**
762 * Gets the number of (unconsumed) entries in the event log.
763 *
764 * @returns The number of entries in the event log.
765 * @param pThis The shared IOMMU device state.
766 */
767static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
768{
769 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
770 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
771 if (idxTail >= idxHead)
772 return idxTail - idxHead;
773
774 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
775 return cMaxEvts - idxHead + idxTail;
776}
777
778
779#if defined(IN_RING3) || defined(LOG_ENABLED)
780/**
781 * Gets the descriptive I/O permission name for a memory access.
782 *
783 * @returns The I/O permission name.
784 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
785 */
786static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
787{
788 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
789 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
790 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
791}
792#endif
793
794
795/**
796 * Checks whether two consecutive I/O page lookup results translates to a physically
797 * contiguous region.
798 *
799 * @returns @c true if they are contiguous, @c false otherwise.
800 * @param pPageLookupPrev The I/O page lookup result of the previous page.
801 * @param pPageLookup The I/O page lookup result of the current page.
802 */
803static bool iommuAmdLookupIsAccessContig(PCIOPAGELOOKUP pPageLookupPrev, PCIOPAGELOOKUP pPageLookup)
804{
805 Assert(pPageLookupPrev->fPerm == pPageLookup->fPerm);
806 size_t const cbPrev = RT_BIT_64(pPageLookupPrev->cShift);
807 RTGCPHYS const GCPhysPrev = pPageLookupPrev->GCPhysSpa;
808 RTGCPHYS const GCPhys = pPageLookup->GCPhysSpa;
809#ifdef RT_STRICT
810 /* Paranoia: Ensure offset bits are 0. */
811 {
812 uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pPageLookupPrev->cShift);
813 uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pPageLookup->cShift);
814 Assert(!(GCPhysPrev & fOffMaskPrev));
815 Assert(!(GCPhys & fOffMask));
816 }
817#endif
818 return GCPhysPrev + cbPrev == GCPhys;
819}
820
821
822/**
823 * Gets the basic I/O device flags for the given device table entry.
824 *
825 * @returns The basic I/O device flags.
826 * @param pDte The device table entry.
827 */
828static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
829{
830 /* Extract basic flags from bits 127:0 of the DTE. */
831 uint16_t fFlags = 0;
832 if (pDte->n.u1Valid)
833 {
834 fFlags |= IOMMU_DTE_CACHE_F_VALID;
835
836 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
837 if (pDte->n.u1SuppressAllPfEvents)
838 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
839 if (pDte->n.u1SuppressPfEvents)
840 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
841
842 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
843 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
844 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
845 }
846
847 /* Extract basic flags from bits 255:128 of the DTE. */
848 if (pDte->n.u1IntrMapValid)
849 {
850 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
851
852 /** @todo Skip the if check here (shift/mask the relevant bit over). */
853 if (pDte->n.u1IgnoreUnmappedIntrs)
854 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
855
856 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
857 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
858 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
859 }
860 return fFlags;
861}
862
863
864/**
865 * Remaps the source MSI to the destination MSI given the IRTE.
866 *
867 * @param pMsiIn The source MSI.
868 * @param pMsiOut Where to store the remapped MSI.
869 * @param pIrte The IRTE used for the remapping.
870 */
871static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
872{
873 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
874 *pMsiOut = *pMsiIn;
875
876 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
877 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
878
879 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
880 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
881}
882
883
884#ifdef IOMMU_WITH_DTE_CACHE
885/**
886 * Looks up an entry in the DTE cache for the given device ID.
887 *
888 * @returns The index of the entry, or the cache capacity if no entry was found.
889 * @param pThis The shared IOMMU device state.
890 * @param idDevice The device ID (bus, device, function).
891 */
892DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
893{
894 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
895 for (uint16_t i = 0; i < cDeviceIds; i++)
896 {
897 if (pThis->aDeviceIds[i] == idDevice)
898 return i;
899 }
900 return cDeviceIds;
901}
902
903
904/**
905 * Gets an free/unused DTE cache entry.
906 *
907 * @returns The index of an unused entry, or cache capacity if the cache is full.
908 * @param pThis The shared IOMMU device state.
909 */
910DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
911{
912 /*
913 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
914 * (the latter being an ugly hack) and cannot be a valid device ID.
915 */
916 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
917 for (uint16_t i = 0; i < cDeviceIds; i++)
918 {
919 if (!pThis->aDeviceIds[i])
920 return i;
921 }
922 return cDeviceIds;
923}
924
925
926/**
927 * Adds or updates the I/O device flags for the given device ID.
928 *
929 * @returns VBox status code.
930 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
931 *
932 * @param pDevIns The IOMMU instance data.
933 * @param idDevice The device ID (bus, device, function).
934 * @param pDte The device table entry.
935 * @param fOrMask The device flags (usually compound flags) to OR in with the
936 * basic flags, see IOMMU_DTE_CACHE_F_XXX.
937 */
938static int iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, uint16_t fOrMask)
939{
940 Assert(pDte);
941 Assert(idDevice);
942
943 int rc = VINF_SUCCESS;
944 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask;
945 uint16_t const idDomain = pDte->n.u16DomainId;
946
947 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
948 IOMMU_CACHE_LOCK(pDevIns, pThis);
949
950 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
951 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
952 if (idxDte < cDteCache)
953 {
954 pThis->aDteCache[idxDte].fFlags = fFlags;
955 pThis->aDteCache[idxDte].idDomain = idDomain;
956 }
957 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
958 {
959 pThis->aDeviceIds[idxDte] = idDevice;
960 pThis->aDteCache[idxDte].fFlags = fFlags;
961 pThis->aDteCache[idxDte].idDomain = idDomain;
962 }
963 else
964 rc = VERR_OUT_OF_RESOURCES;
965
966 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
967 return rc;
968}
969
970
971/**
972 * Adds one or more I/O device flags if the device is already present in the cache.
973 *
974 * @param pDevIns The IOMMU instance data.
975 * @param idDevice The device ID (bus, device, function).
976 * @param fFlags Additional device flags to OR with existing flags, see
977 * IOMMU_DTE_CACHE_F_XXX.
978 */
979static void iommuAmdDteCacheAddFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fFlags)
980{
981 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
982 IOMMU_CACHE_LOCK(pDevIns, pThis);
983
984 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
985 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
986 if ( idxDte < cDteCache
987 && (pThis->aDteCache[idxDte].fFlags & IOMMU_DTE_CACHE_F_PRESENT))
988 pThis->aDteCache[idxDte].fFlags |= fFlags;
989
990 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
991}
992
993
994# ifdef IN_RING3
995/**
996 * Removes a DTE cache entry.
997 *
998 * @param pDevIns The IOMMU instance data.
999 * @param idDevice The device ID to remove cache entries for.
1000 */
1001static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1002{
1003 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1004 IOMMU_CACHE_LOCK(pDevIns, pThis);
1005
1006 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1007 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1008 if (idxDte < cDteCache)
1009 {
1010 pThis->aDteCache[idxDte].fFlags = 0;
1011 pThis->aDteCache[idxDte].idDomain = 0;
1012 }
1013
1014 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1015}
1016
1017
1018/**
1019 * Removes all entries in the device table entry cache.
1020 *
1021 * @param pDevIns The IOMMU instance data.
1022 */
1023static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1024{
1025 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1026 IOMMU_CACHE_LOCK(pDevIns, pThis);
1027 RT_ZERO(pThis->aDeviceIds);
1028 RT_ZERO(pThis->aDteCache);
1029 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1030}
1031# endif /* IN_RING3 */
1032#endif /* IOMMU_WITH_DTE_CACHE */
1033
1034
1035#ifdef IOMMU_WITH_IOTLBE_CACHE
1036/**
1037 * Moves the IOTLB entry to the least recently used slot.
1038 *
1039 * @param pThisR3 The ring-3 IOMMU device state.
1040 * @param pIotlbe The IOTLB entry to move.
1041 */
1042DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1043{
1044 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1045 {
1046 RTListNodeRemove(&pIotlbe->NdLru);
1047 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1048 }
1049}
1050
1051
1052/**
1053 * Moves the IOTLB entry to the most recently used slot.
1054 *
1055 * @param pThisR3 The ring-3 IOMMU device state.
1056 * @param pIotlbe The IOTLB entry to move.
1057 */
1058DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1059{
1060 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1061 {
1062 RTListNodeRemove(&pIotlbe->NdLru);
1063 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1064 }
1065}
1066
1067
1068# ifdef IN_RING3
1069/**
1070 * Dumps the IOTLB entry via the debug info helper.
1071 *
1072 * @returns VINF_SUCCESS.
1073 * @param pNode Pointer to an IOTLB entry to dump info.
1074 * @param pvUser Pointer to an IOTLBEINFOARG.
1075 */
1076static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1077{
1078 /* Validate. */
1079 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1080 AssertPtr(pArgs);
1081 AssertPtr(pArgs->pIommuR3);
1082 AssertPtr(pArgs->pHlp);
1083 //Assert(pArgs->pIommuCC->u32Magic == IOMMU_MAGIC);
1084
1085 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1086 if (idDomain == pArgs->idDomain)
1087 {
1088 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1089 AVLU64KEY const uKey = pIotlbe->Core.Key;
1090 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1091 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1092 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1093 size_t const cbPage = RT_BIT_64(cShift);
1094 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1095 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1096 bool const fEvictPending = pIotlbe->fEvictPending;
1097
1098 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1099 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1100 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1101 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1102 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1103 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1104 }
1105
1106 return VINF_SUCCESS;
1107}
1108# endif /* IN_RING3 */
1109
1110
1111/**
1112 * Removes the IOTLB entry if it's associated with the specified domain ID.
1113 *
1114 * @returns VINF_SUCCESS.
1115 * @param pNode Pointer to an IOTLBE.
1116 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1117 */
1118static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1119{
1120 /* Validate. */
1121 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1122 AssertPtr(pArgs);
1123 AssertPtr(pArgs->pIommuR3);
1124 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1125
1126 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1127 if (idDomain == pArgs->idDomain)
1128 {
1129 /* Mark this entry is as invalidated and needs to be evicted later. */
1130 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1131 pIotlbe->fEvictPending = true;
1132 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1133 }
1134 return VINF_SUCCESS;
1135}
1136
1137
1138/**
1139 * Inserts an IOTLB entry into the cache.
1140 *
1141 * @param pThis The shared IOMMU device state.
1142 * @param pThisR3 The ring-3 IOMMU device state.
1143 * @param pIotlbe The IOTLB entry to initialize and insert.
1144 * @param idDomain The domain ID.
1145 * @param uIova The I/O virtual address.
1146 * @param pPageLookup The I/O page lookup result of the access.
1147 */
1148static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1149 PCIOPAGELOOKUP pPageLookup)
1150{
1151 /* Initialize the IOTLB entry with results of the I/O page walk. */
1152 pIotlbe->Core.Key = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1153 pIotlbe->PageLookup = *pPageLookup;
1154
1155 /* Validate. */
1156 Assert(pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL);
1157 Assert(!pIotlbe->fEvictPending);
1158
1159 /* Check if the entry already exists. */
1160 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, pIotlbe->Core.Key);
1161 if (!pFound)
1162 {
1163 /* Insert the entry into the cache. */
1164 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1165 Assert(fInserted); NOREF(fInserted);
1166 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1167 ++pThisR3->cCachedIotlbes;
1168 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1169 }
1170 else
1171 {
1172 /* Update the existing entry. */
1173 if (pFound->fEvictPending)
1174 {
1175 pFound->fEvictPending = false;
1176 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1177 }
1178 Assert(pFound->PageLookup.cShift == pPageLookup->cShift);
1179 pFound->PageLookup.fPerm = pPageLookup->fPerm;
1180 pFound->PageLookup.GCPhysSpa = pPageLookup->GCPhysSpa;
1181 }
1182}
1183
1184
1185/**
1186 * Removes an IOTLB entry from the cache for the given key.
1187 *
1188 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1189 * the tree.
1190 * @param pThis The shared IOMMU device state.
1191 * @param pThisR3 The ring-3 IOMMU device state.
1192 * @param uKey The key of the IOTLB entry to remove.
1193 */
1194static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1195{
1196 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1197 if (pIotlbe)
1198 {
1199 if (pIotlbe->fEvictPending)
1200 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1201
1202 RT_ZERO(pIotlbe->Core);
1203 RT_ZERO(pIotlbe->PageLookup);
1204 /* We must not erase the LRU node connections here! */
1205 pIotlbe->fEvictPending = false;
1206 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1207
1208 Assert(pThisR3->cCachedIotlbes > 0);
1209 --pThisR3->cCachedIotlbes;
1210 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1211 }
1212 return pIotlbe;
1213}
1214
1215
1216/**
1217 * Looks up an IOTLB from the cache.
1218 *
1219 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1220 * @param pThis The shared IOMMU device state.
1221 * @param pThisR3 The ring-3 IOMMU device state.
1222 * @param idDomain The domain ID.
1223 * @param uIova The I/O virtual address.
1224 */
1225static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1226{
1227 RT_NOREF(pThis);
1228
1229 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1230 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1231 if ( pIotlbe
1232 && !pIotlbe->fEvictPending)
1233 return pIotlbe;
1234
1235 /*
1236 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1237 * them from the cache immediately. We found an entry pending eviction, just return that
1238 * nothing was found (rather than evicting now).
1239 */
1240 return NULL;
1241}
1242
1243
1244/**
1245 * Adds an IOTLB entry to the cache.
1246 *
1247 * @param pThis The shared IOMMU device state.
1248 * @param pThisR3 The ring-3 IOMMU device state.
1249 * @param idDomain The domain ID.
1250 * @param uIova The I/O virtual address.
1251 * @param pPageLookup The I/O page lookup result of the access.
1252 */
1253static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIova, PCIOPAGELOOKUP pPageLookup)
1254{
1255 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1256 Assert(pPageLookup);
1257 Assert(pPageLookup->cShift <= 31);
1258 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1259
1260 /*
1261 * If there are no unused IOTLB entries, evict the LRU entry.
1262 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1263 */
1264 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1265 {
1266 /* Grab the least recently used entry. */
1267 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1268 Assert(pIotlbe);
1269
1270 /* If the entry is in the cache, remove it. */
1271 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1272 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1273
1274 /* Initialize and insert the IOTLB entry into the cache. */
1275 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1276
1277 /* Move the entry to the most recently used slot. */
1278 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1279 }
1280 else
1281 {
1282 /* Grab an unused IOTLB entry from the pre-allocated list. */
1283 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1284 ++pThisR3->idxUnusedIotlbe;
1285
1286 /* Initialize and insert the IOTLB entry into the cache. */
1287 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1288
1289 /* Add the entry to the most recently used slot. */
1290 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1291 }
1292}
1293
1294
1295/**
1296 * Removes all IOTLB entries from the cache.
1297 *
1298 * @param pDevIns The IOMMU instance data.
1299 */
1300static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1301{
1302 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1303 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1304 IOMMU_CACHE_LOCK(pDevIns, pThis);
1305
1306 if (pThisR3->cCachedIotlbes > 0)
1307 {
1308 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
1309 RT_BZERO(pThisR3->paIotlbes, cbIotlbes);
1310 pThisR3->idxUnusedIotlbe = 0;
1311 pThisR3->cCachedIotlbes = 0;
1312 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1313 RTListInit(&pThisR3->LstLruIotlbe);
1314 }
1315
1316 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1317}
1318
1319
1320/**
1321 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1322 * domain ID from the cache.
1323 *
1324 * @param pDevIns The IOMMU instance data.
1325 * @param idDomain The domain ID.
1326 * @param uIova The I/O virtual address to invalidate.
1327 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1328 */
1329static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1330{
1331 /* Validate. */
1332 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1333 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1334 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1335
1336 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1337 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1338 IOMMU_CACHE_LOCK(pDevIns, pThis);
1339
1340 do
1341 {
1342 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1343 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1344 if (pIotlbe)
1345 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1346 uIova += X86_PAGE_4K_SIZE;
1347 cbInvalidate -= X86_PAGE_4K_SIZE;
1348 } while (cbInvalidate > 0);
1349
1350 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1351}
1352
1353
1354/**
1355 * Removes all IOTLB entries for the specified domain ID.
1356 *
1357 * @param pDevIns The IOMMU instance data.
1358 * @param idDomain The domain ID.
1359 */
1360static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1361{
1362 /*
1363 * We need to iterate the tree and search based on the domain ID.
1364 * But it seems we cannot remove items while iterating the tree.
1365 * Thus, we simply mark entries for eviction later but move them to the LRU
1366 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1367 */
1368 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1369 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1370 IOMMU_CACHE_LOCK(pDevIns, pThis);
1371
1372 IOTLBEFLUSHARG Args;
1373 Args.pIommuR3 = pThisR3;
1374 Args.idDomain = idDomain;
1375 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1376
1377 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1378}
1379
1380
1381/**
1382 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1383 *
1384 * @param pDevIns The IOMMU instance data.
1385 * @param idDomain The domain ID.
1386 * @param uIova The I/O virtual address.
1387 * @param cbIova The size of the access (must be 4K aligned).
1388 * @param GCPhysSpa The translated system-physical address.
1389 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
1390 */
1391static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbIova, RTGCPHYS GCPhysSpa,
1392 uint8_t fPerm)
1393{
1394 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1395 Assert(!(GCPhysSpa & X86_PAGE_4K_OFFSET_MASK));
1396 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1397 Assert(cbIova >= X86_PAGE_4K_SIZE);
1398
1399 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1400 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1401
1402 /* Add IOTLB entries for every page in the access. */
1403 IOPAGELOOKUP PageLookup;
1404 RT_ZERO(PageLookup);
1405 PageLookup.cShift = X86_PAGE_4K_SHIFT;
1406 PageLookup.fPerm = fPerm;
1407 PageLookup.GCPhysSpa = GCPhysSpa;
1408
1409 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1410 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1411
1412 IOMMU_CACHE_LOCK(pDevIns, pThis);
1413 /** @todo Re-check DTE cache? */
1414 do
1415 {
1416 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIova, &PageLookup);
1417 uIova += X86_PAGE_4K_SIZE;
1418 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1419 --cPages;
1420 } while (cPages > 0);
1421 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1422}
1423#endif /* IOMMU_WITH_IOTLBE_CACHE */
1424
1425
1426#ifdef IOMMU_WITH_IRTE_CACHE
1427/**
1428 * Looks up an IRTE cache entry.
1429 *
1430 * @returns Index of the found entry, or cache capacity if not found.
1431 * @param pThis The shared IOMMU device state.
1432 * @param idDevice The device ID (bus, device, function).
1433 * @param offIrte The offset into the interrupt remap table.
1434 */
1435static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1436{
1437 /** @todo Consider sorting and binary search when the cache capacity grows.
1438 * For the IRTE cache this should be okay since typically guests do not alter the
1439 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1440 * often. */
1441 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1442 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1443 for (uint16_t i = 0; i < cIrteCache; i++)
1444 if (pThis->aIrteCache[i].uKey == uKey)
1445 return i;
1446 return cIrteCache;
1447}
1448
1449
1450/**
1451 * Gets a free/unused IRTE cache entry.
1452 *
1453 * @returns The index of an unused entry, or cache capacity if the cache is full.
1454 * @param pThis The shared IOMMU device state.
1455 */
1456static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1457{
1458 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1459 for (uint16_t i = 0; i < cIrteCache; i++)
1460 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1461 {
1462 Assert(!pThis->aIrteCache[i].Irte.u32);
1463 return i;
1464 }
1465 return cIrteCache;
1466}
1467
1468
1469/**
1470 * Looks up the IRTE cache for the given MSI.
1471 *
1472 * @returns VBox status code.
1473 * @param pDevIns The IOMMU instance data.
1474 * @param idDevice The device ID (bus, device, function).
1475 * @param enmOp The IOMMU operation being performed.
1476 * @param pMsiIn The source MSI.
1477 * @param pMsiOut Where to store the remapped MSI.
1478 */
1479static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1480{
1481 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1482
1483 int rc = VERR_NOT_FOUND;
1484 /* Deal with such cases in the slower/fallback path. */
1485 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1486 { /* likely */ }
1487 else
1488 return rc;
1489
1490 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1491 IOMMU_CACHE_LOCK(pDevIns, pThis);
1492
1493 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1494 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1495 {
1496 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1497 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1498 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1499 {
1500 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1501
1502 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1503 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1504 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1505 {
1506 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1507 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1508 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1509 {
1510 /* Interrupt table length has been verified prior to adding entries to the cache. */
1511 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1512 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1513 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1514 {
1515 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1516 Assert(pIrte->n.u1RemapEnable);
1517 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1518 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1519 rc = VINF_SUCCESS;
1520 }
1521 }
1522 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1523 {
1524 *pMsiOut = *pMsiIn;
1525 rc = VINF_SUCCESS;
1526 }
1527 }
1528 }
1529 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1530 {
1531 *pMsiOut = *pMsiIn;
1532 rc = VINF_SUCCESS;
1533 }
1534 }
1535
1536 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1537 return rc;
1538}
1539
1540
1541/**
1542 * Adds or updates the IRTE cache for the given IRTE.
1543 *
1544 * @returns VBox status code.
1545 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1546 *
1547 * @param pDevIns The IOMMU instance data.
1548 * @param idDevice The device ID (bus, device, function).
1549 * @param offIrte The offset into the interrupt remap table.
1550 * @param pIrte The IRTE to cache.
1551 */
1552static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1553{
1554 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1555
1556 int rc = VINF_SUCCESS;
1557 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1558 IOMMU_CACHE_LOCK(pDevIns, pThis);
1559
1560 /* Find an existing entry or get an unused slot. */
1561 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1562 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1563 if ( idxIrteCache < cIrteCache
1564 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1565 {
1566 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1567 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1568 }
1569 else
1570 rc = VERR_OUT_OF_RESOURCES;
1571
1572 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1573 return rc;
1574}
1575
1576
1577# ifdef IN_RING3
1578/**
1579 * Removes IRTE cache entries for the given device ID.
1580 *
1581 * @param pDevIns The IOMMU instance data.
1582 * @param idDevice The device ID (bus, device, function).
1583 */
1584static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1585{
1586 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1587 IOMMU_CACHE_LOCK(pDevIns, pThis);
1588 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1589 for (uint16_t i = 0; i < cIrteCache; i++)
1590 {
1591 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1592 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1593 {
1594 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1595 pIrteCache->Irte.u32 = 0;
1596 /* There could multiple IRTE entries for a device ID, continue searching. */
1597 }
1598 }
1599 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1600}
1601
1602
1603/**
1604 * Removes all IRTE cache entries.
1605 *
1606 * @param pDevIns The IOMMU instance data.
1607 */
1608static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1609{
1610 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1611 IOMMU_CACHE_LOCK(pDevIns, pThis);
1612 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1613 for (uint16_t i = 0; i < cIrteCache; i++)
1614 {
1615 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1616 pThis->aIrteCache[i].Irte.u32 = 0;
1617 }
1618 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1619}
1620# endif /* IN_RING3 */
1621#endif /* IOMMU_WITH_IRTE_CACHE */
1622
1623
1624/**
1625 * Atomically reads the control register without locking the IOMMU device.
1626 *
1627 * @returns The control register.
1628 * @param pThis The shared IOMMU device state.
1629 */
1630DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1631{
1632 IOMMU_CTRL_T Ctrl;
1633 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1634 return Ctrl;
1635}
1636
1637
1638/**
1639 * Returns whether MSI is enabled for the IOMMU.
1640 *
1641 * @returns Whether MSI is enabled.
1642 * @param pDevIns The IOMMU device instance.
1643 *
1644 * @note There should be a PCIDevXxx function for this.
1645 */
1646static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1647{
1648 MSI_CAP_HDR_T MsiCapHdr;
1649 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1650 return MsiCapHdr.n.u1MsiEnable;
1651}
1652
1653
1654/**
1655 * Signals a PCI target abort.
1656 *
1657 * @param pDevIns The IOMMU device instance.
1658 */
1659static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1660{
1661 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1662 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1663 PDMPciDevSetStatus(pPciDev, u16Status);
1664}
1665
1666
1667/**
1668 * Wakes up the command thread if there are commands to be processed.
1669 *
1670 * @param pDevIns The IOMMU device instance.
1671 *
1672 * @remarks The IOMMU lock must be held while calling this!
1673 */
1674static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1675{
1676 Log4Func(("\n"));
1677
1678 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1679 if ( pThis->Status.n.u1CmdBufRunning
1680 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1681 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1682 {
1683 Log4Func(("Signaling command thread\n"));
1684 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1685 }
1686}
1687
1688
1689/**
1690 * Reads the Device Table Base Address Register.
1691 */
1692static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1693{
1694 RT_NOREF(pDevIns, offReg);
1695 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1696 return VINF_SUCCESS;
1697}
1698
1699
1700/**
1701 * Reads the Command Buffer Base Address Register.
1702 */
1703static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1704{
1705 RT_NOREF(pDevIns, offReg);
1706 *pu64Value = pThis->CmdBufBaseAddr.u64;
1707 return VINF_SUCCESS;
1708}
1709
1710
1711/**
1712 * Reads the Event Log Base Address Register.
1713 */
1714static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1715{
1716 RT_NOREF(pDevIns, offReg);
1717 *pu64Value = pThis->EvtLogBaseAddr.u64;
1718 return VINF_SUCCESS;
1719}
1720
1721
1722/**
1723 * Reads the Control Register.
1724 */
1725static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1726{
1727 RT_NOREF(pDevIns, offReg);
1728 *pu64Value = pThis->Ctrl.u64;
1729 return VINF_SUCCESS;
1730}
1731
1732
1733/**
1734 * Reads the Exclusion Range Base Address Register.
1735 */
1736static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1737{
1738 RT_NOREF(pDevIns, offReg);
1739 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1740 return VINF_SUCCESS;
1741}
1742
1743
1744/**
1745 * Reads to the Exclusion Range Limit Register.
1746 */
1747static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1748{
1749 RT_NOREF(pDevIns, offReg);
1750 *pu64Value = pThis->ExclRangeLimit.u64;
1751 return VINF_SUCCESS;
1752}
1753
1754
1755/**
1756 * Reads to the Extended Feature Register.
1757 */
1758static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1759{
1760 RT_NOREF(pDevIns, offReg);
1761 *pu64Value = pThis->ExtFeat.u64;
1762 return VINF_SUCCESS;
1763}
1764
1765
1766/**
1767 * Reads to the PPR Log Base Address Register.
1768 */
1769static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1770{
1771 RT_NOREF(pDevIns, offReg);
1772 *pu64Value = pThis->PprLogBaseAddr.u64;
1773 return VINF_SUCCESS;
1774}
1775
1776
1777/**
1778 * Writes the Hardware Event Register (Hi).
1779 */
1780static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1781{
1782 RT_NOREF(pDevIns, offReg);
1783 *pu64Value = pThis->HwEvtHi.u64;
1784 return VINF_SUCCESS;
1785}
1786
1787
1788/**
1789 * Reads the Hardware Event Register (Lo).
1790 */
1791static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1792{
1793 RT_NOREF(pDevIns, offReg);
1794 *pu64Value = pThis->HwEvtLo;
1795 return VINF_SUCCESS;
1796}
1797
1798
1799/**
1800 * Reads the Hardware Event Status Register.
1801 */
1802static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1803{
1804 RT_NOREF(pDevIns, offReg);
1805 *pu64Value = pThis->HwEvtStatus.u64;
1806 return VINF_SUCCESS;
1807}
1808
1809
1810/**
1811 * Reads to the GA Log Base Address Register.
1812 */
1813static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1814{
1815 RT_NOREF(pDevIns, offReg);
1816 *pu64Value = pThis->GALogBaseAddr.u64;
1817 return VINF_SUCCESS;
1818}
1819
1820
1821/**
1822 * Reads to the PPR Log B Base Address Register.
1823 */
1824static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1825{
1826 RT_NOREF(pDevIns, offReg);
1827 *pu64Value = pThis->PprLogBBaseAddr.u64;
1828 return VINF_SUCCESS;
1829}
1830
1831
1832/**
1833 * Reads to the Event Log B Base Address Register.
1834 */
1835static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1836{
1837 RT_NOREF(pDevIns, offReg);
1838 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1839 return VINF_SUCCESS;
1840}
1841
1842
1843/**
1844 * Reads the Device Table Segment Base Address Register.
1845 */
1846static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1847{
1848 RT_NOREF(pDevIns);
1849
1850 /* Figure out which segment is being written. */
1851 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1852 uint8_t const idxSegment = offSegment + 1;
1853 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1854
1855 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1856 return VINF_SUCCESS;
1857}
1858
1859
1860/**
1861 * Reads the Device Specific Feature Extension (DSFX) Register.
1862 */
1863static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1864{
1865 RT_NOREF(pDevIns, offReg);
1866 *pu64Value = pThis->DevSpecificFeat.u64;
1867 return VINF_SUCCESS;
1868}
1869
1870/**
1871 * Reads the Device Specific Control Extension (DSCX) Register.
1872 */
1873static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1874{
1875 RT_NOREF(pDevIns, offReg);
1876 *pu64Value = pThis->DevSpecificCtrl.u64;
1877 return VINF_SUCCESS;
1878}
1879
1880
1881/**
1882 * Reads the Device Specific Status Extension (DSSX) Register.
1883 */
1884static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1885{
1886 RT_NOREF(pDevIns, offReg);
1887 *pu64Value = pThis->DevSpecificStatus.u64;
1888 return VINF_SUCCESS;
1889}
1890
1891
1892/**
1893 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1894 */
1895static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1896{
1897 RT_NOREF(pDevIns, offReg);
1898 uint32_t const uLo = pThis->MiscInfo.au32[0];
1899 uint32_t const uHi = pThis->MiscInfo.au32[1];
1900 *pu64Value = RT_MAKE_U64(uLo, uHi);
1901 return VINF_SUCCESS;
1902}
1903
1904
1905/**
1906 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1907 * Register (32-bit).
1908 */
1909static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1910{
1911 RT_NOREF(pThis, offReg);
1912 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1913 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1914 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1915 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1916 *pu64Value = RT_MAKE_U64(uLo, uHi);
1917 return VINF_SUCCESS;
1918}
1919
1920
1921/**
1922 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1923 */
1924static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1925{
1926 RT_NOREF(pThis, offReg);
1927 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1928 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1929 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1930 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1931 *pu64Value = RT_MAKE_U64(uLo, uHi);
1932 return VINF_SUCCESS;
1933}
1934
1935
1936/**
1937 * Reads the Command Buffer Head Pointer Register.
1938 */
1939static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1940{
1941 RT_NOREF(pDevIns, offReg);
1942 *pu64Value = pThis->CmdBufHeadPtr.u64;
1943 return VINF_SUCCESS;
1944}
1945
1946
1947/**
1948 * Reads the Command Buffer Tail Pointer Register.
1949 */
1950static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1951{
1952 RT_NOREF(pDevIns, offReg);
1953 *pu64Value = pThis->CmdBufTailPtr.u64;
1954 return VINF_SUCCESS;
1955}
1956
1957
1958/**
1959 * Reads the Event Log Head Pointer Register.
1960 */
1961static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1962{
1963 RT_NOREF(pDevIns, offReg);
1964 *pu64Value = pThis->EvtLogHeadPtr.u64;
1965 return VINF_SUCCESS;
1966}
1967
1968
1969/**
1970 * Reads the Event Log Tail Pointer Register.
1971 */
1972static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1973{
1974 RT_NOREF(pDevIns, offReg);
1975 *pu64Value = pThis->EvtLogTailPtr.u64;
1976 return VINF_SUCCESS;
1977}
1978
1979
1980/**
1981 * Reads the Status Register.
1982 */
1983static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1984{
1985 RT_NOREF(pDevIns, offReg);
1986 *pu64Value = pThis->Status.u64;
1987 return VINF_SUCCESS;
1988}
1989
1990
1991/**
1992 * Writes the Device Table Base Address Register.
1993 */
1994static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
1995{
1996 RT_NOREF(pDevIns, offReg);
1997
1998 /* Mask out all unrecognized bits. */
1999 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2000
2001 /* Update the register. */
2002 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2003
2004 /* Paranoia. */
2005 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
2006 return VINF_SUCCESS;
2007}
2008
2009
2010/**
2011 * Writes the Command Buffer Base Address Register.
2012 */
2013static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2014{
2015 RT_NOREF(pDevIns, offReg);
2016
2017 /*
2018 * While this is not explicitly specified like the event log base address register,
2019 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2020 * Inconsistent specs :/
2021 */
2022 if (pThis->Status.n.u1CmdBufRunning)
2023 {
2024 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2025 return VINF_SUCCESS;
2026 }
2027
2028 /* Mask out all unrecognized bits. */
2029 CMD_BUF_BAR_T CmdBufBaseAddr;
2030 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2031
2032 /* Validate the length. */
2033 if (CmdBufBaseAddr.n.u4Len >= 8)
2034 {
2035 /* Update the register. */
2036 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2037
2038 /*
2039 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2040 * See AMD IOMMU spec. 2.4 "Commands".
2041 */
2042 pThis->CmdBufHeadPtr.u64 = 0;
2043 pThis->CmdBufTailPtr.u64 = 0;
2044 }
2045 else
2046 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2047
2048 return VINF_SUCCESS;
2049}
2050
2051
2052/**
2053 * Writes the Event Log Base Address Register.
2054 */
2055static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2056{
2057 RT_NOREF(pDevIns, offReg);
2058
2059 /*
2060 * IOMMU behavior is undefined when software writes this register when event logging is running.
2061 * In our emulation, we ignore the write entirely.
2062 * See AMD IOMMU spec. "Event Log Base Address Register".
2063 */
2064 if (pThis->Status.n.u1EvtLogRunning)
2065 {
2066 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2067 return VINF_SUCCESS;
2068 }
2069
2070 /* Mask out all unrecognized bits. */
2071 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2072 EVT_LOG_BAR_T EvtLogBaseAddr;
2073 EvtLogBaseAddr.u64 = u64Value;
2074
2075 /* Validate the length. */
2076 if (EvtLogBaseAddr.n.u4Len >= 8)
2077 {
2078 /* Update the register. */
2079 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2080
2081 /*
2082 * Writing the event log base address, clears the event log head and tail pointers.
2083 * See AMD IOMMU spec. 2.5 "Event Logging".
2084 */
2085 pThis->EvtLogHeadPtr.u64 = 0;
2086 pThis->EvtLogTailPtr.u64 = 0;
2087 }
2088 else
2089 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2090
2091 return VINF_SUCCESS;
2092}
2093
2094
2095/**
2096 * Writes the Control Register.
2097 */
2098static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2099{
2100 RT_NOREF(pDevIns, offReg);
2101
2102 /* Mask out all unrecognized bits. */
2103 u64Value &= IOMMU_CTRL_VALID_MASK;
2104 IOMMU_CTRL_T NewCtrl;
2105 NewCtrl.u64 = u64Value;
2106
2107 /* Ensure the device table segments are within limits. */
2108 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2109 {
2110 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2111
2112 /* Update the register. */
2113 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2114
2115 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2116 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2117
2118 /* Enable or disable event logging when the bit transitions. */
2119 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2120 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2121 if ( fOldEvtLogEn != fNewEvtLogEn
2122 || fOldIommuEn != fNewIommuEn)
2123 {
2124 if ( fNewIommuEn
2125 && fNewEvtLogEn)
2126 {
2127 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2128 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2129 }
2130 else
2131 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2132 }
2133
2134 /* Enable or disable command buffer processing when the bit transitions. */
2135 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2136 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2137 if ( fOldCmdBufEn != fNewCmdBufEn
2138 || fOldIommuEn != fNewIommuEn)
2139 {
2140 if ( fNewCmdBufEn
2141 && fNewIommuEn)
2142 {
2143 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2144 LogFunc(("Command buffer enabled\n"));
2145
2146 /* Wake up the command thread to start processing commands if any. */
2147 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2148 }
2149 else
2150 {
2151 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2152 LogFunc(("Command buffer disabled\n"));
2153 }
2154 }
2155 }
2156 else
2157 {
2158 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2159 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2160 }
2161
2162 return VINF_SUCCESS;
2163}
2164
2165
2166/**
2167 * Writes to the Exclusion Range Base Address Register.
2168 */
2169static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2170{
2171 RT_NOREF(pDevIns, offReg);
2172 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2173 return VINF_SUCCESS;
2174}
2175
2176
2177/**
2178 * Writes to the Exclusion Range Limit Register.
2179 */
2180static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2181{
2182 RT_NOREF(pDevIns, offReg);
2183 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2184 u64Value |= UINT64_C(0xfff);
2185 pThis->ExclRangeLimit.u64 = u64Value;
2186 return VINF_SUCCESS;
2187}
2188
2189
2190/**
2191 * Writes the Hardware Event Register (Hi).
2192 */
2193static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2194{
2195 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2196 RT_NOREF(pDevIns, offReg);
2197 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2198 pThis->HwEvtHi.u64 = u64Value;
2199 return VINF_SUCCESS;
2200}
2201
2202
2203/**
2204 * Writes the Hardware Event Register (Lo).
2205 */
2206static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2207{
2208 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2209 RT_NOREF(pDevIns, offReg);
2210 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2211 pThis->HwEvtLo = u64Value;
2212 return VINF_SUCCESS;
2213}
2214
2215
2216/**
2217 * Writes the Hardware Event Status Register.
2218 */
2219static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2220{
2221 RT_NOREF(pDevIns, offReg);
2222
2223 /* Mask out all unrecognized bits. */
2224 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2225
2226 /*
2227 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2228 * If the current status bits or the bits being written are both 0, we've nothing to do.
2229 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2230 */
2231 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2232 if (!(HwStatus & RT_BIT(0)))
2233 return VINF_SUCCESS;
2234 if (u64Value & HwStatus & RT_BIT_64(0))
2235 HwStatus &= ~RT_BIT_64(0);
2236 if (u64Value & HwStatus & RT_BIT_64(1))
2237 HwStatus &= ~RT_BIT_64(1);
2238
2239 /* Update the register. */
2240 pThis->HwEvtStatus.u64 = HwStatus;
2241 return VINF_SUCCESS;
2242}
2243
2244
2245/**
2246 * Writes the Device Table Segment Base Address Register.
2247 */
2248static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2249{
2250 RT_NOREF(pDevIns);
2251
2252 /* Figure out which segment is being written. */
2253 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2254 uint8_t const idxSegment = offSegment + 1;
2255 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2256
2257 /* Mask out all unrecognized bits. */
2258 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2259 DEV_TAB_BAR_T DevTabSegBar;
2260 DevTabSegBar.u64 = u64Value;
2261
2262 /* Validate the size. */
2263 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2264 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2265 if (uSegSize <= uMaxSegSize)
2266 {
2267 /* Update the register. */
2268 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2269 }
2270 else
2271 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2272
2273 return VINF_SUCCESS;
2274}
2275
2276
2277/**
2278 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2279 */
2280static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2281{
2282 RT_NOREF(pDevIns, offReg);
2283
2284 /* MSI Vector Register 0 is read-only. */
2285 /* MSI Vector Register 1. */
2286 uint32_t const uReg = u64Value >> 32;
2287 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2288 return VINF_SUCCESS;
2289}
2290
2291
2292/**
2293 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2294 * Register (32-bit).
2295 */
2296static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2297{
2298 RT_NOREF(pThis, offReg);
2299 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2300 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2301
2302 /* MSI capability header. */
2303 {
2304 uint32_t const uReg = u64Value;
2305 MSI_CAP_HDR_T MsiCapHdr;
2306 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2307 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2308 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2309 }
2310
2311 /* MSI Address Lo. */
2312 {
2313 uint32_t const uReg = u64Value >> 32;
2314 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2315 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2316 }
2317
2318 return VINF_SUCCESS;
2319}
2320
2321
2322/**
2323 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2324 */
2325static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2326{
2327 RT_NOREF(pThis, offReg);
2328 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2329 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2330
2331 /* MSI Address Hi. */
2332 {
2333 uint32_t const uReg = u64Value;
2334 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2335 }
2336
2337 /* MSI Data. */
2338 {
2339 uint32_t const uReg = u64Value >> 32;
2340 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2341 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2342 }
2343
2344 return VINF_SUCCESS;
2345}
2346
2347
2348/**
2349 * Writes the Command Buffer Head Pointer Register.
2350 */
2351static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2352{
2353 RT_NOREF(pDevIns, offReg);
2354
2355 /*
2356 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2357 * In our emulation, we ignore the write entirely.
2358 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2359 */
2360 if (pThis->Status.n.u1CmdBufRunning)
2361 {
2362 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2363 return VINF_SUCCESS;
2364 }
2365
2366 /*
2367 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2368 * In our emulation, we ignore the write entirely.
2369 */
2370 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2371 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2372 Assert(cbBuf <= _512K);
2373 if (offBuf >= cbBuf)
2374 {
2375 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2376 return VINF_SUCCESS;
2377 }
2378
2379 /* Update the register. */
2380 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2381
2382 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2383
2384 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2385 return VINF_SUCCESS;
2386}
2387
2388
2389/**
2390 * Writes the Command Buffer Tail Pointer Register.
2391 */
2392static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2393{
2394 RT_NOREF(pDevIns, offReg);
2395
2396 /*
2397 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2398 * In our emulation, we ignore the write entirely.
2399 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2400 */
2401 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2402 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2403 Assert(cbBuf <= _512K);
2404 if (offBuf >= cbBuf)
2405 {
2406 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2407 return VINF_SUCCESS;
2408 }
2409
2410 /*
2411 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2412 * head pointer after adding one or more commands to the buffer.
2413 *
2414 * However, we cannot enforce this strictly because it's legal for software to shrink the
2415 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2416 * at 0). Software might even make the queue empty by making head and tail equal which is
2417 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2418 * in the foot here. As long as we make sure the offset value is within the circular buffer
2419 * bounds (which we do by masking bits above) it should be sufficient.
2420 */
2421 pThis->CmdBufTailPtr.au32[0] = offBuf;
2422
2423 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2424
2425 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2426 return VINF_SUCCESS;
2427}
2428
2429
2430/**
2431 * Writes the Event Log Head Pointer Register.
2432 */
2433static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2434{
2435 RT_NOREF(pDevIns, offReg);
2436
2437 /*
2438 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2439 * In our emulation, we ignore the write entirely.
2440 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2441 */
2442 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2443 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2444 Assert(cbBuf <= _512K);
2445 if (offBuf >= cbBuf)
2446 {
2447 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2448 return VINF_SUCCESS;
2449 }
2450
2451 /* Update the register. */
2452 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2453
2454 LogFlowFunc(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2455 return VINF_SUCCESS;
2456}
2457
2458
2459/**
2460 * Writes the Event Log Tail Pointer Register.
2461 */
2462static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2463{
2464 RT_NOREF(pDevIns, offReg);
2465 NOREF(pThis);
2466
2467 /*
2468 * IOMMU behavior is undefined when software writes this register when the event log is running.
2469 * In our emulation, we ignore the write entirely.
2470 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2471 */
2472 if (pThis->Status.n.u1EvtLogRunning)
2473 {
2474 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2475 return VINF_SUCCESS;
2476 }
2477
2478 /*
2479 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2480 * In our emulation, we ignore the write entirely.
2481 */
2482 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2483 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2484 Assert(cbBuf <= _512K);
2485 if (offBuf >= cbBuf)
2486 {
2487 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2488 return VINF_SUCCESS;
2489 }
2490
2491 /* Update the register. */
2492 pThis->EvtLogTailPtr.au32[0] = offBuf;
2493
2494 LogFlowFunc(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2495 return VINF_SUCCESS;
2496}
2497
2498
2499/**
2500 * Writes the Status Register.
2501 */
2502static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2503{
2504 RT_NOREF(pDevIns, offReg);
2505
2506 /* Mask out all unrecognized bits. */
2507 u64Value &= IOMMU_STATUS_VALID_MASK;
2508
2509 /*
2510 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2511 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2512 */
2513 IOMMU_STATUS_T const OldStatus = pThis->Status;
2514 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2515 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2516 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2517
2518 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2519
2520 /* Update the register. */
2521 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2522 return VINF_SUCCESS;
2523}
2524
2525
2526/**
2527 * Register access table 0.
2528 * The MMIO offset of each entry must be a multiple of 8!
2529 */
2530static const IOMMUREGACC g_aRegAccess0[] =
2531{
2532 /* MMIO off. Register name Read function Write function */
2533 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2534 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2535 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2536 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2537 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2538 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2539 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2540 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2541 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2542 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2543 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2544 { /* 0x58 */ NULL, NULL, NULL },
2545
2546 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2547 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2548 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2549 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2550 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2551 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2552 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2553 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2554 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2555 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2556 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2557 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2558 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2559 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2560 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2561 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2562
2563 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2564 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2565 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2566 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2567
2568 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2569 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2570 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2571 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2572 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2573 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2574 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2575
2576 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2577 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2578 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2579
2580 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2581 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2582 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2583 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2584
2585 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2586 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2587 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2588};
2589AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2590
2591/**
2592 * Register access table 1.
2593 * The MMIO offset of each entry must be a multiple of 8!
2594 */
2595static const IOMMUREGACC g_aRegAccess1[] =
2596{
2597 /* MMIO offset Register name Read function Write function */
2598 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2599 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2600 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2601 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2602 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2603 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2604 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2605 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2606 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2607 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2608 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2609 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2610};
2611AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2612
2613/**
2614 * Register access table 2.
2615 * The MMIO offset of each entry must be a multiple of 8!
2616 */
2617static const IOMMUREGACC g_aRegAccess2[] =
2618{
2619 /* MMIO offset Register name Read Function Write function */
2620 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2621
2622 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2623 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2624 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2625 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2626
2627 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2628 { /* 0x2028 */ NULL, NULL, NULL },
2629
2630 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2631 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2632
2633 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2634 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2635
2636 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2637 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2638
2639 { /* 0x2060 */ NULL, NULL, NULL },
2640 { /* 0x2068 */ NULL, NULL, NULL },
2641
2642 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2643 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2644
2645 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2646 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2647 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2648};
2649AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2650
2651
2652/**
2653 * Gets the register access structure given its MMIO offset.
2654 *
2655 * @returns The register access structure, or NULL if the offset is invalid.
2656 * @param off The MMIO offset of the register being accessed.
2657 */
2658static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2659{
2660 /* Figure out which table the register belongs to and validate its index. */
2661 PCIOMMUREGACC pReg;
2662 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2663 {
2664 uint32_t const idxReg = off >> 3;
2665 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2666 pReg = &g_aRegAccess0[idxReg];
2667 }
2668 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2669 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2670 {
2671 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2672 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2673 pReg = &g_aRegAccess1[idxReg];
2674 }
2675 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2676 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2677 {
2678 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2679 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2680 pReg = &g_aRegAccess2[idxReg];
2681 }
2682 else
2683 pReg = NULL;
2684 return pReg;
2685}
2686
2687
2688/**
2689 * Writes an IOMMU register (32-bit and 64-bit).
2690 *
2691 * @returns Strict VBox status code.
2692 * @param pDevIns The IOMMU device instance.
2693 * @param off MMIO byte offset to the register.
2694 * @param cb The size of the write access.
2695 * @param uValue The value being written.
2696 *
2697 * @thread EMT.
2698 */
2699static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2700{
2701 /*
2702 * Validate the access in case of IOM bug or incorrect assumption.
2703 */
2704 Assert(off < IOMMU_MMIO_REGION_SIZE);
2705 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2706 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2707
2708 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2709
2710 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2711 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2712 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2713 if (pReg)
2714 { /* likely */ }
2715 else
2716 {
2717 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2718 return VINF_SUCCESS;
2719 }
2720
2721 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2722 if (pReg->pfnWrite)
2723 { /* likely */ }
2724 else
2725 {
2726 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2727 return VINF_SUCCESS;
2728 }
2729
2730 /*
2731 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2732 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2733 * consecutive 32-bit registers.
2734 */
2735 if (cb == 8)
2736 {
2737 if (!(off & 7))
2738 {
2739 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2740 VBOXSTRICTRC rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2741 IOMMU_UNLOCK(pDevIns, pThisCC);
2742 return rcStrict;
2743 }
2744
2745 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2746 return VINF_SUCCESS;
2747 }
2748
2749 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2750 Assert(cb == 4);
2751 if (!(off & 7))
2752 {
2753 VBOXSTRICTRC rcStrict;
2754 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2755
2756 /*
2757 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2758 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2759 */
2760 uint64_t u64Read;
2761 if (pReg->pfnRead)
2762 rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2763 else
2764 {
2765 rcStrict = VINF_SUCCESS;
2766 u64Read = 0;
2767 }
2768
2769 if (RT_SUCCESS(rcStrict))
2770 {
2771 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2772 rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2773 }
2774 else
2775 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2776
2777 IOMMU_UNLOCK(pDevIns, pThisCC);
2778 return rcStrict;
2779 }
2780
2781 /*
2782 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2783 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2784 */
2785 VBOXSTRICTRC rcStrict;
2786 Assert(!(off & 3));
2787 Assert(off & 7);
2788 Assert(off >= 4);
2789 uint64_t u64Read;
2790 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2791 if (pReg->pfnRead)
2792 rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2793 else
2794 {
2795 rcStrict = VINF_SUCCESS;
2796 u64Read = 0;
2797 }
2798
2799 if (RT_SUCCESS(rcStrict))
2800 {
2801 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2802 rcStrict = pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2803 }
2804 else
2805 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2806
2807 IOMMU_UNLOCK(pDevIns, pThisCC);
2808 return rcStrict;
2809}
2810
2811
2812/**
2813 * Reads an IOMMU register (64-bit) given its MMIO offset.
2814 *
2815 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2816 * boundary include the lower half of the subsequent register.
2817 *
2818 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2819 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2820 * software will only perform 32-bit reads on those 32-bit registers that are
2821 * aligned on 8-byte boundaries.
2822 *
2823 * @returns Strict VBox status code.
2824 * @param pDevIns The IOMMU device instance.
2825 * @param off The MMIO offset of the register in bytes.
2826 * @param puResult Where to store the value being read.
2827 *
2828 * @thread EMT.
2829 */
2830static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2831{
2832 Assert(off < IOMMU_MMIO_REGION_SIZE);
2833 Assert(!(off & 7) || !(off & 3));
2834
2835 Log4Func(("off=%#x\n", off));
2836
2837 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2838 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2839 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2840 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2841
2842 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2843 if (pReg)
2844 { /* likely */ }
2845 else
2846 {
2847 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2848 return VINF_IOM_MMIO_UNUSED_FF;
2849 }
2850
2851 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2852 if (pReg->pfnRead)
2853 { /* likely */ }
2854 else
2855 {
2856 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2857 return VINF_IOM_MMIO_UNUSED_00;
2858 }
2859
2860 /*
2861 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2862 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2863 */
2864 if (!(off & 7))
2865 {
2866 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2867 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, puResult);
2868 IOMMU_UNLOCK(pDevIns, pThisCC);
2869 return rcStrict;
2870 }
2871
2872 /*
2873 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2874 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2875 */
2876 Assert(!(off & 3));
2877 Assert(off & 7);
2878 Assert(off >= 4);
2879 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2880 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2881 IOMMU_UNLOCK(pDevIns, pThisCC);
2882 if (RT_SUCCESS(rcStrict))
2883 *puResult >>= 32;
2884 else
2885 {
2886 *puResult = 0;
2887 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2888 }
2889
2890 return rcStrict;
2891}
2892
2893
2894/**
2895 * Raises the MSI interrupt for the IOMMU device.
2896 *
2897 * @param pDevIns The IOMMU device instance.
2898 *
2899 * @thread Any.
2900 * @remarks The IOMMU lock may or may not be held.
2901 */
2902static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2903{
2904 LogFlowFunc(("\n"));
2905 if (iommuAmdIsMsiEnabled(pDevIns))
2906 {
2907 LogFunc(("Raising MSI\n"));
2908 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2909 }
2910}
2911
2912#if 0
2913/**
2914 * Clears the MSI interrupt for the IOMMU device.
2915 *
2916 * @param pDevIns The IOMMU device instance.
2917 *
2918 * @thread Any.
2919 * @remarks The IOMMU lock may or may not be held.
2920 */
2921static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2922{
2923 if (iommuAmdIsMsiEnabled(pDevIns))
2924 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2925}
2926#endif
2927
2928/**
2929 * Writes an entry to the event log in memory.
2930 *
2931 * @returns VBox status code.
2932 * @param pDevIns The IOMMU device instance.
2933 * @param pEvent The event to log.
2934 *
2935 * @thread Any.
2936 * @remarks The IOMMU lock must be held while calling this function.
2937 */
2938static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2939{
2940 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2941 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2942
2943 IOMMU_LOCK(pDevIns, pThisCC);
2944
2945 /* Check if event logging is active and the log has not overflowed. */
2946 IOMMU_STATUS_T const Status = pThis->Status;
2947 if ( Status.n.u1EvtLogRunning
2948 && !Status.n.u1EvtOverflow)
2949 {
2950 uint32_t const cbEvt = sizeof(*pEvent);
2951
2952 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2953 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2954 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2955
2956 /* Ensure we have space in the event log. */
2957 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2958 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2959 if (cEvts + 1 < cMaxEvts)
2960 {
2961 /* Write the event log entry to memory. */
2962 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2963 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2964 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2965 if (RT_FAILURE(rc))
2966 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2967
2968 /* Increment the event log tail pointer. */
2969 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2970 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
2971
2972 /* Indicate that an event log entry was written. */
2973 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
2974
2975 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
2976 if (pThis->Ctrl.n.u1EvtIntrEn)
2977 iommuAmdMsiInterruptRaise(pDevIns);
2978 }
2979 else
2980 {
2981 /* Indicate that the event log has overflowed. */
2982 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
2983
2984 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
2985 if (pThis->Ctrl.n.u1EvtIntrEn)
2986 iommuAmdMsiInterruptRaise(pDevIns);
2987 }
2988 }
2989
2990 IOMMU_UNLOCK(pDevIns, pThisCC);
2991
2992 return VINF_SUCCESS;
2993}
2994
2995
2996/**
2997 * Sets an event in the hardware error registers.
2998 *
2999 * @param pDevIns The IOMMU device instance.
3000 * @param pEvent The event.
3001 *
3002 * @thread Any.
3003 */
3004static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3005{
3006 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3007 if (pThis->ExtFeat.n.u1HwErrorSup)
3008 {
3009 if (pThis->HwEvtStatus.n.u1Valid)
3010 pThis->HwEvtStatus.n.u1Overflow = 1;
3011 pThis->HwEvtStatus.n.u1Valid = 1;
3012 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3013 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3014 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
3015 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
3016 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3017 }
3018}
3019
3020
3021/**
3022 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
3023 *
3024 * @param idDevice The device ID (bus, device, function).
3025 * @param idDomain The domain ID.
3026 * @param GCPhysPtEntity The system physical address of the page table
3027 * entity.
3028 * @param enmOp The IOMMU operation being performed.
3029 * @param pEvtPageTabHwErr Where to store the initialized event.
3030 */
3031static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3032 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3033{
3034 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3035 pEvtPageTabHwErr->n.u16DevId = idDevice;
3036 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3037 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3038 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3039 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3040 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3041 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3042 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3043 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3044}
3045
3046
3047/**
3048 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3049 *
3050 * @param pDevIns The IOMMU device instance.
3051 * @param enmOp The IOMMU operation being performed.
3052 * @param pEvtPageTabHwErr The page table hardware error event.
3053 *
3054 * @thread Any.
3055 */
3056static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3057{
3058 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3059 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3060
3061 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3062 IOMMU_LOCK(pDevIns, pThisCC);
3063
3064 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3065 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3066 if (enmOp != IOMMUOP_CMD)
3067 iommuAmdSetPciTargetAbort(pDevIns);
3068
3069 IOMMU_UNLOCK(pDevIns, pThisCC);
3070
3071 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3072 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3073 pEvtPageTabHwErr->n.u2Type));
3074}
3075
3076
3077#ifdef IN_RING3
3078/**
3079 * Initializes a COMMAND_HARDWARE_ERROR event.
3080 *
3081 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3082 * @param pEvtCmdHwErr Where to store the initialized event.
3083 */
3084static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3085{
3086 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3087 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3088 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3089 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3090}
3091
3092
3093/**
3094 * Raises a COMMAND_HARDWARE_ERROR event.
3095 *
3096 * @param pDevIns The IOMMU device instance.
3097 * @param pEvtCmdHwErr The command hardware error event.
3098 *
3099 * @thread Any.
3100 */
3101static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3102{
3103 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3104 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3105 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3106
3107 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3108 IOMMU_LOCK(pDevIns, pThisCC);
3109
3110 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3111 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3112 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3113
3114 IOMMU_UNLOCK(pDevIns, pThisCC);
3115
3116 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3117}
3118#endif /* IN_RING3 */
3119
3120
3121/**
3122 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3123 *
3124 * @param idDevice The device ID (bus, device, function).
3125 * @param GCPhysDte The system physical address of the failed device table
3126 * access.
3127 * @param enmOp The IOMMU operation being performed.
3128 * @param pEvtDevTabHwErr Where to store the initialized event.
3129 */
3130static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3131 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3132{
3133 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3134 pEvtDevTabHwErr->n.u16DevId = idDevice;
3135 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3136 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3137 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3138 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3139 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3140 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3141 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3142}
3143
3144
3145/**
3146 * Raises a DEV_TAB_HARDWARE_ERROR event.
3147 *
3148 * @param pDevIns The IOMMU device instance.
3149 * @param enmOp The IOMMU operation being performed.
3150 * @param pEvtDevTabHwErr The device table hardware error event.
3151 *
3152 * @thread Any.
3153 */
3154static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3155{
3156 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3157 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3158
3159 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3160 IOMMU_LOCK(pDevIns, pThisCC);
3161
3162 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3163 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3164 if (enmOp != IOMMUOP_CMD)
3165 iommuAmdSetPciTargetAbort(pDevIns);
3166
3167 IOMMU_UNLOCK(pDevIns, pThisCC);
3168
3169 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3170 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3171}
3172
3173
3174#ifdef IN_RING3
3175/**
3176 * Initializes an ILLEGAL_COMMAND_ERROR event.
3177 *
3178 * @param GCPhysCmd The system physical address of the failed command
3179 * access.
3180 * @param pEvtIllegalCmd Where to store the initialized event.
3181 */
3182static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3183{
3184 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3185 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3186 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3187 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3188}
3189
3190
3191/**
3192 * Raises an ILLEGAL_COMMAND_ERROR event.
3193 *
3194 * @param pDevIns The IOMMU device instance.
3195 * @param pEvtIllegalCmd The illegal command error event.
3196 */
3197static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3198{
3199 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3200 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3201 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3202
3203 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3204 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3205
3206 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3207}
3208#endif /* IN_RING3 */
3209
3210
3211/**
3212 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3213 *
3214 * @param idDevice The device ID (bus, device, function).
3215 * @param uIova The I/O virtual address.
3216 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3217 * event was caused by an invalid level encoding in the
3218 * DTE.
3219 * @param enmOp The IOMMU operation being performed.
3220 * @param pEvtIllegalDte Where to store the initialized event.
3221 */
3222static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3223 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3224{
3225 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3226 pEvtIllegalDte->n.u16DevId = idDevice;
3227 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3228 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3229 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3230 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3231 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3232 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3233 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3234 * IOMMU spec here but not for this field for I/O page fault event. */
3235 Assert(!(uIova & UINT64_C(0x3)));
3236}
3237
3238
3239/**
3240 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3241 *
3242 * @param pDevIns The IOMMU instance data.
3243 * @param enmOp The IOMMU operation being performed.
3244 * @param pEvtIllegalDte The illegal device table entry event.
3245 * @param enmEvtType The illegal device table entry event type.
3246 *
3247 * @thread Any.
3248 */
3249static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3250 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3251{
3252 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3253 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3254
3255 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3256 if (enmOp != IOMMUOP_CMD)
3257 iommuAmdSetPciTargetAbort(pDevIns);
3258
3259 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3260 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3261 NOREF(enmEvtType);
3262}
3263
3264
3265/**
3266 * Initializes an IO_PAGE_FAULT event.
3267 *
3268 * @param idDevice The device ID (bus, device, function).
3269 * @param idDomain The domain ID.
3270 * @param uIova The I/O virtual address being accessed.
3271 * @param fPresent Transaction to a page marked as present (including
3272 * DTE.V=1) or interrupt marked as remapped
3273 * (IRTE.RemapEn=1).
3274 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3275 * the I/O page fault was caused by invalid level
3276 * encoding.
3277 * @param fPermDenied Permission denied for the address being accessed.
3278 * @param enmOp The IOMMU operation being performed.
3279 * @param pEvtIoPageFault Where to store the initialized event.
3280 */
3281static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3282 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3283{
3284 Assert(!fPermDenied || fPresent);
3285 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3286 pEvtIoPageFault->n.u16DevId = idDevice;
3287 //pEvtIoPageFault->n.u4PasidHi = 0;
3288 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3289 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3290 //pEvtIoPageFault->n.u1NoExecute = 0;
3291 //pEvtIoPageFault->n.u1User = 0;
3292 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3293 pEvtIoPageFault->n.u1Present = fPresent;
3294 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3295 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3296 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3297 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3298 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3299 pEvtIoPageFault->n.u64Addr = uIova;
3300}
3301
3302
3303/**
3304 * Raises an IO_PAGE_FAULT event.
3305 *
3306 * @param pDevIns The IOMMU instance data.
3307 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3308 * @param pIrte The interrupt remapping table entry, can be NULL.
3309 * @param enmOp The IOMMU operation being performed.
3310 * @param pEvtIoPageFault The I/O page fault event.
3311 * @param enmEvtType The I/O page fault event type.
3312 *
3313 * @thread Any.
3314 */
3315static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3316 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3317{
3318 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3319 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3320
3321#ifdef IOMMU_WITH_DTE_CACHE
3322# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheAddFlags((a_pDevIns), (a_DevId), \
3323 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED)
3324#else
3325# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3326#endif
3327
3328 bool fSuppressEvtLogging = false;
3329 if ( enmOp == IOMMUOP_MEM_READ
3330 || enmOp == IOMMUOP_MEM_WRITE)
3331 {
3332 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3333 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3334 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3335 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3336 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3337 {
3338 fSuppressEvtLogging = true;
3339 }
3340 }
3341 else if (enmOp == IOMMUOP_INTR_REQ)
3342 {
3343 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3344 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3345 fSuppressEvtLogging = true;
3346 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3347 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3348 }
3349 /* else: Events are never suppressed for commands. */
3350
3351 switch (enmEvtType)
3352 {
3353 case kIoPageFaultType_PermDenied:
3354 {
3355 /* Cannot be triggered by a command. */
3356 Assert(enmOp != IOMMUOP_CMD);
3357 RT_FALL_THRU();
3358 }
3359 case kIoPageFaultType_DteRsvdPagingMode:
3360 case kIoPageFaultType_PteInvalidPageSize:
3361 case kIoPageFaultType_PteInvalidLvlEncoding:
3362 case kIoPageFaultType_SkippedLevelIovaNotZero:
3363 case kIoPageFaultType_PteRsvdNotZero:
3364 case kIoPageFaultType_PteValidNotSet:
3365 case kIoPageFaultType_DteTranslationDisabled:
3366 case kIoPageFaultType_PasidInvalidRange:
3367 {
3368 /*
3369 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3370 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3371 */
3372 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3373 {
3374 if (!fSuppressEvtLogging)
3375 {
3376 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3377 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3378 }
3379 if (enmOp != IOMMUOP_CMD)
3380 iommuAmdSetPciTargetAbort(pDevIns);
3381 }
3382 break;
3383 }
3384
3385 case kIoPageFaultType_UserSupervisor:
3386 {
3387 /* Access is blocked and only creates an event log entry. */
3388 if (!fSuppressEvtLogging)
3389 {
3390 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3391 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3392 }
3393 break;
3394 }
3395
3396 case kIoPageFaultType_IrteAddrInvalid:
3397 case kIoPageFaultType_IrteRsvdNotZero:
3398 case kIoPageFaultType_IrteRemapEn:
3399 case kIoPageFaultType_IrteRsvdIntType:
3400 case kIoPageFaultType_IntrReqAborted:
3401 case kIoPageFaultType_IntrWithPasid:
3402 {
3403 /* Only trigerred by interrupt requests. */
3404 Assert(enmOp == IOMMUOP_INTR_REQ);
3405 if (!fSuppressEvtLogging)
3406 {
3407 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3408 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3409 }
3410 iommuAmdSetPciTargetAbort(pDevIns);
3411 break;
3412 }
3413
3414 case kIoPageFaultType_SmiFilterMismatch:
3415 {
3416 /* Not supported and probably will never be, assert. */
3417 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3418 break;
3419 }
3420
3421 case kIoPageFaultType_DevId_Invalid:
3422 {
3423 /* Cannot be triggered by a command. */
3424 Assert(enmOp != IOMMUOP_CMD);
3425 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3426 if (!fSuppressEvtLogging)
3427 {
3428 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3429 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3430 }
3431 if ( enmOp == IOMMUOP_MEM_READ
3432 || enmOp == IOMMUOP_MEM_WRITE)
3433 iommuAmdSetPciTargetAbort(pDevIns);
3434 break;
3435 }
3436 }
3437
3438#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3439}
3440
3441
3442/**
3443 * Raises an IO_PAGE_FAULT event given the DTE.
3444 *
3445 * @param pDevIns The IOMMU instance data.
3446 * @param pDte The device table entry.
3447 * @param pIrte The interrupt remapping table entry, can be NULL.
3448 * @param enmOp The IOMMU operation being performed.
3449 * @param pEvtIoPageFault The I/O page fault event.
3450 * @param enmEvtType The I/O page fault event type.
3451 *
3452 * @thread Any.
3453 */
3454static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3455 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3456{
3457 Assert(pDte);
3458 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3459 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3460}
3461
3462
3463/**
3464 * Reads a device table entry for the given the device ID.
3465 *
3466 * @returns VBox status code.
3467 * @param pDevIns The IOMMU device instance.
3468 * @param idDevice The device ID (bus, device, function).
3469 * @param enmOp The IOMMU operation being performed.
3470 * @param pDte Where to store the device table entry.
3471 *
3472 * @thread Any.
3473 */
3474static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3475{
3476 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3477 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3478
3479 IOMMU_LOCK(pDevIns, pThisCC);
3480
3481 /* Figure out which device table segment is being accessed. */
3482 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3483 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3484
3485 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3486 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3487 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3488
3489 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3490 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3491 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3492
3493 /* Ensure the DTE falls completely within the device table segment. */
3494 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3495
3496 IOMMU_UNLOCK(pDevIns, pThisCC);
3497
3498 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3499 {
3500 /* Read the device table entry from guest memory. */
3501 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3502 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3503 if (RT_SUCCESS(rc))
3504 return rc;
3505
3506 /* Raise a device table hardware error. */
3507 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3508
3509 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3510 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3511 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3512 return VERR_IOMMU_DTE_READ_FAILED;
3513 }
3514
3515 /* Raise an I/O page fault for out-of-bounds acccess. */
3516 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3517 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3518 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3519 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3520 kIoPageFaultType_DevId_Invalid);
3521 return VERR_IOMMU_DTE_BAD_OFFSET;
3522}
3523
3524
3525/**
3526 * Performs pre-translation checks for the given device table entry.
3527 *
3528 * @returns VBox status code.
3529 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3530 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3531 * translation is disabled.
3532 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3533 * corresponding event was raised.
3534 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3535 * permissions.
3536 *
3537 * @param pDevIns The IOMMU device instance.
3538 * @param uIova The I/O virtual address to translate.
3539 * @param idDevice The device ID (bus, device, function).
3540 * @param fPerm The I/O permissions for this access, see
3541 * IOMMU_IO_PERM_XXX.
3542 * @param pDte The device table entry.
3543 * @param enmOp The IOMMU operation being performed.
3544 *
3545 * @thread Any.
3546 */
3547static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3548 IOMMUOP enmOp)
3549{
3550 /*
3551 * Check if the translation is valid, otherwise raise an I/O page fault.
3552 */
3553 if (pDte->n.u1TranslationValid)
3554 { /* likely */ }
3555 else
3556 {
3557 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3558 * doesn't explicitly say whether an I/O page fault is raised. From other
3559 * places in the spec. it seems early page walk terminations (starting with
3560 * the DTE) return the state computed so far and raises an I/O page fault. So
3561 * returning an invalid translation rather than skipping translation. */
3562 LogFunc(("Translation valid bit not set -> IOPF\n"));
3563 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3564 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3565 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3566 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3567 kIoPageFaultType_DteTranslationDisabled);
3568 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3569 }
3570
3571 /*
3572 * Check permissions bits in the DTE.
3573 * Note: This MUST be checked prior to checking the root page table level below!
3574 */
3575 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3576 if ((fPerm & fDtePerm) == fPerm)
3577 { /* likely */ }
3578 else
3579 {
3580 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3581 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3582 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3583 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3584 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3585 kIoPageFaultType_PermDenied);
3586 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3587 }
3588
3589 /*
3590 * If the root page table level is 0, translation is disabled and GPA=SPA and
3591 * the DTE.IR and DTE.IW bits control permissions (verified above).
3592 */
3593 uint8_t const uMaxLevel = pDte->n.u3Mode;
3594 if (uMaxLevel != 0)
3595 { /* likely */ }
3596 else
3597 {
3598 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3599 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3600 }
3601
3602 /*
3603 * If the root page table level exceeds the allowed host-address translation level,
3604 * page walk is terminated and translation fails.
3605 */
3606 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3607 { /* likely */ }
3608 else
3609 {
3610 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3611 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3612 * I'm just going with I/O page fault. */
3613 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3614 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3615 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3616 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3617 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3618 kIoPageFaultType_PteInvalidLvlEncoding);
3619 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3620 }
3621
3622 /* The DTE allows translations for this device. */
3623 return VINF_SUCCESS;
3624}
3625
3626
3627/**
3628 * Walks the I/O page table to translate the I/O virtual address to a system
3629 * physical address.
3630 *
3631 * @returns VBox status code.
3632 * @param pDevIns The IOMMU device instance.
3633 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3634 * @param fPerm The I/O permissions for this access, see
3635 * IOMMU_IO_PERM_XXX.
3636 * @param idDevice The device ID (bus, device, function).
3637 * @param pDte The device table entry.
3638 * @param enmOp The IOMMU operation being performed.
3639 * @param pPageLookup Where to store the results of the I/O page lookup. This
3640 * is only updated when VINF_SUCCESS is returned.
3641 *
3642 * @thread Any.
3643 */
3644static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3645 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3646{
3647 Assert(pDte->n.u1Valid);
3648 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3649
3650 /* The virtual address bits indexing table. */
3651 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3652 static uint64_t const s_auIovaLevelMasks[] = { UINT64_C(0x0000000000000000),
3653 UINT64_C(0x00000000001ff000),
3654 UINT64_C(0x000000003fe00000),
3655 UINT64_C(0x0000007fc0000000),
3656 UINT64_C(0x0000ff8000000000),
3657 UINT64_C(0x01ff000000000000),
3658 UINT64_C(0xfe00000000000000),
3659 UINT64_C(0x0000000000000000) };
3660 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) == RT_ELEMENTS(s_auIovaLevelMasks));
3661 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3662
3663 /* Traverse the I/O page table starting with the page directory in the DTE. */
3664 IOPTENTITY_T PtEntity;
3665 PtEntity.u64 = pDte->au64[0];
3666 for (;;)
3667 {
3668 /* Figure out the system physical address of the page table at the current level. */
3669 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3670
3671 /* Read the page table entity at the current level. */
3672 {
3673 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3674 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3675 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3676 uint64_t const offPte = idxPte << 3;
3677 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3678 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3679 if (RT_FAILURE(rc))
3680 {
3681 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3682 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3683 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3684 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3685 return VERR_IOMMU_IPE_2;
3686 }
3687 }
3688
3689 /* Check present bit. */
3690 if (PtEntity.n.u1Present)
3691 { /* likely */ }
3692 else
3693 {
3694 LogFunc(("Page table entry not present (idDevice=%#x) -> IOPF\n", idDevice));
3695 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3696 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3697 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3698 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3699 kIoPageFaultType_PermDenied);
3700 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3701 }
3702
3703 /* Check permission bits. */
3704 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3705 if ((fPerm & fPtePerm) == fPerm)
3706 { /* likely */ }
3707 else
3708 {
3709 LogFunc(("Page table entry access denied (idDevice=%#x fPerm=%#x fPtePerm=%#x) -> IOPF\n", idDevice, fPerm, fPtePerm));
3710 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3711 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3712 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3713 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3714 kIoPageFaultType_PermDenied);
3715 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3716 }
3717
3718 /* If this is a PTE, we're at the final level and we're done. */
3719 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3720 if (uNextLevel == 0)
3721 {
3722 /* The page size of the translation is the default (4K). */
3723 pPageLookup->GCPhysSpa = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3724 pPageLookup->cShift = X86_PAGE_4K_SHIFT;
3725 pPageLookup->fPerm = fPtePerm;
3726 return VINF_SUCCESS;
3727 }
3728 if (uNextLevel == 7)
3729 {
3730 /* The default page size of the translation is overridden. */
3731 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3732 uint8_t cShift = X86_PAGE_4K_SHIFT;
3733 while (GCPhysPte & RT_BIT_64(cShift++))
3734 ;
3735
3736 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3737 Assert(uLevel < IOMMU_MAX_HOST_PT_LEVEL); /* PTE at level 6 handled outside the loop, uLevel should be <= 5. */
3738 if ( cShift > s_acIovaLevelShifts[uLevel]
3739 && cShift < s_acIovaLevelShifts[uLevel + 1])
3740 {
3741 pPageLookup->GCPhysSpa = GCPhysPte;
3742 pPageLookup->cShift = cShift;
3743 pPageLookup->fPerm = fPtePerm;
3744 return VINF_SUCCESS;
3745 }
3746
3747 LogFunc(("Page size invalid cShift=%#x -> IOPF\n", cShift));
3748 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3749 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3750 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3751 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3752 kIoPageFaultType_PteInvalidPageSize);
3753 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3754 }
3755
3756 /* Validate the next level encoding of the PDE. */
3757#if IOMMU_MAX_HOST_PT_LEVEL < 6
3758 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3759 { /* likely */ }
3760 else
3761 {
3762 LogFunc(("Next level of PDE invalid uNextLevel=%#x -> IOPF\n", uNextLevel));
3763 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3764 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3765 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3766 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3767 kIoPageFaultType_PteInvalidLvlEncoding);
3768 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3769 }
3770#else
3771 Assert(uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3772#endif
3773
3774 /* Validate level transition. */
3775 if (uNextLevel < uLevel)
3776 { /* likely */ }
3777 else
3778 {
3779 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3780 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3781 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3782 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3783 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3784 kIoPageFaultType_PteInvalidLvlEncoding);
3785 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3786 }
3787
3788 /* Ensure IOVA bits of skipped levels are zero. */
3789 Assert(uLevel > 0);
3790 uint64_t uIovaSkipMask = 0;
3791 for (unsigned idxLevel = uLevel - 1; idxLevel > uNextLevel; idxLevel--)
3792 uIovaSkipMask |= s_auIovaLevelMasks[idxLevel];
3793 if (!(uIova & uIovaSkipMask))
3794 { /* likely */ }
3795 else
3796 {
3797 LogFunc(("IOVA of skipped levels are not zero %#RX64 (SkipMask=%#RX64) -> IOPF\n", uIova, uIovaSkipMask));
3798 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3799 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3800 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3801 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3802 kIoPageFaultType_SkippedLevelIovaNotZero);
3803 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3804 }
3805
3806 /* Continue with traversing the page directory at this level. */
3807 }
3808}
3809
3810
3811/**
3812 * Page lookup callback for finding an I/O page from guest memory.
3813 *
3814 * @returns VBox status code.
3815 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3816 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3817 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3818 * insufficient to what is requested.
3819 *
3820 * @param pDevIns The IOMMU instance data.
3821 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3822 * 4K aligned).
3823 * @param fPerm The I/O permissions for this access, see
3824 * IOMMU_IO_PERM_XXX.
3825 * @param pAux The auxiliary information required during lookup.
3826 * @param pPageLookup Where to store the looked up I/O page.
3827 */
3828static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3829 PIOPAGELOOKUP pPageLookup)
3830{
3831 AssertPtr(pAux);
3832 AssertPtr(pPageLookup);
3833 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3834
3835 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3836 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3837 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3838 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3839 return rc;
3840}
3841
3842
3843/**
3844 * Looks up a range of I/O virtual addresses.
3845 *
3846 * @returns VBox status code.
3847 * @param pDevIns The IOMMU instance data.
3848 * @param pfnIoPageLookup The lookup function to use.
3849 * @param pAddrIn The I/O address range to lookup.
3850 * @param pAux The auxiliary information required by the lookup
3851 * function.
3852 * @param pAddrOut Where to store the translated I/O address range.
3853 * @param pcbPages Where to store the size of the access (round up to
3854 * the page size). Optional, can be NULL.
3855 */
3856static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3857 PCIOMMUOPAUX pAux, PIOADDRRANGE pAddrOut, size_t *pcbPages)
3858{
3859 AssertPtr(pfnIoPageLookup);
3860 AssertPtr(pAddrIn);
3861 AssertPtr(pAddrOut);
3862
3863 int rc;
3864 size_t const cbIova = pAddrIn->cb;
3865 uint8_t const fPerm = pAddrIn->fPerm;
3866 uint64_t const uIova = pAddrIn->uAddr;
3867 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3868 size_t cbRemaining = cbIova;
3869 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3870 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3871 uint64_t cbPages = 0;
3872
3873 IOPAGELOOKUP PageLookupPrev;
3874 RT_ZERO(PageLookupPrev);
3875 for (;;)
3876 {
3877 IOPAGELOOKUP PageLookup;
3878 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3879 if (RT_SUCCESS(rc))
3880 {
3881 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT);
3882
3883 /* Store the translated address before continuing to access more pages. */
3884 if (cbRemaining == cbIova)
3885 {
3886 uint64_t const offMask = X86_GET_PAGE_OFFSET_MASK(PageLookup.cShift);
3887 uint64_t const offSpa = uIova & offMask;
3888 Assert(!(PageLookup.GCPhysSpa & offMask));
3889 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3890 }
3891 /* Check if addresses translated so far result in a physically contiguous region. */
3892 else if (!iommuAmdLookupIsAccessContig(&PageLookupPrev, &PageLookup))
3893 {
3894 rc = VERR_OUT_OF_RANGE;
3895 break;
3896 }
3897
3898 /* Store the page lookup result from the first/previous page. */
3899 PageLookupPrev = PageLookup;
3900
3901 /* Update size of all pages read thus far. */
3902 uint64_t const cbPage = RT_BIT_64(PageLookup.cShift);
3903 cbPages += cbPage;
3904
3905 /* Check if we need to access more pages. */
3906 if (cbRemaining > cbPage - offIova)
3907 {
3908 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3909 uIovaPage += cbPage; /* Update address of the next access. */
3910 offIova = 0; /* After first page, all pages are accessed from off 0. */
3911 }
3912 else
3913 {
3914 /* Caller (PDM) doesn't expect more data accessed than what was requested. */
3915 cbRemaining = 0;
3916 break;
3917 }
3918 }
3919 else
3920 break;
3921 }
3922
3923 pAddrOut->uAddr = GCPhysSpa; /* Update the translated address. */
3924 pAddrOut->cb = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
3925 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
3926 if (pcbPages)
3927 *pcbPages = cbPages; /* Update the size of the pages accessed. */
3928 return rc;
3929}
3930
3931
3932/**
3933 * Looks up an I/O virtual address from the device table.
3934 *
3935 * @returns VBox status code.
3936 * @param pDevIns The IOMMU instance data.
3937 * @param idDevice The device ID (bus, device, function).
3938 * @param uIova The I/O virtual address to lookup.
3939 * @param cbIova The size of the access.
3940 * @param fPerm The I/O permissions for this access, see
3941 * IOMMU_IO_PERM_XXX.
3942 * @param enmOp The IOMMU operation being performed.
3943 * @param pGCPhysSpa Where to store the translated system physical address.
3944 * @param pcbContiguous Where to store the number of contiguous bytes translated
3945 * and permission-checked.
3946 *
3947 * @thread Any.
3948 */
3949static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
3950 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3951{
3952 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3953 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3954 size_t cbContiguous = 0;
3955
3956 /* Read the device table entry from memory. */
3957 DTE_T Dte;
3958 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
3959 if (RT_SUCCESS(rc))
3960 {
3961 if (Dte.n.u1Valid)
3962 {
3963 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
3964 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
3965 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
3966 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
3967 {
3968 /*
3969 * Check if the DTE is configured for translating addresses.
3970 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
3971 * so there's no need to check the address exclusion base/limit here.
3972 */
3973 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
3974 if (rc == VINF_SUCCESS)
3975 {
3976 IOADDRRANGE AddrIn;
3977 AddrIn.uAddr = uIova;
3978 AddrIn.cb = cbIova;
3979 AddrIn.fPerm = fPerm;
3980
3981 IOMMUOPAUX Aux;
3982 Aux.enmOp = enmOp;
3983 Aux.pDte = &Dte;
3984 Aux.idDevice = idDevice;
3985 Aux.idDomain = Dte.n.u16DomainId;
3986
3987 IOADDRRANGE AddrOut;
3988
3989 /* Lookup the address from the DTE and I/O page tables.*/
3990 size_t cbPages = 0;
3991 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbPages);
3992 GCPhysSpa = AddrOut.uAddr;
3993 cbContiguous = AddrOut.cb;
3994
3995 /* If we stopped since translation resulted in non-contiguous physical addresses,
3996 what we translated so far is still valid. */
3997 if (rc == VERR_OUT_OF_RANGE)
3998 {
3999 Assert(cbContiguous > 0 && cbContiguous < cbIova);
4000 rc = VINF_SUCCESS;
4001 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
4002 }
4003
4004 if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
4005 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4006
4007#ifdef IOMMU_WITH_IOTLBE_CACHE
4008 if (RT_SUCCESS(rc))
4009 {
4010 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
4011 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
4012 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
4013 iommuAmdIotlbAddRange(pDevIns, Dte.n.u16DomainId, uIova & X86_PAGE_4K_BASE_MASK, cbPages,
4014 GCPhysSpa & X86_PAGE_4K_BASE_MASK, AddrOut.fPerm);
4015 }
4016#endif
4017 }
4018 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
4019 {
4020 /*
4021 * Translation is disabled for this device (root paging mode is 0).
4022 * GPA=SPA, but the permission bits are important and controls accesses.
4023 */
4024 GCPhysSpa = uIova;
4025 cbContiguous = cbIova;
4026 rc = VINF_SUCCESS;
4027
4028#ifdef IOMMU_WITH_IOTLBE_CACHE
4029 /* Update that addresses permissions of DTE apply (but omit address translation). */
4030 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_IO_PERM);
4031#endif
4032 }
4033 else
4034 {
4035 /* Address translation failed or access is denied. */
4036 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4037 GCPhysSpa = NIL_RTGCPHYS;
4038 cbContiguous = 0;
4039 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4040 }
4041 }
4042 else
4043 {
4044 /* Invalid reserved bits in the DTE, raise an error event. */
4045 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4046 EVT_ILLEGAL_DTE_T Event;
4047 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4048 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4049 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4050 }
4051 }
4052 else
4053 {
4054 /*
4055 * The DTE is not valid, forward addresses untranslated.
4056 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4057 */
4058 GCPhysSpa = uIova;
4059 cbContiguous = cbIova;
4060
4061#ifdef IOMMU_WITH_IOTLBE_CACHE
4062 /* Update that addresses don't require translation (nor permission checks) but a DTE is present. */
4063 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4064#endif
4065 }
4066 }
4067 else
4068 {
4069 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4070 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4071 }
4072
4073 *pGCPhysSpa = GCPhysSpa;
4074 *pcbContiguous = cbContiguous;
4075 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4076 return rc;
4077}
4078
4079
4080#ifdef IOMMU_WITH_IOTLBE_CACHE
4081/**
4082 * I/O page lookup callback for finding an I/O page from the IOTLB.
4083 *
4084 * @returns VBox status code.
4085 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4086 * @retval VERR_NOT_FOUND when the page is not found.
4087 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4088 * insufficient to what is requested.
4089 *
4090 * @param pDevIns The IOMMU instance data.
4091 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4092 * 4K aligned).
4093 * @param fPerm The I/O permissions for this access, see
4094 * IOMMU_IO_PERM_XXX.
4095 * @param pAux The auxiliary information required during lookup.
4096 * @param pPageLookup Where to store the looked up I/O page.
4097 */
4098static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4099 PIOPAGELOOKUP pPageLookup)
4100{
4101 Assert(pAux);
4102 Assert(pPageLookup);
4103 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4104
4105 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4106 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4107
4108 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4109 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4110 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4111 if (pIotlbe)
4112 {
4113 *pPageLookup = pIotlbe->PageLookup;
4114 if ((pPageLookup->fPerm & fPerm) == fPerm)
4115 {
4116 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4117 return VINF_SUCCESS;
4118 }
4119 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4120 }
4121 return VERR_NOT_FOUND;
4122}
4123
4124
4125/**
4126 * Lookups a memory access from the IOTLB cache.
4127 *
4128 * @returns VBox status code.
4129 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4130 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4131 * address region.
4132 * @retval VERR_NOT_FOUND if the access was not cached.
4133 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4134 * are insufficient.
4135 *
4136 * @param pDevIns The IOMMU instance data.
4137 * @param idDevice The device ID (bus, device, function).
4138 * @param uIova The I/O virtual address to lookup.
4139 * @param cbIova The size of the access.
4140 * @param fPerm The I/O permissions for this access, see
4141 * IOMMU_IO_PERM_XXX.
4142 * @param enmOp The IOMMU operation being performed.
4143 * @param pGCPhysSpa Where to store the translated system physical address.
4144 * @param pcbContiguous Where to store the number of contiguous bytes translated
4145 * and permission-checked.
4146 */
4147static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4148 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4149{
4150 int rc;
4151 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4152
4153#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4154 do { \
4155 *pGCPhysSpa = NIL_RTGCPHYS; \
4156 *pcbContiguous = 0; \
4157 rc = (a_rc); \
4158 } while (0)
4159
4160 /*
4161 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4162 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4163 */
4164 IOMMU_CACHE_LOCK(pDevIns, pThis);
4165
4166 /* Lookup the DTE cache entry. */
4167 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4168 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4169 {
4170 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4171 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4172 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4173 {
4174 /* Lookup IOTLB entries. */
4175 IOADDRRANGE AddrIn;
4176 AddrIn.uAddr = uIova;
4177 AddrIn.cb = cbIova;
4178 AddrIn.fPerm = fPerm;
4179
4180 IOMMUOPAUX Aux;
4181 Aux.enmOp = enmOp;
4182 Aux.pDte = NULL;
4183 Aux.idDevice = idDevice;
4184 Aux.idDomain = pDteCache->idDomain;
4185
4186 IOADDRRANGE AddrOut;
4187 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, NULL /* pcbPages */);
4188 Assert(AddrOut.cb <= cbIova);
4189 *pGCPhysSpa = AddrOut.uAddr;
4190 *pcbContiguous = AddrOut.cb;
4191 }
4192 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4193 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4194 {
4195 /* Address translation is disabled, but DTE permissions apply. */
4196 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4197 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4198 if ((fDtePerm & fPerm) == fPerm)
4199 {
4200 *pGCPhysSpa = uIova;
4201 *pcbContiguous = cbIova;
4202 rc = VINF_SUCCESS;
4203 }
4204 else
4205 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4206 }
4207 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4208 {
4209 /* Forward addresses untranslated, without checking permissions. */
4210 *pGCPhysSpa = uIova;
4211 *pcbContiguous = cbIova;
4212 rc = VINF_SUCCESS;
4213 }
4214 else
4215 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4216 }
4217 else
4218 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4219
4220 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
4221
4222 return rc;
4223
4224#undef IOMMU_IOTLB_LOOKUP_FAILED
4225}
4226#endif /* IOMMU_WITH_IOTLBE_CACHE */
4227
4228
4229/**
4230 * Gets the I/O permission and IOMMU operation type for the given access flags.
4231 *
4232 * @param pThis The shared IOMMU device state.
4233 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4234 * @param penmOp Where to store the IOMMU operation.
4235 * @param pfPerm Where to store the IOMMU I/O permission.
4236 * @param fBulk Whether this is a bulk read or write.
4237 */
4238DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4239{
4240 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4241 {
4242 *penmOp = IOMMUOP_MEM_WRITE;
4243 *pfPerm = IOMMU_IO_PERM_WRITE;
4244#ifdef VBOX_WITH_STATISTICS
4245 if (!fBulk)
4246 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4247 else
4248 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4249#else
4250 RT_NOREF2(pThis, fBulk);
4251#endif
4252 }
4253 else
4254 {
4255 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4256 *penmOp = IOMMUOP_MEM_READ;
4257 *pfPerm = IOMMU_IO_PERM_READ;
4258#ifdef VBOX_WITH_STATISTICS
4259 if (!fBulk)
4260 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4261 else
4262 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4263#else
4264 RT_NOREF2(pThis, fBulk);
4265#endif
4266 }
4267}
4268
4269
4270/**
4271 * Memory access transaction from a device.
4272 *
4273 * @returns VBox status code.
4274 * @param pDevIns The IOMMU device instance.
4275 * @param idDevice The device ID (bus, device, function).
4276 * @param uIova The I/O virtual address being accessed.
4277 * @param cbIova The size of the access.
4278 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4279 * @param pGCPhysSpa Where to store the translated system physical address.
4280 * @param pcbContiguous Where to store the number of contiguous bytes translated
4281 * and permission-checked.
4282 *
4283 * @thread Any.
4284 */
4285static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4286 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4287{
4288 /* Validate. */
4289 AssertPtr(pDevIns);
4290 AssertPtr(pGCPhysSpa);
4291 Assert(cbIova > 0);
4292 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4293
4294 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4295 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4296 if (Ctrl.n.u1IommuEn)
4297 {
4298 IOMMUOP enmOp;
4299 uint8_t fPerm;
4300 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4301 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4302
4303 int rc;
4304#ifdef IOMMU_WITH_IOTLBE_CACHE
4305 /* Lookup the IOVA from the cache. */
4306 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4307 if (rc == VINF_SUCCESS)
4308 {
4309 /* All pages in the access were found in the cache with sufficient permissions. */
4310 Assert(*pcbContiguous == cbIova);
4311 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4312 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4313 return VINF_SUCCESS;
4314 }
4315 if (rc != VERR_OUT_OF_RANGE)
4316 { /* likely */ }
4317 else
4318 {
4319 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4320 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4321 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4322 return VINF_SUCCESS;
4323 }
4324
4325 /*
4326 * Access incomplete as not all pages were in the cache.
4327 * Or permissions were denied for the access (which typically doesn't happen)
4328 * so go through the slower path and raise the required event.
4329 */
4330 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4331 uIova += *pcbContiguous;
4332 cbIova -= *pcbContiguous;
4333 /* We currently are including any permission denied pages as cache misses too.*/
4334 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4335#endif
4336
4337 /* Lookup the IOVA from the device table. */
4338 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4339 if (RT_SUCCESS(rc))
4340 { /* likely */ }
4341 else
4342 {
4343 Assert(rc != VERR_OUT_OF_RANGE);
4344 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4345 cbIova, rc));
4346 }
4347
4348 return rc;
4349 }
4350
4351 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4352 *pGCPhysSpa = uIova;
4353 *pcbContiguous = cbIova;
4354 return VINF_SUCCESS;
4355}
4356
4357
4358/**
4359 * Memory access bulk (one or more 4K pages) request from a device.
4360 *
4361 * @returns VBox status code.
4362 * @param pDevIns The IOMMU device instance.
4363 * @param idDevice The device ID (bus, device, function).
4364 * @param cIovas The number of addresses being accessed.
4365 * @param pauIovas The I/O virtual addresses for each page being accessed.
4366 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4367 * @param paGCPhysSpa Where to store the translated physical addresses.
4368 *
4369 * @thread Any.
4370 */
4371static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4372 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4373{
4374 /* Validate. */
4375 AssertPtr(pDevIns);
4376 Assert(cIovas > 0);
4377 AssertPtr(pauIovas);
4378 AssertPtr(paGCPhysSpa);
4379 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4380
4381 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4382 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4383 if (Ctrl.n.u1IommuEn)
4384 {
4385 IOMMUOP enmOp;
4386 uint8_t fPerm;
4387 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4388 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4389
4390 for (size_t i = 0; i < cIovas; i++)
4391 {
4392 int rc;
4393 size_t cbContig;
4394
4395#ifdef IOMMU_WITH_IOTLBE_CACHE
4396 /* Lookup the IOVA from the IOTLB cache. */
4397 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4398 &cbContig);
4399 if (rc == VINF_SUCCESS)
4400 {
4401 Assert(cbContig == X86_PAGE_SIZE);
4402 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4403 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4404 continue;
4405 }
4406 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4407 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4408#endif
4409
4410 /* Lookup the IOVA from the device table. */
4411 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4412 if (RT_SUCCESS(rc))
4413 { /* likely */ }
4414 else
4415 {
4416 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4417 return rc;
4418 }
4419 Assert(cbContig == X86_PAGE_SIZE);
4420 }
4421 }
4422 else
4423 {
4424 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4425 for (size_t i = 0; i < cIovas; i++)
4426 paGCPhysSpa[i] = pauIovas[i];
4427 }
4428
4429 return VINF_SUCCESS;
4430}
4431
4432
4433/**
4434 * Reads an interrupt remapping table entry from guest memory given its DTE.
4435 *
4436 * @returns VBox status code.
4437 * @param pDevIns The IOMMU device instance.
4438 * @param idDevice The device ID (bus, device, function).
4439 * @param pDte The device table entry.
4440 * @param GCPhysIn The source MSI address (used for reporting errors).
4441 * @param uDataIn The source MSI data.
4442 * @param enmOp The IOMMU operation being performed.
4443 * @param pIrte Where to store the interrupt remapping table entry.
4444 *
4445 * @thread Any.
4446 */
4447static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4448 IOMMUOP enmOp, PIRTE_T pIrte)
4449{
4450 /* Ensure the IRTE length is valid. */
4451 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4452
4453 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4454 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4455 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4456 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4457
4458 /* Ensure the IRTE falls completely within the interrupt table. */
4459 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4460 { /* likely */ }
4461 else
4462 {
4463 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4464 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4465
4466 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4467 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4468 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4469 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4470 kIoPageFaultType_IrteAddrInvalid);
4471 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4472 }
4473
4474 /* Read the IRTE from memory. */
4475 Assert(!(GCPhysIrte & 3));
4476 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4477 if (RT_SUCCESS(rc))
4478 return VINF_SUCCESS;
4479
4480 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4481 * situation. Is it an I/O page fault or a device table hardware error?
4482 * There's no interrupt table hardware error event, but it's unclear what
4483 * we should do here. */
4484 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4485 return VERR_IOMMU_IPE_4;
4486}
4487
4488
4489/**
4490 * Remaps the interrupt using the interrupt remapping table.
4491 *
4492 * @returns VBox status code.
4493 * @param pDevIns The IOMMU instance data.
4494 * @param idDevice The device ID (bus, device, function).
4495 * @param pDte The device table entry.
4496 * @param enmOp The IOMMU operation being performed.
4497 * @param pMsiIn The source MSI.
4498 * @param pMsiOut Where to store the remapped MSI.
4499 *
4500 * @thread Any.
4501 */
4502static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4503 PMSIMSG pMsiOut)
4504{
4505 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4506
4507 IRTE_T Irte;
4508 uint32_t const uMsiInData = pMsiIn->Data.u32;
4509 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4510 if (RT_SUCCESS(rc))
4511 {
4512 if (Irte.n.u1RemapEnable)
4513 {
4514 if (!Irte.n.u1GuestMode)
4515 {
4516 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4517 {
4518 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4519#ifdef IOMMU_WITH_IRTE_CACHE
4520 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4521#endif
4522 return VINF_SUCCESS;
4523 }
4524
4525 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4526 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4527 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4528 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4529 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4530 kIoPageFaultType_IrteRsvdIntType);
4531 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4532 }
4533
4534 LogFunc(("Guest mode not supported -> IOPF\n"));
4535 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4536 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4537 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4538 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4539 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4540 }
4541
4542 LogFunc(("Remapping disabled -> IOPF\n"));
4543 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4544 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4545 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4546 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4547 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4548 }
4549
4550 return rc;
4551}
4552
4553
4554/**
4555 * Looks up an MSI interrupt from the interrupt remapping table.
4556 *
4557 * @returns VBox status code.
4558 * @param pDevIns The IOMMU instance data.
4559 * @param idDevice The device ID (bus, device, function).
4560 * @param enmOp The IOMMU operation being performed.
4561 * @param pMsiIn The source MSI.
4562 * @param pMsiOut Where to store the remapped MSI.
4563 *
4564 * @thread Any.
4565 */
4566static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4567{
4568 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4569 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4570 enmOp));
4571
4572 /* Read the device table entry from memory. */
4573 DTE_T Dte;
4574 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4575 if (RT_SUCCESS(rc))
4576 {
4577#ifdef IOMMU_WITH_IRTE_CACHE
4578 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4579#endif
4580 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4581 if (Dte.n.u1IntrMapValid)
4582 {
4583 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4584 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4585 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4586 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4587 { /* likely */ }
4588 else
4589 {
4590 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4591 EVT_ILLEGAL_DTE_T Event;
4592 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4593 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4594 return VERR_IOMMU_INTR_REMAP_FAILED;
4595 }
4596
4597 /*
4598 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4599 * that's connected through HyperTransport it might be possible; but for us, it
4600 * doesn't seem we need to specially handle these pins.
4601 */
4602
4603 /*
4604 * Validate the MSI source address.
4605 *
4606 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4607 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4608 * claims the region as I/O space.
4609 *
4610 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4611 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4612 * See Intel spec. 10.11.1 "Message Address Register Format".
4613 */
4614 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4615 {
4616 /*
4617 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4618 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4619 */
4620 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4621 bool fPassThru = false;
4622 switch (u8DeliveryMode)
4623 {
4624 case VBOX_MSI_DELIVERY_MODE_FIXED:
4625 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4626 {
4627 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4628 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4629 {
4630 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4631 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4632 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4633 {
4634 /*
4635 * We don't support guest interrupt remapping yet. When we do, we'll need to
4636 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4637 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4638 * already reads the control register, add that as a parameter when we eventually
4639 * support guest interrupt remapping. For now, just assert.
4640 */
4641 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4642 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4643 NOREF(pThis);
4644
4645 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4646 }
4647
4648 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4649 EVT_ILLEGAL_DTE_T Event;
4650 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4651 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4652 return VERR_IOMMU_INTR_REMAP_FAILED;
4653 }
4654
4655 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4656 {
4657 fPassThru = true;
4658 break;
4659 }
4660
4661 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4662 {
4663 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4664 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4665 iommuAmdSetPciTargetAbort(pDevIns);
4666 return VERR_IOMMU_INTR_REMAP_DENIED;
4667 }
4668
4669 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4670 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4671 EVT_ILLEGAL_DTE_T Event;
4672 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4673 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4674 return VERR_IOMMU_INTR_REMAP_FAILED;
4675 }
4676
4677 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4678 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4679 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4680 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4681 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4682 default:
4683 {
4684 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4685 u8DeliveryMode));
4686 iommuAmdSetPciTargetAbort(pDevIns);
4687 return VERR_IOMMU_INTR_REMAP_FAILED;
4688 }
4689 }
4690
4691 /*
4692 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4693 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4694 */
4695 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4696 || !pMsiIn->Addr.n.u1DestMode)
4697 {
4698 if (fPassThru)
4699 {
4700 *pMsiOut = *pMsiIn;
4701 return VINF_SUCCESS;
4702 }
4703 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4704 pMsiIn->Data.n.u8Vector));
4705 }
4706 else
4707 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4708 IOMMU_LOG_PFX, u8DeliveryMode));
4709
4710 iommuAmdSetPciTargetAbort(pDevIns);
4711 return VERR_IOMMU_INTR_REMAP_DENIED;
4712 }
4713 else
4714 {
4715 /** @todo should be cause a PCI target abort here? */
4716 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4717 return VERR_IOMMU_INTR_REMAP_FAILED;
4718 }
4719 }
4720 else
4721 {
4722 LogFlowFunc(("DTE interrupt map not valid\n"));
4723 *pMsiOut = *pMsiIn;
4724 return VINF_SUCCESS;
4725 }
4726 }
4727
4728 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4729 return VERR_IOMMU_INTR_REMAP_FAILED;
4730}
4731
4732
4733/**
4734 * Interrupt remap request from a device.
4735 *
4736 * @returns VBox status code.
4737 * @param pDevIns The IOMMU device instance.
4738 * @param idDevice The device ID (bus, device, function).
4739 * @param pMsiIn The source MSI.
4740 * @param pMsiOut Where to store the remapped MSI.
4741 */
4742static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4743{
4744 /* Validate. */
4745 Assert(pDevIns);
4746 Assert(pMsiIn);
4747 Assert(pMsiOut);
4748
4749 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4750
4751 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4752 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4753 if (Ctrl.n.u1IommuEn)
4754 {
4755 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4756
4757 int rc;
4758#ifdef IOMMU_WITH_IRTE_CACHE
4759 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4760 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4761 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4762 if (RT_SUCCESS(rc))
4763 {
4764 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4765 return VINF_SUCCESS;
4766 }
4767 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4768#endif
4769
4770 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4771 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4772 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4773 return rc;
4774 }
4775
4776 *pMsiOut = *pMsiIn;
4777 return VINF_SUCCESS;
4778}
4779
4780
4781/**
4782 * @callback_method_impl{FNIOMMMIONEWWRITE}
4783 */
4784static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4785{
4786 NOREF(pvUser);
4787 Assert(cb == 4 || cb == 8);
4788 Assert(!(off & (cb - 1)));
4789
4790 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4791 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4792
4793 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4794 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4795}
4796
4797
4798/**
4799 * @callback_method_impl{FNIOMMMIONEWREAD}
4800 */
4801static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4802{
4803 NOREF(pvUser);
4804 Assert(cb == 4 || cb == 8);
4805 Assert(!(off & (cb - 1)));
4806
4807 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4808 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4809
4810 uint64_t uResult;
4811 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4812 if (rcStrict == VINF_SUCCESS)
4813 {
4814 if (cb == 8)
4815 *(uint64_t *)pv = uResult;
4816 else
4817 *(uint32_t *)pv = (uint32_t)uResult;
4818 }
4819
4820 return rcStrict;
4821}
4822
4823
4824#ifdef IN_RING3
4825/**
4826 * Processes an IOMMU command.
4827 *
4828 * @returns VBox status code.
4829 * @param pDevIns The IOMMU device instance.
4830 * @param pCmd The command to process.
4831 * @param GCPhysCmd The system physical address of the command.
4832 * @param pEvtError Where to store the error event in case of failures.
4833 *
4834 * @thread Command thread.
4835 */
4836static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4837{
4838 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4839 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4840
4841 STAM_COUNTER_INC(&pThis->StatCmd);
4842
4843 uint8_t const bCmd = pCmd->n.u4Opcode;
4844 switch (bCmd)
4845 {
4846 case IOMMU_CMD_COMPLETION_WAIT:
4847 {
4848 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4849
4850 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4851 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4852
4853 /* Validate reserved bits in the command. */
4854 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4855 {
4856 /* If Completion Store is requested, write the StoreData to the specified address. */
4857 if (pCmdComWait->n.u1Store)
4858 {
4859 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4860 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4861 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4862 if (RT_FAILURE(rc))
4863 {
4864 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4865 GCPhysStore, rc));
4866 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4867 return VERR_IOMMU_CMD_HW_ERROR;
4868 }
4869 }
4870
4871 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4872 if (pCmdComWait->n.u1Interrupt)
4873 {
4874 IOMMU_LOCK(pDevIns, pThisR3);
4875 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4876 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4877 IOMMU_UNLOCK(pDevIns, pThisR3);
4878 if (fRaiseInt)
4879 iommuAmdMsiInterruptRaise(pDevIns);
4880 }
4881 return VINF_SUCCESS;
4882 }
4883 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4884 return VERR_IOMMU_CMD_INVALID_FORMAT;
4885 }
4886
4887 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4888 {
4889 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4890 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4891 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4892
4893 /* Validate reserved bits in the command. */
4894 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4895 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4896 {
4897#ifdef IOMMU_WITH_DTE_CACHE
4898 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4899#endif
4900 return VINF_SUCCESS;
4901 }
4902 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4903 return VERR_IOMMU_CMD_INVALID_FORMAT;
4904 }
4905
4906 case IOMMU_CMD_INV_IOMMU_PAGES:
4907 {
4908 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4909 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4910 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4911
4912 /* Validate reserved bits in the command. */
4913 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4914 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4915 {
4916#ifdef IOMMU_WITH_IOTLBE_CACHE
4917 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4918 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
4919 uint8_t cShift;
4920 if (!pCmdInvPages->n.u1Size)
4921 cShift = X86_PAGE_4K_SHIFT;
4922 else
4923 {
4924 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4925 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4926 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4927
4928 /*
4929 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4930 * would do the right thing by clearing the entire cache for the specified domain ID.
4931 *
4932 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4933 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4934 * A debug-time assert is in place here to let us know if any software tries this.
4935 *
4936 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4937 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4938 */
4939 Assert(uIova != UINT64_C(0xfffffffffffff000));
4940 }
4941
4942 /*
4943 * Validate invalidation size.
4944 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4945 */
4946 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4947 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4948 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4949 {
4950 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4951 size_t const cbIova = RT_BIT_64(cShift);
4952 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
4953 }
4954 else
4955 {
4956 /*
4957 * The guest provided size is invalid or exceeds the largest, meaningful page size.
4958 * In such situations we must remove all ranges for the specified domain ID.
4959 */
4960 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
4961 }
4962#endif
4963 return VINF_SUCCESS;
4964 }
4965 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4966 return VERR_IOMMU_CMD_INVALID_FORMAT;
4967 }
4968
4969 case IOMMU_CMD_INV_IOTLB_PAGES:
4970 {
4971 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
4972
4973 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
4974 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
4975 {
4976 /** @todo IOMMU: Implement remote IOTLB invalidation. */
4977 return VERR_NOT_IMPLEMENTED;
4978 }
4979 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4980 return VERR_IOMMU_CMD_NOT_SUPPORTED;
4981 }
4982
4983 case IOMMU_CMD_INV_INTR_TABLE:
4984 {
4985 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
4986
4987 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
4988 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
4989
4990 /* Validate reserved bits in the command. */
4991 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
4992 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
4993 {
4994#ifdef IOMMU_WITH_IRTE_CACHE
4995 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
4996#endif
4997 return VINF_SUCCESS;
4998 }
4999 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5000 return VERR_IOMMU_CMD_INVALID_FORMAT;
5001 }
5002
5003 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
5004 {
5005 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
5006 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
5007 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
5008 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5009 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5010 }
5011
5012 case IOMMU_CMD_COMPLETE_PPR_REQ:
5013 {
5014 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
5015
5016 /* We don't support PPR requests yet. */
5017 Assert(!pThis->ExtFeat.n.u1PprSup);
5018 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5019 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5020 }
5021
5022 case IOMMU_CMD_INV_IOMMU_ALL:
5023 {
5024 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
5025 if (pThis->ExtFeat.n.u1InvAllSup)
5026 {
5027 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
5028 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
5029
5030 /* Validate reserved bits in the command. */
5031 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
5032 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
5033 {
5034#ifdef IOMMU_WITH_DTE_CACHE
5035 iommuAmdDteCacheRemoveAll(pDevIns);
5036#endif
5037#ifdef IOMMU_WITH_IOTLBE_CACHE
5038 iommuAmdIotlbRemoveAll(pDevIns);
5039#endif
5040 return VINF_SUCCESS;
5041 }
5042 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5043 return VERR_IOMMU_CMD_INVALID_FORMAT;
5044 }
5045 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5046 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5047 }
5048 }
5049
5050 STAM_COUNTER_DEC(&pThis->StatCmd);
5051 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5052 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5053 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5054}
5055
5056
5057/**
5058 * The IOMMU command thread.
5059 *
5060 * @returns VBox status code.
5061 * @param pDevIns The IOMMU device instance.
5062 * @param pThread The command thread.
5063 */
5064static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5065{
5066 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5067 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5068
5069 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5070 return VINF_SUCCESS;
5071
5072 /*
5073 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5074 * This avoid trashing the heap as well as not wasting time allocating
5075 * and freeing buffers while processing commands.
5076 */
5077 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5078 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5079 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5080
5081 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5082 {
5083 /*
5084 * Sleep perpetually until we are woken up to process commands.
5085 */
5086 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5087 if (!fSignaled)
5088 {
5089 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5090 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5091 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5092 break;
5093 Log4Func(("Woken up with rc=%Rrc\n", rc));
5094 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5095 }
5096
5097 /*
5098 * Fetch and process IOMMU commands.
5099 */
5100 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5101 * temporary host buffer before processing them as a batch. If we want to
5102 * save on host memory a bit, we could (once PGM has the necessary APIs)
5103 * lock the page mappings page mappings and access them directly. */
5104 IOMMU_LOCK(pDevIns, pThisR3);
5105
5106 if (pThis->Status.n.u1CmdBufRunning)
5107 {
5108 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5109 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5110 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5111 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5112
5113 /* Validate. */
5114 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5115 Assert(offHead < cbCmdBuf);
5116 Assert(cbCmdBuf <= cbMaxCmdBuf);
5117
5118 if (offHead != offTail)
5119 {
5120 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5121 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5122
5123 IOMMU_UNLOCK(pDevIns, pThisR3);
5124 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5125 IOMMU_LOCK(pDevIns, pThisR3);
5126
5127 if (RT_SUCCESS(rc))
5128 {
5129 /* Indicate to software we've fetched all commands from the buffer. */
5130 pThis->CmdBufHeadPtr.n.off = offTail;
5131
5132 /* Allow IOMMU to do other work while we process commands. */
5133 IOMMU_UNLOCK(pDevIns, pThisR3);
5134
5135 /* Process the fetched commands. */
5136 EVT_GENERIC_T EvtError;
5137 do
5138 {
5139 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5140 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5141 if (RT_FAILURE(rc))
5142 {
5143 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5144 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5145 {
5146 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5147 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5148 }
5149 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5150 {
5151 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5152 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5153 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5154 }
5155 break;
5156 }
5157
5158 /* Move to the next command in the circular buffer. */
5159 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5160 } while (offHead != offTail);
5161 }
5162 else
5163 {
5164 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5165 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5166 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5167 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5168
5169 IOMMU_UNLOCK(pDevIns, pThisR3);
5170 }
5171 }
5172 else
5173 IOMMU_UNLOCK(pDevIns, pThisR3);
5174 }
5175 else
5176 IOMMU_UNLOCK(pDevIns, pThisR3);
5177 }
5178
5179 RTMemFree(pvCmds);
5180 LogFlowFunc(("Command thread terminating\n"));
5181 return VINF_SUCCESS;
5182}
5183
5184
5185/**
5186 * Wakes up the command thread so it can respond to a state change.
5187 *
5188 * @returns VBox status code.
5189 * @param pDevIns The IOMMU device instance.
5190 * @param pThread The command thread.
5191 */
5192static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5193{
5194 RT_NOREF(pThread);
5195 LogFlowFunc(("\n"));
5196 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5197 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5198}
5199
5200
5201/**
5202 * @callback_method_impl{FNPCICONFIGREAD}
5203 */
5204static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5205 unsigned cb, uint32_t *pu32Value)
5206{
5207 /** @todo IOMMU: PCI config read stat counter. */
5208 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5209 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5210 return rcStrict;
5211}
5212
5213
5214/**
5215 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5216 * register write).
5217 *
5218 * @returns VBox status code.
5219 * @param pDevIns The IOMMU instance data.
5220 *
5221 * @remarks Call this function only when the IOMMU BAR is enabled.
5222 */
5223static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5224{
5225 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5226 Assert(pThis->IommuBar.n.u1Enable);
5227 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5228 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5229 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5230 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5231
5232 /* If the MMIO region is already mapped at the specified address, we're done. */
5233 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5234 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5235 return VINF_SUCCESS;
5236
5237 /* Unmap the previous MMIO region (which is at a different address). */
5238 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5239 {
5240 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5241 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5242 if (RT_FAILURE(rc))
5243 {
5244 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5245 return rc;
5246 }
5247 }
5248
5249 /* Map the newly specified MMIO region. */
5250 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5251 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5252 if (RT_FAILURE(rc))
5253 {
5254 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5255 return rc;
5256 }
5257
5258 return VINF_SUCCESS;
5259}
5260
5261
5262/**
5263 * @callback_method_impl{FNPCICONFIGWRITE}
5264 */
5265static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5266 unsigned cb, uint32_t u32Value)
5267{
5268 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5269
5270 /*
5271 * Discard writes to read-only registers that are specific to the IOMMU.
5272 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5273 * See PCI spec. 6.1. "Configuration Space Organization".
5274 */
5275 switch (uAddress)
5276 {
5277 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5278 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5279 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5280 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5281 {
5282 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5283 return VINF_SUCCESS;
5284 }
5285 }
5286
5287 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5288 IOMMU_LOCK(pDevIns, pThisR3);
5289
5290 VBOXSTRICTRC rcStrict;
5291 switch (uAddress)
5292 {
5293 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5294 {
5295 if (!pThis->IommuBar.n.u1Enable)
5296 {
5297 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5298 if (pThis->IommuBar.n.u1Enable)
5299 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5300 else
5301 rcStrict = VINF_SUCCESS;
5302 }
5303 else
5304 {
5305 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5306 rcStrict = VINF_SUCCESS;
5307 }
5308 break;
5309 }
5310
5311 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5312 {
5313 if (!pThis->IommuBar.n.u1Enable)
5314 {
5315 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5316 pThis->IommuBar.au32[1] = u32Value;
5317 }
5318 else
5319 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5320 rcStrict = VINF_SUCCESS;
5321 break;
5322 }
5323
5324 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5325 {
5326 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5327 RT_FALL_THRU();
5328 }
5329 default:
5330 {
5331 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5332 break;
5333 }
5334 }
5335
5336 IOMMU_UNLOCK(pDevIns, pThisR3);
5337
5338 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5339 return rcStrict;
5340}
5341
5342
5343/**
5344 * @callback_method_impl{FNDBGFHANDLERDEV}
5345 */
5346static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5347{
5348 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5349 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5350 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5351
5352 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
5353
5354 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5355 /* Device Table Base Addresses (all segments). */
5356 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5357 {
5358 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5359 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5360 if (fVerbose)
5361 {
5362 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5363 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5364 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5365 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5366 }
5367 }
5368 /* Command Buffer Base Address Register. */
5369 {
5370 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5371 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5372 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5373 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5374 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5375 if (fVerbose)
5376 {
5377 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5378 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5379 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5380 cEntries, cbBuffer);
5381 }
5382 }
5383 /* Event Log Base Address Register. */
5384 {
5385 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5386 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5387 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5388 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5389 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5390 if (fVerbose)
5391 {
5392 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5393 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5394 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5395 cEntries, cbBuffer);
5396 }
5397 }
5398 /* IOMMU Control Register. */
5399 {
5400 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5401 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5402 if (fVerbose)
5403 {
5404 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5405 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5406 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5407 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5408 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5409 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5410 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5411 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5412 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5413 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5414 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5415 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5416 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5417 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5418 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5419 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5420 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5421 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5422 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5423 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5424 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5425 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5426 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5427 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5428 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5429 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5430 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5431 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5432 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5433 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5434 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5435 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5436 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5437 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5438 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5439 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5440 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5441 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5442 }
5443 }
5444 /* Exclusion Base Address Register. */
5445 {
5446 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5447 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5448 if (fVerbose)
5449 {
5450 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5451 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5452 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5453 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5454 }
5455 }
5456 /* Exclusion Range Limit Register. */
5457 {
5458 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5459 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5460 if (fVerbose)
5461 {
5462 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5463 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5464 }
5465 }
5466 /* Extended Feature Register. */
5467 {
5468 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5469 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5470 if (fVerbose)
5471 {
5472 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5473 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5474 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5475 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5476 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5477 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5478 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5479 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5480 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5481 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5482 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5483 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5484 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5485 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5486 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5487 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5488 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5489 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5490 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5491 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5492 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5493 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5494 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5495 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5496 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5497 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5498 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5499 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5500 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5501 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5502 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5503 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5504 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5505 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5506 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5507 }
5508 }
5509 /* PPR Log Base Address Register. */
5510 {
5511 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5512 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5513 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5514 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5515 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5516 if (fVerbose)
5517 {
5518 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5519 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5520 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5521 cEntries, cbBuffer);
5522 }
5523 }
5524 /* Hardware Event (Hi) Register. */
5525 {
5526 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5527 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5528 if (fVerbose)
5529 {
5530 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5531 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5532 }
5533 }
5534 /* Hardware Event (Lo) Register. */
5535 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5536 /* Hardware Event Status. */
5537 {
5538 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5539 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5540 if (fVerbose)
5541 {
5542 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5543 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5544 }
5545 }
5546 /* Guest Virtual-APIC Log Base Address Register. */
5547 {
5548 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5549 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5550 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5551 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5552 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5553 if (fVerbose)
5554 {
5555 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5556 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5557 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5558 cEntries, cbBuffer);
5559 }
5560 }
5561 /* Guest Virtual-APIC Log Tail Address Register. */
5562 {
5563 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5564 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5565 if (fVerbose)
5566 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5567 }
5568 /* PPR Log B Base Address Register. */
5569 {
5570 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5571 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5572 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5573 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5574 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5575 if (fVerbose)
5576 {
5577 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5578 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5579 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5580 cEntries, cbBuffer);
5581 }
5582 }
5583 /* Event Log B Base Address Register. */
5584 {
5585 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5586 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5587 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5588 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5589 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5590 if (fVerbose)
5591 {
5592 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5593 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5594 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5595 cEntries, cbBuffer);
5596 }
5597 }
5598 /* Device-Specific Feature Extension Register. */
5599 {
5600 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5601 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5602 if (fVerbose)
5603 {
5604 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5605 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5606 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5607 }
5608 }
5609 /* Device-Specific Control Extension Register. */
5610 {
5611 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5612 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5613 if (fVerbose)
5614 {
5615 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5616 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5617 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5618 }
5619 }
5620 /* Device-Specific Status Extension Register. */
5621 {
5622 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5623 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5624 if (fVerbose)
5625 {
5626 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5627 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5628 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5629 }
5630 }
5631 /* Miscellaneous Information Register (Lo and Hi). */
5632 {
5633 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5634 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5635 if (fVerbose)
5636 {
5637 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5638 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5639 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5640 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5641 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5642 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5643 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5644 }
5645 }
5646 /* MSI Capability Header. */
5647 {
5648 MSI_CAP_HDR_T MsiCapHdr;
5649 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5650 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5651 if (fVerbose)
5652 {
5653 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5654 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5655 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5656 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5657 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5658 }
5659 }
5660 /* MSI Address Register (Lo and Hi). */
5661 {
5662 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5663 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5664 MSIADDR MsiAddr;
5665 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5666 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5667 if (fVerbose)
5668 {
5669 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5670 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5671 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5672 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5673 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5674 }
5675 }
5676 /* MSI Data. */
5677 {
5678 MSIDATA MsiData;
5679 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5680 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5681 if (fVerbose)
5682 {
5683 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5684 MsiData.n.u8Vector);
5685 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5686 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5687 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5688 "level" : "edge");
5689 }
5690 }
5691 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5692 {
5693 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5694 MsiMapCapHdr.u32 = 0;
5695 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5696 if (fVerbose)
5697 {
5698 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5699 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5700 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5701 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5702 }
5703 }
5704 /* Performance Optimization Control Register. */
5705 {
5706 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5707 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5708 if (fVerbose)
5709 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5710 }
5711 /* XT (x2APIC) General Interrupt Control Register. */
5712 {
5713 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5714 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5715 if (fVerbose)
5716 {
5717 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5718 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5719 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5720 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5721 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5722 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5723 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5724 }
5725 }
5726 /* XT (x2APIC) PPR Interrupt Control Register. */
5727 {
5728 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5729 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5730 if (fVerbose)
5731 {
5732 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5733 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5734 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5735 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5736 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5737 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5738 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5739 }
5740 }
5741 /* XT (X2APIC) GA Log Interrupt Control Register. */
5742 {
5743 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5744 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5745 if (fVerbose)
5746 {
5747 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5748 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5749 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5750 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5751 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5752 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5753 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5754 }
5755 }
5756 /* MARC Registers. */
5757 {
5758 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5759 {
5760 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5761 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5762 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5763
5764 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5765 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5766 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5767 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5768
5769 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5770 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5771 }
5772 }
5773 /* Reserved Register. */
5774 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5775 /* Command Buffer Head Pointer Register. */
5776 {
5777 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5778 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5779 CmdBufHeadPtr.n.off);
5780 }
5781 /* Command Buffer Tail Pointer Register. */
5782 {
5783 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5784 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5785 CmdBufTailPtr.n.off);
5786 }
5787 /* Event Log Head Pointer Register. */
5788 {
5789 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5790 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5791 EvtLogHeadPtr.n.off);
5792 }
5793 /* Event Log Tail Pointer Register. */
5794 {
5795 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5796 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5797 EvtLogTailPtr.n.off);
5798 }
5799 /* Status Register. */
5800 {
5801 IOMMU_STATUS_T const Status = pThis->Status;
5802 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5803 if (fVerbose)
5804 {
5805 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5806 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5807 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5808 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5809 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5810 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5811 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5812 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5813 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5814 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5815 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5816 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5817 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5818 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5819 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5820 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5821 }
5822 }
5823 /* PPR Log Head Pointer. */
5824 {
5825 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5826 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5827 PprLogHeadPtr.n.off);
5828 }
5829 /* PPR Log Tail Pointer. */
5830 {
5831 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5832 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5833 PprLogTailPtr.n.off);
5834 }
5835 /* Guest Virtual-APIC Log Head Pointer. */
5836 {
5837 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5838 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5839 GALogHeadPtr.n.u12GALogPtr);
5840 }
5841 /* Guest Virtual-APIC Log Tail Pointer. */
5842 {
5843 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5844 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5845 GALogTailPtr.n.u12GALogPtr);
5846 }
5847 /* PPR Log B Head Pointer. */
5848 {
5849 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5850 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5851 PprLogBHeadPtr.n.off);
5852 }
5853 /* PPR Log B Tail Pointer. */
5854 {
5855 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5856 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5857 PprLogBTailPtr.n.off);
5858 }
5859 /* Event Log B Head Pointer. */
5860 {
5861 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5862 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5863 EvtLogBHeadPtr.n.off);
5864 }
5865 /* Event Log B Tail Pointer. */
5866 {
5867 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5868 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5869 EvtLogBTailPtr.n.off);
5870 }
5871 /* PPR Log Auto Response Register. */
5872 {
5873 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5874 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5875 if (fVerbose)
5876 {
5877 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5878 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5879 }
5880 }
5881 /* PPR Log Overflow Early Warning Indicator Register. */
5882 {
5883 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5884 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5885 if (fVerbose)
5886 {
5887 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5888 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5889 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5890 }
5891 }
5892 /* PPR Log Overflow Early Warning Indicator Register. */
5893 {
5894 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5895 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5896 if (fVerbose)
5897 {
5898 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5899 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5900 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5901 }
5902 }
5903}
5904
5905
5906/**
5907 * Dumps the DTE via the info callback helper.
5908 *
5909 * @param pHlp The info helper.
5910 * @param pDte The device table entry.
5911 * @param pszPrefix The string prefix.
5912 */
5913static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5914{
5915 AssertReturnVoid(pHlp);
5916 AssertReturnVoid(pDte);
5917 AssertReturnVoid(pszPrefix);
5918
5919 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5920 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5921 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5922 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5923 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5924 pDte->n.u40PageTableRootPtrLo << 12);
5925 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5926 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5927 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5928 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5929 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5930 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5931 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5932 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5933 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5934 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5935 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5936 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5937 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5938 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5939 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5940 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5941 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5942 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5943 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5944 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5945 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5946 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5947 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5948 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5949 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5950 {
5951 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
5952 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
5953 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
5954 cbIntrTable);
5955 }
5956 else
5957 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
5958 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
5959 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
5960 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
5961 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
5962 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
5963 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
5964 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
5965 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
5966 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
5967 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
5968 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
5969 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
5970 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
5971 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
5972 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
5973 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
5974 pHlp->pfnPrintf(pHlp, "\n");
5975}
5976
5977
5978/**
5979 * @callback_method_impl{FNDBGFHANDLERDEV}
5980 */
5981static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5982{
5983 if (pszArgs)
5984 {
5985 uint16_t idDevice = 0;
5986 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
5987 if (RT_SUCCESS(rc))
5988 {
5989 DTE_T Dte;
5990 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
5991 if (RT_SUCCESS(rc))
5992 {
5993 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
5994 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
5995 return;
5996 }
5997 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
5998 }
5999 else
6000 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
6001 }
6002 else
6003 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
6004}
6005
6006
6007# ifdef IOMMU_WITH_DTE_CACHE
6008/**
6009 * @callback_method_impl{FNDBGFHANDLERDEV}
6010 */
6011static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6012{
6013 RT_NOREF(pszArgs);
6014 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6015 IOMMU_CACHE_LOCK(pDevIns, pThis);
6016
6017 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
6018 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
6019 for (uint16_t i = 0; i < cDteCache; i++)
6020 {
6021 uint16_t const idDevice = pThis->aDeviceIds[i];
6022 if (idDevice)
6023 {
6024 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
6025 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6026 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6027 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6028
6029 PCDTECACHE pDteCache = &pThis->aDteCache[i];
6030 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
6031 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
6032 pHlp->pfnPrintf(pHlp, "\n");
6033 }
6034 }
6035 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6036}
6037# endif /* IOMMU_WITH_DTE_CACHE */
6038
6039
6040# ifdef IOMMU_WITH_IOTLBE_CACHE
6041/**
6042 * @callback_method_impl{FNDBGFHANDLERDEV}
6043 */
6044static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6045{
6046 if (pszArgs)
6047 {
6048 uint16_t idDomain = 0;
6049 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6050 if (RT_SUCCESS(rc))
6051 {
6052 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6053 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6054 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6055 IOTLBEINFOARG Args;
6056 Args.pIommuR3 = pThisR3;
6057 Args.pHlp = pHlp;
6058 Args.idDomain = idDomain;
6059
6060 IOMMU_CACHE_LOCK(pDevIns, pThis);
6061 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6062 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6063 }
6064 else
6065 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6066 }
6067 else
6068 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6069}
6070# endif /* IOMMU_WITH_IOTLBE_CACHE */
6071
6072
6073# ifdef IOMMU_WITH_IRTE_CACHE
6074/**
6075 * Gets the interrupt type name for an interrupt type in the IRTE.
6076 *
6077 * @returns The interrupt type name.
6078 * @param uIntrType The interrupt type (as specified in the IRTE).
6079 */
6080static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6081{
6082 switch (uIntrType)
6083 {
6084 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6085 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6086 default: return "<Reserved>";
6087 }
6088}
6089
6090
6091/**
6092 * @callback_method_impl{FNDBGFHANDLERDEV}
6093 */
6094static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6095{
6096 RT_NOREF(pszArgs);
6097
6098 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6099 IOMMU_CACHE_LOCK(pDevIns, pThis);
6100
6101 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6102 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6103 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6104 {
6105 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6106 uint32_t const uKey = pIrteCache->uKey;
6107 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6108 {
6109 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6110 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6111 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6112 idxIrte, offIrte, idDevice,
6113 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6114 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6115 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6116
6117 PCIRTE_T pIrte = &pIrteCache->Irte;
6118 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6119 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6120 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6121 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6122 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6123 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6124 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6125 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6126 pHlp->pfnPrintf(pHlp, "\n");
6127 }
6128 }
6129 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6130}
6131# endif /* IOMMU_WITH_IRTE_CACHE */
6132
6133
6134/**
6135 * @callback_method_impl{FNDBGFHANDLERDEV}
6136 */
6137static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6138{
6139 RT_NOREF(pszArgs);
6140
6141 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6142 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6143 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6144 NOREF(pPciDev);
6145
6146 uint8_t cSegments = 0;
6147 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6148 {
6149 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6150 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6151 if (GCPhysDevTab)
6152 ++cSegments;
6153 }
6154
6155 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6156 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6157 if (!cSegments)
6158 return;
6159
6160 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6161 {
6162 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6163 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6164 if (GCPhysDevTab)
6165 {
6166 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6167 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6168
6169 void *pvDevTab = RTMemAllocZ(cbDevTab);
6170 if (RT_LIKELY(pvDevTab))
6171 {
6172 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6173 if (RT_SUCCESS(rc))
6174 {
6175 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6176 {
6177 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6178 if ( pDte->n.u1Valid
6179 && pDte->n.u1TranslationValid
6180 && pDte->n.u3Mode != 0)
6181 {
6182 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6183 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6184 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6185 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6186 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6187 pHlp->pfnPrintf(pHlp, "\n");
6188 }
6189 }
6190 pHlp->pfnPrintf(pHlp, "\n");
6191 }
6192 else
6193 {
6194 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6195 cbDevTab, rc);
6196 }
6197
6198 RTMemFree(pvDevTab);
6199 }
6200 else
6201 {
6202 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6203 return;
6204 }
6205 }
6206 }
6207}
6208
6209
6210/**
6211 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6212 */
6213static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6214{
6215 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6216 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6217 LogFlowFunc(("\n"));
6218
6219 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6220 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6221 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6222 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6223 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6224 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6225 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6226
6227 /* Next, save all registers that can be modified by the guest. */
6228 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6229
6230 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6231 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6232 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6233 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6234
6235 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6236 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6237 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6238 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6239 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6240 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6241#if 0
6242 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6243#endif
6244
6245 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6246 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6247 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6248 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6249
6250 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6251 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6252
6253 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6254 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6255
6256#if 0
6257 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6258 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6259 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6260
6261 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6262#endif
6263 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6264
6265 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6266 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6267 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6268
6269 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6270 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6271 for (size_t i = 0; i < cMarcApers; i++)
6272 {
6273 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6274 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6275 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6276 }
6277
6278#if 0
6279 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6280#endif
6281
6282 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6283 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6284 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6285 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6286
6287 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6288
6289 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6290 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6291
6292 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6293 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6294
6295 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6296 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6297
6298 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6299 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6300
6301 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6302 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6303 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6304
6305 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6306}
6307
6308
6309/**
6310 * @callback_method_impl{FNSSMDEVLOADEXEC}
6311 */
6312static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6313{
6314 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6315 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6316 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6317 LogFlowFunc(("\n"));
6318
6319 /* Validate. */
6320 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6321 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6322 {
6323 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6324 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6325 }
6326
6327 /* Load ExtFeat and other read-only registers first. */
6328 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6329 AssertRCReturn(rc, rc);
6330 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6331 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6332 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6333 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6334 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6335 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6336 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6337
6338 /* IOMMU base address register. */
6339 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6340 AssertRCReturn(rc, rc);
6341 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6342
6343 /* Device table base address registers. */
6344 uint8_t cDevTabBaseAddrs;
6345 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6346 AssertRCReturn(rc, rc);
6347 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6348 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6349 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6350 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6351 {
6352 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6353 AssertRCReturn(rc, rc);
6354 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6355 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6356 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6357 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6358 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6359 }
6360
6361 /* Command buffer base address register. */
6362 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6363 AssertRCReturn(rc, rc);
6364 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6365 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6366 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6367
6368 /* Event log base address register. */
6369 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6370 AssertRCReturn(rc, rc);
6371 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6372 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6373 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6374
6375 /* Control register. */
6376 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6377 AssertRCReturn(rc, rc);
6378 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6379 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6380 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6381
6382 /* Exclusion range base address register. */
6383 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6384 AssertRCReturn(rc, rc);
6385 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6386
6387 /* Exclusion range limit register. */
6388 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6389 AssertRCReturn(rc, rc);
6390 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6391 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6392
6393#if 0
6394 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6395#endif
6396
6397 /* PPR log base address register. */
6398 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6399 AssertRCReturn(rc, rc);
6400 Assert(!pThis->ExtFeat.n.u1PprSup);
6401
6402 /* Hardware event (Hi) register. */
6403 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6404 AssertRCReturn(rc, rc);
6405
6406 /* Hardware event (Lo) register. */
6407 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6408 AssertRCReturn(rc, rc);
6409
6410 /* Hardware event status register. */
6411 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6412 AssertRCReturn(rc, rc);
6413 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6414
6415 /* Guest Virtual-APIC log base address register. */
6416 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6417 AssertRCReturn(rc, rc);
6418 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6419
6420 /* Guest Virtual-APIC log tail address register. */
6421 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6422 AssertRCReturn(rc, rc);
6423 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6424
6425 /* PPR log-B base address register. */
6426 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6427 AssertRCReturn(rc, rc);
6428 Assert(!pThis->ExtFeat.n.u1PprSup);
6429
6430 /* Event log-B base address register. */
6431 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6432 AssertRCReturn(rc, rc);
6433 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6434
6435#if 0
6436 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6437 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6438 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6439
6440 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6441#endif
6442
6443 /* Performance optimization control register. */
6444 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6445 AssertRCReturn(rc, rc);
6446 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6447
6448 /* x2APIC registers. */
6449 {
6450 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6451
6452 /* x2APIC general interrupt control register. */
6453 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6454 AssertRCReturn(rc, rc);
6455
6456 /* x2APIC PPR interrupt control register. */
6457 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6458 AssertRCReturn(rc, rc);
6459
6460 /* x2APIC GA log interrupt control register. */
6461 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6462 AssertRCReturn(rc, rc);
6463 }
6464
6465 /* MARC (Memory Access and Routing) registers. */
6466 {
6467 uint8_t cMarcApers;
6468 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6469 AssertRCReturn(rc, rc);
6470 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6471 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6472 for (uint8_t i = 0; i < cMarcApers; i++)
6473 {
6474 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6475 AssertRCReturn(rc, rc);
6476
6477 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6478 AssertRCReturn(rc, rc);
6479
6480 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6481 AssertRCReturn(rc, rc);
6482 }
6483 Assert(!pThis->ExtFeat.n.u2MarcSup);
6484 }
6485
6486#if 0
6487 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6488#endif
6489
6490 /* Command buffer head pointer register. */
6491 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6492 AssertRCReturn(rc, rc);
6493 {
6494 /*
6495 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6496 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6497 * we shouldn't see such values in the saved state.
6498 */
6499 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6500 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6501 Assert(cbBuf <= _512K);
6502 AssertLogRelMsgReturn(offBuf < cbBuf,
6503 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6504 }
6505
6506 /* Command buffer tail pointer register. */
6507 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6508 AssertRCReturn(rc, rc);
6509 {
6510 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6511 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6512 Assert(cbBuf <= _512K);
6513 AssertLogRelMsgReturn(offBuf < cbBuf,
6514 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6515 }
6516
6517 /* Event log head pointer register. */
6518 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6519 AssertRCReturn(rc, rc);
6520 {
6521 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6522 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6523 Assert(cbBuf <= _512K);
6524 AssertLogRelMsgReturn(offBuf < cbBuf,
6525 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6526 }
6527
6528 /* Event log tail pointer register. */
6529 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6530 AssertRCReturn(rc, rc);
6531 {
6532 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6533 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6534 Assert(cbBuf <= _512K);
6535 AssertLogRelMsgReturn(offBuf < cbBuf,
6536 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6537 }
6538
6539 /* Status register. */
6540 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6541 AssertRCReturn(rc, rc);
6542 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6543
6544 /* PPR log head pointer register. */
6545 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6546 AssertRCReturn(rc, rc);
6547 Assert(!pThis->ExtFeat.n.u1PprSup);
6548
6549 /* PPR log tail pointer register. */
6550 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6551 AssertRCReturn(rc, rc);
6552 Assert(!pThis->ExtFeat.n.u1PprSup);
6553
6554 /* Guest Virtual-APIC log head pointer register. */
6555 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6556 AssertRCReturn(rc, rc);
6557 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6558
6559 /* Guest Virtual-APIC log tail pointer register. */
6560 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6561 AssertRCReturn(rc, rc);
6562 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6563
6564 /* PPR log-B head pointer register. */
6565 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6566 AssertRCReturn(rc, rc);
6567 Assert(!pThis->ExtFeat.n.u1PprSup);
6568
6569 /* PPR log-B head pointer register. */
6570 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6571 AssertRCReturn(rc, rc);
6572 Assert(!pThis->ExtFeat.n.u1PprSup);
6573
6574 /* Event log-B head pointer register. */
6575 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6576 AssertRCReturn(rc, rc);
6577 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6578
6579 /* Event log-B tail pointer register. */
6580 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6581 AssertRCReturn(rc, rc);
6582 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6583
6584 /* PPR log auto response register. */
6585 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6586 AssertRCReturn(rc, rc);
6587 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6588
6589 /* PPR log overflow early indicator register. */
6590 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6591 AssertRCReturn(rc, rc);
6592 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6593
6594 /* PPR log-B overflow early indicator register. */
6595 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6596 AssertRCReturn(rc, rc);
6597 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6598
6599 /* End marker. */
6600 {
6601 uint32_t uEndMarker;
6602 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6603 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6604 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6605 rcErr);
6606 }
6607
6608 return rc;
6609}
6610
6611
6612/**
6613 * @callback_method_impl{FNSSMDEVLOADDONE}
6614 */
6615static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6616{
6617 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6618 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6619 RT_NOREF(pSSM);
6620 LogFlowFunc(("\n"));
6621
6622 /* Sanity. */
6623 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6624 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6625
6626 int rc;
6627 IOMMU_LOCK(pDevIns, pThisR3);
6628
6629 /* Map MMIO regions if the IOMMU BAR is enabled. */
6630 if (pThis->IommuBar.n.u1Enable)
6631 rc = iommuAmdR3MmioSetup(pDevIns);
6632 else
6633 rc = VINF_SUCCESS;
6634
6635 /* Wake up the command thread if commands need processing. */
6636 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6637
6638 IOMMU_UNLOCK(pDevIns, pThisR3);
6639
6640 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6641 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6642 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6643 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6644 pThis->ExtFeat.u64));
6645 return rc;
6646}
6647
6648
6649/**
6650 * @interface_method_impl{PDMDEVREG,pfnReset}
6651 */
6652static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6653{
6654 /*
6655 * Resets read-write portion of the IOMMU state.
6656 *
6657 * NOTE! State not initialized here is expected to be initialized during
6658 * device construction and remain read-only through the lifetime of the VM.
6659 */
6660 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6661 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6662 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6663 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6664 LogFlowFunc(("\n"));
6665
6666 IOMMU_LOCK(pDevIns, pThisR3);
6667
6668 RT_ZERO(pThis->aDevTabBaseAddrs);
6669
6670 pThis->CmdBufBaseAddr.u64 = 0;
6671 pThis->CmdBufBaseAddr.n.u4Len = 8;
6672
6673 pThis->EvtLogBaseAddr.u64 = 0;
6674 pThis->EvtLogBaseAddr.n.u4Len = 8;
6675
6676 pThis->Ctrl.u64 = 0;
6677 pThis->Ctrl.n.u1Coherent = 1;
6678 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6679
6680 pThis->ExclRangeBaseAddr.u64 = 0;
6681 pThis->ExclRangeLimit.u64 = 0;
6682
6683 pThis->PprLogBaseAddr.u64 = 0;
6684 pThis->PprLogBaseAddr.n.u4Len = 8;
6685
6686 pThis->HwEvtHi.u64 = 0;
6687 pThis->HwEvtLo = 0;
6688 pThis->HwEvtStatus.u64 = 0;
6689
6690 pThis->GALogBaseAddr.u64 = 0;
6691 pThis->GALogBaseAddr.n.u4Len = 8;
6692 pThis->GALogTailAddr.u64 = 0;
6693
6694 pThis->PprLogBBaseAddr.u64 = 0;
6695 pThis->PprLogBBaseAddr.n.u4Len = 8;
6696
6697 pThis->EvtLogBBaseAddr.u64 = 0;
6698 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6699
6700 pThis->PerfOptCtrl.u32 = 0;
6701
6702 pThis->XtGenIntrCtrl.u64 = 0;
6703 pThis->XtPprIntrCtrl.u64 = 0;
6704 pThis->XtGALogIntrCtrl.u64 = 0;
6705
6706 RT_ZERO(pThis->aMarcApers);
6707
6708 pThis->CmdBufHeadPtr.u64 = 0;
6709 pThis->CmdBufTailPtr.u64 = 0;
6710 pThis->EvtLogHeadPtr.u64 = 0;
6711 pThis->EvtLogTailPtr.u64 = 0;
6712
6713 pThis->Status.u64 = 0;
6714
6715 pThis->PprLogHeadPtr.u64 = 0;
6716 pThis->PprLogTailPtr.u64 = 0;
6717
6718 pThis->GALogHeadPtr.u64 = 0;
6719 pThis->GALogTailPtr.u64 = 0;
6720
6721 pThis->PprLogBHeadPtr.u64 = 0;
6722 pThis->PprLogBTailPtr.u64 = 0;
6723
6724 pThis->EvtLogBHeadPtr.u64 = 0;
6725 pThis->EvtLogBTailPtr.u64 = 0;
6726
6727 pThis->PprLogAutoResp.u64 = 0;
6728 pThis->PprLogOverflowEarly.u64 = 0;
6729 pThis->PprLogBOverflowEarly.u64 = 0;
6730
6731 pThis->IommuBar.u64 = 0;
6732 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6733 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6734
6735 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6736
6737 IOMMU_UNLOCK(pDevIns, pThisR3);
6738
6739#ifdef IOMMU_WITH_DTE_CACHE
6740 iommuAmdDteCacheRemoveAll(pDevIns);
6741#endif
6742#ifdef IOMMU_WITH_IOTLBE_CACHE
6743 iommuAmdIotlbRemoveAll(pDevIns);
6744#endif
6745#ifdef IOMMU_WITH_IRTE_CACHE
6746 iommuAmdIrteCacheRemoveAll(pDevIns);
6747#endif
6748}
6749
6750
6751/**
6752 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6753 */
6754static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6755{
6756 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6757 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6758 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6759 LogFlowFunc(("\n"));
6760
6761 IOMMU_LOCK(pDevIns, pThisR3);
6762
6763 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6764 {
6765 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6766 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6767 }
6768
6769#ifdef IOMMU_WITH_IOTLBE_CACHE
6770 if (pThisR3->paIotlbes)
6771 {
6772 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6773 pThisR3->paIotlbes = NULL;
6774 pThisR3->idxUnusedIotlbe = 0;
6775 }
6776#endif
6777
6778 IOMMU_UNLOCK(pDevIns, pThisR3);
6779 return VINF_SUCCESS;
6780}
6781
6782
6783/**
6784 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6785 */
6786static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6787{
6788 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6789 RT_NOREF(pCfg);
6790
6791 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6792 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6793 pThis->u32Magic = IOMMU_MAGIC;
6794 pThisR3->pDevInsR3 = pDevIns;
6795
6796 LogFlowFunc(("iInstance=%d\n", iInstance));
6797
6798 /*
6799 * Register the IOMMU with PDM.
6800 */
6801 PDMIOMMUREGR3 IommuReg;
6802 RT_ZERO(IommuReg);
6803 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6804 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6805 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6806 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6807 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6808 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6809 if (RT_FAILURE(rc))
6810 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6811 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6812 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6813 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6814 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6815 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6816 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6817 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6818 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6819 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
6820 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
6821 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
6822 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
6823
6824 /*
6825 * We will use PDM's critical section (via helpers) for the IOMMU device.
6826 */
6827 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6828 AssertRCReturn(rc, rc);
6829
6830 /*
6831 * Initialize read-only PCI configuration space.
6832 */
6833 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6834 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6835
6836 /* Header. */
6837 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6838 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6839 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6840 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6841 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6842 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6843 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6844 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6845 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6846 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6847 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6848 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6849 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6850 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6851
6852 /* Capability Header. */
6853 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6854 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6855 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6856 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6857 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6858 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6859 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6860 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6861 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6862 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6863 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6864
6865 /* Base Address Register. */
6866 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6867 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6868
6869 /* IOMMU Range Register. */
6870 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6871
6872 /* Misc. Information Register. */
6873 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6874 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6875 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6876 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6877 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6878 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6879 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6880 uint32_t const uMiscInfoReg1 = 0;
6881 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6882 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6883
6884 /* MSI Capability Header register. */
6885 PDMMSIREG MsiReg;
6886 RT_ZERO(MsiReg);
6887 MsiReg.cMsiVectors = 1;
6888 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6889 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6890 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6891
6892 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6893#if 0
6894 /* MSI Address Lo. */
6895 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6896 /* MSI Address Hi. */
6897 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6898 /* MSI Data. */
6899 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6900#endif
6901
6902#if 0
6903 /** @todo IOMMU: I don't know if we need to support this, enable later if
6904 * required. */
6905 /* MSI Mapping Capability Header register. */
6906 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6907 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6908 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6909 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6910 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6911 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6912 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6913#endif
6914
6915 /*
6916 * Register the PCI function with PDM.
6917 */
6918 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6919 AssertLogRelRCReturn(rc, rc);
6920
6921 /*
6922 * Register MSI support for the PCI device.
6923 * This must be done -after- registering it as a PCI device!
6924 */
6925 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6926 AssertRCReturn(rc, rc);
6927
6928 /*
6929 * Intercept PCI config. space accesses.
6930 */
6931 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6932 AssertLogRelRCReturn(rc, rc);
6933
6934 /*
6935 * Create the MMIO region.
6936 * Mapping of the region is done when software configures it via PCI config space.
6937 */
6938 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6939 NULL /* pvUser */,
6940 IOMMMIO_FLAGS_READ_DWORD_QWORD
6941 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
6942 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
6943 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
6944 "AMD-IOMMU", &pThis->hMmio);
6945 AssertLogRelRCReturn(rc, rc);
6946
6947 /*
6948 * Register saved state handlers.
6949 */
6950 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
6951 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
6952 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
6953 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
6954 AssertLogRelRCReturn(rc, rc);
6955
6956 /*
6957 * Register debugger info items.
6958 */
6959 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
6960 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
6961 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
6962#ifdef IOMMU_WITH_IOTLBE_CACHE
6963 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
6964#endif
6965#ifdef IOMMU_WITH_DTE_CACHE
6966 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
6967#endif
6968#ifdef IOMMU_WITH_IRTE_CACHE
6969 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
6970#endif
6971
6972# ifdef VBOX_WITH_STATISTICS
6973 /*
6974 * Statistics.
6975 */
6976 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
6977 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
6978
6979 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
6980 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
6981
6982 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
6983 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
6984
6985 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
6986 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
6987
6988 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
6989 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
6990
6991 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
6992 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
6993
6994 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
6995 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
6996
6997 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
6998 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
6999 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
7000 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
7001 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
7002 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
7003 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
7004 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
7005 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
7006
7007
7008 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
7009 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
7010
7011 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
7012 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
7013
7014 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
7015 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
7016
7017 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7018 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7019 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
7020 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
7021 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
7022 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
7023 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
7024
7025 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7026 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7027# endif
7028
7029 /*
7030 * Create the command thread and its event semaphore.
7031 */
7032 char szDevIommu[64];
7033 RT_ZERO(szDevIommu);
7034 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
7035 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
7036 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
7037 AssertLogRelRCReturn(rc, rc);
7038
7039 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7040 AssertLogRelRCReturn(rc, rc);
7041
7042#ifdef IOMMU_WITH_DTE_CACHE
7043 /*
7044 * Initialize the critsect of the cache.
7045 */
7046 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7047 AssertLogRelRCReturn(rc, rc);
7048
7049 /* Several places in this code relies on this basic assumption - assert it! */
7050 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7051#endif
7052
7053#ifdef IOMMU_WITH_IOTLBE_CACHE
7054 /*
7055 * Allocate IOTLB entries.
7056 * This is allocated upfront since we expect a relatively small number of entries,
7057 * is more cache-line efficient and easier to track least recently used entries for
7058 * eviction when the cache is full. This also avoids unpredictable behavior during
7059 * the lifetime of the VM if the hyperheap gets full.
7060 */
7061 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7062 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7063 if (!pThisR3->paIotlbes)
7064 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7065 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7066 RTListInit(&pThisR3->LstLruIotlbe);
7067 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7068#endif
7069
7070 /*
7071 * Initialize read-only registers.
7072 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7073 */
7074 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7075 pThis->ExtFeat.u64 = 0;
7076 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7077 //pThis->ExtFeat.n.u1PprSup = 0;
7078 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7079 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7080 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7081 pThis->ExtFeat.n.u1InvAllSup = 1;
7082 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7083 pThis->ExtFeat.n.u1HwErrorSup = 1;
7084 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7085 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7086 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7087 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7088 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7089 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7090 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7091 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7092 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7093 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7094 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7095 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7096 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7097 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7098 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7099 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7100 //pThis->ExtFeat.n.u2MarcSup = 0;
7101 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7102 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7103 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7104 //pThis->ExtFeat.n.u1GstIoSup = 0;
7105 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7106 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7107 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7108 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7109 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7110 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7111 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7112
7113 pThis->DevSpecificFeat.u64 = 0;
7114 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7115 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7116
7117 pThis->DevSpecificCtrl.u64 = 0;
7118 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7119 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7120
7121 pThis->DevSpecificStatus.u64 = 0;
7122 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7123 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7124
7125 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7126
7127 pThis->RsvdReg = 0;
7128
7129 /*
7130 * Initialize parts of the IOMMU state as it would during reset.
7131 * Also initializes non-zero initial values like IRTE cache keys.
7132 * Must be called -after- initializing PCI config. space registers.
7133 */
7134 iommuAmdR3Reset(pDevIns);
7135
7136 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7137 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7138 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7139 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7140 pThis->ExtFeat.u64));
7141 return VINF_SUCCESS;
7142}
7143
7144#else
7145
7146/**
7147 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7148 */
7149static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7150{
7151 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7152 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7153 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7154 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7155
7156 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7157 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7158 AssertRCReturn(rc, rc);
7159
7160 /* Set up the MMIO RZ handlers. */
7161 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7162 AssertRCReturn(rc, rc);
7163
7164 /* Set up the IOMMU RZ callbacks. */
7165 PDMIOMMUREGCC IommuReg;
7166 RT_ZERO(IommuReg);
7167 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7168 IommuReg.idxIommu = pThis->idxIommu;
7169 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7170 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7171 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7172 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7173 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7174 AssertRCReturn(rc, rc);
7175 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7176 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7177 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7178 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
7179 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
7180 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
7181 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
7182 return VINF_SUCCESS;
7183}
7184#endif
7185
7186
7187/**
7188 * The device registration structure.
7189 */
7190const PDMDEVREG g_DeviceIommuAmd =
7191{
7192 /* .u32Version = */ PDM_DEVREG_VERSION,
7193 /* .uReserved0 = */ 0,
7194 /* .szName = */ "iommu-amd",
7195 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7196 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7197 /* .cMaxInstances = */ 1,
7198 /* .uSharedVersion = */ 42,
7199 /* .cbInstanceShared = */ sizeof(IOMMU),
7200 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7201 /* .cbInstanceRC = */ sizeof(IOMMURC),
7202 /* .cMaxPciDevices = */ 1,
7203 /* .cMaxMsixVectors = */ 0,
7204 /* .pszDescription = */ "IOMMU (AMD)",
7205#if defined(IN_RING3)
7206 /* .pszRCMod = */ "VBoxDDRC.rc",
7207 /* .pszR0Mod = */ "VBoxDDR0.r0",
7208 /* .pfnConstruct = */ iommuAmdR3Construct,
7209 /* .pfnDestruct = */ iommuAmdR3Destruct,
7210 /* .pfnRelocate = */ NULL,
7211 /* .pfnMemSetup = */ NULL,
7212 /* .pfnPowerOn = */ NULL,
7213 /* .pfnReset = */ iommuAmdR3Reset,
7214 /* .pfnSuspend = */ NULL,
7215 /* .pfnResume = */ NULL,
7216 /* .pfnAttach = */ NULL,
7217 /* .pfnDetach = */ NULL,
7218 /* .pfnQueryInterface = */ NULL,
7219 /* .pfnInitComplete = */ NULL,
7220 /* .pfnPowerOff = */ NULL,
7221 /* .pfnSoftReset = */ NULL,
7222 /* .pfnReserved0 = */ NULL,
7223 /* .pfnReserved1 = */ NULL,
7224 /* .pfnReserved2 = */ NULL,
7225 /* .pfnReserved3 = */ NULL,
7226 /* .pfnReserved4 = */ NULL,
7227 /* .pfnReserved5 = */ NULL,
7228 /* .pfnReserved6 = */ NULL,
7229 /* .pfnReserved7 = */ NULL,
7230#elif defined(IN_RING0)
7231 /* .pfnEarlyConstruct = */ NULL,
7232 /* .pfnConstruct = */ iommuAmdRZConstruct,
7233 /* .pfnDestruct = */ NULL,
7234 /* .pfnFinalDestruct = */ NULL,
7235 /* .pfnRequest = */ NULL,
7236 /* .pfnReserved0 = */ NULL,
7237 /* .pfnReserved1 = */ NULL,
7238 /* .pfnReserved2 = */ NULL,
7239 /* .pfnReserved3 = */ NULL,
7240 /* .pfnReserved4 = */ NULL,
7241 /* .pfnReserved5 = */ NULL,
7242 /* .pfnReserved6 = */ NULL,
7243 /* .pfnReserved7 = */ NULL,
7244#elif defined(IN_RC)
7245 /* .pfnConstruct = */ iommuAmdRZConstruct,
7246 /* .pfnReserved0 = */ NULL,
7247 /* .pfnReserved1 = */ NULL,
7248 /* .pfnReserved2 = */ NULL,
7249 /* .pfnReserved3 = */ NULL,
7250 /* .pfnReserved4 = */ NULL,
7251 /* .pfnReserved5 = */ NULL,
7252 /* .pfnReserved6 = */ NULL,
7253 /* .pfnReserved7 = */ NULL,
7254#else
7255# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7256#endif
7257 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7258};
7259
7260#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7261
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