VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuAmd.cpp@ 90031

Last change on this file since 90031 was 90031, checked in by vboxsync, 3 years ago

AMD IOMMU: bugref:9654 Build fix.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 308.4 KB
Line 
1/* $Id: DevIommuAmd.cpp 90031 2021-07-05 14:49:56Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - AMD implementation.
4 */
5
6/*
7 * Copyright (C) 2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include <VBox/msi.h>
24#include <VBox/iommu-amd.h>
25#include <VBox/vmm/pdmdev.h>
26
27#include <iprt/x86.h>
28#include <iprt/string.h>
29#include <iprt/avl.h>
30#ifdef IN_RING3
31# include <iprt/mem.h>
32#endif
33
34#include "VBoxDD.h"
35#include "DevIommuAmd.h"
36
37
38/*********************************************************************************************************************************
39* Defined Constants And Macros *
40*********************************************************************************************************************************/
41/** Release log prefix string. */
42#define IOMMU_LOG_PFX "AMD-IOMMU"
43/** The current saved state version. */
44#define IOMMU_SAVED_STATE_VERSION 1
45/** The IOMMU device instance magic. */
46#define IOMMU_MAGIC 0x10acce55
47
48/** Enable the IOTLBE cache only in ring-3 for now, see @bugref{9654#c95}. */
49#ifdef IN_RING3
50//# define IOMMU_WITH_IOTLBE_CACHE /* Disabled for now, see @bugref{9654#c107}. */
51#endif
52/** Enable the interrupt cache. */
53#define IOMMU_WITH_IRTE_CACHE
54
55/* The DTE cache is mandatory for the IOTLB or interrupt cache to work. */
56#if defined(IOMMU_WITH_IOTLBE_CACHE) || defined(IOMMU_WITH_IRTE_CACHE)
57# define IOMMU_WITH_DTE_CACHE
58/** The maximum number of device IDs in the cache. */
59# define IOMMU_DEV_CACHE_COUNT 16
60/** An empty device ID. */
61# define IOMMU_DTE_CACHE_KEY_NIL 0
62#endif
63
64#ifdef IOMMU_WITH_IRTE_CACHE
65/** The maximum number of IRTE cache entries. */
66# define IOMMU_IRTE_CACHE_COUNT 32
67/** A NIL IRTE cache entry key. */
68# define IOMMU_IRTE_CACHE_KEY_NIL (~(uint32_t)0U)
69/** Gets the device ID from an IRTE cache entry key. */
70#define IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(a_Key) RT_HIWORD(a_Key)
71/** Gets the IOVA from the IOTLB entry key. */
72# define IOMMU_IRTE_CACHE_KEY_GET_OFF(a_Key) RT_LOWORD(a_Key)
73/** Makes an IRTE cache entry key.
74 *
75 * Bits 31:16 is the device ID (Bus, Device, Function).
76 * Bits 15:0 is the the offset into the IRTE table.
77 */
78# define IOMMU_IRTE_CACHE_KEY_MAKE(a_DevId, a_off) RT_MAKE_U32(a_off, a_DevId)
79#endif /* IOMMU_WITH_IRTE_CACHE */
80
81#ifdef IOMMU_WITH_IOTLBE_CACHE
82/** The maximum number of IOTLB entries. */
83# define IOMMU_IOTLBE_MAX 96
84/** The mask of bits covering the domain ID in the IOTLBE key. */
85# define IOMMU_IOTLB_DOMAIN_ID_MASK UINT64_C(0xffffff0000000000)
86/** The mask of bits covering the IOVA in the IOTLBE key. */
87# define IOMMU_IOTLB_IOVA_MASK (~IOMMU_IOTLB_DOMAIN_ID_MASK)
88/** The number of bits to shift for the domain ID of the IOTLBE key. */
89# define IOMMU_IOTLB_DOMAIN_ID_SHIFT 40
90/** A NIL IOTLB key. */
91# define IOMMU_IOTLB_KEY_NIL UINT64_C(0)
92/** Gets the domain ID from an IOTLB entry key. */
93# define IOMMU_IOTLB_KEY_GET_DOMAIN_ID(a_Key) ((a_Key) >> IOMMU_IOTLB_DOMAIN_ID_SHIFT)
94/** Gets the IOVA from the IOTLB entry key. */
95# define IOMMU_IOTLB_KEY_GET_IOVA(a_Key) (((a_Key) & IOMMU_IOTLB_IOVA_MASK) << X86_PAGE_4K_SHIFT)
96/** Makes an IOTLB entry key.
97 *
98 * Address bits 63:52 of the IOVA are zero extended, so top 12 bits are free.
99 * Address bits 11:0 of the IOVA are offset into the minimum page size of 4K,
100 * so bottom 12 bits are free.
101 *
102 * Thus we use the top 24 bits of key to hold bits 15:0 of the domain ID.
103 * We use the bottom 40 bits of the key to hold bits 51:12 of the IOVA.
104 */
105# define IOMMU_IOTLB_KEY_MAKE(a_DomainId, a_uIova) ( ((uint64_t)(a_DomainId) << IOMMU_IOTLB_DOMAIN_ID_SHIFT) \
106 | (((a_uIova) >> X86_PAGE_4K_SHIFT) & IOMMU_IOTLB_IOVA_MASK))
107#endif /* IOMMU_WITH_IOTLBE_CACHE */
108
109#ifdef IOMMU_WITH_DTE_CACHE
110/** @name IOMMU_DTE_CACHE_F_XXX: DTE cache flags.
111 *
112 * Some of these flags are "basic" i.e. they correspond directly to their bits in
113 * the DTE. The rest of the flags are based on checks or operations on several DTE
114 * bits.
115 *
116 * The basic flags are:
117 * - VALID (DTE.V)
118 * - IO_PERM_READ (DTE.IR)
119 * - IO_PERM_WRITE (DTE.IW)
120 * - IO_PERM_RSVD (bit following DTW.IW reserved for future & to keep
121 * masking consistent)
122 * - SUPPRESS_ALL_IOPF (DTE.SA)
123 * - SUPPRESS_IOPF (DTE.SE)
124 * - INTR_MAP_VALID (DTE.IV)
125 * - IGNORE_UNMAPPED_INTR (DTE.IG)
126 *
127 * @see iommuAmdGetBasicDevFlags()
128 * @{ */
129/** The DTE is present. */
130# define IOMMU_DTE_CACHE_F_PRESENT RT_BIT(0)
131/** The DTE is valid. */
132# define IOMMU_DTE_CACHE_F_VALID RT_BIT(1)
133/** The DTE permissions apply for address translations. */
134# define IOMMU_DTE_CACHE_F_IO_PERM RT_BIT(2)
135/** DTE permission - I/O read allowed. */
136# define IOMMU_DTE_CACHE_F_IO_PERM_READ RT_BIT(3)
137/** DTE permission - I/O write allowed. */
138# define IOMMU_DTE_CACHE_F_IO_PERM_WRITE RT_BIT(4)
139/** DTE permission - reserved. */
140# define IOMMU_DTE_CACHE_F_IO_PERM_RSVD RT_BIT(5)
141/** Address translation required. */
142# define IOMMU_DTE_CACHE_F_ADDR_TRANSLATE RT_BIT(6)
143/** Suppress all I/O page faults. */
144# define IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF RT_BIT(7)
145/** Suppress I/O page faults. */
146# define IOMMU_DTE_CACHE_F_SUPPRESS_IOPF RT_BIT(8)
147/** Interrupt map valid. */
148# define IOMMU_DTE_CACHE_F_INTR_MAP_VALID RT_BIT(9)
149/** Ignore unmapped interrupts. */
150# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR RT_BIT(10)
151/** An I/O page fault has been raised for this device. */
152# define IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED RT_BIT(11)
153/** Fixed and arbitrary interrupt control: Target Abort. */
154# define IOMMU_DTE_CACHE_F_INTR_CTRL_TARGET_ABORT RT_BIT(12)
155/** Fixed and arbitrary interrupt control: Forward unmapped. */
156# define IOMMU_DTE_CACHE_F_INTR_CTRL_FWD_UNMAPPED RT_BIT(13)
157/** Fixed and arbitrary interrupt control: Remapped. */
158# define IOMMU_DTE_CACHE_F_INTR_CTRL_REMAPPED RT_BIT(14)
159/** Fixed and arbitrary interrupt control: Reserved. */
160# define IOMMU_DTE_CACHE_F_INTR_CTRL_RSVD RT_BIT(15)
161/** @} */
162
163/** The number of bits to shift I/O device flags for DTE permissions. */
164# define IOMMU_DTE_CACHE_F_IO_PERM_SHIFT 3
165/** The mask of DTE permissions in I/O device flags. */
166# define IOMMU_DTE_CACHE_F_IO_PERM_MASK 0x3
167/** The number of bits to shift I/O device flags for interrupt control bits. */
168# define IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT 12
169/** The mask of interrupt control bits in I/O device flags. */
170# define IOMMU_DTE_CACHE_F_INTR_CTRL_MASK 0x3
171/** The number of bits to shift for ignore-unmapped interrupts bit. */
172# define IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR_SHIFT 10
173
174/** Acquires the cache lock. */
175#ifdef IN_RING3
176# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VERR_IGNORED)
177#else
178# define IOMMU_CACHE_LOCK(a_pDevIns, a_pThis) \
179 do { \
180 int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSectCache, VINF_SUCCESS); \
181 AssertRC(rcLock); \
182 } while (0)
183#endif
184
185/** Releases the cache lock. */
186# define IOMMU_CACHE_UNLOCK(a_pDevIns, a_pThis) PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSectCache)
187#endif /* IOMMU_WITH_DTE_CACHE */
188
189/** Acquires the PDM lock (returns a_rcBusy on contention). */
190#define IOMMU_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
191 do { \
192 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)); \
193 if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
194 { /* likely */ } \
195 else \
196 return rcLock; \
197 } while (0)
198
199/** Acquires the PDM lock (shouldn't really fail). */
200#ifdef IN_RING3
201# define IOMMU_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
202#else
203# define IOMMU_LOCK(a_pDevIns, a_pThisCC) \
204 do { \
205 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
206 AssertRC(rcLock); \
207 } while (0)
208#endif
209
210/** Checks if the current thread owns the PDM lock. */
211# define IOMMU_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
212 do \
213 { \
214 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner((a_pDevIns))); \
215 NOREF(a_pThisCC); \
216 } while (0)
217
218/** Releases the PDM lock. */
219# define IOMMU_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock((a_pDevIns))
220
221/** Gets the maximum valid IOVA for the given I/O page-table level. */
222#define IOMMU_GET_MAX_VALID_IOVA(a_Level) ((X86_PAGE_4K_SIZE << ((a_Level) * 9)) - 1)
223
224
225/*********************************************************************************************************************************
226* Structures and Typedefs *
227*********************************************************************************************************************************/
228/**
229 * IOMMU operation (transaction).
230 */
231typedef enum IOMMUOP
232{
233 /** Address translation request. */
234 IOMMUOP_TRANSLATE_REQ = 0,
235 /** Memory read request. */
236 IOMMUOP_MEM_READ,
237 /** Memory write request. */
238 IOMMUOP_MEM_WRITE,
239 /** Interrupt request. */
240 IOMMUOP_INTR_REQ,
241 /** Command. */
242 IOMMUOP_CMD
243} IOMMUOP;
244/** Pointer to a IOMMU operation. */
245typedef IOMMUOP *PIOMMUOP;
246
247/**
248 * I/O page lookup.
249 */
250typedef struct IOPAGELOOKUP
251{
252 /** The translated system physical address. */
253 RTGCPHYS GCPhysSpa;
254 /** The number of offset bits in the system physical address. */
255 uint8_t cShift;
256 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
257 uint8_t fPerm;
258} IOPAGELOOKUP;
259/** Pointer to an I/O page lookup. */
260typedef IOPAGELOOKUP *PIOPAGELOOKUP;
261/** Pointer to a const I/O page lookup. */
262typedef IOPAGELOOKUP const *PCIOPAGELOOKUP;
263
264/**
265 * I/O address range.
266 */
267typedef struct IOADDRRANGE
268{
269 /** The address (virtual or physical). */
270 uint64_t uAddr;
271 /** The size of the access in bytes. */
272 size_t cb;
273 /** The I/O permissions for this translation, see IOMMU_IO_PERM_XXX. */
274 uint8_t fPerm;
275} IOADDRRANGE;
276/** Pointer to an I/O address range. */
277typedef IOADDRRANGE *PIOADDRRANGE;
278/** Pointer to a const I/O address range. */
279typedef IOADDRRANGE const *PCIOADDRRANGE;
280
281#ifdef IOMMU_WITH_DTE_CACHE
282/**
283 * Device Table Entry Cache.
284 */
285typedef struct DTECACHE
286{
287 /** This device's flags, see IOMMU_DTE_CACHE_F_XXX. */
288 uint16_t fFlags;
289 /** The domain ID assigned for this device by software. */
290 uint16_t idDomain;
291} DTECACHE;
292/** Pointer to an I/O device struct. */
293typedef DTECACHE *PDTECACHE;
294/** Pointer to a const I/O device struct. */
295typedef DTECACHE *PCDTECACHE;
296AssertCompileSize(DTECACHE, 4);
297#endif /* IOMMU_WITH_DTE_CACHE */
298
299#ifdef IOMMU_WITH_IOTLBE_CACHE
300/**
301 * I/O TLB Entry.
302 * Keep this as small and aligned as possible.
303 */
304typedef struct IOTLBE
305{
306 /** The AVL tree node. */
307 AVLU64NODECORE Core;
308 /** The least recently used (LRU) list node. */
309 RTLISTNODE NdLru;
310 /** The I/O page lookup results of the translation. */
311 IOPAGELOOKUP PageLookup;
312 /** Whether the entry needs to be evicted from the cache. */
313 bool fEvictPending;
314} IOTLBE;
315/** Pointer to an IOMMU I/O TLB entry struct. */
316typedef IOTLBE *PIOTLBE;
317/** Pointer to a const IOMMU I/O TLB entry struct. */
318typedef IOTLBE const *PCIOTLBE;
319AssertCompileSizeAlignment(IOTLBE, 8);
320AssertCompileMemberOffset(IOTLBE, Core, 0);
321#endif /* IOMMU_WITH_IOTLBE_CACHE */
322
323#ifdef IOMMU_WITH_IRTE_CACHE
324/**
325 * Interrupt Remap Table Entry Cache.
326 */
327typedef struct IRTECACHE
328{
329 /** The key, see IOMMU_IRTE_CACHE_KEY_MAKE. */
330 uint32_t uKey;
331 /** The IRTE. */
332 IRTE_T Irte;
333} IRTECACHE;
334/** Pointer to an IRTE cache struct. */
335typedef IRTECACHE *PIRTECACHE;
336/** Pointer to a const IRTE cache struct. */
337typedef IRTECACHE const *PCIRTECACHE;
338AssertCompileSizeAlignment(IRTECACHE, 4);
339#endif /* IOMMU_WITH_IRTE_CACHE */
340
341/**
342 * The shared IOMMU device state.
343 */
344typedef struct IOMMU
345{
346 /** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
347 uint32_t idxIommu;
348 /** IOMMU magic. */
349 uint32_t u32Magic;
350
351 /** The MMIO handle. */
352 IOMMMIOHANDLE hMmio;
353 /** The event semaphore the command thread waits on. */
354 SUPSEMEVENT hEvtCmdThread;
355 /** Whether the command thread has been signaled for wake up. */
356 bool volatile fCmdThreadSignaled;
357 /** Padding. */
358 bool afPadding0[3];
359 /** The IOMMU PCI address. */
360 PCIBDF uPciAddress;
361
362#ifdef IOMMU_WITH_DTE_CACHE
363 /** The critsect that protects the cache from concurrent access. */
364 PDMCRITSECT CritSectCache;
365 /** Array of device IDs. */
366 uint16_t aDeviceIds[IOMMU_DEV_CACHE_COUNT];
367 /** Array of DTE cache entries. */
368 DTECACHE aDteCache[IOMMU_DEV_CACHE_COUNT];
369#endif
370#ifdef IOMMU_WITH_IRTE_CACHE
371 /** Array of IRTE cache entries. */
372 IRTECACHE aIrteCache[IOMMU_IRTE_CACHE_COUNT];
373#endif
374
375 /** @name PCI: Base capability block registers.
376 * @{ */
377 IOMMU_BAR_T IommuBar; /**< IOMMU base address register. */
378 /** @} */
379
380 /** @name MMIO: Control and status registers.
381 * @{ */
382 DEV_TAB_BAR_T aDevTabBaseAddrs[8]; /**< Device table base address registers. */
383 CMD_BUF_BAR_T CmdBufBaseAddr; /**< Command buffer base address register. */
384 EVT_LOG_BAR_T EvtLogBaseAddr; /**< Event log base address register. */
385 IOMMU_CTRL_T Ctrl; /**< IOMMU control register. */
386 IOMMU_EXCL_RANGE_BAR_T ExclRangeBaseAddr; /**< IOMMU exclusion range base register. */
387 IOMMU_EXCL_RANGE_LIMIT_T ExclRangeLimit; /**< IOMMU exclusion range limit. */
388 IOMMU_EXT_FEAT_T ExtFeat; /**< IOMMU extended feature register. */
389 /** @} */
390
391 /** @name MMIO: Peripheral Page Request (PPR) Log registers.
392 * @{ */
393 PPR_LOG_BAR_T PprLogBaseAddr; /**< PPR Log base address register. */
394 IOMMU_HW_EVT_HI_T HwEvtHi; /**< IOMMU hardware event register (Hi). */
395 IOMMU_HW_EVT_LO_T HwEvtLo; /**< IOMMU hardware event register (Lo). */
396 IOMMU_HW_EVT_STATUS_T HwEvtStatus; /**< IOMMU hardware event status. */
397 /** @} */
398
399 /** @todo IOMMU: SMI filter. */
400
401 /** @name MMIO: Guest Virtual-APIC Log registers.
402 * @{ */
403 GALOG_BAR_T GALogBaseAddr; /**< Guest Virtual-APIC Log base address register. */
404 GALOG_TAIL_ADDR_T GALogTailAddr; /**< Guest Virtual-APIC Log Tail address register. */
405 /** @} */
406
407 /** @name MMIO: Alternate PPR and Event Log registers.
408 * @{ */
409 PPR_LOG_B_BAR_T PprLogBBaseAddr; /**< PPR Log B base address register. */
410 EVT_LOG_B_BAR_T EvtLogBBaseAddr; /**< Event Log B base address register. */
411 /** @} */
412
413 /** @name MMIO: Device-specific feature registers.
414 * @{ */
415 DEV_SPECIFIC_FEAT_T DevSpecificFeat; /**< Device-specific feature extension register (DSFX). */
416 DEV_SPECIFIC_CTRL_T DevSpecificCtrl; /**< Device-specific control extension register (DSCX). */
417 DEV_SPECIFIC_STATUS_T DevSpecificStatus; /**< Device-specific status extension register (DSSX). */
418 /** @} */
419
420 /** @name MMIO: MSI Capability Block registers.
421 * @{ */
422 MSI_MISC_INFO_T MiscInfo; /**< MSI Misc. info registers / MSI Vector registers. */
423 /** @} */
424
425 /** @name MMIO: Performance Optimization Control registers.
426 * @{ */
427 IOMMU_PERF_OPT_CTRL_T PerfOptCtrl; /**< IOMMU Performance optimization control register. */
428 /** @} */
429
430 /** @name MMIO: x2APIC Control registers.
431 * @{ */
432 IOMMU_XT_GEN_INTR_CTRL_T XtGenIntrCtrl; /**< IOMMU X2APIC General interrupt control register. */
433 IOMMU_XT_PPR_INTR_CTRL_T XtPprIntrCtrl; /**< IOMMU X2APIC PPR interrupt control register. */
434 IOMMU_XT_GALOG_INTR_CTRL_T XtGALogIntrCtrl; /**< IOMMU X2APIC Guest Log interrupt control register. */
435 /** @} */
436
437 /** @name MMIO: Memory Address Routing & Control (MARC) registers.
438 * @{ */
439 MARC_APER_T aMarcApers[4]; /**< MARC Aperture Registers. */
440 /** @} */
441
442 /** @name MMIO: Reserved register.
443 * @{ */
444 IOMMU_RSVD_REG_T RsvdReg; /**< IOMMU Reserved Register. */
445 /** @} */
446
447 /** @name MMIO: Command and Event Log pointer registers.
448 * @{ */
449 CMD_BUF_HEAD_PTR_T CmdBufHeadPtr; /**< Command buffer head pointer register. */
450 CMD_BUF_TAIL_PTR_T CmdBufTailPtr; /**< Command buffer tail pointer register. */
451 EVT_LOG_HEAD_PTR_T EvtLogHeadPtr; /**< Event log head pointer register. */
452 EVT_LOG_TAIL_PTR_T EvtLogTailPtr; /**< Event log tail pointer register. */
453 /** @} */
454
455 /** @name MMIO: Command and Event Status register.
456 * @{ */
457 IOMMU_STATUS_T Status; /**< IOMMU status register. */
458 /** @} */
459
460 /** @name MMIO: PPR Log Head and Tail pointer registers.
461 * @{ */
462 PPR_LOG_HEAD_PTR_T PprLogHeadPtr; /**< IOMMU PPR log head pointer register. */
463 PPR_LOG_TAIL_PTR_T PprLogTailPtr; /**< IOMMU PPR log tail pointer register. */
464 /** @} */
465
466 /** @name MMIO: Guest Virtual-APIC Log Head and Tail pointer registers.
467 * @{ */
468 GALOG_HEAD_PTR_T GALogHeadPtr; /**< Guest Virtual-APIC log head pointer register. */
469 GALOG_TAIL_PTR_T GALogTailPtr; /**< Guest Virtual-APIC log tail pointer register. */
470 /** @} */
471
472 /** @name MMIO: PPR Log B Head and Tail pointer registers.
473 * @{ */
474 PPR_LOG_B_HEAD_PTR_T PprLogBHeadPtr; /**< PPR log B head pointer register. */
475 PPR_LOG_B_TAIL_PTR_T PprLogBTailPtr; /**< PPR log B tail pointer register. */
476 /** @} */
477
478 /** @name MMIO: Event Log B Head and Tail pointer registers.
479 * @{ */
480 EVT_LOG_B_HEAD_PTR_T EvtLogBHeadPtr; /**< Event log B head pointer register. */
481 EVT_LOG_B_TAIL_PTR_T EvtLogBTailPtr; /**< Event log B tail pointer register. */
482 /** @} */
483
484 /** @name MMIO: PPR Log Overflow protection registers.
485 * @{ */
486 PPR_LOG_AUTO_RESP_T PprLogAutoResp; /**< PPR Log Auto Response register. */
487 PPR_LOG_OVERFLOW_EARLY_T PprLogOverflowEarly; /**< PPR Log Overflow Early Indicator register. */
488 PPR_LOG_B_OVERFLOW_EARLY_T PprLogBOverflowEarly; /**< PPR Log B Overflow Early Indicator register. */
489 /** @} */
490
491 /** @todo IOMMU: IOMMU Event counter registers. */
492
493#ifdef VBOX_WITH_STATISTICS
494 /** @name IOMMU: Stat counters.
495 * @{ */
496 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
497 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
498 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
499 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
500
501 STAMCOUNTER StatMsiRemapR3; /**< Number of MSI remap requests in R3. */
502 STAMCOUNTER StatMsiRemapRZ; /**< Number of MSI remap requests in RZ. */
503
504 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
505 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
506 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
507 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
508
509 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
510 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
511 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
512 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
513
514 STAMCOUNTER StatCmd; /**< Number of commands processed in total. */
515 STAMCOUNTER StatCmdCompWait; /**< Number of Completion Wait commands processed. */
516 STAMCOUNTER StatCmdInvDte; /**< Number of Invalidate DTE commands processed. */
517 STAMCOUNTER StatCmdInvIommuPages; /**< Number of Invalidate IOMMU pages commands processed. */
518 STAMCOUNTER StatCmdInvIotlbPages; /**< Number of Invalidate IOTLB pages commands processed. */
519 STAMCOUNTER StatCmdInvIntrTable; /**< Number of Invalidate Interrupt Table commands processed. */
520 STAMCOUNTER StatCmdPrefIommuPages; /**< Number of Prefetch IOMMU Pages commands processed. */
521 STAMCOUNTER StatCmdCompletePprReq; /**< Number of Complete PPR Requests commands processed. */
522 STAMCOUNTER StatCmdInvIommuAll; /**< Number of Invalidate IOMMU All commands processed. */
523
524 STAMCOUNTER StatIotlbeCached; /**< Number of IOTLB entries in the cache. */
525 STAMCOUNTER StatIotlbeLazyEvictReuse; /**< Number of IOTLB entries re-used after lazy eviction. */
526
527 STAMPROFILEADV StatProfDteLookup; /**< Profiling of I/O page walk (from memory). */
528 STAMPROFILEADV StatProfIotlbeLookup; /**< Profiling of IOTLB entry lookup (from cache). */
529
530 STAMPROFILEADV StatProfIrteLookup; /**< Profiling of IRTE entry lookup (from memory). */
531 STAMPROFILEADV StatProfIrteCacheLookup; /**< Profiling of IRTE entry lookup (from cache). */
532
533 STAMCOUNTER StatAccessCacheHit; /**< Number of IOTLB cache hits. */
534 STAMCOUNTER StatAccessCacheHitFull; /**< Number of accesses that were fully looked up from the cache. */
535 STAMCOUNTER StatAccessCacheMiss; /**< Number of cache misses (resulting in DTE lookups). */
536 STAMCOUNTER StatAccessCacheNonContig; /**< Number of cache accesses resulting in non-contiguous access. */
537 STAMCOUNTER StatAccessCachePermDenied; /**< Number of cache accesses resulting in insufficient permissions. */
538 STAMCOUNTER StatAccessDteNonContig; /**< Number of DTE accesses resulting in non-contiguous access. */
539 STAMCOUNTER StatAccessDtePermDenied; /**< Number of DTE accesses resulting in insufficient permissions. */
540
541 STAMCOUNTER StatIntrCacheHit; /**< Number of interrupt cache hits. */
542 STAMCOUNTER StatIntrCacheMiss; /**< Number of interrupt cache misses. */
543
544 STAMCOUNTER StatNonStdPageSize; /**< Number of non-standard page size translations. */
545 STAMCOUNTER StatIopfs; /**< Number of I/O page faults. */
546 /** @} */
547#endif
548} IOMMU;
549/** Pointer to the IOMMU device state. */
550typedef IOMMU *PIOMMU;
551/** Pointer to the const IOMMU device state. */
552typedef const IOMMU *PCIOMMU;
553AssertCompileMemberAlignment(IOMMU, hMmio, 8);
554#ifdef IOMMU_WITH_DTE_CACHE
555AssertCompileMemberAlignment(IOMMU, CritSectCache, 8);
556AssertCompileMemberAlignment(IOMMU, aDeviceIds, 8);
557AssertCompileMemberAlignment(IOMMU, aDteCache, 8);
558#endif
559#ifdef IOMMU_WITH_IRTE_CACHE
560AssertCompileMemberAlignment(IOMMU, aIrteCache, 8);
561#endif
562AssertCompileMemberAlignment(IOMMU, IommuBar, 8);
563AssertCompileMemberAlignment(IOMMU, aDevTabBaseAddrs, 8);
564AssertCompileMemberAlignment(IOMMU, CmdBufHeadPtr, 8);
565AssertCompileMemberAlignment(IOMMU, Status, 8);
566
567/**
568 * The ring-3 IOMMU device state.
569 */
570typedef struct IOMMUR3
571{
572 /** Device instance. */
573 PPDMDEVINSR3 pDevInsR3;
574 /** The IOMMU helpers. */
575 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
576 /** The command thread handle. */
577 R3PTRTYPE(PPDMTHREAD) pCmdThread;
578#ifdef IOMMU_WITH_IOTLBE_CACHE
579 /** Pointer to array of pre-allocated IOTLBEs. */
580 PIOTLBE paIotlbes;
581 /** Maps [DomainId,Iova] to [IOTLBE]. */
582 AVLU64TREE TreeIotlbe;
583 /** LRU list anchor for IOTLB entries. */
584 RTLISTANCHOR LstLruIotlbe;
585 /** Index of the next unused IOTLB. */
586 uint32_t idxUnusedIotlbe;
587 /** Number of cached IOTLB entries in the tree. */
588 uint32_t cCachedIotlbes;
589#endif
590} IOMMUR3;
591/** Pointer to the ring-3 IOMMU device state. */
592typedef IOMMUR3 *PIOMMUR3;
593/** Pointer to the const ring-3 IOMMU device state. */
594typedef const IOMMUR3 *PCIOMMUR3;
595#ifdef IOMMU_WITH_IOTLBE_CACHE
596AssertCompileMemberAlignment(IOMMUR3, paIotlbes, 8);
597AssertCompileMemberAlignment(IOMMUR3, TreeIotlbe, 8);
598AssertCompileMemberAlignment(IOMMUR3, LstLruIotlbe, 8);
599#endif
600
601/**
602 * The ring-0 IOMMU device state.
603 */
604typedef struct IOMMUR0
605{
606 /** Device instance. */
607 PPDMDEVINSR0 pDevInsR0;
608 /** The IOMMU helpers. */
609 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
610} IOMMUR0;
611/** Pointer to the ring-0 IOMMU device state. */
612typedef IOMMUR0 *PIOMMUR0;
613
614/**
615 * The raw-mode IOMMU device state.
616 */
617typedef struct IOMMURC
618{
619 /** Device instance. */
620 PPDMDEVINSRC pDevInsRC;
621 /** The IOMMU helpers. */
622 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
623} IOMMURC;
624/** Pointer to the raw-mode IOMMU device state. */
625typedef IOMMURC *PIOMMURC;
626
627/** The IOMMU device state for the current context. */
628typedef CTX_SUFF(IOMMU) IOMMUCC;
629/** Pointer to the IOMMU device state for the current context. */
630typedef CTX_SUFF(PIOMMU) PIOMMUCC;
631
632/**
633 * IOMMU register access.
634 */
635typedef struct IOMMUREGACC
636{
637 const char *pszName;
638 VBOXSTRICTRC (*pfnRead)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value);
639 VBOXSTRICTRC (*pfnWrite)(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value);
640} IOMMUREGACC;
641/** Pointer to an IOMMU register access. */
642typedef IOMMUREGACC *PIOMMUREGACC;
643/** Pointer to a const IOMMU register access. */
644typedef IOMMUREGACC const *PCIOMMUREGACC;
645
646#ifdef IOMMU_WITH_IOTLBE_CACHE
647/**
648 * IOTLBE flush argument.
649 */
650typedef struct IOTLBEFLUSHARG
651{
652 /** The ring-3 IOMMU device state. */
653 PIOMMUR3 pIommuR3;
654 /** The domain ID to flush. */
655 uint16_t idDomain;
656} IOTLBEFLUSHARG;
657/** Pointer to an IOTLBE flush argument. */
658typedef IOTLBEFLUSHARG *PIOTLBEFLUSHARG;
659/** Pointer to a const IOTLBE flush argument. */
660typedef IOTLBEFLUSHARG const *PCIOTLBEFLUSHARG;
661
662/**
663 * IOTLBE Info. argument.
664 */
665typedef struct IOTLBEINFOARG
666{
667 /** The ring-3 IOMMU device state. */
668 PIOMMUR3 pIommuR3;
669 /** The info helper. */
670 PCDBGFINFOHLP pHlp;
671 /** The domain ID to dump IOTLB entry. */
672 uint16_t idDomain;
673} IOTLBEINFOARG;
674/** Pointer to an IOTLBE flush argument. */
675typedef IOTLBEINFOARG *PIOTLBEINFOARG;
676/** Pointer to a const IOTLBE flush argument. */
677typedef IOTLBEINFOARG const *PCIOTLBEINFOARG;
678#endif
679
680/**
681 * IOMMU operation auxiliary info.
682 */
683typedef struct IOMMUOPAUX
684{
685 /** The IOMMU operation being performed. */
686 IOMMUOP enmOp;
687 /** The device table entry (can be NULL). */
688 PCDTE_T pDte;
689 /** The device ID (bus, device, function). */
690 uint16_t idDevice;
691 /** The domain ID (when the DTE isn't provided). */
692 uint16_t idDomain;
693} IOMMUOPAUX;
694/** Pointer to an I/O address lookup struct. */
695typedef IOMMUOPAUX *PIOMMUOPAUX;
696/** Pointer to a const I/O address lookup struct. */
697typedef IOMMUOPAUX const *PCIOMMUOPAUX;
698
699typedef DECLCALLBACKTYPE(int, FNIOPAGELOOKUP,(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
700 PIOPAGELOOKUP pPageLookup));
701typedef FNIOPAGELOOKUP *PFNIOPAGELOOKUP;
702
703
704/*********************************************************************************************************************************
705* Global Variables *
706*********************************************************************************************************************************/
707#ifdef IN_RING3
708/**
709 * An array of the number of device table segments supported.
710 * Indexed by u2DevTabSegSup.
711 */
712static uint8_t const g_acDevTabSegs[] = { 0, 2, 4, 8 };
713#endif
714
715#if (defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)) || defined(LOG_ENABLED)
716/**
717 * The IOMMU I/O permission names.
718 */
719static const char * const g_aszPerm[] = { "none", "read", "write", "read+write" };
720#endif
721
722/**
723 * An array of the masks to select the device table segment index from a device ID.
724 */
725static uint16_t const g_auDevTabSegMasks[] = { 0x0, 0x8000, 0xc000, 0xe000 };
726
727/**
728 * An array of the shift values to select the device table segment index from a
729 * device ID.
730 */
731static uint8_t const g_auDevTabSegShifts[] = { 0, 15, 14, 13 };
732
733/**
734 * The maximum size (inclusive) of each device table segment (0 to 7).
735 * Indexed by the device table segment index.
736 */
737static uint16_t const g_auDevTabSegMaxSizes[] = { 0x1ff, 0xff, 0x7f, 0x7f, 0x3f, 0x3f, 0x3f, 0x3f };
738
739
740#ifndef VBOX_DEVICE_STRUCT_TESTCASE
741/**
742 * Gets the maximum number of buffer entries for the given buffer length.
743 *
744 * @returns Number of buffer entries.
745 * @param uEncodedLen The length (power-of-2 encoded).
746 */
747DECLINLINE(uint32_t) iommuAmdGetBufMaxEntries(uint8_t uEncodedLen)
748{
749 Assert(uEncodedLen > 7);
750 Assert(uEncodedLen < 16);
751 return 2 << (uEncodedLen - 1);
752}
753
754
755/**
756 * Gets the total length of the buffer given a base register's encoded length.
757 *
758 * @returns The length of the buffer in bytes.
759 * @param uEncodedLen The length (power-of-2 encoded).
760 */
761DECLINLINE(uint32_t) iommuAmdGetTotalBufLength(uint8_t uEncodedLen)
762{
763 Assert(uEncodedLen > 7);
764 Assert(uEncodedLen < 16);
765 return (2 << (uEncodedLen - 1)) << 4;
766}
767
768
769/**
770 * Gets the number of (unconsumed) entries in the event log.
771 *
772 * @returns The number of entries in the event log.
773 * @param pThis The shared IOMMU device state.
774 */
775static uint32_t iommuAmdGetEvtLogEntryCount(PIOMMU pThis)
776{
777 uint32_t const idxTail = pThis->EvtLogTailPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
778 uint32_t const idxHead = pThis->EvtLogHeadPtr.n.off >> IOMMU_EVT_GENERIC_SHIFT;
779 if (idxTail >= idxHead)
780 return idxTail - idxHead;
781
782 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
783 return cMaxEvts - idxHead + idxTail;
784}
785
786
787#if (defined(IN_RING3) && defined(IOMMU_WITH_IOTLBE_CACHE)) || defined(LOG_ENABLED)
788/**
789 * Gets the descriptive I/O permission name for a memory access.
790 *
791 * @returns The I/O permission name.
792 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
793 */
794static const char *iommuAmdMemAccessGetPermName(uint8_t fPerm)
795{
796 /* We shouldn't construct an access with "none" or "read+write" (must be read or write) permissions. */
797 Assert(fPerm > 0 && fPerm < RT_ELEMENTS(g_aszPerm));
798 return g_aszPerm[fPerm & IOMMU_IO_PERM_MASK];
799}
800#endif
801
802
803/**
804 * Checks whether two consecutive I/O page lookup results translates to a physically
805 * contiguous region.
806 *
807 * @returns @c true if they are contiguous, @c false otherwise.
808 * @param pPageLookupPrev The I/O page lookup result of the previous page.
809 * @param pPageLookup The I/O page lookup result of the current page.
810 */
811static bool iommuAmdLookupIsAccessContig(PCIOPAGELOOKUP pPageLookupPrev, PCIOPAGELOOKUP pPageLookup)
812{
813 size_t const cbPrev = RT_BIT_64(pPageLookupPrev->cShift);
814 RTGCPHYS const GCPhysPrev = pPageLookupPrev->GCPhysSpa;
815 RTGCPHYS const GCPhys = pPageLookup->GCPhysSpa;
816
817 /* Paranoia: Ensure offset bits are 0. */
818 Assert(!(GCPhysPrev & X86_GET_PAGE_OFFSET_MASK(pPageLookupPrev->cShift)));
819 Assert(!(GCPhys & X86_GET_PAGE_OFFSET_MASK(pPageLookup->cShift)));
820
821 /* Paranoia: Ensure permissions are identical. */
822 Assert(pPageLookupPrev->fPerm == pPageLookup->fPerm);
823
824 return GCPhysPrev + cbPrev == GCPhys;
825}
826
827
828#ifdef IOMMU_WITH_DTE_CACHE
829/**
830 * Gets the basic I/O device flags for the given device table entry.
831 *
832 * @returns The basic I/O device flags.
833 * @param pDte The device table entry.
834 */
835static uint16_t iommuAmdGetBasicDevFlags(PCDTE_T pDte)
836{
837 /* Extract basic flags from bits 127:0 of the DTE. */
838 uint16_t fFlags = 0;
839 if (pDte->n.u1Valid)
840 {
841 fFlags |= IOMMU_DTE_CACHE_F_VALID;
842
843 /** @todo Skip the if checks here (shift/mask the relevant bits over). */
844 if (pDte->n.u1SuppressAllPfEvents)
845 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
846 if (pDte->n.u1SuppressPfEvents)
847 fFlags |= IOMMU_DTE_CACHE_F_SUPPRESS_IOPF;
848
849 uint16_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
850 AssertCompile(IOMMU_DTE_CACHE_F_IO_PERM_MASK == IOMMU_IO_PERM_MASK);
851 fFlags |= fDtePerm << IOMMU_DTE_CACHE_F_IO_PERM_SHIFT;
852 }
853
854 /* Extract basic flags from bits 255:128 of the DTE. */
855 if (pDte->n.u1IntrMapValid)
856 {
857 fFlags |= IOMMU_DTE_CACHE_F_INTR_MAP_VALID;
858
859 /** @todo Skip the if check here (shift/mask the relevant bit over). */
860 if (pDte->n.u1IgnoreUnmappedIntrs)
861 fFlags |= IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
862
863 uint16_t const fIntrCtrl = IOMMU_DTE_GET_INTR_CTRL(pDte);
864 AssertCompile(IOMMU_DTE_CACHE_F_INTR_CTRL_MASK == IOMMU_DTE_INTR_CTRL_MASK);
865 fFlags |= fIntrCtrl << IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT;
866 }
867 return fFlags;
868}
869#endif
870
871
872/**
873 * Remaps the source MSI to the destination MSI given the IRTE.
874 *
875 * @param pMsiIn The source MSI.
876 * @param pMsiOut Where to store the remapped MSI.
877 * @param pIrte The IRTE used for the remapping.
878 */
879static void iommuAmdIrteRemapMsi(PCMSIMSG pMsiIn, PMSIMSG pMsiOut, PCIRTE_T pIrte)
880{
881 /* Preserve all bits from the source MSI address and data that don't map 1:1 from the IRTE. */
882 *pMsiOut = *pMsiIn;
883
884 pMsiOut->Addr.n.u1DestMode = pIrte->n.u1DestMode;
885 pMsiOut->Addr.n.u8DestId = pIrte->n.u8Dest;
886
887 pMsiOut->Data.n.u8Vector = pIrte->n.u8Vector;
888 pMsiOut->Data.n.u3DeliveryMode = pIrte->n.u3IntrType;
889}
890
891
892#ifdef IOMMU_WITH_DTE_CACHE
893/**
894 * Looks up an entry in the DTE cache for the given device ID.
895 *
896 * @returns The index of the entry, or the cache capacity if no entry was found.
897 * @param pThis The shared IOMMU device state.
898 * @param idDevice The device ID (bus, device, function).
899 */
900DECLINLINE(uint16_t) iommuAmdDteCacheEntryLookup(PIOMMU pThis, uint16_t idDevice)
901{
902 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
903 for (uint16_t i = 0; i < cDeviceIds; i++)
904 {
905 if (pThis->aDeviceIds[i] == idDevice)
906 return i;
907 }
908 return cDeviceIds;
909}
910
911
912/**
913 * Gets an free/unused DTE cache entry.
914 *
915 * @returns The index of an unused entry, or cache capacity if the cache is full.
916 * @param pThis The shared IOMMU device state.
917 */
918DECLINLINE(uint16_t) iommuAmdDteCacheEntryGetUnused(PCIOMMU pThis)
919{
920 /*
921 * ASSUMES device ID 0 is the PCI host bridge or the IOMMU itself
922 * (the latter being an ugly hack) and cannot be a valid device ID.
923 */
924 uint16_t const cDeviceIds = RT_ELEMENTS(pThis->aDeviceIds);
925 for (uint16_t i = 0; i < cDeviceIds; i++)
926 {
927 if (!pThis->aDeviceIds[i])
928 return i;
929 }
930 return cDeviceIds;
931}
932
933
934/**
935 * Adds or updates the I/O device flags for the given device ID.
936 *
937 * @returns VBox status code.
938 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
939 *
940 * @param pDevIns The IOMMU instance data.
941 * @param idDevice The device ID (bus, device, function).
942 * @param pDte The device table entry.
943 * @param fOrMask The device flags (usually compound flags) to OR in with the
944 * basic flags, see IOMMU_DTE_CACHE_F_XXX.
945 */
946static int iommuAmdDteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, uint16_t fOrMask)
947{
948 Assert(pDte);
949 Assert(idDevice);
950
951 int rc = VINF_SUCCESS;
952 uint16_t const fFlags = iommuAmdGetBasicDevFlags(pDte) | IOMMU_DTE_CACHE_F_PRESENT | fOrMask;
953 uint16_t const idDomain = pDte->n.u16DomainId;
954
955 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
956 IOMMU_CACHE_LOCK(pDevIns, pThis);
957
958 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
959 uint16_t idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
960 if (idxDte < cDteCache)
961 {
962 pThis->aDteCache[idxDte].fFlags = fFlags;
963 pThis->aDteCache[idxDte].idDomain = idDomain;
964 }
965 else if ((idxDte = iommuAmdDteCacheEntryGetUnused(pThis)) < cDteCache)
966 {
967 pThis->aDeviceIds[idxDte] = idDevice;
968 pThis->aDteCache[idxDte].fFlags = fFlags;
969 pThis->aDteCache[idxDte].idDomain = idDomain;
970 }
971 else
972 rc = VERR_OUT_OF_RESOURCES;
973
974 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
975 return rc;
976}
977
978
979/**
980 * Adds one or more I/O device flags if the device is already present in the cache.
981 *
982 * @param pDevIns The IOMMU instance data.
983 * @param idDevice The device ID (bus, device, function).
984 * @param fFlags Additional device flags to OR with existing flags, see
985 * IOMMU_DTE_CACHE_F_XXX.
986 */
987static void iommuAmdDteCacheAddFlags(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t fFlags)
988{
989 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
990 IOMMU_CACHE_LOCK(pDevIns, pThis);
991
992 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
993 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
994 if ( idxDte < cDteCache
995 && (pThis->aDteCache[idxDte].fFlags & IOMMU_DTE_CACHE_F_PRESENT))
996 pThis->aDteCache[idxDte].fFlags |= fFlags;
997
998 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
999}
1000
1001
1002# ifdef IN_RING3
1003/**
1004 * Removes a DTE cache entry.
1005 *
1006 * @param pDevIns The IOMMU instance data.
1007 * @param idDevice The device ID to remove cache entries for.
1008 */
1009static void iommuAmdDteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1010{
1011 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1012 IOMMU_CACHE_LOCK(pDevIns, pThis);
1013
1014 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDteCache);
1015 uint16_t const idxDte = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1016 if (idxDte < cDteCache)
1017 {
1018 pThis->aDteCache[idxDte].fFlags = 0;
1019 pThis->aDteCache[idxDte].idDomain = 0;
1020 }
1021
1022 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1023}
1024
1025
1026/**
1027 * Removes all entries in the device table entry cache.
1028 *
1029 * @param pDevIns The IOMMU instance data.
1030 */
1031static void iommuAmdDteCacheRemoveAll(PPDMDEVINS pDevIns)
1032{
1033 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1034 IOMMU_CACHE_LOCK(pDevIns, pThis);
1035 RT_ZERO(pThis->aDeviceIds);
1036 RT_ZERO(pThis->aDteCache);
1037 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1038}
1039# endif /* IN_RING3 */
1040#endif /* IOMMU_WITH_DTE_CACHE */
1041
1042
1043#ifdef IOMMU_WITH_IOTLBE_CACHE
1044/**
1045 * Moves the IOTLB entry to the least recently used slot.
1046 *
1047 * @param pThisR3 The ring-3 IOMMU device state.
1048 * @param pIotlbe The IOTLB entry to move.
1049 */
1050DECLINLINE(void) iommuAmdIotlbEntryMoveToLru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1051{
1052 if (!RTListNodeIsFirst(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1053 {
1054 RTListNodeRemove(&pIotlbe->NdLru);
1055 RTListPrepend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1056 }
1057}
1058
1059
1060/**
1061 * Moves the IOTLB entry to the most recently used slot.
1062 *
1063 * @param pThisR3 The ring-3 IOMMU device state.
1064 * @param pIotlbe The IOTLB entry to move.
1065 */
1066DECLINLINE(void) iommuAmdIotlbEntryMoveToMru(PIOMMUR3 pThisR3, PIOTLBE pIotlbe)
1067{
1068 if (!RTListNodeIsLast(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru))
1069 {
1070 RTListNodeRemove(&pIotlbe->NdLru);
1071 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1072 }
1073}
1074
1075
1076# ifdef IN_RING3
1077/**
1078 * Dumps the IOTLB entry via the debug info helper.
1079 *
1080 * @returns VINF_SUCCESS.
1081 * @param pNode Pointer to an IOTLB entry to dump info.
1082 * @param pvUser Pointer to an IOTLBEINFOARG.
1083 */
1084static DECLCALLBACK(int) iommuAmdR3IotlbEntryInfo(PAVLU64NODECORE pNode, void *pvUser)
1085{
1086 /* Validate. */
1087 PCIOTLBEINFOARG pArgs = (PCIOTLBEINFOARG)pvUser;
1088 AssertPtr(pArgs);
1089 AssertPtr(pArgs->pIommuR3);
1090 AssertPtr(pArgs->pHlp);
1091 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1092
1093 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1094 if (idDomain == pArgs->idDomain)
1095 {
1096 PCIOTLBE pIotlbe = (PCIOTLBE)pNode;
1097 AVLU64KEY const uKey = pIotlbe->Core.Key;
1098 uint64_t const uIova = IOMMU_IOTLB_KEY_GET_IOVA(uKey);
1099 RTGCPHYS const GCPhysSpa = pIotlbe->PageLookup.GCPhysSpa;
1100 uint8_t const cShift = pIotlbe->PageLookup.cShift;
1101 size_t const cbPage = RT_BIT_64(cShift);
1102 uint8_t const fPerm = pIotlbe->PageLookup.fPerm;
1103 const char *pszPerm = iommuAmdMemAccessGetPermName(fPerm);
1104 bool const fEvictPending = pIotlbe->fEvictPending;
1105
1106 PCDBGFINFOHLP pHlp = pArgs->pHlp;
1107 pHlp->pfnPrintf(pHlp, " Key = %#RX64 (%#RX64)\n", uKey, uIova);
1108 pHlp->pfnPrintf(pHlp, " GCPhys = %#RGp\n", GCPhysSpa);
1109 pHlp->pfnPrintf(pHlp, " cShift = %u (%zu bytes)\n", cShift, cbPage);
1110 pHlp->pfnPrintf(pHlp, " fPerm = %#x (%s)\n", fPerm, pszPerm);
1111 pHlp->pfnPrintf(pHlp, " fEvictPending = %RTbool\n", fEvictPending);
1112 }
1113
1114 return VINF_SUCCESS;
1115}
1116# endif /* IN_RING3 */
1117
1118
1119/**
1120 * Removes the IOTLB entry if it's associated with the specified domain ID.
1121 *
1122 * @returns VINF_SUCCESS.
1123 * @param pNode Pointer to an IOTLBE.
1124 * @param pvUser Pointer to an IOTLBEFLUSHARG containing the domain ID.
1125 */
1126static DECLCALLBACK(int) iommuAmdIotlbEntryRemoveDomainId(PAVLU64NODECORE pNode, void *pvUser)
1127{
1128 /* Validate. */
1129 PCIOTLBEFLUSHARG pArgs = (PCIOTLBEFLUSHARG)pvUser;
1130 AssertPtr(pArgs);
1131 AssertPtr(pArgs->pIommuR3);
1132 //Assert(pArgs->pIommuR3->u32Magic == IOMMU_MAGIC);
1133
1134 uint16_t const idDomain = IOMMU_IOTLB_KEY_GET_DOMAIN_ID(pNode->Key);
1135 if (idDomain == pArgs->idDomain)
1136 {
1137 /* Mark this entry is as invalidated and needs to be evicted later. */
1138 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1139 pIotlbe->fEvictPending = true;
1140 iommuAmdIotlbEntryMoveToLru(pArgs->pIommuR3, (PIOTLBE)pNode);
1141 }
1142 return VINF_SUCCESS;
1143}
1144
1145
1146/**
1147 * Destroys an IOTLB entry that's in the tree.
1148 *
1149 * @returns VINF_SUCCESS.
1150 * @param pNode Pointer to an IOTLBE.
1151 * @param pvUser Opaque data. Currently not used, will be NULL.
1152 */
1153static DECLCALLBACK(int) iommuAmdIotlbEntryDestroy(PAVLU64NODECORE pNode, void *pvUser)
1154{
1155 RT_NOREF(pvUser);
1156 PIOTLBE pIotlbe = (PIOTLBE)pNode;
1157 Assert(pIotlbe);
1158 pIotlbe->NdLru.pNext = NULL;
1159 pIotlbe->NdLru.pPrev = NULL;
1160 RT_ZERO(pIotlbe->PageLookup);
1161 pIotlbe->fEvictPending = false;
1162 return VINF_SUCCESS;
1163}
1164
1165
1166/**
1167 * Inserts an IOTLB entry into the cache.
1168 *
1169 * @param pThis The shared IOMMU device state.
1170 * @param pThisR3 The ring-3 IOMMU device state.
1171 * @param pIotlbe The IOTLB entry to initialize and insert.
1172 * @param idDomain The domain ID.
1173 * @param uIova The I/O virtual address.
1174 * @param pPageLookup The I/O page lookup result of the access.
1175 */
1176static void iommuAmdIotlbEntryInsert(PIOMMU pThis, PIOMMUR3 pThisR3, PIOTLBE pIotlbe, uint16_t idDomain, uint64_t uIova,
1177 PCIOPAGELOOKUP pPageLookup)
1178{
1179 /* Initialize the IOTLB entry with results of the I/O page walk. */
1180 pIotlbe->Core.Key = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1181 pIotlbe->PageLookup = *pPageLookup;
1182
1183 /* Validate. */
1184 Assert(pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL);
1185 Assert(!pIotlbe->fEvictPending);
1186
1187 /* Check if the entry already exists. */
1188 PIOTLBE pFound = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, pIotlbe->Core.Key);
1189 if (!pFound)
1190 {
1191 /* Insert the entry into the cache. */
1192 bool const fInserted = RTAvlU64Insert(&pThisR3->TreeIotlbe, &pIotlbe->Core);
1193 Assert(fInserted); NOREF(fInserted);
1194 Assert(pThisR3->cCachedIotlbes < IOMMU_IOTLBE_MAX);
1195 ++pThisR3->cCachedIotlbes;
1196 STAM_COUNTER_INC(&pThis->StatIotlbeCached); NOREF(pThis);
1197 }
1198 else
1199 {
1200 /* Update the existing entry. */
1201 if (pFound->fEvictPending)
1202 {
1203 pFound->fEvictPending = false;
1204 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse); NOREF(pThis);
1205 }
1206 Assert(pFound->PageLookup.cShift == pPageLookup->cShift);
1207 pFound->PageLookup.fPerm = pPageLookup->fPerm;
1208 pFound->PageLookup.GCPhysSpa = pPageLookup->GCPhysSpa;
1209 }
1210}
1211
1212
1213/**
1214 * Removes an IOTLB entry from the cache for the given key.
1215 *
1216 * @returns Pointer to the removed IOTLB entry, NULL if the entry wasn't found in
1217 * the tree.
1218 * @param pThis The shared IOMMU device state.
1219 * @param pThisR3 The ring-3 IOMMU device state.
1220 * @param uKey The key of the IOTLB entry to remove.
1221 */
1222static PIOTLBE iommuAmdIotlbEntryRemove(PIOMMU pThis, PIOMMUR3 pThisR3, AVLU64KEY uKey)
1223{
1224 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Remove(&pThisR3->TreeIotlbe, uKey);
1225 if (pIotlbe)
1226 {
1227 if (pIotlbe->fEvictPending)
1228 STAM_COUNTER_INC(&pThis->StatIotlbeLazyEvictReuse);
1229
1230 RT_ZERO(pIotlbe->Core);
1231 RT_ZERO(pIotlbe->PageLookup);
1232 /* We must not erase the LRU node connections here! */
1233 pIotlbe->fEvictPending = false;
1234 Assert(pIotlbe->Core.Key == IOMMU_IOTLB_KEY_NIL);
1235
1236 Assert(pThisR3->cCachedIotlbes > 0);
1237 --pThisR3->cCachedIotlbes;
1238 STAM_COUNTER_DEC(&pThis->StatIotlbeCached); NOREF(pThis);
1239 }
1240 return pIotlbe;
1241}
1242
1243
1244/**
1245 * Looks up an IOTLB from the cache.
1246 *
1247 * @returns Pointer to IOTLB entry if found, NULL otherwise.
1248 * @param pThis The shared IOMMU device state.
1249 * @param pThisR3 The ring-3 IOMMU device state.
1250 * @param idDomain The domain ID.
1251 * @param uIova The I/O virtual address.
1252 */
1253static PIOTLBE iommuAmdIotlbLookup(PIOMMU pThis, PIOMMUR3 pThisR3, uint64_t idDomain, uint64_t uIova)
1254{
1255 RT_NOREF(pThis);
1256
1257 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1258 PIOTLBE pIotlbe = (PIOTLBE)RTAvlU64Get(&pThisR3->TreeIotlbe, uKey);
1259 if ( pIotlbe
1260 && !pIotlbe->fEvictPending)
1261 return pIotlbe;
1262
1263 /*
1264 * Domain Id wildcard invalidations only marks entries for eviction later but doesn't remove
1265 * them from the cache immediately. We found an entry pending eviction, just return that
1266 * nothing was found (rather than evicting now).
1267 */
1268 return NULL;
1269}
1270
1271
1272/**
1273 * Adds an IOTLB entry to the cache.
1274 *
1275 * @param pThis The shared IOMMU device state.
1276 * @param pThisR3 The ring-3 IOMMU device state.
1277 * @param idDomain The domain ID.
1278 * @param uIova The I/O virtual address.
1279 * @param pPageLookup The I/O page lookup result of the access.
1280 */
1281static void iommuAmdIotlbAdd(PIOMMU pThis, PIOMMUR3 pThisR3, uint16_t idDomain, uint64_t uIova, PCIOPAGELOOKUP pPageLookup)
1282{
1283 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1284 Assert(pPageLookup);
1285 Assert(pPageLookup->cShift <= 31);
1286 Assert(pPageLookup->fPerm != IOMMU_IO_PERM_NONE);
1287
1288 /*
1289 * If there are no unused IOTLB entries, evict the LRU entry.
1290 * Otherwise, get a new IOTLB entry from the pre-allocated list.
1291 */
1292 if (pThisR3->idxUnusedIotlbe == IOMMU_IOTLBE_MAX)
1293 {
1294 /* Grab the least recently used entry. */
1295 PIOTLBE pIotlbe = RTListGetFirst(&pThisR3->LstLruIotlbe, IOTLBE, NdLru);
1296 Assert(pIotlbe);
1297
1298 /* If the entry is in the cache, remove it. */
1299 if (pIotlbe->Core.Key != IOMMU_IOTLB_KEY_NIL)
1300 iommuAmdIotlbEntryRemove(pThis, pThisR3, pIotlbe->Core.Key);
1301
1302 /* Initialize and insert the IOTLB entry into the cache. */
1303 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1304
1305 /* Move the entry to the most recently used slot. */
1306 iommuAmdIotlbEntryMoveToMru(pThisR3, pIotlbe);
1307 }
1308 else
1309 {
1310 /* Grab an unused IOTLB entry from the pre-allocated list. */
1311 PIOTLBE pIotlbe = &pThisR3->paIotlbes[pThisR3->idxUnusedIotlbe];
1312 ++pThisR3->idxUnusedIotlbe;
1313
1314 /* Initialize and insert the IOTLB entry into the cache. */
1315 iommuAmdIotlbEntryInsert(pThis, pThisR3, pIotlbe, idDomain, uIova, pPageLookup);
1316
1317 /* Add the entry to the most recently used slot. */
1318 RTListAppend(&pThisR3->LstLruIotlbe, &pIotlbe->NdLru);
1319 }
1320}
1321
1322
1323/**
1324 * Removes all IOTLB entries from the cache.
1325 *
1326 * @param pDevIns The IOMMU instance data.
1327 */
1328static void iommuAmdIotlbRemoveAll(PPDMDEVINS pDevIns)
1329{
1330 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1331 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1332 IOMMU_CACHE_LOCK(pDevIns, pThis);
1333
1334 if (pThisR3->cCachedIotlbes > 0)
1335 {
1336 RTAvlU64Destroy(&pThisR3->TreeIotlbe, iommuAmdIotlbEntryDestroy, NULL /* pvParam */);
1337 RTListInit(&pThisR3->LstLruIotlbe);
1338 pThisR3->idxUnusedIotlbe = 0;
1339 pThisR3->cCachedIotlbes = 0;
1340 STAM_COUNTER_RESET(&pThis->StatIotlbeCached);
1341 }
1342
1343 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1344}
1345
1346
1347/**
1348 * Removes IOTLB entries for the range of I/O virtual addresses and the specified
1349 * domain ID from the cache.
1350 *
1351 * @param pDevIns The IOMMU instance data.
1352 * @param idDomain The domain ID.
1353 * @param uIova The I/O virtual address to invalidate.
1354 * @param cbInvalidate The size of the invalidation (must be 4K aligned).
1355 */
1356static void iommuAmdIotlbRemoveRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbInvalidate)
1357{
1358 /* Validate. */
1359 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1360 Assert(!(cbInvalidate & X86_PAGE_4K_OFFSET_MASK));
1361 Assert(cbInvalidate >= X86_PAGE_4K_SIZE);
1362
1363 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1364 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1365 IOMMU_CACHE_LOCK(pDevIns, pThis);
1366
1367 do
1368 {
1369 uint64_t const uKey = IOMMU_IOTLB_KEY_MAKE(idDomain, uIova);
1370 PIOTLBE pIotlbe = iommuAmdIotlbEntryRemove(pThis, pThisR3, uKey);
1371 if (pIotlbe)
1372 iommuAmdIotlbEntryMoveToLru(pThisR3, pIotlbe);
1373 uIova += X86_PAGE_4K_SIZE;
1374 cbInvalidate -= X86_PAGE_4K_SIZE;
1375 } while (cbInvalidate > 0);
1376
1377 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1378}
1379
1380
1381/**
1382 * Removes all IOTLB entries for the specified domain ID.
1383 *
1384 * @param pDevIns The IOMMU instance data.
1385 * @param idDomain The domain ID.
1386 */
1387static void iommuAmdIotlbRemoveDomainId(PPDMDEVINS pDevIns, uint16_t idDomain)
1388{
1389 /*
1390 * We need to iterate the tree and search based on the domain ID.
1391 * But it seems we cannot remove items while iterating the tree.
1392 * Thus, we simply mark entries for eviction later but move them to the LRU
1393 * so they will eventually get evicted and re-cycled as the cache gets re-populated.
1394 */
1395 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1396 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1397 IOMMU_CACHE_LOCK(pDevIns, pThis);
1398
1399 IOTLBEFLUSHARG Args;
1400 Args.pIommuR3 = pThisR3;
1401 Args.idDomain = idDomain;
1402 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdIotlbEntryRemoveDomainId, &Args);
1403
1404 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1405}
1406
1407
1408/**
1409 * Adds or updates IOTLB entries for the given range of I/O virtual addresses.
1410 *
1411 * @param pDevIns The IOMMU instance data.
1412 * @param idDomain The domain ID.
1413 * @param uIova The I/O virtual address.
1414 * @param cbIova The size of the access (must be 4K aligned).
1415 * @param GCPhysSpa The translated system-physical address.
1416 * @param fPerm The I/O permissions for the access, see IOMMU_IO_PERM_XXX.
1417 */
1418static void iommuAmdIotlbAddRange(PPDMDEVINS pDevIns, uint16_t idDomain, uint64_t uIova, size_t cbIova, RTGCPHYS GCPhysSpa,
1419 uint8_t fPerm)
1420{
1421 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
1422 Assert(!(GCPhysSpa & X86_PAGE_4K_OFFSET_MASK));
1423 Assert(!(cbIova & X86_PAGE_4K_OFFSET_MASK));
1424 Assert(cbIova >= X86_PAGE_4K_SIZE);
1425
1426 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1427 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
1428
1429 /* Add IOTLB entries for every page in the access. */
1430 IOPAGELOOKUP PageLookup;
1431 RT_ZERO(PageLookup);
1432 PageLookup.cShift = X86_PAGE_4K_SHIFT;
1433 PageLookup.fPerm = fPerm;
1434 PageLookup.GCPhysSpa = GCPhysSpa;
1435
1436 size_t cPages = cbIova / X86_PAGE_4K_SIZE;
1437 cPages = RT_MIN(cPages, IOMMU_IOTLBE_MAX);
1438
1439 Assert((cbIova % X86_PAGE_4K_SIZE) == 0);
1440 Assert(cPages > 0);
1441
1442 IOMMU_CACHE_LOCK(pDevIns, pThis);
1443 /** @todo Re-check DTE cache? */
1444 do
1445 {
1446 iommuAmdIotlbAdd(pThis, pThisR3, idDomain, uIova, &PageLookup);
1447 uIova += X86_PAGE_4K_SIZE;
1448 PageLookup.GCPhysSpa += X86_PAGE_4K_SIZE;
1449 --cPages;
1450 } while (cPages > 0);
1451 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1452}
1453#endif /* IOMMU_WITH_IOTLBE_CACHE */
1454
1455
1456#ifdef IOMMU_WITH_IRTE_CACHE
1457/**
1458 * Looks up an IRTE cache entry.
1459 *
1460 * @returns Index of the found entry, or cache capacity if not found.
1461 * @param pThis The shared IOMMU device state.
1462 * @param idDevice The device ID (bus, device, function).
1463 * @param offIrte The offset into the interrupt remap table.
1464 */
1465static uint16_t iommuAmdIrteCacheEntryLookup(PCIOMMU pThis, uint16_t idDevice, uint16_t offIrte)
1466{
1467 /** @todo Consider sorting and binary search when the cache capacity grows.
1468 * For the IRTE cache this should be okay since typically guests do not alter the
1469 * interrupt remapping once programmed, so hopefully sorting shouldn't happen
1470 * often. */
1471 uint32_t const uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1472 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1473 for (uint16_t i = 0; i < cIrteCache; i++)
1474 if (pThis->aIrteCache[i].uKey == uKey)
1475 return i;
1476 return cIrteCache;
1477}
1478
1479
1480/**
1481 * Gets a free/unused IRTE cache entry.
1482 *
1483 * @returns The index of an unused entry, or cache capacity if the cache is full.
1484 * @param pThis The shared IOMMU device state.
1485 */
1486static uint16_t iommuAmdIrteCacheEntryGetUnused(PCIOMMU pThis)
1487{
1488 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1489 for (uint16_t i = 0; i < cIrteCache; i++)
1490 if (pThis->aIrteCache[i].uKey == IOMMU_IRTE_CACHE_KEY_NIL)
1491 {
1492 Assert(!pThis->aIrteCache[i].Irte.u32);
1493 return i;
1494 }
1495 return cIrteCache;
1496}
1497
1498
1499/**
1500 * Looks up the IRTE cache for the given MSI.
1501 *
1502 * @returns VBox status code.
1503 * @param pDevIns The IOMMU instance data.
1504 * @param idDevice The device ID (bus, device, function).
1505 * @param enmOp The IOMMU operation being performed.
1506 * @param pMsiIn The source MSI.
1507 * @param pMsiOut Where to store the remapped MSI.
1508 */
1509static int iommuAmdIrteCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1510{
1511 RT_NOREF(enmOp); /* May need it if we have to report errors (currently we fallback to the slower path to do that). */
1512
1513 int rc = VERR_NOT_FOUND;
1514 /* Deal with such cases in the slower/fallback path. */
1515 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
1516 { /* likely */ }
1517 else
1518 return rc;
1519
1520 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1521 IOMMU_CACHE_LOCK(pDevIns, pThis);
1522
1523 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
1524 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
1525 {
1526 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
1527 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1528 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_INTR_MAP_VALID))
1529 {
1530 Assert((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE); /* Paranoia. */
1531
1532 /* Currently, we only cache remapping of fixed and arbitrated interrupts. */
1533 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
1534 if (u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
1535 {
1536 uint8_t const uIntrCtrl = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_INTR_CTRL_SHIFT)
1537 & IOMMU_DTE_CACHE_F_INTR_CTRL_MASK;
1538 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
1539 {
1540 /* Interrupt table length has been verified prior to adding entries to the cache. */
1541 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(pMsiIn->Data.u32);
1542 uint16_t const idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1543 if (idxIrteCache < RT_ELEMENTS(pThis->aIrteCache))
1544 {
1545 PCIRTE_T pIrte = &pThis->aIrteCache[idxIrteCache].Irte;
1546 Assert(pIrte->n.u1RemapEnable);
1547 Assert(pIrte->n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO);
1548 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, pIrte);
1549 rc = VINF_SUCCESS;
1550 }
1551 }
1552 else if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
1553 {
1554 *pMsiOut = *pMsiIn;
1555 rc = VINF_SUCCESS;
1556 }
1557 }
1558 }
1559 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
1560 {
1561 *pMsiOut = *pMsiIn;
1562 rc = VINF_SUCCESS;
1563 }
1564 }
1565
1566 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1567 return rc;
1568}
1569
1570
1571/**
1572 * Adds or updates the IRTE cache for the given IRTE.
1573 *
1574 * @returns VBox status code.
1575 * @retval VERR_OUT_OF_RESOURCES if the cache is full.
1576 *
1577 * @param pDevIns The IOMMU instance data.
1578 * @param idDevice The device ID (bus, device, function).
1579 * @param offIrte The offset into the interrupt remap table.
1580 * @param pIrte The IRTE to cache.
1581 */
1582static int iommuAmdIrteCacheAdd(PPDMDEVINS pDevIns, uint16_t idDevice, uint16_t offIrte, PCIRTE_T pIrte)
1583{
1584 Assert(offIrte != 0xffff); /* Shouldn't be a valid IRTE table offset since sizeof(IRTE) is a multiple of 4. */
1585
1586 int rc = VINF_SUCCESS;
1587 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1588 Assert(idDevice != pThis->uPciAddress);
1589 IOMMU_CACHE_LOCK(pDevIns, pThis);
1590
1591 /* Find an existing entry or get an unused slot. */
1592 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1593 uint16_t idxIrteCache = iommuAmdIrteCacheEntryLookup(pThis, idDevice, offIrte);
1594 if ( idxIrteCache < cIrteCache
1595 || (idxIrteCache = iommuAmdIrteCacheEntryGetUnused(pThis)) < cIrteCache)
1596 {
1597 pThis->aIrteCache[idxIrteCache].uKey = IOMMU_IRTE_CACHE_KEY_MAKE(idDevice, offIrte);
1598 pThis->aIrteCache[idxIrteCache].Irte = *pIrte;
1599 }
1600 else
1601 rc = VERR_OUT_OF_RESOURCES;
1602
1603 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1604 return rc;
1605}
1606
1607
1608# ifdef IN_RING3
1609/**
1610 * Removes IRTE cache entries for the given device ID.
1611 *
1612 * @param pDevIns The IOMMU instance data.
1613 * @param idDevice The device ID (bus, device, function).
1614 */
1615static void iommuAmdIrteCacheRemove(PPDMDEVINS pDevIns, uint16_t idDevice)
1616{
1617 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1618 IOMMU_CACHE_LOCK(pDevIns, pThis);
1619 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1620 for (uint16_t i = 0; i < cIrteCache; i++)
1621 {
1622 PIRTECACHE pIrteCache = &pThis->aIrteCache[i];
1623 if (idDevice == IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(pIrteCache->uKey))
1624 {
1625 pIrteCache->uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1626 pIrteCache->Irte.u32 = 0;
1627 /* There could multiple IRTE entries for a device ID, continue searching. */
1628 }
1629 }
1630 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1631}
1632
1633
1634/**
1635 * Removes all IRTE cache entries.
1636 *
1637 * @param pDevIns The IOMMU instance data.
1638 */
1639static void iommuAmdIrteCacheRemoveAll(PPDMDEVINS pDevIns)
1640{
1641 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1642 IOMMU_CACHE_LOCK(pDevIns, pThis);
1643 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
1644 for (uint16_t i = 0; i < cIrteCache; i++)
1645 {
1646 pThis->aIrteCache[i].uKey = IOMMU_IRTE_CACHE_KEY_NIL;
1647 pThis->aIrteCache[i].Irte.u32 = 0;
1648 }
1649 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
1650}
1651# endif /* IN_RING3 */
1652#endif /* IOMMU_WITH_IRTE_CACHE */
1653
1654
1655/**
1656 * Atomically reads the control register without locking the IOMMU device.
1657 *
1658 * @returns The control register.
1659 * @param pThis The shared IOMMU device state.
1660 */
1661DECL_FORCE_INLINE(IOMMU_CTRL_T) iommuAmdGetCtrlUnlocked(PCIOMMU pThis)
1662{
1663 IOMMU_CTRL_T Ctrl;
1664 Ctrl.u64 = ASMAtomicReadU64((volatile uint64_t *)&pThis->Ctrl.u64);
1665 return Ctrl;
1666}
1667
1668
1669/**
1670 * Returns whether MSI is enabled for the IOMMU.
1671 *
1672 * @returns Whether MSI is enabled.
1673 * @param pDevIns The IOMMU device instance.
1674 *
1675 * @note There should be a PCIDevXxx function for this.
1676 */
1677static bool iommuAmdIsMsiEnabled(PPDMDEVINS pDevIns)
1678{
1679 MSI_CAP_HDR_T MsiCapHdr;
1680 MsiCapHdr.u32 = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_MSI_CAP_HDR);
1681 return MsiCapHdr.n.u1MsiEnable;
1682}
1683
1684
1685/**
1686 * Signals a PCI target abort.
1687 *
1688 * @param pDevIns The IOMMU device instance.
1689 */
1690static void iommuAmdSetPciTargetAbort(PPDMDEVINS pDevIns)
1691{
1692 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1693 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1694 PDMPciDevSetStatus(pPciDev, u16Status);
1695}
1696
1697
1698/**
1699 * Wakes up the command thread if there are commands to be processed.
1700 *
1701 * @param pDevIns The IOMMU device instance.
1702 *
1703 * @remarks The IOMMU lock must be held while calling this!
1704 */
1705static void iommuAmdCmdThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1706{
1707 Log4Func(("\n"));
1708
1709 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
1710 if ( pThis->Status.n.u1CmdBufRunning
1711 && pThis->CmdBufTailPtr.n.off != pThis->CmdBufHeadPtr.n.off
1712 && !ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, true))
1713 {
1714 Log4Func(("Signaling command thread\n"));
1715 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
1716 }
1717}
1718
1719
1720/**
1721 * Reads the Device Table Base Address Register.
1722 */
1723static VBOXSTRICTRC iommuAmdDevTabBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1724{
1725 RT_NOREF(pDevIns, offReg);
1726 *pu64Value = pThis->aDevTabBaseAddrs[0].u64;
1727 return VINF_SUCCESS;
1728}
1729
1730
1731/**
1732 * Reads the Command Buffer Base Address Register.
1733 */
1734static VBOXSTRICTRC iommuAmdCmdBufBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1735{
1736 RT_NOREF(pDevIns, offReg);
1737 *pu64Value = pThis->CmdBufBaseAddr.u64;
1738 return VINF_SUCCESS;
1739}
1740
1741
1742/**
1743 * Reads the Event Log Base Address Register.
1744 */
1745static VBOXSTRICTRC iommuAmdEvtLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1746{
1747 RT_NOREF(pDevIns, offReg);
1748 *pu64Value = pThis->EvtLogBaseAddr.u64;
1749 return VINF_SUCCESS;
1750}
1751
1752
1753/**
1754 * Reads the Control Register.
1755 */
1756static VBOXSTRICTRC iommuAmdCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1757{
1758 RT_NOREF(pDevIns, offReg);
1759 *pu64Value = pThis->Ctrl.u64;
1760 return VINF_SUCCESS;
1761}
1762
1763
1764/**
1765 * Reads the Exclusion Range Base Address Register.
1766 */
1767static VBOXSTRICTRC iommuAmdExclRangeBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1768{
1769 RT_NOREF(pDevIns, offReg);
1770 *pu64Value = pThis->ExclRangeBaseAddr.u64;
1771 return VINF_SUCCESS;
1772}
1773
1774
1775/**
1776 * Reads to the Exclusion Range Limit Register.
1777 */
1778static VBOXSTRICTRC iommuAmdExclRangeLimit_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1779{
1780 RT_NOREF(pDevIns, offReg);
1781 *pu64Value = pThis->ExclRangeLimit.u64;
1782 return VINF_SUCCESS;
1783}
1784
1785
1786/**
1787 * Reads to the Extended Feature Register.
1788 */
1789static VBOXSTRICTRC iommuAmdExtFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1790{
1791 RT_NOREF(pDevIns, offReg);
1792 *pu64Value = pThis->ExtFeat.u64;
1793 return VINF_SUCCESS;
1794}
1795
1796
1797/**
1798 * Reads to the PPR Log Base Address Register.
1799 */
1800static VBOXSTRICTRC iommuAmdPprLogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1801{
1802 RT_NOREF(pDevIns, offReg);
1803 *pu64Value = pThis->PprLogBaseAddr.u64;
1804 return VINF_SUCCESS;
1805}
1806
1807
1808/**
1809 * Writes the Hardware Event Register (Hi).
1810 */
1811static VBOXSTRICTRC iommuAmdHwEvtHi_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1812{
1813 RT_NOREF(pDevIns, offReg);
1814 *pu64Value = pThis->HwEvtHi.u64;
1815 return VINF_SUCCESS;
1816}
1817
1818
1819/**
1820 * Reads the Hardware Event Register (Lo).
1821 */
1822static VBOXSTRICTRC iommuAmdHwEvtLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1823{
1824 RT_NOREF(pDevIns, offReg);
1825 *pu64Value = pThis->HwEvtLo;
1826 return VINF_SUCCESS;
1827}
1828
1829
1830/**
1831 * Reads the Hardware Event Status Register.
1832 */
1833static VBOXSTRICTRC iommuAmdHwEvtStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1834{
1835 RT_NOREF(pDevIns, offReg);
1836 *pu64Value = pThis->HwEvtStatus.u64;
1837 return VINF_SUCCESS;
1838}
1839
1840
1841/**
1842 * Reads to the GA Log Base Address Register.
1843 */
1844static VBOXSTRICTRC iommuAmdGALogBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1845{
1846 RT_NOREF(pDevIns, offReg);
1847 *pu64Value = pThis->GALogBaseAddr.u64;
1848 return VINF_SUCCESS;
1849}
1850
1851
1852/**
1853 * Reads to the PPR Log B Base Address Register.
1854 */
1855static VBOXSTRICTRC iommuAmdPprLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1856{
1857 RT_NOREF(pDevIns, offReg);
1858 *pu64Value = pThis->PprLogBBaseAddr.u64;
1859 return VINF_SUCCESS;
1860}
1861
1862
1863/**
1864 * Reads to the Event Log B Base Address Register.
1865 */
1866static VBOXSTRICTRC iommuAmdEvtLogBBaseAddr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1867{
1868 RT_NOREF(pDevIns, offReg);
1869 *pu64Value = pThis->EvtLogBBaseAddr.u64;
1870 return VINF_SUCCESS;
1871}
1872
1873
1874/**
1875 * Reads the Device Table Segment Base Address Register.
1876 */
1877static VBOXSTRICTRC iommuAmdDevTabSegBar_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1878{
1879 RT_NOREF(pDevIns);
1880
1881 /* Figure out which segment is being written. */
1882 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
1883 uint8_t const idxSegment = offSegment + 1;
1884 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
1885
1886 *pu64Value = pThis->aDevTabBaseAddrs[idxSegment].u64;
1887 return VINF_SUCCESS;
1888}
1889
1890
1891/**
1892 * Reads the Device Specific Feature Extension (DSFX) Register.
1893 */
1894static VBOXSTRICTRC iommuAmdDevSpecificFeat_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1895{
1896 RT_NOREF(pDevIns, offReg);
1897 *pu64Value = pThis->DevSpecificFeat.u64;
1898 return VINF_SUCCESS;
1899}
1900
1901/**
1902 * Reads the Device Specific Control Extension (DSCX) Register.
1903 */
1904static VBOXSTRICTRC iommuAmdDevSpecificCtrl_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1905{
1906 RT_NOREF(pDevIns, offReg);
1907 *pu64Value = pThis->DevSpecificCtrl.u64;
1908 return VINF_SUCCESS;
1909}
1910
1911
1912/**
1913 * Reads the Device Specific Status Extension (DSSX) Register.
1914 */
1915static VBOXSTRICTRC iommuAmdDevSpecificStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1916{
1917 RT_NOREF(pDevIns, offReg);
1918 *pu64Value = pThis->DevSpecificStatus.u64;
1919 return VINF_SUCCESS;
1920}
1921
1922
1923/**
1924 * Reads the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
1925 */
1926static VBOXSTRICTRC iommuAmdDevMsiVector_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1927{
1928 RT_NOREF(pDevIns, offReg);
1929 uint32_t const uLo = pThis->MiscInfo.au32[0];
1930 uint32_t const uHi = pThis->MiscInfo.au32[1];
1931 *pu64Value = RT_MAKE_U64(uLo, uHi);
1932 return VINF_SUCCESS;
1933}
1934
1935
1936/**
1937 * Reads the MSI Capability Header Register (32-bit) and the MSI Address (Lo)
1938 * Register (32-bit).
1939 */
1940static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1941{
1942 RT_NOREF(pThis, offReg);
1943 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1944 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1945 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
1946 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
1947 *pu64Value = RT_MAKE_U64(uLo, uHi);
1948 return VINF_SUCCESS;
1949}
1950
1951
1952/**
1953 * Reads the MSI Address (Hi) Register (32-bit) and the MSI data register (32-bit).
1954 */
1955static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1956{
1957 RT_NOREF(pThis, offReg);
1958 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1959 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1960 uint32_t const uLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
1961 uint32_t const uHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
1962 *pu64Value = RT_MAKE_U64(uLo, uHi);
1963 return VINF_SUCCESS;
1964}
1965
1966
1967/**
1968 * Reads the Command Buffer Head Pointer Register.
1969 */
1970static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1971{
1972 RT_NOREF(pDevIns, offReg);
1973 *pu64Value = pThis->CmdBufHeadPtr.u64;
1974 return VINF_SUCCESS;
1975}
1976
1977
1978/**
1979 * Reads the Command Buffer Tail Pointer Register.
1980 */
1981static VBOXSTRICTRC iommuAmdCmdBufTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1982{
1983 RT_NOREF(pDevIns, offReg);
1984 *pu64Value = pThis->CmdBufTailPtr.u64;
1985 return VINF_SUCCESS;
1986}
1987
1988
1989/**
1990 * Reads the Event Log Head Pointer Register.
1991 */
1992static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
1993{
1994 RT_NOREF(pDevIns, offReg);
1995 *pu64Value = pThis->EvtLogHeadPtr.u64;
1996 return VINF_SUCCESS;
1997}
1998
1999
2000/**
2001 * Reads the Event Log Tail Pointer Register.
2002 */
2003static VBOXSTRICTRC iommuAmdEvtLogTailPtr_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2004{
2005 RT_NOREF(pDevIns, offReg);
2006 *pu64Value = pThis->EvtLogTailPtr.u64;
2007 return VINF_SUCCESS;
2008}
2009
2010
2011/**
2012 * Reads the Status Register.
2013 */
2014static VBOXSTRICTRC iommuAmdStatus_r(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t *pu64Value)
2015{
2016 RT_NOREF(pDevIns, offReg);
2017 *pu64Value = pThis->Status.u64;
2018 return VINF_SUCCESS;
2019}
2020
2021
2022/**
2023 * Writes the Device Table Base Address Register.
2024 */
2025static VBOXSTRICTRC iommuAmdDevTabBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2026{
2027 RT_NOREF(pDevIns, offReg);
2028
2029 /* Mask out all unrecognized bits. */
2030 u64Value &= IOMMU_DEV_TAB_BAR_VALID_MASK;
2031
2032 /* Update the register. */
2033 pThis->aDevTabBaseAddrs[0].u64 = u64Value;
2034
2035 /* Paranoia. */
2036 Assert(pThis->aDevTabBaseAddrs[0].n.u9Size <= g_auDevTabSegMaxSizes[0]);
2037 return VINF_SUCCESS;
2038}
2039
2040
2041/**
2042 * Writes the Command Buffer Base Address Register.
2043 */
2044static VBOXSTRICTRC iommuAmdCmdBufBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2045{
2046 RT_NOREF(pDevIns, offReg);
2047
2048 /*
2049 * While this is not explicitly specified like the event log base address register,
2050 * the AMD IOMMU spec. does specify "CmdBufRun must be 0b to modify the command buffer registers properly".
2051 * Inconsistent specs :/
2052 */
2053 if (pThis->Status.n.u1CmdBufRunning)
2054 {
2055 LogFunc(("Setting CmdBufBar (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2056 return VINF_SUCCESS;
2057 }
2058
2059 /* Mask out all unrecognized bits. */
2060 CMD_BUF_BAR_T CmdBufBaseAddr;
2061 CmdBufBaseAddr.u64 = u64Value & IOMMU_CMD_BUF_BAR_VALID_MASK;
2062
2063 /* Validate the length. */
2064 if (CmdBufBaseAddr.n.u4Len >= 8)
2065 {
2066 /* Update the register. */
2067 pThis->CmdBufBaseAddr.u64 = CmdBufBaseAddr.u64;
2068
2069 /*
2070 * Writing the command buffer base address, clears the command buffer head and tail pointers.
2071 * See AMD IOMMU spec. 2.4 "Commands".
2072 */
2073 pThis->CmdBufHeadPtr.u64 = 0;
2074 pThis->CmdBufTailPtr.u64 = 0;
2075 }
2076 else
2077 LogFunc(("Command buffer length (%#x) invalid -> Ignored\n", CmdBufBaseAddr.n.u4Len));
2078
2079 return VINF_SUCCESS;
2080}
2081
2082
2083/**
2084 * Writes the Event Log Base Address Register.
2085 */
2086static VBOXSTRICTRC iommuAmdEvtLogBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2087{
2088 RT_NOREF(pDevIns, offReg);
2089
2090 /*
2091 * IOMMU behavior is undefined when software writes this register when event logging is running.
2092 * In our emulation, we ignore the write entirely.
2093 * See AMD IOMMU spec. "Event Log Base Address Register".
2094 */
2095 if (pThis->Status.n.u1EvtLogRunning)
2096 {
2097 LogFunc(("Setting EvtLogBar (%#RX64) when event logging is running -> Ignored\n", u64Value));
2098 return VINF_SUCCESS;
2099 }
2100
2101 /* Mask out all unrecognized bits. */
2102 u64Value &= IOMMU_EVT_LOG_BAR_VALID_MASK;
2103 EVT_LOG_BAR_T EvtLogBaseAddr;
2104 EvtLogBaseAddr.u64 = u64Value;
2105
2106 /* Validate the length. */
2107 if (EvtLogBaseAddr.n.u4Len >= 8)
2108 {
2109 /* Update the register. */
2110 pThis->EvtLogBaseAddr.u64 = EvtLogBaseAddr.u64;
2111
2112 /*
2113 * Writing the event log base address, clears the event log head and tail pointers.
2114 * See AMD IOMMU spec. 2.5 "Event Logging".
2115 */
2116 pThis->EvtLogHeadPtr.u64 = 0;
2117 pThis->EvtLogTailPtr.u64 = 0;
2118 }
2119 else
2120 LogFunc(("Event log length (%#x) invalid -> Ignored\n", EvtLogBaseAddr.n.u4Len));
2121
2122 return VINF_SUCCESS;
2123}
2124
2125
2126/**
2127 * Writes the Control Register.
2128 */
2129static VBOXSTRICTRC iommuAmdCtrl_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2130{
2131 RT_NOREF(pDevIns, offReg);
2132
2133 /* Mask out all unrecognized bits. */
2134 u64Value &= IOMMU_CTRL_VALID_MASK;
2135 IOMMU_CTRL_T NewCtrl;
2136 NewCtrl.u64 = u64Value;
2137
2138 /* Ensure the device table segments are within limits. */
2139 if (NewCtrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup)
2140 {
2141 IOMMU_CTRL_T const OldCtrl = pThis->Ctrl;
2142
2143 /* Update the register. */
2144 ASMAtomicWriteU64(&pThis->Ctrl.u64, NewCtrl.u64);
2145
2146 bool const fNewIommuEn = NewCtrl.n.u1IommuEn;
2147 bool const fOldIommuEn = OldCtrl.n.u1IommuEn;
2148
2149 /* Enable or disable event logging when the bit transitions. */
2150 bool const fOldEvtLogEn = OldCtrl.n.u1EvtLogEn;
2151 bool const fNewEvtLogEn = NewCtrl.n.u1EvtLogEn;
2152 if ( fOldEvtLogEn != fNewEvtLogEn
2153 || fOldIommuEn != fNewIommuEn)
2154 {
2155 if ( fNewIommuEn
2156 && fNewEvtLogEn)
2157 {
2158 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_OVERFLOW);
2159 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_RUNNING);
2160 }
2161 else
2162 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_EVT_LOG_RUNNING);
2163 }
2164
2165 /* Enable or disable command buffer processing when the bit transitions. */
2166 bool const fOldCmdBufEn = OldCtrl.n.u1CmdBufEn;
2167 bool const fNewCmdBufEn = NewCtrl.n.u1CmdBufEn;
2168 if ( fOldCmdBufEn != fNewCmdBufEn
2169 || fOldIommuEn != fNewIommuEn)
2170 {
2171 if ( fNewCmdBufEn
2172 && fNewIommuEn)
2173 {
2174 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_CMD_BUF_RUNNING);
2175 LogFunc(("Command buffer enabled\n"));
2176
2177 /* Wake up the command thread to start processing commands if any. */
2178 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2179 }
2180 else
2181 {
2182 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
2183 LogFunc(("Command buffer disabled\n"));
2184 }
2185 }
2186 }
2187 else
2188 {
2189 LogFunc(("Invalid number of device table segments enabled, exceeds %#x (%#RX64) -> Ignored!\n",
2190 pThis->ExtFeat.n.u2DevTabSegSup, NewCtrl.u64));
2191 }
2192
2193 return VINF_SUCCESS;
2194}
2195
2196
2197/**
2198 * Writes to the Exclusion Range Base Address Register.
2199 */
2200static VBOXSTRICTRC iommuAmdExclRangeBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2201{
2202 RT_NOREF(pDevIns, offReg);
2203 pThis->ExclRangeBaseAddr.u64 = u64Value & IOMMU_EXCL_RANGE_BAR_VALID_MASK;
2204 return VINF_SUCCESS;
2205}
2206
2207
2208/**
2209 * Writes to the Exclusion Range Limit Register.
2210 */
2211static VBOXSTRICTRC iommuAmdExclRangeLimit_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2212{
2213 RT_NOREF(pDevIns, offReg);
2214 u64Value &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
2215 u64Value |= UINT64_C(0xfff);
2216 pThis->ExclRangeLimit.u64 = u64Value;
2217 return VINF_SUCCESS;
2218}
2219
2220
2221/**
2222 * Writes the Hardware Event Register (Hi).
2223 */
2224static VBOXSTRICTRC iommuAmdHwEvtHi_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2225{
2226 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2227 RT_NOREF(pDevIns, offReg);
2228 LogFlowFunc(("Writing %#RX64 to hardware event (Hi) register!\n", u64Value));
2229 pThis->HwEvtHi.u64 = u64Value;
2230 return VINF_SUCCESS;
2231}
2232
2233
2234/**
2235 * Writes the Hardware Event Register (Lo).
2236 */
2237static VBOXSTRICTRC iommuAmdHwEvtLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2238{
2239 /** @todo IOMMU: Why the heck is this marked read/write by the AMD IOMMU spec? */
2240 RT_NOREF(pDevIns, offReg);
2241 LogFlowFunc(("Writing %#RX64 to hardware event (Lo) register!\n", u64Value));
2242 pThis->HwEvtLo = u64Value;
2243 return VINF_SUCCESS;
2244}
2245
2246
2247/**
2248 * Writes the Hardware Event Status Register.
2249 */
2250static VBOXSTRICTRC iommuAmdHwEvtStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2251{
2252 RT_NOREF(pDevIns, offReg);
2253
2254 /* Mask out all unrecognized bits. */
2255 u64Value &= IOMMU_HW_EVT_STATUS_VALID_MASK;
2256
2257 /*
2258 * The two bits (HEO and HEV) are RW1C (Read/Write 1-to-Clear; writing 0 has no effect).
2259 * If the current status bits or the bits being written are both 0, we've nothing to do.
2260 * The Overflow bit (bit 1) is only valid when the Valid bit (bit 0) is 1.
2261 */
2262 uint64_t HwStatus = pThis->HwEvtStatus.u64;
2263 if (!(HwStatus & RT_BIT(0)))
2264 return VINF_SUCCESS;
2265 if (u64Value & HwStatus & RT_BIT_64(0))
2266 HwStatus &= ~RT_BIT_64(0);
2267 if (u64Value & HwStatus & RT_BIT_64(1))
2268 HwStatus &= ~RT_BIT_64(1);
2269
2270 /* Update the register. */
2271 pThis->HwEvtStatus.u64 = HwStatus;
2272 return VINF_SUCCESS;
2273}
2274
2275
2276/**
2277 * Writes the Device Table Segment Base Address Register.
2278 */
2279static VBOXSTRICTRC iommuAmdDevTabSegBar_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2280{
2281 RT_NOREF(pDevIns);
2282
2283 /* Figure out which segment is being written. */
2284 uint8_t const offSegment = (offReg - IOMMU_MMIO_OFF_DEV_TAB_SEG_FIRST) >> 3;
2285 uint8_t const idxSegment = offSegment + 1;
2286 Assert(idxSegment < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
2287
2288 /* Mask out all unrecognized bits. */
2289 u64Value &= IOMMU_DEV_TAB_SEG_BAR_VALID_MASK;
2290 DEV_TAB_BAR_T DevTabSegBar;
2291 DevTabSegBar.u64 = u64Value;
2292
2293 /* Validate the size. */
2294 uint16_t const uSegSize = DevTabSegBar.n.u9Size;
2295 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[idxSegment];
2296 if (uSegSize <= uMaxSegSize)
2297 {
2298 /* Update the register. */
2299 pThis->aDevTabBaseAddrs[idxSegment].u64 = u64Value;
2300 }
2301 else
2302 LogFunc(("Device table segment (%u) size invalid (%#RX32) -> Ignored\n", idxSegment, uSegSize));
2303
2304 return VINF_SUCCESS;
2305}
2306
2307
2308/**
2309 * Writes the MSI Vector Register 0 (32-bit) and the MSI Vector Register 1 (32-bit).
2310 */
2311static VBOXSTRICTRC iommuAmdDevMsiVector_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2312{
2313 RT_NOREF(pDevIns, offReg);
2314
2315 /* MSI Vector Register 0 is read-only. */
2316 /* MSI Vector Register 1. */
2317 uint32_t const uReg = u64Value >> 32;
2318 pThis->MiscInfo.au32[1] = uReg & IOMMU_MSI_VECTOR_1_VALID_MASK;
2319 return VINF_SUCCESS;
2320}
2321
2322
2323/**
2324 * Writes the MSI Capability Header Register (32-bit) or the MSI Address (Lo)
2325 * Register (32-bit).
2326 */
2327static VBOXSTRICTRC iommuAmdMsiCapHdrAndAddrLo_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2328{
2329 RT_NOREF(pThis, offReg);
2330 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2331 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2332
2333 /* MSI capability header. */
2334 {
2335 uint32_t const uReg = u64Value;
2336 MSI_CAP_HDR_T MsiCapHdr;
2337 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
2338 MsiCapHdr.n.u1MsiEnable = RT_BOOL(uReg & IOMMU_MSI_CAP_HDR_MSI_EN_MASK);
2339 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR, MsiCapHdr.u32);
2340 }
2341
2342 /* MSI Address Lo. */
2343 {
2344 uint32_t const uReg = u64Value >> 32;
2345 uint32_t const uMsiAddrLo = uReg & VBOX_MSI_ADDR_VALID_MASK;
2346 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, uMsiAddrLo);
2347 }
2348
2349 return VINF_SUCCESS;
2350}
2351
2352
2353/**
2354 * Writes the MSI Address (Hi) Register (32-bit) or the MSI data register (32-bit).
2355 */
2356static VBOXSTRICTRC iommuAmdMsiAddrHiAndData_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2357{
2358 RT_NOREF(pThis, offReg);
2359 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2360 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2361
2362 /* MSI Address Hi. */
2363 {
2364 uint32_t const uReg = u64Value;
2365 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, uReg);
2366 }
2367
2368 /* MSI Data. */
2369 {
2370 uint32_t const uReg = u64Value >> 32;
2371 uint32_t const uMsiData = uReg & VBOX_MSI_DATA_VALID_MASK;
2372 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, uMsiData);
2373 }
2374
2375 return VINF_SUCCESS;
2376}
2377
2378
2379/**
2380 * Writes the Command Buffer Head Pointer Register.
2381 */
2382static VBOXSTRICTRC iommuAmdCmdBufHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2383{
2384 RT_NOREF(pDevIns, offReg);
2385
2386 /*
2387 * IOMMU behavior is undefined when software writes this register when the command buffer is running.
2388 * In our emulation, we ignore the write entirely.
2389 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2390 */
2391 if (pThis->Status.n.u1CmdBufRunning)
2392 {
2393 LogFunc(("Setting CmdBufHeadPtr (%#RX64) when command buffer is running -> Ignored\n", u64Value));
2394 return VINF_SUCCESS;
2395 }
2396
2397 /*
2398 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2399 * In our emulation, we ignore the write entirely.
2400 */
2401 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
2402 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2403 Assert(cbBuf <= _512K);
2404 if (offBuf >= cbBuf)
2405 {
2406 LogFunc(("Setting CmdBufHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX23) -> Ignored\n", offBuf, cbBuf));
2407 return VINF_SUCCESS;
2408 }
2409
2410 /* Update the register. */
2411 pThis->CmdBufHeadPtr.au32[0] = offBuf;
2412
2413 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2414
2415 Log4Func(("Set CmdBufHeadPtr to %#RX32\n", offBuf));
2416 return VINF_SUCCESS;
2417}
2418
2419
2420/**
2421 * Writes the Command Buffer Tail Pointer Register.
2422 */
2423static VBOXSTRICTRC iommuAmdCmdBufTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2424{
2425 RT_NOREF(pDevIns, offReg);
2426
2427 /*
2428 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2429 * In our emulation, we ignore the write entirely.
2430 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2431 */
2432 uint32_t const offBuf = u64Value & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
2433 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
2434 Assert(cbBuf <= _512K);
2435 if (offBuf >= cbBuf)
2436 {
2437 LogFunc(("Setting CmdBufTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2438 return VINF_SUCCESS;
2439 }
2440
2441 /*
2442 * IOMMU behavior is undefined if software advances the tail pointer equal to or beyond the
2443 * head pointer after adding one or more commands to the buffer.
2444 *
2445 * However, we cannot enforce this strictly because it's legal for software to shrink the
2446 * command queue (by reducing the offset) as well as wrap around the pointer (when head isn't
2447 * at 0). Software might even make the queue empty by making head and tail equal which is
2448 * allowed. I don't think we can or should try too hard to prevent software shooting itself
2449 * in the foot here. As long as we make sure the offset value is within the circular buffer
2450 * bounds (which we do by masking bits above) it should be sufficient.
2451 */
2452 pThis->CmdBufTailPtr.au32[0] = offBuf;
2453
2454 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
2455
2456 Log4Func(("Set CmdBufTailPtr to %#RX32\n", offBuf));
2457 return VINF_SUCCESS;
2458}
2459
2460
2461/**
2462 * Writes the Event Log Head Pointer Register.
2463 */
2464static VBOXSTRICTRC iommuAmdEvtLogHeadPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2465{
2466 RT_NOREF(pDevIns, offReg);
2467
2468 /*
2469 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2470 * In our emulation, we ignore the write entirely.
2471 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2472 */
2473 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
2474 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2475 Assert(cbBuf <= _512K);
2476 if (offBuf >= cbBuf)
2477 {
2478 LogFunc(("Setting EvtLogHeadPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2479 return VINF_SUCCESS;
2480 }
2481
2482 /* Update the register. */
2483 pThis->EvtLogHeadPtr.au32[0] = offBuf;
2484
2485 Log4Func(("Set EvtLogHeadPtr to %#RX32\n", offBuf));
2486 return VINF_SUCCESS;
2487}
2488
2489
2490/**
2491 * Writes the Event Log Tail Pointer Register.
2492 */
2493static VBOXSTRICTRC iommuAmdEvtLogTailPtr_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2494{
2495 RT_NOREF(pDevIns, offReg);
2496 NOREF(pThis);
2497
2498 /*
2499 * IOMMU behavior is undefined when software writes this register when the event log is running.
2500 * In our emulation, we ignore the write entirely.
2501 * See AMD IOMMU spec. 3.3.13 "Command and Event Log Pointer Registers".
2502 */
2503 if (pThis->Status.n.u1EvtLogRunning)
2504 {
2505 LogFunc(("Setting EvtLogTailPtr (%#RX64) when event log is running -> Ignored\n", u64Value));
2506 return VINF_SUCCESS;
2507 }
2508
2509 /*
2510 * IOMMU behavior is undefined when software writes a value outside the buffer length.
2511 * In our emulation, we ignore the write entirely.
2512 */
2513 uint32_t const offBuf = u64Value & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
2514 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
2515 Assert(cbBuf <= _512K);
2516 if (offBuf >= cbBuf)
2517 {
2518 LogFunc(("Setting EvtLogTailPtr (%#RX32) to a value that exceeds buffer length (%#RX32) -> Ignored\n", offBuf, cbBuf));
2519 return VINF_SUCCESS;
2520 }
2521
2522 /* Update the register. */
2523 pThis->EvtLogTailPtr.au32[0] = offBuf;
2524
2525 Log4Func(("Set EvtLogTailPtr to %#RX32\n", offBuf));
2526 return VINF_SUCCESS;
2527}
2528
2529
2530/**
2531 * Writes the Status Register.
2532 */
2533static VBOXSTRICTRC iommuAmdStatus_w(PPDMDEVINS pDevIns, PIOMMU pThis, uint32_t offReg, uint64_t u64Value)
2534{
2535 RT_NOREF(pDevIns, offReg);
2536
2537 /* Mask out all unrecognized bits. */
2538 u64Value &= IOMMU_STATUS_VALID_MASK;
2539
2540 /*
2541 * Compute RW1C (read-only, write-1-to-clear) bits and preserve the rest (which are read-only).
2542 * Writing 0 to an RW1C bit has no effect. Writing 1 to an RW1C bit, clears the bit if it's already 1.
2543 */
2544 IOMMU_STATUS_T const OldStatus = pThis->Status;
2545 uint64_t const fOldRw1cBits = (OldStatus.u64 & IOMMU_STATUS_RW1C_MASK);
2546 uint64_t const fOldRoBits = (OldStatus.u64 & ~IOMMU_STATUS_RW1C_MASK);
2547 uint64_t const fNewRw1cBits = (u64Value & IOMMU_STATUS_RW1C_MASK);
2548
2549 uint64_t const uNewStatus = (fOldRw1cBits & ~fNewRw1cBits) | fOldRoBits;
2550
2551 /* Update the register. */
2552 ASMAtomicWriteU64(&pThis->Status.u64, uNewStatus);
2553 return VINF_SUCCESS;
2554}
2555
2556
2557/**
2558 * Register access table 0.
2559 * The MMIO offset of each entry must be a multiple of 8!
2560 */
2561static const IOMMUREGACC g_aRegAccess0[] =
2562{
2563 /* MMIO off. Register name Read function Write function */
2564 { /* 0x00 */ "DEV_TAB_BAR", iommuAmdDevTabBar_r, iommuAmdDevTabBar_w },
2565 { /* 0x08 */ "CMD_BUF_BAR", iommuAmdCmdBufBar_r, iommuAmdCmdBufBar_w },
2566 { /* 0x10 */ "EVT_LOG_BAR", iommuAmdEvtLogBar_r, iommuAmdEvtLogBar_w },
2567 { /* 0x18 */ "CTRL", iommuAmdCtrl_r, iommuAmdCtrl_w },
2568 { /* 0x20 */ "EXCL_BAR", iommuAmdExclRangeBar_r, iommuAmdExclRangeBar_w },
2569 { /* 0x28 */ "EXCL_RANGE_LIMIT", iommuAmdExclRangeLimit_r, iommuAmdExclRangeLimit_w },
2570 { /* 0x30 */ "EXT_FEAT", iommuAmdExtFeat_r, NULL },
2571 { /* 0x38 */ "PPR_LOG_BAR", iommuAmdPprLogBar_r, NULL },
2572 { /* 0x40 */ "HW_EVT_HI", iommuAmdHwEvtHi_r, iommuAmdHwEvtHi_w },
2573 { /* 0x48 */ "HW_EVT_LO", iommuAmdHwEvtLo_r, iommuAmdHwEvtLo_w },
2574 { /* 0x50 */ "HW_EVT_STATUS", iommuAmdHwEvtStatus_r, iommuAmdHwEvtStatus_w },
2575 { /* 0x58 */ NULL, NULL, NULL },
2576
2577 { /* 0x60 */ "SMI_FLT_0", NULL, NULL },
2578 { /* 0x68 */ "SMI_FLT_1", NULL, NULL },
2579 { /* 0x70 */ "SMI_FLT_2", NULL, NULL },
2580 { /* 0x78 */ "SMI_FLT_3", NULL, NULL },
2581 { /* 0x80 */ "SMI_FLT_4", NULL, NULL },
2582 { /* 0x88 */ "SMI_FLT_5", NULL, NULL },
2583 { /* 0x90 */ "SMI_FLT_6", NULL, NULL },
2584 { /* 0x98 */ "SMI_FLT_7", NULL, NULL },
2585 { /* 0xa0 */ "SMI_FLT_8", NULL, NULL },
2586 { /* 0xa8 */ "SMI_FLT_9", NULL, NULL },
2587 { /* 0xb0 */ "SMI_FLT_10", NULL, NULL },
2588 { /* 0xb8 */ "SMI_FLT_11", NULL, NULL },
2589 { /* 0xc0 */ "SMI_FLT_12", NULL, NULL },
2590 { /* 0xc8 */ "SMI_FLT_13", NULL, NULL },
2591 { /* 0xd0 */ "SMI_FLT_14", NULL, NULL },
2592 { /* 0xd8 */ "SMI_FLT_15", NULL, NULL },
2593
2594 { /* 0xe0 */ "GALOG_BAR", iommuAmdGALogBar_r, NULL },
2595 { /* 0xe8 */ "GALOG_TAIL_ADDR", NULL, NULL },
2596 { /* 0xf0 */ "PPR_LOG_B_BAR", iommuAmdPprLogBBaseAddr_r, NULL },
2597 { /* 0xf8 */ "PPR_EVT_B_BAR", iommuAmdEvtLogBBaseAddr_r, NULL },
2598
2599 { /* 0x100 */ "DEV_TAB_SEG_1", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2600 { /* 0x108 */ "DEV_TAB_SEG_2", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2601 { /* 0x110 */ "DEV_TAB_SEG_3", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2602 { /* 0x118 */ "DEV_TAB_SEG_4", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2603 { /* 0x120 */ "DEV_TAB_SEG_5", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2604 { /* 0x128 */ "DEV_TAB_SEG_6", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2605 { /* 0x130 */ "DEV_TAB_SEG_7", iommuAmdDevTabSegBar_r, iommuAmdDevTabSegBar_w },
2606
2607 { /* 0x138 */ "DEV_SPECIFIC_FEAT", iommuAmdDevSpecificFeat_r, NULL },
2608 { /* 0x140 */ "DEV_SPECIFIC_CTRL", iommuAmdDevSpecificCtrl_r, NULL },
2609 { /* 0x148 */ "DEV_SPECIFIC_STATUS", iommuAmdDevSpecificStatus_r, NULL },
2610
2611 { /* 0x150 */ "MSI_VECTOR_0 or MSI_VECTOR_1", iommuAmdDevMsiVector_r, iommuAmdDevMsiVector_w },
2612 { /* 0x158 */ "MSI_CAP_HDR or MSI_ADDR_LO", iommuAmdMsiCapHdrAndAddrLo_r, iommuAmdMsiCapHdrAndAddrLo_w },
2613 { /* 0x160 */ "MSI_ADDR_HI or MSI_DATA", iommuAmdMsiAddrHiAndData_r, iommuAmdMsiAddrHiAndData_w },
2614 { /* 0x168 */ "MSI_MAPPING_CAP_HDR or PERF_OPT_CTRL", NULL, NULL },
2615
2616 { /* 0x170 */ "XT_GEN_INTR_CTRL", NULL, NULL },
2617 { /* 0x178 */ "XT_PPR_INTR_CTRL", NULL, NULL },
2618 { /* 0x180 */ "XT_GALOG_INT_CTRL", NULL, NULL },
2619};
2620AssertCompile(RT_ELEMENTS(g_aRegAccess0) == (IOMMU_MMIO_OFF_QWORD_TABLE_0_END - IOMMU_MMIO_OFF_QWORD_TABLE_0_START) / 8);
2621
2622/**
2623 * Register access table 1.
2624 * The MMIO offset of each entry must be a multiple of 8!
2625 */
2626static const IOMMUREGACC g_aRegAccess1[] =
2627{
2628 /* MMIO offset Register name Read function Write function */
2629 { /* 0x200 */ "MARC_APER_BAR_0", NULL, NULL },
2630 { /* 0x208 */ "MARC_APER_RELOC_0", NULL, NULL },
2631 { /* 0x210 */ "MARC_APER_LEN_0", NULL, NULL },
2632 { /* 0x218 */ "MARC_APER_BAR_1", NULL, NULL },
2633 { /* 0x220 */ "MARC_APER_RELOC_1", NULL, NULL },
2634 { /* 0x228 */ "MARC_APER_LEN_1", NULL, NULL },
2635 { /* 0x230 */ "MARC_APER_BAR_2", NULL, NULL },
2636 { /* 0x238 */ "MARC_APER_RELOC_2", NULL, NULL },
2637 { /* 0x240 */ "MARC_APER_LEN_2", NULL, NULL },
2638 { /* 0x248 */ "MARC_APER_BAR_3", NULL, NULL },
2639 { /* 0x250 */ "MARC_APER_RELOC_3", NULL, NULL },
2640 { /* 0x258 */ "MARC_APER_LEN_3", NULL, NULL }
2641};
2642AssertCompile(RT_ELEMENTS(g_aRegAccess1) == (IOMMU_MMIO_OFF_QWORD_TABLE_1_END - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) / 8);
2643
2644/**
2645 * Register access table 2.
2646 * The MMIO offset of each entry must be a multiple of 8!
2647 */
2648static const IOMMUREGACC g_aRegAccess2[] =
2649{
2650 /* MMIO offset Register name Read Function Write function */
2651 { /* 0x1ff8 */ "RSVD_REG", NULL, NULL },
2652
2653 { /* 0x2000 */ "CMD_BUF_HEAD_PTR", iommuAmdCmdBufHeadPtr_r, iommuAmdCmdBufHeadPtr_w },
2654 { /* 0x2008 */ "CMD_BUF_TAIL_PTR", iommuAmdCmdBufTailPtr_r , iommuAmdCmdBufTailPtr_w },
2655 { /* 0x2010 */ "EVT_LOG_HEAD_PTR", iommuAmdEvtLogHeadPtr_r, iommuAmdEvtLogHeadPtr_w },
2656 { /* 0x2018 */ "EVT_LOG_TAIL_PTR", iommuAmdEvtLogTailPtr_r, iommuAmdEvtLogTailPtr_w },
2657
2658 { /* 0x2020 */ "STATUS", iommuAmdStatus_r, iommuAmdStatus_w },
2659 { /* 0x2028 */ NULL, NULL, NULL },
2660
2661 { /* 0x2030 */ "PPR_LOG_HEAD_PTR", NULL, NULL },
2662 { /* 0x2038 */ "PPR_LOG_TAIL_PTR", NULL, NULL },
2663
2664 { /* 0x2040 */ "GALOG_HEAD_PTR", NULL, NULL },
2665 { /* 0x2048 */ "GALOG_TAIL_PTR", NULL, NULL },
2666
2667 { /* 0x2050 */ "PPR_LOG_B_HEAD_PTR", NULL, NULL },
2668 { /* 0x2058 */ "PPR_LOG_B_TAIL_PTR", NULL, NULL },
2669
2670 { /* 0x2060 */ NULL, NULL, NULL },
2671 { /* 0x2068 */ NULL, NULL, NULL },
2672
2673 { /* 0x2070 */ "EVT_LOG_B_HEAD_PTR", NULL, NULL },
2674 { /* 0x2078 */ "EVT_LOG_B_TAIL_PTR", NULL, NULL },
2675
2676 { /* 0x2080 */ "PPR_LOG_AUTO_RESP", NULL, NULL },
2677 { /* 0x2088 */ "PPR_LOG_OVERFLOW_EARLY", NULL, NULL },
2678 { /* 0x2090 */ "PPR_LOG_B_OVERFLOW_EARLY", NULL, NULL }
2679};
2680AssertCompile(RT_ELEMENTS(g_aRegAccess2) == (IOMMU_MMIO_OFF_QWORD_TABLE_2_END - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) / 8);
2681
2682
2683/**
2684 * Gets the register access structure given its MMIO offset.
2685 *
2686 * @returns The register access structure, or NULL if the offset is invalid.
2687 * @param off The MMIO offset of the register being accessed.
2688 */
2689static PCIOMMUREGACC iommuAmdGetRegAccess(uint32_t off)
2690{
2691 /* Figure out which table the register belongs to and validate its index. */
2692 PCIOMMUREGACC pReg;
2693 if (off < IOMMU_MMIO_OFF_QWORD_TABLE_0_END)
2694 {
2695 uint32_t const idxReg = off >> 3;
2696 Assert(idxReg < RT_ELEMENTS(g_aRegAccess0));
2697 pReg = &g_aRegAccess0[idxReg];
2698 }
2699 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_1_END
2700 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_1_START)
2701 {
2702 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_1_START) >> 3;
2703 Assert(idxReg < RT_ELEMENTS(g_aRegAccess1));
2704 pReg = &g_aRegAccess1[idxReg];
2705 }
2706 else if ( off < IOMMU_MMIO_OFF_QWORD_TABLE_2_END
2707 && off >= IOMMU_MMIO_OFF_QWORD_TABLE_2_START)
2708 {
2709 uint32_t const idxReg = (off - IOMMU_MMIO_OFF_QWORD_TABLE_2_START) >> 3;
2710 Assert(idxReg < RT_ELEMENTS(g_aRegAccess2));
2711 pReg = &g_aRegAccess2[idxReg];
2712 }
2713 else
2714 pReg = NULL;
2715 return pReg;
2716}
2717
2718
2719/**
2720 * Writes an IOMMU register (32-bit and 64-bit).
2721 *
2722 * @returns Strict VBox status code.
2723 * @param pDevIns The IOMMU device instance.
2724 * @param off MMIO byte offset to the register.
2725 * @param cb The size of the write access.
2726 * @param uValue The value being written.
2727 *
2728 * @thread EMT.
2729 */
2730static VBOXSTRICTRC iommuAmdRegisterWrite(PPDMDEVINS pDevIns, uint32_t off, uint8_t cb, uint64_t uValue)
2731{
2732 /*
2733 * Validate the access in case of IOM bug or incorrect assumption.
2734 */
2735 Assert(off < IOMMU_MMIO_REGION_SIZE);
2736 AssertMsgReturn(cb == 4 || cb == 8, ("Invalid access size %u\n", cb), VINF_SUCCESS);
2737 AssertMsgReturn(!(off & 3), ("Invalid offset %#x\n", off), VINF_SUCCESS);
2738
2739 Log4Func(("off=%#x cb=%u uValue=%#RX64\n", off, cb, uValue));
2740
2741 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2742 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2743 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2744 if (pReg)
2745 { /* likely */ }
2746 else
2747 {
2748 LogFunc(("Writing unknown register %#x with %#RX64 -> Ignored\n", off, uValue));
2749 return VINF_SUCCESS;
2750 }
2751
2752 /* If a write handler doesn't exist, it's either a reserved or read-only register. */
2753 if (pReg->pfnWrite)
2754 { /* likely */ }
2755 else
2756 {
2757 LogFunc(("Writing reserved or read-only register off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2758 return VINF_SUCCESS;
2759 }
2760
2761 /*
2762 * If the write access is 64-bits and aligned on a 64-bit boundary, dispatch right away.
2763 * This handles writes to 64-bit registers as well as aligned, 64-bit writes to two
2764 * consecutive 32-bit registers.
2765 */
2766 if (cb == 8)
2767 {
2768 if (!(off & 7))
2769 {
2770 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2771 VBOXSTRICTRC rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2772 IOMMU_UNLOCK(pDevIns, pThisCC);
2773 return rcStrict;
2774 }
2775
2776 LogFunc(("Misaligned access while writing register at off=%#x (cb=%u) with %#RX64 -> Ignored\n", off, cb, uValue));
2777 return VINF_SUCCESS;
2778 }
2779
2780 /* We shouldn't get sizes other than 32 bits here as we've specified so with IOM. */
2781 Assert(cb == 4);
2782 if (!(off & 7))
2783 {
2784 VBOXSTRICTRC rcStrict;
2785 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2786
2787 /*
2788 * Lower 32 bits of a 64-bit register or a 32-bit register is being written.
2789 * Merge with higher 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2790 */
2791 uint64_t u64Read;
2792 if (pReg->pfnRead)
2793 rcStrict = pReg->pfnRead(pDevIns, pThis, off, &u64Read);
2794 else
2795 {
2796 rcStrict = VINF_SUCCESS;
2797 u64Read = 0;
2798 }
2799
2800 if (RT_SUCCESS(rcStrict))
2801 {
2802 uValue = (u64Read & UINT64_C(0xffffffff00000000)) | uValue;
2803 rcStrict = pReg->pfnWrite(pDevIns, pThis, off, uValue);
2804 }
2805 else
2806 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2807
2808 IOMMU_UNLOCK(pDevIns, pThisCC);
2809 return rcStrict;
2810 }
2811
2812 /*
2813 * Higher 32 bits of a 64-bit register or a 32-bit register at a 32-bit boundary is being written.
2814 * Merge with lower 32 bits (after reading the full 64-bits) and perform a 64-bit write.
2815 */
2816 VBOXSTRICTRC rcStrict;
2817 Assert(!(off & 3));
2818 Assert(off & 7);
2819 Assert(off >= 4);
2820 uint64_t u64Read;
2821 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2822 if (pReg->pfnRead)
2823 rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, &u64Read);
2824 else
2825 {
2826 rcStrict = VINF_SUCCESS;
2827 u64Read = 0;
2828 }
2829
2830 if (RT_SUCCESS(rcStrict))
2831 {
2832 uValue = (uValue << 32) | (u64Read & UINT64_C(0xffffffff));
2833 rcStrict = pReg->pfnWrite(pDevIns, pThis, off - 4, uValue);
2834 }
2835 else
2836 LogFunc(("Reading off %#x during split write failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2837
2838 IOMMU_UNLOCK(pDevIns, pThisCC);
2839 return rcStrict;
2840}
2841
2842
2843/**
2844 * Reads an IOMMU register (64-bit) given its MMIO offset.
2845 *
2846 * All reads are 64-bit but reads to 32-bit registers that are aligned on an 8-byte
2847 * boundary include the lower half of the subsequent register.
2848 *
2849 * This is because most registers are 64-bit and aligned on 8-byte boundaries but
2850 * some are really 32-bit registers aligned on an 8-byte boundary. We cannot assume
2851 * software will only perform 32-bit reads on those 32-bit registers that are
2852 * aligned on 8-byte boundaries.
2853 *
2854 * @returns Strict VBox status code.
2855 * @param pDevIns The IOMMU device instance.
2856 * @param off The MMIO offset of the register in bytes.
2857 * @param puResult Where to store the value being read.
2858 *
2859 * @thread EMT.
2860 */
2861static VBOXSTRICTRC iommuAmdRegisterRead(PPDMDEVINS pDevIns, uint32_t off, uint64_t *puResult)
2862{
2863 Assert(off < IOMMU_MMIO_REGION_SIZE);
2864 Assert(!(off & 7) || !(off & 3));
2865
2866 Log4Func(("off=%#x\n", off));
2867
2868 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2869 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2870 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2871 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev); NOREF(pPciDev);
2872
2873 PCIOMMUREGACC pReg = iommuAmdGetRegAccess(off);
2874 if (pReg)
2875 { /* likely */ }
2876 else
2877 {
2878 LogFunc(("Reading unknown register %#x -> Ignored\n", off));
2879 return VINF_IOM_MMIO_UNUSED_FF;
2880 }
2881
2882 /* If a read handler doesn't exist, it's a reserved or unknown register. */
2883 if (pReg->pfnRead)
2884 { /* likely */ }
2885 else
2886 {
2887 LogFunc(("Reading reserved or unknown register off=%#x -> returning 0s\n", off));
2888 return VINF_IOM_MMIO_UNUSED_00;
2889 }
2890
2891 /*
2892 * If the read access is aligned on a 64-bit boundary, read the full 64-bits and return.
2893 * The caller takes care of truncating upper 32 bits for 32-bit reads.
2894 */
2895 if (!(off & 7))
2896 {
2897 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2898 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off, puResult);
2899 IOMMU_UNLOCK(pDevIns, pThisCC);
2900 return rcStrict;
2901 }
2902
2903 /*
2904 * High 32 bits of a 64-bit register or a 32-bit register at a non 64-bit boundary is being read.
2905 * Read full 64 bits at the previous 64-bit boundary but return only the high 32 bits.
2906 */
2907 Assert(!(off & 3));
2908 Assert(off & 7);
2909 Assert(off >= 4);
2910 IOMMU_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2911 VBOXSTRICTRC rcStrict = pReg->pfnRead(pDevIns, pThis, off - 4, puResult);
2912 IOMMU_UNLOCK(pDevIns, pThisCC);
2913 if (RT_SUCCESS(rcStrict))
2914 *puResult >>= 32;
2915 else
2916 {
2917 *puResult = 0;
2918 LogFunc(("Reading off %#x during split read failed! rc=%Rrc\n -> Ignored", off, VBOXSTRICTRC_VAL(rcStrict)));
2919 }
2920
2921 return rcStrict;
2922}
2923
2924
2925/**
2926 * Raises the MSI interrupt for the IOMMU device.
2927 *
2928 * @param pDevIns The IOMMU device instance.
2929 *
2930 * @thread Any.
2931 * @remarks The IOMMU lock may or may not be held.
2932 */
2933static void iommuAmdMsiInterruptRaise(PPDMDEVINS pDevIns)
2934{
2935 LogFlowFunc(("\n"));
2936 if (iommuAmdIsMsiEnabled(pDevIns))
2937 {
2938 LogFunc(("Raising MSI\n"));
2939 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_HIGH);
2940 }
2941}
2942
2943#if 0
2944/**
2945 * Clears the MSI interrupt for the IOMMU device.
2946 *
2947 * @param pDevIns The IOMMU device instance.
2948 *
2949 * @thread Any.
2950 * @remarks The IOMMU lock may or may not be held.
2951 */
2952static void iommuAmdMsiInterruptClear(PPDMDEVINS pDevIns)
2953{
2954 if (iommuAmdIsMsiEnabled(pDevIns))
2955 PDMDevHlpPCISetIrq(pDevIns, 0, PDM_IRQ_LEVEL_LOW);
2956}
2957#endif
2958
2959/**
2960 * Writes an entry to the event log in memory.
2961 *
2962 * @returns VBox status code.
2963 * @param pDevIns The IOMMU device instance.
2964 * @param pEvent The event to log.
2965 *
2966 * @thread Any.
2967 * @remarks The IOMMU lock must be held while calling this function.
2968 */
2969static int iommuAmdEvtLogEntryWrite(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
2970{
2971 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
2972 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
2973
2974 IOMMU_LOCK(pDevIns, pThisCC);
2975
2976 /* Check if event logging is active and the log has not overflowed. */
2977 IOMMU_STATUS_T const Status = pThis->Status;
2978 if ( Status.n.u1EvtLogRunning
2979 && !Status.n.u1EvtOverflow)
2980 {
2981 uint32_t const cbEvt = sizeof(*pEvent);
2982
2983 /* Get the offset we need to write the event to in memory (circular buffer offset). */
2984 uint32_t const offEvt = pThis->EvtLogTailPtr.n.off;
2985 Assert(!(offEvt & ~IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK));
2986
2987 /* Ensure we have space in the event log. */
2988 uint32_t const cMaxEvts = iommuAmdGetBufMaxEntries(pThis->EvtLogBaseAddr.n.u4Len);
2989 uint32_t const cEvts = iommuAmdGetEvtLogEntryCount(pThis);
2990 if (cEvts + 1 < cMaxEvts)
2991 {
2992 /* Write the event log entry to memory. */
2993 RTGCPHYS const GCPhysEvtLog = pThis->EvtLogBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
2994 RTGCPHYS const GCPhysEvtLogEntry = GCPhysEvtLog + offEvt;
2995 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysEvtLogEntry, pEvent, cbEvt);
2996 if (RT_FAILURE(rc))
2997 LogFunc(("Failed to write event log entry at %#RGp. rc=%Rrc\n", GCPhysEvtLogEntry, rc));
2998
2999 /* Increment the event log tail pointer. */
3000 uint32_t const cbEvtLog = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
3001 pThis->EvtLogTailPtr.n.off = (offEvt + cbEvt) % cbEvtLog;
3002
3003 /* Indicate that an event log entry was written. */
3004 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_INTR);
3005
3006 /* Check and signal an interrupt if software wants to receive one when an event log entry is written. */
3007 if (pThis->Ctrl.n.u1EvtIntrEn)
3008 iommuAmdMsiInterruptRaise(pDevIns);
3009 }
3010 else
3011 {
3012 /* Indicate that the event log has overflowed. */
3013 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_EVT_LOG_OVERFLOW);
3014
3015 /* Check and signal an interrupt if software wants to receive one when the event log has overflowed. */
3016 if (pThis->Ctrl.n.u1EvtIntrEn)
3017 iommuAmdMsiInterruptRaise(pDevIns);
3018 }
3019 }
3020
3021 IOMMU_UNLOCK(pDevIns, pThisCC);
3022
3023 return VINF_SUCCESS;
3024}
3025
3026
3027/**
3028 * Sets an event in the hardware error registers.
3029 *
3030 * @param pDevIns The IOMMU device instance.
3031 * @param pEvent The event.
3032 *
3033 * @thread Any.
3034 */
3035static void iommuAmdHwErrorSet(PPDMDEVINS pDevIns, PCEVT_GENERIC_T pEvent)
3036{
3037 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3038 if (pThis->ExtFeat.n.u1HwErrorSup)
3039 {
3040 if (pThis->HwEvtStatus.n.u1Valid)
3041 pThis->HwEvtStatus.n.u1Overflow = 1;
3042 pThis->HwEvtStatus.n.u1Valid = 1;
3043 pThis->HwEvtHi.u64 = RT_MAKE_U64(pEvent->au32[0], pEvent->au32[1]);
3044 pThis->HwEvtLo = RT_MAKE_U64(pEvent->au32[2], pEvent->au32[3]);
3045 Assert( pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_DEV_TAB_HW_ERROR
3046 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_PAGE_TAB_HW_ERROR
3047 || pThis->HwEvtHi.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
3048 }
3049}
3050
3051
3052/**
3053 * Initializes a PAGE_TAB_HARDWARE_ERROR event.
3054 *
3055 * @param idDevice The device ID (bus, device, function).
3056 * @param idDomain The domain ID.
3057 * @param GCPhysPtEntity The system physical address of the page table
3058 * entity.
3059 * @param enmOp The IOMMU operation being performed.
3060 * @param pEvtPageTabHwErr Where to store the initialized event.
3061 */
3062static void iommuAmdPageTabHwErrorEventInit(uint16_t idDevice, uint16_t idDomain, RTGCPHYS GCPhysPtEntity, IOMMUOP enmOp,
3063 PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3064{
3065 memset(pEvtPageTabHwErr, 0, sizeof(*pEvtPageTabHwErr));
3066 pEvtPageTabHwErr->n.u16DevId = idDevice;
3067 pEvtPageTabHwErr->n.u16DomainOrPasidLo = idDomain;
3068 pEvtPageTabHwErr->n.u1GuestOrNested = 0;
3069 pEvtPageTabHwErr->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3070 pEvtPageTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3071 pEvtPageTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3072 pEvtPageTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3073 pEvtPageTabHwErr->n.u4EvtCode = IOMMU_EVT_PAGE_TAB_HW_ERROR;
3074 pEvtPageTabHwErr->n.u64Addr = GCPhysPtEntity;
3075}
3076
3077
3078/**
3079 * Raises a PAGE_TAB_HARDWARE_ERROR event.
3080 *
3081 * @param pDevIns The IOMMU device instance.
3082 * @param enmOp The IOMMU operation being performed.
3083 * @param pEvtPageTabHwErr The page table hardware error event.
3084 *
3085 * @thread Any.
3086 */
3087static void iommuAmdPageTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_PAGE_TAB_HW_ERR_T pEvtPageTabHwErr)
3088{
3089 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_PAGE_TAB_HW_ERR_T));
3090 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtPageTabHwErr;
3091
3092 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3093 IOMMU_LOCK(pDevIns, pThisCC);
3094
3095 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3096 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3097 if (enmOp != IOMMUOP_CMD)
3098 iommuAmdSetPciTargetAbort(pDevIns);
3099
3100 IOMMU_UNLOCK(pDevIns, pThisCC);
3101
3102 LogFunc(("Raised PAGE_TAB_HARDWARE_ERROR. idDevice=%#x idDomain=%#x GCPhysPtEntity=%#RGp enmOp=%u u2Type=%u\n",
3103 pEvtPageTabHwErr->n.u16DevId, pEvtPageTabHwErr->n.u16DomainOrPasidLo, pEvtPageTabHwErr->n.u64Addr, enmOp,
3104 pEvtPageTabHwErr->n.u2Type));
3105}
3106
3107
3108#ifdef IN_RING3
3109/**
3110 * Initializes a COMMAND_HARDWARE_ERROR event.
3111 *
3112 * @param GCPhysAddr The system physical address the IOMMU attempted to access.
3113 * @param pEvtCmdHwErr Where to store the initialized event.
3114 */
3115static void iommuAmdCmdHwErrorEventInit(RTGCPHYS GCPhysAddr, PEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3116{
3117 memset(pEvtCmdHwErr, 0, sizeof(*pEvtCmdHwErr));
3118 pEvtCmdHwErr->n.u2Type = HWEVTTYPE_DATA_ERROR;
3119 pEvtCmdHwErr->n.u4EvtCode = IOMMU_EVT_COMMAND_HW_ERROR;
3120 pEvtCmdHwErr->n.u64Addr = GCPhysAddr;
3121}
3122
3123
3124/**
3125 * Raises a COMMAND_HARDWARE_ERROR event.
3126 *
3127 * @param pDevIns The IOMMU device instance.
3128 * @param pEvtCmdHwErr The command hardware error event.
3129 *
3130 * @thread Any.
3131 */
3132static void iommuAmdCmdHwErrorEventRaise(PPDMDEVINS pDevIns, PCEVT_CMD_HW_ERR_T pEvtCmdHwErr)
3133{
3134 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_CMD_HW_ERR_T));
3135 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtCmdHwErr;
3136 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3137
3138 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3139 IOMMU_LOCK(pDevIns, pThisCC);
3140
3141 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3142 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3143 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3144
3145 IOMMU_UNLOCK(pDevIns, pThisCC);
3146
3147 LogFunc(("Raised COMMAND_HARDWARE_ERROR. GCPhysCmd=%#RGp u2Type=%u\n", pEvtCmdHwErr->n.u64Addr, pEvtCmdHwErr->n.u2Type));
3148}
3149#endif /* IN_RING3 */
3150
3151
3152/**
3153 * Initializes a DEV_TAB_HARDWARE_ERROR event.
3154 *
3155 * @param idDevice The device ID (bus, device, function).
3156 * @param GCPhysDte The system physical address of the failed device table
3157 * access.
3158 * @param enmOp The IOMMU operation being performed.
3159 * @param pEvtDevTabHwErr Where to store the initialized event.
3160 */
3161static void iommuAmdDevTabHwErrorEventInit(uint16_t idDevice, RTGCPHYS GCPhysDte, IOMMUOP enmOp,
3162 PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3163{
3164 memset(pEvtDevTabHwErr, 0, sizeof(*pEvtDevTabHwErr));
3165 pEvtDevTabHwErr->n.u16DevId = idDevice;
3166 pEvtDevTabHwErr->n.u1Intr = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3167 /** @todo IOMMU: Any other transaction type that can set read/write bit? */
3168 pEvtDevTabHwErr->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3169 pEvtDevTabHwErr->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3170 pEvtDevTabHwErr->n.u2Type = enmOp == IOMMUOP_CMD ? HWEVTTYPE_DATA_ERROR : HWEVTTYPE_TARGET_ABORT;
3171 pEvtDevTabHwErr->n.u4EvtCode = IOMMU_EVT_DEV_TAB_HW_ERROR;
3172 pEvtDevTabHwErr->n.u64Addr = GCPhysDte;
3173}
3174
3175
3176/**
3177 * Raises a DEV_TAB_HARDWARE_ERROR event.
3178 *
3179 * @param pDevIns The IOMMU device instance.
3180 * @param enmOp The IOMMU operation being performed.
3181 * @param pEvtDevTabHwErr The device table hardware error event.
3182 *
3183 * @thread Any.
3184 */
3185static void iommuAmdDevTabHwErrorEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PEVT_DEV_TAB_HW_ERROR_T pEvtDevTabHwErr)
3186{
3187 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_DEV_TAB_HW_ERROR_T));
3188 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtDevTabHwErr;
3189
3190 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3191 IOMMU_LOCK(pDevIns, pThisCC);
3192
3193 iommuAmdHwErrorSet(pDevIns, (PCEVT_GENERIC_T)pEvent);
3194 iommuAmdEvtLogEntryWrite(pDevIns, (PCEVT_GENERIC_T)pEvent);
3195 if (enmOp != IOMMUOP_CMD)
3196 iommuAmdSetPciTargetAbort(pDevIns);
3197
3198 IOMMU_UNLOCK(pDevIns, pThisCC);
3199
3200 LogFunc(("Raised DEV_TAB_HARDWARE_ERROR. idDevice=%#x GCPhysDte=%#RGp enmOp=%u u2Type=%u\n", pEvtDevTabHwErr->n.u16DevId,
3201 pEvtDevTabHwErr->n.u64Addr, enmOp, pEvtDevTabHwErr->n.u2Type));
3202}
3203
3204
3205#ifdef IN_RING3
3206/**
3207 * Initializes an ILLEGAL_COMMAND_ERROR event.
3208 *
3209 * @param GCPhysCmd The system physical address of the failed command
3210 * access.
3211 * @param pEvtIllegalCmd Where to store the initialized event.
3212 */
3213static void iommuAmdIllegalCmdEventInit(RTGCPHYS GCPhysCmd, PEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3214{
3215 Assert(!(GCPhysCmd & UINT64_C(0xf)));
3216 memset(pEvtIllegalCmd, 0, sizeof(*pEvtIllegalCmd));
3217 pEvtIllegalCmd->n.u4EvtCode = IOMMU_EVT_ILLEGAL_CMD_ERROR;
3218 pEvtIllegalCmd->n.u64Addr = GCPhysCmd;
3219}
3220
3221
3222/**
3223 * Raises an ILLEGAL_COMMAND_ERROR event.
3224 *
3225 * @param pDevIns The IOMMU device instance.
3226 * @param pEvtIllegalCmd The illegal command error event.
3227 */
3228static void iommuAmdIllegalCmdEventRaise(PPDMDEVINS pDevIns, PCEVT_ILLEGAL_CMD_ERR_T pEvtIllegalCmd)
3229{
3230 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3231 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalCmd;
3232 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3233
3234 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3235 ASMAtomicAndU64(&pThis->Status.u64, ~IOMMU_STATUS_CMD_BUF_RUNNING);
3236
3237 LogFunc(("Raised ILLEGAL_COMMAND_ERROR. Addr=%#RGp\n", pEvtIllegalCmd->n.u64Addr));
3238}
3239#endif /* IN_RING3 */
3240
3241
3242/**
3243 * Initializes an ILLEGAL_DEV_TABLE_ENTRY event.
3244 *
3245 * @param idDevice The device ID (bus, device, function).
3246 * @param uIova The I/O virtual address.
3247 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if the
3248 * event was caused by an invalid level encoding in the
3249 * DTE.
3250 * @param enmOp The IOMMU operation being performed.
3251 * @param pEvtIllegalDte Where to store the initialized event.
3252 */
3253static void iommuAmdIllegalDteEventInit(uint16_t idDevice, uint64_t uIova, bool fRsvdNotZero, IOMMUOP enmOp,
3254 PEVT_ILLEGAL_DTE_T pEvtIllegalDte)
3255{
3256 memset(pEvtIllegalDte, 0, sizeof(*pEvtIllegalDte));
3257 pEvtIllegalDte->n.u16DevId = idDevice;
3258 pEvtIllegalDte->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3259 pEvtIllegalDte->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3260 pEvtIllegalDte->n.u1RsvdNotZero = fRsvdNotZero;
3261 pEvtIllegalDte->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3262 pEvtIllegalDte->n.u4EvtCode = IOMMU_EVT_ILLEGAL_DEV_TAB_ENTRY;
3263 pEvtIllegalDte->n.u64Addr = uIova & ~UINT64_C(0x3);
3264 /** @todo r=ramshankar: Not sure why the last 2 bits are marked as reserved by the
3265 * IOMMU spec here but not for this field for I/O page fault event. */
3266 Assert(!(uIova & UINT64_C(0x3)));
3267}
3268
3269
3270/**
3271 * Raises an ILLEGAL_DEV_TABLE_ENTRY event.
3272 *
3273 * @param pDevIns The IOMMU instance data.
3274 * @param enmOp The IOMMU operation being performed.
3275 * @param pEvtIllegalDte The illegal device table entry event.
3276 * @param enmEvtType The illegal device table entry event type.
3277 *
3278 * @thread Any.
3279 */
3280static void iommuAmdIllegalDteEventRaise(PPDMDEVINS pDevIns, IOMMUOP enmOp, PCEVT_ILLEGAL_DTE_T pEvtIllegalDte,
3281 EVT_ILLEGAL_DTE_TYPE_T enmEvtType)
3282{
3283 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_ILLEGAL_DTE_T));
3284 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIllegalDte;
3285
3286 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3287 if (enmOp != IOMMUOP_CMD)
3288 iommuAmdSetPciTargetAbort(pDevIns);
3289
3290 LogFunc(("Raised ILLEGAL_DTE_EVENT. idDevice=%#x uIova=%#RX64 enmOp=%u enmEvtType=%u\n", pEvtIllegalDte->n.u16DevId,
3291 pEvtIllegalDte->n.u64Addr, enmOp, enmEvtType));
3292 NOREF(enmEvtType);
3293}
3294
3295
3296/**
3297 * Initializes an IO_PAGE_FAULT event.
3298 *
3299 * @param idDevice The device ID (bus, device, function).
3300 * @param idDomain The domain ID.
3301 * @param uIova The I/O virtual address being accessed.
3302 * @param fPresent Transaction to a page marked as present (including
3303 * DTE.V=1) or interrupt marked as remapped
3304 * (IRTE.RemapEn=1).
3305 * @param fRsvdNotZero Whether reserved bits are not zero. Pass @c false if
3306 * the I/O page fault was caused by invalid level
3307 * encoding.
3308 * @param fPermDenied Permission denied for the address being accessed.
3309 * @param enmOp The IOMMU operation being performed.
3310 * @param pEvtIoPageFault Where to store the initialized event.
3311 */
3312static void iommuAmdIoPageFaultEventInit(uint16_t idDevice, uint16_t idDomain, uint64_t uIova, bool fPresent, bool fRsvdNotZero,
3313 bool fPermDenied, IOMMUOP enmOp, PEVT_IO_PAGE_FAULT_T pEvtIoPageFault)
3314{
3315 Assert(!fPermDenied || fPresent);
3316 memset(pEvtIoPageFault, 0, sizeof(*pEvtIoPageFault));
3317 pEvtIoPageFault->n.u16DevId = idDevice;
3318 //pEvtIoPageFault->n.u4PasidHi = 0;
3319 pEvtIoPageFault->n.u16DomainOrPasidLo = idDomain;
3320 //pEvtIoPageFault->n.u1GuestOrNested = 0;
3321 //pEvtIoPageFault->n.u1NoExecute = 0;
3322 //pEvtIoPageFault->n.u1User = 0;
3323 pEvtIoPageFault->n.u1Interrupt = RT_BOOL(enmOp == IOMMUOP_INTR_REQ);
3324 pEvtIoPageFault->n.u1Present = fPresent;
3325 pEvtIoPageFault->n.u1ReadWrite = RT_BOOL(enmOp == IOMMUOP_MEM_WRITE);
3326 pEvtIoPageFault->n.u1PermDenied = fPermDenied;
3327 pEvtIoPageFault->n.u1RsvdNotZero = fRsvdNotZero;
3328 pEvtIoPageFault->n.u1Translation = RT_BOOL(enmOp == IOMMUOP_TRANSLATE_REQ);
3329 pEvtIoPageFault->n.u4EvtCode = IOMMU_EVT_IO_PAGE_FAULT;
3330 pEvtIoPageFault->n.u64Addr = uIova;
3331}
3332
3333
3334/**
3335 * Raises an IO_PAGE_FAULT event.
3336 *
3337 * @param pDevIns The IOMMU instance data.
3338 * @param fIoDevFlags The I/O device flags, see IOMMU_DTE_CACHE_F_XXX.
3339 * @param pIrte The interrupt remapping table entry, can be NULL.
3340 * @param enmOp The IOMMU operation being performed.
3341 * @param pEvtIoPageFault The I/O page fault event.
3342 * @param enmEvtType The I/O page fault event type.
3343 *
3344 * @thread Any.
3345 */
3346static void iommuAmdIoPageFaultEventRaise(PPDMDEVINS pDevIns, uint16_t fIoDevFlags, PCIRTE_T pIrte, IOMMUOP enmOp,
3347 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3348{
3349 AssertCompile(sizeof(EVT_GENERIC_T) == sizeof(EVT_IO_PAGE_FAULT_T));
3350 PCEVT_GENERIC_T pEvent = (PCEVT_GENERIC_T)pEvtIoPageFault;
3351 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3352 STAM_COUNTER_INC(&pThis->StatIopfs); NOREF(pThis);
3353
3354#ifdef IOMMU_WITH_DTE_CACHE
3355# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) iommuAmdDteCacheAddFlags((a_pDevIns), (a_DevId), \
3356 IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED)
3357#else
3358# define IOMMU_DTE_CACHE_SET_PF_RAISED(a_pDevIns, a_DevId) do { } while (0)
3359#endif
3360
3361 bool fSuppressEvtLogging = false;
3362 if ( enmOp == IOMMUOP_MEM_READ
3363 || enmOp == IOMMUOP_MEM_WRITE)
3364 {
3365 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_VALID
3366 | IOMMU_DTE_CACHE_F_SUPPRESS_IOPF | IOMMU_DTE_CACHE_F_IO_PAGE_FAULT_RAISED;
3367 uint16_t const fSuppressAllIopf = IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_SUPPRESS_ALL_IOPF;
3368 if ( (fIoDevFlags & fSuppressAllIopf) == fSuppressAllIopf
3369 || (fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3370 {
3371 fSuppressEvtLogging = true;
3372 }
3373 }
3374 else if (enmOp == IOMMUOP_INTR_REQ)
3375 {
3376 uint16_t const fSuppressIopf = IOMMU_DTE_CACHE_F_INTR_MAP_VALID | IOMMU_DTE_CACHE_F_IGNORE_UNMAPPED_INTR;
3377 if ((fIoDevFlags & fSuppressIopf) == fSuppressIopf)
3378 fSuppressEvtLogging = true;
3379 else if (pIrte) /** @todo Make this compulsary and assert if it isn't provided. */
3380 fSuppressEvtLogging = pIrte->n.u1SuppressIoPf;
3381 }
3382 /* else: Events are never suppressed for commands. */
3383
3384 switch (enmEvtType)
3385 {
3386 case kIoPageFaultType_PermDenied:
3387 {
3388 /* Cannot be triggered by a command. */
3389 Assert(enmOp != IOMMUOP_CMD);
3390 RT_FALL_THRU();
3391 }
3392 case kIoPageFaultType_DteRsvdPagingMode:
3393 case kIoPageFaultType_PteInvalidPageSize:
3394 case kIoPageFaultType_PteInvalidLvlEncoding:
3395 case kIoPageFaultType_SkippedLevelIovaNotZero:
3396 case kIoPageFaultType_PteRsvdNotZero:
3397 case kIoPageFaultType_PteValidNotSet:
3398 case kIoPageFaultType_DteTranslationDisabled:
3399 case kIoPageFaultType_PasidInvalidRange:
3400 {
3401 /*
3402 * For a translation request, the IOMMU doesn't signal an I/O page fault nor does it
3403 * create an event log entry. See AMD IOMMU spec. 2.1.3.2 "I/O Page Faults".
3404 */
3405 if (enmOp != IOMMUOP_TRANSLATE_REQ)
3406 {
3407 if (!fSuppressEvtLogging)
3408 {
3409 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3410 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3411 }
3412 if (enmOp != IOMMUOP_CMD)
3413 iommuAmdSetPciTargetAbort(pDevIns);
3414 }
3415 break;
3416 }
3417
3418 case kIoPageFaultType_UserSupervisor:
3419 {
3420 /* Access is blocked and only creates an event log entry. */
3421 if (!fSuppressEvtLogging)
3422 {
3423 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3424 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3425 }
3426 break;
3427 }
3428
3429 case kIoPageFaultType_IrteAddrInvalid:
3430 case kIoPageFaultType_IrteRsvdNotZero:
3431 case kIoPageFaultType_IrteRemapEn:
3432 case kIoPageFaultType_IrteRsvdIntType:
3433 case kIoPageFaultType_IntrReqAborted:
3434 case kIoPageFaultType_IntrWithPasid:
3435 {
3436 /* Only trigerred by interrupt requests. */
3437 Assert(enmOp == IOMMUOP_INTR_REQ);
3438 if (!fSuppressEvtLogging)
3439 {
3440 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3441 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3442 }
3443 iommuAmdSetPciTargetAbort(pDevIns);
3444 break;
3445 }
3446
3447 case kIoPageFaultType_SmiFilterMismatch:
3448 {
3449 /* Not supported and probably will never be, assert. */
3450 AssertMsgFailed(("kIoPageFaultType_SmiFilterMismatch - Upstream SMI requests not supported/implemented."));
3451 break;
3452 }
3453
3454 case kIoPageFaultType_DevId_Invalid:
3455 {
3456 /* Cannot be triggered by a command. */
3457 Assert(enmOp != IOMMUOP_CMD);
3458 Assert(enmOp != IOMMUOP_TRANSLATE_REQ); /** @todo IOMMU: We don't support translation requests yet. */
3459 if (!fSuppressEvtLogging)
3460 {
3461 iommuAmdEvtLogEntryWrite(pDevIns, pEvent);
3462 IOMMU_DTE_CACHE_SET_PF_RAISED(pDevIns, pEvtIoPageFault->n.u16DevId);
3463 }
3464 if ( enmOp == IOMMUOP_MEM_READ
3465 || enmOp == IOMMUOP_MEM_WRITE)
3466 iommuAmdSetPciTargetAbort(pDevIns);
3467 break;
3468 }
3469 }
3470
3471#undef IOMMU_DTE_CACHE_SET_PF_RAISED
3472}
3473
3474
3475/**
3476 * Raises an IO_PAGE_FAULT event given the DTE.
3477 *
3478 * @param pDevIns The IOMMU instance data.
3479 * @param pDte The device table entry.
3480 * @param pIrte The interrupt remapping table entry, can be NULL.
3481 * @param enmOp The IOMMU operation being performed.
3482 * @param pEvtIoPageFault The I/O page fault event.
3483 * @param enmEvtType The I/O page fault event type.
3484 *
3485 * @thread Any.
3486 */
3487static void iommuAmdIoPageFaultEventRaiseWithDte(PPDMDEVINS pDevIns, PCDTE_T pDte, PCIRTE_T pIrte, IOMMUOP enmOp,
3488 PCEVT_IO_PAGE_FAULT_T pEvtIoPageFault, EVT_IO_PAGE_FAULT_TYPE_T enmEvtType)
3489{
3490 Assert(pDte);
3491 uint16_t const fIoDevFlags = iommuAmdGetBasicDevFlags(pDte);
3492 return iommuAmdIoPageFaultEventRaise(pDevIns, fIoDevFlags, pIrte, enmOp, pEvtIoPageFault, enmEvtType);
3493}
3494
3495
3496/**
3497 * Reads a device table entry for the given the device ID.
3498 *
3499 * @returns VBox status code.
3500 * @param pDevIns The IOMMU device instance.
3501 * @param idDevice The device ID (bus, device, function).
3502 * @param enmOp The IOMMU operation being performed.
3503 * @param pDte Where to store the device table entry.
3504 *
3505 * @thread Any.
3506 */
3507static int iommuAmdDteRead(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PDTE_T pDte)
3508{
3509 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3510 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
3511
3512 IOMMU_LOCK(pDevIns, pThisCC);
3513
3514 /* Figure out which device table segment is being accessed. */
3515 uint8_t const idxSegsEn = pThis->Ctrl.n.u3DevTabSegEn;
3516 Assert(idxSegsEn < RT_ELEMENTS(g_auDevTabSegShifts));
3517
3518 uint8_t const idxSeg = (idDevice & g_auDevTabSegMasks[idxSegsEn]) >> g_auDevTabSegShifts[idxSegsEn];
3519 Assert(idxSeg < RT_ELEMENTS(pThis->aDevTabBaseAddrs));
3520 AssertCompile(RT_ELEMENTS(g_auDevTabSegShifts) == RT_ELEMENTS(g_auDevTabSegMasks));
3521
3522 RTGCPHYS const GCPhysDevTab = pThis->aDevTabBaseAddrs[idxSeg].n.u40Base << X86_PAGE_4K_SHIFT;
3523 uint32_t const offDte = (idDevice & ~g_auDevTabSegMasks[idxSegsEn]) * sizeof(DTE_T);
3524 RTGCPHYS const GCPhysDte = GCPhysDevTab + offDte;
3525
3526 /* Ensure the DTE falls completely within the device table segment. */
3527 uint32_t const cbDevTabSeg = (pThis->aDevTabBaseAddrs[idxSeg].n.u9Size + 1) << X86_PAGE_4K_SHIFT;
3528
3529 IOMMU_UNLOCK(pDevIns, pThisCC);
3530
3531 if (offDte + sizeof(DTE_T) <= cbDevTabSeg)
3532 {
3533 /* Read the device table entry from guest memory. */
3534 Assert(!(GCPhysDevTab & X86_PAGE_4K_OFFSET_MASK));
3535 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDte, pDte, sizeof(*pDte));
3536 if (RT_SUCCESS(rc))
3537 return rc;
3538
3539 /* Raise a device table hardware error. */
3540 LogFunc(("Failed to read device table entry at %#RGp. rc=%Rrc -> DevTabHwError\n", GCPhysDte, rc));
3541
3542 EVT_DEV_TAB_HW_ERROR_T EvtDevTabHwErr;
3543 iommuAmdDevTabHwErrorEventInit(idDevice, GCPhysDte, enmOp, &EvtDevTabHwErr);
3544 iommuAmdDevTabHwErrorEventRaise(pDevIns, enmOp, &EvtDevTabHwErr);
3545 return VERR_IOMMU_DTE_READ_FAILED;
3546 }
3547
3548 /* Raise an I/O page fault for out-of-bounds acccess. */
3549 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3550 iommuAmdIoPageFaultEventInit(idDevice, 0 /* idDomain */, 0 /* uIova */, false /* fPresent */, false /* fRsvdNotZero */,
3551 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3552 iommuAmdIoPageFaultEventRaise(pDevIns, 0 /* fIoDevFlags */, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3553 kIoPageFaultType_DevId_Invalid);
3554 return VERR_IOMMU_DTE_BAD_OFFSET;
3555}
3556
3557
3558/**
3559 * Performs pre-translation checks for the given device table entry.
3560 *
3561 * @returns VBox status code.
3562 * @retval VINF_SUCCESS if the DTE is valid and supports address translation.
3563 * @retval VINF_IOMMU_ADDR_TRANSLATION_DISABLED if the DTE is valid but address
3564 * translation is disabled.
3565 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED if an error occurred and any
3566 * corresponding event was raised.
3567 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the DTE denies the requested
3568 * permissions.
3569 *
3570 * @param pDevIns The IOMMU device instance.
3571 * @param uIova The I/O virtual address to translate.
3572 * @param idDevice The device ID (bus, device, function).
3573 * @param fPerm The I/O permissions for this access, see
3574 * IOMMU_IO_PERM_XXX.
3575 * @param pDte The device table entry.
3576 * @param enmOp The IOMMU operation being performed.
3577 *
3578 * @thread Any.
3579 */
3580static int iommuAmdPreTranslateChecks(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, uint8_t fPerm, PCDTE_T pDte,
3581 IOMMUOP enmOp)
3582{
3583 /*
3584 * Check if the translation is valid, otherwise raise an I/O page fault.
3585 */
3586 if (pDte->n.u1TranslationValid)
3587 { /* likely */ }
3588 else
3589 {
3590 /** @todo r=ramshankar: The AMD IOMMU spec. says page walk is terminated but
3591 * doesn't explicitly say whether an I/O page fault is raised. From other
3592 * places in the spec. it seems early page walk terminations (starting with
3593 * the DTE) return the state computed so far and raises an I/O page fault. So
3594 * returning an invalid translation rather than skipping translation. */
3595 LogFunc(("Translation valid bit not set -> IOPF\n"));
3596 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3597 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3598 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3599 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3600 kIoPageFaultType_DteTranslationDisabled);
3601 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3602 }
3603
3604 /*
3605 * Check permissions bits in the DTE.
3606 * Note: This MUST be checked prior to checking the root page table level below!
3607 */
3608 uint8_t const fDtePerm = (pDte->au64[0] >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3609 if ((fPerm & fDtePerm) == fPerm)
3610 { /* likely */ }
3611 else
3612 {
3613 LogFunc(("Permission denied by DTE (fPerm=%#x fDtePerm=%#x) -> IOPF\n", fPerm, fDtePerm));
3614 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3615 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3616 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3617 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3618 kIoPageFaultType_PermDenied);
3619 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3620 }
3621
3622 /*
3623 * If the root page table level is 0, translation is disabled and GPA=SPA and
3624 * the DTE.IR and DTE.IW bits control permissions (verified above).
3625 */
3626 uint8_t const uMaxLevel = pDte->n.u3Mode;
3627 if (uMaxLevel != 0)
3628 { /* likely */ }
3629 else
3630 {
3631 Assert((fPerm & fDtePerm) == fPerm); /* Verify we've checked permissions. */
3632 return VINF_IOMMU_ADDR_TRANSLATION_DISABLED;
3633 }
3634
3635 /*
3636 * If the root page table level exceeds the allowed host-address translation level,
3637 * page walk is terminated and translation fails.
3638 */
3639 if (uMaxLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3640 { /* likely */ }
3641 else
3642 {
3643 /** @todo r=ramshankar: I cannot make out from the AMD IOMMU spec. if I should be
3644 * raising an ILLEGAL_DEV_TABLE_ENTRY event or an IO_PAGE_FAULT event here.
3645 * I'm just going with I/O page fault. */
3646 LogFunc(("Invalid root page table level %#x (idDevice=%#x) -> IOPF\n", uMaxLevel, idDevice));
3647 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3648 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3649 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3650 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3651 kIoPageFaultType_PteInvalidLvlEncoding);
3652 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3653 }
3654
3655 /* The DTE allows translations for this device. */
3656 return VINF_SUCCESS;
3657}
3658
3659
3660/**
3661 * Walks the I/O page table to translate the I/O virtual address to a system
3662 * physical address.
3663 *
3664 * @returns VBox status code.
3665 * @param pDevIns The IOMMU device instance.
3666 * @param uIova The I/O virtual address to translate. Must be 4K aligned.
3667 * @param fPerm The I/O permissions for this access, see
3668 * IOMMU_IO_PERM_XXX.
3669 * @param idDevice The device ID (bus, device, function).
3670 * @param pDte The device table entry.
3671 * @param enmOp The IOMMU operation being performed.
3672 * @param pPageLookup Where to store the results of the I/O page lookup. This
3673 * is only updated when VINF_SUCCESS is returned.
3674 *
3675 * @thread Any.
3676 */
3677static int iommuAmdIoPageTableWalk(PPDMDEVINS pDevIns, uint64_t uIova, uint8_t fPerm, uint16_t idDevice, PCDTE_T pDte,
3678 IOMMUOP enmOp, PIOPAGELOOKUP pPageLookup)
3679{
3680 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3681 Assert(pDte->n.u1Valid);
3682 Assert(!(uIova & X86_PAGE_4K_OFFSET_MASK));
3683
3684 /* The virtual address bits indexing table. */
3685 static uint8_t const s_acIovaLevelShifts[] = { 0, 12, 21, 30, 39, 48, 57, 0 };
3686 AssertCompile(RT_ELEMENTS(s_acIovaLevelShifts) > IOMMU_MAX_HOST_PT_LEVEL);
3687
3688 /*
3689 * Traverse the I/O page table starting with the page directory in the DTE.
3690 *
3691 * The Valid (Present bit), Translation Valid and Mode (Next-Level bits) in
3692 * the DTE have been validated already, see iommuAmdPreTranslateChecks.
3693 */
3694 IOPTENTITY_T PtEntity;
3695 PtEntity.u64 = pDte->au64[0];
3696 for (;;)
3697 {
3698 uint8_t const uLevel = PtEntity.n.u3NextLevel;
3699
3700 /* Read the page table entity at the current level. */
3701 {
3702 Assert(uLevel > 0 && uLevel < RT_ELEMENTS(s_acIovaLevelShifts));
3703 Assert(uLevel <= IOMMU_MAX_HOST_PT_LEVEL);
3704 uint16_t const idxPte = (uIova >> s_acIovaLevelShifts[uLevel]) & UINT64_C(0x1ff);
3705 uint64_t const offPte = idxPte << 3;
3706 RTGCPHYS const GCPhysPtEntity = (PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK) + offPte;
3707 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysPtEntity, &PtEntity.u64, sizeof(PtEntity));
3708 if (RT_FAILURE(rc))
3709 {
3710 LogFunc(("Failed to read page table entry at %#RGp. rc=%Rrc -> PageTabHwError\n", GCPhysPtEntity, rc));
3711 EVT_PAGE_TAB_HW_ERR_T EvtPageTabHwErr;
3712 iommuAmdPageTabHwErrorEventInit(idDevice, pDte->n.u16DomainId, GCPhysPtEntity, enmOp, &EvtPageTabHwErr);
3713 iommuAmdPageTabHwErrorEventRaise(pDevIns, enmOp, &EvtPageTabHwErr);
3714 return VERR_IOMMU_IPE_2;
3715 }
3716 }
3717
3718 /* Check present bit. */
3719 if (PtEntity.n.u1Present)
3720 { /* likely */ }
3721 else
3722 {
3723 LogFunc(("Page table entry not present (idDevice=%#x) -> IOPF\n", idDevice));
3724 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3725 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, false /* fPresent */, false /* fRsvdNotZero */,
3726 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3727 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3728 kIoPageFaultType_PermDenied);
3729 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3730 }
3731
3732 /* Validate the encoding of the next level. */
3733 uint8_t const uNextLevel = PtEntity.n.u3NextLevel;
3734#if IOMMU_MAX_HOST_PT_LEVEL < 6
3735 if (uNextLevel <= IOMMU_MAX_HOST_PT_LEVEL)
3736 { /* likely */ }
3737 else
3738 {
3739 LogFunc(("Next-level/paging-mode field of the paging entity invalid. uNextLevel=%#x -> IOPF\n", uNextLevel));
3740 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3741 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, true /* fRsvdNotZero */,
3742 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3743 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3744 kIoPageFaultType_PteInvalidLvlEncoding);
3745 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3746 }
3747#endif
3748
3749 /* Check reserved bits. */
3750 uint64_t const fRsvdMask = uNextLevel == 0 || uNextLevel == 7 ? IOMMU_PTE_RSVD_MASK : IOMMU_PDE_RSVD_MASK;
3751 if (!(PtEntity.u64 & fRsvdMask))
3752 { /* likely */ }
3753 else
3754 {
3755 LogFunc(("Page table entity (%#RX64 level=%u) reserved bits set -> IOPF\n", PtEntity.u64, uNextLevel));
3756 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3757 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, true /* fRsvdNotZero */,
3758 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3759 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3760 kIoPageFaultType_PteRsvdNotZero);
3761 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3762 }
3763
3764 /* Check permission bits. */
3765 uint8_t const fPtePerm = (PtEntity.u64 >> IOMMU_IO_PERM_SHIFT) & IOMMU_IO_PERM_MASK;
3766 if ((fPerm & fPtePerm) == fPerm)
3767 { /* likely */ }
3768 else
3769 {
3770 LogFunc(("Page table entry access denied (idDevice=%#x fPerm=%#x fPtePerm=%#x) -> IOPF\n", idDevice, fPerm, fPtePerm));
3771 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3772 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3773 true /* fPermDenied */, enmOp, &EvtIoPageFault);
3774 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3775 kIoPageFaultType_PermDenied);
3776 return VERR_IOMMU_ADDR_ACCESS_DENIED;
3777 }
3778
3779 /* If the next level is 0 or 7, this is the final level PTE. */
3780 if (uNextLevel == 0)
3781 {
3782 /* The page size of the translation is the default size for the level. */
3783 uint8_t const cShift = s_acIovaLevelShifts[uLevel];
3784 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3785 pPageLookup->GCPhysSpa = GCPhysPte & X86_GET_PAGE_BASE_MASK(cShift);
3786 pPageLookup->cShift = cShift;
3787 pPageLookup->fPerm = fPtePerm;
3788 return VINF_SUCCESS;
3789 }
3790 if (uNextLevel == 7)
3791 {
3792 /* The default page size of the translation is overridden. */
3793 uint8_t cShift = X86_PAGE_4K_SHIFT;
3794 RTGCPHYS const GCPhysPte = PtEntity.u64 & IOMMU_PTENTITY_ADDR_MASK;
3795 while (GCPhysPte & RT_BIT_64(cShift++))
3796 ;
3797
3798 /* The page size must be larger than the default size and lower than the default size of the higher level. */
3799 if ( cShift > s_acIovaLevelShifts[uLevel]
3800 && cShift < s_acIovaLevelShifts[uLevel + 1])
3801 {
3802 pPageLookup->GCPhysSpa = GCPhysPte & X86_GET_PAGE_BASE_MASK(cShift);
3803 pPageLookup->cShift = cShift;
3804 pPageLookup->fPerm = fPtePerm;
3805 STAM_COUNTER_INC(&pThis->StatNonStdPageSize); NOREF(pThis);
3806 return VINF_SUCCESS;
3807 }
3808
3809 LogFunc(("Page size invalid cShift=%u -> IOPF\n", cShift));
3810 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3811 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3812 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3813 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3814 kIoPageFaultType_PteInvalidPageSize);
3815 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3816 }
3817
3818 /* Validate level transition. */
3819 if (uNextLevel < uLevel)
3820 { /* likely */ }
3821 else
3822 {
3823 LogFunc(("Next level (%#x) must be less than the current level (%#x) -> IOPF\n", uNextLevel, uLevel));
3824 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3825 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3826 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3827 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3828 kIoPageFaultType_PteInvalidLvlEncoding);
3829 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3830 }
3831
3832 /* Ensure IOVA bits of skipped levels (if any) are zero. */
3833 uint64_t const fIovaSkipMask = IOMMU_GET_MAX_VALID_IOVA(uLevel - 1) - IOMMU_GET_MAX_VALID_IOVA(uNextLevel);
3834 if (!(uIova & fIovaSkipMask))
3835 { /* likely */ }
3836 else
3837 {
3838 LogFunc(("IOVA of skipped levels are not zero. uIova=%#RX64 fSkipMask=%#RX64 -> IOPF\n", uIova, fIovaSkipMask));
3839 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
3840 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, uIova, true /* fPresent */, false /* fRsvdNotZero */,
3841 false /* fPermDenied */, enmOp, &EvtIoPageFault);
3842 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
3843 kIoPageFaultType_SkippedLevelIovaNotZero);
3844 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
3845 }
3846
3847 /* Traverse to the next level. */
3848 }
3849}
3850
3851
3852/**
3853 * Page lookup callback for finding an I/O page from guest memory.
3854 *
3855 * @returns VBox status code.
3856 * @retval VINF_SUCCESS when the page is found and has the right permissions.
3857 * @retval VERR_IOMMU_ADDR_TRANSLATION_FAILED when address translation fails.
3858 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
3859 * insufficient to what is requested.
3860 *
3861 * @param pDevIns The IOMMU instance data.
3862 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
3863 * 4K aligned).
3864 * @param fPerm The I/O permissions for this access, see
3865 * IOMMU_IO_PERM_XXX.
3866 * @param pAux The auxiliary information required during lookup.
3867 * @param pPageLookup Where to store the looked up I/O page.
3868 */
3869static DECLCALLBACK(int) iommuAmdDteLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
3870 PIOPAGELOOKUP pPageLookup)
3871{
3872 AssertPtr(pAux);
3873 AssertPtr(pPageLookup);
3874 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
3875
3876 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3877 STAM_PROFILE_ADV_START(&pThis->StatProfDteLookup, a);
3878 int rc = iommuAmdIoPageTableWalk(pDevIns, uIovaPage, fPerm, pAux->idDevice, pAux->pDte, pAux->enmOp, pPageLookup);
3879 STAM_PROFILE_ADV_STOP(&pThis->StatProfDteLookup, a); NOREF(pThis);
3880 return rc;
3881}
3882
3883
3884/**
3885 * Looks up a range of I/O virtual addresses.
3886 *
3887 * @returns VBox status code.
3888 * @param pDevIns The IOMMU instance data.
3889 * @param pfnIoPageLookup The lookup function to use.
3890 * @param pAddrIn The I/O address range to lookup.
3891 * @param pAux The auxiliary information required by the lookup
3892 * function.
3893 * @param pAddrOut Where to store the translated I/O address range.
3894 * @param pcbPages Where to store the size of the access (round up to
3895 * the page size). Optional, can be NULL.
3896 */
3897static int iommuAmdLookupIoAddrRange(PPDMDEVINS pDevIns, PFNIOPAGELOOKUP pfnIoPageLookup, PCIOADDRRANGE pAddrIn,
3898 PCIOMMUOPAUX pAux, PIOADDRRANGE pAddrOut, size_t *pcbPages)
3899{
3900 AssertPtr(pfnIoPageLookup);
3901 AssertPtr(pAddrIn);
3902 AssertPtr(pAddrOut);
3903
3904 int rc;
3905 size_t const cbIova = pAddrIn->cb;
3906 uint8_t const fPerm = pAddrIn->fPerm;
3907 uint64_t const uIova = pAddrIn->uAddr;
3908 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3909 size_t cbRemaining = cbIova;
3910 uint64_t uIovaPage = pAddrIn->uAddr & X86_PAGE_4K_BASE_MASK;
3911 uint64_t offIova = pAddrIn->uAddr & X86_PAGE_4K_OFFSET_MASK;
3912 uint64_t cbPages = 0;
3913
3914 IOPAGELOOKUP PageLookupPrev;
3915 RT_ZERO(PageLookupPrev);
3916 for (;;)
3917 {
3918 IOPAGELOOKUP PageLookup;
3919 rc = pfnIoPageLookup(pDevIns, uIovaPage, fPerm, pAux, &PageLookup);
3920 if (RT_SUCCESS(rc))
3921 {
3922 Assert(PageLookup.cShift >= X86_PAGE_4K_SHIFT);
3923
3924 /* Store the translated address before continuing to access more pages. */
3925 if (cbRemaining == cbIova)
3926 {
3927 uint64_t const offMask = X86_GET_PAGE_OFFSET_MASK(PageLookup.cShift);
3928 uint64_t const offSpa = uIova & offMask;
3929 AssertMsg(!(PageLookup.GCPhysSpa & offMask), ("GCPhysSpa=%#RX64 offMask=%#RX64\n",
3930 PageLookup.GCPhysSpa, offMask));
3931 GCPhysSpa = PageLookup.GCPhysSpa | offSpa;
3932 }
3933 /* Check if addresses translated so far result in a physically contiguous region. */
3934 else if (!iommuAmdLookupIsAccessContig(&PageLookupPrev, &PageLookup))
3935 {
3936 rc = VERR_OUT_OF_RANGE;
3937 break;
3938 }
3939
3940 /* Store the page lookup result from the first/previous page. */
3941 PageLookupPrev = PageLookup;
3942
3943 /* Update size of all pages read thus far. */
3944 uint64_t const cbPage = RT_BIT_64(PageLookup.cShift);
3945 cbPages += cbPage;
3946
3947 /* Check if we need to access more pages. */
3948 if (cbRemaining > cbPage - offIova)
3949 {
3950 cbRemaining -= (cbPage - offIova); /* Calculate how much more we need to access. */
3951 uIovaPage += cbPage; /* Update address of the next access. */
3952 offIova = 0; /* After first page, remaining pages are accessed from offset 0. */
3953 }
3954 else
3955 {
3956 /* Caller (PDM) doesn't expect more data accessed than what was requested. */
3957 cbRemaining = 0;
3958 break;
3959 }
3960 }
3961 else
3962 break;
3963 }
3964
3965 pAddrOut->uAddr = GCPhysSpa; /* Update the translated address. */
3966 pAddrOut->cb = cbIova - cbRemaining; /* Update the size of the contiguous memory region. */
3967 pAddrOut->fPerm = PageLookupPrev.fPerm; /* Update the allowed permissions for this access. */
3968 if (pcbPages)
3969 *pcbPages = cbPages; /* Update the size (in bytes) of the pages accessed. */
3970 return rc;
3971}
3972
3973
3974/**
3975 * Looks up an I/O virtual address from the device table.
3976 *
3977 * @returns VBox status code.
3978 * @param pDevIns The IOMMU instance data.
3979 * @param idDevice The device ID (bus, device, function).
3980 * @param uIova The I/O virtual address to lookup.
3981 * @param cbIova The size of the access.
3982 * @param fPerm The I/O permissions for this access, see
3983 * IOMMU_IO_PERM_XXX.
3984 * @param enmOp The IOMMU operation being performed.
3985 * @param pGCPhysSpa Where to store the translated system physical address.
3986 * @param pcbContiguous Where to store the number of contiguous bytes translated
3987 * and permission-checked.
3988 *
3989 * @thread Any.
3990 */
3991static int iommuAmdDteLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm, IOMMUOP enmOp,
3992 PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
3993{
3994 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
3995 RTGCPHYS GCPhysSpa = NIL_RTGCPHYS;
3996 size_t cbContiguous = 0;
3997
3998 /* Read the device table entry from memory. */
3999 DTE_T Dte;
4000 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4001 if (RT_SUCCESS(rc))
4002 {
4003 if (Dte.n.u1Valid)
4004 {
4005 /* Validate bits 127:0 of the device table entry when DTE.V is 1. */
4006 uint64_t const fRsvd0 = Dte.au64[0] & ~(IOMMU_DTE_QWORD_0_VALID_MASK & ~IOMMU_DTE_QWORD_0_FEAT_MASK);
4007 uint64_t const fRsvd1 = Dte.au64[1] & ~(IOMMU_DTE_QWORD_1_VALID_MASK & ~IOMMU_DTE_QWORD_1_FEAT_MASK);
4008 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4009 {
4010 /*
4011 * Check if the DTE is configured for translating addresses.
4012 * Note: Addresses cannot be subject to exclusion as we do -not- support remote IOTLBs,
4013 * so there's no need to check the address exclusion base/limit here.
4014 */
4015 rc = iommuAmdPreTranslateChecks(pDevIns, idDevice, uIova, fPerm, &Dte, enmOp);
4016 if (rc == VINF_SUCCESS)
4017 {
4018 IOADDRRANGE AddrIn;
4019 AddrIn.uAddr = uIova;
4020 AddrIn.cb = cbIova;
4021 AddrIn.fPerm = fPerm;
4022
4023 IOMMUOPAUX Aux;
4024 Aux.enmOp = enmOp;
4025 Aux.pDte = &Dte;
4026 Aux.idDevice = idDevice;
4027 Aux.idDomain = Dte.n.u16DomainId;
4028
4029 IOADDRRANGE AddrOut;
4030
4031 /* Lookup the address from the DTE and I/O page tables.*/
4032 size_t cbPages = 0;
4033 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdDteLookupPage, &AddrIn, &Aux, &AddrOut, &cbPages);
4034 GCPhysSpa = AddrOut.uAddr;
4035 cbContiguous = AddrOut.cb;
4036
4037 /* If we stopped since translation resulted in non-contiguous physical addresses,
4038 what we translated so far is still valid. */
4039 if (rc == VERR_OUT_OF_RANGE)
4040 {
4041 Assert(cbContiguous > 0 && cbContiguous < cbIova);
4042 rc = VINF_SUCCESS;
4043 STAM_COUNTER_INC(&pThis->StatAccessDteNonContig); NOREF(pThis);
4044 }
4045
4046 if (rc == VERR_IOMMU_ADDR_ACCESS_DENIED)
4047 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4048
4049#ifdef IOMMU_WITH_IOTLBE_CACHE
4050 if (RT_SUCCESS(rc))
4051 {
4052 /* Update that addresses requires translation (cumulative permissions of DTE and I/O page tables). */
4053 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_ADDR_TRANSLATE);
4054 /* Update IOTLB for the contiguous range of I/O virtual addresses. */
4055 iommuAmdIotlbAddRange(pDevIns, Dte.n.u16DomainId, uIova & X86_PAGE_4K_BASE_MASK, cbPages,
4056 GCPhysSpa & X86_PAGE_4K_BASE_MASK, AddrOut.fPerm);
4057 }
4058#endif
4059 }
4060 else if (rc == VINF_IOMMU_ADDR_TRANSLATION_DISABLED)
4061 {
4062 /*
4063 * Translation is disabled for this device (root paging mode is 0).
4064 * GPA=SPA, but the permission bits are important and controls accesses.
4065 */
4066 GCPhysSpa = uIova;
4067 cbContiguous = cbIova;
4068 rc = VINF_SUCCESS;
4069
4070#ifdef IOMMU_WITH_IOTLBE_CACHE
4071 /* Update that addresses permissions of DTE apply (but omit address translation). */
4072 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, IOMMU_DTE_CACHE_F_IO_PERM);
4073#endif
4074 }
4075 else
4076 {
4077 /* Address translation failed or access is denied. */
4078 Assert(rc == VERR_IOMMU_ADDR_ACCESS_DENIED || rc == VERR_IOMMU_ADDR_TRANSLATION_FAILED);
4079 GCPhysSpa = NIL_RTGCPHYS;
4080 cbContiguous = 0;
4081 STAM_COUNTER_INC(&pThis->StatAccessDtePermDenied);
4082 }
4083 }
4084 else
4085 {
4086 /* Invalid reserved bits in the DTE, raise an error event. */
4087 LogFunc(("Invalid DTE reserved bits (u64[0]=%#RX64 u64[1]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4088 EVT_ILLEGAL_DTE_T Event;
4089 iommuAmdIllegalDteEventInit(idDevice, uIova, true /* fRsvdNotZero */, enmOp, &Event);
4090 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4091 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4092 }
4093 }
4094 else
4095 {
4096 /*
4097 * The DTE is not valid, forward addresses untranslated.
4098 * See AMD IOMMU spec. "Table 5: Feature Enablement for Address Translation".
4099 */
4100 GCPhysSpa = uIova;
4101 cbContiguous = cbIova;
4102
4103#ifdef IOMMU_WITH_IOTLBE_CACHE
4104 /* Update that addresses don't require translation (nor permission checks) but a DTE is present. */
4105 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4106#endif
4107 }
4108 }
4109 else
4110 {
4111 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4112 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4113 }
4114
4115 *pGCPhysSpa = GCPhysSpa;
4116 *pcbContiguous = cbContiguous;
4117 AssertMsg(rc != VINF_SUCCESS || cbContiguous > 0, ("cbContiguous=%zu\n", cbContiguous));
4118 return rc;
4119}
4120
4121
4122#ifdef IOMMU_WITH_IOTLBE_CACHE
4123/**
4124 * I/O page lookup callback for finding an I/O page from the IOTLB.
4125 *
4126 * @returns VBox status code.
4127 * @retval VINF_SUCCESS when the page is found and has the right permissions.
4128 * @retval VERR_NOT_FOUND when the page is not found.
4129 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED when the page is found but permissions are
4130 * insufficient to what is requested.
4131 *
4132 * @param pDevIns The IOMMU instance data.
4133 * @param uIovaPage The I/O virtual address to lookup in the cache (must be
4134 * 4K aligned).
4135 * @param fPerm The I/O permissions for this access, see
4136 * IOMMU_IO_PERM_XXX.
4137 * @param pAux The auxiliary information required during lookup.
4138 * @param pPageLookup Where to store the looked up I/O page.
4139 */
4140static DECLCALLBACK(int) iommuAmdCacheLookupPage(PPDMDEVINS pDevIns, uint64_t uIovaPage, uint8_t fPerm, PCIOMMUOPAUX pAux,
4141 PIOPAGELOOKUP pPageLookup)
4142{
4143 Assert(pAux);
4144 Assert(pPageLookup);
4145 Assert(!(uIovaPage & X86_PAGE_4K_OFFSET_MASK));
4146
4147 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4148 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4149
4150 STAM_PROFILE_ADV_START(&pThis->StatProfIotlbeLookup, a);
4151 PCIOTLBE pIotlbe = iommuAmdIotlbLookup(pThis, pThisR3, pAux->idDomain, uIovaPage);
4152 STAM_PROFILE_ADV_STOP(&pThis->StatProfIotlbeLookup, a);
4153 if (pIotlbe)
4154 {
4155 *pPageLookup = pIotlbe->PageLookup;
4156 if ((pPageLookup->fPerm & fPerm) == fPerm)
4157 {
4158 STAM_COUNTER_INC(&pThis->StatAccessCacheHit);
4159 return VINF_SUCCESS;
4160 }
4161 return VERR_IOMMU_ADDR_ACCESS_DENIED;
4162 }
4163 return VERR_NOT_FOUND;
4164}
4165
4166
4167/**
4168 * Lookups a memory access from the IOTLB cache.
4169 *
4170 * @returns VBox status code.
4171 * @retval VINF_SUCCESS if the access was cached and permissions are verified.
4172 * @retval VERR_OUT_OF_RANGE if the access resulted in a non-contiguous physical
4173 * address region.
4174 * @retval VERR_NOT_FOUND if the access was not cached.
4175 * @retval VERR_IOMMU_ADDR_ACCESS_DENIED if the access was cached but permissions
4176 * are insufficient.
4177 *
4178 * @param pDevIns The IOMMU instance data.
4179 * @param idDevice The device ID (bus, device, function).
4180 * @param uIova The I/O virtual address to lookup.
4181 * @param cbIova The size of the access.
4182 * @param fPerm The I/O permissions for this access, see
4183 * IOMMU_IO_PERM_XXX.
4184 * @param enmOp The IOMMU operation being performed.
4185 * @param pGCPhysSpa Where to store the translated system physical address.
4186 * @param pcbContiguous Where to store the number of contiguous bytes translated
4187 * and permission-checked.
4188 */
4189static int iommuAmdIotlbCacheLookup(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova, uint8_t fPerm,
4190 IOMMUOP enmOp, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4191{
4192 int rc;
4193 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4194
4195#define IOMMU_IOTLB_LOOKUP_FAILED(a_rc) \
4196 do { \
4197 *pGCPhysSpa = NIL_RTGCPHYS; \
4198 *pcbContiguous = 0; \
4199 rc = (a_rc); \
4200 } while (0)
4201
4202 /*
4203 * We hold the cache lock across both the DTE and the IOTLB lookups (if any) because
4204 * we don't want the DTE cache to be invalidate while we perform IOTBL lookups.
4205 */
4206 IOMMU_CACHE_LOCK(pDevIns, pThis);
4207
4208 /* Lookup the DTE cache entry. */
4209 uint16_t const idxDteCache = iommuAmdDteCacheEntryLookup(pThis, idDevice);
4210 if (idxDteCache < RT_ELEMENTS(pThis->aDteCache))
4211 {
4212 PCDTECACHE pDteCache = &pThis->aDteCache[idxDteCache];
4213 if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4214 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_ADDR_TRANSLATE))
4215 {
4216 /* Lookup IOTLB entries. */
4217 IOADDRRANGE AddrIn;
4218 AddrIn.uAddr = uIova;
4219 AddrIn.cb = cbIova;
4220 AddrIn.fPerm = fPerm;
4221
4222 IOMMUOPAUX Aux;
4223 Aux.enmOp = enmOp;
4224 Aux.pDte = NULL;
4225 Aux.idDevice = idDevice;
4226 Aux.idDomain = pDteCache->idDomain;
4227
4228 IOADDRRANGE AddrOut;
4229 rc = iommuAmdLookupIoAddrRange(pDevIns, iommuAmdCacheLookupPage, &AddrIn, &Aux, &AddrOut, NULL /* pcbPages */);
4230 Assert(AddrOut.cb <= cbIova);
4231 *pGCPhysSpa = AddrOut.uAddr;
4232 *pcbContiguous = AddrOut.cb;
4233 }
4234 else if ((pDteCache->fFlags & (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4235 == (IOMMU_DTE_CACHE_F_PRESENT | IOMMU_DTE_CACHE_F_VALID | IOMMU_DTE_CACHE_F_IO_PERM))
4236 {
4237 /* Address translation is disabled, but DTE permissions apply. */
4238 Assert(!(pDteCache->fFlags & IOMMU_DTE_CACHE_F_ADDR_TRANSLATE));
4239 uint8_t const fDtePerm = (pDteCache->fFlags >> IOMMU_DTE_CACHE_F_IO_PERM_SHIFT) & IOMMU_DTE_CACHE_F_IO_PERM_MASK;
4240 if ((fDtePerm & fPerm) == fPerm)
4241 {
4242 *pGCPhysSpa = uIova;
4243 *pcbContiguous = cbIova;
4244 rc = VINF_SUCCESS;
4245 }
4246 else
4247 IOMMU_IOTLB_LOOKUP_FAILED(VERR_IOMMU_ADDR_ACCESS_DENIED);
4248 }
4249 else if (pDteCache->fFlags & IOMMU_DTE_CACHE_F_PRESENT)
4250 {
4251 /* Forward addresses untranslated, without checking permissions. */
4252 *pGCPhysSpa = uIova;
4253 *pcbContiguous = cbIova;
4254 rc = VINF_SUCCESS;
4255 }
4256 else
4257 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4258 }
4259 else
4260 IOMMU_IOTLB_LOOKUP_FAILED(VERR_NOT_FOUND);
4261
4262 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
4263
4264 return rc;
4265
4266#undef IOMMU_IOTLB_LOOKUP_FAILED
4267}
4268#endif /* IOMMU_WITH_IOTLBE_CACHE */
4269
4270
4271/**
4272 * Gets the I/O permission and IOMMU operation type for the given access flags.
4273 *
4274 * @param pThis The shared IOMMU device state.
4275 * @param fFlags The PDM IOMMU flags, PDMIOMMU_MEM_F_XXX.
4276 * @param penmOp Where to store the IOMMU operation.
4277 * @param pfPerm Where to store the IOMMU I/O permission.
4278 * @param fBulk Whether this is a bulk read or write.
4279 */
4280DECLINLINE(void) iommuAmdMemAccessGetPermAndOp(PIOMMU pThis, uint32_t fFlags, PIOMMUOP penmOp, uint8_t *pfPerm, bool fBulk)
4281{
4282 if (fFlags & PDMIOMMU_MEM_F_WRITE)
4283 {
4284 *penmOp = IOMMUOP_MEM_WRITE;
4285 *pfPerm = IOMMU_IO_PERM_WRITE;
4286#ifdef VBOX_WITH_STATISTICS
4287 if (!fBulk)
4288 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
4289 else
4290 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
4291#else
4292 RT_NOREF2(pThis, fBulk);
4293#endif
4294 }
4295 else
4296 {
4297 Assert(fFlags & PDMIOMMU_MEM_F_READ);
4298 *penmOp = IOMMUOP_MEM_READ;
4299 *pfPerm = IOMMU_IO_PERM_READ;
4300#ifdef VBOX_WITH_STATISTICS
4301 if (!fBulk)
4302 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
4303 else
4304 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
4305#else
4306 RT_NOREF2(pThis, fBulk);
4307#endif
4308 }
4309}
4310
4311
4312/**
4313 * Memory access transaction from a device.
4314 *
4315 * @returns VBox status code.
4316 * @param pDevIns The IOMMU device instance.
4317 * @param idDevice The device ID (bus, device, function).
4318 * @param uIova The I/O virtual address being accessed.
4319 * @param cbIova The size of the access.
4320 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4321 * @param pGCPhysSpa Where to store the translated system physical address.
4322 * @param pcbContiguous Where to store the number of contiguous bytes translated
4323 * and permission-checked.
4324 *
4325 * @thread Any.
4326 */
4327static DECLCALLBACK(int) iommuAmdMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
4328 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
4329{
4330 /* Validate. */
4331 AssertPtr(pDevIns);
4332 AssertPtr(pGCPhysSpa);
4333 Assert(cbIova > 0);
4334 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4335
4336 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4337 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4338 if (Ctrl.n.u1IommuEn)
4339 {
4340 IOMMUOP enmOp;
4341 uint8_t fPerm;
4342 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, false /* fBulk */);
4343 LogFlowFunc(("%s: idDevice=%#x uIova=%#RX64 cb=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, uIova, cbIova));
4344
4345 int rc;
4346#ifdef IOMMU_WITH_IOTLBE_CACHE
4347 /* Lookup the IOVA from the cache. */
4348 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4349 if (rc == VINF_SUCCESS)
4350 {
4351 /* All pages in the access were found in the cache with sufficient permissions. */
4352 Assert(*pcbContiguous == cbIova);
4353 Assert(*pGCPhysSpa != NIL_RTGCPHYS);
4354 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4355 return VINF_SUCCESS;
4356 }
4357 if (rc != VERR_OUT_OF_RANGE)
4358 { /* likely */ }
4359 else
4360 {
4361 /* Access stopped since translations resulted in non-contiguous memory, let caller resume access. */
4362 Assert(*pcbContiguous > 0 && *pcbContiguous < cbIova);
4363 STAM_COUNTER_INC(&pThis->StatAccessCacheNonContig);
4364 return VINF_SUCCESS;
4365 }
4366
4367 /*
4368 * Access incomplete as not all pages were in the cache.
4369 * Or permissions were denied for the access (which typically doesn't happen)
4370 * so go through the slower path and raise the required event.
4371 */
4372 AssertMsg(*pcbContiguous < cbIova, ("Invalid size: cbContiguous=%zu cbIova=%zu\n", *pcbContiguous, cbIova));
4373 uIova += *pcbContiguous;
4374 cbIova -= *pcbContiguous;
4375 /* We currently are including any permission denied pages as cache misses too.*/
4376 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4377#endif
4378
4379 /* Lookup the IOVA from the device table. */
4380 rc = iommuAmdDteLookup(pDevIns, idDevice, uIova, cbIova, fPerm, enmOp, pGCPhysSpa, pcbContiguous);
4381 if (RT_SUCCESS(rc))
4382 { /* likely */ }
4383 else
4384 {
4385 Assert(rc != VERR_OUT_OF_RANGE);
4386 LogFunc(("DTE lookup failed! idDevice=%#x uIova=%#RX64 fPerm=%u cbIova=%zu rc=%#Rrc\n", idDevice, uIova, fPerm,
4387 cbIova, rc));
4388 }
4389
4390 return rc;
4391 }
4392
4393 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4394 *pGCPhysSpa = uIova;
4395 *pcbContiguous = cbIova;
4396 return VINF_SUCCESS;
4397}
4398
4399
4400/**
4401 * Memory access bulk (one or more 4K pages) request from a device.
4402 *
4403 * @returns VBox status code.
4404 * @param pDevIns The IOMMU device instance.
4405 * @param idDevice The device ID (bus, device, function).
4406 * @param cIovas The number of addresses being accessed.
4407 * @param pauIovas The I/O virtual addresses for each page being accessed.
4408 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
4409 * @param paGCPhysSpa Where to store the translated physical addresses.
4410 *
4411 * @thread Any.
4412 */
4413static DECLCALLBACK(int) iommuAmdMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
4414 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
4415{
4416 /* Validate. */
4417 AssertPtr(pDevIns);
4418 Assert(cIovas > 0);
4419 AssertPtr(pauIovas);
4420 AssertPtr(paGCPhysSpa);
4421 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
4422
4423 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4424 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4425 if (Ctrl.n.u1IommuEn)
4426 {
4427 IOMMUOP enmOp;
4428 uint8_t fPerm;
4429 iommuAmdMemAccessGetPermAndOp(pThis, fFlags, &enmOp, &fPerm, true /* fBulk */);
4430 LogFlowFunc(("%s: idDevice=%#x cIovas=%zu\n", iommuAmdMemAccessGetPermName(fPerm), idDevice, cIovas));
4431
4432 for (size_t i = 0; i < cIovas; i++)
4433 {
4434 int rc;
4435 size_t cbContig;
4436
4437#ifdef IOMMU_WITH_IOTLBE_CACHE
4438 /* Lookup the IOVA from the IOTLB cache. */
4439 rc = iommuAmdIotlbCacheLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i],
4440 &cbContig);
4441 if (rc == VINF_SUCCESS)
4442 {
4443 Assert(cbContig == X86_PAGE_SIZE);
4444 Assert(paGCPhysSpa[i] != NIL_RTGCPHYS);
4445 STAM_COUNTER_INC(&pThis->StatAccessCacheHitFull);
4446 continue;
4447 }
4448 Assert(rc == VERR_NOT_FOUND || rc == VERR_IOMMU_ADDR_ACCESS_DENIED);
4449 STAM_COUNTER_INC(&pThis->StatAccessCacheMiss);
4450#endif
4451
4452 /* Lookup the IOVA from the device table. */
4453 rc = iommuAmdDteLookup(pDevIns, idDevice, pauIovas[i], X86_PAGE_SIZE, fPerm, enmOp, &paGCPhysSpa[i], &cbContig);
4454 if (RT_SUCCESS(rc))
4455 { /* likely */ }
4456 else
4457 {
4458 LogFunc(("Failed! idDevice=%#x uIova=%#RX64 fPerm=%u rc=%Rrc\n", idDevice, pauIovas[i], fPerm, rc));
4459 return rc;
4460 }
4461 Assert(cbContig == X86_PAGE_SIZE);
4462 }
4463 }
4464 else
4465 {
4466 /* Addresses are forwarded without translation when the IOMMU is disabled. */
4467 for (size_t i = 0; i < cIovas; i++)
4468 paGCPhysSpa[i] = pauIovas[i];
4469 }
4470
4471 return VINF_SUCCESS;
4472}
4473
4474
4475/**
4476 * Reads an interrupt remapping table entry from guest memory given its DTE.
4477 *
4478 * @returns VBox status code.
4479 * @param pDevIns The IOMMU device instance.
4480 * @param idDevice The device ID (bus, device, function).
4481 * @param pDte The device table entry.
4482 * @param GCPhysIn The source MSI address (used for reporting errors).
4483 * @param uDataIn The source MSI data.
4484 * @param enmOp The IOMMU operation being performed.
4485 * @param pIrte Where to store the interrupt remapping table entry.
4486 *
4487 * @thread Any.
4488 */
4489static int iommuAmdIrteRead(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, RTGCPHYS GCPhysIn, uint32_t uDataIn,
4490 IOMMUOP enmOp, PIRTE_T pIrte)
4491{
4492 /* Ensure the IRTE length is valid. */
4493 Assert(pDte->n.u4IntrTableLength < IOMMU_DTE_INTR_TAB_LEN_MAX);
4494
4495 RTGCPHYS const GCPhysIntrTable = pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK;
4496 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
4497 uint16_t const offIrte = IOMMU_GET_IRTE_OFF(uDataIn);
4498 RTGCPHYS const GCPhysIrte = GCPhysIntrTable + offIrte;
4499
4500 /* Ensure the IRTE falls completely within the interrupt table. */
4501 if (offIrte + sizeof(IRTE_T) <= cbIntrTable)
4502 { /* likely */ }
4503 else
4504 {
4505 LogFunc(("IRTE exceeds table length (GCPhysIntrTable=%#RGp cbIntrTable=%u offIrte=%#x uDataIn=%#x) -> IOPF\n",
4506 GCPhysIntrTable, cbIntrTable, offIrte, uDataIn));
4507
4508 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4509 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, GCPhysIn, false /* fPresent */, false /* fRsvdNotZero */,
4510 false /* fPermDenied */, enmOp, &EvtIoPageFault);
4511 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, NULL /* pIrte */, enmOp, &EvtIoPageFault,
4512 kIoPageFaultType_IrteAddrInvalid);
4513 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4514 }
4515
4516 /* Read the IRTE from memory. */
4517 Assert(!(GCPhysIrte & 3));
4518 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysIrte, pIrte, sizeof(*pIrte));
4519 if (RT_SUCCESS(rc))
4520 return VINF_SUCCESS;
4521
4522 /** @todo The IOMMU spec. does not tell what kind of error is reported in this
4523 * situation. Is it an I/O page fault or a device table hardware error?
4524 * There's no interrupt table hardware error event, but it's unclear what
4525 * we should do here. */
4526 LogFunc(("Failed to read interrupt table entry at %#RGp. rc=%Rrc -> ???\n", GCPhysIrte, rc));
4527 return VERR_IOMMU_IPE_4;
4528}
4529
4530
4531/**
4532 * Remaps the interrupt using the interrupt remapping table.
4533 *
4534 * @returns VBox status code.
4535 * @param pDevIns The IOMMU instance data.
4536 * @param idDevice The device ID (bus, device, function).
4537 * @param pDte The device table entry.
4538 * @param enmOp The IOMMU operation being performed.
4539 * @param pMsiIn The source MSI.
4540 * @param pMsiOut Where to store the remapped MSI.
4541 *
4542 * @thread Any.
4543 */
4544static int iommuAmdIntrRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCDTE_T pDte, IOMMUOP enmOp, PCMSIMSG pMsiIn,
4545 PMSIMSG pMsiOut)
4546{
4547 Assert(pDte->n.u2IntrCtrl == IOMMU_INTR_CTRL_REMAP);
4548
4549 IRTE_T Irte;
4550 uint32_t const uMsiInData = pMsiIn->Data.u32;
4551 int rc = iommuAmdIrteRead(pDevIns, idDevice, pDte, pMsiIn->Addr.u64, uMsiInData, enmOp, &Irte);
4552 if (RT_SUCCESS(rc))
4553 {
4554 if (Irte.n.u1RemapEnable)
4555 {
4556 if (!Irte.n.u1GuestMode)
4557 {
4558 if (Irte.n.u3IntrType <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO)
4559 {
4560 iommuAmdIrteRemapMsi(pMsiIn, pMsiOut, &Irte);
4561#ifdef IOMMU_WITH_IRTE_CACHE
4562 iommuAmdIrteCacheAdd(pDevIns, idDevice, IOMMU_GET_IRTE_OFF(uMsiInData), &Irte);
4563#endif
4564 return VINF_SUCCESS;
4565 }
4566
4567 LogFunc(("Interrupt type (%#x) invalid -> IOPF\n", Irte.n.u3IntrType));
4568 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4569 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4570 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4571 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault,
4572 kIoPageFaultType_IrteRsvdIntType);
4573 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4574 }
4575
4576 LogFunc(("Guest mode not supported -> IOPF\n"));
4577 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4578 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4579 true /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4580 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRsvdNotZero);
4581 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4582 }
4583
4584 LogFunc(("Remapping disabled -> IOPF\n"));
4585 EVT_IO_PAGE_FAULT_T EvtIoPageFault;
4586 iommuAmdIoPageFaultEventInit(idDevice, pDte->n.u16DomainId, pMsiIn->Addr.u64, Irte.n.u1RemapEnable,
4587 false /* fRsvdNotZero */, false /* fPermDenied */, enmOp, &EvtIoPageFault);
4588 iommuAmdIoPageFaultEventRaiseWithDte(pDevIns, pDte, &Irte, enmOp, &EvtIoPageFault, kIoPageFaultType_IrteRemapEn);
4589 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
4590 }
4591
4592 return rc;
4593}
4594
4595
4596/**
4597 * Looks up an MSI interrupt from the interrupt remapping table.
4598 *
4599 * @returns VBox status code.
4600 * @param pDevIns The IOMMU instance data.
4601 * @param idDevice The device ID (bus, device, function).
4602 * @param enmOp The IOMMU operation being performed.
4603 * @param pMsiIn The source MSI.
4604 * @param pMsiOut Where to store the remapped MSI.
4605 *
4606 * @thread Any.
4607 */
4608static int iommuAmdIntrTableLookup(PPDMDEVINS pDevIns, uint16_t idDevice, IOMMUOP enmOp, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4609{
4610 LogFlowFunc(("idDevice=%#x (%#x:%#x:%#x) enmOp=%u\n", idDevice, ((idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK),
4611 ((idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK), (idDevice & VBOX_PCI_DEVFN_FUN_MASK),
4612 enmOp));
4613
4614 /* Read the device table entry from memory. */
4615 DTE_T Dte;
4616 int rc = iommuAmdDteRead(pDevIns, idDevice, enmOp, &Dte);
4617 if (RT_SUCCESS(rc))
4618 {
4619#ifdef IOMMU_WITH_IRTE_CACHE
4620 iommuAmdDteCacheAdd(pDevIns, idDevice, &Dte, 0 /* fFlags */);
4621#endif
4622 /* If the DTE is not valid, all interrupts are forwarded without remapping. */
4623 if (Dte.n.u1IntrMapValid)
4624 {
4625 /* Validate bits 255:128 of the device table entry when DTE.IV is 1. */
4626 uint64_t const fRsvd0 = Dte.au64[2] & ~IOMMU_DTE_QWORD_2_VALID_MASK;
4627 uint64_t const fRsvd1 = Dte.au64[3] & ~IOMMU_DTE_QWORD_3_VALID_MASK;
4628 if (RT_LIKELY(!fRsvd0 && !fRsvd1))
4629 { /* likely */ }
4630 else
4631 {
4632 LogFunc(("Invalid reserved bits in DTE (u64[2]=%#RX64 u64[3]=%#RX64) -> Illegal DTE\n", fRsvd0, fRsvd1));
4633 EVT_ILLEGAL_DTE_T Event;
4634 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4635 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdNotZero);
4636 return VERR_IOMMU_INTR_REMAP_FAILED;
4637 }
4638
4639 /*
4640 * LINT0/LINT1 pins cannot be driven by PCI(e) devices. Perhaps for a Southbridge
4641 * that's connected through HyperTransport it might be possible; but for us, it
4642 * doesn't seem we need to specially handle these pins.
4643 */
4644
4645 /*
4646 * Validate the MSI source address.
4647 *
4648 * 64-bit MSIs are supported by the PCI and AMD IOMMU spec. However as far as the
4649 * CPU is concerned, the MSI region is fixed and we must ensure no other device
4650 * claims the region as I/O space.
4651 *
4652 * See PCI spec. 6.1.4. "Message Signaled Interrupt (MSI) Support".
4653 * See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support".
4654 * See Intel spec. 10.11.1 "Message Address Register Format".
4655 */
4656 if ((pMsiIn->Addr.u64 & VBOX_MSI_ADDR_ADDR_MASK) == VBOX_MSI_ADDR_BASE)
4657 {
4658 /*
4659 * The IOMMU remaps fixed and arbitrated interrupts using the IRTE.
4660 * See AMD IOMMU spec. "2.2.5.1 Interrupt Remapping Tables, Guest Virtual APIC Not Enabled".
4661 */
4662 uint8_t const u8DeliveryMode = pMsiIn->Data.n.u3DeliveryMode;
4663 bool fPassThru = false;
4664 switch (u8DeliveryMode)
4665 {
4666 case VBOX_MSI_DELIVERY_MODE_FIXED:
4667 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO:
4668 {
4669 uint8_t const uIntrCtrl = Dte.n.u2IntrCtrl;
4670 if (uIntrCtrl == IOMMU_INTR_CTRL_REMAP)
4671 {
4672 /* Validate the encoded interrupt table length when IntCtl specifies remapping. */
4673 uint8_t const uIntrTabLen = Dte.n.u4IntrTableLength;
4674 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
4675 {
4676 /*
4677 * We don't support guest interrupt remapping yet. When we do, we'll need to
4678 * check Ctrl.u1GstVirtApicEn and use the guest Virtual APIC Table Root Pointer
4679 * in the DTE rather than the Interrupt Root Table Pointer. Since the caller
4680 * already reads the control register, add that as a parameter when we eventually
4681 * support guest interrupt remapping. For now, just assert.
4682 */
4683 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4684 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
4685 NOREF(pThis);
4686
4687 return iommuAmdIntrRemap(pDevIns, idDevice, &Dte, enmOp, pMsiIn, pMsiOut);
4688 }
4689
4690 LogFunc(("Invalid interrupt table length %#x -> Illegal DTE\n", uIntrTabLen));
4691 EVT_ILLEGAL_DTE_T Event;
4692 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, false /* fRsvdNotZero */, enmOp, &Event);
4693 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntTabLen);
4694 return VERR_IOMMU_INTR_REMAP_FAILED;
4695 }
4696
4697 if (uIntrCtrl == IOMMU_INTR_CTRL_FWD_UNMAPPED)
4698 {
4699 fPassThru = true;
4700 break;
4701 }
4702
4703 if (uIntrCtrl == IOMMU_INTR_CTRL_TARGET_ABORT)
4704 {
4705 LogRelMax(10, ("%s: Remapping disallowed for fixed/arbitrated interrupt %#x -> Target abort\n",
4706 IOMMU_LOG_PFX, pMsiIn->Data.n.u8Vector));
4707 iommuAmdSetPciTargetAbort(pDevIns);
4708 return VERR_IOMMU_INTR_REMAP_DENIED;
4709 }
4710
4711 Assert(uIntrCtrl == IOMMU_INTR_CTRL_RSVD); /* Paranoia. */
4712 LogRelMax(10, ("%s: IntCtl mode invalid %#x -> Illegal DTE\n", IOMMU_LOG_PFX, uIntrCtrl));
4713 EVT_ILLEGAL_DTE_T Event;
4714 iommuAmdIllegalDteEventInit(idDevice, pMsiIn->Addr.u64, true /* fRsvdNotZero */, enmOp, &Event);
4715 iommuAmdIllegalDteEventRaise(pDevIns, enmOp, &Event, kIllegalDteType_RsvdIntCtl);
4716 return VERR_IOMMU_INTR_REMAP_FAILED;
4717 }
4718
4719 /* SMIs are passed through unmapped. We don't implement SMI filters. */
4720 case VBOX_MSI_DELIVERY_MODE_SMI: fPassThru = true; break;
4721 case VBOX_MSI_DELIVERY_MODE_NMI: fPassThru = Dte.n.u1NmiPassthru; break;
4722 case VBOX_MSI_DELIVERY_MODE_INIT: fPassThru = Dte.n.u1InitPassthru; break;
4723 case VBOX_MSI_DELIVERY_MODE_EXT_INT: fPassThru = Dte.n.u1ExtIntPassthru; break;
4724 default:
4725 {
4726 LogRelMax(10, ("%s: MSI data delivery mode invalid %#x -> Target abort\n", IOMMU_LOG_PFX,
4727 u8DeliveryMode));
4728 iommuAmdSetPciTargetAbort(pDevIns);
4729 return VERR_IOMMU_INTR_REMAP_FAILED;
4730 }
4731 }
4732
4733 /*
4734 * For those other than fixed and arbitrated interrupts, destination mode must be 0 (physical).
4735 * See AMD IOMMU spec. The note below Table 19: "IOMMU Controls and Actions for Upstream Interrupts".
4736 */
4737 if ( u8DeliveryMode <= VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO
4738 || !pMsiIn->Addr.n.u1DestMode)
4739 {
4740 if (fPassThru)
4741 {
4742 *pMsiOut = *pMsiIn;
4743 return VINF_SUCCESS;
4744 }
4745 LogRelMax(10, ("%s: Remapping/passthru disallowed for interrupt %#x -> Target abort\n", IOMMU_LOG_PFX,
4746 pMsiIn->Data.n.u8Vector));
4747 }
4748 else
4749 LogRelMax(10, ("%s: Logical destination mode invalid for delivery mode %#x\n -> Target abort\n",
4750 IOMMU_LOG_PFX, u8DeliveryMode));
4751
4752 iommuAmdSetPciTargetAbort(pDevIns);
4753 return VERR_IOMMU_INTR_REMAP_DENIED;
4754 }
4755 else
4756 {
4757 /** @todo should be cause a PCI target abort here? */
4758 LogRelMax(10, ("%s: MSI address region invalid %#RX64\n", IOMMU_LOG_PFX, pMsiIn->Addr.u64));
4759 return VERR_IOMMU_INTR_REMAP_FAILED;
4760 }
4761 }
4762 else
4763 {
4764 LogFlowFunc(("DTE interrupt map not valid\n"));
4765 *pMsiOut = *pMsiIn;
4766 return VINF_SUCCESS;
4767 }
4768 }
4769
4770 LogFunc(("Failed to read device table entry. idDevice=%#x rc=%Rrc\n", idDevice, rc));
4771 return VERR_IOMMU_INTR_REMAP_FAILED;
4772}
4773
4774
4775/**
4776 * Interrupt remap request from a device.
4777 *
4778 * @returns VBox status code.
4779 * @param pDevIns The IOMMU device instance.
4780 * @param idDevice The device ID (bus, device, function).
4781 * @param pMsiIn The source MSI.
4782 * @param pMsiOut Where to store the remapped MSI.
4783 */
4784static DECLCALLBACK(int) iommuAmdMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
4785{
4786 /* Validate. */
4787 Assert(pDevIns);
4788 Assert(pMsiIn);
4789 Assert(pMsiOut);
4790
4791 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4792
4793 /* If this MSI was generated by the IOMMU itself, it's not subject to remapping, see @bugref{9654#c104}. */
4794 if (idDevice == pThis->uPciAddress)
4795 return VERR_IOMMU_CANNOT_CALL_SELF;
4796
4797 /* Interrupts are forwarded with remapping when the IOMMU is disabled. */
4798 IOMMU_CTRL_T const Ctrl = iommuAmdGetCtrlUnlocked(pThis);
4799 if (Ctrl.n.u1IommuEn)
4800 {
4801 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
4802
4803 int rc;
4804#ifdef IOMMU_WITH_IRTE_CACHE
4805 STAM_PROFILE_ADV_START(&pThis->StatProfIrteCacheLookup, a);
4806 rc = iommuAmdIrteCacheLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4807 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteCacheLookup, a);
4808 if (RT_SUCCESS(rc))
4809 {
4810 STAM_COUNTER_INC(&pThis->StatIntrCacheHit);
4811 return VINF_SUCCESS;
4812 }
4813 STAM_COUNTER_INC(&pThis->StatIntrCacheMiss);
4814#endif
4815
4816 STAM_PROFILE_ADV_START(&pThis->StatProfIrteLookup, a);
4817 rc = iommuAmdIntrTableLookup(pDevIns, idDevice, IOMMUOP_INTR_REQ, pMsiIn, pMsiOut);
4818 STAM_PROFILE_ADV_STOP(&pThis->StatProfIrteLookup, a);
4819 return rc;
4820 }
4821
4822 *pMsiOut = *pMsiIn;
4823 return VINF_SUCCESS;
4824}
4825
4826
4827/**
4828 * @callback_method_impl{FNIOMMMIONEWWRITE}
4829 */
4830static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
4831{
4832 NOREF(pvUser);
4833 Assert(cb == 4 || cb == 8);
4834 Assert(!(off & (cb - 1)));
4835
4836 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4837 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite)); NOREF(pThis);
4838
4839 uint64_t const uValue = cb == 8 ? *(uint64_t const *)pv : *(uint32_t const *)pv;
4840 return iommuAmdRegisterWrite(pDevIns, off, cb, uValue);
4841}
4842
4843
4844/**
4845 * @callback_method_impl{FNIOMMMIONEWREAD}
4846 */
4847static DECLCALLBACK(VBOXSTRICTRC) iommuAmdMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
4848{
4849 NOREF(pvUser);
4850 Assert(cb == 4 || cb == 8);
4851 Assert(!(off & (cb - 1)));
4852
4853 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4854 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead)); NOREF(pThis);
4855
4856 uint64_t uResult;
4857 VBOXSTRICTRC rcStrict = iommuAmdRegisterRead(pDevIns, off, &uResult);
4858 if (rcStrict == VINF_SUCCESS)
4859 {
4860 if (cb == 8)
4861 *(uint64_t *)pv = uResult;
4862 else
4863 *(uint32_t *)pv = (uint32_t)uResult;
4864 }
4865
4866 return rcStrict;
4867}
4868
4869
4870#ifdef IN_RING3
4871/**
4872 * Processes an IOMMU command.
4873 *
4874 * @returns VBox status code.
4875 * @param pDevIns The IOMMU device instance.
4876 * @param pCmd The command to process.
4877 * @param GCPhysCmd The system physical address of the command.
4878 * @param pEvtError Where to store the error event in case of failures.
4879 *
4880 * @thread Command thread.
4881 */
4882static int iommuAmdR3CmdProcess(PPDMDEVINS pDevIns, PCCMD_GENERIC_T pCmd, RTGCPHYS GCPhysCmd, PEVT_GENERIC_T pEvtError)
4883{
4884 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
4885 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
4886
4887 STAM_COUNTER_INC(&pThis->StatCmd);
4888
4889 uint8_t const bCmd = pCmd->n.u4Opcode;
4890 switch (bCmd)
4891 {
4892 case IOMMU_CMD_COMPLETION_WAIT:
4893 {
4894 STAM_COUNTER_INC(&pThis->StatCmdCompWait);
4895
4896 PCCMD_COMWAIT_T pCmdComWait = (PCCMD_COMWAIT_T)pCmd;
4897 AssertCompile(sizeof(*pCmdComWait) == sizeof(*pCmd));
4898
4899 /* Validate reserved bits in the command. */
4900 if (!(pCmdComWait->au64[0] & ~IOMMU_CMD_COM_WAIT_QWORD_0_VALID_MASK))
4901 {
4902 /* If Completion Store is requested, write the StoreData to the specified address. */
4903 if (pCmdComWait->n.u1Store)
4904 {
4905 RTGCPHYS const GCPhysStore = RT_MAKE_U64(pCmdComWait->n.u29StoreAddrLo << 3, pCmdComWait->n.u20StoreAddrHi);
4906 uint64_t const u64Data = pCmdComWait->n.u64StoreData;
4907 int rc = PDMDevHlpPCIPhysWrite(pDevIns, GCPhysStore, &u64Data, sizeof(u64Data));
4908 if (RT_FAILURE(rc))
4909 {
4910 LogFunc(("Cmd(%#x): Failed to write StoreData (%#RX64) to %#RGp, rc=%Rrc\n", bCmd, u64Data,
4911 GCPhysStore, rc));
4912 iommuAmdCmdHwErrorEventInit(GCPhysStore, (PEVT_CMD_HW_ERR_T)pEvtError);
4913 return VERR_IOMMU_CMD_HW_ERROR;
4914 }
4915 }
4916
4917 /* If the command requests an interrupt and completion wait interrupts are enabled, raise it. */
4918 if (pCmdComWait->n.u1Interrupt)
4919 {
4920 IOMMU_LOCK(pDevIns, pThisR3);
4921 ASMAtomicOrU64(&pThis->Status.u64, IOMMU_STATUS_COMPLETION_WAIT_INTR);
4922 bool const fRaiseInt = pThis->Ctrl.n.u1CompWaitIntrEn;
4923 IOMMU_UNLOCK(pDevIns, pThisR3);
4924 if (fRaiseInt)
4925 iommuAmdMsiInterruptRaise(pDevIns);
4926 }
4927 return VINF_SUCCESS;
4928 }
4929 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4930 return VERR_IOMMU_CMD_INVALID_FORMAT;
4931 }
4932
4933 case IOMMU_CMD_INV_DEV_TAB_ENTRY:
4934 {
4935 STAM_COUNTER_INC(&pThis->StatCmdInvDte);
4936 PCCMD_INV_DTE_T pCmdInvDte = (PCCMD_INV_DTE_T)pCmd;
4937 AssertCompile(sizeof(*pCmdInvDte) == sizeof(*pCmd));
4938
4939 /* Validate reserved bits in the command. */
4940 if ( !(pCmdInvDte->au64[0] & ~IOMMU_CMD_INV_DTE_QWORD_0_VALID_MASK)
4941 && !(pCmdInvDte->au64[1] & ~IOMMU_CMD_INV_DTE_QWORD_1_VALID_MASK))
4942 {
4943#ifdef IOMMU_WITH_DTE_CACHE
4944 iommuAmdDteCacheRemove(pDevIns, pCmdInvDte->n.u16DevId);
4945#endif
4946 return VINF_SUCCESS;
4947 }
4948 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
4949 return VERR_IOMMU_CMD_INVALID_FORMAT;
4950 }
4951
4952 case IOMMU_CMD_INV_IOMMU_PAGES:
4953 {
4954 STAM_COUNTER_INC(&pThis->StatCmdInvIommuPages);
4955 PCCMD_INV_IOMMU_PAGES_T pCmdInvPages = (PCCMD_INV_IOMMU_PAGES_T)pCmd;
4956 AssertCompile(sizeof(*pCmdInvPages) == sizeof(*pCmd));
4957
4958 /* Validate reserved bits in the command. */
4959 if ( !(pCmdInvPages->au64[0] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_0_VALID_MASK)
4960 && !(pCmdInvPages->au64[1] & ~IOMMU_CMD_INV_IOMMU_PAGES_QWORD_1_VALID_MASK))
4961 {
4962#ifdef IOMMU_WITH_IOTLBE_CACHE
4963 uint64_t const uIova = RT_MAKE_U64(pCmdInvPages->n.u20AddrLo << X86_PAGE_4K_SHIFT, pCmdInvPages->n.u32AddrHi);
4964 uint16_t const idDomain = pCmdInvPages->n.u16DomainId;
4965 uint8_t cShift;
4966 if (!pCmdInvPages->n.u1Size)
4967 cShift = X86_PAGE_4K_SHIFT;
4968 else
4969 {
4970 /* Find the first clear bit starting from bit 12 to 64 of the I/O virtual address. */
4971 unsigned const uFirstZeroBit = ASMBitLastSetU64(~(uIova >> X86_PAGE_4K_SHIFT));
4972 cShift = X86_PAGE_4K_SHIFT + uFirstZeroBit;
4973
4974 /*
4975 * For the address 0x7ffffffffffff000, cShift would be 76 (12+64) and the code below
4976 * would do the right thing by clearing the entire cache for the specified domain ID.
4977 *
4978 * However, for the address 0xfffffffffffff000, cShift would be computed as 12.
4979 * IOMMU behavior is undefined in this case, so it's safe to invalidate just one page.
4980 * A debug-time assert is in place here to let us know if any software tries this.
4981 *
4982 * See AMD IOMMU spec. 2.4.3 "INVALIDATE_IOMMU_PAGES".
4983 * See AMD IOMMU spec. Table 14: "Example Page Size Encodings".
4984 */
4985 Assert(uIova != UINT64_C(0xfffffffffffff000));
4986 }
4987
4988 /*
4989 * Validate invalidation size.
4990 * See AMD IOMMU spec. 2.2.3 "I/O Page Tables for Host Translations".
4991 */
4992 if ( cShift == 12 /* 4K */ || cShift == 13 /* 8K */
4993 || cShift == 14 /* 16K */ || cShift == 20 /* 1M */
4994 || cShift == 22 /* 4M */ || cShift == 32 /* 4G */)
4995 {
4996 /* Remove the range of I/O virtual addresses requesting to be invalidated. */
4997 size_t const cbIova = RT_BIT_64(cShift);
4998 iommuAmdIotlbRemoveRange(pDevIns, idDomain, uIova, cbIova);
4999 }
5000 else
5001 {
5002 /*
5003 * The guest provided size is invalid or exceeds the largest, meaningful page size.
5004 * In such situations we must remove all ranges for the specified domain ID.
5005 */
5006 iommuAmdIotlbRemoveDomainId(pDevIns, idDomain);
5007 }
5008#endif
5009 return VINF_SUCCESS;
5010 }
5011 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5012 return VERR_IOMMU_CMD_INVALID_FORMAT;
5013 }
5014
5015 case IOMMU_CMD_INV_IOTLB_PAGES:
5016 {
5017 STAM_COUNTER_INC(&pThis->StatCmdInvIotlbPages);
5018
5019 uint32_t const uCapHdr = PDMPciDevGetDWord(pDevIns->apPciDevs[0], IOMMU_PCI_OFF_CAP_HDR);
5020 if (RT_BF_GET(uCapHdr, IOMMU_BF_CAPHDR_IOTLB_SUP))
5021 {
5022 /** @todo IOMMU: Implement remote IOTLB invalidation. */
5023 return VERR_NOT_IMPLEMENTED;
5024 }
5025 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5026 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5027 }
5028
5029 case IOMMU_CMD_INV_INTR_TABLE:
5030 {
5031 STAM_COUNTER_INC(&pThis->StatCmdInvIntrTable);
5032
5033 PCCMD_INV_INTR_TABLE_T pCmdInvIntrTable = (PCCMD_INV_INTR_TABLE_T)pCmd;
5034 AssertCompile(sizeof(*pCmdInvIntrTable) == sizeof(*pCmd));
5035
5036 /* Validate reserved bits in the command. */
5037 if ( !(pCmdInvIntrTable->au64[0] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_0_VALID_MASK)
5038 && !(pCmdInvIntrTable->au64[1] & ~IOMMU_CMD_INV_INTR_TABLE_QWORD_1_VALID_MASK))
5039 {
5040#ifdef IOMMU_WITH_IRTE_CACHE
5041 iommuAmdIrteCacheRemove(pDevIns, pCmdInvIntrTable->u.u16DevId);
5042#endif
5043 return VINF_SUCCESS;
5044 }
5045 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5046 return VERR_IOMMU_CMD_INVALID_FORMAT;
5047 }
5048
5049 case IOMMU_CMD_PREFETCH_IOMMU_PAGES:
5050 {
5051 /* Linux doesn't use prefetching of IOMMU pages, so we don't bother for now. */
5052 STAM_COUNTER_INC(&pThis->StatCmdPrefIommuPages);
5053 Assert(!pThis->ExtFeat.n.u1PrefetchSup);
5054 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5055 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5056 }
5057
5058 case IOMMU_CMD_COMPLETE_PPR_REQ:
5059 {
5060 STAM_COUNTER_INC(&pThis->StatCmdCompletePprReq);
5061
5062 /* We don't support PPR requests yet. */
5063 Assert(!pThis->ExtFeat.n.u1PprSup);
5064 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5065 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5066 }
5067
5068 case IOMMU_CMD_INV_IOMMU_ALL:
5069 {
5070 STAM_COUNTER_INC(&pThis->StatCmdInvIommuAll);
5071 if (pThis->ExtFeat.n.u1InvAllSup)
5072 {
5073 PCCMD_INV_IOMMU_ALL_T pCmdInvAll = (PCCMD_INV_IOMMU_ALL_T)pCmd;
5074 AssertCompile(sizeof(*pCmdInvAll) == sizeof(*pCmd));
5075
5076 /* Validate reserved bits in the command. */
5077 if ( !(pCmdInvAll->au64[0] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_0_VALID_MASK)
5078 && !(pCmdInvAll->au64[1] & ~IOMMU_CMD_INV_IOMMU_ALL_QWORD_1_VALID_MASK))
5079 {
5080#ifdef IOMMU_WITH_DTE_CACHE
5081 iommuAmdDteCacheRemoveAll(pDevIns);
5082#endif
5083#ifdef IOMMU_WITH_IOTLBE_CACHE
5084 iommuAmdIotlbRemoveAll(pDevIns);
5085#endif
5086 return VINF_SUCCESS;
5087 }
5088 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5089 return VERR_IOMMU_CMD_INVALID_FORMAT;
5090 }
5091 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5092 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5093 }
5094 }
5095
5096 STAM_COUNTER_DEC(&pThis->StatCmd);
5097 LogFunc(("Cmd(%#x): Unrecognized\n", bCmd));
5098 iommuAmdIllegalCmdEventInit(GCPhysCmd, (PEVT_ILLEGAL_CMD_ERR_T)pEvtError);
5099 return VERR_IOMMU_CMD_NOT_SUPPORTED;
5100}
5101
5102
5103/**
5104 * The IOMMU command thread.
5105 *
5106 * @returns VBox status code.
5107 * @param pDevIns The IOMMU device instance.
5108 * @param pThread The command thread.
5109 */
5110static DECLCALLBACK(int) iommuAmdR3CmdThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5111{
5112 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5113 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5114
5115 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
5116 return VINF_SUCCESS;
5117
5118 /*
5119 * Pre-allocate the maximum command buffer size supported by the IOMMU.
5120 * This avoid trashing the heap as well as not wasting time allocating
5121 * and freeing buffers while processing commands.
5122 */
5123 size_t const cbMaxCmdBuf = sizeof(CMD_GENERIC_T) * iommuAmdGetBufMaxEntries(15);
5124 void *pvCmds = RTMemAllocZ(cbMaxCmdBuf);
5125 AssertPtrReturn(pvCmds, VERR_NO_MEMORY);
5126
5127 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
5128 {
5129 /*
5130 * Sleep perpetually until we are woken up to process commands.
5131 */
5132 bool const fSignaled = ASMAtomicXchgBool(&pThis->fCmdThreadSignaled, false);
5133 if (!fSignaled)
5134 {
5135 int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtCmdThread, RT_INDEFINITE_WAIT);
5136 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
5137 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
5138 break;
5139 Log4Func(("Woken up with rc=%Rrc\n", rc));
5140 ASMAtomicWriteBool(&pThis->fCmdThreadSignaled, false);
5141 }
5142
5143 /*
5144 * Fetch and process IOMMU commands.
5145 */
5146 /** @todo r=ramshankar: We currently copy all commands from guest memory into a
5147 * temporary host buffer before processing them as a batch. If we want to
5148 * save on host memory a bit, we could (once PGM has the necessary APIs)
5149 * lock the page mappings page mappings and access them directly. */
5150 IOMMU_LOCK(pDevIns, pThisR3);
5151
5152 if (pThis->Status.n.u1CmdBufRunning)
5153 {
5154 /* Get the offsets we need to read commands from memory (circular buffer offset). */
5155 uint32_t const cbCmdBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
5156 uint32_t const offTail = pThis->CmdBufTailPtr.n.off;
5157 uint32_t offHead = pThis->CmdBufHeadPtr.n.off;
5158
5159 /* Validate. */
5160 Assert(!(offHead & ~IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK));
5161 Assert(offHead < cbCmdBuf);
5162 Assert(cbCmdBuf <= cbMaxCmdBuf);
5163
5164 if (offHead != offTail)
5165 {
5166 /* Read the entire command buffer from memory (avoids multiple PGM calls). */
5167 RTGCPHYS const GCPhysCmdBufBase = pThis->CmdBufBaseAddr.n.u40Base << X86_PAGE_4K_SHIFT;
5168
5169 IOMMU_UNLOCK(pDevIns, pThisR3);
5170 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysCmdBufBase, pvCmds, cbCmdBuf);
5171 IOMMU_LOCK(pDevIns, pThisR3);
5172
5173 if (RT_SUCCESS(rc))
5174 {
5175 /* Indicate to software we've fetched all commands from the buffer. */
5176 pThis->CmdBufHeadPtr.n.off = offTail;
5177
5178 /* Allow IOMMU to do other work while we process commands. */
5179 IOMMU_UNLOCK(pDevIns, pThisR3);
5180
5181 /* Process the fetched commands. */
5182 EVT_GENERIC_T EvtError;
5183 do
5184 {
5185 PCCMD_GENERIC_T pCmd = (PCCMD_GENERIC_T)((uintptr_t)pvCmds + offHead);
5186 rc = iommuAmdR3CmdProcess(pDevIns, pCmd, GCPhysCmdBufBase + offHead, &EvtError);
5187 if (RT_FAILURE(rc))
5188 {
5189 if ( rc == VERR_IOMMU_CMD_NOT_SUPPORTED
5190 || rc == VERR_IOMMU_CMD_INVALID_FORMAT)
5191 {
5192 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_ILLEGAL_CMD_ERROR);
5193 iommuAmdIllegalCmdEventRaise(pDevIns, (PCEVT_ILLEGAL_CMD_ERR_T)&EvtError);
5194 }
5195 else if (rc == VERR_IOMMU_CMD_HW_ERROR)
5196 {
5197 Assert(EvtError.n.u4EvtCode == IOMMU_EVT_COMMAND_HW_ERROR);
5198 LogFunc(("Raising command hardware error. Cmd=%#x -> COMMAND_HW_ERROR\n", pCmd->n.u4Opcode));
5199 iommuAmdCmdHwErrorEventRaise(pDevIns, (PCEVT_CMD_HW_ERR_T)&EvtError);
5200 }
5201 break;
5202 }
5203
5204 /* Move to the next command in the circular buffer. */
5205 offHead = (offHead + sizeof(CMD_GENERIC_T)) % cbCmdBuf;
5206 } while (offHead != offTail);
5207 }
5208 else
5209 {
5210 LogFunc(("Failed to read command at %#RGp. rc=%Rrc -> COMMAND_HW_ERROR\n", GCPhysCmdBufBase, rc));
5211 EVT_CMD_HW_ERR_T EvtCmdHwErr;
5212 iommuAmdCmdHwErrorEventInit(GCPhysCmdBufBase, &EvtCmdHwErr);
5213 iommuAmdCmdHwErrorEventRaise(pDevIns, &EvtCmdHwErr);
5214
5215 IOMMU_UNLOCK(pDevIns, pThisR3);
5216 }
5217 }
5218 else
5219 IOMMU_UNLOCK(pDevIns, pThisR3);
5220 }
5221 else
5222 IOMMU_UNLOCK(pDevIns, pThisR3);
5223 }
5224
5225 RTMemFree(pvCmds);
5226 LogFlowFunc(("Command thread terminating\n"));
5227 return VINF_SUCCESS;
5228}
5229
5230
5231/**
5232 * Wakes up the command thread so it can respond to a state change.
5233 *
5234 * @returns VBox status code.
5235 * @param pDevIns The IOMMU device instance.
5236 * @param pThread The command thread.
5237 */
5238static DECLCALLBACK(int) iommuAmdR3CmdThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
5239{
5240 RT_NOREF(pThread);
5241 Log4Func(("\n"));
5242 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5243 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtCmdThread);
5244}
5245
5246
5247/**
5248 * @callback_method_impl{FNPCICONFIGREAD}
5249 */
5250static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5251 unsigned cb, uint32_t *pu32Value)
5252{
5253 /** @todo IOMMU: PCI config read stat counter. */
5254 VBOXSTRICTRC rcStrict = PDMDevHlpPCIConfigRead(pDevIns, pPciDev, uAddress, cb, pu32Value);
5255 Log3Func(("uAddress=%#x (cb=%u) -> %#x. rc=%Rrc\n", uAddress, cb, *pu32Value, VBOXSTRICTRC_VAL(rcStrict)));
5256 return rcStrict;
5257}
5258
5259
5260/**
5261 * Sets up the IOMMU MMIO region (usually in response to an IOMMU base address
5262 * register write).
5263 *
5264 * @returns VBox status code.
5265 * @param pDevIns The IOMMU instance data.
5266 *
5267 * @remarks Call this function only when the IOMMU BAR is enabled.
5268 */
5269static int iommuAmdR3MmioSetup(PPDMDEVINS pDevIns)
5270{
5271 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5272 Assert(pThis->IommuBar.n.u1Enable);
5273 Assert(pThis->hMmio != NIL_IOMMMIOHANDLE); /* Paranoia. Ensure we have a valid IOM MMIO handle. */
5274 Assert(!pThis->ExtFeat.n.u1PerfCounterSup); /* Base is 16K aligned when performance counters aren't supported. */
5275 RTGCPHYS const GCPhysMmioBase = RT_MAKE_U64(pThis->IommuBar.au32[0] & 0xffffc000, pThis->IommuBar.au32[1]);
5276 RTGCPHYS const GCPhysMmioBasePrev = PDMDevHlpMmioGetMappingAddress(pDevIns, pThis->hMmio);
5277
5278 /* If the MMIO region is already mapped at the specified address, we're done. */
5279 Assert(GCPhysMmioBase != NIL_RTGCPHYS);
5280 if (GCPhysMmioBasePrev == GCPhysMmioBase)
5281 return VINF_SUCCESS;
5282
5283 /* Unmap the previous MMIO region (which is at a different address). */
5284 if (GCPhysMmioBasePrev != NIL_RTGCPHYS)
5285 {
5286 LogFlowFunc(("Unmapping previous MMIO region at %#RGp\n", GCPhysMmioBasePrev));
5287 int rc = PDMDevHlpMmioUnmap(pDevIns, pThis->hMmio);
5288 if (RT_FAILURE(rc))
5289 {
5290 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBasePrev, rc));
5291 return rc;
5292 }
5293 }
5294
5295 /* Map the newly specified MMIO region. */
5296 LogFlowFunc(("Mapping MMIO region at %#RGp\n", GCPhysMmioBase));
5297 int rc = PDMDevHlpMmioMap(pDevIns, pThis->hMmio, GCPhysMmioBase);
5298 if (RT_FAILURE(rc))
5299 {
5300 LogFunc(("Failed to unmap MMIO region at %#RGp. rc=%Rrc\n", GCPhysMmioBase, rc));
5301 return rc;
5302 }
5303
5304 return VINF_SUCCESS;
5305}
5306
5307
5308/**
5309 * @callback_method_impl{FNPCICONFIGWRITE}
5310 */
5311static DECLCALLBACK(VBOXSTRICTRC) iommuAmdR3PciConfigWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t uAddress,
5312 unsigned cb, uint32_t u32Value)
5313{
5314 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5315
5316 /*
5317 * Discard writes to read-only registers that are specific to the IOMMU.
5318 * Other common PCI registers are handled by the generic code, see devpciR3IsConfigByteWritable().
5319 * See PCI spec. 6.1. "Configuration Space Organization".
5320 */
5321 switch (uAddress)
5322 {
5323 case IOMMU_PCI_OFF_CAP_HDR: /* All bits are read-only. */
5324 case IOMMU_PCI_OFF_RANGE_REG: /* We don't have any devices integrated with the IOMMU. */
5325 case IOMMU_PCI_OFF_MISCINFO_REG_0: /* We don't support MSI-X. */
5326 case IOMMU_PCI_OFF_MISCINFO_REG_1: /* We don't support guest-address translation. */
5327 {
5328 LogFunc(("PCI config write (%#RX32) to read-only register %#x -> Ignored\n", u32Value, uAddress));
5329 return VINF_SUCCESS;
5330 }
5331 }
5332
5333 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
5334 IOMMU_LOCK(pDevIns, pThisR3);
5335
5336 VBOXSTRICTRC rcStrict;
5337 switch (uAddress)
5338 {
5339 case IOMMU_PCI_OFF_BASE_ADDR_REG_LO:
5340 {
5341 if (!pThis->IommuBar.n.u1Enable)
5342 {
5343 pThis->IommuBar.au32[0] = u32Value & IOMMU_BAR_VALID_MASK;
5344 if (pThis->IommuBar.n.u1Enable)
5345 rcStrict = iommuAmdR3MmioSetup(pDevIns);
5346 else
5347 rcStrict = VINF_SUCCESS;
5348 }
5349 else
5350 {
5351 LogFunc(("Writing Base Address (Lo) when it's already enabled -> Ignored\n"));
5352 rcStrict = VINF_SUCCESS;
5353 }
5354 break;
5355 }
5356
5357 case IOMMU_PCI_OFF_BASE_ADDR_REG_HI:
5358 {
5359 if (!pThis->IommuBar.n.u1Enable)
5360 {
5361 AssertCompile((IOMMU_BAR_VALID_MASK >> 32) == 0xffffffff);
5362 pThis->IommuBar.au32[1] = u32Value;
5363 }
5364 else
5365 LogFunc(("Writing Base Address (Hi) when it's already enabled -> Ignored\n"));
5366 rcStrict = VINF_SUCCESS;
5367 break;
5368 }
5369
5370 case IOMMU_PCI_OFF_MSI_CAP_HDR:
5371 {
5372 u32Value |= RT_BIT(23); /* 64-bit MSI addressess must always be enabled for IOMMU. */
5373 RT_FALL_THRU();
5374 }
5375 default:
5376 {
5377 rcStrict = PDMDevHlpPCIConfigWrite(pDevIns, pPciDev, uAddress, cb, u32Value);
5378 break;
5379 }
5380 }
5381
5382 IOMMU_UNLOCK(pDevIns, pThisR3);
5383
5384 Log3Func(("uAddress=%#x (cb=%u) with %#x. rc=%Rrc\n", uAddress, cb, u32Value, VBOXSTRICTRC_VAL(rcStrict)));
5385 return rcStrict;
5386}
5387
5388
5389/**
5390 * @callback_method_impl{FNDBGFHANDLERDEV}
5391 */
5392static DECLCALLBACK(void) iommuAmdR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5393{
5394 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
5395 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
5396 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
5397
5398 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
5399
5400 pHlp->pfnPrintf(pHlp, "AMD-IOMMU:\n");
5401 /* Device Table Base Addresses (all segments). */
5402 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
5403 {
5404 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
5405 pHlp->pfnPrintf(pHlp, " Device Table BAR %u = %#RX64\n", i, DevTabBar.u64);
5406 if (fVerbose)
5407 {
5408 pHlp->pfnPrintf(pHlp, " Size = %#x (%u bytes)\n", DevTabBar.n.u9Size,
5409 IOMMU_GET_DEV_TAB_LEN(&DevTabBar));
5410 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5411 DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT);
5412 }
5413 }
5414 /* Command Buffer Base Address Register. */
5415 {
5416 CMD_BUF_BAR_T const CmdBufBar = pThis->CmdBufBaseAddr;
5417 uint8_t const uEncodedLen = CmdBufBar.n.u4Len;
5418 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5419 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5420 pHlp->pfnPrintf(pHlp, " Command Buffer BAR = %#RX64\n", CmdBufBar.u64);
5421 if (fVerbose)
5422 {
5423 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5424 CmdBufBar.n.u40Base << X86_PAGE_4K_SHIFT);
5425 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5426 cEntries, cbBuffer);
5427 }
5428 }
5429 /* Event Log Base Address Register. */
5430 {
5431 EVT_LOG_BAR_T const EvtLogBar = pThis->EvtLogBaseAddr;
5432 uint8_t const uEncodedLen = EvtLogBar.n.u4Len;
5433 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5434 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5435 pHlp->pfnPrintf(pHlp, " Event Log BAR = %#RX64\n", EvtLogBar.u64);
5436 if (fVerbose)
5437 {
5438 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5439 EvtLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5440 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5441 cEntries, cbBuffer);
5442 }
5443 }
5444 /* IOMMU Control Register. */
5445 {
5446 IOMMU_CTRL_T const Ctrl = pThis->Ctrl;
5447 pHlp->pfnPrintf(pHlp, " Control = %#RX64\n", Ctrl.u64);
5448 if (fVerbose)
5449 {
5450 pHlp->pfnPrintf(pHlp, " IOMMU enable = %RTbool\n", Ctrl.n.u1IommuEn);
5451 pHlp->pfnPrintf(pHlp, " HT Tunnel translation enable = %RTbool\n", Ctrl.n.u1HtTunEn);
5452 pHlp->pfnPrintf(pHlp, " Event log enable = %RTbool\n", Ctrl.n.u1EvtLogEn);
5453 pHlp->pfnPrintf(pHlp, " Event log interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5454 pHlp->pfnPrintf(pHlp, " Completion wait interrupt enable = %RTbool\n", Ctrl.n.u1EvtIntrEn);
5455 pHlp->pfnPrintf(pHlp, " Invalidation timeout = %u\n", Ctrl.n.u3InvTimeOut);
5456 pHlp->pfnPrintf(pHlp, " Pass posted write = %RTbool\n", Ctrl.n.u1PassPW);
5457 pHlp->pfnPrintf(pHlp, " Respose Pass posted write = %RTbool\n", Ctrl.n.u1ResPassPW);
5458 pHlp->pfnPrintf(pHlp, " Coherent = %RTbool\n", Ctrl.n.u1Coherent);
5459 pHlp->pfnPrintf(pHlp, " Isochronous = %RTbool\n", Ctrl.n.u1Isoc);
5460 pHlp->pfnPrintf(pHlp, " Command buffer enable = %RTbool\n", Ctrl.n.u1CmdBufEn);
5461 pHlp->pfnPrintf(pHlp, " PPR log enable = %RTbool\n", Ctrl.n.u1PprLogEn);
5462 pHlp->pfnPrintf(pHlp, " PPR interrupt enable = %RTbool\n", Ctrl.n.u1PprIntrEn);
5463 pHlp->pfnPrintf(pHlp, " PPR enable = %RTbool\n", Ctrl.n.u1PprEn);
5464 pHlp->pfnPrintf(pHlp, " Guest translation eanble = %RTbool\n", Ctrl.n.u1GstTranslateEn);
5465 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC enable = %RTbool\n", Ctrl.n.u1GstVirtApicEn);
5466 pHlp->pfnPrintf(pHlp, " CRW = %#x\n", Ctrl.n.u4Crw);
5467 pHlp->pfnPrintf(pHlp, " SMI filter enable = %RTbool\n", Ctrl.n.u1SmiFilterEn);
5468 pHlp->pfnPrintf(pHlp, " Self-writeback disable = %RTbool\n", Ctrl.n.u1SelfWriteBackDis);
5469 pHlp->pfnPrintf(pHlp, " SMI filter log enable = %RTbool\n", Ctrl.n.u1SmiFilterLogEn);
5470 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC mode enable = %#x\n", Ctrl.n.u3GstVirtApicModeEn);
5471 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC GA log enable = %RTbool\n", Ctrl.n.u1GstLogEn);
5472 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC interrupt enable = %RTbool\n", Ctrl.n.u1GstIntrEn);
5473 pHlp->pfnPrintf(pHlp, " Dual PPR log enable = %#x\n", Ctrl.n.u2DualPprLogEn);
5474 pHlp->pfnPrintf(pHlp, " Dual event log enable = %#x\n", Ctrl.n.u2DualEvtLogEn);
5475 pHlp->pfnPrintf(pHlp, " Device table segmentation enable = %#x\n", Ctrl.n.u3DevTabSegEn);
5476 pHlp->pfnPrintf(pHlp, " Privilege abort enable = %#x\n", Ctrl.n.u2PrivAbortEn);
5477 pHlp->pfnPrintf(pHlp, " PPR auto response enable = %RTbool\n", Ctrl.n.u1PprAutoRespEn);
5478 pHlp->pfnPrintf(pHlp, " MARC enable = %RTbool\n", Ctrl.n.u1MarcEn);
5479 pHlp->pfnPrintf(pHlp, " Block StopMark enable = %RTbool\n", Ctrl.n.u1BlockStopMarkEn);
5480 pHlp->pfnPrintf(pHlp, " PPR auto response always-on enable = %RTbool\n", Ctrl.n.u1PprAutoRespAlwaysOnEn);
5481 pHlp->pfnPrintf(pHlp, " Domain IDPNE = %RTbool\n", Ctrl.n.u1DomainIDPNE);
5482 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling = %RTbool\n", Ctrl.n.u1EnhancedPpr);
5483 pHlp->pfnPrintf(pHlp, " Host page table access/dirty bit update = %#x\n", Ctrl.n.u2HstAccDirtyBitUpdate);
5484 pHlp->pfnPrintf(pHlp, " Guest page table dirty bit disable = %RTbool\n", Ctrl.n.u1GstDirtyUpdateDis);
5485 pHlp->pfnPrintf(pHlp, " x2APIC enable = %RTbool\n", Ctrl.n.u1X2ApicEn);
5486 pHlp->pfnPrintf(pHlp, " x2APIC interrupt enable = %RTbool\n", Ctrl.n.u1X2ApicIntrGenEn);
5487 pHlp->pfnPrintf(pHlp, " Guest page table access bit update = %RTbool\n", Ctrl.n.u1GstAccessUpdateDis);
5488 }
5489 }
5490 /* Exclusion Base Address Register. */
5491 {
5492 IOMMU_EXCL_RANGE_BAR_T const ExclRangeBar = pThis->ExclRangeBaseAddr;
5493 pHlp->pfnPrintf(pHlp, " Exclusion BAR = %#RX64\n", ExclRangeBar.u64);
5494 if (fVerbose)
5495 {
5496 pHlp->pfnPrintf(pHlp, " Exclusion enable = %RTbool\n", ExclRangeBar.n.u1ExclEnable);
5497 pHlp->pfnPrintf(pHlp, " Allow all devices = %RTbool\n", ExclRangeBar.n.u1AllowAll);
5498 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5499 ExclRangeBar.n.u40ExclRangeBase << X86_PAGE_4K_SHIFT);
5500 }
5501 }
5502 /* Exclusion Range Limit Register. */
5503 {
5504 IOMMU_EXCL_RANGE_LIMIT_T const ExclRangeLimit = pThis->ExclRangeLimit;
5505 pHlp->pfnPrintf(pHlp, " Exclusion Range Limit = %#RX64\n", ExclRangeLimit.u64);
5506 if (fVerbose)
5507 {
5508 pHlp->pfnPrintf(pHlp, " Range limit = %#RX64\n",
5509 (ExclRangeLimit.n.u40ExclRangeLimit << X86_PAGE_4K_SHIFT) | X86_PAGE_4K_OFFSET_MASK);
5510 }
5511 }
5512 /* Extended Feature Register. */
5513 {
5514 IOMMU_EXT_FEAT_T ExtFeat = pThis->ExtFeat;
5515 pHlp->pfnPrintf(pHlp, " Extended Feature Register = %#RX64\n", ExtFeat.u64);
5516 if (fVerbose)
5517 {
5518 pHlp->pfnPrintf(pHlp, " Prefetch support = %RTbool\n", ExtFeat.n.u1PrefetchSup);
5519 pHlp->pfnPrintf(pHlp, " PPR support = %RTbool\n", ExtFeat.n.u1PprSup);
5520 pHlp->pfnPrintf(pHlp, " x2APIC support = %RTbool\n", ExtFeat.n.u1X2ApicSup);
5521 pHlp->pfnPrintf(pHlp, " NX and privilege level support = %RTbool\n", ExtFeat.n.u1NoExecuteSup);
5522 pHlp->pfnPrintf(pHlp, " Guest translation support = %RTbool\n", ExtFeat.n.u1GstTranslateSup);
5523 pHlp->pfnPrintf(pHlp, " Invalidate-All command support = %RTbool\n", ExtFeat.n.u1InvAllSup);
5524 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC support = %RTbool\n", ExtFeat.n.u1GstVirtApicSup);
5525 pHlp->pfnPrintf(pHlp, " Hardware error register support = %RTbool\n", ExtFeat.n.u1HwErrorSup);
5526 pHlp->pfnPrintf(pHlp, " Performance counters support = %RTbool\n", ExtFeat.n.u1PerfCounterSup);
5527 pHlp->pfnPrintf(pHlp, " Host address translation size = %#x\n", ExtFeat.n.u2HostAddrTranslateSize);
5528 pHlp->pfnPrintf(pHlp, " Guest address translation size = %#x\n", ExtFeat.n.u2GstAddrTranslateSize);
5529 pHlp->pfnPrintf(pHlp, " Guest CR3 root table level support = %#x\n", ExtFeat.n.u2GstCr3RootTblLevel);
5530 pHlp->pfnPrintf(pHlp, " SMI filter register support = %#x\n", ExtFeat.n.u2SmiFilterSup);
5531 pHlp->pfnPrintf(pHlp, " SMI filter register count = %#x\n", ExtFeat.n.u3SmiFilterCount);
5532 pHlp->pfnPrintf(pHlp, " Guest virtual-APIC modes support = %#x\n", ExtFeat.n.u3GstVirtApicModeSup);
5533 pHlp->pfnPrintf(pHlp, " Dual PPR log support = %#x\n", ExtFeat.n.u2DualPprLogSup);
5534 pHlp->pfnPrintf(pHlp, " Dual event log support = %#x\n", ExtFeat.n.u2DualEvtLogSup);
5535 pHlp->pfnPrintf(pHlp, " Maximum PASID = %#x\n", ExtFeat.n.u5MaxPasidSup);
5536 pHlp->pfnPrintf(pHlp, " User/supervisor page protection support = %RTbool\n", ExtFeat.n.u1UserSupervisorSup);
5537 pHlp->pfnPrintf(pHlp, " Device table segments supported = %#x (%u)\n", ExtFeat.n.u2DevTabSegSup,
5538 g_acDevTabSegs[ExtFeat.n.u2DevTabSegSup]);
5539 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning support = %RTbool\n", ExtFeat.n.u1PprLogOverflowWarn);
5540 pHlp->pfnPrintf(pHlp, " PPR auto response support = %RTbool\n", ExtFeat.n.u1PprAutoRespSup);
5541 pHlp->pfnPrintf(pHlp, " MARC support = %#x\n", ExtFeat.n.u2MarcSup);
5542 pHlp->pfnPrintf(pHlp, " Block StopMark message support = %RTbool\n", ExtFeat.n.u1BlockStopMarkSup);
5543 pHlp->pfnPrintf(pHlp, " Performance optimization support = %RTbool\n", ExtFeat.n.u1PerfOptSup);
5544 pHlp->pfnPrintf(pHlp, " MSI capability MMIO access support = %RTbool\n", ExtFeat.n.u1MsiCapMmioSup);
5545 pHlp->pfnPrintf(pHlp, " Guest I/O protection support = %RTbool\n", ExtFeat.n.u1GstIoSup);
5546 pHlp->pfnPrintf(pHlp, " Host access support = %RTbool\n", ExtFeat.n.u1HostAccessSup);
5547 pHlp->pfnPrintf(pHlp, " Enhanced PPR handling support = %RTbool\n", ExtFeat.n.u1EnhancedPprSup);
5548 pHlp->pfnPrintf(pHlp, " Attribute forward supported = %RTbool\n", ExtFeat.n.u1AttrForwardSup);
5549 pHlp->pfnPrintf(pHlp, " Host dirty support = %RTbool\n", ExtFeat.n.u1HostDirtySup);
5550 pHlp->pfnPrintf(pHlp, " Invalidate IOTLB type support = %RTbool\n", ExtFeat.n.u1InvIoTlbTypeSup);
5551 pHlp->pfnPrintf(pHlp, " Guest page table access bit hw disable = %RTbool\n", ExtFeat.n.u1GstUpdateDisSup);
5552 pHlp->pfnPrintf(pHlp, " Force physical dest for remapped intr. = %RTbool\n", ExtFeat.n.u1ForcePhysDstSup);
5553 }
5554 }
5555 /* PPR Log Base Address Register. */
5556 {
5557 PPR_LOG_BAR_T PprLogBar = pThis->PprLogBaseAddr;
5558 uint8_t const uEncodedLen = PprLogBar.n.u4Len;
5559 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5560 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5561 pHlp->pfnPrintf(pHlp, " PPR Log BAR = %#RX64\n", PprLogBar.u64);
5562 if (fVerbose)
5563 {
5564 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5565 PprLogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5566 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5567 cEntries, cbBuffer);
5568 }
5569 }
5570 /* Hardware Event (Hi) Register. */
5571 {
5572 IOMMU_HW_EVT_HI_T HwEvtHi = pThis->HwEvtHi;
5573 pHlp->pfnPrintf(pHlp, " Hardware Event (Hi) = %#RX64\n", HwEvtHi.u64);
5574 if (fVerbose)
5575 {
5576 pHlp->pfnPrintf(pHlp, " First operand = %#RX64\n", HwEvtHi.n.u60FirstOperand);
5577 pHlp->pfnPrintf(pHlp, " Event code = %#RX8\n", HwEvtHi.n.u4EvtCode);
5578 }
5579 }
5580 /* Hardware Event (Lo) Register. */
5581 pHlp->pfnPrintf(pHlp, " Hardware Event (Lo) = %#RX64\n", pThis->HwEvtLo);
5582 /* Hardware Event Status. */
5583 {
5584 IOMMU_HW_EVT_STATUS_T HwEvtStatus = pThis->HwEvtStatus;
5585 pHlp->pfnPrintf(pHlp, " Hardware Event Status = %#RX64\n", HwEvtStatus.u64);
5586 if (fVerbose)
5587 {
5588 pHlp->pfnPrintf(pHlp, " Valid = %RTbool\n", HwEvtStatus.n.u1Valid);
5589 pHlp->pfnPrintf(pHlp, " Overflow = %RTbool\n", HwEvtStatus.n.u1Overflow);
5590 }
5591 }
5592 /* Guest Virtual-APIC Log Base Address Register. */
5593 {
5594 GALOG_BAR_T const GALogBar = pThis->GALogBaseAddr;
5595 uint8_t const uEncodedLen = GALogBar.n.u4Len;
5596 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5597 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5598 pHlp->pfnPrintf(pHlp, " Guest Log BAR = %#RX64\n", GALogBar.u64);
5599 if (fVerbose)
5600 {
5601 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5602 GALogBar.n.u40Base << X86_PAGE_4K_SHIFT);
5603 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5604 cEntries, cbBuffer);
5605 }
5606 }
5607 /* Guest Virtual-APIC Log Tail Address Register. */
5608 {
5609 GALOG_TAIL_ADDR_T GALogTail = pThis->GALogTailAddr;
5610 pHlp->pfnPrintf(pHlp, " Guest Log Tail Address = %#RX64\n", GALogTail.u64);
5611 if (fVerbose)
5612 pHlp->pfnPrintf(pHlp, " Tail address = %#RX64\n", GALogTail.n.u40GALogTailAddr);
5613 }
5614 /* PPR Log B Base Address Register. */
5615 {
5616 PPR_LOG_B_BAR_T PprLogBBar = pThis->PprLogBBaseAddr;
5617 uint8_t const uEncodedLen = PprLogBBar.n.u4Len;
5618 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5619 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5620 pHlp->pfnPrintf(pHlp, " PPR Log B BAR = %#RX64\n", PprLogBBar.u64);
5621 if (fVerbose)
5622 {
5623 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5624 PprLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5625 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5626 cEntries, cbBuffer);
5627 }
5628 }
5629 /* Event Log B Base Address Register. */
5630 {
5631 EVT_LOG_B_BAR_T EvtLogBBar = pThis->EvtLogBBaseAddr;
5632 uint8_t const uEncodedLen = EvtLogBBar.n.u4Len;
5633 uint32_t const cEntries = iommuAmdGetBufMaxEntries(uEncodedLen);
5634 uint32_t const cbBuffer = iommuAmdGetTotalBufLength(uEncodedLen);
5635 pHlp->pfnPrintf(pHlp, " Event Log B BAR = %#RX64\n", EvtLogBBar.u64);
5636 if (fVerbose)
5637 {
5638 pHlp->pfnPrintf(pHlp, " Base address = %#RX64\n",
5639 EvtLogBBar.n.u40Base << X86_PAGE_4K_SHIFT);
5640 pHlp->pfnPrintf(pHlp, " Length = %u (%u entries, %u bytes)\n", uEncodedLen,
5641 cEntries, cbBuffer);
5642 }
5643 }
5644 /* Device-Specific Feature Extension Register. */
5645 {
5646 DEV_SPECIFIC_FEAT_T const DevSpecificFeat = pThis->DevSpecificFeat;
5647 pHlp->pfnPrintf(pHlp, " Device-specific Feature = %#RX64\n", DevSpecificFeat.u64);
5648 if (fVerbose)
5649 {
5650 pHlp->pfnPrintf(pHlp, " Feature = %#RX32\n", DevSpecificFeat.n.u24DevSpecFeat);
5651 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificFeat.n.u4RevMinor);
5652 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificFeat.n.u4RevMajor);
5653 }
5654 }
5655 /* Device-Specific Control Extension Register. */
5656 {
5657 DEV_SPECIFIC_CTRL_T const DevSpecificCtrl = pThis->DevSpecificCtrl;
5658 pHlp->pfnPrintf(pHlp, " Device-specific Control = %#RX64\n", DevSpecificCtrl.u64);
5659 if (fVerbose)
5660 {
5661 pHlp->pfnPrintf(pHlp, " Control = %#RX32\n", DevSpecificCtrl.n.u24DevSpecCtrl);
5662 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificCtrl.n.u4RevMinor);
5663 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificCtrl.n.u4RevMajor);
5664 }
5665 }
5666 /* Device-Specific Status Extension Register. */
5667 {
5668 DEV_SPECIFIC_STATUS_T const DevSpecificStatus = pThis->DevSpecificStatus;
5669 pHlp->pfnPrintf(pHlp, " Device-specific Status = %#RX64\n", DevSpecificStatus.u64);
5670 if (fVerbose)
5671 {
5672 pHlp->pfnPrintf(pHlp, " Status = %#RX32\n", DevSpecificStatus.n.u24DevSpecStatus);
5673 pHlp->pfnPrintf(pHlp, " Minor revision ID = %#x\n", DevSpecificStatus.n.u4RevMinor);
5674 pHlp->pfnPrintf(pHlp, " Major revision ID = %#x\n", DevSpecificStatus.n.u4RevMajor);
5675 }
5676 }
5677 /* Miscellaneous Information Register (Lo and Hi). */
5678 {
5679 MSI_MISC_INFO_T const MiscInfo = pThis->MiscInfo;
5680 pHlp->pfnPrintf(pHlp, " Misc. Info. Register = %#RX64\n", MiscInfo.u64);
5681 if (fVerbose)
5682 {
5683 pHlp->pfnPrintf(pHlp, " Event Log MSI number = %#x\n", MiscInfo.n.u5MsiNumEvtLog);
5684 pHlp->pfnPrintf(pHlp, " Guest Virtual-Address Size = %#x\n", MiscInfo.n.u3GstVirtAddrSize);
5685 pHlp->pfnPrintf(pHlp, " Physical Address Size = %#x\n", MiscInfo.n.u7PhysAddrSize);
5686 pHlp->pfnPrintf(pHlp, " Virtual-Address Size = %#x\n", MiscInfo.n.u7VirtAddrSize);
5687 pHlp->pfnPrintf(pHlp, " HT Transport ATS Range Reserved = %RTbool\n", MiscInfo.n.u1HtAtsResv);
5688 pHlp->pfnPrintf(pHlp, " PPR MSI number = %#x\n", MiscInfo.n.u5MsiNumPpr);
5689 pHlp->pfnPrintf(pHlp, " GA Log MSI number = %#x\n", MiscInfo.n.u5MsiNumGa);
5690 }
5691 }
5692 /* MSI Capability Header. */
5693 {
5694 MSI_CAP_HDR_T MsiCapHdr;
5695 MsiCapHdr.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_CAP_HDR);
5696 pHlp->pfnPrintf(pHlp, " MSI Capability Header = %#RX32\n", MsiCapHdr.u32);
5697 if (fVerbose)
5698 {
5699 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiCapHdr.n.u8MsiCapId);
5700 pHlp->pfnPrintf(pHlp, " Capability Ptr (PCI config offset) = %#x\n", MsiCapHdr.n.u8MsiCapPtr);
5701 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", MsiCapHdr.n.u1MsiEnable);
5702 pHlp->pfnPrintf(pHlp, " Multi-message capability = %#x\n", MsiCapHdr.n.u3MsiMultiMessCap);
5703 pHlp->pfnPrintf(pHlp, " Multi-message enable = %#x\n", MsiCapHdr.n.u3MsiMultiMessEn);
5704 }
5705 }
5706 /* MSI Address Register (Lo and Hi). */
5707 {
5708 uint32_t const uMsiAddrLo = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO);
5709 uint32_t const uMsiAddrHi = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI);
5710 MSIADDR MsiAddr;
5711 MsiAddr.u64 = RT_MAKE_U64(uMsiAddrLo, uMsiAddrHi);
5712 pHlp->pfnPrintf(pHlp, " MSI Address = %#RX64\n", MsiAddr.u64);
5713 if (fVerbose)
5714 {
5715 pHlp->pfnPrintf(pHlp, " Destination mode = %#x\n", MsiAddr.n.u1DestMode);
5716 pHlp->pfnPrintf(pHlp, " Redirection hint = %#x\n", MsiAddr.n.u1RedirHint);
5717 pHlp->pfnPrintf(pHlp, " Destination Id = %#x\n", MsiAddr.n.u8DestId);
5718 pHlp->pfnPrintf(pHlp, " Address = %#RX32\n", MsiAddr.n.u12Addr);
5719 pHlp->pfnPrintf(pHlp, " Address (Hi) / Rsvd? = %#RX32\n", MsiAddr.n.u32Rsvd0);
5720 }
5721 }
5722 /* MSI Data. */
5723 {
5724 MSIDATA MsiData;
5725 MsiData.u32 = PDMPciDevGetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA);
5726 pHlp->pfnPrintf(pHlp, " MSI Data = %#RX32\n", MsiData.u32);
5727 if (fVerbose)
5728 {
5729 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", MsiData.n.u8Vector,
5730 MsiData.n.u8Vector);
5731 pHlp->pfnPrintf(pHlp, " Delivery mode = %#x\n", MsiData.n.u3DeliveryMode);
5732 pHlp->pfnPrintf(pHlp, " Level = %#x\n", MsiData.n.u1Level);
5733 pHlp->pfnPrintf(pHlp, " Trigger mode = %s\n", MsiData.n.u1TriggerMode ?
5734 "level" : "edge");
5735 }
5736 }
5737 /* MSI Mapping Capability Header (HyperTransport, reporting all 0s currently). */
5738 {
5739 MSI_MAP_CAP_HDR_T MsiMapCapHdr;
5740 MsiMapCapHdr.u32 = 0;
5741 pHlp->pfnPrintf(pHlp, " MSI Mapping Capability Header = %#RX32\n", MsiMapCapHdr.u32);
5742 if (fVerbose)
5743 {
5744 pHlp->pfnPrintf(pHlp, " Capability ID = %#x\n", MsiMapCapHdr.n.u8MsiMapCapId);
5745 pHlp->pfnPrintf(pHlp, " Map enable = %RTbool\n", MsiMapCapHdr.n.u1MsiMapEn);
5746 pHlp->pfnPrintf(pHlp, " Map fixed = %RTbool\n", MsiMapCapHdr.n.u1MsiMapFixed);
5747 pHlp->pfnPrintf(pHlp, " Map capability type = %#x\n", MsiMapCapHdr.n.u5MapCapType);
5748 }
5749 }
5750 /* Performance Optimization Control Register. */
5751 {
5752 IOMMU_PERF_OPT_CTRL_T const PerfOptCtrl = pThis->PerfOptCtrl;
5753 pHlp->pfnPrintf(pHlp, " Performance Optimization Control = %#RX32\n", PerfOptCtrl.u32);
5754 if (fVerbose)
5755 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PerfOptCtrl.n.u1PerfOptEn);
5756 }
5757 /* XT (x2APIC) General Interrupt Control Register. */
5758 {
5759 IOMMU_XT_GEN_INTR_CTRL_T const XtGenIntrCtrl = pThis->XtGenIntrCtrl;
5760 pHlp->pfnPrintf(pHlp, " XT General Interrupt Control = %#RX64\n", XtGenIntrCtrl.u64);
5761 if (fVerbose)
5762 {
5763 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5764 !XtGenIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5765 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5766 RT_MAKE_U64(XtGenIntrCtrl.n.u24X2ApicIntrDstLo, XtGenIntrCtrl.n.u7X2ApicIntrDstHi));
5767 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGenIntrCtrl.n.u8X2ApicIntrVector);
5768 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5769 !XtGenIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5770 }
5771 }
5772 /* XT (x2APIC) PPR Interrupt Control Register. */
5773 {
5774 IOMMU_XT_PPR_INTR_CTRL_T const XtPprIntrCtrl = pThis->XtPprIntrCtrl;
5775 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtPprIntrCtrl.u64);
5776 if (fVerbose)
5777 {
5778 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5779 !XtPprIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5780 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5781 RT_MAKE_U64(XtPprIntrCtrl.n.u24X2ApicIntrDstLo, XtPprIntrCtrl.n.u7X2ApicIntrDstHi));
5782 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtPprIntrCtrl.n.u8X2ApicIntrVector);
5783 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5784 !XtPprIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5785 }
5786 }
5787 /* XT (X2APIC) GA Log Interrupt Control Register. */
5788 {
5789 IOMMU_XT_GALOG_INTR_CTRL_T const XtGALogIntrCtrl = pThis->XtGALogIntrCtrl;
5790 pHlp->pfnPrintf(pHlp, " XT PPR Interrupt Control = %#RX64\n", XtGALogIntrCtrl.u64);
5791 if (fVerbose)
5792 {
5793 pHlp->pfnPrintf(pHlp, " Interrupt destination mode = %s\n",
5794 !XtGALogIntrCtrl.n.u1X2ApicIntrDstMode ? "physical" : "logical");
5795 pHlp->pfnPrintf(pHlp, " Interrupt destination = %#RX64\n",
5796 RT_MAKE_U64(XtGALogIntrCtrl.n.u24X2ApicIntrDstLo, XtGALogIntrCtrl.n.u7X2ApicIntrDstHi));
5797 pHlp->pfnPrintf(pHlp, " Interrupt vector = %#x\n", XtGALogIntrCtrl.n.u8X2ApicIntrVector);
5798 pHlp->pfnPrintf(pHlp, " Interrupt delivery mode = %s\n",
5799 !XtGALogIntrCtrl.n.u8X2ApicIntrVector ? "fixed" : "arbitrated");
5800 }
5801 }
5802 /* MARC Registers. */
5803 {
5804 for (unsigned i = 0; i < RT_ELEMENTS(pThis->aMarcApers); i++)
5805 {
5806 pHlp->pfnPrintf(pHlp, " MARC Aperature %u:\n", i);
5807 MARC_APER_BAR_T const MarcAperBar = pThis->aMarcApers[i].Base;
5808 pHlp->pfnPrintf(pHlp, " Base = %#RX64\n", MarcAperBar.n.u40MarcBaseAddr << X86_PAGE_4K_SHIFT);
5809
5810 MARC_APER_RELOC_T const MarcAperReloc = pThis->aMarcApers[i].Reloc;
5811 pHlp->pfnPrintf(pHlp, " Reloc = %#RX64 (addr: %#RX64, read-only: %RTbool, enable: %RTbool)\n",
5812 MarcAperReloc.u64, MarcAperReloc.n.u40MarcRelocAddr << X86_PAGE_4K_SHIFT,
5813 MarcAperReloc.n.u1ReadOnly, MarcAperReloc.n.u1RelocEn);
5814
5815 MARC_APER_LEN_T const MarcAperLen = pThis->aMarcApers[i].Length;
5816 pHlp->pfnPrintf(pHlp, " Length = %u pages\n", MarcAperLen.n.u40MarcLength);
5817 }
5818 }
5819 /* Reserved Register. */
5820 pHlp->pfnPrintf(pHlp, " Reserved Register = %#RX64\n", pThis->RsvdReg);
5821 /* Command Buffer Head Pointer Register. */
5822 {
5823 CMD_BUF_HEAD_PTR_T const CmdBufHeadPtr = pThis->CmdBufHeadPtr;
5824 pHlp->pfnPrintf(pHlp, " Command Buffer Head Pointer = %#RX64 (off: %#x)\n", CmdBufHeadPtr.u64,
5825 CmdBufHeadPtr.n.off);
5826 }
5827 /* Command Buffer Tail Pointer Register. */
5828 {
5829 CMD_BUF_HEAD_PTR_T const CmdBufTailPtr = pThis->CmdBufTailPtr;
5830 pHlp->pfnPrintf(pHlp, " Command Buffer Tail Pointer = %#RX64 (off: %#x)\n", CmdBufTailPtr.u64,
5831 CmdBufTailPtr.n.off);
5832 }
5833 /* Event Log Head Pointer Register. */
5834 {
5835 EVT_LOG_HEAD_PTR_T const EvtLogHeadPtr = pThis->EvtLogHeadPtr;
5836 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogHeadPtr.u64,
5837 EvtLogHeadPtr.n.off);
5838 }
5839 /* Event Log Tail Pointer Register. */
5840 {
5841 EVT_LOG_TAIL_PTR_T const EvtLogTailPtr = pThis->EvtLogTailPtr;
5842 pHlp->pfnPrintf(pHlp, " Event Log Head Pointer = %#RX64 (off: %#x)\n", EvtLogTailPtr.u64,
5843 EvtLogTailPtr.n.off);
5844 }
5845 /* Status Register. */
5846 {
5847 IOMMU_STATUS_T const Status = pThis->Status;
5848 pHlp->pfnPrintf(pHlp, " Status Register = %#RX64\n", Status.u64);
5849 if (fVerbose)
5850 {
5851 pHlp->pfnPrintf(pHlp, " Event log overflow = %RTbool\n", Status.n.u1EvtOverflow);
5852 pHlp->pfnPrintf(pHlp, " Event log interrupt = %RTbool\n", Status.n.u1EvtLogIntr);
5853 pHlp->pfnPrintf(pHlp, " Completion wait interrupt = %RTbool\n", Status.n.u1CompWaitIntr);
5854 pHlp->pfnPrintf(pHlp, " Event log running = %RTbool\n", Status.n.u1EvtLogRunning);
5855 pHlp->pfnPrintf(pHlp, " Command buffer running = %RTbool\n", Status.n.u1CmdBufRunning);
5856 pHlp->pfnPrintf(pHlp, " PPR overflow = %RTbool\n", Status.n.u1PprOverflow);
5857 pHlp->pfnPrintf(pHlp, " PPR interrupt = %RTbool\n", Status.n.u1PprIntr);
5858 pHlp->pfnPrintf(pHlp, " PPR log running = %RTbool\n", Status.n.u1PprLogRunning);
5859 pHlp->pfnPrintf(pHlp, " Guest log running = %RTbool\n", Status.n.u1GstLogRunning);
5860 pHlp->pfnPrintf(pHlp, " Guest log interrupt = %RTbool\n", Status.n.u1GstLogIntr);
5861 pHlp->pfnPrintf(pHlp, " PPR log B overflow = %RTbool\n", Status.n.u1PprOverflowB);
5862 pHlp->pfnPrintf(pHlp, " PPR log active = %RTbool\n", Status.n.u1PprLogActive);
5863 pHlp->pfnPrintf(pHlp, " Event log B overflow = %RTbool\n", Status.n.u1EvtOverflowB);
5864 pHlp->pfnPrintf(pHlp, " Event log active = %RTbool\n", Status.n.u1EvtLogActive);
5865 pHlp->pfnPrintf(pHlp, " PPR log B overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarlyB);
5866 pHlp->pfnPrintf(pHlp, " PPR log overflow early warning = %RTbool\n", Status.n.u1PprOverflowEarly);
5867 }
5868 }
5869 /* PPR Log Head Pointer. */
5870 {
5871 PPR_LOG_HEAD_PTR_T const PprLogHeadPtr = pThis->PprLogHeadPtr;
5872 pHlp->pfnPrintf(pHlp, " PPR Log Head Pointer = %#RX64 (off: %#x)\n", PprLogHeadPtr.u64,
5873 PprLogHeadPtr.n.off);
5874 }
5875 /* PPR Log Tail Pointer. */
5876 {
5877 PPR_LOG_TAIL_PTR_T const PprLogTailPtr = pThis->PprLogTailPtr;
5878 pHlp->pfnPrintf(pHlp, " PPR Log Tail Pointer = %#RX64 (off: %#x)\n", PprLogTailPtr.u64,
5879 PprLogTailPtr.n.off);
5880 }
5881 /* Guest Virtual-APIC Log Head Pointer. */
5882 {
5883 GALOG_HEAD_PTR_T const GALogHeadPtr = pThis->GALogHeadPtr;
5884 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Head Pointer = %#RX64 (off: %#x)\n", GALogHeadPtr.u64,
5885 GALogHeadPtr.n.u12GALogPtr);
5886 }
5887 /* Guest Virtual-APIC Log Tail Pointer. */
5888 {
5889 GALOG_HEAD_PTR_T const GALogTailPtr = pThis->GALogTailPtr;
5890 pHlp->pfnPrintf(pHlp, " Guest Virtual-APIC Log Tail Pointer = %#RX64 (off: %#x)\n", GALogTailPtr.u64,
5891 GALogTailPtr.n.u12GALogPtr);
5892 }
5893 /* PPR Log B Head Pointer. */
5894 {
5895 PPR_LOG_B_HEAD_PTR_T const PprLogBHeadPtr = pThis->PprLogBHeadPtr;
5896 pHlp->pfnPrintf(pHlp, " PPR Log B Head Pointer = %#RX64 (off: %#x)\n", PprLogBHeadPtr.u64,
5897 PprLogBHeadPtr.n.off);
5898 }
5899 /* PPR Log B Tail Pointer. */
5900 {
5901 PPR_LOG_B_TAIL_PTR_T const PprLogBTailPtr = pThis->PprLogBTailPtr;
5902 pHlp->pfnPrintf(pHlp, " PPR Log B Tail Pointer = %#RX64 (off: %#x)\n", PprLogBTailPtr.u64,
5903 PprLogBTailPtr.n.off);
5904 }
5905 /* Event Log B Head Pointer. */
5906 {
5907 EVT_LOG_B_HEAD_PTR_T const EvtLogBHeadPtr = pThis->EvtLogBHeadPtr;
5908 pHlp->pfnPrintf(pHlp, " Event Log B Head Pointer = %#RX64 (off: %#x)\n", EvtLogBHeadPtr.u64,
5909 EvtLogBHeadPtr.n.off);
5910 }
5911 /* Event Log B Tail Pointer. */
5912 {
5913 EVT_LOG_B_TAIL_PTR_T const EvtLogBTailPtr = pThis->EvtLogBTailPtr;
5914 pHlp->pfnPrintf(pHlp, " Event Log B Tail Pointer = %#RX64 (off: %#x)\n", EvtLogBTailPtr.u64,
5915 EvtLogBTailPtr.n.off);
5916 }
5917 /* PPR Log Auto Response Register. */
5918 {
5919 PPR_LOG_AUTO_RESP_T const PprLogAutoResp = pThis->PprLogAutoResp;
5920 pHlp->pfnPrintf(pHlp, " PPR Log Auto Response Register = %#RX64\n", PprLogAutoResp.u64);
5921 if (fVerbose)
5922 {
5923 pHlp->pfnPrintf(pHlp, " Code = %#x\n", PprLogAutoResp.n.u4AutoRespCode);
5924 pHlp->pfnPrintf(pHlp, " Mask Gen. = %RTbool\n", PprLogAutoResp.n.u1AutoRespMaskGen);
5925 }
5926 }
5927 /* PPR Log Overflow Early Warning Indicator Register. */
5928 {
5929 PPR_LOG_OVERFLOW_EARLY_T const PprLogOverflowEarly = pThis->PprLogOverflowEarly;
5930 pHlp->pfnPrintf(pHlp, " PPR Log overflow early warning = %#RX64\n", PprLogOverflowEarly.u64);
5931 if (fVerbose)
5932 {
5933 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogOverflowEarly.n.u15Threshold);
5934 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogOverflowEarly.n.u1IntrEn);
5935 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogOverflowEarly.n.u1Enable);
5936 }
5937 }
5938 /* PPR Log Overflow Early Warning Indicator Register. */
5939 {
5940 PPR_LOG_OVERFLOW_EARLY_T const PprLogBOverflowEarly = pThis->PprLogBOverflowEarly;
5941 pHlp->pfnPrintf(pHlp, " PPR Log B overflow early warning = %#RX64\n", PprLogBOverflowEarly.u64);
5942 if (fVerbose)
5943 {
5944 pHlp->pfnPrintf(pHlp, " Threshold = %#x\n", PprLogBOverflowEarly.n.u15Threshold);
5945 pHlp->pfnPrintf(pHlp, " Interrupt enable = %RTbool\n", PprLogBOverflowEarly.n.u1IntrEn);
5946 pHlp->pfnPrintf(pHlp, " Enable = %RTbool\n", PprLogBOverflowEarly.n.u1Enable);
5947 }
5948 }
5949}
5950
5951
5952/**
5953 * Dumps the DTE via the info callback helper.
5954 *
5955 * @param pHlp The info helper.
5956 * @param pDte The device table entry.
5957 * @param pszPrefix The string prefix.
5958 */
5959static void iommuAmdR3DbgInfoDteWorker(PCDBGFINFOHLP pHlp, PCDTE_T pDte, const char *pszPrefix)
5960{
5961 AssertReturnVoid(pHlp);
5962 AssertReturnVoid(pDte);
5963 AssertReturnVoid(pszPrefix);
5964
5965 pHlp->pfnPrintf(pHlp, "%sValid = %RTbool\n", pszPrefix, pDte->n.u1Valid);
5966 pHlp->pfnPrintf(pHlp, "%sTranslation Valid = %RTbool\n", pszPrefix, pDte->n.u1TranslationValid);
5967 pHlp->pfnPrintf(pHlp, "%sHost Access Dirty = %#x\n", pszPrefix, pDte->n.u2Had);
5968 pHlp->pfnPrintf(pHlp, "%sPaging Mode = %u\n", pszPrefix, pDte->n.u3Mode);
5969 pHlp->pfnPrintf(pHlp, "%sPage Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix, pDte->n.u40PageTableRootPtrLo,
5970 pDte->n.u40PageTableRootPtrLo << 12);
5971 pHlp->pfnPrintf(pHlp, "%sPPR enable = %RTbool\n", pszPrefix, pDte->n.u1Ppr);
5972 pHlp->pfnPrintf(pHlp, "%sGuest PPR Resp w/ PASID = %RTbool\n", pszPrefix, pDte->n.u1GstPprRespPasid);
5973 pHlp->pfnPrintf(pHlp, "%sGuest I/O Prot Valid = %RTbool\n", pszPrefix, pDte->n.u1GstIoValid);
5974 pHlp->pfnPrintf(pHlp, "%sGuest Translation Valid = %RTbool\n", pszPrefix, pDte->n.u1GstTranslateValid);
5975 pHlp->pfnPrintf(pHlp, "%sGuest Levels Translated = %#x\n", pszPrefix, pDte->n.u2GstMode);
5976 pHlp->pfnPrintf(pHlp, "%sGuest Root Page Table Ptr = %#x %#x %#x (addr=%#RGp)\n", pszPrefix,
5977 pDte->n.u3GstCr3TableRootPtrLo, pDte->n.u16GstCr3TableRootPtrMid, pDte->n.u21GstCr3TableRootPtrHi,
5978 (pDte->n.u21GstCr3TableRootPtrHi << 31)
5979 | (pDte->n.u16GstCr3TableRootPtrMid << 15)
5980 | (pDte->n.u3GstCr3TableRootPtrLo << 12));
5981 pHlp->pfnPrintf(pHlp, "%sI/O Read = %s\n", pszPrefix, pDte->n.u1IoRead ? "allowed" : "denied");
5982 pHlp->pfnPrintf(pHlp, "%sI/O Write = %s\n", pszPrefix, pDte->n.u1IoWrite ? "allowed" : "denied");
5983 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd0);
5984 pHlp->pfnPrintf(pHlp, "%sDomain ID = %u (%#x)\n", pszPrefix, pDte->n.u16DomainId, pDte->n.u16DomainId);
5985 pHlp->pfnPrintf(pHlp, "%sIOTLB Enable = %RTbool\n", pszPrefix, pDte->n.u1IoTlbEnable);
5986 pHlp->pfnPrintf(pHlp, "%sSuppress I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressPfEvents);
5987 pHlp->pfnPrintf(pHlp, "%sSuppress all I/O PFs = %RTbool\n", pszPrefix, pDte->n.u1SuppressAllPfEvents);
5988 pHlp->pfnPrintf(pHlp, "%sPort I/O Control = %#x\n", pszPrefix, pDte->n.u2IoCtl);
5989 pHlp->pfnPrintf(pHlp, "%sIOTLB Cache Hint = %s\n", pszPrefix, pDte->n.u1Cache ? "no caching" : "cache");
5990 pHlp->pfnPrintf(pHlp, "%sSnoop Disable = %RTbool\n", pszPrefix, pDte->n.u1SnoopDisable);
5991 pHlp->pfnPrintf(pHlp, "%sAllow Exclusion = %RTbool\n", pszPrefix, pDte->n.u1AllowExclusion);
5992 pHlp->pfnPrintf(pHlp, "%sSysMgt Message Enable = %RTbool\n", pszPrefix, pDte->n.u2SysMgt);
5993 pHlp->pfnPrintf(pHlp, "%sInterrupt Map Valid = %RTbool\n", pszPrefix, pDte->n.u1IntrMapValid);
5994 uint8_t const uIntrTabLen = pDte->n.u4IntrTableLength;
5995 if (uIntrTabLen < IOMMU_DTE_INTR_TAB_LEN_MAX)
5996 {
5997 uint16_t const cEntries = IOMMU_DTE_GET_INTR_TAB_ENTRIES(pDte);
5998 uint16_t const cbIntrTable = IOMMU_DTE_GET_INTR_TAB_LEN(pDte);
5999 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (%u entries, %u bytes)\n", pszPrefix, uIntrTabLen, cEntries,
6000 cbIntrTable);
6001 }
6002 else
6003 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Length = %#x (invalid!)\n", pszPrefix, uIntrTabLen);
6004 pHlp->pfnPrintf(pHlp, "%sIgnore Unmapped Interrupts = %RTbool\n", pszPrefix, pDte->n.u1IgnoreUnmappedIntrs);
6005 pHlp->pfnPrintf(pHlp, "%sInterrupt Table Root Ptr = %#RX64 (addr=%#RGp)\n", pszPrefix,
6006 pDte->n.u46IntrTableRootPtr, pDte->au64[2] & IOMMU_DTE_IRTE_ROOT_PTR_MASK);
6007 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u4Rsvd0);
6008 pHlp->pfnPrintf(pHlp, "%sINIT passthru = %RTbool\n", pszPrefix, pDte->n.u1InitPassthru);
6009 pHlp->pfnPrintf(pHlp, "%sExtInt passthru = %RTbool\n", pszPrefix, pDte->n.u1ExtIntPassthru);
6010 pHlp->pfnPrintf(pHlp, "%sNMI passthru = %RTbool\n", pszPrefix, pDte->n.u1NmiPassthru);
6011 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u1Rsvd2);
6012 pHlp->pfnPrintf(pHlp, "%sInterrupt Control = %#x\n", pszPrefix, pDte->n.u2IntrCtrl);
6013 pHlp->pfnPrintf(pHlp, "%sLINT0 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint0Passthru);
6014 pHlp->pfnPrintf(pHlp, "%sLINT1 passthru = %RTbool\n", pszPrefix, pDte->n.u1Lint1Passthru);
6015 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u32Rsvd0);
6016 pHlp->pfnPrintf(pHlp, "%sReserved (MBZ) = %#x\n", pszPrefix, pDte->n.u22Rsvd0);
6017 pHlp->pfnPrintf(pHlp, "%sAttribute Override Valid = %RTbool\n", pszPrefix, pDte->n.u1AttrOverride);
6018 pHlp->pfnPrintf(pHlp, "%sMode0FC = %#x\n", pszPrefix, pDte->n.u1Mode0FC);
6019 pHlp->pfnPrintf(pHlp, "%sSnoop Attribute = %#x\n", pszPrefix, pDte->n.u8SnoopAttr);
6020 pHlp->pfnPrintf(pHlp, "\n");
6021}
6022
6023
6024/**
6025 * @callback_method_impl{FNDBGFHANDLERDEV}
6026 */
6027static DECLCALLBACK(void) iommuAmdR3DbgInfoDte(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6028{
6029 if (pszArgs)
6030 {
6031 uint16_t idDevice = 0;
6032 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDevice);
6033 if (RT_SUCCESS(rc))
6034 {
6035 DTE_T Dte;
6036 rc = iommuAmdDteRead(pDevIns, idDevice, IOMMUOP_TRANSLATE_REQ, &Dte);
6037 if (RT_SUCCESS(rc))
6038 {
6039 pHlp->pfnPrintf(pHlp, "DTE for device %#x\n", idDevice);
6040 iommuAmdR3DbgInfoDteWorker(pHlp, &Dte, " ");
6041 return;
6042 }
6043 pHlp->pfnPrintf(pHlp, "Failed to read DTE for device ID %u (%#x). rc=%Rrc\n", idDevice, idDevice, rc);
6044 }
6045 else
6046 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit device ID. rc=%Rrc\n", rc);
6047 }
6048 else
6049 pHlp->pfnPrintf(pHlp, "Missing device ID.\n");
6050}
6051
6052
6053# ifdef IOMMU_WITH_DTE_CACHE
6054/**
6055 * @callback_method_impl{FNDBGFHANDLERDEV}
6056 */
6057static DECLCALLBACK(void) iommuAmdR3DbgInfoDteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6058{
6059 RT_NOREF(pszArgs);
6060 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6061 IOMMU_CACHE_LOCK(pDevIns, pThis);
6062
6063 uint16_t const cDteCache = RT_ELEMENTS(pThis->aDeviceIds);
6064 pHlp->pfnPrintf(pHlp, "DTE Cache: Capacity=%u entries\n", cDteCache);
6065 for (uint16_t i = 0; i < cDteCache; i++)
6066 {
6067 uint16_t const idDevice = pThis->aDeviceIds[i];
6068 if (idDevice)
6069 {
6070 pHlp->pfnPrintf(pHlp, " Entry[%u]: Device=%#x (BDF %02x:%02x.%d)\n", i, idDevice,
6071 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6072 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6073 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6074
6075 PCDTECACHE pDteCache = &pThis->aDteCache[i];
6076 pHlp->pfnPrintf(pHlp, " Flags = %#x\n", pDteCache->fFlags);
6077 pHlp->pfnPrintf(pHlp, " Domain Id = %u\n", pDteCache->idDomain);
6078 pHlp->pfnPrintf(pHlp, "\n");
6079 }
6080 }
6081 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6082}
6083# endif /* IOMMU_WITH_DTE_CACHE */
6084
6085
6086# ifdef IOMMU_WITH_IOTLBE_CACHE
6087/**
6088 * @callback_method_impl{FNDBGFHANDLERDEV}
6089 */
6090static DECLCALLBACK(void) iommuAmdR3DbgInfoIotlb(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6091{
6092 if (pszArgs)
6093 {
6094 uint16_t idDomain = 0;
6095 int rc = RTStrToUInt16Full(pszArgs, 0 /* uBase */, &idDomain);
6096 if (RT_SUCCESS(rc))
6097 {
6098 pHlp->pfnPrintf(pHlp, "IOTLBEs for domain %u (%#x):\n", idDomain, idDomain);
6099 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6100 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6101 IOTLBEINFOARG Args;
6102 Args.pIommuR3 = pThisR3;
6103 Args.pHlp = pHlp;
6104 Args.idDomain = idDomain;
6105
6106 IOMMU_CACHE_LOCK(pDevIns, pThis);
6107 RTAvlU64DoWithAll(&pThisR3->TreeIotlbe, true /* fFromLeft */, iommuAmdR3IotlbEntryInfo, &Args);
6108 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6109 }
6110 else
6111 pHlp->pfnPrintf(pHlp, "Failed to parse a valid 16-bit domain ID. rc=%Rrc\n", rc);
6112 }
6113 else
6114 pHlp->pfnPrintf(pHlp, "Missing domain ID.\n");
6115}
6116# endif /* IOMMU_WITH_IOTLBE_CACHE */
6117
6118
6119# ifdef IOMMU_WITH_IRTE_CACHE
6120/**
6121 * Gets the interrupt type name for an interrupt type in the IRTE.
6122 *
6123 * @returns The interrupt type name.
6124 * @param uIntrType The interrupt type (as specified in the IRTE).
6125 */
6126static const char *iommuAmdIrteGetIntrTypeName(uint8_t uIntrType)
6127{
6128 switch (uIntrType)
6129 {
6130 case VBOX_MSI_DELIVERY_MODE_FIXED: return "Fixed";
6131 case VBOX_MSI_DELIVERY_MODE_LOWEST_PRIO: return "Arbitrated";
6132 default: return "<Reserved>";
6133 }
6134}
6135
6136
6137/**
6138 * @callback_method_impl{FNDBGFHANDLERDEV}
6139 */
6140static DECLCALLBACK(void) iommuAmdR3DbgInfoIrteCache(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6141{
6142 RT_NOREF(pszArgs);
6143
6144 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6145 IOMMU_CACHE_LOCK(pDevIns, pThis);
6146
6147 uint16_t const cIrteCache = RT_ELEMENTS(pThis->aIrteCache);
6148 pHlp->pfnPrintf(pHlp, "IRTE Cache: Capacity=%u entries\n", cIrteCache);
6149 for (uint16_t idxIrte = 0; idxIrte < cIrteCache; idxIrte++)
6150 {
6151 PCIRTECACHE pIrteCache = &pThis->aIrteCache[idxIrte];
6152 uint32_t const uKey = pIrteCache->uKey;
6153 if (uKey != IOMMU_IRTE_CACHE_KEY_NIL)
6154 {
6155 uint16_t const idDevice = IOMMU_IRTE_CACHE_KEY_GET_DEVICE_ID(uKey);
6156 uint16_t const offIrte = IOMMU_IRTE_CACHE_KEY_GET_OFF(uKey);
6157 pHlp->pfnPrintf(pHlp, " Entry[%u]: Offset=%#x Device=%#x (BDF %02x:%02x.%d)\n",
6158 idxIrte, offIrte, idDevice,
6159 (idDevice >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6160 (idDevice >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6161 idDevice & VBOX_PCI_DEVFN_FUN_MASK);
6162
6163 PCIRTE_T pIrte = &pIrteCache->Irte;
6164 pHlp->pfnPrintf(pHlp, " Remap Enable = %RTbool\n", pIrte->n.u1RemapEnable);
6165 pHlp->pfnPrintf(pHlp, " Suppress IOPF = %RTbool\n", pIrte->n.u1SuppressIoPf);
6166 pHlp->pfnPrintf(pHlp, " Interrupt Type = %#x (%s)\n", pIrte->n.u3IntrType,
6167 iommuAmdIrteGetIntrTypeName(pIrte->n.u3IntrType));
6168 pHlp->pfnPrintf(pHlp, " Request EOI = %RTbool\n", pIrte->n.u1ReqEoi);
6169 pHlp->pfnPrintf(pHlp, " Destination mode = %s\n", pIrte->n.u1DestMode ? "Logical" : "Physical");
6170 pHlp->pfnPrintf(pHlp, " Destination Id = %u\n", pIrte->n.u8Dest);
6171 pHlp->pfnPrintf(pHlp, " Vector = %#x (%u)\n", pIrte->n.u8Vector, pIrte->n.u8Vector);
6172 pHlp->pfnPrintf(pHlp, "\n");
6173 }
6174 }
6175 IOMMU_CACHE_UNLOCK(pDevIns, pThis);
6176}
6177# endif /* IOMMU_WITH_IRTE_CACHE */
6178
6179
6180/**
6181 * @callback_method_impl{FNDBGFHANDLERDEV}
6182 */
6183static DECLCALLBACK(void) iommuAmdR3DbgInfoDevTabs(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
6184{
6185 RT_NOREF(pszArgs);
6186
6187 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6188 PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6189 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6190 NOREF(pPciDev);
6191
6192 uint8_t cSegments = 0;
6193 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6194 {
6195 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6196 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6197 if (GCPhysDevTab)
6198 ++cSegments;
6199 }
6200
6201 pHlp->pfnPrintf(pHlp, "AMD-IOMMU device tables with address translations enabled:\n");
6202 pHlp->pfnPrintf(pHlp, " DTE Segments=%u\n", cSegments);
6203 if (!cSegments)
6204 return;
6205
6206 for (uint8_t i = 0; i < RT_ELEMENTS(pThis->aDevTabBaseAddrs); i++)
6207 {
6208 DEV_TAB_BAR_T const DevTabBar = pThis->aDevTabBaseAddrs[i];
6209 RTGCPHYS const GCPhysDevTab = DevTabBar.n.u40Base << X86_PAGE_4K_SHIFT;
6210 if (GCPhysDevTab)
6211 {
6212 uint32_t const cbDevTab = IOMMU_GET_DEV_TAB_LEN(&DevTabBar);
6213 uint32_t const cDtes = cbDevTab / sizeof(DTE_T);
6214
6215 void *pvDevTab = RTMemAllocZ(cbDevTab);
6216 if (RT_LIKELY(pvDevTab))
6217 {
6218 int rc = PDMDevHlpPCIPhysRead(pDevIns, GCPhysDevTab, pvDevTab, cbDevTab);
6219 if (RT_SUCCESS(rc))
6220 {
6221 for (uint32_t idxDte = 0; idxDte < cDtes; idxDte++)
6222 {
6223 PCDTE_T pDte = (PCDTE_T)((uintptr_t)pvDevTab + idxDte * sizeof(DTE_T));
6224 if ( pDte->n.u1Valid
6225 && pDte->n.u1TranslationValid
6226 && pDte->n.u3Mode != 0)
6227 {
6228 pHlp->pfnPrintf(pHlp, " DTE %u (BDF %02x:%02x.%d)\n", idxDte,
6229 (idxDte >> VBOX_PCI_BUS_SHIFT) & VBOX_PCI_BUS_MASK,
6230 (idxDte >> VBOX_PCI_DEVFN_DEV_SHIFT) & VBOX_PCI_DEVFN_DEV_MASK,
6231 idxDte & VBOX_PCI_DEVFN_FUN_MASK);
6232 iommuAmdR3DbgInfoDteWorker(pHlp, pDte, " ");
6233 pHlp->pfnPrintf(pHlp, "\n");
6234 }
6235 }
6236 pHlp->pfnPrintf(pHlp, "\n");
6237 }
6238 else
6239 {
6240 pHlp->pfnPrintf(pHlp, " Failed to read table at %#RGp of size %zu bytes. rc=%Rrc!\n", GCPhysDevTab,
6241 cbDevTab, rc);
6242 }
6243
6244 RTMemFree(pvDevTab);
6245 }
6246 else
6247 {
6248 pHlp->pfnPrintf(pHlp, " Allocating %zu bytes for reading the device table failed!\n", cbDevTab);
6249 return;
6250 }
6251 }
6252 }
6253}
6254
6255
6256/**
6257 * @callback_method_impl{FNSSMDEVSAVEEXEC}
6258 */
6259static DECLCALLBACK(int) iommuAmdR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6260{
6261 PCIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6262 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6263 LogFlowFunc(("\n"));
6264
6265 /* First, save ExtFeat and other registers that cannot be modified by the guest. */
6266 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64);
6267 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64);
6268 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64);
6269 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64);
6270 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64);
6271 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg);
6272
6273 /* Next, save all registers that can be modified by the guest. */
6274 pHlp->pfnSSMPutU64(pSSM, pThis->IommuBar.u64);
6275
6276 uint8_t const cDevTabBaseAddrs = RT_ELEMENTS(pThis->aDevTabBaseAddrs);
6277 pHlp->pfnSSMPutU8(pSSM, cDevTabBaseAddrs);
6278 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6279 pHlp->pfnSSMPutU64(pSSM, pThis->aDevTabBaseAddrs[i].u64);
6280
6281 AssertReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8, VERR_IOMMU_IPE_4);
6282 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufBaseAddr.u64);
6283 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBaseAddr.u64);
6284 pHlp->pfnSSMPutU64(pSSM, pThis->Ctrl.u64);
6285 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeBaseAddr.u64);
6286 pHlp->pfnSSMPutU64(pSSM, pThis->ExclRangeLimit.u64);
6287#if 0
6288 pHlp->pfnSSMPutU64(pSSM, pThis->ExtFeat.u64); /* read-only, done already (above). */
6289#endif
6290
6291 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBaseAddr.u64);
6292 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtHi.u64);
6293 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtLo);
6294 pHlp->pfnSSMPutU64(pSSM, pThis->HwEvtStatus.u64);
6295
6296 pHlp->pfnSSMPutU64(pSSM, pThis->GALogBaseAddr.u64);
6297 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailAddr.u64);
6298
6299 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBBaseAddr.u64);
6300 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBBaseAddr.u64);
6301
6302#if 0
6303 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6304 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6305 pHlp->pfnSSMPutU64(pSSM, pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6306
6307 pHlp->pfnSSMPutU64(pSSM, pThis->MiscInfo.u64); /* read-only, done already (above). */
6308#endif
6309 pHlp->pfnSSMPutU32(pSSM, pThis->PerfOptCtrl.u32);
6310
6311 pHlp->pfnSSMPutU64(pSSM, pThis->XtGenIntrCtrl.u64);
6312 pHlp->pfnSSMPutU64(pSSM, pThis->XtPprIntrCtrl.u64);
6313 pHlp->pfnSSMPutU64(pSSM, pThis->XtGALogIntrCtrl.u64);
6314
6315 size_t const cMarcApers = RT_ELEMENTS(pThis->aMarcApers);
6316 pHlp->pfnSSMPutU8(pSSM, cMarcApers);
6317 for (size_t i = 0; i < cMarcApers; i++)
6318 {
6319 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Base.u64);
6320 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Reloc.u64);
6321 pHlp->pfnSSMPutU64(pSSM, pThis->aMarcApers[i].Length.u64);
6322 }
6323
6324#if 0
6325 pHlp->pfnSSMPutU64(pSSM, pThis->RsvdReg); /* read-only, done already (above). */
6326#endif
6327
6328 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufHeadPtr.u64);
6329 pHlp->pfnSSMPutU64(pSSM, pThis->CmdBufTailPtr.u64);
6330 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogHeadPtr.u64);
6331 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogTailPtr.u64);
6332
6333 pHlp->pfnSSMPutU64(pSSM, pThis->Status.u64);
6334
6335 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogHeadPtr.u64);
6336 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogTailPtr.u64);
6337
6338 pHlp->pfnSSMPutU64(pSSM, pThis->GALogHeadPtr.u64);
6339 pHlp->pfnSSMPutU64(pSSM, pThis->GALogTailPtr.u64);
6340
6341 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBHeadPtr.u64);
6342 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBTailPtr.u64);
6343
6344 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBHeadPtr.u64);
6345 pHlp->pfnSSMPutU64(pSSM, pThis->EvtLogBTailPtr.u64);
6346
6347 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogAutoResp.u64);
6348 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogOverflowEarly.u64);
6349 pHlp->pfnSSMPutU64(pSSM, pThis->PprLogBOverflowEarly.u64);
6350
6351 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
6352}
6353
6354
6355/**
6356 * @callback_method_impl{FNSSMDEVLOADEXEC}
6357 */
6358static DECLCALLBACK(int) iommuAmdR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
6359{
6360 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6361 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6362 int const rcErr = VERR_SSM_UNEXPECTED_DATA;
6363 LogFlowFunc(("\n"));
6364
6365 /* Validate. */
6366 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
6367 if (uVersion != IOMMU_SAVED_STATE_VERSION)
6368 {
6369 LogRel(("%s: Invalid saved-state version %#x\n", IOMMU_LOG_PFX, uVersion));
6370 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
6371 }
6372
6373 /* Load ExtFeat and other read-only registers first. */
6374 int rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64);
6375 AssertRCReturn(rc, rc);
6376 AssertLogRelMsgReturn(pThis->ExtFeat.n.u2HostAddrTranslateSize < 0x3,
6377 ("ExtFeat.HATS register invalid %#RX64\n", pThis->ExtFeat.u64), rcErr);
6378 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64);
6379 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64);
6380 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64);
6381 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64);
6382 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg);
6383
6384 /* IOMMU base address register. */
6385 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->IommuBar.u64);
6386 AssertRCReturn(rc, rc);
6387 pThis->IommuBar.u64 &= IOMMU_BAR_VALID_MASK;
6388
6389 /* Device table base address registers. */
6390 uint8_t cDevTabBaseAddrs;
6391 rc = pHlp->pfnSSMGetU8(pSSM, &cDevTabBaseAddrs);
6392 AssertRCReturn(rc, rc);
6393 AssertLogRelMsgReturn(cDevTabBaseAddrs > 0 && cDevTabBaseAddrs <= RT_ELEMENTS(pThis->aDevTabBaseAddrs),
6394 ("Device table segment count invalid %#x\n", cDevTabBaseAddrs), rcErr);
6395 AssertCompile(RT_ELEMENTS(pThis->aDevTabBaseAddrs) == RT_ELEMENTS(g_auDevTabSegMaxSizes));
6396 for (uint8_t i = 0; i < cDevTabBaseAddrs; i++)
6397 {
6398 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aDevTabBaseAddrs[i].u64);
6399 AssertRCReturn(rc, rc);
6400 pThis->aDevTabBaseAddrs[i].u64 &= IOMMU_DEV_TAB_BAR_VALID_MASK;
6401 uint16_t const uSegSize = pThis->aDevTabBaseAddrs[i].n.u9Size;
6402 uint16_t const uMaxSegSize = g_auDevTabSegMaxSizes[i];
6403 AssertLogRelMsgReturn(uSegSize <= uMaxSegSize,
6404 ("Device table [%u] segment size invalid %u (max %u)\n", i, uSegSize, uMaxSegSize), rcErr);
6405 }
6406
6407 /* Command buffer base address register. */
6408 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufBaseAddr.u64);
6409 AssertRCReturn(rc, rc);
6410 pThis->CmdBufBaseAddr.u64 &= IOMMU_CMD_BUF_BAR_VALID_MASK;
6411 AssertLogRelMsgReturn(pThis->CmdBufBaseAddr.n.u4Len >= 8,
6412 ("Command buffer base address invalid %#RX64\n", pThis->CmdBufBaseAddr.u64), rcErr);
6413
6414 /* Event log base address register. */
6415 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBaseAddr.u64);
6416 AssertRCReturn(rc, rc);
6417 pThis->EvtLogBaseAddr.u64 &= IOMMU_EVT_LOG_BAR_VALID_MASK;
6418 AssertLogRelMsgReturn(pThis->EvtLogBaseAddr.n.u4Len >= 8,
6419 ("Event log base address invalid %#RX64\n", pThis->EvtLogBaseAddr.u64), rcErr);
6420
6421 /* Control register. */
6422 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Ctrl.u64);
6423 AssertRCReturn(rc, rc);
6424 pThis->Ctrl.u64 &= IOMMU_CTRL_VALID_MASK;
6425 AssertLogRelMsgReturn(pThis->Ctrl.n.u3DevTabSegEn <= pThis->ExtFeat.n.u2DevTabSegSup,
6426 ("Control register invalid %#RX64\n", pThis->Ctrl.u64), rcErr);
6427
6428 /* Exclusion range base address register. */
6429 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeBaseAddr.u64);
6430 AssertRCReturn(rc, rc);
6431 pThis->ExclRangeBaseAddr.u64 &= IOMMU_EXCL_RANGE_BAR_VALID_MASK;
6432
6433 /* Exclusion range limit register. */
6434 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->ExclRangeLimit.u64);
6435 AssertRCReturn(rc, rc);
6436 pThis->ExclRangeLimit.u64 &= IOMMU_EXCL_RANGE_LIMIT_VALID_MASK;
6437 pThis->ExclRangeLimit.u64 |= UINT64_C(0xfff);
6438
6439#if 0
6440 pHlp->pfnSSMGetU64(pSSM, &pThis->ExtFeat.u64); /* read-only, done already (above). */
6441#endif
6442
6443 /* PPR log base address register. */
6444 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBaseAddr.u64);
6445 AssertRCReturn(rc, rc);
6446 Assert(!pThis->ExtFeat.n.u1PprSup);
6447
6448 /* Hardware event (Hi) register. */
6449 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtHi.u64);
6450 AssertRCReturn(rc, rc);
6451
6452 /* Hardware event (Lo) register. */
6453 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtLo);
6454 AssertRCReturn(rc, rc);
6455
6456 /* Hardware event status register. */
6457 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->HwEvtStatus.u64);
6458 AssertRCReturn(rc, rc);
6459 pThis->HwEvtStatus.u64 &= IOMMU_HW_EVT_STATUS_VALID_MASK;
6460
6461 /* Guest Virtual-APIC log base address register. */
6462 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogBaseAddr.u64);
6463 AssertRCReturn(rc, rc);
6464 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6465
6466 /* Guest Virtual-APIC log tail address register. */
6467 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailAddr.u64);
6468 AssertRCReturn(rc, rc);
6469 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6470
6471 /* PPR log-B base address register. */
6472 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBBaseAddr.u64);
6473 AssertRCReturn(rc, rc);
6474 Assert(!pThis->ExtFeat.n.u1PprSup);
6475
6476 /* Event log-B base address register. */
6477 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBBaseAddr.u64);
6478 AssertRCReturn(rc, rc);
6479 Assert(!pThis->ExtFeat.n.u2DualPprLogSup);
6480
6481#if 0
6482 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificFeat.u64); /* read-only, done already (above). */
6483 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificCtrl.u64); /* read-only, done already (above). */
6484 pHlp->pfnSSMGetU64(pSSM, &pThis->DevSpecificStatus.u64); /* read-only, done already (above). */
6485
6486 pHlp->pfnSSMGetU64(pSSM, &pThis->MiscInfo.u64); /* read-only, done already (above). */
6487#endif
6488
6489 /* Performance optimization control register. */
6490 rc = pHlp->pfnSSMGetU32(pSSM, &pThis->PerfOptCtrl.u32);
6491 AssertRCReturn(rc, rc);
6492 Assert(!pThis->ExtFeat.n.u1PerfOptSup);
6493
6494 /* x2APIC registers. */
6495 {
6496 Assert(!pThis->ExtFeat.n.u1X2ApicSup);
6497
6498 /* x2APIC general interrupt control register. */
6499 pHlp->pfnSSMGetU64(pSSM, &pThis->XtGenIntrCtrl.u64);
6500 AssertRCReturn(rc, rc);
6501
6502 /* x2APIC PPR interrupt control register. */
6503 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtPprIntrCtrl.u64);
6504 AssertRCReturn(rc, rc);
6505
6506 /* x2APIC GA log interrupt control register. */
6507 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->XtGALogIntrCtrl.u64);
6508 AssertRCReturn(rc, rc);
6509 }
6510
6511 /* MARC (Memory Access and Routing) registers. */
6512 {
6513 uint8_t cMarcApers;
6514 rc = pHlp->pfnSSMGetU8(pSSM, &cMarcApers);
6515 AssertRCReturn(rc, rc);
6516 AssertLogRelMsgReturn(cMarcApers > 0 && cMarcApers <= RT_ELEMENTS(pThis->aMarcApers),
6517 ("MARC register count invalid %#x\n", cMarcApers), rcErr);
6518 for (uint8_t i = 0; i < cMarcApers; i++)
6519 {
6520 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Base.u64);
6521 AssertRCReturn(rc, rc);
6522
6523 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Reloc.u64);
6524 AssertRCReturn(rc, rc);
6525
6526 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->aMarcApers[i].Length.u64);
6527 AssertRCReturn(rc, rc);
6528 }
6529 Assert(!pThis->ExtFeat.n.u2MarcSup);
6530 }
6531
6532#if 0
6533 pHlp->pfnSSMGetU64(pSSM, &pThis->RsvdReg); /* read-only, done already (above). */
6534#endif
6535
6536 /* Command buffer head pointer register. */
6537 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufHeadPtr.u64);
6538 AssertRCReturn(rc, rc);
6539 {
6540 /*
6541 * IOMMU behavior is undefined when software writes a value outside the buffer length.
6542 * In our emulation, since we ignore the write entirely (see iommuAmdCmdBufHeadPtr_w)
6543 * we shouldn't see such values in the saved state.
6544 */
6545 uint32_t const offBuf = pThis->CmdBufHeadPtr.u64 & IOMMU_CMD_BUF_HEAD_PTR_VALID_MASK;
6546 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6547 Assert(cbBuf <= _512K);
6548 AssertLogRelMsgReturn(offBuf < cbBuf,
6549 ("Command buffer head pointer invalid %#x\n", pThis->CmdBufHeadPtr.u64), rcErr);
6550 }
6551
6552 /* Command buffer tail pointer register. */
6553 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->CmdBufTailPtr.u64);
6554 AssertRCReturn(rc, rc);
6555 {
6556 uint32_t const offBuf = pThis->CmdBufTailPtr.u64 & IOMMU_CMD_BUF_TAIL_PTR_VALID_MASK;
6557 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->CmdBufBaseAddr.n.u4Len);
6558 Assert(cbBuf <= _512K);
6559 AssertLogRelMsgReturn(offBuf < cbBuf,
6560 ("Command buffer tail pointer invalid %#x\n", pThis->CmdBufTailPtr.u64), rcErr);
6561 }
6562
6563 /* Event log head pointer register. */
6564 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogHeadPtr.u64);
6565 AssertRCReturn(rc, rc);
6566 {
6567 uint32_t const offBuf = pThis->EvtLogHeadPtr.u64 & IOMMU_EVT_LOG_HEAD_PTR_VALID_MASK;
6568 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6569 Assert(cbBuf <= _512K);
6570 AssertLogRelMsgReturn(offBuf < cbBuf,
6571 ("Event log head pointer invalid %#x\n", pThis->EvtLogHeadPtr.u64), rcErr);
6572 }
6573
6574 /* Event log tail pointer register. */
6575 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogTailPtr.u64);
6576 AssertRCReturn(rc, rc);
6577 {
6578 uint32_t const offBuf = pThis->EvtLogTailPtr.u64 & IOMMU_EVT_LOG_TAIL_PTR_VALID_MASK;
6579 uint32_t const cbBuf = iommuAmdGetTotalBufLength(pThis->EvtLogBaseAddr.n.u4Len);
6580 Assert(cbBuf <= _512K);
6581 AssertLogRelMsgReturn(offBuf < cbBuf,
6582 ("Event log tail pointer invalid %#x\n", pThis->EvtLogTailPtr.u64), rcErr);
6583 }
6584
6585 /* Status register. */
6586 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->Status.u64);
6587 AssertRCReturn(rc, rc);
6588 pThis->Status.u64 &= IOMMU_STATUS_VALID_MASK;
6589
6590 /* PPR log head pointer register. */
6591 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogHeadPtr.u64);
6592 AssertRCReturn(rc, rc);
6593 Assert(!pThis->ExtFeat.n.u1PprSup);
6594
6595 /* PPR log tail pointer register. */
6596 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogTailPtr.u64);
6597 AssertRCReturn(rc, rc);
6598 Assert(!pThis->ExtFeat.n.u1PprSup);
6599
6600 /* Guest Virtual-APIC log head pointer register. */
6601 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogHeadPtr.u64);
6602 AssertRCReturn(rc, rc);
6603 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6604
6605 /* Guest Virtual-APIC log tail pointer register. */
6606 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->GALogTailPtr.u64);
6607 AssertRCReturn(rc, rc);
6608 Assert(!pThis->ExtFeat.n.u1GstVirtApicSup);
6609
6610 /* PPR log-B head pointer register. */
6611 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBHeadPtr.u64);
6612 AssertRCReturn(rc, rc);
6613 Assert(!pThis->ExtFeat.n.u1PprSup);
6614
6615 /* PPR log-B head pointer register. */
6616 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBTailPtr.u64);
6617 AssertRCReturn(rc, rc);
6618 Assert(!pThis->ExtFeat.n.u1PprSup);
6619
6620 /* Event log-B head pointer register. */
6621 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBHeadPtr.u64);
6622 AssertRCReturn(rc, rc);
6623 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6624
6625 /* Event log-B tail pointer register. */
6626 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->EvtLogBTailPtr.u64);
6627 AssertRCReturn(rc, rc);
6628 Assert(!pThis->ExtFeat.n.u2DualEvtLogSup);
6629
6630 /* PPR log auto response register. */
6631 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogAutoResp.u64);
6632 AssertRCReturn(rc, rc);
6633 Assert(!pThis->ExtFeat.n.u1PprAutoRespSup);
6634
6635 /* PPR log overflow early indicator register. */
6636 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogOverflowEarly.u64);
6637 AssertRCReturn(rc, rc);
6638 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6639
6640 /* PPR log-B overflow early indicator register. */
6641 rc = pHlp->pfnSSMGetU64(pSSM, &pThis->PprLogBOverflowEarly.u64);
6642 AssertRCReturn(rc, rc);
6643 Assert(!pThis->ExtFeat.n.u1PprLogOverflowWarn);
6644
6645 /* End marker. */
6646 {
6647 uint32_t uEndMarker;
6648 rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
6649 AssertLogRelMsgRCReturn(rc, ("Failed to read end marker. rc=%Rrc\n", rc), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
6650 AssertLogRelMsgReturn(uEndMarker == UINT32_MAX, ("End marker invalid (%#x expected %#x)\n", uEndMarker, UINT32_MAX),
6651 rcErr);
6652 }
6653
6654 return rc;
6655}
6656
6657
6658/**
6659 * @callback_method_impl{FNSSMDEVLOADDONE}
6660 */
6661static DECLCALLBACK(int) iommuAmdR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
6662{
6663 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6664 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6665 RT_NOREF(pSSM);
6666 LogFlowFunc(("\n"));
6667
6668 /* Sanity. */
6669 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6670 AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
6671
6672 int rc;
6673 IOMMU_LOCK(pDevIns, pThisR3);
6674
6675 /* Map MMIO regions if the IOMMU BAR is enabled. */
6676 if (pThis->IommuBar.n.u1Enable)
6677 rc = iommuAmdR3MmioSetup(pDevIns);
6678 else
6679 rc = VINF_SUCCESS;
6680
6681 /* Wake up the command thread if commands need processing. */
6682 iommuAmdCmdThreadWakeUpIfNeeded(pDevIns);
6683
6684 IOMMU_UNLOCK(pDevIns, pThisR3);
6685
6686 LogRel(("%s: Restored: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
6687 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
6688 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
6689 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
6690 pThis->ExtFeat.u64));
6691 return rc;
6692}
6693
6694
6695/**
6696 * @interface_method_impl{PDMDEVREG,pfnReset}
6697 */
6698static DECLCALLBACK(void) iommuAmdR3Reset(PPDMDEVINS pDevIns)
6699{
6700 /*
6701 * Resets read-write portion of the IOMMU state.
6702 *
6703 * NOTE! State not initialized here is expected to be initialized during
6704 * device construction and remain read-only through the lifetime of the VM.
6705 */
6706 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6707 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6708 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6709 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6710 LogFlowFunc(("\n"));
6711
6712 IOMMU_LOCK(pDevIns, pThisR3);
6713
6714 RT_ZERO(pThis->aDevTabBaseAddrs);
6715
6716 pThis->CmdBufBaseAddr.u64 = 0;
6717 pThis->CmdBufBaseAddr.n.u4Len = 8;
6718
6719 pThis->EvtLogBaseAddr.u64 = 0;
6720 pThis->EvtLogBaseAddr.n.u4Len = 8;
6721
6722 pThis->Ctrl.u64 = 0;
6723 pThis->Ctrl.n.u1Coherent = 1;
6724 Assert(!pThis->ExtFeat.n.u1BlockStopMarkSup);
6725
6726 pThis->ExclRangeBaseAddr.u64 = 0;
6727 pThis->ExclRangeLimit.u64 = 0;
6728
6729 pThis->PprLogBaseAddr.u64 = 0;
6730 pThis->PprLogBaseAddr.n.u4Len = 8;
6731
6732 pThis->HwEvtHi.u64 = 0;
6733 pThis->HwEvtLo = 0;
6734 pThis->HwEvtStatus.u64 = 0;
6735
6736 pThis->GALogBaseAddr.u64 = 0;
6737 pThis->GALogBaseAddr.n.u4Len = 8;
6738 pThis->GALogTailAddr.u64 = 0;
6739
6740 pThis->PprLogBBaseAddr.u64 = 0;
6741 pThis->PprLogBBaseAddr.n.u4Len = 8;
6742
6743 pThis->EvtLogBBaseAddr.u64 = 0;
6744 pThis->EvtLogBBaseAddr.n.u4Len = 8;
6745
6746 pThis->PerfOptCtrl.u32 = 0;
6747
6748 pThis->XtGenIntrCtrl.u64 = 0;
6749 pThis->XtPprIntrCtrl.u64 = 0;
6750 pThis->XtGALogIntrCtrl.u64 = 0;
6751
6752 RT_ZERO(pThis->aMarcApers);
6753
6754 pThis->CmdBufHeadPtr.u64 = 0;
6755 pThis->CmdBufTailPtr.u64 = 0;
6756 pThis->EvtLogHeadPtr.u64 = 0;
6757 pThis->EvtLogTailPtr.u64 = 0;
6758
6759 pThis->Status.u64 = 0;
6760
6761 pThis->PprLogHeadPtr.u64 = 0;
6762 pThis->PprLogTailPtr.u64 = 0;
6763
6764 pThis->GALogHeadPtr.u64 = 0;
6765 pThis->GALogTailPtr.u64 = 0;
6766
6767 pThis->PprLogBHeadPtr.u64 = 0;
6768 pThis->PprLogBTailPtr.u64 = 0;
6769
6770 pThis->EvtLogBHeadPtr.u64 = 0;
6771 pThis->EvtLogBTailPtr.u64 = 0;
6772
6773 pThis->PprLogAutoResp.u64 = 0;
6774 pThis->PprLogOverflowEarly.u64 = 0;
6775 pThis->PprLogBOverflowEarly.u64 = 0;
6776
6777 pThis->IommuBar.u64 = 0;
6778 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0);
6779 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0);
6780
6781 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER);
6782
6783 IOMMU_UNLOCK(pDevIns, pThisR3);
6784
6785#ifdef IOMMU_WITH_DTE_CACHE
6786 iommuAmdDteCacheRemoveAll(pDevIns);
6787#endif
6788#ifdef IOMMU_WITH_IOTLBE_CACHE
6789 iommuAmdIotlbRemoveAll(pDevIns);
6790#endif
6791#ifdef IOMMU_WITH_IRTE_CACHE
6792 iommuAmdIrteCacheRemoveAll(pDevIns);
6793#endif
6794}
6795
6796
6797/**
6798 * @interface_method_impl{PDMDEVREG,pfnDestruct}
6799 */
6800static DECLCALLBACK(int) iommuAmdR3Destruct(PPDMDEVINS pDevIns)
6801{
6802 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
6803 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6804 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6805 LogFlowFunc(("\n"));
6806
6807 IOMMU_LOCK(pDevIns, pThisR3);
6808
6809 if (pThis->hEvtCmdThread != NIL_SUPSEMEVENT)
6810 {
6811 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtCmdThread);
6812 pThis->hEvtCmdThread = NIL_SUPSEMEVENT;
6813 }
6814
6815#ifdef IOMMU_WITH_IOTLBE_CACHE
6816 if (pThisR3->paIotlbes)
6817 {
6818 PDMDevHlpMMHeapFree(pDevIns, pThisR3->paIotlbes);
6819 pThisR3->paIotlbes = NULL;
6820 pThisR3->idxUnusedIotlbe = 0;
6821 }
6822#endif
6823
6824 IOMMU_UNLOCK(pDevIns, pThisR3);
6825 return VINF_SUCCESS;
6826}
6827
6828
6829/**
6830 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6831 */
6832static DECLCALLBACK(int) iommuAmdR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6833{
6834 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6835
6836 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
6837 PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
6838 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
6839
6840 pThis->u32Magic = IOMMU_MAGIC;
6841 pThisR3->pDevInsR3 = pDevIns;
6842
6843 LogFlowFunc(("iInstance=%d\n", iInstance));
6844
6845 /*
6846 * Validate and read the configuration.
6847 */
6848 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "PCIAddress", "");
6849 int rc = pHlp->pfnCFGMQueryU32Def(pCfg, "PCIAddress", &pThis->uPciAddress, NIL_PCIBDF);
6850 if (RT_FAILURE(rc))
6851 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to query 32-bit integer \"PCIAddress\""));
6852 if (!PCIBDF_IS_VALID(pThis->uPciAddress))
6853 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed \"PCIAddress\" of the AMD IOMMU cannot be invalid"));
6854
6855 /*
6856 * Register the IOMMU with PDM.
6857 */
6858 PDMIOMMUREGR3 IommuReg;
6859 RT_ZERO(IommuReg);
6860 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
6861 IommuReg.pfnMemAccess = iommuAmdMemAccess;
6862 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
6863 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
6864 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
6865 rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
6866 if (RT_FAILURE(rc))
6867 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
6868 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
6869 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6870 N_("IOMMU helper version mismatch; got %#x expected %#x"),
6871 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
6872 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
6873 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
6874 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
6875 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
6876 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
6877 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
6878 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
6879 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
6880
6881 /*
6882 * We will use PDM's critical section (via helpers) for the IOMMU device.
6883 */
6884 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
6885 AssertRCReturn(rc, rc);
6886
6887 /*
6888 * Initialize read-only PCI configuration space.
6889 */
6890 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
6891 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
6892
6893 /* Header. */
6894 PDMPciDevSetVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* AMD */
6895 PDMPciDevSetDeviceId(pPciDev, IOMMU_PCI_DEVICE_ID); /* VirtualBox IOMMU device */
6896 PDMPciDevSetCommand(pPciDev, VBOX_PCI_COMMAND_MASTER); /* Enable bus master (as we directly access main memory) */
6897 PDMPciDevSetStatus(pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* Capability list supported */
6898 PDMPciDevSetRevisionId(pPciDev, IOMMU_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
6899 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
6900 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_IOMMU); /* IOMMU */
6901 PDMPciDevSetClassProg(pPciDev, 0x0); /* IOMMU Programming interface */
6902 PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
6903 PDMPciDevSetSubSystemId(pPciDev, IOMMU_PCI_DEVICE_ID); /* AMD */
6904 PDMPciDevSetSubSystemVendorId(pPciDev, IOMMU_PCI_VENDOR_ID); /* VirtualBox IOMMU device */
6905 PDMPciDevSetCapabilityList(pPciDev, IOMMU_PCI_OFF_CAP_HDR); /* Offset into capability registers */
6906 PDMPciDevSetInterruptPin(pPciDev, 0x1); /* INTA#. */
6907 PDMPciDevSetInterruptLine(pPciDev, 0x0); /* For software compatibility; no effect on hardware */
6908
6909 /* Capability Header. */
6910 /* NOTE! Fields (e.g, EFR) must match what we expose in the ACPI tables. */
6911 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_CAP_HDR,
6912 RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_ID, 0xf) /* RO - Secure Device capability block */
6913 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_PTR, IOMMU_PCI_OFF_MSI_CAP_HDR) /* RO - Next capability offset */
6914 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_TYPE, 0x3) /* RO - IOMMU capability block */
6915 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_REV, 0x1) /* RO - IOMMU interface revision */
6916 | RT_BF_MAKE(IOMMU_BF_CAPHDR_IOTLB_SUP, 0x0) /* RO - Remote IOTLB support */
6917 | RT_BF_MAKE(IOMMU_BF_CAPHDR_HT_TUNNEL, 0x0) /* RO - HyperTransport Tunnel support */
6918 | RT_BF_MAKE(IOMMU_BF_CAPHDR_NP_CACHE, 0x0) /* RO - Cache NP page table entries */
6919 | RT_BF_MAKE(IOMMU_BF_CAPHDR_EFR_SUP, 0x1) /* RO - Extended Feature Register support */
6920 | RT_BF_MAKE(IOMMU_BF_CAPHDR_CAP_EXT, 0x1)); /* RO - Misc. Information Register support */
6921
6922 /* Base Address Register. */
6923 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_LO, 0x0); /* RW - Base address (Lo) and enable bit */
6924 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_BASE_ADDR_REG_HI, 0x0); /* RW - Base address (Hi) */
6925
6926 /* IOMMU Range Register. */
6927 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_RANGE_REG, 0x0); /* RW - Range register (implemented as RO by us) */
6928
6929 /* Misc. Information Register. */
6930 /* NOTE! Fields (e.g, GVA size) must match what we expose in the ACPI tables. */
6931 uint32_t const uMiscInfoReg0 = RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM, 0) /* RO - MSI number */
6932 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_GVA_SIZE, 2) /* RO - Guest Virt. Addr size (2=48 bits) */
6933 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_PA_SIZE, 48) /* RO - Physical Addr size (48 bits) */
6934 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_VA_SIZE, 64) /* RO - Virt. Addr size (64 bits) */
6935 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_HT_ATS_RESV, 0) /* RW - HT ATS reserved */
6936 | RT_BF_MAKE(IOMMU_BF_MISCINFO_0_MSI_NUM_PPR, 0); /* RW - PPR interrupt number */
6937 uint32_t const uMiscInfoReg1 = 0;
6938 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_0, uMiscInfoReg0);
6939 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MISCINFO_REG_1, uMiscInfoReg1);
6940
6941 /* MSI Capability Header register. */
6942 PDMMSIREG MsiReg;
6943 RT_ZERO(MsiReg);
6944 MsiReg.cMsiVectors = 1;
6945 MsiReg.iMsiCapOffset = IOMMU_PCI_OFF_MSI_CAP_HDR;
6946 MsiReg.iMsiNextOffset = 0; /* IOMMU_PCI_OFF_MSI_MAP_CAP_HDR */
6947 MsiReg.fMsi64bit = 1; /* 64-bit addressing support is mandatory; See AMD IOMMU spec. 2.8 "IOMMU Interrupt Support". */
6948
6949 /* MSI Address (Lo, Hi) and MSI data are read-write PCI config registers handled by our generic PCI config space code. */
6950#if 0
6951 /* MSI Address Lo. */
6952 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_LO, 0); /* RW - MSI message address (Lo) */
6953 /* MSI Address Hi. */
6954 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_ADDR_HI, 0); /* RW - MSI message address (Hi) */
6955 /* MSI Data. */
6956 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_DATA, 0); /* RW - MSI data */
6957#endif
6958
6959#if 0
6960 /** @todo IOMMU: I don't know if we need to support this, enable later if
6961 * required. */
6962 /* MSI Mapping Capability Header register. */
6963 PDMPciDevSetDWord(pPciDev, IOMMU_PCI_OFF_MSI_MAP_CAP_HDR,
6964 RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_ID, 0x8) /* RO - Capability ID */
6965 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_PTR, 0x0) /* RO - Offset to next capability (NULL) */
6966 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_EN, 0x1) /* RO - MSI mapping capability enable */
6967 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_FIXED, 0x1) /* RO - MSI mapping range is fixed */
6968 | RT_BF_MAKE(IOMMU_BF_MSI_MAP_CAPHDR_CAP_TYPE, 0x15)); /* RO - MSI mapping capability */
6969 /* When implementing don't forget to copy this to its MMIO shadow register (MsiMapCapHdr) in iommuAmdR3Init. */
6970#endif
6971
6972 /*
6973 * Register the PCI function with PDM.
6974 */
6975 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
6976 AssertLogRelRCReturn(rc, rc);
6977
6978 /*
6979 * Register MSI support for the PCI device.
6980 * This must be done -after- registering it as a PCI device!
6981 */
6982 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6983 AssertRCReturn(rc, rc);
6984
6985 /*
6986 * Intercept PCI config. space accesses.
6987 */
6988 rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, iommuAmdR3PciConfigRead, iommuAmdR3PciConfigWrite);
6989 AssertLogRelRCReturn(rc, rc);
6990
6991 /*
6992 * Create the MMIO region.
6993 * Mapping of the region is done when software configures it via PCI config space.
6994 */
6995 rc = PDMDevHlpMmioCreate(pDevIns, IOMMU_MMIO_REGION_SIZE, pPciDev, 0 /* iPciRegion */, iommuAmdMmioWrite, iommuAmdMmioRead,
6996 NULL /* pvUser */,
6997 IOMMMIO_FLAGS_READ_DWORD_QWORD
6998 | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_READ_MISSING
6999 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
7000 | IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
7001 "AMD-IOMMU", &pThis->hMmio);
7002 AssertLogRelRCReturn(rc, rc);
7003
7004 /*
7005 * Register saved state handlers.
7006 */
7007 rc = PDMDevHlpSSMRegisterEx(pDevIns, IOMMU_SAVED_STATE_VERSION, sizeof(IOMMU), NULL /* pszBefore */,
7008 NULL /* pfnLivePrep */, NULL /* pfnLiveExec */, NULL /* pfnLiveVote */,
7009 NULL /* pfnSavePrep */, iommuAmdR3SaveExec, NULL /* pfnSaveDone */,
7010 NULL /* pfnLoadPrep */, iommuAmdR3LoadExec, iommuAmdR3LoadDone);
7011 AssertLogRelRCReturn(rc, rc);
7012
7013 /*
7014 * Register debugger info items.
7015 */
7016 PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", iommuAmdR3DbgInfo);
7017 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudte", "Display the DTE for a device (from memory). Arguments: DeviceID.", iommuAmdR3DbgInfoDte);
7018 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudevtabs", "Display I/O device tables with translation enabled.", iommuAmdR3DbgInfoDevTabs);
7019#ifdef IOMMU_WITH_IOTLBE_CACHE
7020 PDMDevHlpDBGFInfoRegister(pDevIns, "iommutlb", "Display IOTLBs for a domain. Arguments: DomainID.", iommuAmdR3DbgInfoIotlb);
7021#endif
7022#ifdef IOMMU_WITH_DTE_CACHE
7023 PDMDevHlpDBGFInfoRegister(pDevIns, "iommudtecache", "Display the DTE cache.", iommuAmdR3DbgInfoDteCache);
7024#endif
7025#ifdef IOMMU_WITH_IRTE_CACHE
7026 PDMDevHlpDBGFInfoRegister(pDevIns, "iommuirtecache", "Display the IRTE cache.", iommuAmdR3DbgInfoIrteCache);
7027#endif
7028
7029# ifdef VBOX_WITH_STATISTICS
7030 /*
7031 * Statistics.
7032 */
7033 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
7034 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
7035
7036 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
7037 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
7038
7039 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
7040 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
7041
7042 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
7043 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
7044
7045 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
7046 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
7047
7048 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
7049 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
7050
7051 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
7052 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
7053
7054 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmd, STAMTYPE_COUNTER, "R3/Commands", STAMUNIT_OCCURENCES, "Number of commands processed (total).");
7055 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompWait, STAMTYPE_COUNTER, "R3/Commands/CompWait", STAMUNIT_OCCURENCES, "Number of Completion Wait commands processed.");
7056 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvDte, STAMTYPE_COUNTER, "R3/Commands/InvDte", STAMUNIT_OCCURENCES, "Number of Invalidate DTE commands processed.");
7057 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuPages, STAMTYPE_COUNTER, "R3/Commands/InvIommuPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU Pages commands processed.");
7058 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIotlbPages, STAMTYPE_COUNTER, "R3/Commands/InvIotlbPages", STAMUNIT_OCCURENCES, "Number of Invalidate IOTLB Pages commands processed.");
7059 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIntrTable, STAMTYPE_COUNTER, "R3/Commands/InvIntrTable", STAMUNIT_OCCURENCES, "Number of Invalidate Interrupt Table commands processed.");
7060 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdPrefIommuPages, STAMTYPE_COUNTER, "R3/Commands/PrefIommuPages", STAMUNIT_OCCURENCES, "Number of Prefetch IOMMU Pages commands processed.");
7061 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdCompletePprReq, STAMTYPE_COUNTER, "R3/Commands/CompletePprReq", STAMUNIT_OCCURENCES, "Number of Complete PPR Requests commands processed.");
7062 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCmdInvIommuAll, STAMTYPE_COUNTER, "R3/Commands/InvIommuAll", STAMUNIT_OCCURENCES, "Number of Invalidate IOMMU All commands processed.");
7063
7064
7065 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeCached, STAMTYPE_COUNTER, "IOTLB/Cached", STAMUNIT_OCCURENCES, "Number of IOTLB entries in the cache.");
7066 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbeLazyEvictReuse, STAMTYPE_COUNTER, "IOTLB/LazyEvictReuse", STAMUNIT_OCCURENCES, "Number of IOTLB entries reused after lazy eviction.");
7067
7068 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfDteLookup, STAMTYPE_PROFILE, "Profile/DteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling DTE lookup.");
7069 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIotlbeLookup, STAMTYPE_PROFILE, "Profile/IotlbeLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IOTLBE lookup.");
7070
7071 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteLookup, STAMTYPE_PROFILE, "Profile/IrteLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE lookup.");
7072 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatProfIrteCacheLookup, STAMTYPE_PROFILE, "Profile/IrteCacheLookup", STAMUNIT_TICKS_PER_CALL, "Profiling IRTE cache lookup.");
7073
7074 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHit, STAMTYPE_COUNTER, "MemAccess/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7075 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheMiss, STAMTYPE_COUNTER, "MemAccess/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7076 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheHitFull, STAMTYPE_COUNTER, "MemAccess/CacheHitFull", STAMUNIT_OCCURENCES, "Number of accesses that was entirely in the cache.");
7077 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCacheNonContig, STAMTYPE_COUNTER, "MemAccess/CacheNonContig", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in non-contiguous translated regions.");
7078 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessCachePermDenied, STAMTYPE_COUNTER, "MemAccess/CacheAddrDenied", STAMUNIT_OCCURENCES, "Number of cache accesses that resulted in denied permissions.");
7079 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDteNonContig, STAMTYPE_COUNTER, "MemAccess/DteNonContig", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in non-contiguous translated regions.");
7080 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDtePermDenied, STAMTYPE_COUNTER, "MemAccess/DtePermDenied", STAMUNIT_OCCURENCES, "Number of DTE accesses that resulted in denied permissions.");
7081
7082 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheHit, STAMTYPE_COUNTER, "Interrupt/CacheHit", STAMUNIT_OCCURENCES, "Number of cache hits.");
7083 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIntrCacheMiss, STAMTYPE_COUNTER, "Interrupt/CacheMiss", STAMUNIT_OCCURENCES, "Number of cache misses.");
7084
7085 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatNonStdPageSize, STAMTYPE_COUNTER, "MemAccess/NonStdPageSize", STAMUNIT_OCCURENCES, "Number of non-standard page size translations.");
7086 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIopfs, STAMTYPE_COUNTER, "MemAccess/IOPFs", STAMUNIT_OCCURENCES, "Number of I/O page faults.");
7087# endif
7088
7089 /*
7090 * Create the command thread and its event semaphore.
7091 */
7092 char szDevIommu[64];
7093 RT_ZERO(szDevIommu);
7094 RTStrPrintf(szDevIommu, sizeof(szDevIommu), "IOMMU-%u", iInstance);
7095 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pCmdThread, pThis, iommuAmdR3CmdThread, iommuAmdR3CmdThreadWakeUp,
7096 0 /* cbStack */, RTTHREADTYPE_IO, szDevIommu);
7097 AssertLogRelRCReturn(rc, rc);
7098
7099 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtCmdThread);
7100 AssertLogRelRCReturn(rc, rc);
7101
7102#ifdef IOMMU_WITH_DTE_CACHE
7103 /*
7104 * Initialize the critsect of the cache.
7105 */
7106 rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSectCache, RT_SRC_POS, "IOMMUCache-#%u", pDevIns->iInstance);
7107 AssertLogRelRCReturn(rc, rc);
7108
7109 /* Several places in this code relies on this basic assumption - assert it! */
7110 AssertCompile(RT_ELEMENTS(pThis->aDeviceIds) == RT_ELEMENTS(pThis->aDteCache));
7111#endif
7112
7113#ifdef IOMMU_WITH_IOTLBE_CACHE
7114 /*
7115 * Allocate IOTLB entries.
7116 * This is allocated upfront since we expect a relatively small number of entries,
7117 * is more cache-line efficient and easier to track least recently used entries for
7118 * eviction when the cache is full. This also avoids unpredictable behavior during
7119 * the lifetime of the VM if the hyperheap gets full.
7120 */
7121 size_t const cbIotlbes = sizeof(IOTLBE) * IOMMU_IOTLBE_MAX;
7122 pThisR3->paIotlbes = (PIOTLBE)PDMDevHlpMMHeapAllocZ(pDevIns, cbIotlbes);
7123 if (!pThisR3->paIotlbes)
7124 return PDMDevHlpVMSetError(pDevIns, VERR_NO_MEMORY, RT_SRC_POS,
7125 N_("Failed to allocate %zu bytes from the hyperheap for the IOTLB cache."), cbIotlbes);
7126 RTListInit(&pThisR3->LstLruIotlbe);
7127 LogRel(("%s: Allocated %zu bytes from the hyperheap for the IOTLB cache\n", IOMMU_LOG_PFX, cbIotlbes));
7128#endif
7129
7130 /*
7131 * Initialize read-only registers.
7132 * NOTE! Fields here must match their corresponding field in the ACPI tables.
7133 */
7134 /* Don't remove the commented lines below as it lets us see all features at a glance. */
7135 pThis->ExtFeat.u64 = 0;
7136 //pThis->ExtFeat.n.u1PrefetchSup = 0;
7137 //pThis->ExtFeat.n.u1PprSup = 0;
7138 //pThis->ExtFeat.n.u1X2ApicSup = 0;
7139 //pThis->ExtFeat.n.u1NoExecuteSup = 0;
7140 //pThis->ExtFeat.n.u1GstTranslateSup = 0;
7141 pThis->ExtFeat.n.u1InvAllSup = 1;
7142 //pThis->ExtFeat.n.u1GstVirtApicSup = 0;
7143 pThis->ExtFeat.n.u1HwErrorSup = 1;
7144 //pThis->ExtFeat.n.u1PerfCounterSup = 0;
7145 AssertCompile((IOMMU_MAX_HOST_PT_LEVEL & 0x3) < 3);
7146 pThis->ExtFeat.n.u2HostAddrTranslateSize = (IOMMU_MAX_HOST_PT_LEVEL & 0x3);
7147 //pThis->ExtFeat.n.u2GstAddrTranslateSize = 0; /* Requires GstTranslateSup */
7148 //pThis->ExtFeat.n.u2GstCr3RootTblLevel = 0; /* Requires GstTranslateSup */
7149 //pThis->ExtFeat.n.u2SmiFilterSup = 0;
7150 //pThis->ExtFeat.n.u3SmiFilterCount = 0;
7151 //pThis->ExtFeat.n.u3GstVirtApicModeSup = 0; /* Requires GstVirtApicSup */
7152 //pThis->ExtFeat.n.u2DualPprLogSup = 0;
7153 //pThis->ExtFeat.n.u2DualEvtLogSup = 0;
7154 //pThis->ExtFeat.n.u5MaxPasidSup = 0; /* Requires GstTranslateSup */
7155 //pThis->ExtFeat.n.u1UserSupervisorSup = 0;
7156 AssertCompile(IOMMU_MAX_DEV_TAB_SEGMENTS <= 3);
7157 pThis->ExtFeat.n.u2DevTabSegSup = IOMMU_MAX_DEV_TAB_SEGMENTS;
7158 //pThis->ExtFeat.n.u1PprLogOverflowWarn = 0;
7159 //pThis->ExtFeat.n.u1PprAutoRespSup = 0;
7160 //pThis->ExtFeat.n.u2MarcSup = 0;
7161 //pThis->ExtFeat.n.u1BlockStopMarkSup = 0;
7162 //pThis->ExtFeat.n.u1PerfOptSup = 0;
7163 pThis->ExtFeat.n.u1MsiCapMmioSup = 1;
7164 //pThis->ExtFeat.n.u1GstIoSup = 0;
7165 //pThis->ExtFeat.n.u1HostAccessSup = 0;
7166 //pThis->ExtFeat.n.u1EnhancedPprSup = 0;
7167 //pThis->ExtFeat.n.u1AttrForwardSup = 0;
7168 //pThis->ExtFeat.n.u1HostDirtySup = 0;
7169 //pThis->ExtFeat.n.u1InvIoTlbTypeSup = 0;
7170 //pThis->ExtFeat.n.u1GstUpdateDisSup = 0;
7171 //pThis->ExtFeat.n.u1ForcePhysDstSup = 0;
7172
7173 pThis->DevSpecificFeat.u64 = 0;
7174 pThis->DevSpecificFeat.n.u4RevMajor = IOMMU_DEVSPEC_FEAT_MAJOR_VERSION;
7175 pThis->DevSpecificFeat.n.u4RevMinor = IOMMU_DEVSPEC_FEAT_MINOR_VERSION;
7176
7177 pThis->DevSpecificCtrl.u64 = 0;
7178 pThis->DevSpecificCtrl.n.u4RevMajor = IOMMU_DEVSPEC_CTRL_MAJOR_VERSION;
7179 pThis->DevSpecificCtrl.n.u4RevMinor = IOMMU_DEVSPEC_CTRL_MINOR_VERSION;
7180
7181 pThis->DevSpecificStatus.u64 = 0;
7182 pThis->DevSpecificStatus.n.u4RevMajor = IOMMU_DEVSPEC_STATUS_MAJOR_VERSION;
7183 pThis->DevSpecificStatus.n.u4RevMinor = IOMMU_DEVSPEC_STATUS_MINOR_VERSION;
7184
7185 pThis->MiscInfo.u64 = RT_MAKE_U64(uMiscInfoReg0, uMiscInfoReg1);
7186
7187 pThis->RsvdReg = 0;
7188
7189 /*
7190 * Initialize parts of the IOMMU state as it would during reset.
7191 * Also initializes non-zero initial values like IRTE cache keys.
7192 * Must be called -after- initializing PCI config. space registers.
7193 */
7194 iommuAmdR3Reset(pDevIns);
7195
7196 LogRel(("%s: DSFX=%u.%u DSCX=%u.%u DSSX=%u.%u ExtFeat=%#RX64\n", IOMMU_LOG_PFX,
7197 pThis->DevSpecificFeat.n.u4RevMajor, pThis->DevSpecificFeat.n.u4RevMinor,
7198 pThis->DevSpecificCtrl.n.u4RevMajor, pThis->DevSpecificCtrl.n.u4RevMinor,
7199 pThis->DevSpecificStatus.n.u4RevMajor, pThis->DevSpecificStatus.n.u4RevMinor,
7200 pThis->ExtFeat.u64));
7201 return VINF_SUCCESS;
7202}
7203
7204#else
7205
7206/**
7207 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
7208 */
7209static DECLCALLBACK(int) iommuAmdRZConstruct(PPDMDEVINS pDevIns)
7210{
7211 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
7212 PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
7213 PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
7214 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
7215
7216 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
7217 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
7218 AssertRCReturn(rc, rc);
7219
7220 /* Set up the MMIO RZ handlers. */
7221 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuAmdMmioWrite, iommuAmdMmioRead, NULL /* pvUser */);
7222 AssertRCReturn(rc, rc);
7223
7224 /* Set up the IOMMU RZ callbacks. */
7225 PDMIOMMUREGCC IommuReg;
7226 RT_ZERO(IommuReg);
7227 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
7228 IommuReg.idxIommu = pThis->idxIommu;
7229 IommuReg.pfnMemAccess = iommuAmdMemAccess;
7230 IommuReg.pfnMemBulkAccess = iommuAmdMemBulkAccess;
7231 IommuReg.pfnMsiRemap = iommuAmdMsiRemap;
7232 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
7233 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
7234 AssertRCReturn(rc, rc);
7235 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
7236 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7237 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
7238 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
7239 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
7240 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
7241 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
7242 return VINF_SUCCESS;
7243}
7244#endif
7245
7246
7247/**
7248 * The device registration structure.
7249 */
7250const PDMDEVREG g_DeviceIommuAmd =
7251{
7252 /* .u32Version = */ PDM_DEVREG_VERSION,
7253 /* .uReserved0 = */ 0,
7254 /* .szName = */ "iommu-amd",
7255 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
7256 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
7257 /* .cMaxInstances = */ 1,
7258 /* .uSharedVersion = */ 42,
7259 /* .cbInstanceShared = */ sizeof(IOMMU),
7260 /* .cbInstanceCC = */ sizeof(IOMMUCC),
7261 /* .cbInstanceRC = */ sizeof(IOMMURC),
7262 /* .cMaxPciDevices = */ 1,
7263 /* .cMaxMsixVectors = */ 0,
7264 /* .pszDescription = */ "IOMMU (AMD)",
7265#if defined(IN_RING3)
7266 /* .pszRCMod = */ "VBoxDDRC.rc",
7267 /* .pszR0Mod = */ "VBoxDDR0.r0",
7268 /* .pfnConstruct = */ iommuAmdR3Construct,
7269 /* .pfnDestruct = */ iommuAmdR3Destruct,
7270 /* .pfnRelocate = */ NULL,
7271 /* .pfnMemSetup = */ NULL,
7272 /* .pfnPowerOn = */ NULL,
7273 /* .pfnReset = */ iommuAmdR3Reset,
7274 /* .pfnSuspend = */ NULL,
7275 /* .pfnResume = */ NULL,
7276 /* .pfnAttach = */ NULL,
7277 /* .pfnDetach = */ NULL,
7278 /* .pfnQueryInterface = */ NULL,
7279 /* .pfnInitComplete = */ NULL,
7280 /* .pfnPowerOff = */ NULL,
7281 /* .pfnSoftReset = */ NULL,
7282 /* .pfnReserved0 = */ NULL,
7283 /* .pfnReserved1 = */ NULL,
7284 /* .pfnReserved2 = */ NULL,
7285 /* .pfnReserved3 = */ NULL,
7286 /* .pfnReserved4 = */ NULL,
7287 /* .pfnReserved5 = */ NULL,
7288 /* .pfnReserved6 = */ NULL,
7289 /* .pfnReserved7 = */ NULL,
7290#elif defined(IN_RING0)
7291 /* .pfnEarlyConstruct = */ NULL,
7292 /* .pfnConstruct = */ iommuAmdRZConstruct,
7293 /* .pfnDestruct = */ NULL,
7294 /* .pfnFinalDestruct = */ NULL,
7295 /* .pfnRequest = */ NULL,
7296 /* .pfnReserved0 = */ NULL,
7297 /* .pfnReserved1 = */ NULL,
7298 /* .pfnReserved2 = */ NULL,
7299 /* .pfnReserved3 = */ NULL,
7300 /* .pfnReserved4 = */ NULL,
7301 /* .pfnReserved5 = */ NULL,
7302 /* .pfnReserved6 = */ NULL,
7303 /* .pfnReserved7 = */ NULL,
7304#elif defined(IN_RC)
7305 /* .pfnConstruct = */ iommuAmdRZConstruct,
7306 /* .pfnReserved0 = */ NULL,
7307 /* .pfnReserved1 = */ NULL,
7308 /* .pfnReserved2 = */ NULL,
7309 /* .pfnReserved3 = */ NULL,
7310 /* .pfnReserved4 = */ NULL,
7311 /* .pfnReserved5 = */ NULL,
7312 /* .pfnReserved6 = */ NULL,
7313 /* .pfnReserved7 = */ NULL,
7314#else
7315# error "Not in IN_RING3, IN_RING0 or IN_RC!"
7316#endif
7317 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
7318};
7319
7320#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
7321
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette