DevIommuIntel.cpp@ 88530

Last change on this file since 88530 was 88521, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Updates to adjust for changes in Oct 2020 and Apr 2021 Intel VT-d specs.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 59.9 KB

Line
1	/* $Id: DevIommuIntel.cpp 88521 2021-04-15 10:56:57Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/string.h>
27
28
29	/*********************************************************************************************************************************
30	* Defined Constants And Macros *
31	*********************************************************************************************************************************/
32	/** Gets the low uint32_t of a uint64_t or something equivalent.
33	*
34	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
35	* used as it asserts for correctness when compiling on certain compilers). */
36	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
37
38	/** Gets the high uint32_t of a uint64_t or something equivalent.
39	*
40	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
41	* used as it asserts for correctness when compiling on certain compilers). */
42	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
43
44	/** Asserts MMIO access' offset and size are valid or returns appropriate error
45	* code suitable for returning from MMIO access handlers. */
46	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
47	do { \
48	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
49	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
50	} while (0);
51
52	/** Checks whether the MMIO offset is valid. */
53	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
54	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
55
56	/** @name DMAR implementation specifics.
57	* @{ */
58	/** The number of fault recording registers our implementation supports.
59	* Normal guest operation shouldn't trigger faults anyway, so we only support the
60	* minimum number of registers (which is 1).
61	*
62	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG::NFR). */
63	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
64
65	/** Offset of first register in group 0. */
66	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
67	/** Offset of last register in group 0 (inclusive). */
68	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
69	/** Last valid offset in group 0 (exclusive). */
70	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
71	/** Size of the group 0 (in bytes). */
72	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
73	/*< Implementation-specific MMIO offset of IVA_REG. /
74	#define DMAR_MMIO_OFF_IVA_REG 0xe50
75	/*< Implementation-specific MMIO offset of IOTLB_REG. /
76	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
77	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
78	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
79	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
80	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
81	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
82
83	/** Offset of first register in group 1. */
84	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
85	/** Offset of last register in group 1 (inclusive). */
86	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
87	/** Last valid offset in group 1 (exclusive). */
88	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
89	/** Size of the group 1 (in bytes). */
90	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
91
92	/** DMAR implementation's minor version number (exposed to software). */
93	#define DMAR_VER_MINOR 0
94	/** DMAR implementation's major version number (exposed to software). */
95	#define DMAR_VER_MAJOR 1
96	/** @} */
97
98	/** Release log prefix string. */
99	#define DMAR_LOG_PFX "Intel-IOMMU"
100	/** The current saved state version. */
101	#define DMAR_SAVED_STATE_VERSION 1
102
103
104	/*********************************************************************************************************************************
105	* Structures and Typedefs *
106	*********************************************************************************************************************************/
107	/**
108	* The shared DMAR device state.
109	*/
110	typedef struct DMAR
111	{
112	/** IOMMU device index. */
113	uint32_t idxIommu;
114	/** DMAR magic. */
115	uint32_t u32Magic;
116
117	/** The MMIO handle. */
118	IOMMMIOHANDLE hMmio;
119
120	/** Registers (group 0). */
121	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
122	/** Registers (group 1). */
123	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
124
125	/** @name Register copies for a tiny bit faster and more convenient access.
126	* @{ */
127	/** Copy of CAP_REG. */
128	uint64_t fCap;
129	/** Copy of ECAP_REG. */
130	uint64_t fExtCap;
131	/** @} */
132
133	#ifdef VBOX_WITH_STATISTICS
134	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
135	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
136	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
137	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
138
139	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
140	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
141
142	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
143	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
144	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
145	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
146
147	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
148	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
149	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
150	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
151	#endif
152	} DMAR;
153	/** Pointer to the DMAR device state. */
154	typedef DMAR *PDMAR;
155	/** Pointer to the const DMAR device state. */
156	typedef const DMAR *PCDMAR;
157
158	/**
159	* The ring-3 DMAR device state.
160	*/
161	typedef struct DMARR3
162	{
163	/** Device instance. */
164	PPDMDEVINSR3 pDevInsR3;
165	/** The IOMMU helper. */
166	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
167	} DMARR3;
168	/** Pointer to the ring-3 DMAR device state. */
169	typedef DMARR3 *PDMARR3;
170	/** Pointer to the const ring-3 DMAR device state. */
171	typedef const DMARR3 *PCDMARR3;
172
173	/**
174	* The ring-0 DMAR device state.
175	*/
176	typedef struct DMARR0
177	{
178	/** Device instance. */
179	PPDMDEVINSR0 pDevInsR0;
180	/** The IOMMU helper. */
181	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
182	} DMARR0;
183	/** Pointer to the ring-0 IOMMU device state. */
184	typedef DMARR0 *PDMARR0;
185	/** Pointer to the const ring-0 IOMMU device state. */
186	typedef const DMARR0 *PCDMARR0;
187
188	/**
189	* The raw-mode DMAR device state.
190	*/
191	typedef struct DMARRC
192	{
193	/** Device instance. */
194	PPDMDEVINSRC pDevInsRC;
195	/** The IOMMU helper. */
196	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
197	} DMARRC;
198	/** Pointer to the raw-mode DMAR device state. */
199	typedef DMARRC *PDMARRC;
200	/** Pointer to the const raw-mode DMAR device state. */
201	typedef const DMARRC *PCIDMARRC;
202
203	/** The DMAR device state for the current context. */
204	typedef CTX_SUFF(DMAR) DMARCC;
205	/** Pointer to the DMAR device state for the current context. */
206	typedef CTX_SUFF(PDMAR) PDMARCC;
207
208
209	/*********************************************************************************************************************************
210	* Global Variables *
211	*********************************************************************************************************************************/
212	/**
213	* Read-write masks for DMAR registers (group 0).
214	*/
215	static uint32_t const g_au32RwMasks0[] =
216	{
217	/* Offset Register Low High */
218	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
219	/* 0x004 Reserved */ 0,
220	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
221	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
222	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
223	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
224	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
225	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
226	/* 0x030 Reserved */ 0,
227	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
228	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
229	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
230	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
231	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
232	/* 0x048 Reserved */ 0, 0,
233	/* 0x050 Reserved */ 0, 0,
234	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
235	/* 0x060 Reserved */ 0,
236	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
237	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
238	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
239	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
240	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
241	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
242	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
243	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
244	/* 0x098 Reserved */ 0,
245	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
246	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
247	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
248	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
249	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
250	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
251	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
252	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
253	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
254	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
255	/* 0x0d8 Reserved */ 0,
256	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
257	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
258	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
259	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
260	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
261	/* 0x0f0 Reserved */ 0, 0,
262	/* 0x0f8 Reserved */ 0, 0,
263	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
264	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
265	/* 0x110 Reserved */ 0, 0,
266	/* 0x118 Reserved */ 0, 0,
267	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
268	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
269	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
270	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
271	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
272	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
273	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
274	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
275	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
276	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
277	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
278	/* 0x178 Reserved */ 0, 0,
279	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
280	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
281	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
282	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
283	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
284	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
285	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
286	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
287	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
288	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
289	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
290	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
291	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
292	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
293	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
294	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
295	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
296	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
297	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
298	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
299	};
300	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
301
302	/**
303	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
304	*/
305	static uint32_t const g_au32Rw1cMasks0[] =
306	{
307	/* Offset Register Low High */
308	/* 0x000 VER_REG */ 0,
309	/* 0x004 Reserved */ 0,
310	/* 0x008 CAP_REG */ 0, 0,
311	/* 0x010 ECAP_REG */ 0, 0,
312	/* 0x018 GCMD_REG */ 0,
313	/* 0x01c GSTS_REG */ 0,
314	/* 0x020 RTADDR_REG */ 0, 0,
315	/* 0x028 CCMD_REG */ 0, 0,
316	/* 0x030 Reserved */ 0,
317	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
318	/* 0x038 FECTL_REG */ 0,
319	/* 0x03c FEDATA_REG */ 0,
320	/* 0x040 FEADDR_REG */ 0,
321	/* 0x044 FEUADDR_REG */ 0,
322	/* 0x048 Reserved */ 0, 0,
323	/* 0x050 Reserved */ 0, 0,
324	/* 0x058 AFLOG_REG */ 0, 0,
325	/* 0x060 Reserved */ 0,
326	/* 0x064 PMEN_REG */ 0,
327	/* 0x068 PLMBASE_REG */ 0,
328	/* 0x06c PLMLIMIT_REG */ 0,
329	/* 0x070 PHMBASE_REG */ 0, 0,
330	/* 0x078 PHMLIMIT_REG */ 0, 0,
331	/* 0x080 IQH_REG */ 0, 0,
332	/* 0x088 IQT_REG */ 0, 0,
333	/* 0x090 IQA_REG */ 0, 0,
334	/* 0x098 Reserved */ 0,
335	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
336	/* 0x0a0 IECTL_REG */ 0,
337	/* 0x0a4 IEDATA_REG */ 0,
338	/* 0x0a8 IEADDR_REG */ 0,
339	/* 0x0ac IEUADDR_REG */ 0,
340	/* 0x0b0 IQERCD_REG */ 0, 0,
341	/* 0x0b8 IRTA_REG */ 0, 0,
342	/* 0x0c0 PQH_REG */ 0, 0,
343	/* 0x0c8 PQT_REG */ 0, 0,
344	/* 0x0d0 PQA_REG */ 0, 0,
345	/* 0x0d8 Reserved */ 0,
346	/* 0x0dc PRS_REG */ 0,
347	/* 0x0e0 PECTL_REG */ 0,
348	/* 0x0e4 PEDATA_REG */ 0,
349	/* 0x0e8 PEADDR_REG */ 0,
350	/* 0x0ec PEUADDR_REG */ 0,
351	/* 0x0f0 Reserved */ 0, 0,
352	/* 0x0f8 Reserved */ 0, 0,
353	/* 0x100 MTRRCAP_REG */ 0, 0,
354	/* 0x108 MTRRDEF_REG */ 0, 0,
355	/* 0x110 Reserved */ 0, 0,
356	/* 0x118 Reserved */ 0, 0,
357	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
358	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
359	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
360	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
361	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
362	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
363	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
364	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
365	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
366	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
367	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
368	/* 0x178 Reserved */ 0, 0,
369	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
370	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
371	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
372	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
373	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
374	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
375	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
376	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
377	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
378	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
379	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
380	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
381	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
382	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
383	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
384	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
385	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
386	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
387	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
388	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
389	};
390	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
391
392	/**
393	* Read-write masks for DMAR registers (group 1).
394	*/
395	static uint32_t const g_au32RwMasks1[] =
396	{
397	/* Offset Register Low High */
398	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
399	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
400	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
401	/* 0xe18 VCMDRSVD_REG */ 0, 0,
402	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
403	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
404	/* 0xe30 Reserved */ 0, 0,
405	/* 0xe38 Reserved */ 0, 0,
406	/* 0xe40 Reserved */ 0, 0,
407	/* 0xe48 Reserved */ 0, 0,
408	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
409	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
410	/* 0xe60 Reserved */ 0, 0,
411	/* 0xe68 Reserved */ 0, 0,
412	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
413	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
414	};
415	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
416	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
417
418	/**
419	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
420	*/
421	static uint32_t const g_au32Rw1cMasks1[] =
422	{
423	/* Offset Register Low High */
424	/* 0xe00 VCCAP_REG */ 0, 0,
425	/* 0xe08 VCMD_EO_REG */ 0, 0,
426	/* 0xe10 VCMD_REG */ 0, 0,
427	/* 0xe18 VCMDRSVD_REG */ 0, 0,
428	/* 0xe20 VCRSP_REG */ 0, 0,
429	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
430	/* 0xe30 Reserved */ 0, 0,
431	/* 0xe38 Reserved */ 0, 0,
432	/* 0xe40 Reserved */ 0, 0,
433	/* 0xe48 Reserved */ 0, 0,
434	/* 0xe50 IVA_REG */ 0, 0,
435	/* 0xe58 IOTLB_REG */ 0, 0,
436	/* 0xe60 Reserved */ 0, 0,
437	/* 0xe68 Reserved */ 0, 0,
438	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
439	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
440	};
441	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
442
443	/** Array of RW masks for each register group. */
444	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
445
446	/** Array of RW1C masks for each register group. */
447	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
448
449	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
450	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
451
452
453	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
454	/**
455	* Gets the number of supported adjusted guest-address width (SAGAW) in bits given a
456	* CAP_REG.SAGAW value.
457	*
458	* @returns Number of SAGAW bits.
459	* @param uSagaw The CAP_REG.SAGAW value.
460	*/
461	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
462	{
463	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
464	return 30 + (uSagaw * 9);
465	return 0;
466	}
467
468
469	/**
470	* Gets the supported adjusted guest-address width (SAGAW) given the maximum guest
471	* address width (MGAW).
472	*
473	* @returns The CAP_REG.SAGAW value.
474	* @param uMgaw The CAP_REG.MGAW value.
475	*/
476	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
477	{
478	switch (uMgaw + 1)
479	{
480	case 39: return 1;
481	case 48: return 2;
482	case 57: return 3;
483	}
484	return 0;
485	}
486
487
488	/**
489	* Gets the group the register belongs to given its MMIO offset.
490	*
491	* @returns Pointer to the first element of the register group.
492	* @param pThis The shared DMAR device state.
493	* @param offReg The MMIO offset of the register.
494	* @param cbReg The size of the access being made (for bounds checking on
495	* debug builds).
496	* @param pIdxGroup Where to store the index of the register group the register
497	* belongs to.
498	*/
499	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
500	{
501	uint16_t const offLast = offReg + cbReg - 1;
502	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
503	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
504
505	uint8_t *const apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
506	*pIdxGroup = !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
507	return apbRegs[*pIdxGroup];
508	}
509
510
511	/**
512	* Writes a 64-bit register with the exactly the supplied value.
513	*
514	* @param pThis The shared DMAR device state.
515	* @param offReg The MMIO offset of the register.
516	* @param uReg The 64-bit value to write.
517	*/
518	DECLINLINE(void) dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
519	{
520	uint8_t idxGroup;
521	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
522	NOREF(idxGroup);
523	(uint64_t )(pabRegs + offReg) = uReg;
524	}
525
526
527	/**
528	* Writes a 32-bit register with the exactly the supplied value.
529	*
530	* @param pThis The shared DMAR device state.
531	* @param offReg The MMIO offset of the register.
532	* @param uReg The 32-bit value to write.
533	*/
534	DECLINLINE(void) dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
535	{
536	uint8_t idxGroup;
537	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
538	NOREF(idxGroup);
539	(uint32_t )(pabRegs + offReg) = uReg;
540	}
541
542
543	/**
544	* Reads a 64-bit register with exactly the value it contains.
545	*
546	* @param pThis The shared DMAR device state.
547	* @param offReg The MMIO offset of the register.
548	* @param puReg Where to store the raw 64-bit register value.
549	* @param pfRwMask Where to store the RW mask corresponding to this register.
550	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
551	*/
552	DECLINLINE(void) dmarRegReadRaw64(PDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
553	{
554	uint8_t idxGroup;
555	uint8_t const *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
556	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
557	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
558	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
559	puReg = (uint64_t *)(pabRegs + offReg);
560	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
561	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
562	}
563
564
565	/**
566	* Reads a 32-bit register with exactly the value it contains.
567	*
568	* @param pThis The shared DMAR device state.
569	* @param offReg The MMIO offset of the register.
570	* @param puReg Where to store the raw 32-bit register value.
571	* @param pfRwMask Where to store the RW mask corresponding to this register.
572	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
573	*/
574	DECLINLINE(void) dmarRegReadRaw32(PDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
575	{
576	uint8_t idxGroup;
577	uint8_t const *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
578	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
579	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
580	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
581	puReg = (uint32_t *)(pabRegs + offReg);
582	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
583	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
584	}
585
586
587	/**
588	* Writes a 64-bit register as it would be when written by software.
589	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
590	*
591	* @returns The value that's actually written to the register.
592	* @param pThis The shared DMAR device state.
593	* @param offReg The MMIO offset of the register.
594	* @param uReg The 64-bit value to write.
595	*/
596	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
597	{
598	/* Read current value from the 64-bit register. */
599	uint64_t uCurReg;
600	uint64_t fRwMask;
601	uint64_t fRw1cMask;
602	dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
603
604	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
605	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
606	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
607	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
608
609	/* Write new value to the 64-bit register. */
610	dmarRegWriteRaw64(pThis, offReg, uNewReg);
611	return uNewReg;
612	}
613
614
615	/**
616	* Writes a 32-bit register as it would be when written by software.
617	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
618	*
619	* @returns The value that's actually written to the register.
620	* @param pThis The shared DMAR device state.
621	* @param offReg The MMIO offset of the register.
622	* @param uReg The 32-bit value to write.
623	*/
624	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
625	{
626	/* Read current value from the 32-bit register. */
627	uint32_t uCurReg;
628	uint32_t fRwMask;
629	uint32_t fRw1cMask;
630	dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
631
632	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
633	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
634	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
635	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
636
637	/* Write new value to the 32-bit register. */
638	dmarRegWriteRaw32(pThis, offReg, uNewReg);
639	return uNewReg;
640	}
641
642
643	/**
644	* Reads a 64-bit register as it would be when read by software.
645	*
646	* @returns The 64-bit register value.
647	* @param pThis The shared DMAR device state.
648	* @param offReg The MMIO offset of the register.
649	*/
650	static uint64_t dmarRegRead64(PDMAR pThis, uint16_t offReg)
651	{
652	uint64_t uCurReg;
653	uint64_t fRwMask;
654	uint64_t fRw1cMask;
655	dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
656	NOREF(fRwMask); NOREF(fRw1cMask);
657	return uCurReg;
658	}
659
660
661	/**
662	* Reads a 32-bit register as it would be when read by software.
663	*
664	* @returns The 32-bit register value.
665	* @param pThis The shared DMAR device state.
666	* @param offReg The MMIO offset of the register.
667	*/
668	static uint32_t dmarRegRead32(PDMAR pThis, uint16_t offReg)
669	{
670	uint32_t uCurReg;
671	uint32_t fRwMask;
672	uint32_t fRw1cMask;
673	dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
674	NOREF(fRwMask); NOREF(fRw1cMask);
675	return uCurReg;
676	}
677
678
679	/**
680	* Handles writes to IQT_REG.
681	*
682	* @returns Strict VBox status code.
683	* @param pDevIns The IOMMU device instance.
684	* @param off The MMIO register offset.
685	* @param uIqtReg The value written to IQT_REG.
686	*/
687	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t off, uint64_t uIqtReg)
688	{
689	/* We only care about the low dword of VTD_MMIO_OFF_IQT_REG. */
690	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
691	if (off == VTD_MMIO_OFF_IQT_REG)
692	{
693	/* Verify if the queue tail offset is aligned according to the descriptor width in IQA_REG. */
694	uint16_t const offQueueTail = VTD_IQT_REG_GET_QT(uIqtReg);
695	uint64_t const uIqaReg = dmarRegRead64(pThis, VTD_MMIO_OFF_IQA_REG);
696	uint8_t const uDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
697	if ( uDw != VTD_IQA_REG_DW_256_BIT
698	\|\| !(offQueueTail & 0x1f))
699	{
700	/** @todo IOMMU: Figure out what to do here, like waking up worker thread or
701	* something. */
702	}
703	else
704	{
705	/* Raise invalidation queue error as queue tail not aligned to 256-bits. */
706	/** @todo IOMMU: Raise error. */
707	}
708	}
709	return VINF_SUCCESS;
710	}
711
712
713	/**
714	* Memory access bulk (one or more 4K pages) request from a device.
715	*
716	* @returns VBox status code.
717	* @param pDevIns The IOMMU device instance.
718	* @param idDevice The device ID (bus, device, function).
719	* @param cIovas The number of addresses being accessed.
720	* @param pauIovas The I/O virtual addresses for each page being accessed.
721	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
722	* @param paGCPhysSpa Where to store the translated physical addresses.
723	*
724	* @thread Any.
725	*/
726	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
727	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
728	{
729	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
730	return VERR_NOT_IMPLEMENTED;
731	}
732
733
734	/**
735	* Memory access transaction from a device.
736	*
737	* @returns VBox status code.
738	* @param pDevIns The IOMMU device instance.
739	* @param idDevice The device ID (bus, device, function).
740	* @param uIova The I/O virtual address being accessed.
741	* @param cbIova The size of the access.
742	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
743	* @param pGCPhysSpa Where to store the translated system physical address.
744	* @param pcbContiguous Where to store the number of contiguous bytes translated
745	* and permission-checked.
746	*
747	* @thread Any.
748	*/
749	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
750	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
751	{
752	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
753	return VERR_NOT_IMPLEMENTED;
754	}
755
756
757	/**
758	* Interrupt remap request from a device.
759	*
760	* @returns VBox status code.
761	* @param pDevIns The IOMMU device instance.
762	* @param idDevice The device ID (bus, device, function).
763	* @param pMsiIn The source MSI.
764	* @param pMsiOut Where to store the remapped MSI.
765	*/
766	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
767	{
768	RT_NOREF3(idDevice, pMsiIn, pMsiOut);
769	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
770	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap)); NOREF(pThis);
771
772	return VERR_NOT_IMPLEMENTED;
773	}
774
775
776	/**
777	* @callback_method_impl{FNIOMMMIONEWWRITE}
778	*/
779	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
780	{
781	RT_NOREF1(pvUser);
782	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
783
784	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
785	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
786
787	uint16_t const offReg = off;
788	uint16_t const offLast = offReg + cb - 1;
789	if (DMAR_IS_MMIO_OFF_VALID(offLast))
790	{
791	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv)
792	: dmarRegWrite32(pThis, offReg, (uint32_t )pv);
793	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
794	switch (off)
795	{
796	case VTD_MMIO_OFF_IQT_REG:
797	case VTD_MMIO_OFF_IQT_REG + 4:
798	{
799	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
800	break;
801	}
802	}
803
804	LogFlowFunc(("offReg=%#x rc=%Rrc\n", offReg, VBOXSTRICTRC_VAL(rcStrict)));
805	return rcStrict;
806	}
807
808	return VINF_IOM_MMIO_UNUSED_FF;
809	}
810
811
812	/**
813	* @callback_method_impl{FNIOMMMIONEWREAD}
814	*/
815	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
816	{
817	RT_NOREF1(pvUser);
818	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
819
820	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
821	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
822
823	uint16_t const offReg = off;
824	uint16_t const offLast = offReg + cb - 1;
825	if (DMAR_IS_MMIO_OFF_VALID(offLast))
826	{
827	if (cb == 8)
828	{
829	(uint64_t )pv = dmarRegRead64(pThis, offReg);
830	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
831	}
832	else
833	{
834	(uint32_t )pv = dmarRegRead32(pThis, offReg);
835	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
836	}
837
838	return VINF_SUCCESS;
839	}
840
841	return VINF_IOM_MMIO_UNUSED_FF;
842	}
843
844
845	#ifdef IN_RING3
846	/**
847	* Initializes all registers in the DMAR unit.
848	*
849	* @param pDevIns The IOMMU device instance.
850	*/
851	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
852	{
853	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
854	RT_ZERO(pThis->abRegs0);
855	RT_ZERO(pThis->abRegs1);
856
857	/*
858	* Initialize registers not mutable by software prior to initializing other registers.
859	*/
860	/* VER_REG */
861	{
862	uint8_t const uVer = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
863	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
864	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, uVer);
865	}
866
867	uint8_t const fFlts = 1; /* First-Level translation support. */
868	uint8_t const fSlts = 1; /* Second-Level translation support. */
869	uint8_t const fPt = 1; /* Pass-Through support. */
870	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
871	uint8_t const fNest = 0; /* Nested translation support. */
872
873	/* CAP_REG */
874	{
875	uint8_t cGstPhysAddrBits;
876	uint8_t cGstLinearAddrBits;
877	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
878
879	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
880	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
881	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
882	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
883	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
884	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
885	uint8_t const fMamv = (fSl2gp ? /* Maximum address mask value (for second-level invalidations). */
886	X86_PAGE_1G_SHIFT : X86_PAGE_2M_SHIFT) - X86_PAGE_4K_SHIFT;
887	uint8_t const fNd = 2; /* Number of domains (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
888	7=Reserved). */
889	uint8_t const fPsi = 1; /* Page selective invalidation. */
890	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
891	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
892	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
893
894	pThis->fCap = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
895	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
896	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
897	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
898	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
899	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
900	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
901	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
902	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
903	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
904	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
905	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
906	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
907	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
908	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
909	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
910	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
911	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
912	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, 0) /* Whether we invalidate interrupt cache on SIRTP flow. */
913	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, 0); /* Whether we invalidate translation cache on SRTP flow. */
914	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCap);
915	}
916
917	/* ECAP_REG */
918	{
919	uint8_t const fQi = 1; /* Queued invalidations. */
920	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
921	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
922	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
923	uint8_t const fSrs = 1; /* Supervisor request support. */
924	uint8_t const fEim = 1; /* Extended interrupt mode.*/
925	uint8_t const fAdms = 1; /* Abort DMA mode support. */
926
927	pThis->fExtCap = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
928	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, 1)
929	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
930	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
931	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
932	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
933	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
934	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
935	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
936	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
937	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
938	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
939	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
940	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
941	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
942	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
943	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
944	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
945	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
946	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
947	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
948	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
949	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
950	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
951	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
952	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
953	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
954	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
955	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
956	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCap);
957	}
958
959	/*
960	* Initialize registers mutable by software.
961	*/
962	/* FECTL_REG */
963	{
964	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
965	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
966	}
967
968	/* ICETL_REG */
969	{
970	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
971	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
972	}
973
974	#ifdef VBOX_STRICT
975	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
976	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
977	#endif
978	}
979
980
981	/**
982	* @interface_method_impl{PDMDEVREG,pfnReset}
983	*/
984	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
985	{
986	RT_NOREF1(pDevIns);
987	LogFlowFunc(("\n"));
988
989	dmarR3RegsInit(pDevIns);
990	}
991
992
993	/**
994	* @interface_method_impl{PDMDEVREG,pfnDestruct}
995	*/
996	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
997	{
998	RT_NOREF(pDevIns);
999	LogFlowFunc(("\n"));
1000	return VINF_SUCCESS;
1001	}
1002
1003
1004	/**
1005	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1006	*/
1007	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1008	{
1009	RT_NOREF(pCfg);
1010
1011	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1012	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
1013	pThisR3->pDevInsR3 = pDevIns;
1014
1015	LogFlowFunc(("iInstance=%d\n", iInstance));
1016	NOREF(iInstance);
1017
1018	/*
1019	* Register the IOMMU with PDM.
1020	*/
1021	PDMIOMMUREGR3 IommuReg;
1022	RT_ZERO(IommuReg);
1023	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
1024	IommuReg.pfnMemAccess = iommuIntelMemAccess;
1025	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
1026	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
1027	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
1028	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
1029	if (RT_FAILURE(rc))
1030	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
1031	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
1032	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1033	N_("IOMMU helper version mismatch; got %#x expected %#x"),
1034	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
1035	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
1036	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1037	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
1038	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
1039	/*
1040	* Use PDM's critical section (via helpers) for the IOMMU device.
1041	*/
1042	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1043	AssertRCReturn(rc, rc);
1044
1045	/*
1046	* Initialize PCI configuration registers.
1047	*/
1048	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1049	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1050
1051	/* Header. */
1052	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
1053	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
1054	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
1055	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
1056	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
1057	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
1058	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
1059	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
1060
1061	/** @todo VTD: Chipset spec says PCI Express Capability Id. Relevant for us? */
1062	PDMPciDevSetStatus(pPciDev, 0);
1063	PDMPciDevSetCapabilityList(pPciDev, 0);
1064
1065	/** @todo VTD: VTBAR at 0x180? */
1066
1067	/*
1068	* Register the PCI function with PDM.
1069	*/
1070	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
1071	AssertLogRelRCReturn(rc, rc);
1072
1073	/** @todo VTD: Register MSI but what's the MSI capability offset? */
1074	#if 0
1075	/*
1076	* Register MSI support for the PCI device.
1077	* This must be done -after- registering it as a PCI device!
1078	*/
1079	#endif
1080
1081	/*
1082	* Register MMIO region.
1083	*/
1084	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
1085	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
1086	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
1087	"Intel-IOMMU", &pThis->hMmio);
1088	AssertRCReturn(rc, rc);
1089
1090	#ifdef VBOX_WITH_STATISTICS
1091	/*
1092	* Statistics.
1093	*/
1094	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
1095	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
1096
1097	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
1098	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
1099
1100	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
1101	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
1102
1103	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
1104	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
1105
1106	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
1107	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
1108
1109	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
1110	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
1111
1112	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
1113	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
1114	#endif
1115
1116	/*
1117	* Initialize registers.
1118	*/
1119	dmarR3RegsInit(pDevIns);
1120
1121	/*
1122	* Log some of the features exposed to software.
1123	*/
1124	uint32_t const uVerReg = dmarRegRead32(pThis, VTD_MMIO_OFF_VER_REG);
1125	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_MGAW) + 1;
1126	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_SAGAW));
1127	uint16_t const offFrcd = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_FRO);
1128	uint16_t const offIva = RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_IRO);
1129	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n", DMAR_LOG_PFX,
1130	RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
1131	pThis->fCap, pThis->fExtCap, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
1132	return VINF_SUCCESS;
1133	}
1134
1135	#else
1136
1137	/**
1138	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1139	*/
1140	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
1141	{
1142	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1143	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1144	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
1145	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
1146
1147	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
1148	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1149	AssertRCReturn(rc, rc);
1150
1151	/* Set up the MMIO RZ handlers. */
1152	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
1153	AssertRCReturn(rc, rc);
1154
1155	/* Set up the IOMMU RZ callbacks. */
1156	PDMIOMMUREGCC IommuReg;
1157	RT_ZERO(IommuReg);
1158	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
1159	IommuReg.idxIommu = pThis->idxIommu;
1160	IommuReg.pfnMemAccess = iommuIntelMemAccess;
1161	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
1162	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
1163	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
1164
1165	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
1166	AssertRCReturn(rc, rc);
1167	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
1168	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
1169	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
1170	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
1171	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
1172
1173	return VINF_SUCCESS;
1174	}
1175
1176	#endif
1177
1178
1179	/**
1180	* The device registration structure.
1181	*/
1182	PDMDEVREG const g_DeviceIommuIntel =
1183	{
1184	/* .u32Version = */ PDM_DEVREG_VERSION,
1185	/* .uReserved0 = */ 0,
1186	/* .szName = */ "iommu-intel",
1187	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1188	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
1189	/* .cMaxInstances = */ 1,
1190	/* .uSharedVersion = */ 42,
1191	/* .cbInstanceShared = */ sizeof(DMAR),
1192	/* .cbInstanceCC = */ sizeof(DMARCC),
1193	/* .cbInstanceRC = */ sizeof(DMARRC),
1194	/* .cMaxPciDevices = */ 1,
1195	/* .cMaxMsixVectors = */ 0,
1196	/* .pszDescription = */ "IOMMU (Intel)",
1197	#if defined(IN_RING3)
1198	/* .pszRCMod = */ "VBoxDDRC.rc",
1199	/* .pszR0Mod = */ "VBoxDDR0.r0",
1200	/* .pfnConstruct = */ iommuIntelR3Construct,
1201	/* .pfnDestruct = */ iommuIntelR3Destruct,
1202	/* .pfnRelocate = */ NULL,
1203	/* .pfnMemSetup = */ NULL,
1204	/* .pfnPowerOn = */ NULL,
1205	/* .pfnReset = */ iommuIntelR3Reset,
1206	/* .pfnSuspend = */ NULL,
1207	/* .pfnResume = */ NULL,
1208	/* .pfnAttach = */ NULL,
1209	/* .pfnDetach = */ NULL,
1210	/* .pfnQueryInterface = */ NULL,
1211	/* .pfnInitComplete = */ NULL,
1212	/* .pfnPowerOff = */ NULL,
1213	/* .pfnSoftReset = */ NULL,
1214	/* .pfnReserved0 = */ NULL,
1215	/* .pfnReserved1 = */ NULL,
1216	/* .pfnReserved2 = */ NULL,
1217	/* .pfnReserved3 = */ NULL,
1218	/* .pfnReserved4 = */ NULL,
1219	/* .pfnReserved5 = */ NULL,
1220	/* .pfnReserved6 = */ NULL,
1221	/* .pfnReserved7 = */ NULL,
1222	#elif defined(IN_RING0)
1223	/* .pfnEarlyConstruct = */ NULL,
1224	/* .pfnConstruct = */ iommuIntelRZConstruct,
1225	/* .pfnDestruct = */ NULL,
1226	/* .pfnFinalDestruct = */ NULL,
1227	/* .pfnRequest = */ NULL,
1228	/* .pfnReserved0 = */ NULL,
1229	/* .pfnReserved1 = */ NULL,
1230	/* .pfnReserved2 = */ NULL,
1231	/* .pfnReserved3 = */ NULL,
1232	/* .pfnReserved4 = */ NULL,
1233	/* .pfnReserved5 = */ NULL,
1234	/* .pfnReserved6 = */ NULL,
1235	/* .pfnReserved7 = */ NULL,
1236	#elif defined(IN_RC)
1237	/* .pfnConstruct = */ iommuIntelRZConstruct,
1238	/* .pfnReserved0 = */ NULL,
1239	/* .pfnReserved1 = */ NULL,
1240	/* .pfnReserved2 = */ NULL,
1241	/* .pfnReserved3 = */ NULL,
1242	/* .pfnReserved4 = */ NULL,
1243	/* .pfnReserved5 = */ NULL,
1244	/* .pfnReserved6 = */ NULL,
1245	/* .pfnReserved7 = */ NULL,
1246	#else
1247	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1248	#endif
1249	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1250	};
1251
1252	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1253

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88530

Download in other formats: