DevIommuIntel.cpp@ 88588

Last change on this file since 88588 was 88584, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 WIP.
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1	/* $Id: DevIommuIntel.cpp 88584 2021-04-19 15:54:58Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/string.h>
27
28
29	/*********************************************************************************************************************************
30	* Defined Constants And Macros *
31	*********************************************************************************************************************************/
32	/** Gets the low uint32_t of a uint64_t or something equivalent.
33	*
34	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
35	* used as it asserts for correctness when compiling on certain compilers). */
36	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
37
38	/** Gets the high uint32_t of a uint64_t or something equivalent.
39	*
40	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
41	* used as it asserts for correctness when compiling on certain compilers). */
42	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
43
44	/** Asserts MMIO access' offset and size are valid or returns appropriate error
45	* code suitable for returning from MMIO access handlers. */
46	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
47	do { \
48	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
49	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
50	} while (0);
51
52	/** Checks whether the MMIO offset is valid. */
53	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
54	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
55
56	/** Acquires the DMAR lock but returns with the given error code on failure. */
57	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
58	do { \
59	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
60	{ /* likely */ } \
61	else \
62	return (a_rcBusy); \
63	} while (0)
64
65	/** Release the DMAR lock. */
66	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
67
68	/** Checks whether the calling thread is the owner of the DMAR lock. */
69	#define DMAR_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)
70
71	/** Asserts that the calling thread owns the DMAR lock. */
72	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
73	do { \
74	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
75	RT_NOREF1(a_pThisCC); \
76	} while (0)
77
78	/** The number of fault recording registers our implementation supports.
79	* Normal guest operation shouldn't trigger faults anyway, so we only support the
80	* minimum number of registers (which is 1).
81	*
82	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
83	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
84
85	/** Offset of first register in group 0. */
86	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
87	/** Offset of last register in group 0 (inclusive). */
88	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
89	/** Last valid offset in group 0 (exclusive). */
90	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
91	/** Size of the group 0 (in bytes). */
92	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
93	/*< Implementation-specific MMIO offset of IVA_REG. /
94	#define DMAR_MMIO_OFF_IVA_REG 0xe50
95	/*< Implementation-specific MMIO offset of IOTLB_REG. /
96	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
97	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
98	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
99	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
100	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
101	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
102
103	/** Offset of first register in group 1. */
104	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
105	/** Offset of last register in group 1 (inclusive). */
106	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
107	/** Last valid offset in group 1 (exclusive). */
108	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
109	/** Size of the group 1 (in bytes). */
110	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
111
112	/** DMAR implementation's major version number (exposed to software).
113	* We report 6 as the major version since we support queued invalidations as
114	* software may make assumptions based on that.
115	*
116	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
117	#define DMAR_VER_MAJOR 6
118	/** DMAR implementation's minor version number (exposed to software). */
119	#define DMAR_VER_MINOR 0
120
121	/** Release log prefix string. */
122	#define DMAR_LOG_PFX "Intel-IOMMU"
123	/** The current saved state version. */
124	#define DMAR_SAVED_STATE_VERSION 1
125
126
127	/*********************************************************************************************************************************
128	* Structures and Typedefs *
129	*********************************************************************************************************************************/
130	/**
131	* DMAR error diagnostics.
132	*
133	* @note Members of this enum are used as array indices, so no gaps are allowed.
134	* Please update g_apsz when you add new fields to this enum.
135	*/
136	typedef enum
137	{
138	kDmarDiag_None = 0,
139	kDmarDiag_IqtReg_Qt_NotAligned,
140	/* Last member for determining array index limit. */
141	kDmarDiag_End
142	} DMARDIAG;
143	AssertCompileSize(DMARDIAG, 4);
144
145	/** DMAR diagnostic enum description expansion. */
146	#define DMARDIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
147
148	/** DMAR diagnostics description. */
149	static const char *const g_apszDmarDiagDesc[] =
150	{
151	DMARDIAG_DESC(kNone, "None" ),
152	DMARDIAG_DESC(kDmarDiag_IqtReg_Qt_NotAligned, "IqtReg_Qt_NotAligned")
153	/* kDmarDiag_End */
154	};
155	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
156	#undef DMARDIAG_DESC
157
158	/**
159	* The shared DMAR device state.
160	*/
161	typedef struct DMAR
162	{
163	/** IOMMU device index. */
164	uint32_t idxIommu;
165	/** DMAR magic. */
166	uint32_t u32Magic;
167
168	/** The MMIO handle. */
169	IOMMMIOHANDLE hMmio;
170
171	/** Registers (group 0). */
172	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
173	/** Registers (group 1). */
174	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
175
176	/** @name Register copies for a tiny bit faster and more convenient access.
177	* @{ */
178	/** Copy of VER_REG. */
179	uint8_t uVerReg;
180	/** Alignment. */
181	uint8_t abPadding[3];
182	/** Error diagnostic. */
183	DMARDIAG enmDiag;
184	/** Copy of CAP_REG. */
185	uint64_t fCap;
186	/** Copy of ECAP_REG. */
187	uint64_t fExtCap;
188	/** @} */
189
190	#ifdef VBOX_WITH_STATISTICS
191	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
192	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
193	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
194	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
195
196	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
197	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
198
199	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
200	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
201	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
202	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
203
204	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
205	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
206	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
207	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
208	#endif
209	} DMAR;
210	/** Pointer to the DMAR device state. */
211	typedef DMAR *PDMAR;
212	/** Pointer to the const DMAR device state. */
213	typedef const DMAR *PCDMAR;
214
215	/**
216	* The ring-3 DMAR device state.
217	*/
218	typedef struct DMARR3
219	{
220	/** Device instance. */
221	PPDMDEVINSR3 pDevInsR3;
222	/** The IOMMU helper. */
223	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
224	} DMARR3;
225	/** Pointer to the ring-3 DMAR device state. */
226	typedef DMARR3 *PDMARR3;
227	/** Pointer to the const ring-3 DMAR device state. */
228	typedef const DMARR3 *PCDMARR3;
229
230	/**
231	* The ring-0 DMAR device state.
232	*/
233	typedef struct DMARR0
234	{
235	/** Device instance. */
236	PPDMDEVINSR0 pDevInsR0;
237	/** The IOMMU helper. */
238	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
239	} DMARR0;
240	/** Pointer to the ring-0 IOMMU device state. */
241	typedef DMARR0 *PDMARR0;
242	/** Pointer to the const ring-0 IOMMU device state. */
243	typedef const DMARR0 *PCDMARR0;
244
245	/**
246	* The raw-mode DMAR device state.
247	*/
248	typedef struct DMARRC
249	{
250	/** Device instance. */
251	PPDMDEVINSRC pDevInsRC;
252	/** The IOMMU helper. */
253	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
254	} DMARRC;
255	/** Pointer to the raw-mode DMAR device state. */
256	typedef DMARRC *PDMARRC;
257	/** Pointer to the const raw-mode DMAR device state. */
258	typedef const DMARRC *PCIDMARRC;
259
260	/** The DMAR device state for the current context. */
261	typedef CTX_SUFF(DMAR) DMARCC;
262	/** Pointer to the DMAR device state for the current context. */
263	typedef CTX_SUFF(PDMAR) PDMARCC;
264	/** Pointer to the const DMAR device state for the current context. */
265	typedef const CTX_SUFF(PDMAR) PCDMARCC;
266
267
268	/*********************************************************************************************************************************
269	* Global Variables *
270	*********************************************************************************************************************************/
271	/**
272	* Read-write masks for DMAR registers (group 0).
273	*/
274	static uint32_t const g_au32RwMasks0[] =
275	{
276	/* Offset Register Low High */
277	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
278	/* 0x004 Reserved */ 0,
279	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
280	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
281	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
282	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
283	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
284	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
285	/* 0x030 Reserved */ 0,
286	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
287	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
288	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
289	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
290	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
291	/* 0x048 Reserved */ 0, 0,
292	/* 0x050 Reserved */ 0, 0,
293	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
294	/* 0x060 Reserved */ 0,
295	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
296	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
297	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
298	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
299	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
300	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
301	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
302	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
303	/* 0x098 Reserved */ 0,
304	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
305	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
306	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
307	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
308	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
309	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
310	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
311	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
312	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
313	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
314	/* 0x0d8 Reserved */ 0,
315	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
316	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
317	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
318	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
319	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
320	/* 0x0f0 Reserved */ 0, 0,
321	/* 0x0f8 Reserved */ 0, 0,
322	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
323	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
324	/* 0x110 Reserved */ 0, 0,
325	/* 0x118 Reserved */ 0, 0,
326	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
327	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
328	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
329	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
330	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
331	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
332	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
333	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
334	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
335	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
336	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
337	/* 0x178 Reserved */ 0, 0,
338	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
339	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
340	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
341	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
342	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
343	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
344	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
345	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
346	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
347	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
348	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
349	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
350	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
351	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
352	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
353	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
354	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
355	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
356	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
357	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
358	};
359	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
360
361	/**
362	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
363	*/
364	static uint32_t const g_au32Rw1cMasks0[] =
365	{
366	/* Offset Register Low High */
367	/* 0x000 VER_REG */ 0,
368	/* 0x004 Reserved */ 0,
369	/* 0x008 CAP_REG */ 0, 0,
370	/* 0x010 ECAP_REG */ 0, 0,
371	/* 0x018 GCMD_REG */ 0,
372	/* 0x01c GSTS_REG */ 0,
373	/* 0x020 RTADDR_REG */ 0, 0,
374	/* 0x028 CCMD_REG */ 0, 0,
375	/* 0x030 Reserved */ 0,
376	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
377	/* 0x038 FECTL_REG */ 0,
378	/* 0x03c FEDATA_REG */ 0,
379	/* 0x040 FEADDR_REG */ 0,
380	/* 0x044 FEUADDR_REG */ 0,
381	/* 0x048 Reserved */ 0, 0,
382	/* 0x050 Reserved */ 0, 0,
383	/* 0x058 AFLOG_REG */ 0, 0,
384	/* 0x060 Reserved */ 0,
385	/* 0x064 PMEN_REG */ 0,
386	/* 0x068 PLMBASE_REG */ 0,
387	/* 0x06c PLMLIMIT_REG */ 0,
388	/* 0x070 PHMBASE_REG */ 0, 0,
389	/* 0x078 PHMLIMIT_REG */ 0, 0,
390	/* 0x080 IQH_REG */ 0, 0,
391	/* 0x088 IQT_REG */ 0, 0,
392	/* 0x090 IQA_REG */ 0, 0,
393	/* 0x098 Reserved */ 0,
394	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
395	/* 0x0a0 IECTL_REG */ 0,
396	/* 0x0a4 IEDATA_REG */ 0,
397	/* 0x0a8 IEADDR_REG */ 0,
398	/* 0x0ac IEUADDR_REG */ 0,
399	/* 0x0b0 IQERCD_REG */ 0, 0,
400	/* 0x0b8 IRTA_REG */ 0, 0,
401	/* 0x0c0 PQH_REG */ 0, 0,
402	/* 0x0c8 PQT_REG */ 0, 0,
403	/* 0x0d0 PQA_REG */ 0, 0,
404	/* 0x0d8 Reserved */ 0,
405	/* 0x0dc PRS_REG */ 0,
406	/* 0x0e0 PECTL_REG */ 0,
407	/* 0x0e4 PEDATA_REG */ 0,
408	/* 0x0e8 PEADDR_REG */ 0,
409	/* 0x0ec PEUADDR_REG */ 0,
410	/* 0x0f0 Reserved */ 0, 0,
411	/* 0x0f8 Reserved */ 0, 0,
412	/* 0x100 MTRRCAP_REG */ 0, 0,
413	/* 0x108 MTRRDEF_REG */ 0, 0,
414	/* 0x110 Reserved */ 0, 0,
415	/* 0x118 Reserved */ 0, 0,
416	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
417	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
418	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
419	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
420	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
421	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
422	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
423	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
424	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
425	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
426	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
427	/* 0x178 Reserved */ 0, 0,
428	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
429	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
430	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
431	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
432	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
433	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
434	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
435	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
436	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
437	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
438	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
439	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
440	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
441	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
442	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
443	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
444	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
445	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
446	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
447	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
448	};
449	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
450
451	/**
452	* Read-write masks for DMAR registers (group 1).
453	*/
454	static uint32_t const g_au32RwMasks1[] =
455	{
456	/* Offset Register Low High */
457	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
458	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
459	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
460	/* 0xe18 VCMDRSVD_REG */ 0, 0,
461	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
462	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
463	/* 0xe30 Reserved */ 0, 0,
464	/* 0xe38 Reserved */ 0, 0,
465	/* 0xe40 Reserved */ 0, 0,
466	/* 0xe48 Reserved */ 0, 0,
467	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
468	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
469	/* 0xe60 Reserved */ 0, 0,
470	/* 0xe68 Reserved */ 0, 0,
471	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
472	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
473	};
474	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
475	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
476
477	/**
478	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
479	*/
480	static uint32_t const g_au32Rw1cMasks1[] =
481	{
482	/* Offset Register Low High */
483	/* 0xe00 VCCAP_REG */ 0, 0,
484	/* 0xe08 VCMD_EO_REG */ 0, 0,
485	/* 0xe10 VCMD_REG */ 0, 0,
486	/* 0xe18 VCMDRSVD_REG */ 0, 0,
487	/* 0xe20 VCRSP_REG */ 0, 0,
488	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
489	/* 0xe30 Reserved */ 0, 0,
490	/* 0xe38 Reserved */ 0, 0,
491	/* 0xe40 Reserved */ 0, 0,
492	/* 0xe48 Reserved */ 0, 0,
493	/* 0xe50 IVA_REG */ 0, 0,
494	/* 0xe58 IOTLB_REG */ 0, 0,
495	/* 0xe60 Reserved */ 0, 0,
496	/* 0xe68 Reserved */ 0, 0,
497	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
498	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
499	};
500	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
501
502	/** Array of RW masks for each register group. */
503	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
504
505	/** Array of RW1C masks for each register group. */
506	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
507
508	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
509	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
510
511
512	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
513	/**
514	* Gets the number of supported adjusted guest-address width (SAGAW) in bits given a
515	* CAP_REG.SAGAW value.
516	*
517	* @returns Number of SAGAW bits.
518	* @param uSagaw The CAP_REG.SAGAW value.
519	*/
520	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
521	{
522	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
523	return 30 + (uSagaw * 9);
524	return 0;
525	}
526
527
528	/**
529	* Gets the supported adjusted guest-address width (SAGAW) given the maximum guest
530	* address width (MGAW).
531	*
532	* @returns The CAP_REG.SAGAW value.
533	* @param uMgaw The CAP_REG.MGAW value.
534	*/
535	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
536	{
537	switch (uMgaw + 1)
538	{
539	case 39: return 1;
540	case 48: return 2;
541	case 57: return 3;
542	}
543	return 0;
544	}
545
546
547	/**
548	* Gets the index of the group the register belongs to given its MMIO offset.
549	*
550	* @returns The group index.
551	* @param offReg The MMIO offset of the register.
552	* @param cbReg The size of the access being made (for bounds checking on
553	* debug builds).
554	*/
555	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
556	{
557	uint16_t const offLast = offReg + cbReg - 1;
558	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
559	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
560	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
561	}
562
563
564	/**
565	* Gets the group the register belongs to given its MMIO offset.
566	*
567	* @returns Pointer to the first element of the register group.
568	* @param pThis The shared DMAR device state.
569	* @param offReg The MMIO offset of the register.
570	* @param cbReg The size of the access being made (for bounds checking on
571	* debug builds).
572	* @param pIdxGroup Where to store the index of the register group the register
573	* belongs to.
574	*/
575	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
576	{
577	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
578	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
579	return apbRegs[*pIdxGroup];
580	}
581
582
583	/**
584	* Const/read-only version of dmarRegGetGroup.
585	*
586	* @copydoc dmarRegGetGroup
587	*/
588	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
589	{
590	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
591	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
592	return apbRegs[*pIdxGroup];
593	}
594
595
596	/**
597	* Writes a 64-bit register with the exactly the supplied value.
598	*
599	* @param pThis The shared DMAR device state.
600	* @param offReg The MMIO offset of the register.
601	* @param uReg The 64-bit value to write.
602	*/
603	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
604	{
605	uint8_t idxGroup;
606	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
607	NOREF(idxGroup);
608	(uint64_t )(pabRegs + offReg) = uReg;
609	}
610
611
612	/**
613	* Writes a 32-bit register with the exactly the supplied value.
614	*
615	* @param pThis The shared DMAR device state.
616	* @param offReg The MMIO offset of the register.
617	* @param uReg The 32-bit value to write.
618	*/
619	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
620	{
621	uint8_t idxGroup;
622	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
623	NOREF(idxGroup);
624	(uint32_t )(pabRegs + offReg) = uReg;
625	}
626
627
628	/**
629	* Modifies a 32-bit register.
630	*
631	* @param pThis The shared DMAR device state.
632	* @param offReg The MMIO offset of the register.
633	* @param fAndMask The AND mask (applied first).
634	* @param fOrMask The OR mask.
635	*/
636	static void dmarRegChange32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
637	{
638	uint8_t idxGroup;
639	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
640	NOREF(idxGroup);
641	uint32_t uReg = (uint32_t )(pabRegs + offReg);
642	uReg = (uReg & fAndMask) \| fOrMask;
643	(uint32_t )(pabRegs + offReg) = uReg;
644	}
645
646
647	/**
648	* Modifies a 64-bit register.
649	*
650	* @param pThis The shared DMAR device state.
651	* @param offReg The MMIO offset of the register.
652	* @param fAndMask The AND mask (applied first).
653	* @param fOrMask The OR mask.
654	*/
655	static void dmarRegChange64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
656	{
657	uint8_t idxGroup;
658	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
659	NOREF(idxGroup);
660	uint64_t uReg = (uint64_t )(pabRegs + offReg);
661	uReg = (uReg & fAndMask) \| fOrMask;
662	(uint64_t )(pabRegs + offReg) = uReg;
663	}
664
665
666	/**
667	* Reads a 64-bit register with exactly the value it contains.
668	*
669	* @param pThis The shared DMAR device state.
670	* @param offReg The MMIO offset of the register.
671	* @param puReg Where to store the raw 64-bit register value.
672	* @param pfRwMask Where to store the RW mask corresponding to this register.
673	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
674	*/
675	static void dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
676	{
677	uint8_t idxGroup;
678	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
679	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
680	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
681	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
682	puReg = (uint64_t *)(pabRegs + offReg);
683	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
684	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
685	}
686
687
688	/**
689	* Reads a 32-bit register with exactly the value it contains.
690	*
691	* @param pThis The shared DMAR device state.
692	* @param offReg The MMIO offset of the register.
693	* @param puReg Where to store the raw 32-bit register value.
694	* @param pfRwMask Where to store the RW mask corresponding to this register.
695	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
696	*/
697	static void dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
698	{
699	uint8_t idxGroup;
700	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
701	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
702	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
703	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
704	puReg = (uint32_t *)(pabRegs + offReg);
705	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
706	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
707	}
708
709
710	/**
711	* Writes a 64-bit register as it would be when written by software.
712	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
713	*
714	* @returns The value that's actually written to the register.
715	* @param pThis The shared DMAR device state.
716	* @param offReg The MMIO offset of the register.
717	* @param uReg The 64-bit value to write.
718	*/
719	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
720	{
721	/* Read current value from the 64-bit register. */
722	uint64_t uCurReg;
723	uint64_t fRwMask;
724	uint64_t fRw1cMask;
725	dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
726
727	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
728	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
729	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
730	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
731
732	/* Write new value to the 64-bit register. */
733	dmarRegWriteRaw64(pThis, offReg, uNewReg);
734	return uNewReg;
735	}
736
737
738	/**
739	* Writes a 32-bit register as it would be when written by software.
740	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
741	*
742	* @returns The value that's actually written to the register.
743	* @param pThis The shared DMAR device state.
744	* @param offReg The MMIO offset of the register.
745	* @param uReg The 32-bit value to write.
746	*/
747	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
748	{
749	/* Read current value from the 32-bit register. */
750	uint32_t uCurReg;
751	uint32_t fRwMask;
752	uint32_t fRw1cMask;
753	dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
754
755	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
756	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
757	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
758	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
759
760	/* Write new value to the 32-bit register. */
761	dmarRegWriteRaw32(pThis, offReg, uNewReg);
762	return uNewReg;
763	}
764
765
766	/**
767	* Reads a 64-bit register as it would be when read by software.
768	*
769	* @returns The 64-bit register value.
770	* @param pThis The shared DMAR device state.
771	* @param offReg The MMIO offset of the register.
772	*/
773	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
774	{
775	uint64_t uCurReg;
776	uint64_t fRwMask;
777	uint64_t fRw1cMask;
778	dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
779	NOREF(fRwMask); NOREF(fRw1cMask);
780	return uCurReg;
781	}
782
783
784	/**
785	* Reads a 32-bit register as it would be when read by software.
786	*
787	* @returns The 32-bit register value.
788	* @param pThis The shared DMAR device state.
789	* @param offReg The MMIO offset of the register.
790	*/
791	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
792	{
793	uint32_t uCurReg;
794	uint32_t fRwMask;
795	uint32_t fRw1cMask;
796	dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
797	NOREF(fRwMask); NOREF(fRw1cMask);
798	return uCurReg;
799	}
800
801
802	/**
803	* Gets the table translation mode from the RTADDR_REG.
804	*
805	* @returns The table translation mode.
806	* @param pThis The shared DMAR device state.
807	*/
808	static uint8_t dmarRtAddrRegGetTtm(PCDMAR pThis)
809	{
810	uint64_t const uRtAddrReg = dmarRegRead64(pThis, VTD_MMIO_OFF_RTADDR_REG);
811	return RT_BF_GET(uRtAddrReg, VTD_BF_RTADDR_REG_TTM);
812	}
813
814
815	/**
816	* Raises an IQE (invalidation queue error) fault.
817	*
818	* @param pDevIns The IOMMU device instance.
819	* @param pThis The shared DMAR device state.
820	* @param enmIqei The IQE information.
821	* @param enmDiag The diagnostic reason.
822	*/
823	static void dmarFaultRaiseIqe(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IQERCD_IQEI_T enmIqei)
824	{
825	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
826	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
827	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
828
829	/* Set the error bit. */
830	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
831	dmarRegChange32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
832
833	/* Set the error information. */
834	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
835	dmarRegChange64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
836
837	/* Update diagnostic reason. */
838	pThis->enmDiag = enmDiag;
839
840	/** @todo Raise interrupt based on FECTL_REG. */
841	}
842
843
844	/**
845	* Handles writes to CCMD_REG.
846	*
847	* @returns Strict VBox status code.
848	* @param pDevIns The IOMMU device instance.
849	* @param off The MMIO register offset.
850	* @param cb The size of the MMIO access (in bytes).
851	* @param uCcmdReg The value written to CCMD_REG.
852	*/
853	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t off, uint8_t cb, uint64_t uCcmdReg)
854	{
855	/* We only care about responding to high 32-bits writes, low 32-bits are data. */
856	if (off + cb > VTD_MMIO_OFF_CCMD_REG + 4)
857	{
858	/* Check if we need to invalidate the context-context. */
859	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
860	if (fIcc)
861	{
862	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
863	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
864	if (uMajorVersion < 6)
865	{
866	/** @todo Verify queued-invalidation is not enabled.
867	* See Intel spec. 6.5.1 "Register-based Invalidation Interface" */
868
869	/* Verify table translation mode is legacy. */
870	uint8_t const fTtm = dmarRtAddrRegGetTtm(pThis);
871	if (fTtm == VTD_TTM_LEGACY_MODE)
872	{
873	/** @todo Invalidate. */
874	return VINF_SUCCESS;
875	}
876	}
877
878	/** @todo Raise error. */
879	}
880	}
881	return VINF_SUCCESS;
882	}
883
884
885	/**
886	* Handles writes to IQT_REG.
887	*
888	* @returns Strict VBox status code.
889	* @param pDevIns The IOMMU device instance.
890	* @param off The MMIO register offset.
891	* @param uIqtReg The value written to IQT_REG.
892	*/
893	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t off, uint64_t uIqtReg)
894	{
895	/* We only care about the low 32-bits, high 32-bits are reserved. */
896	if (off == VTD_MMIO_OFF_IQT_REG)
897	{
898	/* Verify if the queue tail offset is aligned according to the descriptor width in IQA_REG. */
899	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
900	uint16_t const offQueueTail = VTD_IQT_REG_GET_QT(uIqtReg);
901	uint64_t const uIqaReg = dmarRegRead64(pThis, VTD_MMIO_OFF_IQA_REG);
902	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
903	if ( fDw != VTD_IQA_REG_DW_256_BIT
904	\|\| !(offQueueTail & 0x1f))
905	{
906	/** @todo Figure out what to do here, like waking up worker thread or
907	* something. */
908	}
909	else
910	dmarFaultRaiseIqe(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, kQueueTailNotAligned);
911	}
912	return VINF_SUCCESS;
913	}
914
915
916	/**
917	* Memory access bulk (one or more 4K pages) request from a device.
918	*
919	* @returns VBox status code.
920	* @param pDevIns The IOMMU device instance.
921	* @param idDevice The device ID (bus, device, function).
922	* @param cIovas The number of addresses being accessed.
923	* @param pauIovas The I/O virtual addresses for each page being accessed.
924	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
925	* @param paGCPhysSpa Where to store the translated physical addresses.
926	*
927	* @thread Any.
928	*/
929	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
930	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
931	{
932	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
933	return VERR_NOT_IMPLEMENTED;
934	}
935
936
937	/**
938	* Memory access transaction from a device.
939	*
940	* @returns VBox status code.
941	* @param pDevIns The IOMMU device instance.
942	* @param idDevice The device ID (bus, device, function).
943	* @param uIova The I/O virtual address being accessed.
944	* @param cbIova The size of the access.
945	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
946	* @param pGCPhysSpa Where to store the translated system physical address.
947	* @param pcbContiguous Where to store the number of contiguous bytes translated
948	* and permission-checked.
949	*
950	* @thread Any.
951	*/
952	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
953	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
954	{
955	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
956	return VERR_NOT_IMPLEMENTED;
957	}
958
959
960	/**
961	* Interrupt remap request from a device.
962	*
963	* @returns VBox status code.
964	* @param pDevIns The IOMMU device instance.
965	* @param idDevice The device ID (bus, device, function).
966	* @param pMsiIn The source MSI.
967	* @param pMsiOut Where to store the remapped MSI.
968	*/
969	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
970	{
971	RT_NOREF3(idDevice, pMsiIn, pMsiOut);
972	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
973	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap)); NOREF(pThis);
974
975	return VERR_NOT_IMPLEMENTED;
976	}
977
978
979	/**
980	* @callback_method_impl{FNIOMMMIONEWWRITE}
981	*/
982	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
983	{
984	RT_NOREF1(pvUser);
985	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
986
987	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
988	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
989
990	uint16_t const offReg = off;
991	uint16_t const offLast = offReg + cb - 1;
992	if (DMAR_IS_MMIO_OFF_VALID(offLast))
993	{
994	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv)
995	: dmarRegWrite32(pThis, offReg, (uint32_t )pv);
996	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
997	switch (off)
998	{
999	case VTD_MMIO_OFF_IQT_REG:
1000	case VTD_MMIO_OFF_IQT_REG + 4:
1001	{
1002	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
1003	break;
1004	}
1005
1006	case VTD_MMIO_OFF_CCMD_REG:
1007	case VTD_MMIO_OFF_CCMD_REG + 4:
1008	{
1009	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
1010	break;
1011	}
1012	}
1013
1014	LogFlowFunc(("offReg=%#x rc=%Rrc\n", offReg, VBOXSTRICTRC_VAL(rcStrict)));
1015	return rcStrict;
1016	}
1017
1018	return VINF_IOM_MMIO_UNUSED_FF;
1019	}
1020
1021
1022	/**
1023	* @callback_method_impl{FNIOMMMIONEWREAD}
1024	*/
1025	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1026	{
1027	RT_NOREF1(pvUser);
1028	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1029
1030	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1031	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1032
1033	uint16_t const offReg = off;
1034	uint16_t const offLast = offReg + cb - 1;
1035	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1036	{
1037	if (cb == 8)
1038	{
1039	(uint64_t )pv = dmarRegRead64(pThis, offReg);
1040	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
1041	}
1042	else
1043	{
1044	(uint32_t )pv = dmarRegRead32(pThis, offReg);
1045	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
1046	}
1047
1048	return VINF_SUCCESS;
1049	}
1050
1051	return VINF_IOM_MMIO_UNUSED_FF;
1052	}
1053
1054
1055	#ifdef IN_RING3
1056	/**
1057	* @callback_method_impl{FNDBGFHANDLERDEV}
1058	*/
1059	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1060	{
1061	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1062	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1063	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1064
1065	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
1066
1067	DMARDIAG const enmDiag = pThis->enmDiag;
1068	const char *pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
1069
1070	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
1071	pHlp->pfnPrintf(pHlp, " Diag = %u (%s)\n", enmDiag, pszDiag);
1072	pHlp->pfnPrintf(pHlp, "\n");
1073	}
1074
1075
1076	/**
1077	* Initializes all registers in the DMAR unit.
1078	*
1079	* @param pDevIns The IOMMU device instance.
1080	*/
1081	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
1082	{
1083	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1084	RT_ZERO(pThis->abRegs0);
1085	RT_ZERO(pThis->abRegs1);
1086
1087	/*
1088	* Initialize registers not mutable by software prior to initializing other registers.
1089	*/
1090	/* VER_REG */
1091	{
1092	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
1093	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
1094	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
1095	}
1096
1097	uint8_t const fFlts = 1; /* First-Level translation support. */
1098	uint8_t const fSlts = 1; /* Second-Level translation support. */
1099	uint8_t const fPt = 1; /* Pass-Through support. */
1100	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
1101	uint8_t const fNest = 0; /* Nested translation support. */
1102
1103	/* CAP_REG */
1104	{
1105	uint8_t cGstPhysAddrBits;
1106	uint8_t cGstLinearAddrBits;
1107	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
1108
1109	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
1110	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
1111	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
1112	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
1113	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
1114	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
1115	uint8_t const fMamv = (fSl2gp ? /* Maximum address mask value (for second-level invalidations). */
1116	X86_PAGE_1G_SHIFT : X86_PAGE_2M_SHIFT) - X86_PAGE_4K_SHIFT;
1117	uint8_t const fNd = 2; /* Number of domains (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
1118	7=Reserved). */
1119	uint8_t const fPsi = 1; /* Page selective invalidation. */
1120	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
1121	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
1122	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
1123
1124	pThis->fCap = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
1125	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
1126	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
1127	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
1128	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
1129	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
1130	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
1131	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
1132	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
1133	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
1134	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
1135	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
1136	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
1137	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
1138	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
1139	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
1140	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
1141	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
1142	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
1143	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, 0) /* Whether we invalidate interrupt cache on SIRTP flow. */
1144	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, 0); /* Whether we invalidate translation cache on SRTP flow. */
1145	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCap);
1146	}
1147
1148	/* ECAP_REG */
1149	{
1150	uint8_t const fQi = 1; /* Queued invalidations. */
1151	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
1152	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
1153	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
1154	uint8_t const fSrs = 1; /* Supervisor request support. */
1155	uint8_t const fEim = 1; /* Extended interrupt mode.*/
1156	uint8_t const fAdms = 1; /* Abort DMA mode support. */
1157
1158	pThis->fExtCap = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
1159	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, 1)
1160	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
1161	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
1162	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
1163	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
1164	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
1165	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
1166	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
1167	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
1168	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
1169	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
1170	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
1171	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
1172	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
1173	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
1174	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
1175	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
1176	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
1177	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
1178	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
1179	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
1180	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
1181	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
1182	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
1183	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
1184	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
1185	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
1186	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
1187	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCap);
1188	}
1189
1190	/*
1191	* Initialize registers mutable by software.
1192	*/
1193	/* FECTL_REG */
1194	{
1195	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
1196	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
1197	}
1198
1199	/* ICETL_REG */
1200	{
1201	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
1202	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
1203	}
1204
1205	#ifdef VBOX_STRICT
1206	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
1207	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
1208	#endif
1209	}
1210
1211
1212	/**
1213	* @interface_method_impl{PDMDEVREG,pfnReset}
1214	*/
1215	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
1216	{
1217	RT_NOREF1(pDevIns);
1218	LogFlowFunc(("\n"));
1219
1220	dmarR3RegsInit(pDevIns);
1221	}
1222
1223
1224	/**
1225	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1226	*/
1227	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
1228	{
1229	RT_NOREF(pDevIns);
1230	LogFlowFunc(("\n"));
1231	return VINF_SUCCESS;
1232	}
1233
1234
1235	/**
1236	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1237	*/
1238	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1239	{
1240	RT_NOREF(pCfg);
1241
1242	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1243	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
1244	pThisR3->pDevInsR3 = pDevIns;
1245
1246	LogFlowFunc(("iInstance=%d\n", iInstance));
1247	NOREF(iInstance);
1248
1249	/*
1250	* Register the IOMMU with PDM.
1251	*/
1252	PDMIOMMUREGR3 IommuReg;
1253	RT_ZERO(IommuReg);
1254	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
1255	IommuReg.pfnMemAccess = iommuIntelMemAccess;
1256	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
1257	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
1258	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
1259	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
1260	if (RT_FAILURE(rc))
1261	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
1262	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
1263	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1264	N_("IOMMU helper version mismatch; got %#x expected %#x"),
1265	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
1266	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
1267	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1268	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
1269	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
1270	/*
1271	* Use PDM's critical section (via helpers) for the IOMMU device.
1272	*/
1273	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1274	AssertRCReturn(rc, rc);
1275
1276	/*
1277	* Initialize PCI configuration registers.
1278	*/
1279	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1280	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1281
1282	/* Header. */
1283	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
1284	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
1285	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
1286	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
1287	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
1288	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
1289	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
1290	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
1291
1292	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
1293	PDMPciDevSetStatus(pPciDev, 0);
1294	PDMPciDevSetCapabilityList(pPciDev, 0);
1295
1296	/** @todo VTBAR at 0x180? */
1297
1298	/*
1299	* Register the PCI function with PDM.
1300	*/
1301	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
1302	AssertLogRelRCReturn(rc, rc);
1303
1304	/** @todo Register MSI but what's the MSI capability offset? */
1305	#if 0
1306	/*
1307	* Register MSI support for the PCI device.
1308	* This must be done -after- registering it as a PCI device!
1309	*/
1310	#endif
1311
1312	/*
1313	* Register MMIO region.
1314	*/
1315	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
1316	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
1317	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
1318	"Intel-IOMMU", &pThis->hMmio);
1319	AssertRCReturn(rc, rc);
1320
1321	/*
1322	* Register debugger info items.
1323	*/
1324	PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
1325
1326	#ifdef VBOX_WITH_STATISTICS
1327	/*
1328	* Statistics.
1329	*/
1330	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
1331	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
1332
1333	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
1334	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
1335
1336	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
1337	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
1338
1339	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
1340	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
1341
1342	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
1343	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
1344
1345	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
1346	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
1347
1348	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
1349	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
1350	#endif
1351
1352	/*
1353	* Initialize registers.
1354	*/
1355	dmarR3RegsInit(pDevIns);
1356
1357	/*
1358	* Log some of the features exposed to software.
1359	*/
1360	uint32_t const uVerReg = pThis->uVerReg;
1361	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_MGAW) + 1;
1362	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_SAGAW));
1363	uint16_t const offFrcd = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_FRO);
1364	uint16_t const offIva = RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_IRO);
1365	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n", DMAR_LOG_PFX,
1366	RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
1367	pThis->fCap, pThis->fExtCap, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
1368	return VINF_SUCCESS;
1369	}
1370
1371	#else
1372
1373	/**
1374	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1375	*/
1376	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
1377	{
1378	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1379	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1380	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
1381	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
1382
1383	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
1384	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1385	AssertRCReturn(rc, rc);
1386
1387	/* Set up the MMIO RZ handlers. */
1388	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
1389	AssertRCReturn(rc, rc);
1390
1391	/* Set up the IOMMU RZ callbacks. */
1392	PDMIOMMUREGCC IommuReg;
1393	RT_ZERO(IommuReg);
1394	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
1395	IommuReg.idxIommu = pThis->idxIommu;
1396	IommuReg.pfnMemAccess = iommuIntelMemAccess;
1397	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
1398	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
1399	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
1400
1401	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
1402	AssertRCReturn(rc, rc);
1403	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
1404	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
1405	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
1406	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
1407	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
1408	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
1409	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
1410
1411	return VINF_SUCCESS;
1412	}
1413
1414	#endif
1415
1416
1417	/**
1418	* The device registration structure.
1419	*/
1420	PDMDEVREG const g_DeviceIommuIntel =
1421	{
1422	/* .u32Version = */ PDM_DEVREG_VERSION,
1423	/* .uReserved0 = */ 0,
1424	/* .szName = */ "iommu-intel",
1425	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1426	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
1427	/* .cMaxInstances = */ 1,
1428	/* .uSharedVersion = */ 42,
1429	/* .cbInstanceShared = */ sizeof(DMAR),
1430	/* .cbInstanceCC = */ sizeof(DMARCC),
1431	/* .cbInstanceRC = */ sizeof(DMARRC),
1432	/* .cMaxPciDevices = */ 1,
1433	/* .cMaxMsixVectors = */ 0,
1434	/* .pszDescription = */ "IOMMU (Intel)",
1435	#if defined(IN_RING3)
1436	/* .pszRCMod = */ "VBoxDDRC.rc",
1437	/* .pszR0Mod = */ "VBoxDDR0.r0",
1438	/* .pfnConstruct = */ iommuIntelR3Construct,
1439	/* .pfnDestruct = */ iommuIntelR3Destruct,
1440	/* .pfnRelocate = */ NULL,
1441	/* .pfnMemSetup = */ NULL,
1442	/* .pfnPowerOn = */ NULL,
1443	/* .pfnReset = */ iommuIntelR3Reset,
1444	/* .pfnSuspend = */ NULL,
1445	/* .pfnResume = */ NULL,
1446	/* .pfnAttach = */ NULL,
1447	/* .pfnDetach = */ NULL,
1448	/* .pfnQueryInterface = */ NULL,
1449	/* .pfnInitComplete = */ NULL,
1450	/* .pfnPowerOff = */ NULL,
1451	/* .pfnSoftReset = */ NULL,
1452	/* .pfnReserved0 = */ NULL,
1453	/* .pfnReserved1 = */ NULL,
1454	/* .pfnReserved2 = */ NULL,
1455	/* .pfnReserved3 = */ NULL,
1456	/* .pfnReserved4 = */ NULL,
1457	/* .pfnReserved5 = */ NULL,
1458	/* .pfnReserved6 = */ NULL,
1459	/* .pfnReserved7 = */ NULL,
1460	#elif defined(IN_RING0)
1461	/* .pfnEarlyConstruct = */ NULL,
1462	/* .pfnConstruct = */ iommuIntelRZConstruct,
1463	/* .pfnDestruct = */ NULL,
1464	/* .pfnFinalDestruct = */ NULL,
1465	/* .pfnRequest = */ NULL,
1466	/* .pfnReserved0 = */ NULL,
1467	/* .pfnReserved1 = */ NULL,
1468	/* .pfnReserved2 = */ NULL,
1469	/* .pfnReserved3 = */ NULL,
1470	/* .pfnReserved4 = */ NULL,
1471	/* .pfnReserved5 = */ NULL,
1472	/* .pfnReserved6 = */ NULL,
1473	/* .pfnReserved7 = */ NULL,
1474	#elif defined(IN_RC)
1475	/* .pfnConstruct = */ iommuIntelRZConstruct,
1476	/* .pfnReserved0 = */ NULL,
1477	/* .pfnReserved1 = */ NULL,
1478	/* .pfnReserved2 = */ NULL,
1479	/* .pfnReserved3 = */ NULL,
1480	/* .pfnReserved4 = */ NULL,
1481	/* .pfnReserved5 = */ NULL,
1482	/* .pfnReserved6 = */ NULL,
1483	/* .pfnReserved7 = */ NULL,
1484	#else
1485	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1486	#endif
1487	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1488	};
1489
1490	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1491

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88588

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