DevIommuIntel.cpp@ 88675

Last change on this file since 88675 was 88669, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 WIP.
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1	/* $Id: DevIommuIntel.cpp 88669 2021-04-23 07:14:48Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/string.h>
27
28
29	/*********************************************************************************************************************************
30	* Defined Constants And Macros *
31	*********************************************************************************************************************************/
32	/** Gets the low uint32_t of a uint64_t or something equivalent.
33	*
34	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
35	* used as it asserts for correctness when compiling on certain compilers). */
36	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
37
38	/** Gets the high uint32_t of a uint64_t or something equivalent.
39	*
40	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
41	* used as it asserts for correctness when compiling on certain compilers). */
42	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
43
44	/** Asserts MMIO access' offset and size are valid or returns appropriate error
45	* code suitable for returning from MMIO access handlers. */
46	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
47	do { \
48	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
49	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
50	} while (0)
51
52	/** Checks whether the MMIO offset is valid. */
53	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
54	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
55
56	/** Acquires the DMAR lock but returns with the given error code on failure. */
57	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
58	do { \
59	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
60	{ /* likely */ } \
61	else \
62	return (a_rcBusy); \
63	} while (0)
64
65	/** Acquires the DMAR lock and is not expected to fail. */
66	#define DMAR_LOCK(a_pDevIns, a_pThisCC) \
67	do { \
68	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED); \
69	Assert(rcLock == VINF_SUCCESS); \
70	} while (0)
71
72	/** Release the DMAR lock. */
73	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
74
75	/** Asserts that the calling thread owns the DMAR lock. */
76	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
77	do { \
78	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
79	RT_NOREF1(a_pThisCC); \
80	} while (0)
81
82	/** The number of fault recording registers our implementation supports.
83	* Normal guest operation shouldn't trigger faults anyway, so we only support the
84	* minimum number of registers (which is 1).
85	*
86	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
87	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
88
89	/** Offset of first register in group 0. */
90	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
91	/** Offset of last register in group 0 (inclusive). */
92	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
93	/** Last valid offset in group 0 (exclusive). */
94	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
95	/** Size of the group 0 (in bytes). */
96	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
97	/*< Implementation-specific MMIO offset of IVA_REG. /
98	#define DMAR_MMIO_OFF_IVA_REG 0xe50
99	/*< Implementation-specific MMIO offset of IOTLB_REG. /
100	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
101	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
102	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
103	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
104	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
105	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
106
107	/** Offset of first register in group 1. */
108	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
109	/** Offset of last register in group 1 (inclusive). */
110	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
111	/** Last valid offset in group 1 (exclusive). */
112	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
113	/** Size of the group 1 (in bytes). */
114	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
115
116	/** DMAR implementation's major version number (exposed to software).
117	* We report 6 as the major version since we support queued-invalidations as
118	* software may make assumptions based on that.
119	*
120	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
121	#define DMAR_VER_MAJOR 6
122	/** DMAR implementation's minor version number (exposed to software). */
123	#define DMAR_VER_MINOR 0
124
125	/** Release log prefix string. */
126	#define DMAR_LOG_PFX "Intel-IOMMU"
127	/** The current saved state version. */
128	#define DMAR_SAVED_STATE_VERSION 1
129
130
131	/*********************************************************************************************************************************
132	* Structures and Typedefs *
133	*********************************************************************************************************************************/
134	/**
135	* DMAR error diagnostics.
136	*
137	* @note Members of this enum are used as array indices, so no gaps in enum
138	* values are not allowed. Update g_apszDmarDiagDesc when you modify
139	* fields in this enum.
140	*/
141	typedef enum
142	{
143	kDmarDiag_None = 0,
144	kDmarDiag_IqtReg_Qt_NotAligned,
145	kDmarDiag_IqaReg_Dw_Invalid,
146	/* Last member for determining array index limit. */
147	kDmarDiag_End
148	} DMARDIAG;
149	AssertCompileSize(DMARDIAG, 4);
150
151	/** DMAR diagnostic enum description expansion. */
152	#define DMARDIAG_DESC(a_Def, a_Desc) #a_Def " - " #a_Desc
153
154	/** DMAR diagnostics description. */
155	static const char *const g_apszDmarDiagDesc[] =
156	{
157	DMARDIAG_DESC(kNone , "None" ),
158	DMARDIAG_DESC(kDmarDiag_IqtReg_Qt_NotAligned, "IqtReg_Qt_NotAligned"),
159	DMARDIAG_DESC(kDmarDiag_IqaReg_Dw_Invalid , "IqaReg_Dw_Invalid" )
160	/* kDmarDiag_End */
161	};
162	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
163	#undef DMARDIAG_DESC
164
165	/**
166	* The shared DMAR device state.
167	*/
168	typedef struct DMAR
169	{
170	/** IOMMU device index. */
171	uint32_t idxIommu;
172	/** DMAR magic. */
173	uint32_t u32Magic;
174
175	/** The MMIO handle. */
176	IOMMMIOHANDLE hMmio;
177	/** The event semaphore the invalidation-queue thread waits on. */
178	SUPSEMEVENT hEvtInvQueue;
179	/** Whether the invalidation-queue thread has been signaled. */
180	bool volatile fInvQueueThreadSignaled;
181	/** Padding. */
182	bool afPadding0[3];
183	/** Error diagnostic. */
184	DMARDIAG enmDiag;
185
186	/** Registers (group 0). */
187	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
188	/** Registers (group 1). */
189	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
190
191	/** @name Register copies for a tiny bit faster and more convenient access.
192	* @{ */
193	/** Copy of VER_REG. */
194	uint8_t uVerReg;
195	/** Alignment. */
196	uint8_t abPadding[7];
197	/** Copy of CAP_REG. */
198	uint64_t fCap;
199	/** Copy of ECAP_REG. */
200	uint64_t fExtCap;
201	/** @} */
202
203	#ifdef VBOX_WITH_STATISTICS
204	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
205	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
206	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
207	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
208
209	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
210	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
211
212	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
213	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
214	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
215	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
216
217	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
218	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
219	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
220	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
221	#endif
222	} DMAR;
223	/** Pointer to the DMAR device state. */
224	typedef DMAR *PDMAR;
225	/** Pointer to the const DMAR device state. */
226	typedef DMAR const *PCDMAR;
227	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
228	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
229
230	/**
231	* The ring-3 DMAR device state.
232	*/
233	typedef struct DMARR3
234	{
235	/** Device instance. */
236	PPDMDEVINSR3 pDevInsR3;
237	/** The IOMMU helper. */
238	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
239	/** The invalidation-queue thread. */
240	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
241	} DMARR3;
242	/** Pointer to the ring-3 DMAR device state. */
243	typedef DMARR3 *PDMARR3;
244	/** Pointer to the const ring-3 DMAR device state. */
245	typedef DMARR3 const *PCDMARR3;
246
247	/**
248	* The ring-0 DMAR device state.
249	*/
250	typedef struct DMARR0
251	{
252	/** Device instance. */
253	PPDMDEVINSR0 pDevInsR0;
254	/** The IOMMU helper. */
255	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
256	} DMARR0;
257	/** Pointer to the ring-0 IOMMU device state. */
258	typedef DMARR0 *PDMARR0;
259	/** Pointer to the const ring-0 IOMMU device state. */
260	typedef DMARR0 const *PCDMARR0;
261
262	/**
263	* The raw-mode DMAR device state.
264	*/
265	typedef struct DMARRC
266	{
267	/** Device instance. */
268	PPDMDEVINSRC pDevInsRC;
269	/** The IOMMU helper. */
270	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
271	} DMARRC;
272	/** Pointer to the raw-mode DMAR device state. */
273	typedef DMARRC *PDMARRC;
274	/** Pointer to the const raw-mode DMAR device state. */
275	typedef DMARRC const *PCIDMARRC;
276
277	/** The DMAR device state for the current context. */
278	typedef CTX_SUFF(DMAR) DMARCC;
279	/** Pointer to the DMAR device state for the current context. */
280	typedef CTX_SUFF(PDMAR) PDMARCC;
281	/** Pointer to the const DMAR device state for the current context. */
282	typedef CTX_SUFF(PDMAR) const PCDMARCC;
283
284
285	/*********************************************************************************************************************************
286	* Global Variables *
287	*********************************************************************************************************************************/
288	/**
289	* Read-write masks for DMAR registers (group 0).
290	*/
291	static uint32_t const g_au32RwMasks0[] =
292	{
293	/* Offset Register Low High */
294	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
295	/* 0x004 Reserved */ 0,
296	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
297	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
298	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
299	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
300	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
301	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
302	/* 0x030 Reserved */ 0,
303	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
304	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
305	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
306	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
307	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
308	/* 0x048 Reserved */ 0, 0,
309	/* 0x050 Reserved */ 0, 0,
310	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
311	/* 0x060 Reserved */ 0,
312	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
313	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
314	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
315	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
316	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
317	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
318	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
319	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
320	/* 0x098 Reserved */ 0,
321	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
322	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
323	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
324	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
325	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
326	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
327	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
328	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
329	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
330	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
331	/* 0x0d8 Reserved */ 0,
332	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
333	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
334	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
335	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
336	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
337	/* 0x0f0 Reserved */ 0, 0,
338	/* 0x0f8 Reserved */ 0, 0,
339	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
340	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
341	/* 0x110 Reserved */ 0, 0,
342	/* 0x118 Reserved */ 0, 0,
343	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
344	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
345	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
346	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
347	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
348	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
349	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
350	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
351	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
352	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
353	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
354	/* 0x178 Reserved */ 0, 0,
355	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
356	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
357	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
358	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
359	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
360	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
361	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
362	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
363	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
364	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
365	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
366	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
367	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
368	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
369	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
370	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
371	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
372	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
373	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
374	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
375	};
376	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
377
378	/**
379	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
380	*/
381	static uint32_t const g_au32Rw1cMasks0[] =
382	{
383	/* Offset Register Low High */
384	/* 0x000 VER_REG */ 0,
385	/* 0x004 Reserved */ 0,
386	/* 0x008 CAP_REG */ 0, 0,
387	/* 0x010 ECAP_REG */ 0, 0,
388	/* 0x018 GCMD_REG */ 0,
389	/* 0x01c GSTS_REG */ 0,
390	/* 0x020 RTADDR_REG */ 0, 0,
391	/* 0x028 CCMD_REG */ 0, 0,
392	/* 0x030 Reserved */ 0,
393	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
394	/* 0x038 FECTL_REG */ 0,
395	/* 0x03c FEDATA_REG */ 0,
396	/* 0x040 FEADDR_REG */ 0,
397	/* 0x044 FEUADDR_REG */ 0,
398	/* 0x048 Reserved */ 0, 0,
399	/* 0x050 Reserved */ 0, 0,
400	/* 0x058 AFLOG_REG */ 0, 0,
401	/* 0x060 Reserved */ 0,
402	/* 0x064 PMEN_REG */ 0,
403	/* 0x068 PLMBASE_REG */ 0,
404	/* 0x06c PLMLIMIT_REG */ 0,
405	/* 0x070 PHMBASE_REG */ 0, 0,
406	/* 0x078 PHMLIMIT_REG */ 0, 0,
407	/* 0x080 IQH_REG */ 0, 0,
408	/* 0x088 IQT_REG */ 0, 0,
409	/* 0x090 IQA_REG */ 0, 0,
410	/* 0x098 Reserved */ 0,
411	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
412	/* 0x0a0 IECTL_REG */ 0,
413	/* 0x0a4 IEDATA_REG */ 0,
414	/* 0x0a8 IEADDR_REG */ 0,
415	/* 0x0ac IEUADDR_REG */ 0,
416	/* 0x0b0 IQERCD_REG */ 0, 0,
417	/* 0x0b8 IRTA_REG */ 0, 0,
418	/* 0x0c0 PQH_REG */ 0, 0,
419	/* 0x0c8 PQT_REG */ 0, 0,
420	/* 0x0d0 PQA_REG */ 0, 0,
421	/* 0x0d8 Reserved */ 0,
422	/* 0x0dc PRS_REG */ 0,
423	/* 0x0e0 PECTL_REG */ 0,
424	/* 0x0e4 PEDATA_REG */ 0,
425	/* 0x0e8 PEADDR_REG */ 0,
426	/* 0x0ec PEUADDR_REG */ 0,
427	/* 0x0f0 Reserved */ 0, 0,
428	/* 0x0f8 Reserved */ 0, 0,
429	/* 0x100 MTRRCAP_REG */ 0, 0,
430	/* 0x108 MTRRDEF_REG */ 0, 0,
431	/* 0x110 Reserved */ 0, 0,
432	/* 0x118 Reserved */ 0, 0,
433	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
434	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
435	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
436	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
437	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
438	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
439	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
440	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
441	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
442	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
443	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
444	/* 0x178 Reserved */ 0, 0,
445	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
446	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
447	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
448	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
449	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
450	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
451	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
452	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
453	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
454	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
455	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
456	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
457	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
458	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
459	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
460	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
461	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
462	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
463	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
464	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
465	};
466	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
467
468	/**
469	* Read-write masks for DMAR registers (group 1).
470	*/
471	static uint32_t const g_au32RwMasks1[] =
472	{
473	/* Offset Register Low High */
474	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
475	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
476	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
477	/* 0xe18 VCMDRSVD_REG */ 0, 0,
478	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
479	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
480	/* 0xe30 Reserved */ 0, 0,
481	/* 0xe38 Reserved */ 0, 0,
482	/* 0xe40 Reserved */ 0, 0,
483	/* 0xe48 Reserved */ 0, 0,
484	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
485	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
486	/* 0xe60 Reserved */ 0, 0,
487	/* 0xe68 Reserved */ 0, 0,
488	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
489	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
490	};
491	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
492	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
493
494	/**
495	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
496	*/
497	static uint32_t const g_au32Rw1cMasks1[] =
498	{
499	/* Offset Register Low High */
500	/* 0xe00 VCCAP_REG */ 0, 0,
501	/* 0xe08 VCMD_EO_REG */ 0, 0,
502	/* 0xe10 VCMD_REG */ 0, 0,
503	/* 0xe18 VCMDRSVD_REG */ 0, 0,
504	/* 0xe20 VCRSP_REG */ 0, 0,
505	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
506	/* 0xe30 Reserved */ 0, 0,
507	/* 0xe38 Reserved */ 0, 0,
508	/* 0xe40 Reserved */ 0, 0,
509	/* 0xe48 Reserved */ 0, 0,
510	/* 0xe50 IVA_REG */ 0, 0,
511	/* 0xe58 IOTLB_REG */ 0, 0,
512	/* 0xe60 Reserved */ 0, 0,
513	/* 0xe68 Reserved */ 0, 0,
514	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
515	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
516	};
517	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
518
519	/** Array of RW masks for each register group. */
520	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
521
522	/** Array of RW1C masks for each register group. */
523	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
524
525	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
526	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
527
528
529	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
530	/** @todo Add IOMMU struct size/alignment verification, see
531	* Devices/testcase/Makefile.kmk and
532	* Devices/testcase/tstDeviceStructSize[RC].cpp */
533
534	/**
535	* Gets the number of supported adjusted guest-address width (SAGAW) in bits given a
536	* CAP_REG.SAGAW value.
537	*
538	* @returns Number of SAGAW bits.
539	* @param uSagaw The CAP_REG.SAGAW value.
540	*/
541	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
542	{
543	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
544	return 30 + (uSagaw * 9);
545	return 0;
546	}
547
548
549	/**
550	* Gets the supported adjusted guest-address width (SAGAW) given the maximum guest
551	* address width (MGAW).
552	*
553	* @returns The CAP_REG.SAGAW value.
554	* @param uMgaw The CAP_REG.MGAW value.
555	*/
556	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
557	{
558	switch (uMgaw + 1)
559	{
560	case 39: return 1;
561	case 48: return 2;
562	case 57: return 3;
563	}
564	return 0;
565	}
566
567
568	/**
569	* Gets the index of the group the register belongs to given its MMIO offset.
570	*
571	* @returns The group index.
572	* @param offReg The MMIO offset of the register.
573	* @param cbReg The size of the access being made (for bounds checking on
574	* debug builds).
575	*/
576	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
577	{
578	uint16_t const offLast = offReg + cbReg - 1;
579	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
580	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
581	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
582	}
583
584
585	/**
586	* Gets the group the register belongs to given its MMIO offset.
587	*
588	* @returns Pointer to the first element of the register group.
589	* @param pThis The shared DMAR device state.
590	* @param offReg The MMIO offset of the register.
591	* @param cbReg The size of the access being made (for bounds checking on
592	* debug builds).
593	* @param pIdxGroup Where to store the index of the register group the register
594	* belongs to.
595	*/
596	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
597	{
598	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
599	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
600	return apbRegs[*pIdxGroup];
601	}
602
603
604	/**
605	* Const/read-only version of dmarRegGetGroup.
606	*
607	* @copydoc dmarRegGetGroup
608	*/
609	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
610	{
611	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
612	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
613	return apbRegs[*pIdxGroup];
614	}
615
616
617	/**
618	* Writes a 32-bit register with the exactly the supplied value.
619	*
620	* @param pThis The shared DMAR device state.
621	* @param offReg The MMIO offset of the register.
622	* @param uReg The 32-bit value to write.
623	*/
624	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
625	{
626	uint8_t idxGroup;
627	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
628	NOREF(idxGroup);
629	(uint32_t )(pabRegs + offReg) = uReg;
630	}
631
632
633	/**
634	* Writes a 64-bit register with the exactly the supplied value.
635	*
636	* @param pThis The shared DMAR device state.
637	* @param offReg The MMIO offset of the register.
638	* @param uReg The 64-bit value to write.
639	*/
640	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
641	{
642	uint8_t idxGroup;
643	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
644	NOREF(idxGroup);
645	(uint64_t )(pabRegs + offReg) = uReg;
646	}
647
648
649	/**
650	* Reads a 32-bit register with exactly the value it contains.
651	*
652	* @param pThis The shared DMAR device state.
653	* @param offReg The MMIO offset of the register.
654	*/
655	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
656	{
657	uint8_t idxGroup;
658	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
659	NOREF(idxGroup);
660	return (uint32_t )(pabRegs + offReg);
661	}
662
663
664	/**
665	* Reads a 64-bit register with exactly the value it contains.
666	*
667	* @param pThis The shared DMAR device state.
668	* @param offReg The MMIO offset of the register.
669	*/
670	static uint32_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
671	{
672	uint8_t idxGroup;
673	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
674	NOREF(idxGroup);
675	return (uint64_t )(pabRegs + offReg);
676	}
677
678
679	/**
680	* Reads a 32-bit register with exactly the value it contains along with their
681	* corresponding masks
682	*
683	* @param pThis The shared DMAR device state.
684	* @param offReg The MMIO offset of the register.
685	* @param puReg Where to store the raw 32-bit register value.
686	* @param pfRwMask Where to store the RW mask corresponding to this register.
687	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
688	*/
689	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
690	{
691	uint8_t idxGroup;
692	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
693	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
694	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
695	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
696	puReg = (uint32_t *)(pabRegs + offReg);
697	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
698	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
699	}
700
701
702	/**
703	* Reads a 64-bit register with exactly the value it contains along with their
704	* corresponding masks.
705	*
706	* @param pThis The shared DMAR device state.
707	* @param offReg The MMIO offset of the register.
708	* @param puReg Where to store the raw 64-bit register value.
709	* @param pfRwMask Where to store the RW mask corresponding to this register.
710	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
711	*/
712	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
713	{
714	uint8_t idxGroup;
715	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
716	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
717	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
718	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
719	puReg = (uint64_t *)(pabRegs + offReg);
720	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
721	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
722	}
723
724
725	/**
726	* Writes a 32-bit register as it would be when written by software.
727	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
728	*
729	* @returns The value that's actually written to the register.
730	* @param pThis The shared DMAR device state.
731	* @param offReg The MMIO offset of the register.
732	* @param uReg The 32-bit value to write.
733	*/
734	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
735	{
736	/* Read current value from the 32-bit register. */
737	uint32_t uCurReg;
738	uint32_t fRwMask;
739	uint32_t fRw1cMask;
740	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
741
742	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
743	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
744	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
745	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
746
747	/* Write new value to the 32-bit register. */
748	dmarRegWriteRaw32(pThis, offReg, uNewReg);
749	return uNewReg;
750	}
751
752
753	/**
754	* Writes a 64-bit register as it would be when written by software.
755	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
756	*
757	* @returns The value that's actually written to the register.
758	* @param pThis The shared DMAR device state.
759	* @param offReg The MMIO offset of the register.
760	* @param uReg The 64-bit value to write.
761	*/
762	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
763	{
764	/* Read current value from the 64-bit register. */
765	uint64_t uCurReg;
766	uint64_t fRwMask;
767	uint64_t fRw1cMask;
768	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
769
770	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
771	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
772	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
773	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
774
775	/* Write new value to the 64-bit register. */
776	dmarRegWriteRaw64(pThis, offReg, uNewReg);
777	return uNewReg;
778	}
779
780
781	/**
782	* Reads a 32-bit register as it would be when read by software.
783	*
784	* @returns The 32-bit register value.
785	* @param pThis The shared DMAR device state.
786	* @param offReg The MMIO offset of the register.
787	*/
788	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
789	{
790	return dmarRegReadRaw32(pThis, offReg);
791	}
792
793
794	/**
795	* Reads a 64-bit register as it would be when read by software.
796	*
797	* @returns The 64-bit register value.
798	* @param pThis The shared DMAR device state.
799	* @param offReg The MMIO offset of the register.
800	*/
801	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
802	{
803	return dmarRegReadRaw64(pThis, offReg);
804	}
805
806
807	/**
808	* Modifies a 32-bit register.
809	*
810	* @param pThis The shared DMAR device state.
811	* @param offReg The MMIO offset of the register.
812	* @param fAndMask The AND mask (applied first).
813	* @param fOrMask The OR mask.
814	* @remarks This does NOT apply RO or RW1C masks while modifying the
815	* register.
816	*/
817	static void dmarRegChange32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
818	{
819	uint32_t uReg = dmarRegRead32(pThis, offReg);
820	uReg = (uReg & fAndMask) \| fOrMask;
821	dmarRegWriteRaw32(pThis, offReg, uReg);
822	}
823
824
825	/**
826	* Modifies a 64-bit register.
827	*
828	* @param pThis The shared DMAR device state.
829	* @param offReg The MMIO offset of the register.
830	* @param fAndMask The AND mask (applied first).
831	* @param fOrMask The OR mask.
832	* @remarks This does NOT apply RO or RW1C masks while modifying the
833	* register.
834	*/
835	static void dmarRegChange64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
836	{
837	uint64_t uReg = dmarRegRead64(pThis, offReg);
838	uReg = (uReg & fAndMask) \| fOrMask;
839	dmarRegWriteRaw64(pThis, offReg, uReg);
840	}
841
842
843	/**
844	* Gets the table translation mode from the RTADDR_REG.
845	*
846	* @returns The table translation mode.
847	* @param pThis The shared DMAR device state.
848	*/
849	static uint8_t dmarRtAddrRegGetTtm(PCDMAR pThis)
850	{
851	uint64_t const uRtAddrReg = dmarRegRead64(pThis, VTD_MMIO_OFF_RTADDR_REG);
852	return RT_BF_GET(uRtAddrReg, VTD_BF_RTADDR_REG_TTM);
853	}
854
855
856	/**
857	* Checks whether the invalidation-queue is empty.
858	*
859	* @returns @c true if empty, @c false otherwise.
860	* @param pThis The shared DMAR device state.
861	*/
862	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
863	{
864	uint64_t const uIqtReg = dmarRegRead64(pThis, VTD_MMIO_OFF_IQT_REG);
865	uint32_t const offQueueTail = VTD_IQT_REG_GET_QT(uIqtReg);
866
867	uint64_t const uIqhReg = dmarRegRead64(pThis, VTD_MMIO_OFF_IQH_REG);
868	uint32_t const offQueueHead = VTD_IQT_REG_GET_QH(uIqhReg);
869
870	return offQueueTail == offQueueHead;
871	}
872
873
874	/**
875	* Checks whether the invalidation-queue is capable of processing requests.
876	*
877	* @returns @c true if the invalidation-queue can be processed, @c false otherwise.
878	* @param pThis The shared DMAR device state.
879	*/
880	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
881	{
882	/* Check if queued-invalidation is enabled. */
883	uint32_t const uGstsReg = dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG);
884	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
885	{
886	/* Check if there are no IQ errors and that the queue isn't empty. */
887	uint32_t const uFstsReg = dmarRegRead32(pThis, VTD_MMIO_OFF_FSTS_REG);
888	if ( !(uFstsReg & VTD_BF_FSTS_REG_IQE_MASK)
889	&& !dmarInvQueueIsEmpty(pThis))
890	return true;
891	}
892	return false;
893	}
894
895
896	/**
897	* Wakes up the invalidation-queue thread if there are requests to be processed.
898	*
899	* @param pDevIns The IOMMU device instance.
900	*/
901	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
902	{
903	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
904	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
905	Log4Func(("\n"));
906
907	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
908
909	if ( dmarInvQueueCanProcessRequests(pThis)
910	&& !ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, true))
911	{
912	Log4Func(("Signaling the invalidation-queue thread\n"));
913	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
914	}
915	}
916
917
918	/**
919	* Raises an interrupt in response to an event.
920	*
921	* @param pDevIns The IOMMU device instance.
922	*/
923	static void dmarFaultRaiseInterrupt(PPDMDEVINS pDevIns)
924	{
925	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
926	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
927	#ifdef RT_STRICT
928	{
929	uint32_t const uFstsReg = dmarRegRead32(pThis, VTD_MMIO_OFF_FSTS_REG);
930	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
931	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
932	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
933	\| VTD_BF_FSTS_REG_IQE_MASK;
934	Assert(uFstsReg & fFaultMask);
935	}
936	#endif
937
938	uint32_t uFectlReg = dmarRegRead32(pThis, VTD_MMIO_OFF_FECTL_REG);
939	if (!(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
940	{
941	MSIMSG Msi;
942	Msi.Addr.u64 = RT_MAKE_U64(dmarRegRead32(pThis, VTD_MMIO_OFF_FEADDR_REG),
943	dmarRegRead32(pThis, VTD_MMIO_OFF_FEUADDR_REG));
944	Msi.Data.u32 = dmarRegRead32(pThis, VTD_MMIO_OFF_FEDATA_REG);
945
946	/** @todo Assert Msi.Addr is in the MSR_IA32_APICBASE_ADDR range and ensure on
947	* FEADD_REG write it can't be anything else. */
948
949	/* Software has unmasked the interrupt, raise it. */
950	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
951
952	/* Clear interrupt pending bit. */
953	uFectlReg &= ~VTD_BF_FECTL_REG_IP_MASK;
954	dmarRegWrite32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
955	}
956	else
957	{
958	/* Interrupt is masked, set the interrupt pending bit. */
959	uFectlReg \|= VTD_BF_FECTL_REG_IP_MASK;
960	dmarRegWrite32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
961	}
962	}
963
964
965	#if 0
966	/**
967	* Checks whether a primary fault can be recorded.
968	*
969	* @returns @c true if the fault can be recorded, @c false otherwise.
970	* @param pThis The shared DMAR device state.
971	*/
972	static bool dmarPrimaryFaultCanRecord(PDMAR pThis)
973	{
974	uint32_t uFstsReg = dmarRegRead32(pThis, VTD_MMIO_OFF_FSTS_REG);
975	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
976	return false;
977
978	/*
979	* If we add more FRCD registers, we'll have to loop through them here.
980	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
981	* nor do we need to increment FRI.
982	*
983	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
984	*/
985	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
986	uint64_t const uFrcdRegHi = dmarRegRead64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
987	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
988	{
989	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
990	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
991	return false;
992	}
993
994	uFstsReg \|= VTD_BF_FSTS_REG_PPF_MASK;
995	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
996	return true;
997	}
998	#endif
999
1000
1001	/**
1002	* Records an IQE fault.
1003	*
1004	* @param pDevIns The IOMMU device instance.
1005	* @param enmIqei The IQE information.
1006	* @param enmDiag The diagnostic reason.
1007	*/
1008	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IQERCD_IQEI_T enmIqei)
1009	{
1010	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1011	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1012	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1013
1014	/* Always update the latest diagnostic reason. */
1015	pThis->enmDiag = enmDiag;
1016
1017	/* Set the error bit. */
1018	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1019	dmarRegChange32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1020
1021	/* Set the error information. */
1022	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1023	dmarRegChange64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1024
1025	dmarFaultRaiseInterrupt(pDevIns);
1026	}
1027
1028
1029	/**
1030	* Handles writes to CCMD_REG.
1031	*
1032	* @returns Strict VBox status code.
1033	* @param pDevIns The IOMMU device instance.
1034	* @param offReg The MMIO register offset.
1035	* @param cbReg The size of the MMIO access (in bytes).
1036	* @param uCcmdReg The value written to CCMD_REG.
1037	*/
1038	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1039	{
1040	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1041	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1042	{
1043	/* Check if we need to invalidate the context-context. */
1044	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1045	if (fIcc)
1046	{
1047	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1048	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1049	if (uMajorVersion < 6)
1050	{
1051	/** @todo Verify queued-invalidation is not enabled.
1052	* See Intel VT-d spec. 6.5.1 "Register-based Invalidation Interface" */
1053
1054	/* Verify table translation mode is legacy. */
1055	uint8_t const fTtm = dmarRtAddrRegGetTtm(pThis);
1056	if (fTtm == VTD_TTM_LEGACY_MODE)
1057	{
1058	/** @todo Invalidate. */
1059	return VINF_SUCCESS;
1060	}
1061	}
1062
1063	/** @todo Record error. */
1064	}
1065	}
1066	return VINF_SUCCESS;
1067	}
1068
1069
1070	/**
1071	* Handles writes to IQT_REG.
1072	*
1073	* @returns Strict VBox status code.
1074	* @param pDevIns The IOMMU device instance.
1075	* @param offReg The MMIO register offset.
1076	* @param uIqtReg The value written to IQT_REG.
1077	*/
1078	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1079	{
1080	/* We only care about the low 32-bits, high 32-bits are reserved. */
1081	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1082	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1083
1084	uint32_t const offQt = VTD_IQT_REG_GET_QT(uIqtReg);
1085	uint64_t const uIqaReg = dmarRegRead64(pThis, VTD_MMIO_OFF_IQA_REG);
1086	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1087
1088	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1089	if ( fDw != VTD_IQA_REG_DW_256_BIT
1090	\|\| !(offQt & RT_BIT(4)))
1091	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1092	else
1093	{
1094	/* Hardware treats bit 4 as RsvdZ here, so clear it. */
1095	dmarRegChange32(pThis, offReg, ~RT_BIT(4) /* fAndMask/ , 0 / fOrMask */);
1096	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, kQueueTailNotAligned);
1097	}
1098	return VINF_SUCCESS;
1099	}
1100
1101
1102	/**
1103	* Handles writes to IQA_REG.
1104	*
1105	* @returns Strict VBox status code.
1106	* @param pDevIns The IOMMU device instance.
1107	* @param offReg The MMIO register offset.
1108	* @param uIqaReg The value written to IQA_REG.
1109	*/
1110	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1111	{
1112	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1113	Assert(offReg == VTD_MMIO_OFF_IQA_REG);
1114
1115	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1116	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1117	* cannot happen or that it's ignored when it does happen. */
1118
1119	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1120	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1121	if (fDw == VTD_IQA_REG_DW_256_BIT)
1122	{
1123	bool const fSupports256BitDw = (pThis->fExtCap & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1124	if (fSupports256BitDw)
1125	{ /* likely */ }
1126	else
1127	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_Invalid, kInvalidDescriptorWidth);
1128	}
1129	return VINF_SUCCESS;
1130	}
1131
1132
1133	/**
1134	* Memory access bulk (one or more 4K pages) request from a device.
1135	*
1136	* @returns VBox status code.
1137	* @param pDevIns The IOMMU device instance.
1138	* @param idDevice The device ID (bus, device, function).
1139	* @param cIovas The number of addresses being accessed.
1140	* @param pauIovas The I/O virtual addresses for each page being accessed.
1141	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1142	* @param paGCPhysSpa Where to store the translated physical addresses.
1143	*
1144	* @thread Any.
1145	*/
1146	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1147	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1148	{
1149	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1150	return VERR_NOT_IMPLEMENTED;
1151	}
1152
1153
1154	/**
1155	* Memory access transaction from a device.
1156	*
1157	* @returns VBox status code.
1158	* @param pDevIns The IOMMU device instance.
1159	* @param idDevice The device ID (bus, device, function).
1160	* @param uIova The I/O virtual address being accessed.
1161	* @param cbIova The size of the access.
1162	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1163	* @param pGCPhysSpa Where to store the translated system physical address.
1164	* @param pcbContiguous Where to store the number of contiguous bytes translated
1165	* and permission-checked.
1166	*
1167	* @thread Any.
1168	*/
1169	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1170	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
1171	{
1172	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
1173	return VERR_NOT_IMPLEMENTED;
1174	}
1175
1176
1177	/**
1178	* Interrupt remap request from a device.
1179	*
1180	* @returns VBox status code.
1181	* @param pDevIns The IOMMU device instance.
1182	* @param idDevice The device ID (bus, device, function).
1183	* @param pMsiIn The source MSI.
1184	* @param pMsiOut Where to store the remapped MSI.
1185	*/
1186	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1187	{
1188	RT_NOREF3(idDevice, pMsiIn, pMsiOut);
1189	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1190	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap)); NOREF(pThis);
1191
1192	return VERR_NOT_IMPLEMENTED;
1193	}
1194
1195
1196	/**
1197	* @callback_method_impl{FNIOMMMIONEWWRITE}
1198	*/
1199	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1200	{
1201	RT_NOREF1(pvUser);
1202	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1203
1204	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1205	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1206
1207	uint16_t const offReg = off;
1208	uint16_t const offLast = offReg + cb - 1;
1209	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1210	{
1211	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1212	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
1213
1214	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv)
1215	: dmarRegWrite32(pThis, offReg, (uint32_t )pv);
1216	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1217	switch (off)
1218	{
1219	case VTD_MMIO_OFF_CCMD_REG:
1220	case VTD_MMIO_OFF_CCMD_REG + 4:
1221	{
1222	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
1223	break;
1224	}
1225
1226	case VTD_MMIO_OFF_IQT_REG:
1227	/* VTD_MMIO_OFF_IQT_REG + 4: (RsvdZ) */
1228	{
1229	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
1230	break;
1231	}
1232
1233	case VTD_MMIO_OFF_IQA_REG:
1234	/* VTD_MMIO_OFF_IQA_REG + 4: (Data) */
1235	{
1236	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
1237	break;
1238	}
1239	}
1240
1241	DMAR_UNLOCK(pDevIns, pThisCC);
1242	LogFlowFunc(("offReg=%#x rc=%Rrc\n", offReg, VBOXSTRICTRC_VAL(rcStrict)));
1243	return rcStrict;
1244	}
1245
1246	return VINF_IOM_MMIO_UNUSED_FF;
1247	}
1248
1249
1250	/**
1251	* @callback_method_impl{FNIOMMMIONEWREAD}
1252	*/
1253	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1254	{
1255	RT_NOREF1(pvUser);
1256	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1257
1258	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1259	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1260
1261	uint16_t const offReg = off;
1262	uint16_t const offLast = offReg + cb - 1;
1263	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1264	{
1265	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1266	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
1267
1268	if (cb == 8)
1269	{
1270	(uint64_t )pv = dmarRegRead64(pThis, offReg);
1271	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
1272	}
1273	else
1274	{
1275	(uint32_t )pv = dmarRegRead32(pThis, offReg);
1276	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
1277	}
1278
1279	DMAR_UNLOCK(pDevIns, pThisCC);
1280	return VINF_SUCCESS;
1281	}
1282
1283	return VINF_IOM_MMIO_UNUSED_FF;
1284	}
1285
1286
1287	#ifdef IN_RING3
1288	/**
1289	* The invalidation-queue thread.
1290	*
1291	* @returns VBox status code.
1292	* @param pDevIns The IOMMU device instance.
1293	* @param pThread The command thread.
1294	*/
1295	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1296	{
1297	NOREF(pThread);
1298	LogFlowFunc(("\n"));
1299
1300	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
1301	return VINF_SUCCESS;
1302
1303	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1304	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1305
1306	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
1307	{
1308	/*
1309	* Sleep until we are woken up.
1310	*/
1311	bool const fSignaled = ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, false);
1312	if (!fSignaled)
1313	{
1314	int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
1315	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
1316	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
1317	break;
1318	ASMAtomicWriteBool(&pThis->fInvQueueThreadSignaled, false);
1319	}
1320
1321	/*
1322	* Fetch and process invalidation requests.
1323	*/
1324	DMAR_LOCK_RET(pDevIns, pThisR3, VERR_IGNORED);
1325	/** @todo use dmarInvQueueCanProcessRequests instead? */
1326	uint32_t const uGstsReg = dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG);
1327	DMAR_UNLOCK(pDevIns, pThisR3);
1328
1329	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1330	{
1331	/** @todo Read invalidation descriptors and perform invalidation. */
1332	}
1333	}
1334
1335	LogFlowFunc(("Invalidation-queue thread terminating\n"));
1336	return VINF_SUCCESS;
1337	}
1338
1339
1340	/**
1341	* Wakes up the invalidation-queue thread so it can respond to a state
1342	* change.
1343	*
1344	* @returns VBox status code.
1345	* @param pDevIns The IOMMU device instance.
1346	* @param pThread The invalidation-queue thread.
1347	*
1348	* @thread EMT.
1349	*/
1350	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1351	{
1352	RT_NOREF(pThread);
1353	LogFlowFunc(("\n"));
1354	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1355	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1356	}
1357
1358
1359	/**
1360	* @callback_method_impl{FNDBGFHANDLERDEV}
1361	*/
1362	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1363	{
1364	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1365	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1366	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1367
1368	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
1369
1370	DMARDIAG const enmDiag = pThis->enmDiag;
1371	const char *pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
1372
1373	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
1374	pHlp->pfnPrintf(pHlp, " Diag = %u (%s)\n", enmDiag, pszDiag);
1375	pHlp->pfnPrintf(pHlp, "\n");
1376	}
1377
1378
1379	/**
1380	* Initializes all registers in the DMAR unit.
1381	*
1382	* @param pDevIns The IOMMU device instance.
1383	*/
1384	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
1385	{
1386	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1387	RT_ZERO(pThis->abRegs0);
1388	RT_ZERO(pThis->abRegs1);
1389
1390	/*
1391	* Initialize registers not mutable by software prior to initializing other registers.
1392	*/
1393	/* VER_REG */
1394	{
1395	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
1396	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
1397	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
1398	}
1399
1400	uint8_t const fFlts = 1; /* First-Level translation support. */
1401	uint8_t const fSlts = 1; /* Second-Level translation support. */
1402	uint8_t const fPt = 1; /* Pass-Through support. */
1403	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
1404	uint8_t const fNest = 0; /* Nested translation support. */
1405
1406	/* CAP_REG */
1407	{
1408	uint8_t cGstPhysAddrBits;
1409	uint8_t cGstLinearAddrBits;
1410	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
1411
1412	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
1413	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
1414	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
1415	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
1416	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
1417	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
1418	uint8_t const fMamv = (fSl2gp ? /* Maximum address mask value (for second-level invalidations). */
1419	X86_PAGE_1G_SHIFT : X86_PAGE_2M_SHIFT) - X86_PAGE_4K_SHIFT;
1420	uint8_t const fNd = 2; /* Number of domains (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
1421	7=Reserved). */
1422	uint8_t const fPsi = 1; /* Page selective invalidation. */
1423	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
1424	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
1425	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
1426
1427	pThis->fCap = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
1428	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
1429	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
1430	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
1431	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
1432	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
1433	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
1434	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
1435	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
1436	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
1437	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
1438	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
1439	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
1440	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
1441	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
1442	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
1443	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
1444	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
1445	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
1446	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, 0) /* Whether we invalidate interrupt cache on SIRTP flow. */
1447	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, 0); /* Whether we invalidate translation cache on SRTP flow. */
1448	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCap);
1449	}
1450
1451	/* ECAP_REG */
1452	{
1453	uint8_t const fQi = 1; /* Queued-invalidations. */
1454	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
1455	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
1456	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
1457	uint8_t const fSrs = 1; /* Supervisor request support. */
1458	uint8_t const fEim = 1; /* Extended interrupt mode.*/
1459	uint8_t const fAdms = 1; /* Abort DMA mode support. */
1460
1461	pThis->fExtCap = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
1462	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, 1)
1463	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
1464	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
1465	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
1466	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
1467	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
1468	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
1469	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
1470	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
1471	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
1472	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
1473	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
1474	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
1475	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
1476	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
1477	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
1478	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
1479	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
1480	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
1481	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
1482	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
1483	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
1484	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
1485	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
1486	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
1487	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
1488	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
1489	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
1490	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCap);
1491	}
1492
1493	/*
1494	* Initialize registers mutable by software.
1495	*/
1496	/* FECTL_REG */
1497	{
1498	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
1499	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
1500	}
1501
1502	/* ICETL_REG */
1503	{
1504	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
1505	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
1506	}
1507
1508	#ifdef VBOX_STRICT
1509	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
1510	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
1511	#endif
1512	}
1513
1514
1515	/**
1516	* @interface_method_impl{PDMDEVREG,pfnReset}
1517	*/
1518	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
1519	{
1520	RT_NOREF1(pDevIns);
1521	LogFlowFunc(("\n"));
1522
1523	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1524	DMAR_LOCK(pDevIns, pThisR3);
1525
1526	dmarR3RegsInit(pDevIns);
1527
1528	DMAR_UNLOCK(pDevIns, pThisR3);
1529	}
1530
1531
1532	/**
1533	* @interface_method_impl{PDMDEVREG,pfnDestruct}
1534	*/
1535	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
1536	{
1537	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1538	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1539	LogFlowFunc(("\n"));
1540
1541	DMAR_LOCK_RET(pDevIns, pThisR3, VERR_IGNORED);
1542
1543	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
1544	{
1545	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
1546	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
1547	}
1548
1549	DMAR_UNLOCK(pDevIns, pThisR3);
1550	return VINF_SUCCESS;
1551	}
1552
1553
1554	/**
1555	* @interface_method_impl{PDMDEVREG,pfnConstruct}
1556	*/
1557	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1558	{
1559	RT_NOREF(pCfg);
1560
1561	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1562	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
1563	pThisR3->pDevInsR3 = pDevIns;
1564
1565	LogFlowFunc(("iInstance=%d\n", iInstance));
1566	NOREF(iInstance);
1567
1568	/*
1569	* Register the IOMMU with PDM.
1570	*/
1571	PDMIOMMUREGR3 IommuReg;
1572	RT_ZERO(IommuReg);
1573	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
1574	IommuReg.pfnMemAccess = iommuIntelMemAccess;
1575	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
1576	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
1577	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
1578	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
1579	if (RT_FAILURE(rc))
1580	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
1581	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
1582	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1583	N_("IOMMU helper version mismatch; got %#x expected %#x"),
1584	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
1585	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
1586	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
1587	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
1588	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
1589	/*
1590	* Use PDM's critical section (via helpers) for the IOMMU device.
1591	*/
1592	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1593	AssertRCReturn(rc, rc);
1594
1595	/*
1596	* Initialize PCI configuration registers.
1597	*/
1598	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1599	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1600
1601	/* Header. */
1602	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
1603	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
1604	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
1605	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
1606	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
1607	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
1608	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
1609	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
1610
1611	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
1612	PDMPciDevSetStatus(pPciDev, 0);
1613	PDMPciDevSetCapabilityList(pPciDev, 0);
1614
1615	/** @todo VTBAR at 0x180? */
1616
1617	/*
1618	* Register the PCI function with PDM.
1619	*/
1620	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
1621	AssertLogRelRCReturn(rc, rc);
1622
1623	/** @todo Register MSI but what's the MSI capability offset? */
1624	#if 0
1625	/*
1626	* Register MSI support for the PCI device.
1627	* This must be done -after- registering it as a PCI device!
1628	*/
1629	#endif
1630
1631	/*
1632	* Register MMIO region.
1633	*/
1634	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
1635	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
1636	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
1637	&pThis->hMmio);
1638	AssertLogRelRCReturn(rc, rc);
1639
1640	/*
1641	* Register debugger info items.
1642	*/
1643	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
1644	AssertLogRelRCReturn(rc, rc);
1645
1646	#ifdef VBOX_WITH_STATISTICS
1647	/*
1648	* Statistics.
1649	*/
1650	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
1651	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
1652
1653	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
1654	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
1655
1656	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
1657	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
1658
1659	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
1660	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
1661
1662	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
1663	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
1664
1665	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
1666	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
1667
1668	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
1669	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
1670	#endif
1671
1672	/*
1673	* Initialize registers.
1674	*/
1675	dmarR3RegsInit(pDevIns);
1676
1677	/*
1678	* Create invalidation-queue thread and semaphore.
1679	*/
1680	char szInvQueueThread[32];
1681	RT_ZERO(szInvQueueThread);
1682	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
1683	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
1684	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
1685	AssertLogRelRCReturn(rc, rc);
1686
1687	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
1688	AssertLogRelRCReturn(rc, rc);
1689
1690	/*
1691	* Log some of the features exposed to software.
1692	*/
1693	uint32_t const uVerReg = pThis->uVerReg;
1694	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_MGAW) + 1;
1695	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_SAGAW));
1696	uint16_t const offFrcd = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_FRO);
1697	uint16_t const offIva = RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_IRO);
1698	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
1699	DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
1700	pThis->fCap, pThis->fExtCap, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
1701
1702	return VINF_SUCCESS;
1703	}
1704
1705	#else
1706
1707	/**
1708	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1709	*/
1710	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
1711	{
1712	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1713	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1714	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
1715	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
1716
1717	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
1718	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1719	AssertRCReturn(rc, rc);
1720
1721	/* Set up the MMIO RZ handlers. */
1722	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
1723	AssertRCReturn(rc, rc);
1724
1725	/* Set up the IOMMU RZ callbacks. */
1726	PDMIOMMUREGCC IommuReg;
1727	RT_ZERO(IommuReg);
1728	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
1729	IommuReg.idxIommu = pThis->idxIommu;
1730	IommuReg.pfnMemAccess = iommuIntelMemAccess;
1731	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
1732	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
1733	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
1734
1735	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
1736	AssertRCReturn(rc, rc);
1737	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
1738	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
1739	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
1740	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
1741	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
1742	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
1743	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
1744
1745	return VINF_SUCCESS;
1746	}
1747
1748	#endif
1749
1750
1751	/**
1752	* The device registration structure.
1753	*/
1754	PDMDEVREG const g_DeviceIommuIntel =
1755	{
1756	/* .u32Version = */ PDM_DEVREG_VERSION,
1757	/* .uReserved0 = */ 0,
1758	/* .szName = */ "iommu-intel",
1759	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1760	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
1761	/* .cMaxInstances = */ 1,
1762	/* .uSharedVersion = */ 42,
1763	/* .cbInstanceShared = */ sizeof(DMAR),
1764	/* .cbInstanceCC = */ sizeof(DMARCC),
1765	/* .cbInstanceRC = */ sizeof(DMARRC),
1766	/* .cMaxPciDevices = */ 1,
1767	/* .cMaxMsixVectors = */ 0,
1768	/* .pszDescription = */ "IOMMU (Intel)",
1769	#if defined(IN_RING3)
1770	/* .pszRCMod = */ "VBoxDDRC.rc",
1771	/* .pszR0Mod = */ "VBoxDDR0.r0",
1772	/* .pfnConstruct = */ iommuIntelR3Construct,
1773	/* .pfnDestruct = */ iommuIntelR3Destruct,
1774	/* .pfnRelocate = */ NULL,
1775	/* .pfnMemSetup = */ NULL,
1776	/* .pfnPowerOn = */ NULL,
1777	/* .pfnReset = */ iommuIntelR3Reset,
1778	/* .pfnSuspend = */ NULL,
1779	/* .pfnResume = */ NULL,
1780	/* .pfnAttach = */ NULL,
1781	/* .pfnDetach = */ NULL,
1782	/* .pfnQueryInterface = */ NULL,
1783	/* .pfnInitComplete = */ NULL,
1784	/* .pfnPowerOff = */ NULL,
1785	/* .pfnSoftReset = */ NULL,
1786	/* .pfnReserved0 = */ NULL,
1787	/* .pfnReserved1 = */ NULL,
1788	/* .pfnReserved2 = */ NULL,
1789	/* .pfnReserved3 = */ NULL,
1790	/* .pfnReserved4 = */ NULL,
1791	/* .pfnReserved5 = */ NULL,
1792	/* .pfnReserved6 = */ NULL,
1793	/* .pfnReserved7 = */ NULL,
1794	#elif defined(IN_RING0)
1795	/* .pfnEarlyConstruct = */ NULL,
1796	/* .pfnConstruct = */ iommuIntelRZConstruct,
1797	/* .pfnDestruct = */ NULL,
1798	/* .pfnFinalDestruct = */ NULL,
1799	/* .pfnRequest = */ NULL,
1800	/* .pfnReserved0 = */ NULL,
1801	/* .pfnReserved1 = */ NULL,
1802	/* .pfnReserved2 = */ NULL,
1803	/* .pfnReserved3 = */ NULL,
1804	/* .pfnReserved4 = */ NULL,
1805	/* .pfnReserved5 = */ NULL,
1806	/* .pfnReserved6 = */ NULL,
1807	/* .pfnReserved7 = */ NULL,
1808	#elif defined(IN_RC)
1809	/* .pfnConstruct = */ iommuIntelRZConstruct,
1810	/* .pfnReserved0 = */ NULL,
1811	/* .pfnReserved1 = */ NULL,
1812	/* .pfnReserved2 = */ NULL,
1813	/* .pfnReserved3 = */ NULL,
1814	/* .pfnReserved4 = */ NULL,
1815	/* .pfnReserved5 = */ NULL,
1816	/* .pfnReserved6 = */ NULL,
1817	/* .pfnReserved7 = */ NULL,
1818	#else
1819	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1820	#endif
1821	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1822	};
1823
1824	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1825

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88675

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