DevIommuIntel.cpp@ 88968

Last change on this file since 88968 was 88894, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Interrupt remapping, work-in-progress.
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1	/* $Id: DevIommuIntel.cpp 88894 2021-05-06 09:46:39Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock (not expected to fail). */
67	#ifdef IN_RING3
68	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69	#else
70	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71	do { \
72	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73	AssertRC(rcLock); \
74	} while (0)
75	#endif
76
77	/** Release the DMAR lock. */
78	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80	/** Asserts that the calling thread owns the DMAR lock. */
81	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82	do { \
83	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84	RT_NOREF1(a_pThisCC); \
85	} while (0)
86
87	/** Asserts that the calling thread does not own the DMAR lock. */
88	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89	do { \
90	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91	RT_NOREF1(a_pThisCC); \
92	} while (0)
93
94	/** The number of fault recording registers our implementation supports.
95	* Normal guest operation shouldn't trigger faults anyway, so we only support the
96	* minimum number of registers (which is 1).
97	*
98	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101	/** Offset of first register in group 0. */
102	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
103	/** Offset of last register in group 0 (inclusive). */
104	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
105	/** Last valid offset in group 0 (exclusive). */
106	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
107	/** Size of the group 0 (in bytes). */
108	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
109	/*< Implementation-specific MMIO offset of IVA_REG. /
110	#define DMAR_MMIO_OFF_IVA_REG 0xe50
111	/*< Implementation-specific MMIO offset of IOTLB_REG. /
112	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
113	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
114	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
115	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
116	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
117	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
118
119	/** Offset of first register in group 1. */
120	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
121	/** Offset of last register in group 1 (inclusive). */
122	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
123	/** Last valid offset in group 1 (exclusive). */
124	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
125	/** Size of the group 1 (in bytes). */
126	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
127
128	/** DMAR implementation's major version number (exposed to software).
129	* We report 6 as the major version since we support queued-invalidations as
130	* software may make assumptions based on that.
131	*
132	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
133	#define DMAR_VER_MAJOR 6
134	/** DMAR implementation's minor version number (exposed to software). */
135	#define DMAR_VER_MINOR 0
136
137	/** Release log prefix string. */
138	#define DMAR_LOG_PFX "Intel-IOMMU"
139	/** The current saved state version. */
140	#define DMAR_SAVED_STATE_VERSION 1
141
142
143	/*********************************************************************************************************************************
144	* Structures and Typedefs *
145	*********************************************************************************************************************************/
146	/**
147	* DMAR error diagnostics.
148	* Sorted alphabetically so it's easier to add and locate items, no other reason.
149	*
150	* @note Members of this enum are used as array indices, so no gaps in enum
151	* values are not allowed. Update g_apszDmarDiagDesc when you modify
152	* fields in this enum.
153	*/
154	typedef enum
155	{
156	kDmarDiag_None = 0,
157	kDmarDiag_CcmdReg_NotSupported,
158	kDmarDiag_CcmdReg_Qi_Enabled,
159	kDmarDiag_CcmdReg_Ttm_Invalid,
160	kDmarDiag_IqaReg_Dsc_Fetch_Error,
161	kDmarDiag_IqaReg_Dw_128_Invalid,
162	kDmarDiag_IqaReg_Dw_256_Invalid,
163	kDmarDiag_Iqei_Dsc_Type_Invalid,
164	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
165	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
166	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
167	kDmarDiag_Iqei_Ttm_Rsvd,
168	kDmarDiag_IqtReg_Qt_Invalid,
169	kDmarDiag_IqtReg_Qt_NotAligned,
170	kDmarDiag_Ir_Cfi_Blocked,
171	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
172	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
173	kDmarDiag_Ir_Rfi_Irte_Not_Present,
174	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
175	kDmarDiag_Ir_Rfi_Irte_Rsvd,
176	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
177	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
178	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
179	kDmarDiag_Ir_Rfi_Rsvd,
180	/* Member for determining array index limit. */
181	kDmarDiag_End,
182	/* Type size hack. */
183	kDmarDiag_32Bit_Hack = 0x7fffffff
184	} DMARDIAG;
185	AssertCompileSize(DMARDIAG, 4);
186
187	/** DMAR diagnostic enum description expansion.
188	* The below construct ensures typos in the input to this macro are caught
189	* during compile time. */
190	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
191
192	/** DMAR diagnostics description for members in DMARDIAG. */
193	static const char *const g_apszDmarDiagDesc[] =
194	{
195	DMARDIAG_DESC(None ),
196	DMARDIAG_DESC(CcmdReg_NotSupported ),
197	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
198	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
199	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
200	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
201	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
202	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
203	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
204	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
205	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
206	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
207	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
208	DMARDIAG_DESC(IqtReg_Qt_NotAligned ),
209	DMARDIAG_DESC(Ir_Cfi_Blocked ),
210	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
211	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
212	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
213	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
214	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
215	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
216	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
217	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
218	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
219	/* kDmarDiag_End */
220	};
221	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
222	#undef DMARDIAG_DESC
223
224	/**
225	* The shared DMAR device state.
226	*/
227	typedef struct DMAR
228	{
229	/** IOMMU device index. */
230	uint32_t idxIommu;
231	/** DMAR magic. */
232	uint32_t u32Magic;
233
234	/** Registers (group 0). */
235	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
236	/** Registers (group 1). */
237	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
238
239	/** @name Lazily activated registers.
240	* These are the active values for lazily activated registers. Software is free to
241	* modify the actual register values while remapping/translation is enabled but they
242	* take effect only when explicitly signaled by software, hence we need to hold the
243	* active values separately.
244	* @{ */
245	/** Currently active IRTA_REG. */
246	uint64_t uIrtaReg;
247	/** Currently active RTADDR_REG. */
248	uint64_t uRtaddrReg;
249	/** @} */
250
251	/** @name Register copies for a tiny bit faster and more convenient access.
252	* @{ */
253	/** Copy of VER_REG. */
254	uint8_t uVerReg;
255	/** Alignment. */
256	uint8_t abPadding[7];
257	/** Copy of CAP_REG. */
258	uint64_t fCapReg;
259	/** Copy of ECAP_REG. */
260	uint64_t fExtCapReg;
261	/** @} */
262
263	/** The event semaphore the invalidation-queue thread waits on. */
264	SUPSEMEVENT hEvtInvQueue;
265	/** Whether the invalidation-queue thread has been signaled. */
266	bool volatile fInvQueueThreadSignaled;
267	/** Padding. */
268	bool afPadding0[3];
269	/** Error diagnostic. */
270	DMARDIAG enmDiag;
271	/** The MMIO handle. */
272	IOMMMIOHANDLE hMmio;
273
274	#ifdef VBOX_WITH_STATISTICS
275	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
276	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
277	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
278	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
279
280	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
281	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
282	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
283	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
284
285	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
286	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
287	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
288	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
289
290	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
291	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
292	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
293	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
294
295	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
296	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
297	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
298	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
299	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
300	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
301	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
302	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
303	#endif
304	} DMAR;
305	/** Pointer to the DMAR device state. */
306	typedef DMAR *PDMAR;
307	/** Pointer to the const DMAR device state. */
308	typedef DMAR const *PCDMAR;
309	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
310	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
311
312	/**
313	* The ring-3 DMAR device state.
314	*/
315	typedef struct DMARR3
316	{
317	/** Device instance. */
318	PPDMDEVINSR3 pDevInsR3;
319	/** The IOMMU helper. */
320	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
321	/** The invalidation-queue thread. */
322	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
323	} DMARR3;
324	/** Pointer to the ring-3 DMAR device state. */
325	typedef DMARR3 *PDMARR3;
326	/** Pointer to the const ring-3 DMAR device state. */
327	typedef DMARR3 const *PCDMARR3;
328
329	/**
330	* The ring-0 DMAR device state.
331	*/
332	typedef struct DMARR0
333	{
334	/** Device instance. */
335	PPDMDEVINSR0 pDevInsR0;
336	/** The IOMMU helper. */
337	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
338	} DMARR0;
339	/** Pointer to the ring-0 IOMMU device state. */
340	typedef DMARR0 *PDMARR0;
341	/** Pointer to the const ring-0 IOMMU device state. */
342	typedef DMARR0 const *PCDMARR0;
343
344	/**
345	* The raw-mode DMAR device state.
346	*/
347	typedef struct DMARRC
348	{
349	/** Device instance. */
350	PPDMDEVINSRC pDevInsRC;
351	/** The IOMMU helper. */
352	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
353	} DMARRC;
354	/** Pointer to the raw-mode DMAR device state. */
355	typedef DMARRC *PDMARRC;
356	/** Pointer to the const raw-mode DMAR device state. */
357	typedef DMARRC const *PCIDMARRC;
358
359	/** The DMAR device state for the current context. */
360	typedef CTX_SUFF(DMAR) DMARCC;
361	/** Pointer to the DMAR device state for the current context. */
362	typedef CTX_SUFF(PDMAR) PDMARCC;
363	/** Pointer to the const DMAR device state for the current context. */
364	typedef CTX_SUFF(PDMAR) const PCDMARCC;
365
366
367	/*********************************************************************************************************************************
368	* Global Variables *
369	*********************************************************************************************************************************/
370	/**
371	* Read-write masks for DMAR registers (group 0).
372	*/
373	static uint32_t const g_au32RwMasks0[] =
374	{
375	/* Offset Register Low High */
376	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
377	/* 0x004 Reserved */ 0,
378	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
379	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
380	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
381	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
382	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
383	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
384	/* 0x030 Reserved */ 0,
385	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
386	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
387	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
388	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
389	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
390	/* 0x048 Reserved */ 0, 0,
391	/* 0x050 Reserved */ 0, 0,
392	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
393	/* 0x060 Reserved */ 0,
394	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
395	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
396	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
397	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
398	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
399	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
400	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
401	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
402	/* 0x098 Reserved */ 0,
403	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
404	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
405	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
406	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
407	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
408	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
409	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
410	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
411	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
412	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
413	/* 0x0d8 Reserved */ 0,
414	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
415	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
416	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
417	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
418	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
419	/* 0x0f0 Reserved */ 0, 0,
420	/* 0x0f8 Reserved */ 0, 0,
421	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
422	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
423	/* 0x110 Reserved */ 0, 0,
424	/* 0x118 Reserved */ 0, 0,
425	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
426	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
427	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
428	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
429	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
430	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
431	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
432	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
433	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
434	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
435	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
436	/* 0x178 Reserved */ 0, 0,
437	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
438	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
439	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
440	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
441	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
442	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
443	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
444	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
445	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
446	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
447	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
448	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
449	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
450	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
451	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
452	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
453	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
454	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
455	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
456	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
457	};
458	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
459
460	/**
461	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
462	*/
463	static uint32_t const g_au32Rw1cMasks0[] =
464	{
465	/* Offset Register Low High */
466	/* 0x000 VER_REG */ 0,
467	/* 0x004 Reserved */ 0,
468	/* 0x008 CAP_REG */ 0, 0,
469	/* 0x010 ECAP_REG */ 0, 0,
470	/* 0x018 GCMD_REG */ 0,
471	/* 0x01c GSTS_REG */ 0,
472	/* 0x020 RTADDR_REG */ 0, 0,
473	/* 0x028 CCMD_REG */ 0, 0,
474	/* 0x030 Reserved */ 0,
475	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
476	/* 0x038 FECTL_REG */ 0,
477	/* 0x03c FEDATA_REG */ 0,
478	/* 0x040 FEADDR_REG */ 0,
479	/* 0x044 FEUADDR_REG */ 0,
480	/* 0x048 Reserved */ 0, 0,
481	/* 0x050 Reserved */ 0, 0,
482	/* 0x058 AFLOG_REG */ 0, 0,
483	/* 0x060 Reserved */ 0,
484	/* 0x064 PMEN_REG */ 0,
485	/* 0x068 PLMBASE_REG */ 0,
486	/* 0x06c PLMLIMIT_REG */ 0,
487	/* 0x070 PHMBASE_REG */ 0, 0,
488	/* 0x078 PHMLIMIT_REG */ 0, 0,
489	/* 0x080 IQH_REG */ 0, 0,
490	/* 0x088 IQT_REG */ 0, 0,
491	/* 0x090 IQA_REG */ 0, 0,
492	/* 0x098 Reserved */ 0,
493	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
494	/* 0x0a0 IECTL_REG */ 0,
495	/* 0x0a4 IEDATA_REG */ 0,
496	/* 0x0a8 IEADDR_REG */ 0,
497	/* 0x0ac IEUADDR_REG */ 0,
498	/* 0x0b0 IQERCD_REG */ 0, 0,
499	/* 0x0b8 IRTA_REG */ 0, 0,
500	/* 0x0c0 PQH_REG */ 0, 0,
501	/* 0x0c8 PQT_REG */ 0, 0,
502	/* 0x0d0 PQA_REG */ 0, 0,
503	/* 0x0d8 Reserved */ 0,
504	/* 0x0dc PRS_REG */ 0,
505	/* 0x0e0 PECTL_REG */ 0,
506	/* 0x0e4 PEDATA_REG */ 0,
507	/* 0x0e8 PEADDR_REG */ 0,
508	/* 0x0ec PEUADDR_REG */ 0,
509	/* 0x0f0 Reserved */ 0, 0,
510	/* 0x0f8 Reserved */ 0, 0,
511	/* 0x100 MTRRCAP_REG */ 0, 0,
512	/* 0x108 MTRRDEF_REG */ 0, 0,
513	/* 0x110 Reserved */ 0, 0,
514	/* 0x118 Reserved */ 0, 0,
515	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
516	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
517	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
518	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
519	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
520	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
521	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
522	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
523	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
524	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
525	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
526	/* 0x178 Reserved */ 0, 0,
527	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
528	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
529	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
530	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
531	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
532	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
533	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
534	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
535	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
536	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
537	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
538	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
539	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
540	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
541	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
542	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
543	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
544	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
545	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
546	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
547	};
548	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
549
550	/**
551	* Read-write masks for DMAR registers (group 1).
552	*/
553	static uint32_t const g_au32RwMasks1[] =
554	{
555	/* Offset Register Low High */
556	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
557	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
558	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
559	/* 0xe18 VCMDRSVD_REG */ 0, 0,
560	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
561	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
562	/* 0xe30 Reserved */ 0, 0,
563	/* 0xe38 Reserved */ 0, 0,
564	/* 0xe40 Reserved */ 0, 0,
565	/* 0xe48 Reserved */ 0, 0,
566	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
567	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
568	/* 0xe60 Reserved */ 0, 0,
569	/* 0xe68 Reserved */ 0, 0,
570	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
571	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
572	};
573	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
574	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
575
576	/**
577	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
578	*/
579	static uint32_t const g_au32Rw1cMasks1[] =
580	{
581	/* Offset Register Low High */
582	/* 0xe00 VCCAP_REG */ 0, 0,
583	/* 0xe08 VCMD_EO_REG */ 0, 0,
584	/* 0xe10 VCMD_REG */ 0, 0,
585	/* 0xe18 VCMDRSVD_REG */ 0, 0,
586	/* 0xe20 VCRSP_REG */ 0, 0,
587	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
588	/* 0xe30 Reserved */ 0, 0,
589	/* 0xe38 Reserved */ 0, 0,
590	/* 0xe40 Reserved */ 0, 0,
591	/* 0xe48 Reserved */ 0, 0,
592	/* 0xe50 IVA_REG */ 0, 0,
593	/* 0xe58 IOTLB_REG */ 0, 0,
594	/* 0xe60 Reserved */ 0, 0,
595	/* 0xe68 Reserved */ 0, 0,
596	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
597	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
598	};
599	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
600
601	/** Array of RW masks for each register group. */
602	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
603
604	/** Array of RW1C masks for each register group. */
605	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
606
607	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
608	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
609
610
611	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
612	/** @todo Add IOMMU struct size/alignment verification, see
613	* Devices/testcase/Makefile.kmk and
614	* Devices/testcase/tstDeviceStructSize[RC].cpp */
615
616	/**
617	* Returns the number of supported adjusted guest-address width (SAGAW) in bits
618	* given a CAP_REG.SAGAW value.
619	*
620	* @returns Number of SAGAW bits.
621	* @param uSagaw The CAP_REG.SAGAW value.
622	*/
623	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
624	{
625	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
626	return 30 + (uSagaw * 9);
627	return 0;
628	}
629
630
631	/**
632	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
633	* guest address width (MGAW).
634	*
635	* @returns The CAP_REG.SAGAW value.
636	* @param uMgaw The CAP_REG.MGAW value.
637	*/
638	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
639	{
640	switch (uMgaw + 1)
641	{
642	case 39: return 1;
643	case 48: return 2;
644	case 57: return 3;
645	}
646	return 0;
647	}
648
649
650	/**
651	* Returns whether the interrupt remapping fault is qualified or not.
652	*
653	* @returns @c true if qualified, @c false otherwise.
654	* @param enmIrFault The interrupt remapping fault condition.
655	*/
656	static bool vtdIrFaultIsQualified(VTD_IR_FAULT_T enmIrFault)
657	{
658	switch (enmIrFault)
659	{
660	case kIrf_Irte_Not_Present:
661	case kIrf_Irte_Present_Rsvd:
662	case kIrf_Irte_Present_Invalid:
663	case kIrf_Pid_Read_Failed:
664	case kIrf_Pid_Rsvd:
665	return true;
666	default:
667	return false;
668	}
669	}
670
671
672	/**
673	* Returns table translation mode's descriptive name.
674	*
675	* @returns The descriptive name.
676	* @param uTtm The RTADDR_REG.TTM value.
677	*/
678	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
679	{
680	Assert(!(uTtm & 3));
681	static const char* s_apszTtmNames[] =
682	{
683	"Legacy Mode",
684	"Scalable Mode",
685	"Reserved",
686	"Abort-DMA Mode"
687	};
688	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
689	}
690
691
692	/**
693	* Gets the index of the group the register belongs to given its MMIO offset.
694	*
695	* @returns The group index.
696	* @param offReg The MMIO offset of the register.
697	* @param cbReg The size of the access being made (for bounds checking on
698	* debug builds).
699	*/
700	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
701	{
702	uint16_t const offLast = offReg + cbReg - 1;
703	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
704	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
705	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
706	}
707
708
709	/**
710	* Gets the group the register belongs to given its MMIO offset.
711	*
712	* @returns Pointer to the first element of the register group.
713	* @param pThis The shared DMAR device state.
714	* @param offReg The MMIO offset of the register.
715	* @param cbReg The size of the access being made (for bounds checking on
716	* debug builds).
717	* @param pIdxGroup Where to store the index of the register group the register
718	* belongs to.
719	*/
720	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
721	{
722	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
723	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
724	return apbRegs[*pIdxGroup];
725	}
726
727
728	/**
729	* Const/read-only version of dmarRegGetGroup.
730	*
731	* @copydoc dmarRegGetGroup
732	*/
733	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
734	{
735	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
736	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
737	return apbRegs[*pIdxGroup];
738	}
739
740
741	/**
742	* Writes a 32-bit register with the exactly the supplied value.
743	*
744	* @param pThis The shared DMAR device state.
745	* @param offReg The MMIO offset of the register.
746	* @param uReg The 32-bit value to write.
747	*/
748	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
749	{
750	uint8_t idxGroup;
751	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
752	NOREF(idxGroup);
753	(uint32_t )(pabRegs + offReg) = uReg;
754	}
755
756
757	/**
758	* Writes a 64-bit register with the exactly the supplied value.
759	*
760	* @param pThis The shared DMAR device state.
761	* @param offReg The MMIO offset of the register.
762	* @param uReg The 64-bit value to write.
763	*/
764	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
765	{
766	uint8_t idxGroup;
767	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
768	NOREF(idxGroup);
769	(uint64_t )(pabRegs + offReg) = uReg;
770	}
771
772
773	/**
774	* Reads a 32-bit register with exactly the value it contains.
775	*
776	* @returns The raw register value.
777	* @param pThis The shared DMAR device state.
778	* @param offReg The MMIO offset of the register.
779	*/
780	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
781	{
782	uint8_t idxGroup;
783	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
784	NOREF(idxGroup);
785	return (uint32_t )(pabRegs + offReg);
786	}
787
788
789	/**
790	* Reads a 64-bit register with exactly the value it contains.
791	*
792	* @returns The raw register value.
793	* @param pThis The shared DMAR device state.
794	* @param offReg The MMIO offset of the register.
795	*/
796	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
797	{
798	uint8_t idxGroup;
799	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
800	NOREF(idxGroup);
801	return (uint64_t )(pabRegs + offReg);
802	}
803
804
805	/**
806	* Reads a 32-bit register with exactly the value it contains along with their
807	* corresponding masks
808	*
809	* @param pThis The shared DMAR device state.
810	* @param offReg The MMIO offset of the register.
811	* @param puReg Where to store the raw 32-bit register value.
812	* @param pfRwMask Where to store the RW mask corresponding to this register.
813	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
814	*/
815	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
816	{
817	uint8_t idxGroup;
818	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
819	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
820	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
821	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
822	puReg = (uint32_t *)(pabRegs + offReg);
823	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
824	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
825	}
826
827
828	/**
829	* Reads a 64-bit register with exactly the value it contains along with their
830	* corresponding masks.
831	*
832	* @param pThis The shared DMAR device state.
833	* @param offReg The MMIO offset of the register.
834	* @param puReg Where to store the raw 64-bit register value.
835	* @param pfRwMask Where to store the RW mask corresponding to this register.
836	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
837	*/
838	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
839	{
840	uint8_t idxGroup;
841	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
842	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
843	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
844	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
845	puReg = (uint64_t *)(pabRegs + offReg);
846	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
847	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
848	}
849
850
851	/**
852	* Writes a 32-bit register as it would be when written by software.
853	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
854	*
855	* @returns The value that's actually written to the register.
856	* @param pThis The shared DMAR device state.
857	* @param offReg The MMIO offset of the register.
858	* @param uReg The 32-bit value to write.
859	*/
860	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
861	{
862	/* Read current value from the 32-bit register. */
863	uint32_t uCurReg;
864	uint32_t fRwMask;
865	uint32_t fRw1cMask;
866	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
867
868	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
869	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
870	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
871	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
872
873	/* Write new value to the 32-bit register. */
874	dmarRegWriteRaw32(pThis, offReg, uNewReg);
875	return uNewReg;
876	}
877
878
879	/**
880	* Writes a 64-bit register as it would be when written by software.
881	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
882	*
883	* @returns The value that's actually written to the register.
884	* @param pThis The shared DMAR device state.
885	* @param offReg The MMIO offset of the register.
886	* @param uReg The 64-bit value to write.
887	*/
888	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
889	{
890	/* Read current value from the 64-bit register. */
891	uint64_t uCurReg;
892	uint64_t fRwMask;
893	uint64_t fRw1cMask;
894	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
895
896	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
897	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
898	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
899	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
900
901	/* Write new value to the 64-bit register. */
902	dmarRegWriteRaw64(pThis, offReg, uNewReg);
903	return uNewReg;
904	}
905
906
907	/**
908	* Reads a 32-bit register as it would be when read by software.
909	*
910	* @returns The register value.
911	* @param pThis The shared DMAR device state.
912	* @param offReg The MMIO offset of the register.
913	*/
914	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
915	{
916	return dmarRegReadRaw32(pThis, offReg);
917	}
918
919
920	/**
921	* Reads a 64-bit register as it would be when read by software.
922	*
923	* @returns The register value.
924	* @param pThis The shared DMAR device state.
925	* @param offReg The MMIO offset of the register.
926	*/
927	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
928	{
929	return dmarRegReadRaw64(pThis, offReg);
930	}
931
932
933	/**
934	* Modifies a 32-bit register.
935	*
936	* @param pThis The shared DMAR device state.
937	* @param offReg The MMIO offset of the register.
938	* @param fAndMask The AND mask (applied first).
939	* @param fOrMask The OR mask.
940	* @remarks This does NOT apply RO or RW1C masks while modifying the
941	* register.
942	*/
943	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
944	{
945	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
946	uReg = (uReg & fAndMask) \| fOrMask;
947	dmarRegWriteRaw32(pThis, offReg, uReg);
948	}
949
950
951	/**
952	* Modifies a 64-bit register.
953	*
954	* @param pThis The shared DMAR device state.
955	* @param offReg The MMIO offset of the register.
956	* @param fAndMask The AND mask (applied first).
957	* @param fOrMask The OR mask.
958	* @remarks This does NOT apply RO or RW1C masks while modifying the
959	* register.
960	*/
961	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
962	{
963	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
964	uReg = (uReg & fAndMask) \| fOrMask;
965	dmarRegWriteRaw64(pThis, offReg, uReg);
966	}
967
968
969	/**
970	* Checks if the invalidation-queue is empty.
971	*
972	* Extended version which optionally returns the current queue head and tail
973	* offsets.
974	*
975	* @returns @c true if empty, @c false otherwise.
976	* @param pThis The shared DMAR device state.
977	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
978	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
979	*/
980	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
981	{
982	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
983	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
984	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
985
986	/* Don't bother masking QT, QH since other bits are RsvdZ. */
987	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
988	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
989	if (poffQh)
990	*poffQh = uIqhReg;
991	if (poffQt)
992	*poffQt = uIqtReg;
993	return uIqtReg == uIqhReg;
994	}
995
996
997	/**
998	* Checks if the invalidation-queue is empty.
999	*
1000	* @returns @c true if empty, @c false otherwise.
1001	* @param pThis The shared DMAR device state.
1002	*/
1003	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1004	{
1005	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1006	}
1007
1008
1009	/**
1010	* Checks if the invalidation-queue is capable of processing requests.
1011	*
1012	* @returns @c true if the invalidation-queue can process requests, @c false
1013	* otherwise.
1014	* @param pThis The shared DMAR device state.
1015	*/
1016	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1017	{
1018	/* Check if queued-invalidation is enabled. */
1019	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1020	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1021	{
1022	/* Check if there are no invalidation-queue or timeout errors. */
1023	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1024	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1025	return true;
1026	}
1027	return false;
1028	}
1029
1030
1031	/**
1032	* Wakes up the invalidation-queue thread if there are requests to be processed.
1033	*
1034	* @param pDevIns The IOMMU device instance.
1035	*/
1036	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1037	{
1038	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1039	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1040	Log4Func(("\n"));
1041
1042	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1043
1044	if ( dmarInvQueueCanProcessRequests(pThis)
1045	&& !dmarInvQueueIsEmpty(pThis)
1046	&& !ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, true))
1047	{
1048	Log4Func(("Signaling the invalidation-queue thread\n"));
1049	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1050	}
1051	}
1052
1053
1054	/**
1055	* Raises an interrupt in response to a fault event.
1056	*
1057	* @param pDevIns The IOMMU device instance.
1058	*
1059	* @remarks This assumes the caller has already set the required status bits in the
1060	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1061	*/
1062	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1063	{
1064	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1065	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1066
1067	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1068
1069	#ifdef RT_STRICT
1070	{
1071	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1072	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1073	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1074	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1075	\| VTD_BF_FSTS_REG_IQE_MASK;
1076	Assert(uFstsReg & fFaultMask);
1077	}
1078	#endif
1079
1080	uint32_t uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
1081	if (!(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1082	{
1083	/* Software has unmasked the interrupt, raise it. */
1084	MSIMSG Msi;
1085	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
1086	Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
1087	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
1088
1089	/** @todo Assert Msi.Addr is in the MSR_IA32_APICBASE_ADDR range and ensure on
1090	* FEADD_REG write it can't be anything else? */
1091	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1092
1093	/* Clear interrupt pending bit. */
1094	uFectlReg &= ~VTD_BF_FECTL_REG_IP_MASK;
1095	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1096	}
1097	else
1098	{
1099	/* Interrupt is masked, set the interrupt pending bit. */
1100	uFectlReg \|= VTD_BF_FECTL_REG_IP_MASK;
1101	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1102	}
1103	}
1104
1105
1106	#ifdef IN_RING3
1107	/**
1108	* Raises an interrupt in response to an invalidation (complete) event.
1109	*
1110	* @param pDevIns The IOMMU device instance.
1111	*/
1112	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1113	{
1114	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1115	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1116
1117	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1118
1119	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1120	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1121	{
1122	uint32_t uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
1123	if (!(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1124	{
1125	/* Software has unmasked the interrupt, raise it. */
1126	MSIMSG Msi;
1127	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
1128	Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
1129	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
1130
1131	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1132
1133	/* Clear interrupt pending bit. */
1134	uIectlReg &= ~VTD_BF_IECTL_REG_IP_MASK;
1135	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
1136	}
1137	else
1138	{
1139	/* Interrupt is masked, set the interrupt pending bit. */
1140	uIectlReg \|= VTD_BF_IECTL_REG_IP_MASK;
1141	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
1142	}
1143	}
1144	}
1145	#endif /* IN_RING3 */
1146
1147
1148	/**
1149	* Checks if a primary fault can be recorded.
1150	*
1151	* @returns @c true if the fault can be recorded, @c false otherwise.
1152	* @param pDevIns The IOMMU device instance.
1153	* @param pThis The shared DMAR device state.
1154	*
1155	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1156	* NOT call it unless there is a fault condition!
1157	*/
1158	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1159	{
1160	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1161	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1162
1163	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1164	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1165	return false;
1166
1167	/*
1168	* If we add more FRCD registers, we'll have to loop through them here.
1169	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1170	* nor do we need to increment FRI.
1171	*
1172	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1173	*/
1174	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1175	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1176	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1177	{
1178	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1179	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1180	return false;
1181	}
1182
1183	return true;
1184	}
1185
1186
1187	/**
1188	* Records an interrupt request fault.
1189	*
1190	* @param pDevIns The IOMMU device instance.
1191	* @param enmDiag The diagnostic reason.
1192	* @param enmIrFault The interrupt fault reason.
1193	* @param idDevice The device ID (bus, device, function).
1194	* @param idxIntr The interrupt index.
1195	*/
1196	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IR_FAULT_T enmIrFault, uint16_t idDevice,
1197	uint16_t idxIntr)
1198	{
1199	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1200	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1201
1202	DMAR_LOCK(pDevIns, pThisCC);
1203
1204	/* Update the diagnostic reason. */
1205	pThis->enmDiag = enmDiag;
1206
1207	/* We don't support advance fault logging. */
1208	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1209
1210	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1211	{
1212	/* Update the fault recording registers with the fault information. */
1213	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1214	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1215	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1216	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1217	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1218	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1219
1220	/* Set the Pending Primary Fault (PPF) field in the status register. */
1221	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1222
1223	/* Raise interrupt if necessary. */
1224	dmarFaultEventRaiseInterrupt(pDevIns);
1225	}
1226
1227	DMAR_UNLOCK(pDevIns, pThisCC);
1228	}
1229
1230
1231	/**
1232	* Records a qualified interrupt request fault.
1233	*
1234	* Qualified faults are those that can be suppressed by software using the FPD bit
1235	* in the IRTE.
1236	*
1237	* @param pDevIns The IOMMU device instance.
1238	* @param enmDiag The diagnostic reason.
1239	* @param enmIrFault The interrupt fault reason.
1240	* @param idDevice The device ID (bus, device, function).
1241	* @param idxIntr The interrupt index.
1242	* @param pIrte The IRTE that caused this fault.
1243	*/
1244	static void dmarIrFaultRecordQualified(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IR_FAULT_T enmIrFault, uint16_t idDevice,
1245	uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1246	{
1247	Assert(vtdIrFaultIsQualified(enmIrFault));
1248	Assert(pIrte);
1249	if (!(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK))
1250	return dmarIrFaultRecord(pDevIns, enmDiag, enmIrFault, idDevice, idxIntr);
1251	}
1252
1253
1254	/**
1255	* Records an IQE fault.
1256	*
1257	* @param pDevIns The IOMMU device instance.
1258	* @param enmIqei The IQE information.
1259	* @param enmDiag The diagnostic reason.
1260	*/
1261	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IQEI_T enmIqei)
1262	{
1263	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1264	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1265
1266	DMAR_LOCK(pDevIns, pThisCC);
1267
1268	/* Update the diagnostic reason. */
1269	pThis->enmDiag = enmDiag;
1270
1271	/* Set the error bit. */
1272	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1273	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1274
1275	/* Set the error information. */
1276	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1277	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1278
1279	dmarFaultEventRaiseInterrupt(pDevIns);
1280
1281	DMAR_UNLOCK(pDevIns, pThisCC);
1282	}
1283
1284
1285	/**
1286	* Handles writes to GCMD_REG.
1287	*
1288	* @returns Strict VBox status code.
1289	* @param pDevIns The IOMMU device instance.
1290	* @param uGcmdReg The value written to GCMD_REG.
1291	*/
1292	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1293	{
1294	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1295	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1296	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1297	uint64_t const fExtCapReg = pThis->fExtCapReg;
1298
1299	/* Queued-invalidation. */
1300	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1301	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1302	{
1303	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1304	{
1305	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1306	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1307	}
1308	else
1309	{
1310	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1311	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1312	}
1313	}
1314
1315	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1316	{
1317	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1318	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1319	{
1320	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1321	* supported. */
1322	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1323	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1324	}
1325
1326	/* Interrupt remapping. */
1327	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1328	{
1329	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1330	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1331	else
1332	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1333	}
1334
1335	/* Compatibility format interrupts. */
1336	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1337	{
1338	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1339	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1340	else
1341	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1342	}
1343	}
1344
1345	/* Set Root Table Pointer (SRTP). */
1346	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1347	{
1348	/** @todo Perform global invalidation of all remapping translation caches when
1349	* ESRTPS is supported. */
1350	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1351	}
1352
1353	/** @todo Rest of the bits. */
1354
1355	return VINF_SUCCESS;
1356	}
1357
1358
1359	/**
1360	* Handles writes to CCMD_REG.
1361	*
1362	* @returns Strict VBox status code.
1363	* @param pDevIns The IOMMU device instance.
1364	* @param offReg The MMIO register offset.
1365	* @param cbReg The size of the MMIO access (in bytes).
1366	* @param uCcmdReg The value written to CCMD_REG.
1367	*/
1368	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1369	{
1370	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1371	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1372	{
1373	/* Check if we need to invalidate the context-context. */
1374	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1375	if (fIcc)
1376	{
1377	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1378	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1379	if (uMajorVersion < 6)
1380	{
1381	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1382	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1383	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1384	{
1385	/* Verify table translation mode is legacy. */
1386	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1387	if (fTtm == VTD_TTM_LEGACY_MODE)
1388	{
1389	/** @todo Invalidate. */
1390	return VINF_SUCCESS;
1391	}
1392	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1393	}
1394	else
1395	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1396	}
1397	else
1398	pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1399	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1400	}
1401	}
1402	return VINF_SUCCESS;
1403	}
1404
1405
1406	/**
1407	* Handles writes to IQT_REG.
1408	*
1409	* @returns Strict VBox status code.
1410	* @param pDevIns The IOMMU device instance.
1411	* @param offReg The MMIO register offset.
1412	* @param uIqtReg The value written to IQT_REG.
1413	*/
1414	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1415	{
1416	/* We only care about the low 32-bits, high 32-bits are reserved. */
1417	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1418	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1419
1420	/* Paranoia. */
1421	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1422
1423	uint32_t const offQt = uIqtReg;
1424	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1425	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1426
1427	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1428	if ( fDw != VTD_IQA_REG_DW_256_BIT
1429	\|\| !(offQt & RT_BIT(4)))
1430	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1431	else
1432	{
1433	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1434	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1435	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, kIqei_QueueTailNotAligned);
1436	}
1437	return VINF_SUCCESS;
1438	}
1439
1440
1441	/**
1442	* Handles writes to IQA_REG.
1443	*
1444	* @returns Strict VBox status code.
1445	* @param pDevIns The IOMMU device instance.
1446	* @param offReg The MMIO register offset.
1447	* @param uIqaReg The value written to IQA_REG.
1448	*/
1449	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1450	{
1451	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1452	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1453
1454	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1455	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1456	* cannot happen or that it's ignored when it does happen. */
1457
1458	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1459	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1460	if (fDw == VTD_IQA_REG_DW_256_BIT)
1461	{
1462	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1463	if (fSupports256BitDw)
1464	{ /* likely */ }
1465	else
1466	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, kIqei_InvalidDescriptorWidth);
1467	}
1468	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1469
1470	return VINF_SUCCESS;
1471	}
1472
1473
1474	/**
1475	* Memory access bulk (one or more 4K pages) request from a device.
1476	*
1477	* @returns VBox status code.
1478	* @param pDevIns The IOMMU device instance.
1479	* @param idDevice The device ID (bus, device, function).
1480	* @param cIovas The number of addresses being accessed.
1481	* @param pauIovas The I/O virtual addresses for each page being accessed.
1482	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1483	* @param paGCPhysSpa Where to store the translated physical addresses.
1484	*
1485	* @thread Any.
1486	*/
1487	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1488	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1489	{
1490	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1491	return VERR_NOT_IMPLEMENTED;
1492	}
1493
1494
1495	/**
1496	* Memory access transaction from a device.
1497	*
1498	* @returns VBox status code.
1499	* @param pDevIns The IOMMU device instance.
1500	* @param idDevice The device ID (bus, device, function).
1501	* @param uIova The I/O virtual address being accessed.
1502	* @param cbIova The size of the access.
1503	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1504	* @param pGCPhysSpa Where to store the translated system physical address.
1505	* @param pcbContiguous Where to store the number of contiguous bytes translated
1506	* and permission-checked.
1507	*
1508	* @thread Any.
1509	*/
1510	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1511	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
1512	{
1513	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
1514	return VERR_NOT_IMPLEMENTED;
1515	}
1516
1517
1518	/**
1519	* Reads an IRTE from guest memory.
1520	*
1521	* @returns VBox status code.
1522	* @param pDevIns The IOMMU device instance.
1523	* @param uIrtaReg The IRTA_REG.
1524	* @param idxIntr The interrupt index.
1525	* @param pIrte Where to store the read IRTE.
1526	*/
1527	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
1528	{
1529	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
1530
1531	size_t const cbIrte = sizeof(*pIrte);
1532	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
1533	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
1534	}
1535
1536
1537	/**
1538	* Remaps the source MSI to the destination MSI given the IRTE.
1539	*
1540	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
1541	* IRTA_REG.EIME).
1542	* @param pIrte The IRTE used for the remapping.
1543	* @param pMsiIn The source MSI (currently unused).
1544	* @param pMsiOut Where to store the remapped MSI.
1545	*/
1546	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1547	{
1548	NOREF(pMsiIn);
1549	uint64_t const uIrteQword0 = pIrte->au64[0];
1550
1551	/*
1552	* Let's start with a clean slate and preserve unspecified bits if the need arises.
1553	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
1554	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
1555	* it copies it from the source MSI.
1556	*/
1557	RT_ZERO(*pMsiOut);
1558	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
1559	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
1560	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
1561	if (fExtIntrMode)
1562	{
1563	/*
1564	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
1565	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
1566	*/
1567	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
1568	pMsiOut->Addr.n.u8DestId = idDest;
1569	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
1570	}
1571	else
1572	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
1573
1574	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
1575	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
1576	pMsiOut->Data.n.u1Level = 1;
1577	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
1578	}
1579
1580
1581	/**
1582	* Handles remapping of interrupts in remappable interrupt format.
1583	*
1584	* @returns VBox status code.
1585	* @param pDevIns The IOMMU device instance.
1586	* @param uIrtaReg The IRTA_REG.
1587	* @param idDevice The device ID (bus, device, function).
1588	* @param pMsiIn The source MSI.
1589	* @param pMsiOut Where to store the remapped MSI.
1590	*/
1591	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1592	{
1593	Assert(VTD_MSI_ADDR_GET_INTR_FORMAT(pMsiIn->Addr.u64) == VTD_INTR_FORMAT_REMAPPABLE);
1594
1595	/* Validate reserved bits in the interrupt request. */
1596	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
1597	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
1598	{
1599	/* Compute the index into the interrupt remap table. */
1600	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
1601	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
1602	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
1603	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
1604	uint16_t const idxIntr = fSubHandleValid
1605	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
1606	: uHandle;
1607
1608	/* Validate the index. */
1609	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
1610	if (idxIntr < cEntries)
1611	{
1612	/** @todo Implement and read IRTE from interrupt-entry cache here. */
1613
1614	/* Read the interrupt remap table entry (IRTE) at the index. */
1615	VTD_IRTE_T Irte;
1616	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
1617	if (RT_SUCCESS(rc))
1618	{
1619	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
1620	uint64_t const uIrteQword0 = Irte.au64[0];
1621	uint64_t const uIrteQword1 = Irte.au64[1];
1622	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
1623	if (fPresent)
1624	{
1625	/* Validate reserved bits in the IRTE. */
1626	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
1627	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
1628	if ( !(uIrteQword0 & ~fQw0ValidMask)
1629	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
1630	{
1631	/* Validate requester id (the device ID) as configured in the IRTE. */
1632	bool fSrcValid;
1633	DMARDIAG enmIrDiag;
1634	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
1635	switch (fSvt)
1636	{
1637	case VTD_IRTE_SVT_NONE:
1638	{
1639	fSrcValid = true;
1640	enmIrDiag = kDmarDiag_None;
1641	break;
1642	}
1643
1644	case VTD_IRTE_SVT_VALIDATE_MASK:
1645	{
1646	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
1647	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
1648	uint16_t const fValidMask = s_afValidMasks[idxMask];
1649	fSrcValid = (idDevice & fValidMask) == idDevice;
1650	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
1651	break;
1652	}
1653
1654	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
1655	{
1656	uint16_t const uSourceId = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
1657	uint8_t const uBusFirst = RT_HI_U8(uSourceId);
1658	uint8_t const uBusLast = RT_LO_U8(uSourceId);
1659	uint8_t const uRequesterIdBus = idDevice >> VBOX_PCI_BUS_SHIFT;
1660	fSrcValid = (uRequesterIdBus >= uBusFirst && uRequesterIdBus <= uBusLast);
1661	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
1662	break;
1663	}
1664
1665	default:
1666	{
1667	fSrcValid = false;
1668	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
1669	break;
1670	}
1671	}
1672
1673	if (fSrcValid)
1674	{
1675	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
1676	if (!fPostedMode)
1677	{
1678	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
1679	return VINF_SUCCESS;
1680	}
1681	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, kIrf_Irte_Present_Rsvd,
1682	idDevice, idxIntr, &Irte);
1683	}
1684	else
1685	dmarIrFaultRecordQualified(pDevIns, enmIrDiag, kIrf_Irte_Present_Rsvd, idDevice, idxIntr, &Irte);
1686	}
1687	else
1688	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, kIrf_Irte_Present_Rsvd, idDevice,
1689	idxIntr, &Irte);
1690	}
1691	else
1692	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, kIrf_Irte_Not_Present, idDevice,
1693	idxIntr, &Irte);
1694	}
1695	else
1696	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, kIrf_Irte_Read_Failed, idDevice, idxIntr);
1697	}
1698	else
1699	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, kIrf_Intr_Index_Invalid, idDevice, idxIntr);
1700	}
1701	else
1702	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, kIrf_Remappable_Intr_Rsvd, idDevice, 0 /* idxIntr */);
1703	return VERR_IOMMU_INTR_REMAP_DENIED;
1704	}
1705
1706
1707	/**
1708	* Interrupt remap request from a device.
1709	*
1710	* @returns VBox status code.
1711	* @param pDevIns The IOMMU device instance.
1712	* @param idDevice The device ID (bus, device, function).
1713	* @param pMsiIn The source MSI.
1714	* @param pMsiOut Where to store the remapped MSI.
1715	*/
1716	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1717	{
1718	/* Validate. */
1719	Assert(pDevIns);
1720	Assert(pMsiIn);
1721	Assert(pMsiOut);
1722	RT_NOREF1(idDevice);
1723
1724	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1725	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1726
1727	/* Lock and read all registers required for interrupt remapping up-front. */
1728	DMAR_LOCK(pDevIns, pThisCC);
1729	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1730	uint64_t const uIrtaReg = pThis->uIrtaReg;
1731	DMAR_UNLOCK(pDevIns, pThisCC);
1732
1733	/* Check if interrupt remapping is enabled. */
1734	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
1735	{
1736	/* Handle compatibility format interrupts. */
1737	bool const fIsRemapFormat = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
1738	if (!fIsRemapFormat)
1739	{
1740	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
1741
1742	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
1743	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
1744	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
1745	{
1746	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, kIrf_Cfi_Blocked, idDevice, 0 /* idxIntr */);
1747	return VERR_IOMMU_INTR_REMAP_DENIED;
1748	}
1749
1750	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
1751	pMsiOut = pMsiIn;
1752	return VINF_SUCCESS;
1753	}
1754
1755	/* Handle remappable format interrupts. */
1756	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
1757	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
1758	}
1759
1760	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
1761	pMsiOut = pMsiIn;
1762	return VINF_SUCCESS;
1763	}
1764
1765
1766	/**
1767	* @callback_method_impl{FNIOMMMIONEWWRITE}
1768	*/
1769	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1770	{
1771	RT_NOREF1(pvUser);
1772	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1773
1774	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1775	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1776
1777	uint16_t const offReg = off;
1778	uint16_t const offLast = offReg + cb - 1;
1779	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1780	{
1781	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1782	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
1783
1784	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv)
1785	: dmarRegWrite32(pThis, offReg, (uint32_t )pv);
1786	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1787	switch (off)
1788	{
1789	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
1790	{
1791	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
1792	break;
1793	}
1794
1795	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
1796	case VTD_MMIO_OFF_CCMD_REG + 4:
1797	{
1798	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
1799	break;
1800	}
1801
1802	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
1803	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
1804	{
1805	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
1806	break;
1807	}
1808
1809	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
1810	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
1811	{
1812	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
1813	break;
1814	}
1815	}
1816
1817	DMAR_UNLOCK(pDevIns, pThisCC);
1818	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
1819	return rcStrict;
1820	}
1821
1822	return VINF_IOM_MMIO_UNUSED_FF;
1823	}
1824
1825
1826	/**
1827	* @callback_method_impl{FNIOMMMIONEWREAD}
1828	*/
1829	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1830	{
1831	RT_NOREF1(pvUser);
1832	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1833
1834	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1835	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1836
1837	uint16_t const offReg = off;
1838	uint16_t const offLast = offReg + cb - 1;
1839	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1840	{
1841	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1842	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
1843
1844	if (cb == 8)
1845	{
1846	(uint64_t )pv = dmarRegRead64(pThis, offReg);
1847	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
1848	}
1849	else
1850	{
1851	(uint32_t )pv = dmarRegRead32(pThis, offReg);
1852	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
1853	}
1854
1855	DMAR_UNLOCK(pDevIns, pThisCC);
1856	return VINF_SUCCESS;
1857	}
1858
1859	return VINF_IOM_MMIO_UNUSED_FF;
1860	}
1861
1862
1863	#ifdef IN_RING3
1864	/**
1865	* Process requests in the invalidation queue.
1866	*
1867	* @param pDevIns The IOMMU device instance.
1868	* @param pvRequests The requests to process.
1869	* @param cbRequests The size of all requests (in bytes).
1870	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
1871	* VTD_IQA_REG_DW_256_BIT).
1872	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
1873	*/
1874	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
1875	uint8_t fTtm)
1876	{
1877	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
1878	do \
1879	{ \
1880	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
1881	return; \
1882	} while (0)
1883
1884	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1885	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1886
1887	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
1888	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
1889
1890	/*
1891	* The below check is redundant since we check both TTM and DW for each
1892	* descriptor type we process. However, the error reported by hardware
1893	* may differ hence this is kept commented out but not removed from the code
1894	* if we need to change this in the future.
1895	*
1896	* In our implementation, we would report the descriptor type as invalid,
1897	* while on real hardware it may report descriptor width as invalid.
1898	* The Intel VT-d spec. is not clear which error takes preceedence.
1899	*/
1900	#if 0
1901	/*
1902	* Verify that 128-bit descriptors are not used when operating in scalable mode.
1903	* We don't check this while software writes IQA_REG but defer it until now because
1904	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
1905	* -IS- performed when software writes IQA_REG since it only requires checking against
1906	* immutable hardware features.
1907	*/
1908	if ( fTtm != VTD_TTM_SCALABLE_MODE
1909	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
1910	{ /* likely */ }
1911	else
1912	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, kIqei_InvalidDescriptorWidth);
1913	#endif
1914
1915	/*
1916	* Process requests in FIFO order.
1917	*/
1918	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
1919	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
1920	{
1921	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
1922	uint64_t const uQword0 = puDscQwords[0];
1923	uint64_t const uQword1 = puDscQwords[1];
1924	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
1925	switch (fDscType)
1926	{
1927	case VTD_INV_WAIT_DSC_TYPE:
1928	{
1929	/* Validate descriptor type. */
1930	if ( fTtm == VTD_TTM_LEGACY_MODE
1931	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
1932	{ /* likely */ }
1933	else
1934	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, kIqei_InvalidDescriptorType);
1935
1936	/* Validate reserved bits. */
1937	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
1938	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
1939	: VTD_INV_WAIT_DSC_0_VALID_MASK;
1940	if ( !(uQword0 & ~fValidMask0)
1941	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
1942	{ /* likely */ }
1943	else
1944	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, kIqei_RsvdFieldViolation);
1945
1946	if (fDw == VTD_IQA_REG_DW_256_BIT)
1947	{
1948	if ( !puDscQwords[2]
1949	&& !puDscQwords[3])
1950	{ /* likely */ }
1951	else
1952	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, kIqei_RsvdFieldViolation);
1953	}
1954
1955	/* Perform status write (this must be done prior to generating the completion interrupt). */
1956	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
1957	if (fSw)
1958	{
1959	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
1960	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
1961	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
1962	AssertRC(rc);
1963	}
1964
1965	/* Generate invalidation event interrupt. */
1966	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
1967	if (fIf)
1968	{
1969	DMAR_LOCK(pDevIns, pThisR3);
1970	dmarR3InvEventRaiseInterrupt(pDevIns);
1971	DMAR_UNLOCK(pDevIns, pThisR3);
1972	}
1973
1974	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
1975	break;
1976	}
1977
1978	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
1979	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
1980	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
1981	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
1982	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
1983	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
1984	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
1985	default:
1986	{
1987	/* Stop processing further requests. */
1988	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
1989	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, kIqei_InvalidDescriptorType);
1990	}
1991	}
1992	}
1993	#undef DMAR_IQE_FAULT_RECORD_RET
1994	}
1995
1996
1997	/**
1998	* The invalidation-queue thread.
1999	*
2000	* @returns VBox status code.
2001	* @param pDevIns The IOMMU device instance.
2002	* @param pThread The command thread.
2003	*/
2004	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2005	{
2006	NOREF(pThread);
2007	LogFlowFunc(("\n"));
2008
2009	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2010	return VINF_SUCCESS;
2011
2012	/*
2013	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
2014	* This prevents trashing the heap as well as deal with out-of-memory situations
2015	* up-front while starting the VM. It also simplifies the code from having to
2016	* dynamically grow/shrink the allocation based on how software sizes the queue.
2017	* Guests normally don't alter the queue size all the time, but that's not an
2018	* assumption we can make.
2019	*/
2020	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
2021	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
2022	void *pvRequests = RTMemAllocZ(cbMaxQs);
2023	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
2024
2025	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2026	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2027
2028	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2029	{
2030	/*
2031	* Sleep until we are woken up.
2032	*/
2033	bool const fSignaled = ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, false);
2034	if (!fSignaled)
2035	{
2036	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
2037	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2038	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2039	break;
2040	ASMAtomicWriteBool(&pThis->fInvQueueThreadSignaled, false);
2041	}
2042
2043	DMAR_LOCK(pDevIns, pThisR3);
2044	if (dmarInvQueueCanProcessRequests(pThis))
2045	{
2046	uint32_t offQueueHead;
2047	uint32_t offQueueTail;
2048	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
2049	if (!fIsEmpty)
2050	{
2051	/*
2052	* Get the current queue size, descriptor width, queue base address and the
2053	* table translation mode while the lock is still held.
2054	*/
2055	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2056	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
2057	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
2058	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2059	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2060	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
2061
2062	/* Paranoia. */
2063	Assert(cbQueue <= cbMaxQs);
2064	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
2065	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
2066	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
2067	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
2068	Assert(offQueueHead < cbQueue);
2069
2070	/*
2071	* A table translation mode of "reserved" isn't valid for any descriptor type.
2072	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
2073	* but if ESRTPS is support, we will perform a global invalidation when software
2074	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
2075	* So caching TTM while reading all descriptors should not be a problem.
2076	*
2077	* Also, validate the queue tail offset as it's mutable by software.
2078	*/
2079	if ( fTtm != VTD_TTM_RSVD
2080	&& offQueueTail < cbQueue)
2081	{
2082	/* Don't hold the lock while reading (a potentially large amount of) requests */
2083	DMAR_UNLOCK(pDevIns, pThisR3);
2084
2085	int rc;
2086	uint32_t cbRequests;
2087	if (offQueueTail > offQueueHead)
2088	{
2089	/* The requests have not wrapped around, read them in one go. */
2090	cbRequests = offQueueTail - offQueueHead;
2091	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
2092	}
2093	else
2094	{
2095	/* The requests have wrapped around, read forward and wrapped-around. */
2096	uint32_t const cbForward = cbQueue - offQueueHead;
2097	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
2098
2099	uint32_t const cbWrapped = offQueueTail;
2100	if ( RT_SUCCESS(rc)
2101	&& cbWrapped > 0)
2102	{
2103	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
2104	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
2105	}
2106	cbRequests = cbForward + cbWrapped;
2107	}
2108
2109	/* Re-acquire the lock since we need to update device state. */
2110	DMAR_LOCK(pDevIns, pThisR3);
2111
2112	if (RT_SUCCESS(rc))
2113	{
2114	/* Indicate to software we've fetched all requests. */
2115	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
2116
2117	/* Don't hold the lock while processing requests. */
2118	DMAR_UNLOCK(pDevIns, pThisR3);
2119
2120	/* Process all requests. */
2121	Assert(cbRequests <= cbQueue);
2122	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
2123
2124	/*
2125	* We've processed all requests and the lock shouldn't be held at this point.
2126	* Using 'continue' here allows us to skip re-acquiring the lock just to release
2127	* it again before going back to the thread loop. It's a bit ugly but it certainly
2128	* helps with performance.
2129	*/
2130	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2131	continue;
2132	}
2133	else
2134	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, kIqei_FetchDescriptorError);
2135	}
2136	else
2137	{
2138	if (fTtm == VTD_TTM_RSVD)
2139	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, kIqei_InvalidTtm);
2140	else
2141	{
2142	Assert(offQueueTail >= cbQueue);
2143	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, kIqei_InvalidTailPointer);
2144	}
2145	}
2146	}
2147	}
2148	DMAR_UNLOCK(pDevIns, pThisR3);
2149	}
2150
2151	RTMemFree(pvRequests);
2152	pvRequests = NULL;
2153
2154	LogFlowFunc(("Invalidation-queue thread terminating\n"));
2155	return VINF_SUCCESS;
2156	}
2157
2158
2159	/**
2160	* Wakes up the invalidation-queue thread so it can respond to a state
2161	* change.
2162	*
2163	* @returns VBox status code.
2164	* @param pDevIns The IOMMU device instance.
2165	* @param pThread The invalidation-queue thread.
2166	*
2167	* @thread EMT.
2168	*/
2169	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2170	{
2171	RT_NOREF(pThread);
2172	LogFlowFunc(("\n"));
2173	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2174	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
2175	}
2176
2177
2178	/**
2179	* @callback_method_impl{FNDBGFHANDLERDEV}
2180	*/
2181	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2182	{
2183	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2184	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2185	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
2186
2187	/*
2188	* We lock the device to get a consistent register state as it is
2189	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
2190	* ones we care about here) into temporaries and release the lock ASAP.
2191	*
2192	* Order of register being read and outputted is in accordance with the
2193	* spec. for no particular reason.
2194	* See Intel VT-d spec. 10.4 "Register Descriptions".
2195	*/
2196	DMAR_LOCK(pDevIns, pThisR3);
2197
2198	DMARDIAG const enmDiag = pThis->enmDiag;
2199	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
2200	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
2201	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
2202	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
2203	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2204	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
2205	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
2206	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
2207	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
2208	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
2209	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
2210	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
2211	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
2212	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
2213	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
2214	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
2215	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
2216	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
2217	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
2218	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
2219	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2220	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
2221	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
2222	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
2223	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
2224	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
2225	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
2226	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
2227	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
2228	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
2229	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
2230	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
2231	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
2232	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
2233	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
2234	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
2235	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
2236	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
2237
2238	DMAR_UNLOCK(pDevIns, pThisR3);
2239
2240	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
2241	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
2242	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
2243
2244	/*
2245	* Non-verbose output.
2246	*/
2247	if (!fVerbose)
2248	{
2249	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2250	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2251	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2252	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2253	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2254	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2255	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2256	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2257	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2258	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2259	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2260	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2261	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2262	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2263	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2264	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2265	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2266	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2267	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2268	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2269	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2270	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2271	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2272	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2273	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2274	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2275	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2276	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2277	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2278	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2279	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2280	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2281	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2282	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2283	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2284	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2285	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2286	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2287	pHlp->pfnPrintf(pHlp, "\n");
2288	return;
2289	}
2290
2291	/*
2292	* Verbose output.
2293	*/
2294	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2295	{
2296	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
2297	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
2298	}
2299	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2300	{
2301	uint8_t const uSagaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW);
2302	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
2303	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
2304	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
2305	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
2306	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
2307	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
2308	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
2309	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
2310	pHlp->pfnPrintf(pHlp, " SAGAW = %#x (%u bits)\n", uSagaw, vtdCapRegGetSagawBits(uSagaw));
2311	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
2312	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
2313	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
2314	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
2315	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
2316	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
2317	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
2318	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
2319	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
2320	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
2321	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
2322	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
2323	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
2324	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
2325	}
2326	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2327	{
2328	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
2329	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
2330	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
2331	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
2332	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
2333	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
2334	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
2335	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
2336	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
2337	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
2338	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
2339	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
2340	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
2341	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
2342	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
2343	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
2344	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
2345	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
2346	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
2347	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
2348	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
2349	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
2350	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
2351	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
2352	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
2353	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
2354	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
2355	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
2356	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
2357	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
2358	}
2359	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2360	{
2361	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
2362	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Bypass" : "Block");
2363	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
2364	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
2365	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
2366	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
2367	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2368	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2369	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
2370	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
2371	}
2372	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2373	{
2374	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
2375	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Bypass" : "Block");
2376	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
2377	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
2378	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
2379	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
2380	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
2381	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
2382	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
2383	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
2384	}
2385	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2386	{
2387	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2388	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
2389	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_RTA));
2390	}
2391	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2392	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2393	{
2394	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
2395	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
2396	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
2397	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
2398	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
2399	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
2400	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
2401	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
2402	}
2403	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2404	{
2405	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
2406	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
2407	}
2408	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2409	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2410	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2411	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2412	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2413	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2414	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2415	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2416	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2417	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2418	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2419	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2420	{
2421	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2422	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
2423	uint8_t const cQueuePages = 1 << fQs;
2424	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
2425	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
2426	}
2427	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2428	{
2429	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
2430	}
2431	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2432	{
2433	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
2434	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
2435	}
2436	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2437	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2438	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2439	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2440	{
2441	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
2442	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
2443	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
2444	}
2445	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2446	{
2447	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2448	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
2449	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_IRTA));
2450	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
2451	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
2452	}
2453	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2454	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2455	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2456	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2457	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2458	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2459	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2460	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2461	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2462	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2463	pHlp->pfnPrintf(pHlp, "\n");
2464	}
2465
2466
2467	/**
2468	* Initializes all registers in the DMAR unit.
2469	*
2470	* @param pDevIns The IOMMU device instance.
2471	*/
2472	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
2473	{
2474	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2475
2476	/*
2477	* Wipe all registers (required on reset).
2478	*/
2479	RT_ZERO(pThis->abRegs0);
2480	RT_ZERO(pThis->abRegs1);
2481
2482	/*
2483	* Initialize registers not mutable by software prior to initializing other registers.
2484	*/
2485	/* VER_REG */
2486	{
2487	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
2488	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
2489	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
2490	}
2491
2492	uint8_t const fFlts = 1; /* First-Level translation support. */
2493	uint8_t const fSlts = 1; /* Second-Level translation support. */
2494	uint8_t const fPt = 1; /* Pass-Through support. */
2495	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
2496	uint8_t const fNest = 0; /* Nested translation support. */
2497
2498	/* CAP_REG */
2499	{
2500	uint8_t cGstPhysAddrBits;
2501	uint8_t cGstLinearAddrBits;
2502	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
2503
2504	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
2505	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
2506	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
2507	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
2508	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
2509	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
2510	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
2511	: X86_PAGE_2M_SHIFT)
2512	- X86_PAGE_4K_SHIFT;
2513	uint8_t const fNd = 2; /* Number of domains supported (0=16, 1=64, 2=256, 3=1K, 4=4K,
2514	5=16K, 6=64K, 7=Reserved). */
2515	uint8_t const fPsi = 1; /* Page selective invalidation. */
2516	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
2517	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
2518	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
2519	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
2520	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
2521
2522	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
2523	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
2524	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
2525	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
2526	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
2527	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
2528	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
2529	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
2530	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
2531	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
2532	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
2533	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
2534	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
2535	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
2536	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
2537	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
2538	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
2539	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
2540	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
2541	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
2542	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
2543	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
2544	}
2545
2546	/* ECAP_REG */
2547	{
2548	uint8_t const fQi = 1; /* Queued-invalidations. */
2549	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
2550	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
2551	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
2552	uint8_t const fSrs = 1; /* Supervisor request support. */
2553	uint8_t const fEim = 1; /* Extended interrupt mode.*/
2554	uint8_t const fAdms = 1; /* Abort DMA mode support. */
2555
2556	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
2557	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
2558	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
2559	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
2560	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
2561	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
2562	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
2563	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
2564	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
2565	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
2566	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
2567	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
2568	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
2569	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
2570	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
2571	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
2572	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
2573	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
2574	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
2575	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
2576	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
2577	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
2578	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
2579	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
2580	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
2581	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
2582	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
2583	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
2584	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
2585	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
2586	}
2587
2588	/*
2589	* Initialize registers mutable by software.
2590	*/
2591	/* FECTL_REG */
2592	{
2593	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
2594	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
2595	}
2596
2597	/* ICETL_REG */
2598	{
2599	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
2600	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
2601	}
2602
2603	#ifdef VBOX_STRICT
2604	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
2605	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
2606	#endif
2607	}
2608
2609
2610	/**
2611	* @interface_method_impl{PDMDEVREG,pfnReset}
2612	*/
2613	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
2614	{
2615	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2616	LogFlowFunc(("\n"));
2617
2618	DMAR_LOCK(pDevIns, pThisR3);
2619	dmarR3RegsInit(pDevIns);
2620	DMAR_UNLOCK(pDevIns, pThisR3);
2621	}
2622
2623
2624	/**
2625	* @interface_method_impl{PDMDEVREG,pfnDestruct}
2626	*/
2627	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
2628	{
2629	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2630	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2631	LogFlowFunc(("\n"));
2632
2633	DMAR_LOCK(pDevIns, pThisR3);
2634
2635	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
2636	{
2637	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
2638	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
2639	}
2640
2641	DMAR_UNLOCK(pDevIns, pThisR3);
2642	return VINF_SUCCESS;
2643	}
2644
2645
2646	/**
2647	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2648	*/
2649	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2650	{
2651	RT_NOREF(pCfg);
2652
2653	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2654	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
2655	pThisR3->pDevInsR3 = pDevIns;
2656
2657	LogFlowFunc(("iInstance=%d\n", iInstance));
2658	NOREF(iInstance);
2659
2660	/*
2661	* Register the IOMMU with PDM.
2662	*/
2663	PDMIOMMUREGR3 IommuReg;
2664	RT_ZERO(IommuReg);
2665	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2666	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2667	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2668	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2669	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2670	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
2671	if (RT_FAILURE(rc))
2672	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
2673	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
2674	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2675	N_("IOMMU helper version mismatch; got %#x expected %#x"),
2676	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
2677	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
2678	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2679	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
2680	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
2681	/*
2682	* Use PDM's critical section (via helpers) for the IOMMU device.
2683	*/
2684	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2685	AssertRCReturn(rc, rc);
2686
2687	/*
2688	* Initialize PCI configuration registers.
2689	*/
2690	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2691	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2692
2693	/* Header. */
2694	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2695	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2696	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
2697	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
2698	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
2699	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
2700	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2701	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2702
2703	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
2704	PDMPciDevSetStatus(pPciDev, 0);
2705	PDMPciDevSetCapabilityList(pPciDev, 0);
2706
2707	/** @todo VTBAR at 0x180? */
2708
2709	/*
2710	* Register the PCI function with PDM.
2711	*/
2712	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
2713	AssertLogRelRCReturn(rc, rc);
2714
2715	/** @todo Register MSI but what's the MSI capability offset? */
2716	#if 0
2717	/*
2718	* Register MSI support for the PCI device.
2719	* This must be done -after- registering it as a PCI device!
2720	*/
2721	#endif
2722
2723	/*
2724	* Register MMIO region.
2725	*/
2726	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
2727	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
2728	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
2729	&pThis->hMmio);
2730	AssertLogRelRCReturn(rc, rc);
2731
2732	/*
2733	* Register debugger info items.
2734	*/
2735	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
2736	AssertLogRelRCReturn(rc, rc);
2737
2738	#ifdef VBOX_WITH_STATISTICS
2739	/*
2740	* Statistics.
2741	*/
2742	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
2743	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
2744
2745	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
2746	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
2747
2748	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
2749	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
2750	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
2751	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
2752
2753	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
2754	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
2755
2756	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
2757	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
2758
2759	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
2760	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
2761
2762	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
2763	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
2764
2765	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
2766	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
2767	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
2768	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
2769	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
2770	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
2771	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
2772	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
2773	#endif
2774
2775	/*
2776	* Initialize registers.
2777	*/
2778	dmarR3RegsInit(pDevIns);
2779
2780	/*
2781	* Create invalidation-queue thread and semaphore.
2782	*/
2783	char szInvQueueThread[32];
2784	RT_ZERO(szInvQueueThread);
2785	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
2786	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
2787	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
2788	AssertLogRelRCReturn(rc, rc);
2789
2790	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
2791	AssertLogRelRCReturn(rc, rc);
2792
2793	/*
2794	* Log some of the features exposed to software.
2795	*/
2796	uint32_t const uVerReg = pThis->uVerReg;
2797	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
2798	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW));
2799	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
2800	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
2801	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
2802	DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
2803	pThis->fCapReg, pThis->fExtCapReg, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
2804
2805	return VINF_SUCCESS;
2806	}
2807
2808	#else
2809
2810	/**
2811	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
2812	*/
2813	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
2814	{
2815	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2816	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2817	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
2818	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
2819
2820	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
2821	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2822	AssertRCReturn(rc, rc);
2823
2824	/* Set up the MMIO RZ handlers. */
2825	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
2826	AssertRCReturn(rc, rc);
2827
2828	/* Set up the IOMMU RZ callbacks. */
2829	PDMIOMMUREGCC IommuReg;
2830	RT_ZERO(IommuReg);
2831	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2832	IommuReg.idxIommu = pThis->idxIommu;
2833	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2834	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2835	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2836	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2837
2838	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
2839	AssertRCReturn(rc, rc);
2840	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
2841	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2842	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2843	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
2844	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
2845	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
2846	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
2847
2848	return VINF_SUCCESS;
2849	}
2850
2851	#endif
2852
2853
2854	/**
2855	* The device registration structure.
2856	*/
2857	PDMDEVREG const g_DeviceIommuIntel =
2858	{
2859	/* .u32Version = */ PDM_DEVREG_VERSION,
2860	/* .uReserved0 = */ 0,
2861	/* .szName = */ "iommu-intel",
2862	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
2863	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
2864	/* .cMaxInstances = */ 1,
2865	/* .uSharedVersion = */ 42,
2866	/* .cbInstanceShared = */ sizeof(DMAR),
2867	/* .cbInstanceCC = */ sizeof(DMARCC),
2868	/* .cbInstanceRC = */ sizeof(DMARRC),
2869	/* .cMaxPciDevices = */ 1,
2870	/* .cMaxMsixVectors = */ 0,
2871	/* .pszDescription = */ "IOMMU (Intel)",
2872	#if defined(IN_RING3)
2873	/* .pszRCMod = */ "VBoxDDRC.rc",
2874	/* .pszR0Mod = */ "VBoxDDR0.r0",
2875	/* .pfnConstruct = */ iommuIntelR3Construct,
2876	/* .pfnDestruct = */ iommuIntelR3Destruct,
2877	/* .pfnRelocate = */ NULL,
2878	/* .pfnMemSetup = */ NULL,
2879	/* .pfnPowerOn = */ NULL,
2880	/* .pfnReset = */ iommuIntelR3Reset,
2881	/* .pfnSuspend = */ NULL,
2882	/* .pfnResume = */ NULL,
2883	/* .pfnAttach = */ NULL,
2884	/* .pfnDetach = */ NULL,
2885	/* .pfnQueryInterface = */ NULL,
2886	/* .pfnInitComplete = */ NULL,
2887	/* .pfnPowerOff = */ NULL,
2888	/* .pfnSoftReset = */ NULL,
2889	/* .pfnReserved0 = */ NULL,
2890	/* .pfnReserved1 = */ NULL,
2891	/* .pfnReserved2 = */ NULL,
2892	/* .pfnReserved3 = */ NULL,
2893	/* .pfnReserved4 = */ NULL,
2894	/* .pfnReserved5 = */ NULL,
2895	/* .pfnReserved6 = */ NULL,
2896	/* .pfnReserved7 = */ NULL,
2897	#elif defined(IN_RING0)
2898	/* .pfnEarlyConstruct = */ NULL,
2899	/* .pfnConstruct = */ iommuIntelRZConstruct,
2900	/* .pfnDestruct = */ NULL,
2901	/* .pfnFinalDestruct = */ NULL,
2902	/* .pfnRequest = */ NULL,
2903	/* .pfnReserved0 = */ NULL,
2904	/* .pfnReserved1 = */ NULL,
2905	/* .pfnReserved2 = */ NULL,
2906	/* .pfnReserved3 = */ NULL,
2907	/* .pfnReserved4 = */ NULL,
2908	/* .pfnReserved5 = */ NULL,
2909	/* .pfnReserved6 = */ NULL,
2910	/* .pfnReserved7 = */ NULL,
2911	#elif defined(IN_RC)
2912	/* .pfnConstruct = */ iommuIntelRZConstruct,
2913	/* .pfnReserved0 = */ NULL,
2914	/* .pfnReserved1 = */ NULL,
2915	/* .pfnReserved2 = */ NULL,
2916	/* .pfnReserved3 = */ NULL,
2917	/* .pfnReserved4 = */ NULL,
2918	/* .pfnReserved5 = */ NULL,
2919	/* .pfnReserved6 = */ NULL,
2920	/* .pfnReserved7 = */ NULL,
2921	#else
2922	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
2923	#endif
2924	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
2925	};
2926
2927	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2928

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88968

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