DevIommuIntel.cpp@ 89637

Last change on this file since 89637 was 89591, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Don't mask out the destination page offset bits in passthrough mode (caller no longer does it).
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1	/* $Id: DevIommuIntel.cpp 89591 2021-06-10 08:45:07Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <VBox/iommu-intel.h>
27	#include <iprt/mem.h>
28	#include <iprt/string.h>
29
30
31	/*********************************************************************************************************************************
32	* Defined Constants And Macros *
33	*********************************************************************************************************************************/
34	/** Gets the low uint32_t of a uint64_t or something equivalent.
35	*
36	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
37	* used as it asserts for correctness when compiling on certain compilers). */
38	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
39
40	/** Gets the high uint32_t of a uint64_t or something equivalent.
41	*
42	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
43	* used as it asserts for correctness when compiling on certain compilers). */
44	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
45
46	/** Asserts MMIO access' offset and size are valid or returns appropriate error
47	* code suitable for returning from MMIO access handlers. */
48	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
49	do { \
50	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
51	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
52	} while (0)
53
54	/** Checks if the MMIO offset is valid. */
55	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
56	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
57
58	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
59	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
60	do { \
61	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
62	{ /* likely */ } \
63	else \
64	return (a_rcBusy); \
65	} while (0)
66
67	/** Acquires the DMAR lock (not expected to fail). */
68	#ifdef IN_RING3
69	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
70	#else
71	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
72	do { \
73	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
74	AssertRC(rcLock); \
75	} while (0)
76	#endif
77
78	/** Release the DMAR lock. */
79	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
80
81	/** Asserts that the calling thread owns the DMAR lock. */
82	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
83	do { \
84	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
85	RT_NOREF1(a_pThisCC); \
86	} while (0)
87
88	/** Asserts that the calling thread does not own the DMAR lock. */
89	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
90	do { \
91	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
92	RT_NOREF1(a_pThisCC); \
93	} while (0)
94
95	/** The number of fault recording registers our implementation supports.
96	* Normal guest operation shouldn't trigger faults anyway, so we only support the
97	* minimum number of registers (which is 1).
98	*
99	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
100	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
101
102	/** Number of register groups (used in saved states). */
103	#define DMAR_MMIO_GROUP_COUNT 2
104	/** Offset of first register in group 0. */
105	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
106	/** Offset of last register in group 0 (inclusive). */
107	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
108	/** Last valid offset in group 0 (exclusive). */
109	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
110	/** Size of the group 0 (in bytes). */
111	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
112	/*< Implementation-specific MMIO offset of IVA_REG. /
113	#define DMAR_MMIO_OFF_IVA_REG 0xe50
114	/*< Implementation-specific MMIO offset of IOTLB_REG. /
115	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
116	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
117	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
118	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
119	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
120	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
121
122	/** Offset of first register in group 1. */
123	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
124	/** Offset of last register in group 1 (inclusive). */
125	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
126	/** Last valid offset in group 1 (exclusive). */
127	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
128	/** Size of the group 1 (in bytes). */
129	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
130
131	/** DMAR implementation's major version number (exposed to software).
132	* We report 6 as the major version since we support queued-invalidations as
133	* software may make assumptions based on that.
134	*
135	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
136	#define DMAR_VER_MAJOR 6
137	/** DMAR implementation's minor version number (exposed to software). */
138	#define DMAR_VER_MINOR 0
139
140	/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
141	* 7=Reserved). */
142	#define DMAR_ND 6
143
144	/** @name DMAR_PERM_XXX: DMA request permissions.
145	* The order of R, W, X bits is important as it corresponds to those bits in
146	* page-table entries.
147	*
148	* @{ */
149	/** DMA request permission: Read. */
150	#define DMAR_PERM_READ RT_BIT(0)
151	/** DMA request permission: Write. */
152	#define DMAR_PERM_WRITE RT_BIT(1)
153	/** DMA request permission: Execute (ER). */
154	#define DMAR_PERM_EXE RT_BIT(2)
155	/** DMA request permission: Supervisor privilege (PR). */
156	#define DMAR_PERM_PRIV RT_BIT(3)
157	/** DMA request permissions: All. */
158	#define DMAR_PERM_ALL (DMAR_PERM_READ \| DMAR_PERM_WRITE \| DMAR_PERM_EXE \| DMAR_PERM_PRIV)
159	/** @} */
160
161	/** Release log prefix string. */
162	#define DMAR_LOG_PFX "Intel-IOMMU"
163	/** The current saved state version. */
164	#define DMAR_SAVED_STATE_VERSION 1
165
166
167	/*********************************************************************************************************************************
168	* Structures and Typedefs *
169	*********************************************************************************************************************************/
170	/**
171	* DMAR error diagnostics.
172	* Sorted alphabetically so it's easier to add and locate items, no other reason.
173	*
174	* @note Members of this enum are used as array indices, so no gaps in enum
175	* values are not allowed. Update g_apszDmarDiagDesc when you modify
176	* fields in this enum.
177	*/
178	typedef enum
179	{
180	/* No error, this must be zero! */
181	kDmarDiag_None = 0,
182
183	/* Address Translation Faults. */
184	kDmarDiag_At_Lm_CtxEntry_Not_Present,
185	kDmarDiag_At_Lm_CtxEntry_Read_Failed,
186	kDmarDiag_At_Lm_CtxEntry_Rsvd,
187	kDmarDiag_At_Lm_Pt_At_Block,
188	kDmarDiag_At_Lm_Pt_Aw_Invalid,
189	kDmarDiag_At_Lm_RootEntry_Not_Present,
190	kDmarDiag_At_Lm_RootEntry_Read_Failed,
191	kDmarDiag_At_Lm_RootEntry_Rsvd,
192	kDmarDiag_At_Lm_Tt_Invalid,
193	kDmarDiag_At_Lm_Ut_At_Block,
194	kDmarDiag_At_Lm_Ut_Aw_Invalid,
195	kDmarDiag_At_Rta_Adms_Not_Supported,
196	kDmarDiag_At_Rta_Rsvd,
197	kDmarDiag_At_Rta_Smts_Not_Supported,
198	kDmarDiag_At_Xm_AddrIn_Invalid,
199	kDmarDiag_At_Xm_AddrOut_Invalid,
200	kDmarDiag_At_Xm_Perm_Denied,
201	kDmarDiag_At_Xm_Pte_Rsvd,
202	kDmarDiag_At_Xm_Pte_Sllps_Invalid,
203	kDmarDiag_At_Xm_Read_Pte_Failed,
204	kDmarDiag_At_Xm_Slpptr_Read_Failed,
205
206	/* CCMD_REG faults. */
207	kDmarDiag_CcmdReg_Not_Supported,
208	kDmarDiag_CcmdReg_Qi_Enabled,
209	kDmarDiag_CcmdReg_Ttm_Invalid,
210
211	/* IQA_REG faults. */
212	kDmarDiag_IqaReg_Dsc_Fetch_Error,
213	kDmarDiag_IqaReg_Dw_128_Invalid,
214	kDmarDiag_IqaReg_Dw_256_Invalid,
215
216	/* Invalidation Queue Error Info. */
217	kDmarDiag_Iqei_Dsc_Type_Invalid,
218	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
219	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
220	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
221	kDmarDiag_Iqei_Ttm_Rsvd,
222
223	/* IQT_REG faults. */
224	kDmarDiag_IqtReg_Qt_Invalid,
225	kDmarDiag_IqtReg_Qt_Not_Aligned,
226
227	/* Interrupt Remapping Faults. */
228	kDmarDiag_Ir_Cfi_Blocked,
229	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
230	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
231	kDmarDiag_Ir_Rfi_Irte_Not_Present,
232	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
233	kDmarDiag_Ir_Rfi_Irte_Rsvd,
234	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
235	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
236	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
237	kDmarDiag_Ir_Rfi_Rsvd,
238
239	/* Member for determining array index limit. */
240	kDmarDiag_End,
241
242	/* Usual 32-bit type size hack. */
243	kDmarDiag_32Bit_Hack = 0x7fffffff
244	} DMARDIAG;
245	AssertCompileSize(DMARDIAG, 4);
246
247	/** DMAR diagnostic enum description expansion.
248	* The below construct ensures typos in the input to this macro are caught
249	* during compile time. */
250	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
251
252	/** DMAR diagnostics description for members in DMARDIAG. */
253	static const char *const g_apszDmarDiagDesc[] =
254	{
255	DMARDIAG_DESC(None ),
256
257	/* Address Translation Faults. */
258	DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
259	DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
260	DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
261	DMARDIAG_DESC(At_Lm_Pt_At_Block ),
262	DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
263	DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
264	DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
265	DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
266	DMARDIAG_DESC(At_Lm_Tt_Invalid ),
267	DMARDIAG_DESC(At_Lm_Ut_At_Block ),
268	DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
269	DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
270	DMARDIAG_DESC(At_Rta_Rsvd ),
271	DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
272	DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
273	DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
274	DMARDIAG_DESC(At_Xm_Perm_Denied ),
275	DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
276	DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
277	DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
278	DMARDIAG_DESC(At_Xm_Slpptr_Read_Failed ),
279
280	/* CCMD_REG faults. */
281	DMARDIAG_DESC(CcmdReg_Not_Supported ),
282	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
283	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
284
285	/* IQA_REG faults. */
286	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
287	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
288	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
289
290	/* Invalidation Queue Error Info. */
291	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
292	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
293	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
294	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
295	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
296
297	/* IQT_REG faults. */
298	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
299	DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
300
301	/* Interrupt remapping faults. */
302	DMARDIAG_DESC(Ir_Cfi_Blocked ),
303	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
304	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
305	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
306	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
307	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
308	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
309	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
310	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
311	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
312	/* kDmarDiag_End */
313	};
314	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
315	#undef DMARDIAG_DESC
316
317	/**
318	* The shared DMAR device state.
319	*/
320	typedef struct DMAR
321	{
322	/** IOMMU device index. */
323	uint32_t idxIommu;
324	/** Padding. */
325	uint32_t u32Padding0;
326
327	/** Registers (group 0). */
328	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
329	/** Registers (group 1). */
330	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
331
332	/** @name Lazily activated registers.
333	* These are the active values for lazily activated registers. Software is free to
334	* modify the actual register values while remapping/translation is enabled but they
335	* take effect only when explicitly signaled by software, hence we need to hold the
336	* active values separately.
337	* @{ */
338	/** Currently active IRTA_REG. */
339	uint64_t uIrtaReg;
340	/** Currently active RTADDR_REG. */
341	uint64_t uRtaddrReg;
342	/** @} */
343
344	/** @name Register copies for a tiny bit faster and more convenient access.
345	* @{ */
346	/** Copy of VER_REG. */
347	uint8_t uVerReg;
348	/** Alignment. */
349	uint8_t abPadding0[7];
350	/** Copy of CAP_REG. */
351	uint64_t fCapReg;
352	/** Copy of ECAP_REG. */
353	uint64_t fExtCapReg;
354	/** @} */
355
356	/** Host-address width (HAW) base address mask. */
357	uint64_t fHawBaseMask;
358	/** Maximum guest-address width (MGAW) invalid address mask. */
359	uint64_t fMgawInvMask;
360	/** Maximum supported paging level (3, 4 or 5). */
361	uint8_t cMaxPagingLevel;
362	/** DMA request valid permissions mask. */
363	uint8_t fPermValidMask;
364	/** Alignment. */
365	uint8_t abPadding1[6];
366
367	/** The event semaphore the invalidation-queue thread waits on. */
368	SUPSEMEVENT hEvtInvQueue;
369	/** Error diagnostic. */
370	DMARDIAG enmDiag;
371	/** Padding. */
372	uint32_t uPadding0;
373	/** The MMIO handle. */
374	IOMMMIOHANDLE hMmio;
375
376	#ifdef VBOX_WITH_STATISTICS
377	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
378	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
379	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
380	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
381
382	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
383	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
384	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
385	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
386
387	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
388	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
389	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
390	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
391
392	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
393	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
394	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
395	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
396
397	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
398	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
399	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
400	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
401	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
402	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
403	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
404	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
405	#endif
406	} DMAR;
407	/** Pointer to the DMAR device state. */
408	typedef DMAR *PDMAR;
409	/** Pointer to the const DMAR device state. */
410	typedef DMAR const *PCDMAR;
411	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
412	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
413
414	/**
415	* The ring-3 DMAR device state.
416	*/
417	typedef struct DMARR3
418	{
419	/** Device instance. */
420	PPDMDEVINSR3 pDevInsR3;
421	/** The IOMMU helper. */
422	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
423	/** The invalidation-queue thread. */
424	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
425	} DMARR3;
426	/** Pointer to the ring-3 DMAR device state. */
427	typedef DMARR3 *PDMARR3;
428	/** Pointer to the const ring-3 DMAR device state. */
429	typedef DMARR3 const *PCDMARR3;
430
431	/**
432	* The ring-0 DMAR device state.
433	*/
434	typedef struct DMARR0
435	{
436	/** Device instance. */
437	PPDMDEVINSR0 pDevInsR0;
438	/** The IOMMU helper. */
439	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
440	} DMARR0;
441	/** Pointer to the ring-0 IOMMU device state. */
442	typedef DMARR0 *PDMARR0;
443	/** Pointer to the const ring-0 IOMMU device state. */
444	typedef DMARR0 const *PCDMARR0;
445
446	/**
447	* The raw-mode DMAR device state.
448	*/
449	typedef struct DMARRC
450	{
451	/** Device instance. */
452	PPDMDEVINSRC pDevInsRC;
453	/** The IOMMU helper. */
454	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
455	} DMARRC;
456	/** Pointer to the raw-mode DMAR device state. */
457	typedef DMARRC *PDMARRC;
458	/** Pointer to the const raw-mode DMAR device state. */
459	typedef DMARRC const *PCIDMARRC;
460
461	/** The DMAR device state for the current context. */
462	typedef CTX_SUFF(DMAR) DMARCC;
463	/** Pointer to the DMAR device state for the current context. */
464	typedef CTX_SUFF(PDMAR) PDMARCC;
465	/** Pointer to the const DMAR device state for the current context. */
466	typedef CTX_SUFF(PDMAR) const PCDMARCC;
467
468	/**
469	* DMAR originated events that generate interrupts.
470	*/
471	typedef enum DMAREVENTTYPE
472	{
473	/** Invalidation completion event. */
474	DMAREVENTTYPE_INV_COMPLETE = 0,
475	/** Fault event. */
476	DMAREVENTTYPE_FAULT
477	} DMAREVENTTYPE;
478
479	/**
480	* I/O Page.
481	*/
482	typedef struct DMARIOPAGE
483	{
484	/** The base DMA address of a page. */
485	RTGCPHYS GCPhysBase;
486	/** The page shift. */
487	uint8_t cShift;
488	/** The permissions of this page (DMAR_PERM_XXX). */
489	uint8_t fPerm;
490	} DMARIOPAGE;
491	/** Pointer to an I/O page. */
492	typedef DMARIOPAGE *PDMARIOPAGE;
493	/** Pointer to a const I/O address range. */
494	typedef DMARIOPAGE const *PCDMARIOPAGE;
495
496	/**
497	* I/O Address Range.
498	*/
499	typedef struct DMARIOADDRRANGE
500	{
501	/** The starting DMA address of this range. */
502	uint64_t uAddr;
503	/** The size of the range (in bytes). */
504	size_t cb;
505	/** The permissions of this range (DMAR_PERM_XXX). */
506	uint8_t fPerm;
507	} DMARIOADDRRANGE;
508	/** Pointer to an I/O address range. */
509	typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
510	/** Pointer to a const I/O address range. */
511	typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
512
513	/**
514	* DMA Memory Request (Input).
515	*/
516	typedef struct DMARMEMREQIN
517	{
518	/** The address range being accessed. */
519	DMARIOADDRRANGE AddrRange;
520	/** The source device ID (bus, device, function). */
521	uint16_t idDevice;
522	/** The PASID if present (can be NIL_PCIPASID). */
523	PCIPASID Pasid;
524	/* The address translation type. */
525	PCIADDRTYPE enmAddrType;
526	/** The request type. */
527	VTDREQTYPE enmReqType;
528	} DMARMEMREQIN;
529	/** Pointer to a DMA memory request input. */
530	typedef DMARMEMREQIN *PDMARMEMREQIN;
531	/** Pointer to a const DMA memory input. */
532	typedef DMARMEMREQIN const *PCDMARMEMREQIN;
533
534	/**
535	* DMA Memory Request (Output).
536	*/
537	typedef struct DMARMEMREQOUT
538	{
539	/** The address range of the translated region. */
540	DMARIOADDRRANGE AddrRange;
541	/** The domain ID of the translated region. */
542	uint16_t idDomain;
543	} DMARMEMREQOUT;
544	/** Pointer to a DMA memory request output. */
545	typedef DMARMEMREQOUT *PDMARMEMREQOUT;
546	/** Pointer to a const DMA memory request output. */
547	typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
548
549	/**
550	* DMA Memory Request (Auxiliary Info).
551	* These get updated and used as part of the translation process.
552	*/
553	typedef struct DMARMEMREQAUX
554	{
555	/** The table translation mode (VTD_TTM_XXX). */
556	uint8_t fTtm;
557	/** The fault processing disabled (FPD) bit. */
558	uint8_t fFpd;
559	/** The paging level of the translation. */
560	uint8_t cPagingLevel;
561	uint8_t abPadding[5];
562	/** The address of the first-level page-table. */
563	uint64_t GCPhysFlPt;
564	/** The address of second-level page-table. */
565	uint64_t GCPhysSlPt;
566	} DMARMEMREQAUX;
567	/** Pointer to a DMA memory request output. */
568	typedef DMARMEMREQAUX *PDMARMEMREQAUX;
569	/** Pointer to a const DMA memory request output. */
570	typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
571
572	/**
573	* DMA Memory Request Remapping Information.
574	*/
575	typedef struct DMARMEMREQREMAP
576	{
577	/** The DMA memory request input. */
578	DMARMEMREQIN In;
579	/** DMA memory request auxiliary information. */
580	DMARMEMREQAUX Aux;
581	/** The DMA memory request output. */
582	DMARMEMREQOUT Out;
583	} DMARMEMREQREMAP;
584	/** Pointer to a DMA remap info. */
585	typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
586	/** Pointer to a const DMA remap info. */
587	typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
588
589	/**
590	* Callback function to lookup a DMA address.
591	*
592	* @returns VBox status code.
593	* @param pDevIns The IOMMU device instance.
594	* @param pMemReqIn The DMA memory request input.
595	* @param pMemReqAux The DMA memory request auxiliary info.
596	* @param pIoPageOut Where to store the output of the lookup.
597	*/
598	typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
599	PDMARIOPAGE pIoPageOut));
600	/** Pointer to a DMA address-lookup function. */
601	typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
602
603
604	/*********************************************************************************************************************************
605	* Global Variables *
606	*********************************************************************************************************************************/
607	/**
608	* Read-write masks for DMAR registers (group 0).
609	*/
610	static uint32_t const g_au32RwMasks0[] =
611	{
612	/* Offset Register Low High */
613	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
614	/* 0x004 Reserved */ 0,
615	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
616	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
617	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
618	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
619	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
620	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
621	/* 0x030 Reserved */ 0,
622	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
623	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
624	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
625	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
626	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
627	/* 0x048 Reserved */ 0, 0,
628	/* 0x050 Reserved */ 0, 0,
629	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
630	/* 0x060 Reserved */ 0,
631	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
632	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
633	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
634	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
635	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
636	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
637	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
638	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
639	/* 0x098 Reserved */ 0,
640	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
641	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
642	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
643	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
644	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
645	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
646	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
647	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
648	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
649	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
650	/* 0x0d8 Reserved */ 0,
651	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
652	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
653	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
654	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
655	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
656	/* 0x0f0 Reserved */ 0, 0,
657	/* 0x0f8 Reserved */ 0, 0,
658	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
659	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
660	/* 0x110 Reserved */ 0, 0,
661	/* 0x118 Reserved */ 0, 0,
662	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
663	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
664	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
665	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
666	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
667	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
668	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
669	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
670	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
671	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
672	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
673	/* 0x178 Reserved */ 0, 0,
674	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
675	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
676	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
677	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
678	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
679	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
680	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
681	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
682	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
683	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
684	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
685	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
686	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
687	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
688	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
689	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
690	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
691	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
692	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
693	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
694	};
695	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
696
697	/**
698	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
699	*/
700	static uint32_t const g_au32Rw1cMasks0[] =
701	{
702	/* Offset Register Low High */
703	/* 0x000 VER_REG */ 0,
704	/* 0x004 Reserved */ 0,
705	/* 0x008 CAP_REG */ 0, 0,
706	/* 0x010 ECAP_REG */ 0, 0,
707	/* 0x018 GCMD_REG */ 0,
708	/* 0x01c GSTS_REG */ 0,
709	/* 0x020 RTADDR_REG */ 0, 0,
710	/* 0x028 CCMD_REG */ 0, 0,
711	/* 0x030 Reserved */ 0,
712	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
713	/* 0x038 FECTL_REG */ 0,
714	/* 0x03c FEDATA_REG */ 0,
715	/* 0x040 FEADDR_REG */ 0,
716	/* 0x044 FEUADDR_REG */ 0,
717	/* 0x048 Reserved */ 0, 0,
718	/* 0x050 Reserved */ 0, 0,
719	/* 0x058 AFLOG_REG */ 0, 0,
720	/* 0x060 Reserved */ 0,
721	/* 0x064 PMEN_REG */ 0,
722	/* 0x068 PLMBASE_REG */ 0,
723	/* 0x06c PLMLIMIT_REG */ 0,
724	/* 0x070 PHMBASE_REG */ 0, 0,
725	/* 0x078 PHMLIMIT_REG */ 0, 0,
726	/* 0x080 IQH_REG */ 0, 0,
727	/* 0x088 IQT_REG */ 0, 0,
728	/* 0x090 IQA_REG */ 0, 0,
729	/* 0x098 Reserved */ 0,
730	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
731	/* 0x0a0 IECTL_REG */ 0,
732	/* 0x0a4 IEDATA_REG */ 0,
733	/* 0x0a8 IEADDR_REG */ 0,
734	/* 0x0ac IEUADDR_REG */ 0,
735	/* 0x0b0 IQERCD_REG */ 0, 0,
736	/* 0x0b8 IRTA_REG */ 0, 0,
737	/* 0x0c0 PQH_REG */ 0, 0,
738	/* 0x0c8 PQT_REG */ 0, 0,
739	/* 0x0d0 PQA_REG */ 0, 0,
740	/* 0x0d8 Reserved */ 0,
741	/* 0x0dc PRS_REG */ 0,
742	/* 0x0e0 PECTL_REG */ 0,
743	/* 0x0e4 PEDATA_REG */ 0,
744	/* 0x0e8 PEADDR_REG */ 0,
745	/* 0x0ec PEUADDR_REG */ 0,
746	/* 0x0f0 Reserved */ 0, 0,
747	/* 0x0f8 Reserved */ 0, 0,
748	/* 0x100 MTRRCAP_REG */ 0, 0,
749	/* 0x108 MTRRDEF_REG */ 0, 0,
750	/* 0x110 Reserved */ 0, 0,
751	/* 0x118 Reserved */ 0, 0,
752	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
753	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
754	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
755	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
756	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
757	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
758	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
759	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
760	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
761	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
762	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
763	/* 0x178 Reserved */ 0, 0,
764	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
765	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
766	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
767	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
768	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
769	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
770	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
771	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
772	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
773	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
774	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
775	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
776	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
777	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
778	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
779	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
780	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
781	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
782	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
783	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
784	};
785	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
786
787	/**
788	* Read-write masks for DMAR registers (group 1).
789	*/
790	static uint32_t const g_au32RwMasks1[] =
791	{
792	/* Offset Register Low High */
793	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
794	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
795	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
796	/* 0xe18 VCMDRSVD_REG */ 0, 0,
797	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
798	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
799	/* 0xe30 Reserved */ 0, 0,
800	/* 0xe38 Reserved */ 0, 0,
801	/* 0xe40 Reserved */ 0, 0,
802	/* 0xe48 Reserved */ 0, 0,
803	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
804	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
805	/* 0xe60 Reserved */ 0, 0,
806	/* 0xe68 Reserved */ 0, 0,
807	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
808	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
809	};
810	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
811	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
812
813	/**
814	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
815	*/
816	static uint32_t const g_au32Rw1cMasks1[] =
817	{
818	/* Offset Register Low High */
819	/* 0xe00 VCCAP_REG */ 0, 0,
820	/* 0xe08 VCMD_EO_REG */ 0, 0,
821	/* 0xe10 VCMD_REG */ 0, 0,
822	/* 0xe18 VCMDRSVD_REG */ 0, 0,
823	/* 0xe20 VCRSP_REG */ 0, 0,
824	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
825	/* 0xe30 Reserved */ 0, 0,
826	/* 0xe38 Reserved */ 0, 0,
827	/* 0xe40 Reserved */ 0, 0,
828	/* 0xe48 Reserved */ 0, 0,
829	/* 0xe50 IVA_REG */ 0, 0,
830	/* 0xe58 IOTLB_REG */ 0, 0,
831	/* 0xe60 Reserved */ 0, 0,
832	/* 0xe68 Reserved */ 0, 0,
833	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
834	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
835	};
836	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
837
838	/** Array of RW masks for each register group. */
839	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
840
841	/** Array of RW1C masks for each register group. */
842	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
843
844	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
845	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
846
847	/** Array of valid domain-ID bits. */
848	static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
849	AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
850
851
852	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
853	/**
854	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
855	* guest address width (MGAW).
856	*
857	* @returns The CAP_REG.SAGAW value.
858	* @param uMgaw The CAP_REG.MGAW value.
859	*/
860	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
861	{
862	/*
863	* It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
864	* 5-level paging but not 4 or 3-level paging. So smaller page-table levels
865	* are always OR'ed in below.
866	*
867	* The bit values below (57, 48, 39 bits) represents the levels of page-table walks
868	* for 4KB base page size (5-level, 4-level and 3-level paging respectively).
869	*
870	* See Intel VT-d spec. 10.4.2 "Capability Register".
871	*/
872	++uMgaw;
873	uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1)
874	: uMgaw >= 48 ? RT_BIT(2) \| RT_BIT(1)
875	: uMgaw >= 39 ? RT_BIT(1)
876	: 0;
877	return fSagaw;
878	}
879
880
881	/**
882	* Returns the maximum supported paging level given the supported adjusted
883	* guest-address width (SAGAW) field.
884	*
885	* @returns The highest paging level supported, 0 if invalid.
886	* @param fSagaw The CAP_REG.SAGAW value.
887	*/
888	static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
889	{
890	uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
891	: fSagaw & RT_BIT(2) ? 4
892	: fSagaw & RT_BIT(1) ? 3
893	: 0;
894	return cMaxPagingLevel;
895	}
896
897
898	/**
899	* Returns whether the interrupt remapping (IR) fault is qualified or not.
900	*
901	* @returns @c true if qualified, @c false otherwise.
902	* @param enmIrFault The interrupt remapping fault condition.
903	*/
904	static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
905	{
906	switch (enmIrFault)
907	{
908	case VTDIRFAULT_IRTE_NOT_PRESENT:
909	case VTDIRFAULT_IRTE_PRESENT_RSVD:
910	case VTDIRFAULT_IRTE_PRESENT_INVALID:
911	case VTDIRFAULT_PID_READ_FAILED:
912	case VTDIRFAULT_PID_RSVD:
913	return true;
914	default:
915	return false;
916	}
917	}
918
919
920	/**
921	* Returns table translation mode's descriptive name.
922	*
923	* @returns The descriptive name.
924	* @param uTtm The RTADDR_REG.TTM value.
925	*/
926	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
927	{
928	Assert(!(uTtm & 3));
929	static const char* s_apszTtmNames[] =
930	{
931	"Legacy Mode",
932	"Scalable Mode",
933	"Reserved",
934	"Abort-DMA Mode"
935	};
936	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
937	}
938
939
940	/**
941	* Gets the index of the group the register belongs to given its MMIO offset.
942	*
943	* @returns The group index.
944	* @param offReg The MMIO offset of the register.
945	* @param cbReg The size of the access being made (for bounds checking on
946	* debug builds).
947	*/
948	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
949	{
950	uint16_t const offLast = offReg + cbReg - 1;
951	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
952	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
953	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
954	}
955
956
957	/**
958	* Gets the group the register belongs to given its MMIO offset.
959	*
960	* @returns Pointer to the first element of the register group.
961	* @param pThis The shared DMAR device state.
962	* @param offReg The MMIO offset of the register.
963	* @param cbReg The size of the access being made (for bounds checking on
964	* debug builds).
965	* @param pIdxGroup Where to store the index of the register group the register
966	* belongs to.
967	*/
968	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
969	{
970	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
971	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
972	return apbRegs[*pIdxGroup];
973	}
974
975
976	/**
977	* Const/read-only version of dmarRegGetGroup.
978	*
979	* @copydoc dmarRegGetGroup
980	*/
981	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
982	{
983	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
984	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
985	return apbRegs[*pIdxGroup];
986	}
987
988
989	/**
990	* Writes a 32-bit register with the exactly the supplied value.
991	*
992	* @param pThis The shared DMAR device state.
993	* @param offReg The MMIO offset of the register.
994	* @param uReg The 32-bit value to write.
995	*/
996	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
997	{
998	uint8_t idxGroup;
999	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
1000	NOREF(idxGroup);
1001	(uint32_t )(pabRegs + offReg) = uReg;
1002	}
1003
1004
1005	/**
1006	* Writes a 64-bit register with the exactly the supplied value.
1007	*
1008	* @param pThis The shared DMAR device state.
1009	* @param offReg The MMIO offset of the register.
1010	* @param uReg The 64-bit value to write.
1011	*/
1012	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1013	{
1014	uint8_t idxGroup;
1015	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1016	NOREF(idxGroup);
1017	(uint64_t )(pabRegs + offReg) = uReg;
1018	}
1019
1020
1021	/**
1022	* Reads a 32-bit register with exactly the value it contains.
1023	*
1024	* @returns The raw register value.
1025	* @param pThis The shared DMAR device state.
1026	* @param offReg The MMIO offset of the register.
1027	*/
1028	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1029	{
1030	uint8_t idxGroup;
1031	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1032	NOREF(idxGroup);
1033	return (uint32_t )(pabRegs + offReg);
1034	}
1035
1036
1037	/**
1038	* Reads a 64-bit register with exactly the value it contains.
1039	*
1040	* @returns The raw register value.
1041	* @param pThis The shared DMAR device state.
1042	* @param offReg The MMIO offset of the register.
1043	*/
1044	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1045	{
1046	uint8_t idxGroup;
1047	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1048	NOREF(idxGroup);
1049	return (uint64_t )(pabRegs + offReg);
1050	}
1051
1052
1053	/**
1054	* Reads a 32-bit register with exactly the value it contains along with their
1055	* corresponding masks
1056	*
1057	* @param pThis The shared DMAR device state.
1058	* @param offReg The MMIO offset of the register.
1059	* @param puReg Where to store the raw 32-bit register value.
1060	* @param pfRwMask Where to store the RW mask corresponding to this register.
1061	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1062	*/
1063	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
1064	{
1065	uint8_t idxGroup;
1066	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1067	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1068	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1069	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1070	puReg = (uint32_t *)(pabRegs + offReg);
1071	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
1072	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
1073	}
1074
1075
1076	/**
1077	* Reads a 64-bit register with exactly the value it contains along with their
1078	* corresponding masks.
1079	*
1080	* @param pThis The shared DMAR device state.
1081	* @param offReg The MMIO offset of the register.
1082	* @param puReg Where to store the raw 64-bit register value.
1083	* @param pfRwMask Where to store the RW mask corresponding to this register.
1084	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1085	*/
1086	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
1087	{
1088	uint8_t idxGroup;
1089	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1090	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1091	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1092	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1093	puReg = (uint64_t *)(pabRegs + offReg);
1094	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
1095	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
1096	}
1097
1098
1099	/**
1100	* Writes a 32-bit register as it would be when written by software.
1101	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1102	*
1103	* @returns The value that's actually written to the register.
1104	* @param pThis The shared DMAR device state.
1105	* @param offReg The MMIO offset of the register.
1106	* @param uReg The 32-bit value to write.
1107	* @param puPrev Where to store the register value prior to writing.
1108	*/
1109	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1110	{
1111	/* Read current value from the 32-bit register. */
1112	uint32_t uCurReg;
1113	uint32_t fRwMask;
1114	uint32_t fRw1cMask;
1115	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1116	*puPrev = uCurReg;
1117
1118	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1119	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1120	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1121	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1122
1123	/* Write new value to the 32-bit register. */
1124	dmarRegWriteRaw32(pThis, offReg, uNewReg);
1125	return uNewReg;
1126	}
1127
1128
1129	/**
1130	* Writes a 64-bit register as it would be when written by software.
1131	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1132	*
1133	* @returns The value that's actually written to the register.
1134	* @param pThis The shared DMAR device state.
1135	* @param offReg The MMIO offset of the register.
1136	* @param uReg The 64-bit value to write.
1137	* @param puPrev Where to store the register value prior to writing.
1138	*/
1139	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1140	{
1141	/* Read current value from the 64-bit register. */
1142	uint64_t uCurReg;
1143	uint64_t fRwMask;
1144	uint64_t fRw1cMask;
1145	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1146	*puPrev = uCurReg;
1147
1148	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1149	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1150	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1151	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1152
1153	/* Write new value to the 64-bit register. */
1154	dmarRegWriteRaw64(pThis, offReg, uNewReg);
1155	return uNewReg;
1156	}
1157
1158
1159	/**
1160	* Reads a 32-bit register as it would be when read by software.
1161	*
1162	* @returns The register value.
1163	* @param pThis The shared DMAR device state.
1164	* @param offReg The MMIO offset of the register.
1165	*/
1166	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1167	{
1168	return dmarRegReadRaw32(pThis, offReg);
1169	}
1170
1171
1172	/**
1173	* Reads a 64-bit register as it would be when read by software.
1174	*
1175	* @returns The register value.
1176	* @param pThis The shared DMAR device state.
1177	* @param offReg The MMIO offset of the register.
1178	*/
1179	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1180	{
1181	return dmarRegReadRaw64(pThis, offReg);
1182	}
1183
1184
1185	/**
1186	* Modifies a 32-bit register.
1187	*
1188	* @param pThis The shared DMAR device state.
1189	* @param offReg The MMIO offset of the register.
1190	* @param fAndMask The AND mask (applied first).
1191	* @param fOrMask The OR mask.
1192	* @remarks This does NOT apply RO or RW1C masks while modifying the
1193	* register.
1194	*/
1195	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1196	{
1197	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1198	uReg = (uReg & fAndMask) \| fOrMask;
1199	dmarRegWriteRaw32(pThis, offReg, uReg);
1200	}
1201
1202
1203	/**
1204	* Modifies a 64-bit register.
1205	*
1206	* @param pThis The shared DMAR device state.
1207	* @param offReg The MMIO offset of the register.
1208	* @param fAndMask The AND mask (applied first).
1209	* @param fOrMask The OR mask.
1210	* @remarks This does NOT apply RO or RW1C masks while modifying the
1211	* register.
1212	*/
1213	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1214	{
1215	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1216	uReg = (uReg & fAndMask) \| fOrMask;
1217	dmarRegWriteRaw64(pThis, offReg, uReg);
1218	}
1219
1220
1221	/**
1222	* Checks if the invalidation-queue is empty.
1223	*
1224	* Extended version which optionally returns the current queue head and tail
1225	* offsets.
1226	*
1227	* @returns @c true if empty, @c false otherwise.
1228	* @param pThis The shared DMAR device state.
1229	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
1230	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1231	*/
1232	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
1233	{
1234	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1235	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1236	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1237
1238	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1239	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1240	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1241	if (poffQh)
1242	*poffQh = uIqhReg;
1243	if (poffQt)
1244	*poffQt = uIqtReg;
1245	return uIqtReg == uIqhReg;
1246	}
1247
1248
1249	/**
1250	* Checks if the invalidation-queue is empty.
1251	*
1252	* @returns @c true if empty, @c false otherwise.
1253	* @param pThis The shared DMAR device state.
1254	*/
1255	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1256	{
1257	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1258	}
1259
1260
1261	/**
1262	* Checks if the invalidation-queue is capable of processing requests.
1263	*
1264	* @returns @c true if the invalidation-queue can process requests, @c false
1265	* otherwise.
1266	* @param pThis The shared DMAR device state.
1267	*/
1268	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1269	{
1270	/* Check if queued-invalidation is enabled. */
1271	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1272	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1273	{
1274	/* Check if there are no invalidation-queue or timeout errors. */
1275	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1276	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1277	return true;
1278	}
1279	return false;
1280	}
1281
1282
1283	/**
1284	* Wakes up the invalidation-queue thread if there are requests to be processed.
1285	*
1286	* @param pDevIns The IOMMU device instance.
1287	*/
1288	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1289	{
1290	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1291	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1292	LogFlowFunc(("\n"));
1293
1294	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1295
1296	if ( dmarInvQueueCanProcessRequests(pThis)
1297	&& !dmarInvQueueIsEmpty(pThis))
1298	{
1299	Log4Func(("Signaling the invalidation-queue thread\n"));
1300	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1301	}
1302	}
1303
1304
1305	/**
1306	* Raises an event on behalf of the DMAR.
1307	*
1308	* These are events that are generated by the DMAR itself (like faults and
1309	* invalidation completion notifications).
1310	*
1311	* @param pDevIns The IOMMU device instance.
1312	* @param enmEventType The DMAR event type.
1313	*
1314	* @remarks The DMAR lock must be held while calling this function.
1315	*/
1316	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1317	{
1318	uint16_t offCtlReg;
1319	uint32_t fIntrMaskedMask;
1320	uint32_t fIntrPendingMask;
1321	uint16_t offMsiAddrLoReg;
1322	uint16_t offMsiAddrHiReg;
1323	uint16_t offMsiDataReg;
1324	switch (enmEventType)
1325	{
1326	case DMAREVENTTYPE_INV_COMPLETE:
1327	{
1328	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1329	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1330	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1331	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1332	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1333	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1334	break;
1335	}
1336
1337	case DMAREVENTTYPE_FAULT:
1338	{
1339	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1340	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1341	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1342	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1343	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1344	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1345	break;
1346	}
1347
1348	default:
1349	{
1350	/* Shouldn't ever happen. */
1351	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1352	}
1353	}
1354
1355	/* Check if software has masked the interrupt. */
1356	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1357	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1358	if (!(uCtlReg & fIntrMaskedMask))
1359	{
1360	/*
1361	* Interrupt is unmasked, raise it.
1362	* Interrupts generated by the DMAR have trigger mode and level as 0.
1363	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1364	*/
1365	MSIMSG Msi;
1366	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1367	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1368	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1369	Assert(Msi.Data.n.u1Level == 0);
1370	Assert(Msi.Data.n.u1TriggerMode == 0);
1371
1372	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1373	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1374
1375	/* Clear interrupt pending bit. */
1376	uCtlReg &= ~fIntrPendingMask;
1377	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1378	}
1379	else
1380	{
1381	/* Interrupt is masked, set the interrupt pending bit. */
1382	uCtlReg \|= fIntrPendingMask;
1383	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1384	}
1385	}
1386
1387
1388	/**
1389	* Raises an interrupt in response to a fault event.
1390	*
1391	* @param pDevIns The IOMMU device instance.
1392	*
1393	* @remarks This assumes the caller has already set the required status bits in the
1394	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1395	*/
1396	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1397	{
1398	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1399	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1400	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1401
1402	#ifdef RT_STRICT
1403	{
1404	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1405	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1406	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1407	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1408	\| VTD_BF_FSTS_REG_IQE_MASK;
1409	Assert(uFstsReg & fFaultMask);
1410	}
1411	#endif
1412	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1413	}
1414
1415
1416	#ifdef IN_RING3
1417	/**
1418	* Raises an interrupt in response to an invalidation (complete) event.
1419	*
1420	* @param pDevIns The IOMMU device instance.
1421	*/
1422	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1423	{
1424	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1425	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1426	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1427
1428	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1429	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1430	{
1431	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1432	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1433	}
1434	}
1435	#endif /* IN_RING3 */
1436
1437
1438	/**
1439	* Checks if a primary fault can be recorded.
1440	*
1441	* @returns @c true if the fault can be recorded, @c false otherwise.
1442	* @param pDevIns The IOMMU device instance.
1443	* @param pThis The shared DMAR device state.
1444	*
1445	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1446	* NOT call it unless there is a fault condition!
1447	*/
1448	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1449	{
1450	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1451	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1452
1453	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1454	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1455	return false;
1456
1457	/*
1458	* If we add more FRCD registers, we'll have to loop through them here.
1459	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1460	* nor do we need to increment FRI.
1461	*
1462	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1463	*/
1464	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1465	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1466	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1467	{
1468	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1469	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1470	return false;
1471	}
1472
1473	return true;
1474	}
1475
1476
1477	/**
1478	* Records a primary fault.
1479	*
1480	* @param pDevIns The IOMMU device instance.
1481	* @param uFrcdHi The FRCD_HI_REG value for this fault.
1482	* @param uFrcdLo The FRCD_LO_REG value for this fault.
1483	*/
1484	static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1485	{
1486	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1487	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1488
1489	DMAR_LOCK(pDevIns, pThisCC);
1490
1491	/* We don't support advance fault logging. */
1492	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1493
1494	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1495	{
1496	/* Update the fault recording registers with the fault information. */
1497	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1498	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1499
1500	/* Set the Pending Primary Fault (PPF) field in the status register. */
1501	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1502
1503	/* Raise interrupt if necessary. */
1504	dmarFaultEventRaiseInterrupt(pDevIns);
1505	}
1506
1507	DMAR_UNLOCK(pDevIns, pThisCC);
1508	}
1509
1510
1511	/**
1512	* Records an interrupt request fault.
1513	*
1514	* @param pDevIns The IOMMU device instance.
1515	* @param enmDiag The diagnostic reason.
1516	* @param idDevice The device ID (bus, device, function).
1517	* @param idxIntr The interrupt index.
1518	* @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1519	* not qualified.
1520	*/
1521	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1522	{
1523	/*
1524	* Update the diagnostic reason (even if software wants to supress faults).
1525	*/
1526	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1527	pThis->enmDiag = enmDiag;
1528
1529	/*
1530	* Figure out the fault reason to report to software from our diagnostic code.
1531	* The case labels below are sorted alphabetically for convenience.
1532	*/
1533	VTDIRFAULT enmIrFault;
1534	switch (enmDiag)
1535	{
1536	case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1537	case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1538	case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1539	case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1540	case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1541	case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1542	case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1543	case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1544	case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1545	case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1546
1547	/* Shouldn't ever happen. */
1548	default:
1549	{
1550	AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1551	enmDiag));
1552	}
1553	}
1554
1555	/*
1556	* Qualified faults are those that can be suppressed by software using the FPD bit
1557	* in the interrupt-remapping table entry.
1558	*/
1559	bool fFpd;
1560	bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1561	if (fQualifiedFault)
1562	{
1563	AssertReturnVoid(pIrte);
1564	fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1565	}
1566	else
1567	fFpd = false;
1568
1569	if (!fFpd)
1570	{
1571	/* Construct and record the error. */
1572	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1573	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1574	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1575	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1576	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1577	}
1578	}
1579
1580
1581	/**
1582	* Records an address translation fault.
1583	*
1584	* @param pDevIns The IOMMU device instance.
1585	* @param enmDiag The diagnostic reason.
1586	* @param pMemReqIn The DMA memory request input.
1587	* @param pMemReqAux The DMA memory request auxiliary info.
1588	*/
1589	static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1590	{
1591	/*
1592	* Update the diagnostic reason (even if software wants to supress faults).
1593	*/
1594	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1595	pThis->enmDiag = enmDiag;
1596
1597	/*
1598	* Qualified faults are those that can be suppressed by software using the FPD bit
1599	* in the context entry, scalable-mode context entry etc.
1600	*/
1601	if (!pMemReqAux->fFpd)
1602	{
1603	/*
1604	* Figure out the fault reason to report to software from our diagnostic code.
1605	* The case labels below are sorted alphabetically for convenience.
1606	*/
1607	VTDATFAULT enmAtFault;
1608	bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1609	switch (enmDiag)
1610	{
1611	/* LM (Legacy Mode) faults. */
1612	case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1613	case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1614	case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1615	case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1616	case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1617	case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1618	case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1619	case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1620	case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1621	case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1622	case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1623
1624	/* RTA (Root Table Address) faults. */
1625	case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1626	case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1627	case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1628
1629	/* XM (Legacy mode or Scalable Mode) faults. */
1630	case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1631	case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1632	case kDmarDiag_At_Xm_Perm_Denied: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1633	case kDmarDiag_At_Xm_Pte_Rsvd:
1634	case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1635	case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1636	case kDmarDiag_At_Xm_Slpptr_Read_Failed: enmAtFault = fLm ? VTDATFAULT_LCT_4_3 : VTDATFAULT_SSL_4; break;
1637
1638	/* Shouldn't ever happen. */
1639	default:
1640	{
1641	AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1642	DMAR_LOG_PFX, enmDiag));
1643	}
1644	}
1645
1646	/* Construct and record the error. */
1647	uint16_t const idDevice = pMemReqIn->idDevice;
1648	uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1649	uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1650	uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1651	uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1652	bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1653	uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1654	PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1655
1656	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1657	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1658	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1659	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1660	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1661	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1662	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1663	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1664	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1665	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1666	uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1667	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1668	}
1669	}
1670
1671
1672	/**
1673	* Records an IQE fault.
1674	*
1675	* @param pDevIns The IOMMU device instance.
1676	* @param enmIqei The IQE information.
1677	* @param enmDiag The diagnostic reason.
1678	*/
1679	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1680	{
1681	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1682	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1683
1684	DMAR_LOCK(pDevIns, pThisCC);
1685
1686	/* Update the diagnostic reason. */
1687	pThis->enmDiag = enmDiag;
1688
1689	/* Set the error bit. */
1690	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1691	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1692
1693	/* Set the error information. */
1694	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1695	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1696
1697	dmarFaultEventRaiseInterrupt(pDevIns);
1698
1699	DMAR_UNLOCK(pDevIns, pThisCC);
1700	}
1701
1702
1703	/**
1704	* Handles writes to GCMD_REG.
1705	*
1706	* @returns Strict VBox status code.
1707	* @param pDevIns The IOMMU device instance.
1708	* @param uGcmdReg The value written to GCMD_REG.
1709	*/
1710	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1711	{
1712	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1713	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1714	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1715	uint64_t const fExtCapReg = pThis->fExtCapReg;
1716
1717	/* Queued-invalidation. */
1718	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1719	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1720	{
1721	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1722	{
1723	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1724	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1725	}
1726	else
1727	{
1728	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1729	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1730	}
1731	}
1732
1733	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1734	{
1735	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1736	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1737	{
1738	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1739	* supported. */
1740	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1741	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1742	}
1743
1744	/* Interrupt remapping. */
1745	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1746	{
1747	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1748	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1749	else
1750	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1751	}
1752
1753	/* Compatibility format interrupts. */
1754	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1755	{
1756	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1757	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1758	else
1759	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1760	}
1761	}
1762
1763	/* Set Root Table Pointer (SRTP). */
1764	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1765	{
1766	/** @todo Perform global invalidation of all remapping translation caches when
1767	* ESRTPS is supported. */
1768	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1769	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1770	}
1771
1772	/* Translation (DMA remapping). */
1773	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1774	{
1775	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1776	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1777	else
1778	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1779	}
1780
1781	return VINF_SUCCESS;
1782	}
1783
1784
1785	/**
1786	* Handles writes to CCMD_REG.
1787	*
1788	* @returns Strict VBox status code.
1789	* @param pDevIns The IOMMU device instance.
1790	* @param offReg The MMIO register offset.
1791	* @param cbReg The size of the MMIO access (in bytes).
1792	* @param uCcmdReg The value written to CCMD_REG.
1793	*/
1794	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1795	{
1796	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1797	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1798	{
1799	/* Check if we need to invalidate the context-context. */
1800	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1801	if (fIcc)
1802	{
1803	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1804	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1805	if (uMajorVersion < 6)
1806	{
1807	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1808	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1809	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1810	{
1811	/* Verify table translation mode is legacy. */
1812	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1813	if (fTtm == VTD_TTM_LEGACY_MODE)
1814	{
1815	/** @todo Invalidate. */
1816	return VINF_SUCCESS;
1817	}
1818	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1819	}
1820	else
1821	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1822	}
1823	else
1824	pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1825	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1826	}
1827	}
1828	return VINF_SUCCESS;
1829	}
1830
1831
1832	/**
1833	* Handles writes to FECTL_REG.
1834	*
1835	* @returns Strict VBox status code.
1836	* @param pDevIns The IOMMU device instance.
1837	* @param uFectlReg The value written to FECTL_REG.
1838	*/
1839	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1840	{
1841	/*
1842	* If software unmasks the interrupt when the interrupt is pending, we must raise
1843	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1844	*/
1845	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1846	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1847	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1848	return VINF_SUCCESS;
1849	}
1850
1851
1852	/**
1853	* Handles writes to FSTS_REG.
1854	*
1855	* @returns Strict VBox status code.
1856	* @param pDevIns The IOMMU device instance.
1857	* @param uFstsReg The value written to FSTS_REG.
1858	* @param uPrev The value in FSTS_REG prior to writing it.
1859	*/
1860	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1861	{
1862	/*
1863	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1864	* the interrupt pending (IP) bit must be cleared.
1865	*
1866	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1867	*/
1868	uint32_t const fChanged = uPrev ^ uFstsReg;
1869	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1870	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1871	{
1872	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1873	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1874	}
1875	return VINF_SUCCESS;
1876	}
1877
1878
1879	/**
1880	* Handles writes to IQT_REG.
1881	*
1882	* @returns Strict VBox status code.
1883	* @param pDevIns The IOMMU device instance.
1884	* @param offReg The MMIO register offset.
1885	* @param uIqtReg The value written to IQT_REG.
1886	*/
1887	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1888	{
1889	/* We only care about the low 32-bits, high 32-bits are reserved. */
1890	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1891	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1892
1893	/* Paranoia. */
1894	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1895
1896	uint32_t const offQt = uIqtReg;
1897	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1898	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1899
1900	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1901	if ( fDw != VTD_IQA_REG_DW_256_BIT
1902	\|\| !(offQt & RT_BIT(4)))
1903	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1904	else
1905	{
1906	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1907	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1908	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1909	}
1910	return VINF_SUCCESS;
1911	}
1912
1913
1914	/**
1915	* Handles writes to IQA_REG.
1916	*
1917	* @returns Strict VBox status code.
1918	* @param pDevIns The IOMMU device instance.
1919	* @param offReg The MMIO register offset.
1920	* @param uIqaReg The value written to IQA_REG.
1921	*/
1922	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1923	{
1924	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1925	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1926
1927	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1928	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1929	* cannot happen or that it's ignored when it does happen. */
1930
1931	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1932	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1933	if (fDw == VTD_IQA_REG_DW_256_BIT)
1934	{
1935	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1936	if (fSupports256BitDw)
1937	{ /* likely */ }
1938	else
1939	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1940	}
1941	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1942
1943	return VINF_SUCCESS;
1944	}
1945
1946
1947	/**
1948	* Handles writes to ICS_REG.
1949	*
1950	* @returns Strict VBox status code.
1951	* @param pDevIns The IOMMU device instance.
1952	* @param uIcsReg The value written to ICS_REG.
1953	*/
1954	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1955	{
1956	/*
1957	* If the IP field is set when software services the interrupt condition,
1958	* (by clearing the IWC field), the IP field must be cleared.
1959	*/
1960	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1961	{
1962	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1963	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1964	}
1965	return VINF_SUCCESS;
1966	}
1967
1968
1969	/**
1970	* Handles writes to IECTL_REG.
1971	*
1972	* @returns Strict VBox status code.
1973	* @param pDevIns The IOMMU device instance.
1974	* @param uIectlReg The value written to IECTL_REG.
1975	*/
1976	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1977	{
1978	/*
1979	* If software unmasks the interrupt when the interrupt is pending, we must raise
1980	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1981	*/
1982	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1983	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1984	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1985	return VINF_SUCCESS;
1986	}
1987
1988
1989	/**
1990	* Handles writes to FRCD_REG (High 64-bits).
1991	*
1992	* @returns Strict VBox status code.
1993	* @param pDevIns The IOMMU device instance.
1994	* @param offReg The MMIO register offset.
1995	* @param cbReg The size of the MMIO access (in bytes).
1996	* @param uFrcdHiReg The value written to FRCD_REG.
1997	* @param uPrev The value in FRCD_REG prior to writing it.
1998	*/
1999	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
2000	{
2001	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
2002	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
2003	{
2004	/*
2005	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
2006	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
2007	* has only 1 FRCD register.
2008	*
2009	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
2010	*/
2011	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2012	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2013	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2014	{
2015	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2016	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2017	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2018	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2019	}
2020	}
2021	return VINF_SUCCESS;
2022	}
2023
2024
2025	/**
2026	* Performs a PCI target abort for a DMA remapping (DR) operation.
2027	*
2028	* @param pDevIns The IOMMU device instance.
2029	*/
2030	static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2031	{
2032	/** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2033	* as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2034	* who knows. */
2035	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2036	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2037	PDMPciDevSetStatus(pPciDev, u16Status);
2038	}
2039
2040
2041	/**
2042	* Checks whether the address width (AW) is supported by our hardware
2043	* implementation for legacy mode address translation.
2044	*
2045	* @returns @c true if it's supported, @c false otherwise.
2046	* @param pThis The shared DMAR device state.
2047	* @param pCtxEntry The context entry.
2048	* @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2049	*/
2050	static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2051	{
2052	uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2053	uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2054	uint8_t const fAwMask = RT_BIT(fAw);
2055	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2056	Assert(!(fSagaw & ~(RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3))));
2057
2058	uint8_t const cPagingLevel = fAw + 2;
2059	if (pcPagingLevel)
2060	*pcPagingLevel = cPagingLevel;
2061
2062	/* With pass-through, the address width must be the largest AGAW supported by hardware. */
2063	if (fTt == VTD_TT_UNTRANSLATED_PT)
2064	{
2065	Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2066	return cPagingLevel == pThis->cMaxPagingLevel;
2067	}
2068
2069	/* The address width must be any of the ones supported by hardware. */
2070	if (fAw < 4)
2071	return (fSagaw & fAwMask) != 0;
2072
2073	return false;
2074	}
2075
2076
2077	/**
2078	* Reads a root entry from guest memory.
2079	*
2080	* @returns VBox status code.
2081	* @param pDevIns The IOMMU device instance.
2082	* @param uRtaddrReg The current RTADDR_REG value.
2083	* @param idxRootEntry The index of the root entry to read.
2084	* @param pRootEntry Where to store the read root entry.
2085	*/
2086	static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2087	{
2088	size_t const cbRootEntry = sizeof(*pRootEntry);
2089	RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2090	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2091	}
2092
2093
2094	/**
2095	* Reads a context entry from guest memory.
2096	*
2097	* @returns VBox status code.
2098	* @param pDevIns The IOMMU device instance.
2099	* @param GCPhysCtxTable The physical address of the context table.
2100	* @param idxCtxEntry The index of the context entry to read.
2101	* @param pCtxEntry Where to store the read context entry.
2102	*/
2103	static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2104	{
2105	/* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2106	size_t const cbCtxEntry = sizeof(*pCtxEntry);
2107	RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2108	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2109	}
2110
2111
2112	/**
2113	* Validates and updates the output I/O page of a translation.
2114	*
2115	* @returns VBox status code.
2116	* @param pDevIns The IOMMU device instance.
2117	* @param GCPhysBase The output address of the translation.
2118	* @param cShift The page shift of the translated address.
2119	* @param fPerm The permissions granted for the translated region.
2120	* @param pMemReqIn The DMA memory request input.
2121	* @param pMemReqAux The DMA memory request auxiliary info.
2122	* @param pIoPageOut Where to store the output of the translation.
2123	*/
2124	static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2125	PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2126	{
2127	Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2128
2129	/* Ensure the output address is not in the interrupt address range. */
2130	if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2131	{
2132	pIoPageOut->GCPhysBase = GCPhysBase;
2133	pIoPageOut->cShift = cShift;
2134	pIoPageOut->fPerm = fPerm;
2135	return VINF_SUCCESS;
2136	}
2137
2138	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2139	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2140	}
2141
2142
2143	/**
2144	* Performs second level translation by walking the I/O page tables.
2145	*
2146	* This is a DMA address-lookup callback function which performs the translation
2147	* (and access control) as part of the lookup.
2148	*
2149	* @returns VBox status code.
2150	* @param pDevIns The IOMMU device instance.
2151	* @param pMemReqIn The DMA memory request input.
2152	* @param pMemReqAux The DMA memory request auxiliary info.
2153	* @param pIoPageOut Where to store the output of the translation.
2154	*/
2155	static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2156	PDMARIOPAGE pIoPageOut)
2157	{
2158	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2159
2160	/* Sanity. */
2161	Assert(pIoPageOut);
2162	Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ \| DMAR_PERM_WRITE));
2163	Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2164	\|\| pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2165	Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
2166
2167	/* Mask of valid paging entry bits. */
2168	static uint64_t const s_auPtEntityRsvd[] = { VTD_SL_PTE_VALID_MASK,
2169	VTD_SL_PDE_VALID_MASK,
2170	VTD_SL_PDPE_VALID_MASK,
2171	VTD_SL_PML4E_VALID_MASK,
2172	VTD_SL_PML5E_VALID_MASK };
2173
2174	/* Paranoia. */
2175	Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2176	AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == 5);
2177
2178	/* Second-level translations restricts input address to an implementation-specific MGAW. */
2179	uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2180	if (!(uAddrIn & pThis->fMgawInvMask))
2181	{ /* likely */ }
2182	else
2183	{
2184	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2185	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2186	}
2187
2188	/*
2189	* Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2190	* Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2191	*/
2192	uint64_t uPtEntity = pMemReqAux->GCPhysSlPt;
2193	for (int8_t idxLevel = pMemReqAux->cPagingLevel - 1; idxLevel >= 0; idxLevel--)
2194	{
2195	/*
2196	* Read the paging entry for the current level.
2197	*/
2198	uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
2199	{
2200	uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2201	uint16_t const offPte = idxPte << 3;
2202	RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) \| offPte;
2203	int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2204	if (RT_SUCCESS(rc))
2205	{ /* likely */ }
2206	else
2207	{
2208	if ((GCPhysPtEntity & X86_PAGE_BASE_MASK) == pMemReqAux->GCPhysSlPt)
2209	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2210	else
2211	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2212	break;
2213	}
2214	}
2215
2216	/*
2217	* Check I/O permissions.
2218	* This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2219	* See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2220	*/
2221	uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2222	uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2223	Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2224	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK)); /* No Second-level access/dirty support. */
2225	if ((fPtPerm & fReqPerm) == fReqPerm)
2226	{ /* likely */ }
2227	else
2228	{
2229	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Denied, pMemReqIn, pMemReqAux);
2230	break;
2231	}
2232
2233	/*
2234	* Validate reserved bits of the current paging entry.
2235	*/
2236	if (!(uPtEntity & ~s_auPtEntityRsvd[idxLevel]))
2237	{ /* likely */ }
2238	else
2239	{
2240	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2241	break;
2242	}
2243
2244	/*
2245	* Check if this is a 1GB page or a 2MB page.
2246	*/
2247	AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2248	uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2249	if (fLargePage && idxLevel > 0)
2250	{
2251	Assert(idxLevel == 1 \|\| idxLevel == 2); /* Is guaranteed by the reserved bits check above. */
2252	uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2253	if (fSllpsMask & RT_BIT(idxLevel - 1))
2254	{
2255	/*
2256	* We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2257	* All other reserved bits are identical to the regular page-size paging entity which we've already
2258	* checked above.
2259	*/
2260	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2261
2262	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2263	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2264	}
2265
2266	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2267	break;
2268	}
2269
2270	/*
2271	* If this is the final PTE, compute the translation address and we're done.
2272	*/
2273	if (idxLevel == 0)
2274	{
2275	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2276	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2277	}
2278	}
2279
2280	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2281	}
2282
2283
2284	/**
2285	* Checks whether two consecutive I/O page results of a DMA memory request
2286	* translates to a physically contiguous region.
2287	*
2288	* @returns @c true if the I/O pages are contiguous, @c false otherwise.
2289	* @param pIoPagePrev The previous I/O page.
2290	* @param pIoPage The current I/O page.
2291	*/
2292	static bool dmarIsIoPageAccessContig(PCDMARIOPAGE pIoPagePrev, PCDMARIOPAGE pIoPage)
2293	{
2294	/* Paranoia: Permissions for pages of a DMA memory request must be identical. */
2295	Assert(pIoPagePrev->fPerm == pIoPage->fPerm);
2296
2297	size_t const cbPrev = RT_BIT_64(pIoPagePrev->cShift);
2298	RTGCPHYS const GCPhysPrev = pIoPagePrev->GCPhysBase;
2299	RTGCPHYS const GCPhys = pIoPage->GCPhysBase;
2300	#ifdef RT_STRICT
2301	/* Paranoia: Ensure offset bits are 0. */
2302	{
2303	uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pIoPagePrev->cShift);
2304	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pIoPage->cShift);
2305	Assert(!(GCPhysPrev & fOffMaskPrev));
2306	Assert(!(GCPhys & fOffMask));
2307	}
2308	#endif
2309	return GCPhysPrev + cbPrev == GCPhys;
2310	}
2311
2312
2313	/**
2314	* Looks up the range of addresses for a DMA memory request remapping.
2315	*
2316	* @returns VBox status code.
2317	* @param pDevIns The IOMMU device instance.
2318	* @param pfnLookup The DMA address lookup function.
2319	* @param pMemReqRemap The DMA memory request remapping info.
2320	*/
2321	static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2322	{
2323	AssertPtr(pfnLookup);
2324
2325	RTGCPHYS GCPhysAddr = NIL_RTGCPHYS;
2326	DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2327	uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2328	size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2329	uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2330	uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2331	size_t cbRemaining = cbAddrIn;
2332
2333	int rc;
2334	DMARIOPAGE IoPagePrev;
2335	RT_ZERO(IoPagePrev);
2336	for (;;)
2337	{
2338	/* Update the input memory request with the next address in our range that needs translation. */
2339	MemReqIn.AddrRange.uAddr = uAddrInBase;
2340	MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2341
2342	DMARIOPAGE IoPage;
2343	rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2344	if (RT_SUCCESS(rc))
2345	{
2346	Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2347
2348	/* Store the translated address before continuing to access more pages. */
2349	if (cbRemaining == cbAddrIn)
2350	{
2351	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2352	uint64_t const offAddrOut = uAddrIn & fOffMask;
2353	Assert(!(IoPage.GCPhysBase & fOffMask));
2354	GCPhysAddr = IoPage.GCPhysBase \| offAddrOut;
2355	}
2356	/* Check if addresses translated so far result in a physically contiguous region. */
2357	else if (!dmarIsIoPageAccessContig(&IoPagePrev, &IoPage))
2358	{
2359	rc = VERR_OUT_OF_RANGE;
2360	break;
2361	}
2362
2363	/* Store the I/O page lookup from the first/previous access. */
2364	IoPagePrev = IoPage;
2365
2366	/* Check if we need to access more pages. */
2367	size_t const cbPage = RT_BIT_64(IoPage.cShift);
2368	if (cbRemaining > cbPage - offAddrIn)
2369	{
2370	cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2371	uAddrInBase += cbPage; /* Update address of the next access. */
2372	offAddrIn = 0; /* After first page, all pages are accessed from offset 0. */
2373	}
2374	else
2375	{
2376	/* Caller (PDM) doesn't expect more data accessed than what was requested. */
2377	cbRemaining = 0;
2378	break;
2379	}
2380	}
2381	else
2382	break;
2383	}
2384
2385	pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddr;
2386	pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2387	pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2388	return rc;
2389	}
2390
2391
2392	/**
2393	* Handles legacy mode DMA address remapping.
2394	*
2395	* @returns VBox status code.
2396	* @param pDevIns The IOMMU device instance.
2397	* @param uRtaddrReg The current RTADDR_REG value.
2398	* @param pMemReqRemap The DMA memory request remapping info.
2399	*/
2400	static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2401	{
2402	PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2403	PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2404	PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2405	Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2406
2407	/* Read the root-entry from guest memory. */
2408	uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2409	VTD_ROOT_ENTRY_T RootEntry;
2410	int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2411	if (RT_SUCCESS(rc))
2412	{
2413	/* Check if the root entry is present (must be done before validating reserved bits). */
2414	uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2415	uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2416	bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2417	if (fRootEntryPresent)
2418	{
2419	/* Validate reserved bits in the root entry. */
2420	if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2421	&& !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2422	{
2423	/* Read the context-entry from guest memory. */
2424	RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2425	uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2426	VTD_CONTEXT_ENTRY_T CtxEntry;
2427	rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2428	if (RT_SUCCESS(rc))
2429	{
2430	uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2431	uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2432
2433	/* Note the FPD bit which software can use to supress translation faults from here on in. */
2434	pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2435
2436	/* Check if the context-entry is present (must be done before validating reserved bits). */
2437	bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2438	if (fCtxEntryPresent)
2439	{
2440	/* Validate reserved bits in the context-entry. */
2441	if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2442	&& !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
2443	{
2444	/* Get the domain ID for this mapping. */
2445	pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2446
2447	/* Validate the translation type (TT). */
2448	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2449	uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2450	switch (fTt)
2451	{
2452	case VTD_TT_UNTRANSLATED_SLP:
2453	{
2454	/*
2455	* Untranslated requests are translated using second-level paging structures referenced
2456	* through SLPTPTR. Translated requests and Translation Requests are blocked.
2457	*/
2458	if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2459	{
2460	/* Validate the address width and get the paging level. */
2461	uint8_t cPagingLevel;
2462	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2463	{
2464	/*
2465	* The second-level page table is located at the physical address specified
2466	* in the context entry with which we can finally perform second-level translation.
2467	*/
2468	pMemReqAux->cPagingLevel = cPagingLevel;
2469	pMemReqAux->GCPhysSlPt = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2470	return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2471	}
2472	else
2473	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2474	}
2475	else
2476	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2477	break;
2478	}
2479
2480	case VTD_TT_UNTRANSLATED_PT:
2481	{
2482	/*
2483	* Untranslated requests are processed as pass-through (PT) if PT is supported.
2484	* Translated and translation requests are blocked. If PT isn't supported this TT value
2485	* is reserved which I assume raises a fault (hence fallthru below).
2486	*/
2487	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2488	{
2489	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2490	{
2491	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2492	{
2493	PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2494	PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2495	pOut->AddrRange.uAddr = pIn->AddrRange.uAddr;
2496	pOut->AddrRange.cb = pIn->AddrRange.cb;
2497	pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2498	return VINF_SUCCESS;
2499	}
2500	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2501	}
2502	else
2503	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2504	break;
2505	}
2506	RT_FALL_THRU();
2507	}
2508
2509	case VTD_TT_UNTRANSLATED_DEV_TLB:
2510	{
2511	/*
2512	* Untranslated, translated and translation requests are supported but requires
2513	* device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2514	*/
2515	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2516	RT_FALL_THRU();
2517	}
2518
2519	default:
2520	{
2521	/* Any other TT value is reserved. */
2522	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2523	break;
2524	}
2525	}
2526	}
2527	else
2528	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2529	}
2530	else
2531	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2532	}
2533	else
2534	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2535	}
2536	else
2537	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2538	}
2539	else
2540	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2541	}
2542	else
2543	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2544	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2545	}
2546
2547
2548	/**
2549	* Handles remapping of DMA address requests in scalable mode.
2550	*
2551	* @returns VBox status code.
2552	* @param pDevIns The IOMMU device instance.
2553	* @param uRtaddrReg The current RTADDR_REG value.
2554	* @param pMemReqRemap The DMA memory request remapping info.
2555	*/
2556	static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2557	{
2558	RT_NOREF2(uRtaddrReg, pMemReqRemap);
2559	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2560	Assert(pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK);
2561	return VERR_NOT_IMPLEMENTED;
2562	}
2563
2564
2565	/**
2566	* Gets the DMA access permissions and the address-translation request
2567	* type given the PDM IOMMU memory access flags.
2568	*
2569	* @param pDevIns The IOMMU device instance.
2570	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2571	* @param fBulk Whether this is a bulk memory access (used for
2572	* statistics).
2573	* @param penmReqType Where to store the address-translation request type.
2574	* @param pfReqPerm Where to store the DMA access permissions.
2575	*/
2576	static void dmarDrGetPermAndReqType(PPDMDEVINS pDevIns, uint32_t fFlags, bool fBulk, PVTDREQTYPE penmReqType, uint8_t *pfReqPerm)
2577	{
2578	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2579	if (fFlags & PDMIOMMU_MEM_F_READ)
2580	{
2581	*penmReqType = VTDREQTYPE_READ;
2582	*pfReqPerm = DMAR_PERM_READ;
2583	#ifdef VBOX_WITH_STATISTICS
2584	if (!fBulk)
2585	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2586	else
2587	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2588	#else
2589	RT_NOREF2(pThis, fBulk);
2590	#endif
2591	}
2592	else
2593	{
2594	*penmReqType = VTDREQTYPE_WRITE;
2595	*pfReqPerm = DMAR_PERM_WRITE;
2596	#ifdef VBOX_WITH_STATISTICS
2597	if (!fBulk)
2598	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2599	else
2600	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2601	#else
2602	RT_NOREF2(pThis, fBulk);
2603	#endif
2604	}
2605	}
2606
2607
2608	/**
2609	* Handles DMA remapping based on the table translation mode (TTM).
2610	*
2611	* @returns VBox status code.
2612	* @param pDevIns The IOMMU device instance.
2613	* @param uRtaddrReg The current RTADDR_REG value.
2614	* @param pMemReqRemap The DMA memory request remapping info.
2615	*/
2616	static int dmarDrMemReqRemap(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2617	{
2618	int rc;
2619	switch (pMemReqRemap->Aux.fTtm)
2620	{
2621	case VTD_TTM_LEGACY_MODE:
2622	{
2623	rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2624	break;
2625	}
2626
2627	case VTD_TTM_SCALABLE_MODE:
2628	{
2629	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2630	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2631	rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2632	else
2633	{
2634	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2635	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2636	}
2637	break;
2638	}
2639
2640	case VTD_TTM_ABORT_DMA_MODE:
2641	{
2642	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2643	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2644	dmarDrTargetAbort(pDevIns);
2645	else
2646	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2647	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2648	break;
2649	}
2650
2651	default:
2652	{
2653	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2654	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &pMemReqRemap->In, &pMemReqRemap->Aux);
2655	break;
2656	}
2657	}
2658	return rc;
2659	}
2660
2661
2662	/**
2663	* Memory access bulk (one or more 4K pages) request from a device.
2664	*
2665	* @returns VBox status code.
2666	* @param pDevIns The IOMMU device instance.
2667	* @param idDevice The device ID (bus, device, function).
2668	* @param cIovas The number of addresses being accessed.
2669	* @param pauIovas The I/O virtual addresses for each page being accessed.
2670	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2671	* @param paGCPhysSpa Where to store the translated physical addresses.
2672	*
2673	* @thread Any.
2674	*/
2675	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2676	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2677	{
2678	/* Validate. */
2679	AssertPtr(pDevIns);
2680	Assert(cIovas > 0);
2681	AssertPtr(pauIovas);
2682	AssertPtr(paGCPhysSpa);
2683	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2684
2685	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2686	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2687
2688	DMAR_LOCK(pDevIns, pThisCC);
2689	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2690	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2691	DMAR_UNLOCK(pDevIns, pThisCC);
2692
2693	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2694	{
2695	VTDREQTYPE enmReqType;
2696	uint8_t fReqPerm;
2697	dmarDrGetPermAndReqType(pDevIns, fFlags, true /* fBulk */, &enmReqType, &fReqPerm);
2698
2699	DMARMEMREQREMAP MemReqRemap;
2700	RT_ZERO(MemReqRemap);
2701	MemReqRemap.In.AddrRange.cb = X86_PAGE_SIZE;
2702	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2703	MemReqRemap.In.idDevice = idDevice;
2704	MemReqRemap.In.Pasid = NIL_PCIPASID;
2705	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2706	MemReqRemap.In.enmReqType = enmReqType;
2707	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2708	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2709
2710	for (size_t i = 0; i < cIovas; i++)
2711	{
2712	MemReqRemap.In.AddrRange.uAddr = pauIovas[i] & X86_PAGE_BASE_MASK;
2713	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2714	if (RT_SUCCESS(rc))
2715	{
2716	paGCPhysSpa[i] = MemReqRemap.Out.AddrRange.uAddr \| (pauIovas[i] & X86_PAGE_OFFSET_MASK);
2717	Assert(MemReqRemap.Out.AddrRange.cb == MemReqRemap.In.AddrRange.cb);
2718	}
2719	else
2720	{
2721	LogFlowFunc(("idDevice=%#x uIova=%#RX64 fPerm=%#x rc=%Rrc\n", idDevice, pauIovas[i], fReqPerm, rc));
2722	return rc;
2723	}
2724	}
2725	}
2726	else
2727	{
2728	/* Addresses are forwarded without translation when the translation is disabled. */
2729	for (size_t i = 0; i < cIovas; i++)
2730	paGCPhysSpa[i] = pauIovas[i];
2731	}
2732
2733	return VINF_SUCCESS;
2734	}
2735
2736
2737	/**
2738	* Memory access transaction from a device.
2739	*
2740	* @returns VBox status code.
2741	* @param pDevIns The IOMMU device instance.
2742	* @param idDevice The device ID (bus, device, function).
2743	* @param uIova The I/O virtual address being accessed.
2744	* @param cbIova The size of the access.
2745	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2746	* @param pGCPhysSpa Where to store the translated system physical address.
2747	* @param pcbContiguous Where to store the number of contiguous bytes translated
2748	* and permission-checked.
2749	*
2750	* @thread Any.
2751	*/
2752	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2753	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2754	{
2755	/* Validate. */
2756	AssertPtr(pDevIns);
2757	AssertPtr(pGCPhysSpa);
2758	AssertPtr(pcbContiguous);
2759	Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2760	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2761
2762	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2763	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2764
2765	DMAR_LOCK(pDevIns, pThisCC);
2766	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2767	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2768	DMAR_UNLOCK(pDevIns, pThisCC);
2769
2770	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2771	{
2772	VTDREQTYPE enmReqType;
2773	uint8_t fReqPerm;
2774	dmarDrGetPermAndReqType(pDevIns, fFlags, false /* fBulk */, &enmReqType, &fReqPerm);
2775
2776	DMARMEMREQREMAP MemReqRemap;
2777	RT_ZERO(MemReqRemap);
2778	MemReqRemap.In.AddrRange.uAddr = uIova;
2779	MemReqRemap.In.AddrRange.cb = cbIova;
2780	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2781	MemReqRemap.In.idDevice = idDevice;
2782	MemReqRemap.In.Pasid = NIL_PCIPASID;
2783	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2784	MemReqRemap.In.enmReqType = enmReqType;
2785	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2786	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2787
2788	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2789	*pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2790	*pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2791	return rc;
2792	}
2793
2794	*pGCPhysSpa = uIova;
2795	*pcbContiguous = cbIova;
2796	return VINF_SUCCESS;
2797	}
2798
2799
2800	/**
2801	* Reads an IRTE from guest memory.
2802	*
2803	* @returns VBox status code.
2804	* @param pDevIns The IOMMU device instance.
2805	* @param uIrtaReg The IRTA_REG.
2806	* @param idxIntr The interrupt index.
2807	* @param pIrte Where to store the read IRTE.
2808	*/
2809	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2810	{
2811	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2812
2813	size_t const cbIrte = sizeof(*pIrte);
2814	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2815	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2816	}
2817
2818
2819	/**
2820	* Remaps the source MSI to the destination MSI given the IRTE.
2821	*
2822	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2823	* IRTA_REG.EIME).
2824	* @param pIrte The IRTE used for the remapping.
2825	* @param pMsiIn The source MSI (currently unused).
2826	* @param pMsiOut Where to store the remapped MSI.
2827	*/
2828	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2829	{
2830	NOREF(pMsiIn);
2831	uint64_t const uIrteQword0 = pIrte->au64[0];
2832
2833	/*
2834	* Let's start with a clean slate and preserve unspecified bits if the need arises.
2835	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2836	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2837	* it copies it from the source MSI.
2838	*/
2839	RT_ZERO(*pMsiOut);
2840	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2841	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2842	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2843	if (fExtIntrMode)
2844	{
2845	/*
2846	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2847	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2848	*/
2849	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2850	pMsiOut->Addr.n.u8DestId = idDest;
2851	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2852	}
2853	else
2854	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2855
2856	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2857	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2858	pMsiOut->Data.n.u1Level = 1;
2859	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2860	}
2861
2862
2863	/**
2864	* Handles remapping of interrupts in remappable interrupt format.
2865	*
2866	* @returns VBox status code.
2867	* @param pDevIns The IOMMU device instance.
2868	* @param uIrtaReg The IRTA_REG.
2869	* @param idDevice The device ID (bus, device, function).
2870	* @param pMsiIn The source MSI.
2871	* @param pMsiOut Where to store the remapped MSI.
2872	*/
2873	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2874	{
2875	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2876
2877	/* Validate reserved bits in the interrupt request. */
2878	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2879	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2880	{
2881	/* Compute the index into the interrupt remap table. */
2882	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2883	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2884	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
2885	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2886	uint16_t const idxIntr = fSubHandleValid
2887	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2888	: uHandle;
2889
2890	/* Validate the index. */
2891	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2892	if (idxIntr < cEntries)
2893	{
2894	/** @todo Implement and read IRTE from interrupt-entry cache here. */
2895
2896	/* Read the interrupt remap table entry (IRTE) at the index. */
2897	VTD_IRTE_T Irte;
2898	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2899	if (RT_SUCCESS(rc))
2900	{
2901	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2902	uint64_t const uIrteQword0 = Irte.au64[0];
2903	uint64_t const uIrteQword1 = Irte.au64[1];
2904	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2905	if (fPresent)
2906	{
2907	/* Validate reserved bits in the IRTE. */
2908	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2909	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2910	if ( !(uIrteQword0 & ~fQw0ValidMask)
2911	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2912	{
2913	/* Validate requester id (the device ID) as configured in the IRTE. */
2914	bool fSrcValid;
2915	DMARDIAG enmIrDiag;
2916	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2917	switch (fSvt)
2918	{
2919	case VTD_IRTE_SVT_NONE:
2920	{
2921	fSrcValid = true;
2922	enmIrDiag = kDmarDiag_None;
2923	break;
2924	}
2925
2926	case VTD_IRTE_SVT_VALIDATE_MASK:
2927	{
2928	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2929	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2930	uint16_t const fValidMask = s_afValidMasks[idxMask];
2931	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2932	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2933	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2934	break;
2935	}
2936
2937	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2938	{
2939	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2940	uint8_t const uBusFirst = RT_HI_U8(idSource);
2941	uint8_t const uBusLast = RT_LO_U8(idSource);
2942	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2943	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2944	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2945	break;
2946	}
2947
2948	default:
2949	{
2950	fSrcValid = false;
2951	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2952	break;
2953	}
2954	}
2955
2956	if (fSrcValid)
2957	{
2958	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2959	if (!fPostedMode)
2960	{
2961	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2962	return VINF_SUCCESS;
2963	}
2964	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2965	}
2966	else
2967	dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2968	}
2969	else
2970	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2971	}
2972	else
2973	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2974	}
2975	else
2976	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2977	}
2978	else
2979	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2980	}
2981	else
2982	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr /, NULL / pIrte */);
2983	return VERR_IOMMU_INTR_REMAP_DENIED;
2984	}
2985
2986
2987	/**
2988	* Interrupt remap request from a device.
2989	*
2990	* @returns VBox status code.
2991	* @param pDevIns The IOMMU device instance.
2992	* @param idDevice The device ID (bus, device, function).
2993	* @param pMsiIn The source MSI.
2994	* @param pMsiOut Where to store the remapped MSI.
2995	*/
2996	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2997	{
2998	/* Validate. */
2999	Assert(pDevIns);
3000	Assert(pMsiIn);
3001	Assert(pMsiOut);
3002	RT_NOREF1(idDevice);
3003
3004	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3005	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3006
3007	/* Lock and read all registers required for interrupt remapping up-front. */
3008	DMAR_LOCK(pDevIns, pThisCC);
3009	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3010	uint64_t const uIrtaReg = pThis->uIrtaReg;
3011	DMAR_UNLOCK(pDevIns, pThisCC);
3012
3013	/* Check if interrupt remapping is enabled. */
3014	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
3015	{
3016	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
3017	if (!fIsRemappable)
3018	{
3019	/* Handle compatibility format interrupts. */
3020	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
3021
3022	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
3023	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
3024	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
3025	{
3026	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
3027	return VERR_IOMMU_INTR_REMAP_DENIED;
3028	}
3029
3030	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
3031	pMsiOut = pMsiIn;
3032	return VINF_SUCCESS;
3033	}
3034
3035	/* Handle remappable format interrupts. */
3036	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
3037	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
3038	}
3039
3040	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
3041	pMsiOut = pMsiIn;
3042	return VINF_SUCCESS;
3043	}
3044
3045
3046	/**
3047	* @callback_method_impl{FNIOMMMIONEWWRITE}
3048	*/
3049	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3050	{
3051	RT_NOREF1(pvUser);
3052	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3053
3054	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3055	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
3056
3057	uint16_t const offReg = off;
3058	uint16_t const offLast = offReg + cb - 1;
3059	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3060	{
3061	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3062	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
3063
3064	uint64_t uPrev = 0;
3065	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
3066	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
3067	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3068	switch (off)
3069	{
3070	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
3071	{
3072	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
3073	break;
3074	}
3075
3076	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
3077	case VTD_MMIO_OFF_CCMD_REG + 4:
3078	{
3079	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
3080	break;
3081	}
3082
3083	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
3084	{
3085	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
3086	break;
3087	}
3088
3089	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
3090	{
3091	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
3092	break;
3093	}
3094
3095	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
3096	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
3097	{
3098	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
3099	break;
3100	}
3101
3102	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3103	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
3104	{
3105	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3106	break;
3107	}
3108
3109	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3110	{
3111	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3112	break;
3113	}
3114
3115	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3116	{
3117	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3118	break;
3119	}
3120
3121	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3122	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3123	{
3124	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3125	break;
3126	}
3127	}
3128
3129	DMAR_UNLOCK(pDevIns, pThisCC);
3130	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3131	return rcStrict;
3132	}
3133
3134	return VINF_IOM_MMIO_UNUSED_FF;
3135	}
3136
3137
3138	/**
3139	* @callback_method_impl{FNIOMMMIONEWREAD}
3140	*/
3141	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3142	{
3143	RT_NOREF1(pvUser);
3144	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3145
3146	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3147	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3148
3149	uint16_t const offReg = off;
3150	uint16_t const offLast = offReg + cb - 1;
3151	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3152	{
3153	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3154	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3155
3156	if (cb == 8)
3157	{
3158	(uint64_t )pv = dmarRegRead64(pThis, offReg);
3159	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
3160	}
3161	else
3162	{
3163	(uint32_t )pv = dmarRegRead32(pThis, offReg);
3164	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
3165	}
3166
3167	DMAR_UNLOCK(pDevIns, pThisCC);
3168	return VINF_SUCCESS;
3169	}
3170
3171	return VINF_IOM_MMIO_UNUSED_FF;
3172	}
3173
3174
3175	#ifdef IN_RING3
3176	/**
3177	* Process requests in the invalidation queue.
3178	*
3179	* @param pDevIns The IOMMU device instance.
3180	* @param pvRequests The requests to process.
3181	* @param cbRequests The size of all requests (in bytes).
3182	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3183	* VTD_IQA_REG_DW_256_BIT).
3184	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3185	*/
3186	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3187	uint8_t fTtm)
3188	{
3189	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3190	do \
3191	{ \
3192	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3193	return; \
3194	} while (0)
3195
3196	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3197	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3198
3199	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3200	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3201
3202	/*
3203	* The below check is redundant since we check both TTM and DW for each
3204	* descriptor type we process. However, the order of errors reported by hardware
3205	* may differ hence this is kept commented out but not removed if we need to
3206	* change this in the future.
3207	*
3208	* In our implementation, we would report the descriptor type as invalid,
3209	* while on real hardware it may report descriptor width as invalid.
3210	* The Intel VT-d spec. is not clear which error takes preceedence.
3211	*/
3212	#if 0
3213	/*
3214	* Verify that 128-bit descriptors are not used when operating in scalable mode.
3215	* We don't check this while software writes IQA_REG but defer it until now because
3216	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3217	* -IS- performed when software writes IQA_REG since it only requires checking against
3218	* immutable hardware features.
3219	*/
3220	if ( fTtm != VTD_TTM_SCALABLE_MODE
3221	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
3222	{ /* likely */ }
3223	else
3224	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3225	#endif
3226
3227	/*
3228	* Process requests in FIFO order.
3229	*/
3230	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3231	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3232	{
3233	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
3234	uint64_t const uQword0 = puDscQwords[0];
3235	uint64_t const uQword1 = puDscQwords[1];
3236	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3237	switch (fDscType)
3238	{
3239	case VTD_INV_WAIT_DSC_TYPE:
3240	{
3241	/* Validate descriptor type. */
3242	if ( fTtm == VTD_TTM_LEGACY_MODE
3243	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
3244	{ /* likely */ }
3245	else
3246	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3247
3248	/* Validate reserved bits. */
3249	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3250	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3251	: VTD_INV_WAIT_DSC_0_VALID_MASK;
3252	if ( !(uQword0 & ~fValidMask0)
3253	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3254	{ /* likely */ }
3255	else
3256	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3257
3258	if (fDw == VTD_IQA_REG_DW_256_BIT)
3259	{
3260	if ( !puDscQwords[2]
3261	&& !puDscQwords[3])
3262	{ /* likely */ }
3263	else
3264	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3265	}
3266
3267	/* Perform status write (this must be done prior to generating the completion interrupt). */
3268	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3269	if (fSw)
3270	{
3271	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3272	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3273	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3274	AssertRC(rc);
3275	}
3276
3277	/* Generate invalidation event interrupt. */
3278	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3279	if (fIf)
3280	{
3281	DMAR_LOCK(pDevIns, pThisR3);
3282	dmarR3InvEventRaiseInterrupt(pDevIns);
3283	DMAR_UNLOCK(pDevIns, pThisR3);
3284	}
3285
3286	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3287	break;
3288	}
3289
3290	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3291	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3292	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3293	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3294	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3295	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3296	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3297	default:
3298	{
3299	/* Stop processing further requests. */
3300	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3301	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3302	}
3303	}
3304	}
3305	#undef DMAR_IQE_FAULT_RECORD_RET
3306	}
3307
3308
3309	/**
3310	* The invalidation-queue thread.
3311	*
3312	* @returns VBox status code.
3313	* @param pDevIns The IOMMU device instance.
3314	* @param pThread The command thread.
3315	*/
3316	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3317	{
3318	NOREF(pThread);
3319	LogFlowFunc(("\n"));
3320
3321	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3322	return VINF_SUCCESS;
3323
3324	/*
3325	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3326	* This prevents trashing the heap as well as deal with out-of-memory situations
3327	* up-front while starting the VM. It also simplifies the code from having to
3328	* dynamically grow/shrink the allocation based on how software sizes the queue.
3329	* Guests normally don't alter the queue size all the time, but that's not an
3330	* assumption we can make.
3331	*/
3332	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3333	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3334	void *pvRequests = RTMemAllocZ(cbMaxQs);
3335	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3336
3337	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3338	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3339
3340	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3341	{
3342	/*
3343	* Sleep until we are woken up.
3344	*/
3345	{
3346	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3347	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3348	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3349	break;
3350	}
3351
3352	DMAR_LOCK(pDevIns, pThisR3);
3353	if (dmarInvQueueCanProcessRequests(pThis))
3354	{
3355	uint32_t offQueueHead;
3356	uint32_t offQueueTail;
3357	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3358	if (!fIsEmpty)
3359	{
3360	/*
3361	* Get the current queue size, descriptor width, queue base address and the
3362	* table translation mode while the lock is still held.
3363	*/
3364	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3365	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3366	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3367	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3368	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3369	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3370
3371	/* Paranoia. */
3372	Assert(cbQueue <= cbMaxQs);
3373	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3374	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3375	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
3376	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
3377	Assert(offQueueHead < cbQueue);
3378
3379	/*
3380	* A table translation mode of "reserved" isn't valid for any descriptor type.
3381	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3382	* but if ESRTPS is support, we will perform a global invalidation when software
3383	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3384	* So caching TTM while reading all descriptors should not be a problem.
3385	*
3386	* Also, validate the queue tail offset as it's mutable by software.
3387	*/
3388	if ( fTtm != VTD_TTM_RSVD
3389	&& offQueueTail < cbQueue)
3390	{
3391	/* Don't hold the lock while reading (a potentially large amount of) requests */
3392	DMAR_UNLOCK(pDevIns, pThisR3);
3393
3394	int rc;
3395	uint32_t cbRequests;
3396	if (offQueueTail > offQueueHead)
3397	{
3398	/* The requests have not wrapped around, read them in one go. */
3399	cbRequests = offQueueTail - offQueueHead;
3400	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3401	}
3402	else
3403	{
3404	/* The requests have wrapped around, read forward and wrapped-around. */
3405	uint32_t const cbForward = cbQueue - offQueueHead;
3406	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3407
3408	uint32_t const cbWrapped = offQueueTail;
3409	if ( RT_SUCCESS(rc)
3410	&& cbWrapped > 0)
3411	{
3412	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3413	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3414	}
3415	cbRequests = cbForward + cbWrapped;
3416	}
3417
3418	/* Re-acquire the lock since we need to update device state. */
3419	DMAR_LOCK(pDevIns, pThisR3);
3420
3421	if (RT_SUCCESS(rc))
3422	{
3423	/* Indicate to software we've fetched all requests. */
3424	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3425
3426	/* Don't hold the lock while processing requests. */
3427	DMAR_UNLOCK(pDevIns, pThisR3);
3428
3429	/* Process all requests. */
3430	Assert(cbRequests <= cbQueue);
3431	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3432
3433	/*
3434	* We've processed all requests and the lock shouldn't be held at this point.
3435	* Using 'continue' here allows us to skip re-acquiring the lock just to release
3436	* it again before going back to the thread loop. It's a bit ugly but it certainly
3437	* helps with performance.
3438	*/
3439	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3440	continue;
3441	}
3442	else
3443	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3444	}
3445	else
3446	{
3447	if (fTtm == VTD_TTM_RSVD)
3448	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3449	else
3450	{
3451	Assert(offQueueTail >= cbQueue);
3452	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3453	}
3454	}
3455	}
3456	}
3457	DMAR_UNLOCK(pDevIns, pThisR3);
3458	}
3459
3460	RTMemFree(pvRequests);
3461	pvRequests = NULL;
3462
3463	LogFlowFunc(("Invalidation-queue thread terminating\n"));
3464	return VINF_SUCCESS;
3465	}
3466
3467
3468	/**
3469	* Wakes up the invalidation-queue thread so it can respond to a state
3470	* change.
3471	*
3472	* @returns VBox status code.
3473	* @param pDevIns The IOMMU device instance.
3474	* @param pThread The invalidation-queue thread.
3475	*
3476	* @thread EMT.
3477	*/
3478	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3479	{
3480	RT_NOREF(pThread);
3481	LogFlowFunc(("\n"));
3482	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3483	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3484	}
3485
3486
3487	/**
3488	* @callback_method_impl{FNDBGFHANDLERDEV}
3489	*/
3490	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3491	{
3492	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3493	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3494	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3495
3496	/*
3497	* We lock the device to get a consistent register state as it is
3498	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3499	* ones we care about here) into temporaries and release the lock ASAP.
3500	*
3501	* Order of register being read and outputted is in accordance with the
3502	* spec. for no particular reason.
3503	* See Intel VT-d spec. 10.4 "Register Descriptions".
3504	*/
3505	DMAR_LOCK(pDevIns, pThisR3);
3506
3507	DMARDIAG const enmDiag = pThis->enmDiag;
3508	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3509	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3510	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3511	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3512	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3513	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3514	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3515	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3516	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3517	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3518	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3519	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3520	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3521	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3522	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3523	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3524	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3525	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3526	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3527	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3528	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3529	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3530	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3531	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3532	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3533	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3534	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3535	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3536	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3537	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3538	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3539	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3540	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3541	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3542	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3543	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3544	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3545	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3546
3547	DMAR_UNLOCK(pDevIns, pThisR3);
3548
3549	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3550	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3551	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3552
3553	/*
3554	* Non-verbose output.
3555	*/
3556	if (!fVerbose)
3557	{
3558	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3559	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3560	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3561	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3562	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3563	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3564	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3565	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3566	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3567	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3568	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3569	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3570	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3571	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3572	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3573	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3574	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3575	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3576	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3577	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3578	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3579	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3580	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3581	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3582	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3583	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3584	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3585	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3586	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3587	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3588	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3589	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3590	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3591	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3592	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3593	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3594	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3595	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3596	pHlp->pfnPrintf(pHlp, "\n");
3597	return;
3598	}
3599
3600	/*
3601	* Verbose output.
3602	*/
3603	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3604	{
3605	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3606	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3607	}
3608	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3609	{
3610	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3611	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3612	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3613	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3614	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3615	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3616	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3617	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3618	pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3619	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3620	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3621	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3622	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3623	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3624	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3625	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3626	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3627	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3628	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3629	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3630	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3631	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3632	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3633	}
3634	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3635	{
3636	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3637	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3638	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3639	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3640	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3641	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3642	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3643	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3644	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3645	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3646	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3647	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3648	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3649	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3650	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3651	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3652	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3653	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3654	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3655	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3656	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3657	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3658	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3659	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3660	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3661	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3662	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3663	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3664	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3665	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3666	}
3667	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3668	{
3669	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3670	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3671	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3672	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3673	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3674	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3675	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3676	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3677	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3678	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3679	}
3680	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3681	{
3682	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3683	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3684	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3685	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3686	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3687	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3688	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3689	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3690	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3691	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3692	}
3693	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3694	{
3695	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3696	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3697	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3698	}
3699	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3700	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3701	{
3702	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3703	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3704	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3705	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3706	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3707	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3708	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3709	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3710	}
3711	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3712	{
3713	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3714	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3715	}
3716	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3717	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3718	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3719	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3720	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3721	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3722	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3723	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3724	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3725	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3726	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3727	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3728	{
3729	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3730	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3731	uint8_t const cQueuePages = 1 << fQs;
3732	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3733	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3734	}
3735	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3736	{
3737	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3738	}
3739	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3740	{
3741	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3742	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3743	}
3744	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3745	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3746	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3747	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3748	{
3749	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3750	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3751	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3752	}
3753	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3754	{
3755	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3756	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3757	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3758	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3759	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3760	}
3761	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3762	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3763	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3764	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3765	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3766	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3767	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3768	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3769	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3770	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3771	pHlp->pfnPrintf(pHlp, "\n");
3772	}
3773
3774
3775	/**
3776	* Initializes all registers in the DMAR unit.
3777	*
3778	* @param pDevIns The IOMMU device instance.
3779	*/
3780	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3781	{
3782	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3783	LogFlowFunc(("\n"));
3784
3785	/*
3786	* Wipe all registers (required on reset).
3787	*/
3788	RT_ZERO(pThis->abRegs0);
3789	RT_ZERO(pThis->abRegs1);
3790
3791	/*
3792	* Initialize registers not mutable by software prior to initializing other registers.
3793	*/
3794	/* VER_REG */
3795	{
3796	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3797	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3798	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3799	}
3800
3801	uint8_t const fFlts = 0; /* First-level translation support. */
3802	uint8_t const fSlts = 1; /* Second-level translation support. */
3803	uint8_t const fPt = 1; /* Pass-Through support. */
3804	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3805	uint8_t const fNest = 0; /* Nested translation support. */
3806
3807	/* CAP_REG */
3808	{
3809	uint8_t cGstPhysAddrBits;
3810	uint8_t cGstLinearAddrBits;
3811	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3812
3813	uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3814	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3815	uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3816	uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3817	uint8_t const fSllps = fSl2mp \| (fSl2gp << 1); /* Second-level large page support. */
3818	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3819	: X86_PAGE_2M_SHIFT)
3820	- X86_PAGE_4K_SHIFT;
3821	uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3822	uint8_t const fPsi = 1; /* Page selective invalidation. */
3823	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3824	uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3825	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3826	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3827	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3828	AssertCompile(DMAR_ND <= 6);
3829
3830	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3831	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3832	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3833	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3834	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3835	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3836	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3837	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3838	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3839	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3840	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3841	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3842	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3843	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3844	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3845	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3846	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3847	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3848	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3849	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3850	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3851	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3852
3853	pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3854	pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3855	pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3856	}
3857
3858	/* ECAP_REG */
3859	{
3860	uint8_t const fQi = 1; /* Queued-invalidations. */
3861	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3862	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3863	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3864	uint8_t const fEim = 1; /* Extended interrupt mode.*/
3865	uint8_t const fAdms = 1; /* Abort DMA mode support. */
3866	uint8_t const fErs = 0; /* Execute Request (not supported). */
3867
3868	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3869	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3870	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3871	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3872	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3873	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3874	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3875	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3876	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3877	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3878	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3879	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3880	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3881	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3882	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3883	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3884	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3885	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3886	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3887	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3888	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3889	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3890	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3891	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3892	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3893	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3894	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3895	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3896	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3897	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3898
3899	pThis->fPermValidMask = DMAR_PERM_READ \| DMAR_PERM_WRITE;
3900	if (fErs)
3901	pThis->fPermValidMask = DMAR_PERM_EXE;
3902	}
3903
3904	/*
3905	* Initialize registers mutable by software.
3906	*/
3907	/* FECTL_REG */
3908	{
3909	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3910	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3911	}
3912
3913	/* ICETL_REG */
3914	{
3915	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3916	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3917	}
3918
3919	#ifdef VBOX_STRICT
3920	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3921	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3922	#endif
3923	}
3924
3925
3926	/**
3927	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3928	*/
3929	static DECLCALLBACK(int) dmarR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3930	{
3931	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
3932	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3933	LogFlowFunc(("\n"));
3934
3935	/* First, save software-immutable registers that we validate on state load. */
3936	pHlp->pfnSSMPutU32(pSSM, pThis->uVerReg);
3937	pHlp->pfnSSMPutU64(pSSM, pThis->fCapReg);
3938	pHlp->pfnSSMPutU64(pSSM, pThis->fExtCapReg);
3939
3940	/* Save MMIO registers. */
3941	pHlp->pfnSSMPutU32(pSSM, DMAR_MMIO_GROUP_COUNT);
3942	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs0));
3943	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs0[0], sizeof(pThis->abRegs0));
3944	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs1));
3945	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs1[0], sizeof(pThis->abRegs1));
3946
3947	/* Save lazily activated registers. */
3948	pHlp->pfnSSMPutU64(pSSM, pThis->uIrtaReg);
3949	pHlp->pfnSSMPutU64(pSSM, pThis->uRtaddrReg);
3950
3951	/* Save terminator marker and return status. */
3952	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
3953	}
3954
3955
3956	/**
3957	* @callback_method_impl{FNSSMDEVLOADEXEC}
3958	*/
3959	static DECLCALLBACK(int) dmarR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3960	{
3961	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3962	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3963	int const rcDataErr = VERR_SSM_UNEXPECTED_DATA;
3964	int const rcFmtErr = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3965	LogFlowFunc(("\n"));
3966
3967	/*
3968	* Validate saved-state version.
3969	*/
3970	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
3971	if (uVersion != DMAR_SAVED_STATE_VERSION)
3972	{
3973	LogRel(("%s: Invalid saved-state version %#x\n", DMAR_LOG_PFX, uVersion));
3974	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3975	}
3976
3977	/*
3978	* Load and validate software-immutable registers.
3979	* The features we had exposed to the guest (in the saved state) must be identical
3980	* to what is currently emulated.
3981	*/
3982	{
3983	/* VER_REG */
3984	uint32_t uVerReg;
3985	int rc = pHlp->pfnSSMGetU32(pSSM, &uVerReg);
3986	AssertRCReturn(rc, rc);
3987	AssertLogRelMsgReturn(uVerReg == pThis->uVerReg,
3988	("%s: VER_REG mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, pThis->uVerReg, uVerReg),
3989	rcDataErr);
3990	/* CAP_REG */
3991	uint64_t fCapReg;
3992	pHlp->pfnSSMGetU64(pSSM, &fCapReg);
3993	AssertLogRelMsgReturn(fCapReg == pThis->fCapReg,
3994	("%s: CAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fCapReg, fCapReg),
3995	rcDataErr);
3996	/* ECAP_REG */
3997	uint64_t fExtCapReg;
3998	pHlp->pfnSSMGetU64(pSSM, &fExtCapReg);
3999	AssertLogRelMsgReturn(fExtCapReg == pThis->fExtCapReg,
4000	("%s: ECAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fExtCapReg,
4001	fExtCapReg), rcDataErr);
4002	}
4003
4004	/*
4005	* Load MMIO registers.
4006	*/
4007	{
4008	/* Group count. */
4009	uint32_t cRegGroups;
4010	pHlp->pfnSSMGetU32(pSSM, &cRegGroups);
4011	AssertLogRelMsgReturn(cRegGroups == DMAR_MMIO_GROUP_COUNT,
4012	("%s: MMIO group count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_GROUP_COUNT,
4013	cRegGroups), rcFmtErr);
4014	/* Group 0. */
4015	uint32_t cbRegs0;
4016	pHlp->pfnSSMGetU32(pSSM, &cbRegs0);
4017	AssertLogRelMsgReturn(cbRegs0 == sizeof(pThis->abRegs0),
4018	("%s: MMIO group 0 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs0),
4019	cbRegs0), rcFmtErr);
4020	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs0[0], cbRegs0);
4021	/* Group 1. */
4022	uint32_t cbRegs1;
4023	pHlp->pfnSSMGetU32(pSSM, &cbRegs1);
4024	AssertLogRelMsgReturn(cbRegs1 == sizeof(pThis->abRegs1),
4025	("%s: MMIO group 1 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs1),
4026	cbRegs1), rcFmtErr);
4027	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs1[0], cbRegs1);
4028	}
4029
4030	/*
4031	* Load lazily activated registers.
4032	*/
4033	{
4034	/* Active IRTA_REG. */
4035	pHlp->pfnSSMGetU64(pSSM, &pThis->uIrtaReg);
4036	AssertLogRelMsgReturn(!(pThis->uIrtaReg & ~VTD_IRTA_REG_RW_MASK),
4037	("%s: IRTA_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uIrtaReg), rcDataErr);
4038	/* Active RTADDR_REG. */
4039	pHlp->pfnSSMGetU64(pSSM, &pThis->uRtaddrReg);
4040	AssertLogRelMsgReturn(!(pThis->uRtaddrReg & ~VTD_RTADDR_REG_RW_MASK),
4041	("%s: RTADDR_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uRtaddrReg), rcDataErr);
4042	}
4043
4044	/*
4045	* Verify terminator marker.
4046	*/
4047	{
4048	uint32_t uEndMarker;
4049	int const rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
4050	AssertRCReturn(rc, rc);
4051	AssertLogRelMsgReturn(uEndMarker == UINT32_MAX,
4052	("%s: End marker mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, UINT32_MAX, uEndMarker),
4053	rcFmtErr);
4054	}
4055	return VINF_SUCCESS;
4056	}
4057
4058
4059	/**
4060	* @callback_method_impl{FNSSMDEVLOADDONE}
4061	*/
4062	static DECLCALLBACK(int) dmarR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4063	{
4064	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4065	LogFlowFunc(("\n"));
4066	RT_NOREF(pSSM);
4067	AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
4068
4069	DMAR_LOCK(pDevIns, pThisR3);
4070	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
4071	DMAR_UNLOCK(pDevIns, pThisR3);
4072	return VINF_SUCCESS;
4073	}
4074
4075
4076	/**
4077	* @interface_method_impl{PDMDEVREG,pfnReset}
4078	*/
4079	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
4080	{
4081	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4082	LogFlowFunc(("\n"));
4083
4084	DMAR_LOCK(pDevIns, pThisR3);
4085	dmarR3RegsInit(pDevIns);
4086	DMAR_UNLOCK(pDevIns, pThisR3);
4087	}
4088
4089
4090	/**
4091	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4092	*/
4093	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
4094	{
4095	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4096	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4097	LogFlowFunc(("\n"));
4098
4099	DMAR_LOCK(pDevIns, pThisR3);
4100
4101	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
4102	{
4103	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
4104	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
4105	}
4106
4107	DMAR_UNLOCK(pDevIns, pThisR3);
4108	return VINF_SUCCESS;
4109	}
4110
4111
4112	/**
4113	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4114	*/
4115	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4116	{
4117	RT_NOREF(pCfg);
4118
4119	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4120	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4121	pThisR3->pDevInsR3 = pDevIns;
4122
4123	LogFlowFunc(("iInstance=%d\n", iInstance));
4124	NOREF(iInstance);
4125
4126	/*
4127	* Register the IOMMU with PDM.
4128	*/
4129	PDMIOMMUREGR3 IommuReg;
4130	RT_ZERO(IommuReg);
4131	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4132	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4133	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4134	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4135	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4136	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4137	if (RT_FAILURE(rc))
4138	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4139	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4140	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4141	N_("IOMMU helper version mismatch; got %#x expected %#x"),
4142	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4143	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4144	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4145	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4146	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4147	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
4148	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
4149	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
4150	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
4151
4152	/*
4153	* Use PDM's critical section (via helpers) for the IOMMU device.
4154	*/
4155	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4156	AssertRCReturn(rc, rc);
4157
4158	/*
4159	* Initialize PCI configuration registers.
4160	*/
4161	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4162	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4163
4164	/* Header. */
4165	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4166	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4167	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4168	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4169	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
4170	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
4171	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4172	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4173
4174	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
4175	PDMPciDevSetStatus(pPciDev, 0);
4176	PDMPciDevSetCapabilityList(pPciDev, 0);
4177	/** @todo VTBAR at 0x180? */
4178
4179	/*
4180	* Register the PCI function with PDM.
4181	*/
4182	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4183	AssertLogRelRCReturn(rc, rc);
4184
4185	/*
4186	* Register MMIO region.
4187	*/
4188	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
4189	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
4190	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
4191	&pThis->hMmio);
4192	AssertLogRelRCReturn(rc, rc);
4193
4194	/*
4195	* Register saved state handlers.
4196	*/
4197	rc = PDMDevHlpSSMRegisterEx(pDevIns, DMAR_SAVED_STATE_VERSION, sizeof(DMAR), NULL /* pszBefore */,
4198	NULL /* pfnLivePrep /, NULL / pfnLiveExec /, NULL / pfnLiveVote */,
4199	NULL /* pfnSavePrep /, dmarR3SaveExec, NULL / pfnSaveDone */,
4200	NULL /* pfnLoadPrep */, dmarR3LoadExec, dmarR3LoadDone);
4201	AssertLogRelRCReturn(rc, rc);
4202
4203	/*
4204	* Register debugger info items.
4205	*/
4206	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
4207	AssertLogRelRCReturn(rc, rc);
4208
4209	#ifdef VBOX_WITH_STATISTICS
4210	/*
4211	* Statistics.
4212	*/
4213	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4214	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4215
4216	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4217	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4218
4219	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
4220	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
4221	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
4222	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
4223
4224	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4225	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4226
4227	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4228	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4229
4230	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4231	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4232
4233	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4234	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4235
4236	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
4237	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
4238	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
4239	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
4240	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
4241	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
4242	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
4243	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
4244	#endif
4245
4246	/*
4247	* Initialize registers.
4248	*/
4249	dmarR3RegsInit(pDevIns);
4250
4251	/*
4252	* Create invalidation-queue thread and semaphore.
4253	*/
4254	char szInvQueueThread[32];
4255	RT_ZERO(szInvQueueThread);
4256	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4257	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4258	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4259	AssertLogRelRCReturn(rc, rc);
4260
4261	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4262	AssertLogRelRCReturn(rc, rc);
4263
4264	/*
4265	* Log some of the features exposed to software.
4266	*/
4267	uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4268	uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4269	uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4270	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4271	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4272	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4273	LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4274	DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4275	LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4276	DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4277	pThis->fMgawInvMask, offFrcd, offIva));
4278	return VINF_SUCCESS;
4279	}
4280
4281	#else
4282
4283	/**
4284	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4285	*/
4286	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4287	{
4288	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4289	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4290	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4291	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4292
4293	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
4294	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4295	AssertRCReturn(rc, rc);
4296
4297	/* Set up the MMIO RZ handlers. */
4298	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4299	AssertRCReturn(rc, rc);
4300
4301	/* Set up the IOMMU RZ callbacks. */
4302	PDMIOMMUREGCC IommuReg;
4303	RT_ZERO(IommuReg);
4304	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4305	IommuReg.idxIommu = pThis->idxIommu;
4306	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4307	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4308	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4309	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4310
4311	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4312	AssertRCReturn(rc, rc);
4313	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4314	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4315	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4316	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4317	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4318	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4319	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4320
4321	return VINF_SUCCESS;
4322	}
4323
4324	#endif
4325
4326
4327	/**
4328	* The device registration structure.
4329	*/
4330	PDMDEVREG const g_DeviceIommuIntel =
4331	{
4332	/* .u32Version = */ PDM_DEVREG_VERSION,
4333	/* .uReserved0 = */ 0,
4334	/* .szName = */ "iommu-intel",
4335	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4336	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4337	/* .cMaxInstances = */ 1,
4338	/* .uSharedVersion = */ 42,
4339	/* .cbInstanceShared = */ sizeof(DMAR),
4340	/* .cbInstanceCC = */ sizeof(DMARCC),
4341	/* .cbInstanceRC = */ sizeof(DMARRC),
4342	/* .cMaxPciDevices = */ 1,
4343	/* .cMaxMsixVectors = */ 0,
4344	/* .pszDescription = */ "IOMMU (Intel)",
4345	#if defined(IN_RING3)
4346	/* .pszRCMod = */ "VBoxDDRC.rc",
4347	/* .pszR0Mod = */ "VBoxDDR0.r0",
4348	/* .pfnConstruct = */ iommuIntelR3Construct,
4349	/* .pfnDestruct = */ iommuIntelR3Destruct,
4350	/* .pfnRelocate = */ NULL,
4351	/* .pfnMemSetup = */ NULL,
4352	/* .pfnPowerOn = */ NULL,
4353	/* .pfnReset = */ iommuIntelR3Reset,
4354	/* .pfnSuspend = */ NULL,
4355	/* .pfnResume = */ NULL,
4356	/* .pfnAttach = */ NULL,
4357	/* .pfnDetach = */ NULL,
4358	/* .pfnQueryInterface = */ NULL,
4359	/* .pfnInitComplete = */ NULL,
4360	/* .pfnPowerOff = */ NULL,
4361	/* .pfnSoftReset = */ NULL,
4362	/* .pfnReserved0 = */ NULL,
4363	/* .pfnReserved1 = */ NULL,
4364	/* .pfnReserved2 = */ NULL,
4365	/* .pfnReserved3 = */ NULL,
4366	/* .pfnReserved4 = */ NULL,
4367	/* .pfnReserved5 = */ NULL,
4368	/* .pfnReserved6 = */ NULL,
4369	/* .pfnReserved7 = */ NULL,
4370	#elif defined(IN_RING0)
4371	/* .pfnEarlyConstruct = */ NULL,
4372	/* .pfnConstruct = */ iommuIntelRZConstruct,
4373	/* .pfnDestruct = */ NULL,
4374	/* .pfnFinalDestruct = */ NULL,
4375	/* .pfnRequest = */ NULL,
4376	/* .pfnReserved0 = */ NULL,
4377	/* .pfnReserved1 = */ NULL,
4378	/* .pfnReserved2 = */ NULL,
4379	/* .pfnReserved3 = */ NULL,
4380	/* .pfnReserved4 = */ NULL,
4381	/* .pfnReserved5 = */ NULL,
4382	/* .pfnReserved6 = */ NULL,
4383	/* .pfnReserved7 = */ NULL,
4384	#elif defined(IN_RC)
4385	/* .pfnConstruct = */ iommuIntelRZConstruct,
4386	/* .pfnReserved0 = */ NULL,
4387	/* .pfnReserved1 = */ NULL,
4388	/* .pfnReserved2 = */ NULL,
4389	/* .pfnReserved3 = */ NULL,
4390	/* .pfnReserved4 = */ NULL,
4391	/* .pfnReserved5 = */ NULL,
4392	/* .pfnReserved6 = */ NULL,
4393	/* .pfnReserved7 = */ NULL,
4394	#else
4395	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4396	#endif
4397	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4398	};
4399
4400	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4401

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89637

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