DevIommuIntel.cpp@ 89706

Last change on this file since 89706 was 89668, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Should be enough to save just IVA_REG and FRCD_LO_REG offsets since the other two are adjacent registers (defined by the spec).
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1	/* $Id: DevIommuIntel.cpp 89668 2021-06-14 07:57:12Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <VBox/iommu-intel.h>
27	#include <iprt/mem.h>
28	#include <iprt/string.h>
29
30
31	/*********************************************************************************************************************************
32	* Defined Constants And Macros *
33	*********************************************************************************************************************************/
34	/** Gets the low uint32_t of a uint64_t or something equivalent.
35	*
36	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
37	* used as it asserts for correctness when compiling on certain compilers). */
38	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
39
40	/** Gets the high uint32_t of a uint64_t or something equivalent.
41	*
42	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
43	* used as it asserts for correctness when compiling on certain compilers). */
44	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
45
46	/** Asserts MMIO access' offset and size are valid or returns appropriate error
47	* code suitable for returning from MMIO access handlers. */
48	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
49	do { \
50	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
51	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
52	} while (0)
53
54	/** Checks if the MMIO offset is valid. */
55	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
56	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
57
58	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
59	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
60	do { \
61	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
62	{ /* likely */ } \
63	else \
64	return (a_rcBusy); \
65	} while (0)
66
67	/** Acquires the DMAR lock (not expected to fail). */
68	#ifdef IN_RING3
69	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
70	#else
71	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
72	do { \
73	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
74	AssertRC(rcLock); \
75	} while (0)
76	#endif
77
78	/** Release the DMAR lock. */
79	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
80
81	/** Asserts that the calling thread owns the DMAR lock. */
82	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
83	do { \
84	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
85	RT_NOREF1(a_pThisCC); \
86	} while (0)
87
88	/** Asserts that the calling thread does not own the DMAR lock. */
89	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
90	do { \
91	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
92	RT_NOREF1(a_pThisCC); \
93	} while (0)
94
95	/** The number of fault recording registers our implementation supports.
96	* Normal guest operation shouldn't trigger faults anyway, so we only support the
97	* minimum number of registers (which is 1).
98	*
99	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
100	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
101
102	/** Number of register groups (used in saved states). */
103	#define DMAR_MMIO_GROUP_COUNT 2
104	/** Offset of first register in group 0. */
105	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
106	/** Offset of last register in group 0 (inclusive). */
107	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
108	/** Last valid offset in group 0 (exclusive). */
109	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
110	/** Size of the group 0 (in bytes). */
111	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
112	/** Number of implementation-defined MMIO register offsets - IVA_REG and
113	* FRCD_LO_REG (used in saved state). IOTLB_REG and FRCD_HI_REG are derived from
114	* IVA_REG and FRCD_LO_REG respectively */
115	#define DMAR_MMIO_OFF_IMPL_COUNT 2
116	/** Implementation-specific MMIO offset of IVA_REG (used in saved state). */
117	#define DMAR_MMIO_OFF_IVA_REG 0xe50
118	/** Implementation-specific MMIO offset of IOTLB_REG. */
119	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
120	/** Implementation-specific MMIO offset of FRCD_LO_REG (used in saved state). */
121	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
122	/** Implementation-specific MMIO offset of FRCD_HI_REG. */
123	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
124	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
125	AssertCompile(DMAR_MMIO_OFF_IOTLB_REG == DMAR_MMIO_OFF_IVA_REG + 8);
126	AssertCompile(DMAR_MMIO_OFF_FRCD_HI_REG == DMAR_MMIO_OFF_FRCD_LO_REG + 8);
127
128	/** Offset of first register in group 1. */
129	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
130	/** Offset of last register in group 1 (inclusive). */
131	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
132	/** Last valid offset in group 1 (exclusive). */
133	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
134	/** Size of the group 1 (in bytes). */
135	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
136
137	/** DMAR implementation's major version number (exposed to software).
138	* We report 6 as the major version since we support queued-invalidations as
139	* software may make assumptions based on that.
140	*
141	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
142	#define DMAR_VER_MAJOR 6
143	/** DMAR implementation's minor version number (exposed to software). */
144	#define DMAR_VER_MINOR 0
145
146	/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
147	* 7=Reserved). */
148	#define DMAR_ND 6
149
150	/** @name DMAR_PERM_XXX: DMA request permissions.
151	* The order of R, W, X bits is important as it corresponds to those bits in
152	* page-table entries.
153	*
154	* @{ */
155	/** DMA request permission: Read. */
156	#define DMAR_PERM_READ RT_BIT(0)
157	/** DMA request permission: Write. */
158	#define DMAR_PERM_WRITE RT_BIT(1)
159	/** DMA request permission: Execute (ER). */
160	#define DMAR_PERM_EXE RT_BIT(2)
161	/** DMA request permission: Supervisor privilege (PR). */
162	#define DMAR_PERM_PRIV RT_BIT(3)
163	/** DMA request permissions: All. */
164	#define DMAR_PERM_ALL (DMAR_PERM_READ \| DMAR_PERM_WRITE \| DMAR_PERM_EXE \| DMAR_PERM_PRIV)
165	/** @} */
166
167	/** Release log prefix string. */
168	#define DMAR_LOG_PFX "Intel-IOMMU"
169	/** The current saved state version. */
170	#define DMAR_SAVED_STATE_VERSION 1
171
172
173	/*********************************************************************************************************************************
174	* Structures and Typedefs *
175	*********************************************************************************************************************************/
176	/**
177	* DMAR error diagnostics.
178	* Sorted alphabetically so it's easier to add and locate items, no other reason.
179	*
180	* @note Members of this enum are used as array indices, so no gaps in enum
181	* values are not allowed. Update g_apszDmarDiagDesc when you modify
182	* fields in this enum.
183	*/
184	typedef enum
185	{
186	/* No error, this must be zero! */
187	kDmarDiag_None = 0,
188
189	/* Address Translation Faults. */
190	kDmarDiag_At_Lm_CtxEntry_Not_Present,
191	kDmarDiag_At_Lm_CtxEntry_Read_Failed,
192	kDmarDiag_At_Lm_CtxEntry_Rsvd,
193	kDmarDiag_At_Lm_Pt_At_Block,
194	kDmarDiag_At_Lm_Pt_Aw_Invalid,
195	kDmarDiag_At_Lm_RootEntry_Not_Present,
196	kDmarDiag_At_Lm_RootEntry_Read_Failed,
197	kDmarDiag_At_Lm_RootEntry_Rsvd,
198	kDmarDiag_At_Lm_Tt_Invalid,
199	kDmarDiag_At_Lm_Ut_At_Block,
200	kDmarDiag_At_Lm_Ut_Aw_Invalid,
201	kDmarDiag_At_Rta_Adms_Not_Supported,
202	kDmarDiag_At_Rta_Rsvd,
203	kDmarDiag_At_Rta_Smts_Not_Supported,
204	kDmarDiag_At_Xm_AddrIn_Invalid,
205	kDmarDiag_At_Xm_AddrOut_Invalid,
206	kDmarDiag_At_Xm_Perm_Denied,
207	kDmarDiag_At_Xm_Pte_Rsvd,
208	kDmarDiag_At_Xm_Pte_Sllps_Invalid,
209	kDmarDiag_At_Xm_Read_Pte_Failed,
210	kDmarDiag_At_Xm_Slpptr_Read_Failed,
211
212	/* CCMD_REG faults. */
213	kDmarDiag_CcmdReg_Not_Supported,
214	kDmarDiag_CcmdReg_Qi_Enabled,
215	kDmarDiag_CcmdReg_Ttm_Invalid,
216
217	/* IQA_REG faults. */
218	kDmarDiag_IqaReg_Dsc_Fetch_Error,
219	kDmarDiag_IqaReg_Dw_128_Invalid,
220	kDmarDiag_IqaReg_Dw_256_Invalid,
221
222	/* Invalidation Queue Error Info. */
223	kDmarDiag_Iqei_Dsc_Type_Invalid,
224	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
225	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
226	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
227	kDmarDiag_Iqei_Ttm_Rsvd,
228
229	/* IQT_REG faults. */
230	kDmarDiag_IqtReg_Qt_Invalid,
231	kDmarDiag_IqtReg_Qt_Not_Aligned,
232
233	/* Interrupt Remapping Faults. */
234	kDmarDiag_Ir_Cfi_Blocked,
235	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
236	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
237	kDmarDiag_Ir_Rfi_Irte_Not_Present,
238	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
239	kDmarDiag_Ir_Rfi_Irte_Rsvd,
240	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
241	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
242	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
243	kDmarDiag_Ir_Rfi_Rsvd,
244
245	/* Member for determining array index limit. */
246	kDmarDiag_End,
247
248	/* Usual 32-bit type size hack. */
249	kDmarDiag_32Bit_Hack = 0x7fffffff
250	} DMARDIAG;
251	AssertCompileSize(DMARDIAG, 4);
252
253	/** DMAR diagnostic enum description expansion.
254	* The below construct ensures typos in the input to this macro are caught
255	* during compile time. */
256	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
257
258	/** DMAR diagnostics description for members in DMARDIAG. */
259	static const char *const g_apszDmarDiagDesc[] =
260	{
261	DMARDIAG_DESC(None ),
262
263	/* Address Translation Faults. */
264	DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
265	DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
266	DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
267	DMARDIAG_DESC(At_Lm_Pt_At_Block ),
268	DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
269	DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
270	DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
271	DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
272	DMARDIAG_DESC(At_Lm_Tt_Invalid ),
273	DMARDIAG_DESC(At_Lm_Ut_At_Block ),
274	DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
275	DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
276	DMARDIAG_DESC(At_Rta_Rsvd ),
277	DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
278	DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
279	DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
280	DMARDIAG_DESC(At_Xm_Perm_Denied ),
281	DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
282	DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
283	DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
284	DMARDIAG_DESC(At_Xm_Slpptr_Read_Failed ),
285
286	/* CCMD_REG faults. */
287	DMARDIAG_DESC(CcmdReg_Not_Supported ),
288	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
289	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
290
291	/* IQA_REG faults. */
292	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
293	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
294	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
295
296	/* Invalidation Queue Error Info. */
297	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
298	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
299	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
300	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
301	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
302
303	/* IQT_REG faults. */
304	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
305	DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
306
307	/* Interrupt remapping faults. */
308	DMARDIAG_DESC(Ir_Cfi_Blocked ),
309	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
310	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
311	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
312	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
313	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
314	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
315	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
316	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
317	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
318	/* kDmarDiag_End */
319	};
320	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
321	#undef DMARDIAG_DESC
322
323	/**
324	* The shared DMAR device state.
325	*/
326	typedef struct DMAR
327	{
328	/** IOMMU device index. */
329	uint32_t idxIommu;
330	/** Padding. */
331	uint32_t u32Padding0;
332
333	/** Registers (group 0). */
334	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
335	/** Registers (group 1). */
336	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
337
338	/** @name Lazily activated registers.
339	* These are the active values for lazily activated registers. Software is free to
340	* modify the actual register values while remapping/translation is enabled but they
341	* take effect only when explicitly signaled by software, hence we need to hold the
342	* active values separately.
343	* @{ */
344	/** Currently active IRTA_REG. */
345	uint64_t uIrtaReg;
346	/** Currently active RTADDR_REG. */
347	uint64_t uRtaddrReg;
348	/** @} */
349
350	/** @name Register copies for a tiny bit faster and more convenient access.
351	* @{ */
352	/** Copy of VER_REG. */
353	uint8_t uVerReg;
354	/** Alignment. */
355	uint8_t abPadding0[7];
356	/** Copy of CAP_REG. */
357	uint64_t fCapReg;
358	/** Copy of ECAP_REG. */
359	uint64_t fExtCapReg;
360	/** @} */
361
362	/** Host-address width (HAW) base address mask. */
363	uint64_t fHawBaseMask;
364	/** Maximum guest-address width (MGAW) invalid address mask. */
365	uint64_t fMgawInvMask;
366	/** Maximum supported paging level (3, 4 or 5). */
367	uint8_t cMaxPagingLevel;
368	/** DMA request valid permissions mask. */
369	uint8_t fPermValidMask;
370	/** Alignment. */
371	uint8_t abPadding1[6];
372
373	/** The event semaphore the invalidation-queue thread waits on. */
374	SUPSEMEVENT hEvtInvQueue;
375	/** Error diagnostic. */
376	DMARDIAG enmDiag;
377	/** Padding. */
378	uint32_t uPadding0;
379	/** The MMIO handle. */
380	IOMMMIOHANDLE hMmio;
381
382	#ifdef VBOX_WITH_STATISTICS
383	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
384	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
385	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
386	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
387
388	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
389	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
390	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
391	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
392
393	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
394	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
395	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
396	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
397
398	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
399	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
400	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
401	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
402
403	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
404	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
405	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
406	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
407	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
408	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
409	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
410	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
411	#endif
412	} DMAR;
413	/** Pointer to the DMAR device state. */
414	typedef DMAR *PDMAR;
415	/** Pointer to the const DMAR device state. */
416	typedef DMAR const *PCDMAR;
417	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
418	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
419
420	/**
421	* The ring-3 DMAR device state.
422	*/
423	typedef struct DMARR3
424	{
425	/** Device instance. */
426	PPDMDEVINSR3 pDevInsR3;
427	/** The IOMMU helper. */
428	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
429	/** The invalidation-queue thread. */
430	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
431	} DMARR3;
432	/** Pointer to the ring-3 DMAR device state. */
433	typedef DMARR3 *PDMARR3;
434	/** Pointer to the const ring-3 DMAR device state. */
435	typedef DMARR3 const *PCDMARR3;
436
437	/**
438	* The ring-0 DMAR device state.
439	*/
440	typedef struct DMARR0
441	{
442	/** Device instance. */
443	PPDMDEVINSR0 pDevInsR0;
444	/** The IOMMU helper. */
445	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
446	} DMARR0;
447	/** Pointer to the ring-0 IOMMU device state. */
448	typedef DMARR0 *PDMARR0;
449	/** Pointer to the const ring-0 IOMMU device state. */
450	typedef DMARR0 const *PCDMARR0;
451
452	/**
453	* The raw-mode DMAR device state.
454	*/
455	typedef struct DMARRC
456	{
457	/** Device instance. */
458	PPDMDEVINSRC pDevInsRC;
459	/** The IOMMU helper. */
460	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
461	} DMARRC;
462	/** Pointer to the raw-mode DMAR device state. */
463	typedef DMARRC *PDMARRC;
464	/** Pointer to the const raw-mode DMAR device state. */
465	typedef DMARRC const *PCIDMARRC;
466
467	/** The DMAR device state for the current context. */
468	typedef CTX_SUFF(DMAR) DMARCC;
469	/** Pointer to the DMAR device state for the current context. */
470	typedef CTX_SUFF(PDMAR) PDMARCC;
471	/** Pointer to the const DMAR device state for the current context. */
472	typedef CTX_SUFF(PDMAR) const PCDMARCC;
473
474	/**
475	* DMAR originated events that generate interrupts.
476	*/
477	typedef enum DMAREVENTTYPE
478	{
479	/** Invalidation completion event. */
480	DMAREVENTTYPE_INV_COMPLETE = 0,
481	/** Fault event. */
482	DMAREVENTTYPE_FAULT
483	} DMAREVENTTYPE;
484
485	/**
486	* I/O Page.
487	*/
488	typedef struct DMARIOPAGE
489	{
490	/** The base DMA address of a page. */
491	RTGCPHYS GCPhysBase;
492	/** The page shift. */
493	uint8_t cShift;
494	/** The permissions of this page (DMAR_PERM_XXX). */
495	uint8_t fPerm;
496	} DMARIOPAGE;
497	/** Pointer to an I/O page. */
498	typedef DMARIOPAGE *PDMARIOPAGE;
499	/** Pointer to a const I/O address range. */
500	typedef DMARIOPAGE const *PCDMARIOPAGE;
501
502	/**
503	* I/O Address Range.
504	*/
505	typedef struct DMARIOADDRRANGE
506	{
507	/** The starting DMA address of this range. */
508	uint64_t uAddr;
509	/** The size of the range (in bytes). */
510	size_t cb;
511	/** The permissions of this range (DMAR_PERM_XXX). */
512	uint8_t fPerm;
513	} DMARIOADDRRANGE;
514	/** Pointer to an I/O address range. */
515	typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
516	/** Pointer to a const I/O address range. */
517	typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
518
519	/**
520	* DMA Memory Request (Input).
521	*/
522	typedef struct DMARMEMREQIN
523	{
524	/** The address range being accessed. */
525	DMARIOADDRRANGE AddrRange;
526	/** The source device ID (bus, device, function). */
527	uint16_t idDevice;
528	/** The PASID if present (can be NIL_PCIPASID). */
529	PCIPASID Pasid;
530	/* The address translation type. */
531	PCIADDRTYPE enmAddrType;
532	/** The request type. */
533	VTDREQTYPE enmReqType;
534	} DMARMEMREQIN;
535	/** Pointer to a DMA memory request input. */
536	typedef DMARMEMREQIN *PDMARMEMREQIN;
537	/** Pointer to a const DMA memory input. */
538	typedef DMARMEMREQIN const *PCDMARMEMREQIN;
539
540	/**
541	* DMA Memory Request (Output).
542	*/
543	typedef struct DMARMEMREQOUT
544	{
545	/** The address range of the translated region. */
546	DMARIOADDRRANGE AddrRange;
547	/** The domain ID of the translated region. */
548	uint16_t idDomain;
549	} DMARMEMREQOUT;
550	/** Pointer to a DMA memory request output. */
551	typedef DMARMEMREQOUT *PDMARMEMREQOUT;
552	/** Pointer to a const DMA memory request output. */
553	typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
554
555	/**
556	* DMA Memory Request (Auxiliary Info).
557	* These get updated and used as part of the translation process.
558	*/
559	typedef struct DMARMEMREQAUX
560	{
561	/** The table translation mode (VTD_TTM_XXX). */
562	uint8_t fTtm;
563	/** The fault processing disabled (FPD) bit. */
564	uint8_t fFpd;
565	/** The paging level of the translation. */
566	uint8_t cPagingLevel;
567	uint8_t abPadding[5];
568	/** The address of the first-level page-table. */
569	uint64_t GCPhysFlPt;
570	/** The address of second-level page-table. */
571	uint64_t GCPhysSlPt;
572	} DMARMEMREQAUX;
573	/** Pointer to a DMA memory request output. */
574	typedef DMARMEMREQAUX *PDMARMEMREQAUX;
575	/** Pointer to a const DMA memory request output. */
576	typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
577
578	/**
579	* DMA Memory Request Remapping Information.
580	*/
581	typedef struct DMARMEMREQREMAP
582	{
583	/** The DMA memory request input. */
584	DMARMEMREQIN In;
585	/** DMA memory request auxiliary information. */
586	DMARMEMREQAUX Aux;
587	/** The DMA memory request output. */
588	DMARMEMREQOUT Out;
589	} DMARMEMREQREMAP;
590	/** Pointer to a DMA remap info. */
591	typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
592	/** Pointer to a const DMA remap info. */
593	typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
594
595	/**
596	* Callback function to lookup a DMA address.
597	*
598	* @returns VBox status code.
599	* @param pDevIns The IOMMU device instance.
600	* @param pMemReqIn The DMA memory request input.
601	* @param pMemReqAux The DMA memory request auxiliary info.
602	* @param pIoPageOut Where to store the output of the lookup.
603	*/
604	typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
605	PDMARIOPAGE pIoPageOut));
606	/** Pointer to a DMA address-lookup function. */
607	typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
608
609
610	/*********************************************************************************************************************************
611	* Global Variables *
612	*********************************************************************************************************************************/
613	/**
614	* Read-write masks for DMAR registers (group 0).
615	*/
616	static uint32_t const g_au32RwMasks0[] =
617	{
618	/* Offset Register Low High */
619	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
620	/* 0x004 Reserved */ 0,
621	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
622	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
623	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
624	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
625	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
626	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
627	/* 0x030 Reserved */ 0,
628	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
629	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
630	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
631	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
632	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
633	/* 0x048 Reserved */ 0, 0,
634	/* 0x050 Reserved */ 0, 0,
635	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
636	/* 0x060 Reserved */ 0,
637	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
638	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
639	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
640	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
641	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
642	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
643	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
644	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
645	/* 0x098 Reserved */ 0,
646	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
647	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
648	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
649	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
650	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
651	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
652	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
653	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
654	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
655	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
656	/* 0x0d8 Reserved */ 0,
657	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
658	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
659	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
660	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
661	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
662	/* 0x0f0 Reserved */ 0, 0,
663	/* 0x0f8 Reserved */ 0, 0,
664	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
665	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
666	/* 0x110 Reserved */ 0, 0,
667	/* 0x118 Reserved */ 0, 0,
668	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
669	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
670	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
671	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
672	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
673	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
674	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
675	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
676	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
677	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
678	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
679	/* 0x178 Reserved */ 0, 0,
680	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
681	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
682	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
683	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
684	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
685	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
686	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
687	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
688	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
689	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
690	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
691	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
692	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
693	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
694	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
695	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
696	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
697	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
698	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
699	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
700	};
701	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
702
703	/**
704	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
705	*/
706	static uint32_t const g_au32Rw1cMasks0[] =
707	{
708	/* Offset Register Low High */
709	/* 0x000 VER_REG */ 0,
710	/* 0x004 Reserved */ 0,
711	/* 0x008 CAP_REG */ 0, 0,
712	/* 0x010 ECAP_REG */ 0, 0,
713	/* 0x018 GCMD_REG */ 0,
714	/* 0x01c GSTS_REG */ 0,
715	/* 0x020 RTADDR_REG */ 0, 0,
716	/* 0x028 CCMD_REG */ 0, 0,
717	/* 0x030 Reserved */ 0,
718	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
719	/* 0x038 FECTL_REG */ 0,
720	/* 0x03c FEDATA_REG */ 0,
721	/* 0x040 FEADDR_REG */ 0,
722	/* 0x044 FEUADDR_REG */ 0,
723	/* 0x048 Reserved */ 0, 0,
724	/* 0x050 Reserved */ 0, 0,
725	/* 0x058 AFLOG_REG */ 0, 0,
726	/* 0x060 Reserved */ 0,
727	/* 0x064 PMEN_REG */ 0,
728	/* 0x068 PLMBASE_REG */ 0,
729	/* 0x06c PLMLIMIT_REG */ 0,
730	/* 0x070 PHMBASE_REG */ 0, 0,
731	/* 0x078 PHMLIMIT_REG */ 0, 0,
732	/* 0x080 IQH_REG */ 0, 0,
733	/* 0x088 IQT_REG */ 0, 0,
734	/* 0x090 IQA_REG */ 0, 0,
735	/* 0x098 Reserved */ 0,
736	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
737	/* 0x0a0 IECTL_REG */ 0,
738	/* 0x0a4 IEDATA_REG */ 0,
739	/* 0x0a8 IEADDR_REG */ 0,
740	/* 0x0ac IEUADDR_REG */ 0,
741	/* 0x0b0 IQERCD_REG */ 0, 0,
742	/* 0x0b8 IRTA_REG */ 0, 0,
743	/* 0x0c0 PQH_REG */ 0, 0,
744	/* 0x0c8 PQT_REG */ 0, 0,
745	/* 0x0d0 PQA_REG */ 0, 0,
746	/* 0x0d8 Reserved */ 0,
747	/* 0x0dc PRS_REG */ 0,
748	/* 0x0e0 PECTL_REG */ 0,
749	/* 0x0e4 PEDATA_REG */ 0,
750	/* 0x0e8 PEADDR_REG */ 0,
751	/* 0x0ec PEUADDR_REG */ 0,
752	/* 0x0f0 Reserved */ 0, 0,
753	/* 0x0f8 Reserved */ 0, 0,
754	/* 0x100 MTRRCAP_REG */ 0, 0,
755	/* 0x108 MTRRDEF_REG */ 0, 0,
756	/* 0x110 Reserved */ 0, 0,
757	/* 0x118 Reserved */ 0, 0,
758	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
759	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
760	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
761	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
762	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
763	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
764	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
765	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
766	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
767	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
768	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
769	/* 0x178 Reserved */ 0, 0,
770	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
771	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
772	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
773	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
774	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
775	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
776	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
777	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
778	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
779	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
780	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
781	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
782	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
783	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
784	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
785	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
786	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
787	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
788	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
789	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
790	};
791	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
792
793	/**
794	* Read-write masks for DMAR registers (group 1).
795	*/
796	static uint32_t const g_au32RwMasks1[] =
797	{
798	/* Offset Register Low High */
799	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
800	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
801	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
802	/* 0xe18 VCMDRSVD_REG */ 0, 0,
803	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
804	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
805	/* 0xe30 Reserved */ 0, 0,
806	/* 0xe38 Reserved */ 0, 0,
807	/* 0xe40 Reserved */ 0, 0,
808	/* 0xe48 Reserved */ 0, 0,
809	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
810	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
811	/* 0xe60 Reserved */ 0, 0,
812	/* 0xe68 Reserved */ 0, 0,
813	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
814	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
815	};
816	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
817	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
818
819	/**
820	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
821	*/
822	static uint32_t const g_au32Rw1cMasks1[] =
823	{
824	/* Offset Register Low High */
825	/* 0xe00 VCCAP_REG */ 0, 0,
826	/* 0xe08 VCMD_EO_REG */ 0, 0,
827	/* 0xe10 VCMD_REG */ 0, 0,
828	/* 0xe18 VCMDRSVD_REG */ 0, 0,
829	/* 0xe20 VCRSP_REG */ 0, 0,
830	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
831	/* 0xe30 Reserved */ 0, 0,
832	/* 0xe38 Reserved */ 0, 0,
833	/* 0xe40 Reserved */ 0, 0,
834	/* 0xe48 Reserved */ 0, 0,
835	/* 0xe50 IVA_REG */ 0, 0,
836	/* 0xe58 IOTLB_REG */ 0, 0,
837	/* 0xe60 Reserved */ 0, 0,
838	/* 0xe68 Reserved */ 0, 0,
839	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
840	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
841	};
842	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
843
844	/** Array of RW masks for each register group. */
845	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
846
847	/** Array of RW1C masks for each register group. */
848	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
849
850	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
851	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
852
853	/** Array of valid domain-ID bits. */
854	static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
855	AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
856
857
858	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
859	/**
860	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
861	* guest address width (MGAW).
862	*
863	* @returns The CAP_REG.SAGAW value.
864	* @param uMgaw The CAP_REG.MGAW value.
865	*/
866	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
867	{
868	/*
869	* It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
870	* 5-level paging but not 4 or 3-level paging. So smaller page-table levels
871	* are always OR'ed in below.
872	*
873	* The bit values below (57, 48, 39 bits) represents the levels of page-table walks
874	* for 4KB base page size (5-level, 4-level and 3-level paging respectively).
875	*
876	* See Intel VT-d spec. 10.4.2 "Capability Register".
877	*/
878	++uMgaw;
879	uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1)
880	: uMgaw >= 48 ? RT_BIT(2) \| RT_BIT(1)
881	: uMgaw >= 39 ? RT_BIT(1)
882	: 0;
883	return fSagaw;
884	}
885
886
887	/**
888	* Returns the maximum supported paging level given the supported adjusted
889	* guest-address width (SAGAW) field.
890	*
891	* @returns The highest paging level supported, 0 if invalid.
892	* @param fSagaw The CAP_REG.SAGAW value.
893	*/
894	static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
895	{
896	uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
897	: fSagaw & RT_BIT(2) ? 4
898	: fSagaw & RT_BIT(1) ? 3
899	: 0;
900	return cMaxPagingLevel;
901	}
902
903
904	/**
905	* Returns whether the interrupt remapping (IR) fault is qualified or not.
906	*
907	* @returns @c true if qualified, @c false otherwise.
908	* @param enmIrFault The interrupt remapping fault condition.
909	*/
910	static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
911	{
912	switch (enmIrFault)
913	{
914	case VTDIRFAULT_IRTE_NOT_PRESENT:
915	case VTDIRFAULT_IRTE_PRESENT_RSVD:
916	case VTDIRFAULT_IRTE_PRESENT_INVALID:
917	case VTDIRFAULT_PID_READ_FAILED:
918	case VTDIRFAULT_PID_RSVD:
919	return true;
920	default:
921	return false;
922	}
923	}
924
925
926	/**
927	* Returns table translation mode's descriptive name.
928	*
929	* @returns The descriptive name.
930	* @param uTtm The RTADDR_REG.TTM value.
931	*/
932	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
933	{
934	Assert(!(uTtm & 3));
935	static const char* s_apszTtmNames[] =
936	{
937	"Legacy Mode",
938	"Scalable Mode",
939	"Reserved",
940	"Abort-DMA Mode"
941	};
942	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
943	}
944
945
946	/**
947	* Gets the index of the group the register belongs to given its MMIO offset.
948	*
949	* @returns The group index.
950	* @param offReg The MMIO offset of the register.
951	* @param cbReg The size of the access being made (for bounds checking on
952	* debug builds).
953	*/
954	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
955	{
956	uint16_t const offLast = offReg + cbReg - 1;
957	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
958	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
959	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
960	}
961
962
963	/**
964	* Gets the group the register belongs to given its MMIO offset.
965	*
966	* @returns Pointer to the first element of the register group.
967	* @param pThis The shared DMAR device state.
968	* @param offReg The MMIO offset of the register.
969	* @param cbReg The size of the access being made (for bounds checking on
970	* debug builds).
971	* @param pIdxGroup Where to store the index of the register group the register
972	* belongs to.
973	*/
974	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
975	{
976	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
977	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
978	return apbRegs[*pIdxGroup];
979	}
980
981
982	/**
983	* Const/read-only version of dmarRegGetGroup.
984	*
985	* @copydoc dmarRegGetGroup
986	*/
987	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
988	{
989	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
990	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
991	return apbRegs[*pIdxGroup];
992	}
993
994
995	/**
996	* Writes a 32-bit register with the exactly the supplied value.
997	*
998	* @param pThis The shared DMAR device state.
999	* @param offReg The MMIO offset of the register.
1000	* @param uReg The 32-bit value to write.
1001	*/
1002	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
1003	{
1004	uint8_t idxGroup;
1005	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
1006	NOREF(idxGroup);
1007	(uint32_t )(pabRegs + offReg) = uReg;
1008	}
1009
1010
1011	/**
1012	* Writes a 64-bit register with the exactly the supplied value.
1013	*
1014	* @param pThis The shared DMAR device state.
1015	* @param offReg The MMIO offset of the register.
1016	* @param uReg The 64-bit value to write.
1017	*/
1018	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1019	{
1020	uint8_t idxGroup;
1021	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1022	NOREF(idxGroup);
1023	(uint64_t )(pabRegs + offReg) = uReg;
1024	}
1025
1026
1027	/**
1028	* Reads a 32-bit register with exactly the value it contains.
1029	*
1030	* @returns The raw register value.
1031	* @param pThis The shared DMAR device state.
1032	* @param offReg The MMIO offset of the register.
1033	*/
1034	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1035	{
1036	uint8_t idxGroup;
1037	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1038	NOREF(idxGroup);
1039	return (uint32_t )(pabRegs + offReg);
1040	}
1041
1042
1043	/**
1044	* Reads a 64-bit register with exactly the value it contains.
1045	*
1046	* @returns The raw register value.
1047	* @param pThis The shared DMAR device state.
1048	* @param offReg The MMIO offset of the register.
1049	*/
1050	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1051	{
1052	uint8_t idxGroup;
1053	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1054	NOREF(idxGroup);
1055	return (uint64_t )(pabRegs + offReg);
1056	}
1057
1058
1059	/**
1060	* Reads a 32-bit register with exactly the value it contains along with their
1061	* corresponding masks
1062	*
1063	* @param pThis The shared DMAR device state.
1064	* @param offReg The MMIO offset of the register.
1065	* @param puReg Where to store the raw 32-bit register value.
1066	* @param pfRwMask Where to store the RW mask corresponding to this register.
1067	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1068	*/
1069	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
1070	{
1071	uint8_t idxGroup;
1072	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1073	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1074	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1075	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1076	puReg = (uint32_t *)(pabRegs + offReg);
1077	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
1078	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
1079	}
1080
1081
1082	/**
1083	* Reads a 64-bit register with exactly the value it contains along with their
1084	* corresponding masks.
1085	*
1086	* @param pThis The shared DMAR device state.
1087	* @param offReg The MMIO offset of the register.
1088	* @param puReg Where to store the raw 64-bit register value.
1089	* @param pfRwMask Where to store the RW mask corresponding to this register.
1090	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1091	*/
1092	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
1093	{
1094	uint8_t idxGroup;
1095	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1096	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1097	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1098	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1099	puReg = (uint64_t *)(pabRegs + offReg);
1100	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
1101	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
1102	}
1103
1104
1105	/**
1106	* Writes a 32-bit register as it would be when written by software.
1107	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1108	*
1109	* @returns The value that's actually written to the register.
1110	* @param pThis The shared DMAR device state.
1111	* @param offReg The MMIO offset of the register.
1112	* @param uReg The 32-bit value to write.
1113	* @param puPrev Where to store the register value prior to writing.
1114	*/
1115	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1116	{
1117	/* Read current value from the 32-bit register. */
1118	uint32_t uCurReg;
1119	uint32_t fRwMask;
1120	uint32_t fRw1cMask;
1121	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1122	*puPrev = uCurReg;
1123
1124	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1125	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1126	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1127	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1128
1129	/* Write new value to the 32-bit register. */
1130	dmarRegWriteRaw32(pThis, offReg, uNewReg);
1131	return uNewReg;
1132	}
1133
1134
1135	/**
1136	* Writes a 64-bit register as it would be when written by software.
1137	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1138	*
1139	* @returns The value that's actually written to the register.
1140	* @param pThis The shared DMAR device state.
1141	* @param offReg The MMIO offset of the register.
1142	* @param uReg The 64-bit value to write.
1143	* @param puPrev Where to store the register value prior to writing.
1144	*/
1145	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1146	{
1147	/* Read current value from the 64-bit register. */
1148	uint64_t uCurReg;
1149	uint64_t fRwMask;
1150	uint64_t fRw1cMask;
1151	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1152	*puPrev = uCurReg;
1153
1154	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1155	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1156	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1157	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1158
1159	/* Write new value to the 64-bit register. */
1160	dmarRegWriteRaw64(pThis, offReg, uNewReg);
1161	return uNewReg;
1162	}
1163
1164
1165	/**
1166	* Reads a 32-bit register as it would be when read by software.
1167	*
1168	* @returns The register value.
1169	* @param pThis The shared DMAR device state.
1170	* @param offReg The MMIO offset of the register.
1171	*/
1172	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1173	{
1174	return dmarRegReadRaw32(pThis, offReg);
1175	}
1176
1177
1178	/**
1179	* Reads a 64-bit register as it would be when read by software.
1180	*
1181	* @returns The register value.
1182	* @param pThis The shared DMAR device state.
1183	* @param offReg The MMIO offset of the register.
1184	*/
1185	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1186	{
1187	return dmarRegReadRaw64(pThis, offReg);
1188	}
1189
1190
1191	/**
1192	* Modifies a 32-bit register.
1193	*
1194	* @param pThis The shared DMAR device state.
1195	* @param offReg The MMIO offset of the register.
1196	* @param fAndMask The AND mask (applied first).
1197	* @param fOrMask The OR mask.
1198	* @remarks This does NOT apply RO or RW1C masks while modifying the
1199	* register.
1200	*/
1201	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1202	{
1203	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1204	uReg = (uReg & fAndMask) \| fOrMask;
1205	dmarRegWriteRaw32(pThis, offReg, uReg);
1206	}
1207
1208
1209	/**
1210	* Modifies a 64-bit register.
1211	*
1212	* @param pThis The shared DMAR device state.
1213	* @param offReg The MMIO offset of the register.
1214	* @param fAndMask The AND mask (applied first).
1215	* @param fOrMask The OR mask.
1216	* @remarks This does NOT apply RO or RW1C masks while modifying the
1217	* register.
1218	*/
1219	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1220	{
1221	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1222	uReg = (uReg & fAndMask) \| fOrMask;
1223	dmarRegWriteRaw64(pThis, offReg, uReg);
1224	}
1225
1226
1227	/**
1228	* Checks if the invalidation-queue is empty.
1229	*
1230	* Extended version which optionally returns the current queue head and tail
1231	* offsets.
1232	*
1233	* @returns @c true if empty, @c false otherwise.
1234	* @param pThis The shared DMAR device state.
1235	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
1236	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1237	*/
1238	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
1239	{
1240	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1241	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1242	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1243
1244	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1245	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1246	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1247	if (poffQh)
1248	*poffQh = uIqhReg;
1249	if (poffQt)
1250	*poffQt = uIqtReg;
1251	return uIqtReg == uIqhReg;
1252	}
1253
1254
1255	/**
1256	* Checks if the invalidation-queue is empty.
1257	*
1258	* @returns @c true if empty, @c false otherwise.
1259	* @param pThis The shared DMAR device state.
1260	*/
1261	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1262	{
1263	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1264	}
1265
1266
1267	/**
1268	* Checks if the invalidation-queue is capable of processing requests.
1269	*
1270	* @returns @c true if the invalidation-queue can process requests, @c false
1271	* otherwise.
1272	* @param pThis The shared DMAR device state.
1273	*/
1274	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1275	{
1276	/* Check if queued-invalidation is enabled. */
1277	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1278	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1279	{
1280	/* Check if there are no invalidation-queue or timeout errors. */
1281	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1282	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1283	return true;
1284	}
1285	return false;
1286	}
1287
1288
1289	/**
1290	* Wakes up the invalidation-queue thread if there are requests to be processed.
1291	*
1292	* @param pDevIns The IOMMU device instance.
1293	*/
1294	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1295	{
1296	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1297	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1298	LogFlowFunc(("\n"));
1299
1300	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1301
1302	if ( dmarInvQueueCanProcessRequests(pThis)
1303	&& !dmarInvQueueIsEmpty(pThis))
1304	{
1305	Log4Func(("Signaling the invalidation-queue thread\n"));
1306	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1307	}
1308	}
1309
1310
1311	/**
1312	* Raises an event on behalf of the DMAR.
1313	*
1314	* These are events that are generated by the DMAR itself (like faults and
1315	* invalidation completion notifications).
1316	*
1317	* @param pDevIns The IOMMU device instance.
1318	* @param enmEventType The DMAR event type.
1319	*
1320	* @remarks The DMAR lock must be held while calling this function.
1321	*/
1322	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1323	{
1324	uint16_t offCtlReg;
1325	uint32_t fIntrMaskedMask;
1326	uint32_t fIntrPendingMask;
1327	uint16_t offMsiAddrLoReg;
1328	uint16_t offMsiAddrHiReg;
1329	uint16_t offMsiDataReg;
1330	switch (enmEventType)
1331	{
1332	case DMAREVENTTYPE_INV_COMPLETE:
1333	{
1334	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1335	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1336	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1337	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1338	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1339	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1340	break;
1341	}
1342
1343	case DMAREVENTTYPE_FAULT:
1344	{
1345	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1346	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1347	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1348	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1349	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1350	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1351	break;
1352	}
1353
1354	default:
1355	{
1356	/* Shouldn't ever happen. */
1357	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1358	}
1359	}
1360
1361	/* Check if software has masked the interrupt. */
1362	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1363	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1364	if (!(uCtlReg & fIntrMaskedMask))
1365	{
1366	/*
1367	* Interrupt is unmasked, raise it.
1368	* Interrupts generated by the DMAR have trigger mode and level as 0.
1369	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1370	*/
1371	MSIMSG Msi;
1372	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1373	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1374	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1375	Assert(Msi.Data.n.u1Level == 0);
1376	Assert(Msi.Data.n.u1TriggerMode == 0);
1377
1378	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1379	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1380
1381	/* Clear interrupt pending bit. */
1382	uCtlReg &= ~fIntrPendingMask;
1383	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1384	}
1385	else
1386	{
1387	/* Interrupt is masked, set the interrupt pending bit. */
1388	uCtlReg \|= fIntrPendingMask;
1389	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1390	}
1391	}
1392
1393
1394	/**
1395	* Raises an interrupt in response to a fault event.
1396	*
1397	* @param pDevIns The IOMMU device instance.
1398	*
1399	* @remarks This assumes the caller has already set the required status bits in the
1400	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1401	*/
1402	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1403	{
1404	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1405	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1406	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1407
1408	#ifdef RT_STRICT
1409	{
1410	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1411	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1412	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1413	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1414	\| VTD_BF_FSTS_REG_IQE_MASK;
1415	Assert(uFstsReg & fFaultMask);
1416	}
1417	#endif
1418	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1419	}
1420
1421
1422	#ifdef IN_RING3
1423	/**
1424	* Raises an interrupt in response to an invalidation (complete) event.
1425	*
1426	* @param pDevIns The IOMMU device instance.
1427	*/
1428	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1429	{
1430	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1431	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1432	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1433
1434	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1435	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1436	{
1437	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1438	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1439	}
1440	}
1441	#endif /* IN_RING3 */
1442
1443
1444	/**
1445	* Checks if a primary fault can be recorded.
1446	*
1447	* @returns @c true if the fault can be recorded, @c false otherwise.
1448	* @param pDevIns The IOMMU device instance.
1449	* @param pThis The shared DMAR device state.
1450	*
1451	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1452	* NOT call it unless there is a fault condition!
1453	*/
1454	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1455	{
1456	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1457	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1458
1459	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1460	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1461	return false;
1462
1463	/*
1464	* If we add more FRCD registers, we'll have to loop through them here.
1465	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1466	* nor do we need to increment FRI.
1467	*
1468	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1469	*/
1470	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1471	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1472	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1473	{
1474	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1475	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1476	return false;
1477	}
1478
1479	return true;
1480	}
1481
1482
1483	/**
1484	* Records a primary fault.
1485	*
1486	* @param pDevIns The IOMMU device instance.
1487	* @param uFrcdHi The FRCD_HI_REG value for this fault.
1488	* @param uFrcdLo The FRCD_LO_REG value for this fault.
1489	*/
1490	static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1491	{
1492	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1493	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1494
1495	DMAR_LOCK(pDevIns, pThisCC);
1496
1497	/* We don't support advance fault logging. */
1498	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1499
1500	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1501	{
1502	/* Update the fault recording registers with the fault information. */
1503	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1504	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1505
1506	/* Set the Pending Primary Fault (PPF) field in the status register. */
1507	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1508
1509	/* Raise interrupt if necessary. */
1510	dmarFaultEventRaiseInterrupt(pDevIns);
1511	}
1512
1513	DMAR_UNLOCK(pDevIns, pThisCC);
1514	}
1515
1516
1517	/**
1518	* Records an interrupt request fault.
1519	*
1520	* @param pDevIns The IOMMU device instance.
1521	* @param enmDiag The diagnostic reason.
1522	* @param idDevice The device ID (bus, device, function).
1523	* @param idxIntr The interrupt index.
1524	* @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1525	* not qualified.
1526	*/
1527	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1528	{
1529	/*
1530	* Update the diagnostic reason (even if software wants to supress faults).
1531	*/
1532	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1533	pThis->enmDiag = enmDiag;
1534
1535	/*
1536	* Figure out the fault reason to report to software from our diagnostic code.
1537	* The case labels below are sorted alphabetically for convenience.
1538	*/
1539	VTDIRFAULT enmIrFault;
1540	switch (enmDiag)
1541	{
1542	case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1543	case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1544	case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1545	case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1546	case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1547	case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1548	case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1549	case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1550	case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1551	case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1552
1553	/* Shouldn't ever happen. */
1554	default:
1555	{
1556	AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1557	enmDiag));
1558	}
1559	}
1560
1561	/*
1562	* Qualified faults are those that can be suppressed by software using the FPD bit
1563	* in the interrupt-remapping table entry.
1564	*/
1565	bool fFpd;
1566	bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1567	if (fQualifiedFault)
1568	{
1569	AssertReturnVoid(pIrte);
1570	fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1571	}
1572	else
1573	fFpd = false;
1574
1575	if (!fFpd)
1576	{
1577	/* Construct and record the error. */
1578	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1579	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1580	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1581	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1582	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1583	}
1584	}
1585
1586
1587	/**
1588	* Records an address translation fault.
1589	*
1590	* @param pDevIns The IOMMU device instance.
1591	* @param enmDiag The diagnostic reason.
1592	* @param pMemReqIn The DMA memory request input.
1593	* @param pMemReqAux The DMA memory request auxiliary info.
1594	*/
1595	static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1596	{
1597	/*
1598	* Update the diagnostic reason (even if software wants to supress faults).
1599	*/
1600	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1601	pThis->enmDiag = enmDiag;
1602
1603	/*
1604	* Qualified faults are those that can be suppressed by software using the FPD bit
1605	* in the context entry, scalable-mode context entry etc.
1606	*/
1607	if (!pMemReqAux->fFpd)
1608	{
1609	/*
1610	* Figure out the fault reason to report to software from our diagnostic code.
1611	* The case labels below are sorted alphabetically for convenience.
1612	*/
1613	VTDATFAULT enmAtFault;
1614	bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1615	switch (enmDiag)
1616	{
1617	/* LM (Legacy Mode) faults. */
1618	case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1619	case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1620	case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1621	case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1622	case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1623	case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1624	case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1625	case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1626	case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1627	case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1628	case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1629
1630	/* RTA (Root Table Address) faults. */
1631	case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1632	case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1633	case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1634
1635	/* XM (Legacy mode or Scalable Mode) faults. */
1636	case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1637	case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1638	case kDmarDiag_At_Xm_Perm_Denied: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1639	case kDmarDiag_At_Xm_Pte_Rsvd:
1640	case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1641	case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1642	case kDmarDiag_At_Xm_Slpptr_Read_Failed: enmAtFault = fLm ? VTDATFAULT_LCT_4_3 : VTDATFAULT_SSL_4; break;
1643
1644	/* Shouldn't ever happen. */
1645	default:
1646	{
1647	AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1648	DMAR_LOG_PFX, enmDiag));
1649	}
1650	}
1651
1652	/* Construct and record the error. */
1653	uint16_t const idDevice = pMemReqIn->idDevice;
1654	uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1655	uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1656	uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1657	uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1658	bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1659	uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1660	PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1661
1662	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1663	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1664	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1665	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1666	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1667	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1668	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1669	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1670	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1671	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1672	uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1673	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1674	}
1675	}
1676
1677
1678	/**
1679	* Records an IQE fault.
1680	*
1681	* @param pDevIns The IOMMU device instance.
1682	* @param enmIqei The IQE information.
1683	* @param enmDiag The diagnostic reason.
1684	*/
1685	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1686	{
1687	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1688	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1689
1690	DMAR_LOCK(pDevIns, pThisCC);
1691
1692	/* Update the diagnostic reason. */
1693	pThis->enmDiag = enmDiag;
1694
1695	/* Set the error bit. */
1696	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1697	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1698
1699	/* Set the error information. */
1700	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1701	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1702
1703	dmarFaultEventRaiseInterrupt(pDevIns);
1704
1705	DMAR_UNLOCK(pDevIns, pThisCC);
1706	}
1707
1708
1709	/**
1710	* Handles writes to GCMD_REG.
1711	*
1712	* @returns Strict VBox status code.
1713	* @param pDevIns The IOMMU device instance.
1714	* @param uGcmdReg The value written to GCMD_REG.
1715	*/
1716	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1717	{
1718	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1719	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1720	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1721	uint64_t const fExtCapReg = pThis->fExtCapReg;
1722
1723	/* Queued-invalidation. */
1724	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1725	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1726	{
1727	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1728	{
1729	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1730	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1731	}
1732	else
1733	{
1734	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1735	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1736	}
1737	}
1738
1739	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1740	{
1741	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1742	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1743	{
1744	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1745	* supported. */
1746	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1747	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1748	}
1749
1750	/* Interrupt remapping. */
1751	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1752	{
1753	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1754	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1755	else
1756	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1757	}
1758
1759	/* Compatibility format interrupts. */
1760	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1761	{
1762	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1763	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1764	else
1765	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1766	}
1767	}
1768
1769	/* Set Root Table Pointer (SRTP). */
1770	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1771	{
1772	/** @todo Perform global invalidation of all remapping translation caches when
1773	* ESRTPS is supported. */
1774	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1775	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1776	}
1777
1778	/* Translation (DMA remapping). */
1779	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1780	{
1781	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1782	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1783	else
1784	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1785	}
1786
1787	return VINF_SUCCESS;
1788	}
1789
1790
1791	/**
1792	* Handles writes to CCMD_REG.
1793	*
1794	* @returns Strict VBox status code.
1795	* @param pDevIns The IOMMU device instance.
1796	* @param offReg The MMIO register offset.
1797	* @param cbReg The size of the MMIO access (in bytes).
1798	* @param uCcmdReg The value written to CCMD_REG.
1799	*/
1800	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1801	{
1802	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1803	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1804	{
1805	/* Check if we need to invalidate the context-context. */
1806	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1807	if (fIcc)
1808	{
1809	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1810	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1811	if (uMajorVersion < 6)
1812	{
1813	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1814	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1815	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1816	{
1817	/* Verify table translation mode is legacy. */
1818	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1819	if (fTtm == VTD_TTM_LEGACY_MODE)
1820	{
1821	/** @todo Invalidate. */
1822	return VINF_SUCCESS;
1823	}
1824	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1825	}
1826	else
1827	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1828	}
1829	else
1830	pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1831	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1832	}
1833	}
1834	return VINF_SUCCESS;
1835	}
1836
1837
1838	/**
1839	* Handles writes to FECTL_REG.
1840	*
1841	* @returns Strict VBox status code.
1842	* @param pDevIns The IOMMU device instance.
1843	* @param uFectlReg The value written to FECTL_REG.
1844	*/
1845	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1846	{
1847	/*
1848	* If software unmasks the interrupt when the interrupt is pending, we must raise
1849	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1850	*/
1851	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1852	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1853	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1854	return VINF_SUCCESS;
1855	}
1856
1857
1858	/**
1859	* Handles writes to FSTS_REG.
1860	*
1861	* @returns Strict VBox status code.
1862	* @param pDevIns The IOMMU device instance.
1863	* @param uFstsReg The value written to FSTS_REG.
1864	* @param uPrev The value in FSTS_REG prior to writing it.
1865	*/
1866	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1867	{
1868	/*
1869	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1870	* the interrupt pending (IP) bit must be cleared.
1871	*
1872	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1873	*/
1874	uint32_t const fChanged = uPrev ^ uFstsReg;
1875	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1876	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1877	{
1878	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1879	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1880	}
1881	return VINF_SUCCESS;
1882	}
1883
1884
1885	/**
1886	* Handles writes to IQT_REG.
1887	*
1888	* @returns Strict VBox status code.
1889	* @param pDevIns The IOMMU device instance.
1890	* @param offReg The MMIO register offset.
1891	* @param uIqtReg The value written to IQT_REG.
1892	*/
1893	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1894	{
1895	/* We only care about the low 32-bits, high 32-bits are reserved. */
1896	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1897	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1898
1899	/* Paranoia. */
1900	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1901
1902	uint32_t const offQt = uIqtReg;
1903	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1904	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1905
1906	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1907	if ( fDw != VTD_IQA_REG_DW_256_BIT
1908	\|\| !(offQt & RT_BIT(4)))
1909	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1910	else
1911	{
1912	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1913	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1914	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1915	}
1916	return VINF_SUCCESS;
1917	}
1918
1919
1920	/**
1921	* Handles writes to IQA_REG.
1922	*
1923	* @returns Strict VBox status code.
1924	* @param pDevIns The IOMMU device instance.
1925	* @param offReg The MMIO register offset.
1926	* @param uIqaReg The value written to IQA_REG.
1927	*/
1928	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1929	{
1930	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1931	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1932
1933	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1934	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1935	* cannot happen or that it's ignored when it does happen. */
1936
1937	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1938	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1939	if (fDw == VTD_IQA_REG_DW_256_BIT)
1940	{
1941	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1942	if (fSupports256BitDw)
1943	{ /* likely */ }
1944	else
1945	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1946	}
1947	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1948
1949	return VINF_SUCCESS;
1950	}
1951
1952
1953	/**
1954	* Handles writes to ICS_REG.
1955	*
1956	* @returns Strict VBox status code.
1957	* @param pDevIns The IOMMU device instance.
1958	* @param uIcsReg The value written to ICS_REG.
1959	*/
1960	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1961	{
1962	/*
1963	* If the IP field is set when software services the interrupt condition,
1964	* (by clearing the IWC field), the IP field must be cleared.
1965	*/
1966	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1967	{
1968	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1969	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1970	}
1971	return VINF_SUCCESS;
1972	}
1973
1974
1975	/**
1976	* Handles writes to IECTL_REG.
1977	*
1978	* @returns Strict VBox status code.
1979	* @param pDevIns The IOMMU device instance.
1980	* @param uIectlReg The value written to IECTL_REG.
1981	*/
1982	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1983	{
1984	/*
1985	* If software unmasks the interrupt when the interrupt is pending, we must raise
1986	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1987	*/
1988	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1989	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1990	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1991	return VINF_SUCCESS;
1992	}
1993
1994
1995	/**
1996	* Handles writes to FRCD_REG (High 64-bits).
1997	*
1998	* @returns Strict VBox status code.
1999	* @param pDevIns The IOMMU device instance.
2000	* @param offReg The MMIO register offset.
2001	* @param cbReg The size of the MMIO access (in bytes).
2002	* @param uFrcdHiReg The value written to FRCD_REG.
2003	* @param uPrev The value in FRCD_REG prior to writing it.
2004	*/
2005	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
2006	{
2007	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
2008	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
2009	{
2010	/*
2011	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
2012	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
2013	* has only 1 FRCD register.
2014	*
2015	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
2016	*/
2017	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2018	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2019	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2020	{
2021	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2022	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2023	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2024	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2025	}
2026	}
2027	return VINF_SUCCESS;
2028	}
2029
2030
2031	/**
2032	* Performs a PCI target abort for a DMA remapping (DR) operation.
2033	*
2034	* @param pDevIns The IOMMU device instance.
2035	*/
2036	static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2037	{
2038	/** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2039	* as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2040	* who knows. */
2041	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2042	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2043	PDMPciDevSetStatus(pPciDev, u16Status);
2044	}
2045
2046
2047	/**
2048	* Checks whether the address width (AW) is supported by our hardware
2049	* implementation for legacy mode address translation.
2050	*
2051	* @returns @c true if it's supported, @c false otherwise.
2052	* @param pThis The shared DMAR device state.
2053	* @param pCtxEntry The context entry.
2054	* @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2055	*/
2056	static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2057	{
2058	uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2059	uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2060	uint8_t const fAwMask = RT_BIT(fAw);
2061	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2062	Assert(!(fSagaw & ~(RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3))));
2063
2064	uint8_t const cPagingLevel = fAw + 2;
2065	if (pcPagingLevel)
2066	*pcPagingLevel = cPagingLevel;
2067
2068	/* With pass-through, the address width must be the largest AGAW supported by hardware. */
2069	if (fTt == VTD_TT_UNTRANSLATED_PT)
2070	{
2071	Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2072	return cPagingLevel == pThis->cMaxPagingLevel;
2073	}
2074
2075	/* The address width must be any of the ones supported by hardware. */
2076	if (fAw < 4)
2077	return (fSagaw & fAwMask) != 0;
2078
2079	return false;
2080	}
2081
2082
2083	/**
2084	* Reads a root entry from guest memory.
2085	*
2086	* @returns VBox status code.
2087	* @param pDevIns The IOMMU device instance.
2088	* @param uRtaddrReg The current RTADDR_REG value.
2089	* @param idxRootEntry The index of the root entry to read.
2090	* @param pRootEntry Where to store the read root entry.
2091	*/
2092	static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2093	{
2094	size_t const cbRootEntry = sizeof(*pRootEntry);
2095	RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2096	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2097	}
2098
2099
2100	/**
2101	* Reads a context entry from guest memory.
2102	*
2103	* @returns VBox status code.
2104	* @param pDevIns The IOMMU device instance.
2105	* @param GCPhysCtxTable The physical address of the context table.
2106	* @param idxCtxEntry The index of the context entry to read.
2107	* @param pCtxEntry Where to store the read context entry.
2108	*/
2109	static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2110	{
2111	/* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2112	size_t const cbCtxEntry = sizeof(*pCtxEntry);
2113	RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2114	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2115	}
2116
2117
2118	/**
2119	* Validates and updates the output I/O page of a translation.
2120	*
2121	* @returns VBox status code.
2122	* @param pDevIns The IOMMU device instance.
2123	* @param GCPhysBase The output address of the translation.
2124	* @param cShift The page shift of the translated address.
2125	* @param fPerm The permissions granted for the translated region.
2126	* @param pMemReqIn The DMA memory request input.
2127	* @param pMemReqAux The DMA memory request auxiliary info.
2128	* @param pIoPageOut Where to store the output of the translation.
2129	*/
2130	static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2131	PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2132	{
2133	Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2134
2135	/* Ensure the output address is not in the interrupt address range. */
2136	if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2137	{
2138	pIoPageOut->GCPhysBase = GCPhysBase;
2139	pIoPageOut->cShift = cShift;
2140	pIoPageOut->fPerm = fPerm;
2141	return VINF_SUCCESS;
2142	}
2143
2144	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2145	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2146	}
2147
2148
2149	/**
2150	* Performs second level translation by walking the I/O page tables.
2151	*
2152	* This is a DMA address-lookup callback function which performs the translation
2153	* (and access control) as part of the lookup.
2154	*
2155	* @returns VBox status code.
2156	* @param pDevIns The IOMMU device instance.
2157	* @param pMemReqIn The DMA memory request input.
2158	* @param pMemReqAux The DMA memory request auxiliary info.
2159	* @param pIoPageOut Where to store the output of the translation.
2160	*/
2161	static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2162	PDMARIOPAGE pIoPageOut)
2163	{
2164	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2165
2166	/* Sanity. */
2167	Assert(pIoPageOut);
2168	Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ \| DMAR_PERM_WRITE));
2169	Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2170	\|\| pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2171	Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
2172
2173	/* Mask of valid paging entry bits. */
2174	static uint64_t const s_auPtEntityRsvd[] = { VTD_SL_PTE_VALID_MASK,
2175	VTD_SL_PDE_VALID_MASK,
2176	VTD_SL_PDPE_VALID_MASK,
2177	VTD_SL_PML4E_VALID_MASK,
2178	VTD_SL_PML5E_VALID_MASK };
2179
2180	/* Paranoia. */
2181	Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2182	AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == 5);
2183
2184	/* Second-level translations restricts input address to an implementation-specific MGAW. */
2185	uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2186	if (!(uAddrIn & pThis->fMgawInvMask))
2187	{ /* likely */ }
2188	else
2189	{
2190	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2191	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2192	}
2193
2194	/*
2195	* Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2196	* Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2197	*/
2198	uint64_t uPtEntity = pMemReqAux->GCPhysSlPt;
2199	for (int8_t idxLevel = pMemReqAux->cPagingLevel - 1; idxLevel >= 0; idxLevel--)
2200	{
2201	/*
2202	* Read the paging entry for the current level.
2203	*/
2204	uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
2205	{
2206	uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2207	uint16_t const offPte = idxPte << 3;
2208	RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) \| offPte;
2209	int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2210	if (RT_SUCCESS(rc))
2211	{ /* likely */ }
2212	else
2213	{
2214	if ((GCPhysPtEntity & X86_PAGE_BASE_MASK) == pMemReqAux->GCPhysSlPt)
2215	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2216	else
2217	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2218	break;
2219	}
2220	}
2221
2222	/*
2223	* Check I/O permissions.
2224	* This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2225	* See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2226	*/
2227	uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2228	uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2229	Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2230	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK)); /* No Second-level access/dirty support. */
2231	if ((fPtPerm & fReqPerm) == fReqPerm)
2232	{ /* likely */ }
2233	else
2234	{
2235	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Denied, pMemReqIn, pMemReqAux);
2236	break;
2237	}
2238
2239	/*
2240	* Validate reserved bits of the current paging entry.
2241	*/
2242	if (!(uPtEntity & ~s_auPtEntityRsvd[idxLevel]))
2243	{ /* likely */ }
2244	else
2245	{
2246	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2247	break;
2248	}
2249
2250	/*
2251	* Check if this is a 1GB page or a 2MB page.
2252	*/
2253	AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2254	uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2255	if (fLargePage && idxLevel > 0)
2256	{
2257	Assert(idxLevel == 1 \|\| idxLevel == 2); /* Is guaranteed by the reserved bits check above. */
2258	uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2259	if (fSllpsMask & RT_BIT(idxLevel - 1))
2260	{
2261	/*
2262	* We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2263	* All other reserved bits are identical to the regular page-size paging entity which we've already
2264	* checked above.
2265	*/
2266	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2267
2268	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2269	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2270	}
2271
2272	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2273	break;
2274	}
2275
2276	/*
2277	* If this is the final PTE, compute the translation address and we're done.
2278	*/
2279	if (idxLevel == 0)
2280	{
2281	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2282	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2283	}
2284	}
2285
2286	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2287	}
2288
2289
2290	/**
2291	* Checks whether two consecutive I/O page results of a DMA memory request
2292	* translates to a physically contiguous region.
2293	*
2294	* @returns @c true if the I/O pages are contiguous, @c false otherwise.
2295	* @param pIoPagePrev The previous I/O page.
2296	* @param pIoPage The current I/O page.
2297	*/
2298	static bool dmarIsIoPageAccessContig(PCDMARIOPAGE pIoPagePrev, PCDMARIOPAGE pIoPage)
2299	{
2300	/* Paranoia: Permissions for pages of a DMA memory request must be identical. */
2301	Assert(pIoPagePrev->fPerm == pIoPage->fPerm);
2302
2303	size_t const cbPrev = RT_BIT_64(pIoPagePrev->cShift);
2304	RTGCPHYS const GCPhysPrev = pIoPagePrev->GCPhysBase;
2305	RTGCPHYS const GCPhys = pIoPage->GCPhysBase;
2306	#ifdef RT_STRICT
2307	/* Paranoia: Ensure offset bits are 0. */
2308	{
2309	uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pIoPagePrev->cShift);
2310	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pIoPage->cShift);
2311	Assert(!(GCPhysPrev & fOffMaskPrev));
2312	Assert(!(GCPhys & fOffMask));
2313	}
2314	#endif
2315	return GCPhysPrev + cbPrev == GCPhys;
2316	}
2317
2318
2319	/**
2320	* Looks up the range of addresses for a DMA memory request remapping.
2321	*
2322	* @returns VBox status code.
2323	* @param pDevIns The IOMMU device instance.
2324	* @param pfnLookup The DMA address lookup function.
2325	* @param pMemReqRemap The DMA memory request remapping info.
2326	*/
2327	static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2328	{
2329	AssertPtr(pfnLookup);
2330
2331	RTGCPHYS GCPhysAddr = NIL_RTGCPHYS;
2332	DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2333	uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2334	size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2335	uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2336	uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2337	size_t cbRemaining = cbAddrIn;
2338
2339	int rc;
2340	DMARIOPAGE IoPagePrev;
2341	RT_ZERO(IoPagePrev);
2342	for (;;)
2343	{
2344	/* Update the input memory request with the next address in our range that needs translation. */
2345	MemReqIn.AddrRange.uAddr = uAddrInBase;
2346	MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2347
2348	DMARIOPAGE IoPage;
2349	rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2350	if (RT_SUCCESS(rc))
2351	{
2352	Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2353
2354	/* Store the translated address before continuing to access more pages. */
2355	if (cbRemaining == cbAddrIn)
2356	{
2357	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2358	uint64_t const offAddrOut = uAddrIn & fOffMask;
2359	Assert(!(IoPage.GCPhysBase & fOffMask));
2360	GCPhysAddr = IoPage.GCPhysBase \| offAddrOut;
2361	}
2362	/* Check if addresses translated so far result in a physically contiguous region. */
2363	else if (!dmarIsIoPageAccessContig(&IoPagePrev, &IoPage))
2364	{
2365	rc = VERR_OUT_OF_RANGE;
2366	break;
2367	}
2368
2369	/* Store the I/O page lookup from the first/previous access. */
2370	IoPagePrev = IoPage;
2371
2372	/* Check if we need to access more pages. */
2373	size_t const cbPage = RT_BIT_64(IoPage.cShift);
2374	if (cbRemaining > cbPage - offAddrIn)
2375	{
2376	cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2377	uAddrInBase += cbPage; /* Update address of the next access. */
2378	offAddrIn = 0; /* After first page, all pages are accessed from offset 0. */
2379	}
2380	else
2381	{
2382	/* Caller (PDM) doesn't expect more data accessed than what was requested. */
2383	cbRemaining = 0;
2384	break;
2385	}
2386	}
2387	else
2388	break;
2389	}
2390
2391	pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddr;
2392	pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2393	pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2394	return rc;
2395	}
2396
2397
2398	/**
2399	* Handles legacy mode DMA address remapping.
2400	*
2401	* @returns VBox status code.
2402	* @param pDevIns The IOMMU device instance.
2403	* @param uRtaddrReg The current RTADDR_REG value.
2404	* @param pMemReqRemap The DMA memory request remapping info.
2405	*/
2406	static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2407	{
2408	PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2409	PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2410	PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2411	Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2412
2413	/* Read the root-entry from guest memory. */
2414	uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2415	VTD_ROOT_ENTRY_T RootEntry;
2416	int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2417	if (RT_SUCCESS(rc))
2418	{
2419	/* Check if the root entry is present (must be done before validating reserved bits). */
2420	uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2421	uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2422	bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2423	if (fRootEntryPresent)
2424	{
2425	/* Validate reserved bits in the root entry. */
2426	if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2427	&& !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2428	{
2429	/* Read the context-entry from guest memory. */
2430	RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2431	uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2432	VTD_CONTEXT_ENTRY_T CtxEntry;
2433	rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2434	if (RT_SUCCESS(rc))
2435	{
2436	uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2437	uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2438
2439	/* Note the FPD bit which software can use to supress translation faults from here on in. */
2440	pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2441
2442	/* Check if the context-entry is present (must be done before validating reserved bits). */
2443	bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2444	if (fCtxEntryPresent)
2445	{
2446	/* Validate reserved bits in the context-entry. */
2447	if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2448	&& !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
2449	{
2450	/* Get the domain ID for this mapping. */
2451	pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2452
2453	/* Validate the translation type (TT). */
2454	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2455	uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2456	switch (fTt)
2457	{
2458	case VTD_TT_UNTRANSLATED_SLP:
2459	{
2460	/*
2461	* Untranslated requests are translated using second-level paging structures referenced
2462	* through SLPTPTR. Translated requests and Translation Requests are blocked.
2463	*/
2464	if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2465	{
2466	/* Validate the address width and get the paging level. */
2467	uint8_t cPagingLevel;
2468	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2469	{
2470	/*
2471	* The second-level page table is located at the physical address specified
2472	* in the context entry with which we can finally perform second-level translation.
2473	*/
2474	pMemReqAux->cPagingLevel = cPagingLevel;
2475	pMemReqAux->GCPhysSlPt = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2476	return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2477	}
2478	else
2479	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2480	}
2481	else
2482	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2483	break;
2484	}
2485
2486	case VTD_TT_UNTRANSLATED_PT:
2487	{
2488	/*
2489	* Untranslated requests are processed as pass-through (PT) if PT is supported.
2490	* Translated and translation requests are blocked. If PT isn't supported this TT value
2491	* is reserved which I assume raises a fault (hence fallthru below).
2492	*/
2493	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2494	{
2495	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2496	{
2497	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2498	{
2499	PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2500	PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2501	pOut->AddrRange.uAddr = pIn->AddrRange.uAddr;
2502	pOut->AddrRange.cb = pIn->AddrRange.cb;
2503	pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2504	return VINF_SUCCESS;
2505	}
2506	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2507	}
2508	else
2509	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2510	break;
2511	}
2512	RT_FALL_THRU();
2513	}
2514
2515	case VTD_TT_UNTRANSLATED_DEV_TLB:
2516	{
2517	/*
2518	* Untranslated, translated and translation requests are supported but requires
2519	* device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2520	*/
2521	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2522	RT_FALL_THRU();
2523	}
2524
2525	default:
2526	{
2527	/* Any other TT value is reserved. */
2528	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2529	break;
2530	}
2531	}
2532	}
2533	else
2534	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2535	}
2536	else
2537	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2538	}
2539	else
2540	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2541	}
2542	else
2543	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2544	}
2545	else
2546	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2547	}
2548	else
2549	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2550	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2551	}
2552
2553
2554	/**
2555	* Handles remapping of DMA address requests in scalable mode.
2556	*
2557	* @returns VBox status code.
2558	* @param pDevIns The IOMMU device instance.
2559	* @param uRtaddrReg The current RTADDR_REG value.
2560	* @param pMemReqRemap The DMA memory request remapping info.
2561	*/
2562	static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2563	{
2564	RT_NOREF2(uRtaddrReg, pMemReqRemap);
2565	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2566	Assert(pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK);
2567	return VERR_NOT_IMPLEMENTED;
2568	}
2569
2570
2571	/**
2572	* Gets the DMA access permissions and the address-translation request
2573	* type given the PDM IOMMU memory access flags.
2574	*
2575	* @param pDevIns The IOMMU device instance.
2576	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2577	* @param fBulk Whether this is a bulk memory access (used for
2578	* statistics).
2579	* @param penmReqType Where to store the address-translation request type.
2580	* @param pfReqPerm Where to store the DMA access permissions.
2581	*/
2582	static void dmarDrGetPermAndReqType(PPDMDEVINS pDevIns, uint32_t fFlags, bool fBulk, PVTDREQTYPE penmReqType, uint8_t *pfReqPerm)
2583	{
2584	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2585	if (fFlags & PDMIOMMU_MEM_F_READ)
2586	{
2587	*penmReqType = VTDREQTYPE_READ;
2588	*pfReqPerm = DMAR_PERM_READ;
2589	#ifdef VBOX_WITH_STATISTICS
2590	if (!fBulk)
2591	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2592	else
2593	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkRead));
2594	#else
2595	RT_NOREF2(pThis, fBulk);
2596	#endif
2597	}
2598	else
2599	{
2600	*penmReqType = VTDREQTYPE_WRITE;
2601	*pfReqPerm = DMAR_PERM_WRITE;
2602	#ifdef VBOX_WITH_STATISTICS
2603	if (!fBulk)
2604	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2605	else
2606	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemBulkWrite));
2607	#else
2608	RT_NOREF2(pThis, fBulk);
2609	#endif
2610	}
2611	}
2612
2613
2614	/**
2615	* Handles DMA remapping based on the table translation mode (TTM).
2616	*
2617	* @returns VBox status code.
2618	* @param pDevIns The IOMMU device instance.
2619	* @param uRtaddrReg The current RTADDR_REG value.
2620	* @param pMemReqRemap The DMA memory request remapping info.
2621	*/
2622	static int dmarDrMemReqRemap(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2623	{
2624	int rc;
2625	switch (pMemReqRemap->Aux.fTtm)
2626	{
2627	case VTD_TTM_LEGACY_MODE:
2628	{
2629	rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2630	break;
2631	}
2632
2633	case VTD_TTM_SCALABLE_MODE:
2634	{
2635	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2636	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2637	rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, pMemReqRemap);
2638	else
2639	{
2640	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2641	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2642	}
2643	break;
2644	}
2645
2646	case VTD_TTM_ABORT_DMA_MODE:
2647	{
2648	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2649	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2650	dmarDrTargetAbort(pDevIns);
2651	else
2652	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &pMemReqRemap->In, &pMemReqRemap->Aux);
2653	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2654	break;
2655	}
2656
2657	default:
2658	{
2659	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2660	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &pMemReqRemap->In, &pMemReqRemap->Aux);
2661	break;
2662	}
2663	}
2664	return rc;
2665	}
2666
2667
2668	/**
2669	* Memory access bulk (one or more 4K pages) request from a device.
2670	*
2671	* @returns VBox status code.
2672	* @param pDevIns The IOMMU device instance.
2673	* @param idDevice The device ID (bus, device, function).
2674	* @param cIovas The number of addresses being accessed.
2675	* @param pauIovas The I/O virtual addresses for each page being accessed.
2676	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2677	* @param paGCPhysSpa Where to store the translated physical addresses.
2678	*
2679	* @thread Any.
2680	*/
2681	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2682	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2683	{
2684	/* Validate. */
2685	AssertPtr(pDevIns);
2686	Assert(cIovas > 0);
2687	AssertPtr(pauIovas);
2688	AssertPtr(paGCPhysSpa);
2689	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2690
2691	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2692	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2693
2694	DMAR_LOCK(pDevIns, pThisCC);
2695	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2696	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2697	DMAR_UNLOCK(pDevIns, pThisCC);
2698
2699	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2700	{
2701	VTDREQTYPE enmReqType;
2702	uint8_t fReqPerm;
2703	dmarDrGetPermAndReqType(pDevIns, fFlags, true /* fBulk */, &enmReqType, &fReqPerm);
2704
2705	DMARMEMREQREMAP MemReqRemap;
2706	RT_ZERO(MemReqRemap);
2707	MemReqRemap.In.AddrRange.cb = X86_PAGE_SIZE;
2708	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2709	MemReqRemap.In.idDevice = idDevice;
2710	MemReqRemap.In.Pasid = NIL_PCIPASID;
2711	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2712	MemReqRemap.In.enmReqType = enmReqType;
2713	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2714	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2715
2716	for (size_t i = 0; i < cIovas; i++)
2717	{
2718	MemReqRemap.In.AddrRange.uAddr = pauIovas[i] & X86_PAGE_BASE_MASK;
2719	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2720	if (RT_SUCCESS(rc))
2721	{
2722	paGCPhysSpa[i] = MemReqRemap.Out.AddrRange.uAddr \| (pauIovas[i] & X86_PAGE_OFFSET_MASK);
2723	Assert(MemReqRemap.Out.AddrRange.cb == MemReqRemap.In.AddrRange.cb);
2724	}
2725	else
2726	{
2727	LogFlowFunc(("idDevice=%#x uIova=%#RX64 fPerm=%#x rc=%Rrc\n", idDevice, pauIovas[i], fReqPerm, rc));
2728	return rc;
2729	}
2730	}
2731	}
2732	else
2733	{
2734	/* Addresses are forwarded without translation when the translation is disabled. */
2735	for (size_t i = 0; i < cIovas; i++)
2736	paGCPhysSpa[i] = pauIovas[i];
2737	}
2738
2739	return VINF_SUCCESS;
2740	}
2741
2742
2743	/**
2744	* Memory access transaction from a device.
2745	*
2746	* @returns VBox status code.
2747	* @param pDevIns The IOMMU device instance.
2748	* @param idDevice The device ID (bus, device, function).
2749	* @param uIova The I/O virtual address being accessed.
2750	* @param cbIova The size of the access.
2751	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2752	* @param pGCPhysSpa Where to store the translated system physical address.
2753	* @param pcbContiguous Where to store the number of contiguous bytes translated
2754	* and permission-checked.
2755	*
2756	* @thread Any.
2757	*/
2758	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2759	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2760	{
2761	/* Validate. */
2762	AssertPtr(pDevIns);
2763	AssertPtr(pGCPhysSpa);
2764	AssertPtr(pcbContiguous);
2765	Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2766	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2767
2768	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2769	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2770
2771	DMAR_LOCK(pDevIns, pThisCC);
2772	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2773	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2774	DMAR_UNLOCK(pDevIns, pThisCC);
2775
2776	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2777	{
2778	VTDREQTYPE enmReqType;
2779	uint8_t fReqPerm;
2780	dmarDrGetPermAndReqType(pDevIns, fFlags, false /* fBulk */, &enmReqType, &fReqPerm);
2781
2782	DMARMEMREQREMAP MemReqRemap;
2783	RT_ZERO(MemReqRemap);
2784	MemReqRemap.In.AddrRange.uAddr = uIova;
2785	MemReqRemap.In.AddrRange.cb = cbIova;
2786	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2787	MemReqRemap.In.idDevice = idDevice;
2788	MemReqRemap.In.Pasid = NIL_PCIPASID;
2789	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2790	MemReqRemap.In.enmReqType = enmReqType;
2791	MemReqRemap.Aux.fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2792	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2793
2794	int const rc = dmarDrMemReqRemap(pDevIns, uRtaddrReg, &MemReqRemap);
2795	*pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2796	*pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2797	return rc;
2798	}
2799
2800	*pGCPhysSpa = uIova;
2801	*pcbContiguous = cbIova;
2802	return VINF_SUCCESS;
2803	}
2804
2805
2806	/**
2807	* Reads an IRTE from guest memory.
2808	*
2809	* @returns VBox status code.
2810	* @param pDevIns The IOMMU device instance.
2811	* @param uIrtaReg The IRTA_REG.
2812	* @param idxIntr The interrupt index.
2813	* @param pIrte Where to store the read IRTE.
2814	*/
2815	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2816	{
2817	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2818
2819	size_t const cbIrte = sizeof(*pIrte);
2820	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2821	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2822	}
2823
2824
2825	/**
2826	* Remaps the source MSI to the destination MSI given the IRTE.
2827	*
2828	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2829	* IRTA_REG.EIME).
2830	* @param pIrte The IRTE used for the remapping.
2831	* @param pMsiIn The source MSI (currently unused).
2832	* @param pMsiOut Where to store the remapped MSI.
2833	*/
2834	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2835	{
2836	NOREF(pMsiIn);
2837	uint64_t const uIrteQword0 = pIrte->au64[0];
2838
2839	/*
2840	* Let's start with a clean slate and preserve unspecified bits if the need arises.
2841	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2842	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2843	* it copies it from the source MSI.
2844	*/
2845	RT_ZERO(*pMsiOut);
2846	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2847	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2848	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2849	if (fExtIntrMode)
2850	{
2851	/*
2852	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2853	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2854	*/
2855	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2856	pMsiOut->Addr.n.u8DestId = idDest;
2857	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2858	}
2859	else
2860	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2861
2862	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2863	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2864	pMsiOut->Data.n.u1Level = 1;
2865	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2866	}
2867
2868
2869	/**
2870	* Handles remapping of interrupts in remappable interrupt format.
2871	*
2872	* @returns VBox status code.
2873	* @param pDevIns The IOMMU device instance.
2874	* @param uIrtaReg The IRTA_REG.
2875	* @param idDevice The device ID (bus, device, function).
2876	* @param pMsiIn The source MSI.
2877	* @param pMsiOut Where to store the remapped MSI.
2878	*/
2879	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2880	{
2881	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2882
2883	/* Validate reserved bits in the interrupt request. */
2884	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2885	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2886	{
2887	/* Compute the index into the interrupt remap table. */
2888	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2889	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2890	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
2891	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2892	uint16_t const idxIntr = fSubHandleValid
2893	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2894	: uHandle;
2895
2896	/* Validate the index. */
2897	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2898	if (idxIntr < cEntries)
2899	{
2900	/** @todo Implement and read IRTE from interrupt-entry cache here. */
2901
2902	/* Read the interrupt remap table entry (IRTE) at the index. */
2903	VTD_IRTE_T Irte;
2904	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2905	if (RT_SUCCESS(rc))
2906	{
2907	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2908	uint64_t const uIrteQword0 = Irte.au64[0];
2909	uint64_t const uIrteQword1 = Irte.au64[1];
2910	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2911	if (fPresent)
2912	{
2913	/* Validate reserved bits in the IRTE. */
2914	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2915	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2916	if ( !(uIrteQword0 & ~fQw0ValidMask)
2917	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2918	{
2919	/* Validate requester id (the device ID) as configured in the IRTE. */
2920	bool fSrcValid;
2921	DMARDIAG enmIrDiag;
2922	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2923	switch (fSvt)
2924	{
2925	case VTD_IRTE_SVT_NONE:
2926	{
2927	fSrcValid = true;
2928	enmIrDiag = kDmarDiag_None;
2929	break;
2930	}
2931
2932	case VTD_IRTE_SVT_VALIDATE_MASK:
2933	{
2934	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2935	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2936	uint16_t const fValidMask = s_afValidMasks[idxMask];
2937	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2938	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2939	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2940	break;
2941	}
2942
2943	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2944	{
2945	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2946	uint8_t const uBusFirst = RT_HI_U8(idSource);
2947	uint8_t const uBusLast = RT_LO_U8(idSource);
2948	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2949	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2950	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2951	break;
2952	}
2953
2954	default:
2955	{
2956	fSrcValid = false;
2957	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2958	break;
2959	}
2960	}
2961
2962	if (fSrcValid)
2963	{
2964	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2965	if (!fPostedMode)
2966	{
2967	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2968	return VINF_SUCCESS;
2969	}
2970	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2971	}
2972	else
2973	dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2974	}
2975	else
2976	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2977	}
2978	else
2979	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2980	}
2981	else
2982	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2983	}
2984	else
2985	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2986	}
2987	else
2988	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr /, NULL / pIrte */);
2989	return VERR_IOMMU_INTR_REMAP_DENIED;
2990	}
2991
2992
2993	/**
2994	* Interrupt remap request from a device.
2995	*
2996	* @returns VBox status code.
2997	* @param pDevIns The IOMMU device instance.
2998	* @param idDevice The device ID (bus, device, function).
2999	* @param pMsiIn The source MSI.
3000	* @param pMsiOut Where to store the remapped MSI.
3001	*/
3002	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
3003	{
3004	/* Validate. */
3005	Assert(pDevIns);
3006	Assert(pMsiIn);
3007	Assert(pMsiOut);
3008	RT_NOREF1(idDevice);
3009
3010	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3011	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3012
3013	/* Lock and read all registers required for interrupt remapping up-front. */
3014	DMAR_LOCK(pDevIns, pThisCC);
3015	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3016	uint64_t const uIrtaReg = pThis->uIrtaReg;
3017	DMAR_UNLOCK(pDevIns, pThisCC);
3018
3019	/* Check if interrupt remapping is enabled. */
3020	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
3021	{
3022	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
3023	if (!fIsRemappable)
3024	{
3025	/* Handle compatibility format interrupts. */
3026	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
3027
3028	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
3029	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
3030	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
3031	{
3032	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
3033	return VERR_IOMMU_INTR_REMAP_DENIED;
3034	}
3035
3036	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
3037	pMsiOut = pMsiIn;
3038	return VINF_SUCCESS;
3039	}
3040
3041	/* Handle remappable format interrupts. */
3042	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
3043	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
3044	}
3045
3046	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
3047	pMsiOut = pMsiIn;
3048	return VINF_SUCCESS;
3049	}
3050
3051
3052	/**
3053	* @callback_method_impl{FNIOMMMIONEWWRITE}
3054	*/
3055	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3056	{
3057	RT_NOREF1(pvUser);
3058	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3059
3060	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3061	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
3062
3063	uint16_t const offReg = off;
3064	uint16_t const offLast = offReg + cb - 1;
3065	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3066	{
3067	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3068	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
3069
3070	uint64_t uPrev = 0;
3071	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
3072	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
3073	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3074	switch (off)
3075	{
3076	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
3077	{
3078	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
3079	break;
3080	}
3081
3082	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
3083	case VTD_MMIO_OFF_CCMD_REG + 4:
3084	{
3085	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
3086	break;
3087	}
3088
3089	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
3090	{
3091	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
3092	break;
3093	}
3094
3095	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
3096	{
3097	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
3098	break;
3099	}
3100
3101	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
3102	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
3103	{
3104	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
3105	break;
3106	}
3107
3108	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3109	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
3110	{
3111	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3112	break;
3113	}
3114
3115	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3116	{
3117	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3118	break;
3119	}
3120
3121	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3122	{
3123	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3124	break;
3125	}
3126
3127	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3128	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3129	{
3130	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3131	break;
3132	}
3133	}
3134
3135	DMAR_UNLOCK(pDevIns, pThisCC);
3136	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3137	return rcStrict;
3138	}
3139
3140	return VINF_IOM_MMIO_UNUSED_FF;
3141	}
3142
3143
3144	/**
3145	* @callback_method_impl{FNIOMMMIONEWREAD}
3146	*/
3147	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3148	{
3149	RT_NOREF1(pvUser);
3150	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3151
3152	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3153	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3154
3155	uint16_t const offReg = off;
3156	uint16_t const offLast = offReg + cb - 1;
3157	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3158	{
3159	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3160	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3161
3162	if (cb == 8)
3163	{
3164	(uint64_t )pv = dmarRegRead64(pThis, offReg);
3165	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
3166	}
3167	else
3168	{
3169	(uint32_t )pv = dmarRegRead32(pThis, offReg);
3170	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
3171	}
3172
3173	DMAR_UNLOCK(pDevIns, pThisCC);
3174	return VINF_SUCCESS;
3175	}
3176
3177	return VINF_IOM_MMIO_UNUSED_FF;
3178	}
3179
3180
3181	#ifdef IN_RING3
3182	/**
3183	* Process requests in the invalidation queue.
3184	*
3185	* @param pDevIns The IOMMU device instance.
3186	* @param pvRequests The requests to process.
3187	* @param cbRequests The size of all requests (in bytes).
3188	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3189	* VTD_IQA_REG_DW_256_BIT).
3190	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3191	*/
3192	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3193	uint8_t fTtm)
3194	{
3195	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3196	do \
3197	{ \
3198	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3199	return; \
3200	} while (0)
3201
3202	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3203	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3204
3205	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3206	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3207
3208	/*
3209	* The below check is redundant since we check both TTM and DW for each
3210	* descriptor type we process. However, the order of errors reported by hardware
3211	* may differ hence this is kept commented out but not removed if we need to
3212	* change this in the future.
3213	*
3214	* In our implementation, we would report the descriptor type as invalid,
3215	* while on real hardware it may report descriptor width as invalid.
3216	* The Intel VT-d spec. is not clear which error takes preceedence.
3217	*/
3218	#if 0
3219	/*
3220	* Verify that 128-bit descriptors are not used when operating in scalable mode.
3221	* We don't check this while software writes IQA_REG but defer it until now because
3222	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3223	* -IS- performed when software writes IQA_REG since it only requires checking against
3224	* immutable hardware features.
3225	*/
3226	if ( fTtm != VTD_TTM_SCALABLE_MODE
3227	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
3228	{ /* likely */ }
3229	else
3230	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3231	#endif
3232
3233	/*
3234	* Process requests in FIFO order.
3235	*/
3236	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3237	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3238	{
3239	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
3240	uint64_t const uQword0 = puDscQwords[0];
3241	uint64_t const uQword1 = puDscQwords[1];
3242	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3243	switch (fDscType)
3244	{
3245	case VTD_INV_WAIT_DSC_TYPE:
3246	{
3247	/* Validate descriptor type. */
3248	if ( fTtm == VTD_TTM_LEGACY_MODE
3249	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
3250	{ /* likely */ }
3251	else
3252	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3253
3254	/* Validate reserved bits. */
3255	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3256	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3257	: VTD_INV_WAIT_DSC_0_VALID_MASK;
3258	if ( !(uQword0 & ~fValidMask0)
3259	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3260	{ /* likely */ }
3261	else
3262	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3263
3264	if (fDw == VTD_IQA_REG_DW_256_BIT)
3265	{
3266	if ( !puDscQwords[2]
3267	&& !puDscQwords[3])
3268	{ /* likely */ }
3269	else
3270	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3271	}
3272
3273	/* Perform status write (this must be done prior to generating the completion interrupt). */
3274	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3275	if (fSw)
3276	{
3277	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3278	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3279	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3280	AssertRC(rc);
3281	}
3282
3283	/* Generate invalidation event interrupt. */
3284	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3285	if (fIf)
3286	{
3287	DMAR_LOCK(pDevIns, pThisR3);
3288	dmarR3InvEventRaiseInterrupt(pDevIns);
3289	DMAR_UNLOCK(pDevIns, pThisR3);
3290	}
3291
3292	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3293	break;
3294	}
3295
3296	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3297	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3298	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3299	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3300	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3301	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3302	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3303	default:
3304	{
3305	/* Stop processing further requests. */
3306	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3307	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3308	}
3309	}
3310	}
3311	#undef DMAR_IQE_FAULT_RECORD_RET
3312	}
3313
3314
3315	/**
3316	* The invalidation-queue thread.
3317	*
3318	* @returns VBox status code.
3319	* @param pDevIns The IOMMU device instance.
3320	* @param pThread The command thread.
3321	*/
3322	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3323	{
3324	NOREF(pThread);
3325	LogFlowFunc(("\n"));
3326
3327	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3328	return VINF_SUCCESS;
3329
3330	/*
3331	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3332	* This prevents trashing the heap as well as deal with out-of-memory situations
3333	* up-front while starting the VM. It also simplifies the code from having to
3334	* dynamically grow/shrink the allocation based on how software sizes the queue.
3335	* Guests normally don't alter the queue size all the time, but that's not an
3336	* assumption we can make.
3337	*/
3338	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3339	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3340	void *pvRequests = RTMemAllocZ(cbMaxQs);
3341	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3342
3343	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3344	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3345
3346	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3347	{
3348	/*
3349	* Sleep until we are woken up.
3350	*/
3351	{
3352	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3353	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3354	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3355	break;
3356	}
3357
3358	DMAR_LOCK(pDevIns, pThisR3);
3359	if (dmarInvQueueCanProcessRequests(pThis))
3360	{
3361	uint32_t offQueueHead;
3362	uint32_t offQueueTail;
3363	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3364	if (!fIsEmpty)
3365	{
3366	/*
3367	* Get the current queue size, descriptor width, queue base address and the
3368	* table translation mode while the lock is still held.
3369	*/
3370	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3371	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3372	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3373	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3374	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3375	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3376
3377	/* Paranoia. */
3378	Assert(cbQueue <= cbMaxQs);
3379	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3380	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3381	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
3382	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
3383	Assert(offQueueHead < cbQueue);
3384
3385	/*
3386	* A table translation mode of "reserved" isn't valid for any descriptor type.
3387	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3388	* but if ESRTPS is support, we will perform a global invalidation when software
3389	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3390	* So caching TTM while reading all descriptors should not be a problem.
3391	*
3392	* Also, validate the queue tail offset as it's mutable by software.
3393	*/
3394	if ( fTtm != VTD_TTM_RSVD
3395	&& offQueueTail < cbQueue)
3396	{
3397	/* Don't hold the lock while reading (a potentially large amount of) requests */
3398	DMAR_UNLOCK(pDevIns, pThisR3);
3399
3400	int rc;
3401	uint32_t cbRequests;
3402	if (offQueueTail > offQueueHead)
3403	{
3404	/* The requests have not wrapped around, read them in one go. */
3405	cbRequests = offQueueTail - offQueueHead;
3406	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3407	}
3408	else
3409	{
3410	/* The requests have wrapped around, read forward and wrapped-around. */
3411	uint32_t const cbForward = cbQueue - offQueueHead;
3412	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3413
3414	uint32_t const cbWrapped = offQueueTail;
3415	if ( RT_SUCCESS(rc)
3416	&& cbWrapped > 0)
3417	{
3418	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3419	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3420	}
3421	cbRequests = cbForward + cbWrapped;
3422	}
3423
3424	/* Re-acquire the lock since we need to update device state. */
3425	DMAR_LOCK(pDevIns, pThisR3);
3426
3427	if (RT_SUCCESS(rc))
3428	{
3429	/* Indicate to software we've fetched all requests. */
3430	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3431
3432	/* Don't hold the lock while processing requests. */
3433	DMAR_UNLOCK(pDevIns, pThisR3);
3434
3435	/* Process all requests. */
3436	Assert(cbRequests <= cbQueue);
3437	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3438
3439	/*
3440	* We've processed all requests and the lock shouldn't be held at this point.
3441	* Using 'continue' here allows us to skip re-acquiring the lock just to release
3442	* it again before going back to the thread loop. It's a bit ugly but it certainly
3443	* helps with performance.
3444	*/
3445	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3446	continue;
3447	}
3448	else
3449	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3450	}
3451	else
3452	{
3453	if (fTtm == VTD_TTM_RSVD)
3454	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3455	else
3456	{
3457	Assert(offQueueTail >= cbQueue);
3458	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3459	}
3460	}
3461	}
3462	}
3463	DMAR_UNLOCK(pDevIns, pThisR3);
3464	}
3465
3466	RTMemFree(pvRequests);
3467	pvRequests = NULL;
3468
3469	LogFlowFunc(("Invalidation-queue thread terminating\n"));
3470	return VINF_SUCCESS;
3471	}
3472
3473
3474	/**
3475	* Wakes up the invalidation-queue thread so it can respond to a state
3476	* change.
3477	*
3478	* @returns VBox status code.
3479	* @param pDevIns The IOMMU device instance.
3480	* @param pThread The invalidation-queue thread.
3481	*
3482	* @thread EMT.
3483	*/
3484	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3485	{
3486	RT_NOREF(pThread);
3487	LogFlowFunc(("\n"));
3488	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3489	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3490	}
3491
3492
3493	/**
3494	* @callback_method_impl{FNDBGFHANDLERDEV}
3495	*/
3496	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3497	{
3498	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3499	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3500	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3501
3502	/*
3503	* We lock the device to get a consistent register state as it is
3504	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3505	* ones we care about here) into temporaries and release the lock ASAP.
3506	*
3507	* Order of register being read and outputted is in accordance with the
3508	* spec. for no particular reason.
3509	* See Intel VT-d spec. 10.4 "Register Descriptions".
3510	*/
3511	DMAR_LOCK(pDevIns, pThisR3);
3512
3513	DMARDIAG const enmDiag = pThis->enmDiag;
3514	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3515	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3516	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3517	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3518	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3519	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3520	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3521	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3522	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3523	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3524	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3525	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3526	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3527	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3528	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3529	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3530	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3531	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3532	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3533	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3534	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3535	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3536	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3537	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3538	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3539	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3540	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3541	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3542	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3543	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3544	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3545	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3546	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3547	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3548	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3549	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3550	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3551	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3552
3553	DMAR_UNLOCK(pDevIns, pThisR3);
3554
3555	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3556	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3557	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3558
3559	/*
3560	* Non-verbose output.
3561	*/
3562	if (!fVerbose)
3563	{
3564	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3565	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3566	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3567	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3568	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3569	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3570	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3571	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3572	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3573	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3574	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3575	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3576	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3577	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3578	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3579	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3580	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3581	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3582	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3583	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3584	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3585	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3586	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3587	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3588	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3589	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3590	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3591	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3592	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3593	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3594	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3595	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3596	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3597	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3598	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3599	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3600	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3601	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3602	pHlp->pfnPrintf(pHlp, "\n");
3603	return;
3604	}
3605
3606	/*
3607	* Verbose output.
3608	*/
3609	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3610	{
3611	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3612	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3613	}
3614	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3615	{
3616	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3617	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3618	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3619	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3620	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3621	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3622	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3623	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3624	pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3625	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3626	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3627	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3628	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3629	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3630	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3631	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3632	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3633	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3634	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3635	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3636	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3637	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3638	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3639	}
3640	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3641	{
3642	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3643	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3644	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3645	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3646	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3647	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3648	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3649	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3650	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3651	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3652	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3653	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3654	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3655	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3656	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3657	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3658	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3659	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3660	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3661	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3662	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3663	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3664	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3665	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3666	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3667	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3668	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3669	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3670	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3671	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3672	}
3673	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3674	{
3675	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3676	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3677	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3678	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3679	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3680	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3681	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3682	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3683	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3684	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3685	}
3686	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3687	{
3688	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3689	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3690	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3691	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3692	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3693	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3694	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3695	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3696	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3697	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3698	}
3699	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3700	{
3701	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3702	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3703	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3704	}
3705	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3706	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3707	{
3708	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3709	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3710	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3711	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3712	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3713	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3714	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3715	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3716	}
3717	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3718	{
3719	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3720	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3721	}
3722	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3723	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3724	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3725	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3726	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3727	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3728	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3729	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3730	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3731	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3732	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3733	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3734	{
3735	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3736	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3737	uint8_t const cQueuePages = 1 << fQs;
3738	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3739	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3740	}
3741	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3742	{
3743	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3744	}
3745	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3746	{
3747	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3748	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3749	}
3750	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3751	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3752	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3753	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3754	{
3755	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3756	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3757	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3758	}
3759	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3760	{
3761	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3762	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3763	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3764	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3765	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3766	}
3767	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3768	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3769	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3770	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3771	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3772	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3773	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3774	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3775	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3776	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3777	pHlp->pfnPrintf(pHlp, "\n");
3778	}
3779
3780
3781	/**
3782	* Initializes all registers in the DMAR unit.
3783	*
3784	* @param pDevIns The IOMMU device instance.
3785	*/
3786	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3787	{
3788	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3789	LogFlowFunc(("\n"));
3790
3791	/*
3792	* Wipe all registers (required on reset).
3793	*/
3794	RT_ZERO(pThis->abRegs0);
3795	RT_ZERO(pThis->abRegs1);
3796
3797	/*
3798	* Initialize registers not mutable by software prior to initializing other registers.
3799	*/
3800	/* VER_REG */
3801	{
3802	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3803	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3804	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3805	}
3806
3807	uint8_t const fFlts = 0; /* First-level translation support. */
3808	uint8_t const fSlts = 1; /* Second-level translation support. */
3809	uint8_t const fPt = 1; /* Pass-Through support. */
3810	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3811	uint8_t const fNest = 0; /* Nested translation support. */
3812
3813	/* CAP_REG */
3814	{
3815	uint8_t cGstPhysAddrBits;
3816	uint8_t cGstLinearAddrBits;
3817	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3818
3819	uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3820	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3821	uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3822	uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3823	uint8_t const fSllps = fSl2mp \| (fSl2gp << 1); /* Second-level large page support. */
3824	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3825	: X86_PAGE_2M_SHIFT)
3826	- X86_PAGE_4K_SHIFT;
3827	uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3828	uint8_t const fPsi = 1; /* Page selective invalidation. */
3829	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3830	uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3831	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3832	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3833	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3834	AssertCompile(DMAR_ND <= 6);
3835
3836	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3837	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3838	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3839	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3840	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3841	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3842	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3843	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3844	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3845	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3846	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3847	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3848	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3849	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3850	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3851	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3852	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3853	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3854	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3855	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3856	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3857	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3858
3859	pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3860	pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3861	pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3862	}
3863
3864	/* ECAP_REG */
3865	{
3866	uint8_t const fQi = 1; /* Queued-invalidations. */
3867	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3868	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3869	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3870	uint8_t const fEim = 1; /* Extended interrupt mode.*/
3871	uint8_t const fAdms = 1; /* Abort DMA mode support. */
3872	uint8_t const fErs = 0; /* Execute Request (not supported). */
3873
3874	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3875	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3876	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3877	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3878	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3879	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3880	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3881	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3882	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3883	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3884	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3885	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3886	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3887	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3888	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3889	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3890	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3891	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3892	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3893	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3894	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3895	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3896	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3897	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3898	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3899	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3900	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3901	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3902	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3903	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3904
3905	pThis->fPermValidMask = DMAR_PERM_READ \| DMAR_PERM_WRITE;
3906	if (fErs)
3907	pThis->fPermValidMask = DMAR_PERM_EXE;
3908	}
3909
3910	/*
3911	* Initialize registers mutable by software.
3912	*/
3913	/* FECTL_REG */
3914	{
3915	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3916	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3917	}
3918
3919	/* ICETL_REG */
3920	{
3921	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3922	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3923	}
3924
3925	#ifdef VBOX_STRICT
3926	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3927	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3928	#endif
3929	}
3930
3931
3932	/**
3933	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3934	*/
3935	static DECLCALLBACK(int) dmarR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3936	{
3937	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
3938	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3939	LogFlowFunc(("\n"));
3940
3941	/* First, save software-immutable registers that we validate on state load. */
3942	pHlp->pfnSSMPutU32(pSSM, pThis->uVerReg);
3943	pHlp->pfnSSMPutU64(pSSM, pThis->fCapReg);
3944	pHlp->pfnSSMPutU64(pSSM, pThis->fExtCapReg);
3945
3946	/* Save MMIO registers. */
3947	pHlp->pfnSSMPutU32(pSSM, DMAR_MMIO_GROUP_COUNT);
3948	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs0));
3949	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs0[0], sizeof(pThis->abRegs0));
3950	pHlp->pfnSSMPutU32(pSSM, sizeof(pThis->abRegs1));
3951	pHlp->pfnSSMPutMem(pSSM, &pThis->abRegs1[0], sizeof(pThis->abRegs1));
3952
3953	/*
3954	* Save our implemention-defined MMIO registers offsets.
3955	* The register themselves are currently all part of group 1 (saved above).
3956	* We save these to ensure they're located where the code expects them while loading state.
3957	*/
3958	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IMPL_COUNT);
3959	AssertCompile(DMAR_MMIO_OFF_IMPL_COUNT == 2);
3960	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_IVA_REG);
3961	pHlp->pfnSSMPutU16(pSSM, DMAR_MMIO_OFF_FRCD_LO_REG);
3962
3963	/* Save lazily activated registers. */
3964	pHlp->pfnSSMPutU64(pSSM, pThis->uIrtaReg);
3965	pHlp->pfnSSMPutU64(pSSM, pThis->uRtaddrReg);
3966
3967	/* Save terminator marker and return status. */
3968	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
3969	}
3970
3971
3972	/**
3973	* @callback_method_impl{FNSSMDEVLOADEXEC}
3974	*/
3975	static DECLCALLBACK(int) dmarR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3976	{
3977	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3978	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3979	int const rcDataErr = VERR_SSM_UNEXPECTED_DATA;
3980	int const rcFmtErr = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
3981	LogFlowFunc(("\n"));
3982
3983	/*
3984	* Validate saved-state version.
3985	*/
3986	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
3987	if (uVersion != DMAR_SAVED_STATE_VERSION)
3988	{
3989	LogRel(("%s: Invalid saved-state version %#x\n", DMAR_LOG_PFX, uVersion));
3990	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3991	}
3992
3993	/*
3994	* Load and validate software-immutable registers.
3995	* The features we had exposed to the guest (in the saved state) must be identical
3996	* to what is currently emulated.
3997	*/
3998	{
3999	/* VER_REG */
4000	uint32_t uVerReg = 0;
4001	int rc = pHlp->pfnSSMGetU32(pSSM, &uVerReg);
4002	AssertRCReturn(rc, rc);
4003	AssertLogRelMsgReturn(uVerReg == pThis->uVerReg,
4004	("%s: VER_REG mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, pThis->uVerReg, uVerReg),
4005	rcDataErr);
4006	/* CAP_REG */
4007	uint64_t fCapReg = 0;
4008	pHlp->pfnSSMGetU64(pSSM, &fCapReg);
4009	AssertLogRelMsgReturn(fCapReg == pThis->fCapReg,
4010	("%s: CAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fCapReg, fCapReg),
4011	rcDataErr);
4012	/* ECAP_REG */
4013	uint64_t fExtCapReg = 0;
4014	pHlp->pfnSSMGetU64(pSSM, &fExtCapReg);
4015	AssertLogRelMsgReturn(fExtCapReg == pThis->fExtCapReg,
4016	("%s: ECAP_REG mismatch (expected %#RX64 got %#RX64)\n", DMAR_LOG_PFX, pThis->fExtCapReg,
4017	fExtCapReg), rcDataErr);
4018	}
4019
4020	/*
4021	* Load MMIO registers.
4022	*/
4023	{
4024	/* Group count. */
4025	uint32_t cRegGroups = 0;
4026	pHlp->pfnSSMGetU32(pSSM, &cRegGroups);
4027	AssertLogRelMsgReturn(cRegGroups == DMAR_MMIO_GROUP_COUNT,
4028	("%s: MMIO group count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_GROUP_COUNT,
4029	cRegGroups), rcFmtErr);
4030	/* Group 0. */
4031	uint32_t cbRegs0 = 0;
4032	pHlp->pfnSSMGetU32(pSSM, &cbRegs0);
4033	AssertLogRelMsgReturn(cbRegs0 == sizeof(pThis->abRegs0),
4034	("%s: MMIO group 0 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs0),
4035	cbRegs0), rcFmtErr);
4036	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs0[0], cbRegs0);
4037	/* Group 1. */
4038	uint32_t cbRegs1 = 0;
4039	pHlp->pfnSSMGetU32(pSSM, &cbRegs1);
4040	AssertLogRelMsgReturn(cbRegs1 == sizeof(pThis->abRegs1),
4041	("%s: MMIO group 1 size mismatch (expected %u got %u)\n", DMAR_LOG_PFX, sizeof(pThis->abRegs1),
4042	cbRegs1), rcFmtErr);
4043	pHlp->pfnSSMGetMem(pSSM, &pThis->abRegs1[0], cbRegs1);
4044	}
4045
4046	/*
4047	* Validate implementation-defined MMIO register offsets.
4048	*/
4049	{
4050	/* Offset count. */
4051	uint16_t cOffsets = 0;
4052	pHlp->pfnSSMGetU16(pSSM, &cOffsets);
4053	AssertLogRelMsgReturn(cOffsets == DMAR_MMIO_OFF_IMPL_COUNT,
4054	("%s: MMIO offset count mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IMPL_COUNT,
4055	cOffsets), rcFmtErr);
4056	/* IVA_REG. */
4057	uint16_t offReg = 0;
4058	pHlp->pfnSSMGetU16(pSSM, &offReg);
4059	AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_IVA_REG,
4060	("%s: IVA_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IVA_REG,
4061	offReg), rcFmtErr);
4062	/* IOTLB_REG. */
4063	AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_IOTLB_REG,
4064	("%s: IOTLB_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_IOTLB_REG,
4065	offReg), rcFmtErr);
4066	/* FRCD_LO_REG. */
4067	pHlp->pfnSSMGetU16(pSSM, &offReg);
4068	AssertLogRelMsgReturn(offReg == DMAR_MMIO_OFF_FRCD_LO_REG,
4069	("%s: FRCD_LO_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_LO_REG,
4070	offReg), rcFmtErr);
4071	/* FRCD_HI_REG. */
4072	AssertLogRelMsgReturn(offReg + 8 == DMAR_MMIO_OFF_FRCD_HI_REG,
4073	("%s: FRCD_HI_REG offset mismatch (expected %u got %u)\n", DMAR_LOG_PFX, DMAR_MMIO_OFF_FRCD_HI_REG,
4074	offReg), rcFmtErr);
4075	}
4076
4077	/*
4078	* Load lazily activated registers.
4079	*/
4080	{
4081	/* Active IRTA_REG. */
4082	pHlp->pfnSSMGetU64(pSSM, &pThis->uIrtaReg);
4083	AssertLogRelMsgReturn(!(pThis->uIrtaReg & ~VTD_IRTA_REG_RW_MASK),
4084	("%s: IRTA_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uIrtaReg), rcDataErr);
4085	/* Active RTADDR_REG. */
4086	pHlp->pfnSSMGetU64(pSSM, &pThis->uRtaddrReg);
4087	AssertLogRelMsgReturn(!(pThis->uRtaddrReg & ~VTD_RTADDR_REG_RW_MASK),
4088	("%s: RTADDR_REG reserved bits set %#RX64\n", DMAR_LOG_PFX, pThis->uRtaddrReg), rcDataErr);
4089	}
4090
4091	/*
4092	* Verify terminator marker.
4093	*/
4094	{
4095	uint32_t uEndMarker = 0;
4096	int const rc = pHlp->pfnSSMGetU32(pSSM, &uEndMarker);
4097	AssertRCReturn(rc, rc);
4098	AssertLogRelMsgReturn(uEndMarker == UINT32_MAX,
4099	("%s: End marker mismatch (expected %#RX32 got %#RX32)\n", DMAR_LOG_PFX, UINT32_MAX, uEndMarker),
4100	rcFmtErr);
4101	}
4102	return VINF_SUCCESS;
4103	}
4104
4105
4106	/**
4107	* @callback_method_impl{FNSSMDEVLOADDONE}
4108	*/
4109	static DECLCALLBACK(int) dmarR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
4110	{
4111	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4112	LogFlowFunc(("\n"));
4113	RT_NOREF(pSSM);
4114	AssertPtrReturn(pThisR3, VERR_INVALID_POINTER);
4115
4116	DMAR_LOCK(pDevIns, pThisR3);
4117	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
4118	DMAR_UNLOCK(pDevIns, pThisR3);
4119	return VINF_SUCCESS;
4120	}
4121
4122
4123	/**
4124	* @interface_method_impl{PDMDEVREG,pfnReset}
4125	*/
4126	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
4127	{
4128	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4129	LogFlowFunc(("\n"));
4130
4131	DMAR_LOCK(pDevIns, pThisR3);
4132	dmarR3RegsInit(pDevIns);
4133	DMAR_UNLOCK(pDevIns, pThisR3);
4134	}
4135
4136
4137	/**
4138	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4139	*/
4140	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
4141	{
4142	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4143	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
4144	LogFlowFunc(("\n"));
4145
4146	DMAR_LOCK(pDevIns, pThisR3);
4147
4148	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
4149	{
4150	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
4151	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
4152	}
4153
4154	DMAR_UNLOCK(pDevIns, pThisR3);
4155	return VINF_SUCCESS;
4156	}
4157
4158
4159	/**
4160	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4161	*/
4162	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4163	{
4164	RT_NOREF(pCfg);
4165
4166	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4167	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
4168	pThisR3->pDevInsR3 = pDevIns;
4169
4170	LogFlowFunc(("iInstance=%d\n", iInstance));
4171	NOREF(iInstance);
4172
4173	/*
4174	* Register the IOMMU with PDM.
4175	*/
4176	PDMIOMMUREGR3 IommuReg;
4177	RT_ZERO(IommuReg);
4178	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4179	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4180	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4181	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4182	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4183	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
4184	if (RT_FAILURE(rc))
4185	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
4186	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
4187	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4188	N_("IOMMU helper version mismatch; got %#x expected %#x"),
4189	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
4190	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
4191	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
4192	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
4193	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
4194	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
4195	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
4196	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
4197	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
4198
4199	/*
4200	* Use PDM's critical section (via helpers) for the IOMMU device.
4201	*/
4202	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4203	AssertRCReturn(rc, rc);
4204
4205	/*
4206	* Initialize PCI configuration registers.
4207	*/
4208	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4209	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4210
4211	/* Header. */
4212	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4213	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4214	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
4215	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
4216	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
4217	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
4218	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
4219	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
4220
4221	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
4222	PDMPciDevSetStatus(pPciDev, 0);
4223	PDMPciDevSetCapabilityList(pPciDev, 0);
4224	/** @todo VTBAR at 0x180? */
4225
4226	/*
4227	* Register the PCI function with PDM.
4228	*/
4229	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4230	AssertLogRelRCReturn(rc, rc);
4231
4232	/*
4233	* Register MMIO region.
4234	*/
4235	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
4236	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
4237	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
4238	&pThis->hMmio);
4239	AssertLogRelRCReturn(rc, rc);
4240
4241	/*
4242	* Register saved state handlers.
4243	*/
4244	rc = PDMDevHlpSSMRegisterEx(pDevIns, DMAR_SAVED_STATE_VERSION, sizeof(DMAR), NULL /* pszBefore */,
4245	NULL /* pfnLivePrep /, NULL / pfnLiveExec /, NULL / pfnLiveVote */,
4246	NULL /* pfnSavePrep /, dmarR3SaveExec, NULL / pfnSaveDone */,
4247	NULL /* pfnLoadPrep */, dmarR3LoadExec, dmarR3LoadDone);
4248	AssertLogRelRCReturn(rc, rc);
4249
4250	/*
4251	* Register debugger info items.
4252	*/
4253	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
4254	AssertLogRelRCReturn(rc, rc);
4255
4256	#ifdef VBOX_WITH_STATISTICS
4257	/*
4258	* Statistics.
4259	*/
4260	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
4261	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
4262
4263	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
4264	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
4265
4266	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
4267	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
4268	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
4269	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
4270
4271	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
4272	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
4273
4274	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
4275	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
4276
4277	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
4278	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
4279
4280	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4281	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4282
4283	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
4284	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
4285	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
4286	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
4287	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
4288	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
4289	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
4290	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
4291	#endif
4292
4293	/*
4294	* Initialize registers.
4295	*/
4296	dmarR3RegsInit(pDevIns);
4297
4298	/*
4299	* Create invalidation-queue thread and semaphore.
4300	*/
4301	char szInvQueueThread[32];
4302	RT_ZERO(szInvQueueThread);
4303	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4304	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4305	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4306	AssertLogRelRCReturn(rc, rc);
4307
4308	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4309	AssertLogRelRCReturn(rc, rc);
4310
4311	/*
4312	* Log some of the features exposed to software.
4313	*/
4314	uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4315	uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4316	uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4317	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4318	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4319	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4320	LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4321	DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4322	LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4323	DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4324	pThis->fMgawInvMask, offFrcd, offIva));
4325	return VINF_SUCCESS;
4326	}
4327
4328	#else
4329
4330	/**
4331	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4332	*/
4333	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4334	{
4335	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4336	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4337	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4338	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4339
4340	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
4341	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4342	AssertRCReturn(rc, rc);
4343
4344	/* Set up the MMIO RZ handlers. */
4345	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4346	AssertRCReturn(rc, rc);
4347
4348	/* Set up the IOMMU RZ callbacks. */
4349	PDMIOMMUREGCC IommuReg;
4350	RT_ZERO(IommuReg);
4351	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4352	IommuReg.idxIommu = pThis->idxIommu;
4353	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4354	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4355	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4356	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4357
4358	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4359	AssertRCReturn(rc, rc);
4360	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4361	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4362	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4363	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4364	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4365	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4366	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4367
4368	return VINF_SUCCESS;
4369	}
4370
4371	#endif
4372
4373
4374	/**
4375	* The device registration structure.
4376	*/
4377	PDMDEVREG const g_DeviceIommuIntel =
4378	{
4379	/* .u32Version = */ PDM_DEVREG_VERSION,
4380	/* .uReserved0 = */ 0,
4381	/* .szName = */ "iommu-intel",
4382	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4383	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4384	/* .cMaxInstances = */ 1,
4385	/* .uSharedVersion = */ 42,
4386	/* .cbInstanceShared = */ sizeof(DMAR),
4387	/* .cbInstanceCC = */ sizeof(DMARCC),
4388	/* .cbInstanceRC = */ sizeof(DMARRC),
4389	/* .cMaxPciDevices = */ 1,
4390	/* .cMaxMsixVectors = */ 0,
4391	/* .pszDescription = */ "IOMMU (Intel)",
4392	#if defined(IN_RING3)
4393	/* .pszRCMod = */ "VBoxDDRC.rc",
4394	/* .pszR0Mod = */ "VBoxDDR0.r0",
4395	/* .pfnConstruct = */ iommuIntelR3Construct,
4396	/* .pfnDestruct = */ iommuIntelR3Destruct,
4397	/* .pfnRelocate = */ NULL,
4398	/* .pfnMemSetup = */ NULL,
4399	/* .pfnPowerOn = */ NULL,
4400	/* .pfnReset = */ iommuIntelR3Reset,
4401	/* .pfnSuspend = */ NULL,
4402	/* .pfnResume = */ NULL,
4403	/* .pfnAttach = */ NULL,
4404	/* .pfnDetach = */ NULL,
4405	/* .pfnQueryInterface = */ NULL,
4406	/* .pfnInitComplete = */ NULL,
4407	/* .pfnPowerOff = */ NULL,
4408	/* .pfnSoftReset = */ NULL,
4409	/* .pfnReserved0 = */ NULL,
4410	/* .pfnReserved1 = */ NULL,
4411	/* .pfnReserved2 = */ NULL,
4412	/* .pfnReserved3 = */ NULL,
4413	/* .pfnReserved4 = */ NULL,
4414	/* .pfnReserved5 = */ NULL,
4415	/* .pfnReserved6 = */ NULL,
4416	/* .pfnReserved7 = */ NULL,
4417	#elif defined(IN_RING0)
4418	/* .pfnEarlyConstruct = */ NULL,
4419	/* .pfnConstruct = */ iommuIntelRZConstruct,
4420	/* .pfnDestruct = */ NULL,
4421	/* .pfnFinalDestruct = */ NULL,
4422	/* .pfnRequest = */ NULL,
4423	/* .pfnReserved0 = */ NULL,
4424	/* .pfnReserved1 = */ NULL,
4425	/* .pfnReserved2 = */ NULL,
4426	/* .pfnReserved3 = */ NULL,
4427	/* .pfnReserved4 = */ NULL,
4428	/* .pfnReserved5 = */ NULL,
4429	/* .pfnReserved6 = */ NULL,
4430	/* .pfnReserved7 = */ NULL,
4431	#elif defined(IN_RC)
4432	/* .pfnConstruct = */ iommuIntelRZConstruct,
4433	/* .pfnReserved0 = */ NULL,
4434	/* .pfnReserved1 = */ NULL,
4435	/* .pfnReserved2 = */ NULL,
4436	/* .pfnReserved3 = */ NULL,
4437	/* .pfnReserved4 = */ NULL,
4438	/* .pfnReserved5 = */ NULL,
4439	/* .pfnReserved6 = */ NULL,
4440	/* .pfnReserved7 = */ NULL,
4441	#else
4442	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4443	#endif
4444	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4445	};
4446
4447	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4448

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89706

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