DevIommuIntel.cpp@ 88385

Last change on this file since 88385 was 88370, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 WIP.
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1	/* $Id: DevIommuIntel.cpp 88370 2021-04-05 12:16:49Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/string.h>
27
28
29	/*********************************************************************************************************************************
30	* Defined Constants And Macros *
31	*********************************************************************************************************************************/
32	/** Gets the low uint32_t of a uint64_t or something equivalent.
33	*
34	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
35	* used as it asserts for correctness when compiling on certain compilers). */
36	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
37
38	/** Gets the high uint32_t of a uint64_t or something equivalent.
39	*
40	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
41	* used as it asserts for correctness when compiling on certain compilers). */
42	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
43
44	/** Asserts MMIO access' offset and size are valid or returns appropriate error
45	* code suitable for returning from MMIO access handlers. */
46	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
47	do { \
48	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
49	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
50	} while (0);
51
52	/** Checks whether the MMIO offset is valid. */
53	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
54	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
55
56	/** The number of fault recording registers our implementation supports.
57	* Normal guest operation shouldn't trigger faults anyway, so we only support the
58	* minimum number of registers (which is 1).
59	*
60	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG::NFR). */
61	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
62
63	/** Offset of first register in group 0. */
64	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
65	/** Offset of last register in group 0 (inclusive). */
66	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
67	/** Last valid offset in group 0 (exclusive). */
68	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
69	/** Size of the group 0 (in bytes). */
70	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
71
72	#define DMAR_MMIO_OFF_IVA_REG 0xe40 /*< Implementation-specific MMIO offset of IVA_REG. /
73	#define DMAR_MMIO_OFF_IOTLB_REG 0xe48 /*< Implementation-specific MMIO offset of IOTLB_REG. /
74	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe60 /*< Implementation-specific MMIO offset of FRCD_LO_REG. /
75	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe68 /*< Implementation-specific MMIO offset of FRCD_HI_REG. /
76	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
77
78	/** Offset of first register in group 1. */
79	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
80	/** Offset of last register in group 1 (inclusive). */
81	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
82	/** Last valid offset in group 1 (exclusive). */
83	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
84	/** Size of the group 1 (in bytes). */
85	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
86
87	/** Release log prefix string. */
88	#define DMAR_LOG_PFX "Intel-IOMMU"
89
90	/** The current saved state version. */
91	#define DMAR_SAVED_STATE_VERSION 1
92
93
94	/*********************************************************************************************************************************
95	* Structures and Typedefs *
96	*********************************************************************************************************************************/
97	/**
98	* The shared DMAR device state.
99	*/
100	typedef struct DMAR
101	{
102	/** IOMMU device index. */
103	uint32_t idxIommu;
104	/** DMAR magic. */
105	uint32_t u32Magic;
106
107	/** The MMIO handle. */
108	IOMMMIOHANDLE hMmio;
109
110	/** DMAR registers (group 0). */
111	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
112	/** DMAR registers (group 1). */
113	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
114
115	#ifdef VBOX_WITH_STATISTICS
116	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
117	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
118	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
119	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
120
121	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
122	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
123
124	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
125	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
126	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
127	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
128
129	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
130	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
131	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
132	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
133	#endif
134	} DMAR;
135	/** Pointer to the DMAR device state. */
136	typedef DMAR *PDMAR;
137	/** Pointer to the const DMAR device state. */
138	typedef const DMAR *PCDMAR;
139
140	/**
141	* The ring-3 DMAR device state.
142	*/
143	typedef struct DMARR3
144	{
145	/** Device instance. */
146	PPDMDEVINSR3 pDevInsR3;
147	/** The IOMMU helper. */
148	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
149	} DMARR3;
150	/** Pointer to the ring-3 DMAR device state. */
151	typedef DMARR3 *PDMARR3;
152	/** Pointer to the const ring-3 DMAR device state. */
153	typedef const DMARR3 *PCDMARR3;
154
155	/**
156	* The ring-0 DMAR device state.
157	*/
158	typedef struct DMARR0
159	{
160	/** Device instance. */
161	PPDMDEVINSR0 pDevInsR0;
162	/** The IOMMU helper. */
163	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
164	} DMARR0;
165	/** Pointer to the ring-0 IOMMU device state. */
166	typedef DMARR0 *PDMARR0;
167	/** Pointer to the const ring-0 IOMMU device state. */
168	typedef const DMARR0 *PCDMARR0;
169
170	/**
171	* The raw-mode DMAR device state.
172	*/
173	typedef struct DMARRC
174	{
175	/** Device instance. */
176	PPDMDEVINSRC pDevInsRC;
177	/** The IOMMU helper. */
178	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
179	} DMARRC;
180	/** Pointer to the raw-mode DMAR device state. */
181	typedef DMARRC *PDMARRC;
182	/** Pointer to the const raw-mode DMAR device state. */
183	typedef const DMARRC *PCIDMARRC;
184
185	/** The DMAR device state for the current context. */
186	typedef CTX_SUFF(DMAR) DMARCC;
187	/** Pointer to the DMAR device state for the current context. */
188	typedef CTX_SUFF(PDMAR) PDMARCC;
189
190
191	/*********************************************************************************************************************************
192	* Global Variables *
193	*********************************************************************************************************************************/
194	/**
195	* Read-write masks for DMAR registers (group 0).
196	*/
197	static const uint32_t g_au32RwMasks0[] =
198	{
199	/* Offset Register Low High */
200	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
201	/* 0x004 Reserved */ 0,
202	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
203	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
204	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
205	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
206	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
207	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
208	/* 0x030 Reserved */ 0,
209	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
210	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
211	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
212	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
213	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
214	/* 0x048 Reserved */ 0, 0,
215	/* 0x050 Reserved */ 0, 0,
216	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
217	/* 0x060 Reserved */ 0,
218	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
219	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
220	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
221	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
222	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
223	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
224	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
225	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
226	/* 0x098 Reserved */ 0,
227	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
228	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
229	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
230	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
231	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
232	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
233	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
234	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
235	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
236	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
237	/* 0x0d8 Reserved */ 0,
238	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
239	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
240	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
241	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
242	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
243	/* 0x0f0 Reserved */ 0, 0,
244	/* 0x0f8 Reserved */ 0, 0,
245	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
246	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
247	/* 0x110 Reserved */ 0, 0,
248	/* 0x118 Reserved */ 0, 0,
249	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
250	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
251	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
252	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
253	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
254	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
255	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
256	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
257	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
258	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
259	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
260	/* 0x178 Reserved */ 0, 0,
261	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
262	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
263	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
264	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
265	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
266	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
267	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
268	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
269	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
270	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
271	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
272	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
273	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
274	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
275	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
276	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
277	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
278	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
279	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
280	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
281	};
282	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
283
284	/**
285	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
286	*/
287	static const uint32_t g_au32Rw1cMasks0[] =
288	{
289	/* Offset Register Low High */
290	/* 0x000 VER_REG */ 0,
291	/* 0x004 Reserved */ 0,
292	/* 0x008 CAP_REG */ 0, 0,
293	/* 0x010 ECAP_REG */ 0, 0,
294	/* 0x018 GCMD_REG */ 0,
295	/* 0x01c GSTS_REG */ 0,
296	/* 0x020 RTADDR_REG */ 0, 0,
297	/* 0x028 CCMD_REG */ 0, 0,
298	/* 0x030 Reserved */ 0,
299	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
300	/* 0x038 FECTL_REG */ 0,
301	/* 0x03c FEDATA_REG */ 0,
302	/* 0x040 FEADDR_REG */ 0,
303	/* 0x044 FEUADDR_REG */ 0,
304	/* 0x048 Reserved */ 0, 0,
305	/* 0x050 Reserved */ 0, 0,
306	/* 0x058 AFLOG_REG */ 0, 0,
307	/* 0x060 Reserved */ 0,
308	/* 0x064 PMEN_REG */ 0,
309	/* 0x068 PLMBASE_REG */ 0,
310	/* 0x06c PLMLIMIT_REG */ 0,
311	/* 0x070 PHMBASE_REG */ 0, 0,
312	/* 0x078 PHMLIMIT_REG */ 0, 0,
313	/* 0x080 IQH_REG */ 0, 0,
314	/* 0x088 IQT_REG */ 0, 0,
315	/* 0x090 IQA_REG */ 0, 0,
316	/* 0x098 Reserved */ 0,
317	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
318	/* 0x0a0 IECTL_REG */ 0,
319	/* 0x0a4 IEDATA_REG */ 0,
320	/* 0x0a8 IEADDR_REG */ 0,
321	/* 0x0ac IEUADDR_REG */ 0,
322	/* 0x0b0 IQERCD_REG */ 0, 0,
323	/* 0x0b8 IRTA_REG */ 0, 0,
324	/* 0x0c0 PQH_REG */ 0, 0,
325	/* 0x0c8 PQT_REG */ 0, 0,
326	/* 0x0d0 PQA_REG */ 0, 0,
327	/* 0x0d8 Reserved */ 0,
328	/* 0x0dc PRS_REG */ 0,
329	/* 0x0e0 PECTL_REG */ 0,
330	/* 0x0e4 PEDATA_REG */ 0,
331	/* 0x0e8 PEADDR_REG */ 0,
332	/* 0x0ec PEUADDR_REG */ 0,
333	/* 0x0f0 Reserved */ 0, 0,
334	/* 0x0f8 Reserved */ 0, 0,
335	/* 0x100 MTRRCAP_REG */ 0, 0,
336	/* 0x108 MTRRDEF_REG */ 0, 0,
337	/* 0x110 Reserved */ 0, 0,
338	/* 0x118 Reserved */ 0, 0,
339	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
340	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
341	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
342	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
343	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
344	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
345	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
346	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
347	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
348	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
349	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
350	/* 0x178 Reserved */ 0, 0,
351	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
352	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
353	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
354	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
355	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
356	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
357	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
358	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
359	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
360	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
361	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
362	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
363	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
364	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
365	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
366	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
367	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
368	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
369	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
370	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
371	};
372	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
373
374	/**
375	* Read-write masks for DMAR registers (group 1).
376	*/
377	static const uint32_t g_au32RwMasks1[] =
378	{
379	/* Offset Register Low High */
380	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
381	/* 0xe08 Reserved */ 0, 0,
382	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
383	/* 0xe18 VCMDRSVD_REG */ 0, 0,
384	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
385	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
386	/* 0xe30 Reserved */ 0, 0,
387	/* 0xe38 Reserved */ 0, 0,
388	/* 0xe40 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
389	/* 0xe48 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
390	/* 0xe50 Reserved */ 0, 0,
391	/* 0xe58 Reserved */ 0, 0,
392	/* 0xe60 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
393	/* 0xe68 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
394	};
395	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
396	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
397
398	/**
399	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
400	*/
401	static const uint32_t g_au32Rw1cMasks1[] =
402	{
403	/* Offset Register Low High */
404	/* 0xe00 VCCAP_REG */ 0, 0,
405	/* 0xe08 Reserved */ 0, 0,
406	/* 0xe10 VCMD_REG */ 0, 0,
407	/* 0xe18 VCMDRSVD_REG */ 0, 0,
408	/* 0xe20 VCRSP_REG */ 0, 0,
409	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
410	/* 0xe30 Reserved */ 0, 0,
411	/* 0xe38 Reserved */ 0, 0,
412	/* 0xe40 IVA_REG */ 0, 0,
413	/* 0xe48 IOTLB_REG */ 0, 0,
414	/* 0xe50 Reserved */ 0, 0,
415	/* 0xe58 Reserved */ 0, 0,
416	/* 0xe60 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
417	/* 0xe68 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
418	};
419	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
420
421	/** Array of RW masks for each register group. */
422	static const uint8_t g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
423
424	/** Array of RW1C masks for each register group. */
425	static const uint8_t g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
426
427	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
428	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
429
430
431	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
432
433	/**
434	* Gets the group the register belongs to given its MMIO offset.
435	*
436	* @returns Pointer to the first element of the register group.
437	* @param pThis The shared DMAR device state.
438	* @param offReg The MMIO offset of the register.
439	* @param cbReg The size of the access being made (for bounds checking on
440	* debug builds).
441	* @param pIdxGroup Where to store the index of the register group the register
442	* belongs to.
443	*/
444	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
445	{
446	uint16_t const offLast = offReg + cbReg - 1;
447	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
448	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
449
450	uint8_t *const apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
451	*pIdxGroup = !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
452	return apbRegs[*pIdxGroup];
453	}
454
455
456	/**
457	* Writes a 64-bit register with the exactly the supplied value.
458	*
459	* @param pThis The shared DMAR device state.
460	* @param offReg The MMIO offset of the register.
461	* @param uReg The 64-bit value to write.
462	*/
463	DECLINLINE(void) dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
464	{
465	uint8_t idxGroup;
466	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
467	NOREF(idxGroup);
468	(uint64_t )(pabRegs + offReg) = uReg;
469	}
470
471
472	/**
473	* Writes a 32-bit register with the exactly the supplied value.
474	*
475	* @param pThis The shared DMAR device state.
476	* @param offReg The MMIO offset of the register.
477	* @param uReg The 32-bit value to write.
478	*/
479	DECLINLINE(void) dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
480	{
481	uint8_t idxGroup;
482	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
483	NOREF(idxGroup);
484	(uint32_t )(pabRegs + offReg) = uReg;
485	}
486
487
488	/**
489	* Reads a 64-bit register with exactly the value it contains.
490	*
491	* @param pThis The shared DMAR device state.
492	* @param offReg The MMIO offset of the register.
493	* @param puReg Where to store the raw 64-bit register value.
494	* @param pfRwMask Where to store the RW mask corresponding to this register.
495	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
496	*/
497	DECLINLINE(void) dmarRegReadRaw64(PDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
498	{
499	uint8_t idxGroup;
500	uint8_t const *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
501	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
502	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
503	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
504	puReg = (uint64_t *)(pabRegs + offReg);
505	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
506	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
507	}
508
509
510	/**
511	* Reads a 32-bit register with exactly the value it contains.
512	*
513	* @param pThis The shared DMAR device state.
514	* @param offReg The MMIO offset of the register.
515	* @param puReg Where to store the raw 32-bit register value.
516	* @param pfRwMask Where to store the RW mask corresponding to this register.
517	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
518	*/
519	DECLINLINE(void) dmarRegReadRaw32(PDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
520	{
521	uint8_t idxGroup;
522	uint8_t const *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
523	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
524	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
525	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
526	puReg = (uint32_t *)(pabRegs + offReg);
527	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
528	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
529	}
530
531
532	/**
533	* Writes a 64-bit register as it would be when written by software.
534	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
535	*
536	* @param pThis The shared DMAR device state.
537	* @param offReg The MMIO offset of the register.
538	* @param uReg The 64-bit value to write.
539	*/
540	static void dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
541	{
542	/* Read current value from the 64-bit register. */
543	uint64_t uCurReg;
544	uint64_t fRwMask;
545	uint64_t fRw1cMask;
546	dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
547
548	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
549	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
550	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
551	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
552
553	/* Write new value to the 64-bit register. */
554	dmarRegWriteRaw64(pThis, offReg, uNewReg);
555	}
556
557
558	/**
559	* Writes a 32-bit register as it would be when written by software.
560	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
561	*
562	* @param pThis The shared DMAR device state.
563	* @param offReg The MMIO offset of the register.
564	* @param uReg The 32-bit value to write.
565	*/
566	static void dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
567	{
568	/* Read current value from the 32-bit register. */
569	uint32_t uCurReg;
570	uint32_t fRwMask;
571	uint32_t fRw1cMask;
572	dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
573
574	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
575	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
576	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
577	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
578
579	/* Write new value to the 32-bit register. */
580	dmarRegWriteRaw32(pThis, offReg, uNewReg);
581	}
582
583
584	/**
585	* Reads a 64-bit register as it would be when read by software.
586	*
587	* @returns The 64-bit register value.
588	* @param pThis The shared DMAR device state.
589	* @param offReg The MMIO offset of the register.
590	*/
591	static uint64_t dmarRegRead64(PDMAR pThis, uint16_t offReg)
592	{
593	uint64_t uCurReg;
594	uint64_t fRwMask;
595	uint64_t fRw1cMask;
596	dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
597	NOREF(fRwMask); NOREF(fRw1cMask);
598	return uCurReg;
599	}
600
601
602	/**
603	* Reads a 32-bit register as it would be when read by software.
604	*
605	* @returns The 32-bit register value.
606	* @param pThis The shared DMAR device state.
607	* @param offReg The MMIO offset of the register.
608	*/
609	static uint32_t dmarRegRead32(PDMAR pThis, uint16_t offReg)
610	{
611	uint32_t uCurReg;
612	uint32_t fRwMask;
613	uint32_t fRw1cMask;
614	dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
615	NOREF(fRwMask); NOREF(fRw1cMask);
616	return uCurReg;
617	}
618
619
620	/**
621	* Memory access bulk (one or more 4K pages) request from a device.
622	*
623	* @returns VBox status code.
624	* @param pDevIns The IOMMU device instance.
625	* @param idDevice The device ID (bus, device, function).
626	* @param cIovas The number of addresses being accessed.
627	* @param pauIovas The I/O virtual addresses for each page being accessed.
628	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
629	* @param paGCPhysSpa Where to store the translated physical addresses.
630	*
631	* @thread Any.
632	*/
633	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
634	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
635	{
636	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
637	return VERR_NOT_IMPLEMENTED;
638	}
639
640
641	/**
642	* Memory access transaction from a device.
643	*
644	* @returns VBox status code.
645	* @param pDevIns The IOMMU device instance.
646	* @param idDevice The device ID (bus, device, function).
647	* @param uIova The I/O virtual address being accessed.
648	* @param cbIova The size of the access.
649	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
650	* @param pGCPhysSpa Where to store the translated system physical address.
651	* @param pcbContiguous Where to store the number of contiguous bytes translated
652	* and permission-checked.
653	*
654	* @thread Any.
655	*/
656	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
657	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
658	{
659	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
660	return VERR_NOT_IMPLEMENTED;
661	}
662
663
664	/**
665	* Interrupt remap request from a device.
666	*
667	* @returns VBox status code.
668	* @param pDevIns The IOMMU device instance.
669	* @param idDevice The device ID (bus, device, function).
670	* @param pMsiIn The source MSI.
671	* @param pMsiOut Where to store the remapped MSI.
672	*/
673	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
674	{
675	RT_NOREF4(pDevIns, idDevice, pMsiIn, pMsiOut);
676	return VERR_NOT_IMPLEMENTED;
677	}
678
679
680	/**
681	* @callback_method_impl{FNIOMMMIONEWWRITE}
682	*/
683	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
684	{
685	RT_NOREF1(pvUser);
686	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
687
688	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
689	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
690
691	uint16_t const offReg = off;
692	uint16_t const offLast = offReg + cb - 1;
693	if (DMAR_IS_MMIO_OFF_VALID(offLast))
694	{
695	switch (off)
696	{
697	default:
698	{
699	if (cb == 8)
700	dmarRegWrite64(pThis, offReg, (uint64_t )pv);
701	else
702	dmarRegWrite32(pThis, offReg, (uint32_t )pv);
703	break;
704	}
705	}
706
707	LogFlowFunc(("offReg=%#x\n", offReg));
708	return VINF_SUCCESS;
709	}
710
711	return VINF_IOM_MMIO_UNUSED_FF;
712	}
713
714
715	/**
716	* @callback_method_impl{FNIOMMMIONEWREAD}
717	*/
718	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
719	{
720	RT_NOREF1(pvUser);
721	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
722
723	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
724	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
725
726	uint16_t const offReg = off;
727	uint16_t const offLast = offReg + cb - 1;
728	if (DMAR_IS_MMIO_OFF_VALID(offLast))
729	{
730	if (cb == 8)
731	(uint64_t )pv = dmarRegRead64(pThis, offReg);
732	else
733	(uint32_t )pv = dmarRegRead32(pThis, offReg);
734
735	LogFlowFunc(("offReg=%#x\n", offReg));
736	return VINF_SUCCESS;
737	}
738
739	return VINF_IOM_MMIO_UNUSED_FF;
740	}
741
742
743	#ifdef IN_RING3
744	/**
745	* @interface_method_impl{PDMDEVREG,pfnReset}
746	*/
747	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
748	{
749	RT_NOREF1(pDevIns);
750	LogFlowFunc(("\n"));
751	}
752
753
754	/**
755	* @interface_method_impl{PDMDEVREG,pfnDestruct}
756	*/
757	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
758	{
759	RT_NOREF(pDevIns);
760	LogFlowFunc(("\n"));
761	return VINF_SUCCESS;
762	}
763
764
765	/**
766	* @interface_method_impl{PDMDEVREG,pfnConstruct}
767	*/
768	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
769	{
770	RT_NOREF(pCfg);
771
772	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
773	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
774	pThisR3->pDevInsR3 = pDevIns;
775
776	LogFlowFunc(("iInstance=%d\n", iInstance));
777	NOREF(iInstance);
778
779	/*
780	* Register the IOMMU with PDM.
781	*/
782	PDMIOMMUREGR3 IommuReg;
783	RT_ZERO(IommuReg);
784	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
785	IommuReg.pfnMemAccess = iommuIntelMemAccess;
786	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
787	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
788	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
789	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
790	if (RT_FAILURE(rc))
791	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
792	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
793	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
794	N_("IOMMU helper version mismatch; got %#x expected %#x"),
795	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
796	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
797	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
798	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
799	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
800	/*
801	* Use PDM's critical section (via helpers) for the IOMMU device.
802	*/
803	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
804	AssertRCReturn(rc, rc);
805
806	/*
807	* Initialize PCI configuration registers.
808	*/
809	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
810	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
811
812	/* Header. */
813	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
814	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
815	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
816	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
817	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
818	PDMPciDevSetHeaderType(pPciDev, 0x0); /* Single function, type 0 */
819	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
820	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
821
822	/** @todo VTD: Chipset spec says PCI Express Capability Id. Relevant for us? */
823	PDMPciDevSetStatus(pPciDev, 0);
824	PDMPciDevSetCapabilityList(pPciDev, 0);
825
826	/** @todo VTD: VTBAR at 0x180? */
827
828	/*
829	* Register the PCI function with PDM.
830	*/
831	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
832	AssertLogRelRCReturn(rc, rc);
833
834	/** @todo VTD: Register MSI but what's the MSI capability offset? */
835	#if 0
836	/*
837	* Register MSI support for the PCI device.
838	* This must be done -after- registering it as a PCI device!
839	*/
840	#endif
841
842	/** @todo VTD: Intercept PCI config space accesses for debugging. */
843	#if 0
844	/*
845	* Intercept PCI config. space accesses.
846	*/
847	rc = PDMDevHlpPCIInterceptConfigAccesses(pDevIns, pPciDev, ..);
848	AssertLogRelRCReturn(rc, rc);
849	#endif
850
851	/*
852	* Register MMIO region.
853	*/
854	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
855	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
856	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
857	"Intel-IOMMU", &pThis->hMmio);
858	AssertRCReturn(rc, rc);
859
860	# ifdef VBOX_WITH_STATISTICS
861	/*
862	* Statistics.
863	*/
864	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
865	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
866
867	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
868	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
869
870	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
871	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
872
873	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
874	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
875
876	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
877	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
878
879	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
880	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
881
882	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
883	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
884	# endif
885
886	LogRel(("%s: Capabilities=%#RX64 Extended-Capabilities=%#RX64\n", DMAR_LOG_PFX, dmarRegRead64(pThis, VTD_MMIO_OFF_CAP_REG),
887	dmarRegRead64(pThis, VTD_MMIO_OFF_ECAP_REG)));
888	return VINF_SUCCESS;
889	}
890
891	#else
892
893	/**
894	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
895	*/
896	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
897	{
898	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
899	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
900	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
901	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
902
903	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
904	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
905	AssertRCReturn(rc, rc);
906
907	/* Set up the MMIO RZ handlers. */
908	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
909	AssertRCReturn(rc, rc);
910
911	/* Set up the IOMMU RZ callbacks. */
912	PDMIOMMUREGCC IommuReg;
913	RT_ZERO(IommuReg);
914	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
915	IommuReg.idxIommu = pThis->idxIommu;
916	IommuReg.pfnMemAccess = iommuIntelMemAccess;
917	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
918	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
919	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
920
921	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
922	AssertRCReturn(rc, rc);
923	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
924	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
925	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
926	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
927	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
928
929	return VINF_SUCCESS;
930	}
931
932	#endif
933
934
935	/**
936	* The device registration structure.
937	*/
938	const PDMDEVREG g_DeviceIommuIntel =
939	{
940	/* .u32Version = */ PDM_DEVREG_VERSION,
941	/* .uReserved0 = */ 0,
942	/* .szName = */ "iommu-intel",
943	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
944	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
945	/* .cMaxInstances = */ 1,
946	/* .uSharedVersion = */ 42,
947	/* .cbInstanceShared = */ sizeof(DMAR),
948	/* .cbInstanceCC = */ sizeof(DMARCC),
949	/* .cbInstanceRC = */ sizeof(DMARRC),
950	/* .cMaxPciDevices = / 1, /* @todo Make this 0 if this isn't a PCI device. */
951	/* .cMaxMsixVectors = */ 0,
952	/* .pszDescription = */ "IOMMU (Intel)",
953	#if defined(IN_RING3)
954	/* .pszRCMod = */ "VBoxDDRC.rc",
955	/* .pszR0Mod = */ "VBoxDDR0.r0",
956	/* .pfnConstruct = */ iommuIntelR3Construct,
957	/* .pfnDestruct = */ iommuIntelR3Destruct,
958	/* .pfnRelocate = */ NULL,
959	/* .pfnMemSetup = */ NULL,
960	/* .pfnPowerOn = */ NULL,
961	/* .pfnReset = */ iommuIntelR3Reset,
962	/* .pfnSuspend = */ NULL,
963	/* .pfnResume = */ NULL,
964	/* .pfnAttach = */ NULL,
965	/* .pfnDetach = */ NULL,
966	/* .pfnQueryInterface = */ NULL,
967	/* .pfnInitComplete = */ NULL,
968	/* .pfnPowerOff = */ NULL,
969	/* .pfnSoftReset = */ NULL,
970	/* .pfnReserved0 = */ NULL,
971	/* .pfnReserved1 = */ NULL,
972	/* .pfnReserved2 = */ NULL,
973	/* .pfnReserved3 = */ NULL,
974	/* .pfnReserved4 = */ NULL,
975	/* .pfnReserved5 = */ NULL,
976	/* .pfnReserved6 = */ NULL,
977	/* .pfnReserved7 = */ NULL,
978	#elif defined(IN_RING0)
979	/* .pfnEarlyConstruct = */ NULL,
980	/* .pfnConstruct = */ iommuIntelRZConstruct,
981	/* .pfnDestruct = */ NULL,
982	/* .pfnFinalDestruct = */ NULL,
983	/* .pfnRequest = */ NULL,
984	/* .pfnReserved0 = */ NULL,
985	/* .pfnReserved1 = */ NULL,
986	/* .pfnReserved2 = */ NULL,
987	/* .pfnReserved3 = */ NULL,
988	/* .pfnReserved4 = */ NULL,
989	/* .pfnReserved5 = */ NULL,
990	/* .pfnReserved6 = */ NULL,
991	/* .pfnReserved7 = */ NULL,
992	#elif defined(IN_RC)
993	/* .pfnConstruct = */ iommuIntelRZConstruct,
994	/* .pfnReserved0 = */ NULL,
995	/* .pfnReserved1 = */ NULL,
996	/* .pfnReserved2 = */ NULL,
997	/* .pfnReserved3 = */ NULL,
998	/* .pfnReserved4 = */ NULL,
999	/* .pfnReserved5 = */ NULL,
1000	/* .pfnReserved6 = */ NULL,
1001	/* .pfnReserved7 = */ NULL,
1002	#else
1003	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1004	#endif
1005	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1006	};
1007
1008	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1009

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88385

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