DevIommuIntel.cpp@ 88480

Last change on this file since 88480 was 88427, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 WIP.
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1	/* $Id: DevIommuIntel.cpp 88427 2021-04-09 10:14:43Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/string.h>
27
28
29	/*********************************************************************************************************************************
30	* Defined Constants And Macros *
31	*********************************************************************************************************************************/
32	/** Gets the low uint32_t of a uint64_t or something equivalent.
33	*
34	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
35	* used as it asserts for correctness when compiling on certain compilers). */
36	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
37
38	/** Gets the high uint32_t of a uint64_t or something equivalent.
39	*
40	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
41	* used as it asserts for correctness when compiling on certain compilers). */
42	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
43
44	/** Asserts MMIO access' offset and size are valid or returns appropriate error
45	* code suitable for returning from MMIO access handlers. */
46	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
47	do { \
48	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
49	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
50	} while (0);
51
52	/** Checks whether the MMIO offset is valid. */
53	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
54	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
55
56	/** @name DMAR implementation specifics.
57	* @{ */
58	/** The number of fault recording registers our implementation supports.
59	* Normal guest operation shouldn't trigger faults anyway, so we only support the
60	* minimum number of registers (which is 1).
61	*
62	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG::NFR). */
63	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
64
65	/** Offset of first register in group 0. */
66	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
67	/** Offset of last register in group 0 (inclusive). */
68	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
69	/** Last valid offset in group 0 (exclusive). */
70	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
71	/** Size of the group 0 (in bytes). */
72	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
73	/*< Implementation-specific MMIO offset of IVA_REG. /
74	#define DMAR_MMIO_OFF_IVA_REG 0xe40
75	/*< Implementation-specific MMIO offset of IOTLB_REG. /
76	#define DMAR_MMIO_OFF_IOTLB_REG 0xe48
77	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
78	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe60
79	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
80	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe68
81	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
82
83	/** Offset of first register in group 1. */
84	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
85	/** Offset of last register in group 1 (inclusive). */
86	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
87	/** Last valid offset in group 1 (exclusive). */
88	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
89	/** Size of the group 1 (in bytes). */
90	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
91
92	/** DMAR implementation's minor version number (exposed to software). */
93	#define DMAR_VER_MINOR 0
94	/** DMAR implementation's major version number (exposed to software). */
95	#define DMAR_VER_MAJOR 1
96	/** @} */
97
98	/** Release log prefix string. */
99	#define DMAR_LOG_PFX "Intel-IOMMU"
100	/** The current saved state version. */
101	#define DMAR_SAVED_STATE_VERSION 1
102
103
104	/*********************************************************************************************************************************
105	* Structures and Typedefs *
106	*********************************************************************************************************************************/
107	/**
108	* The shared DMAR device state.
109	*/
110	typedef struct DMAR
111	{
112	/** IOMMU device index. */
113	uint32_t idxIommu;
114	/** DMAR magic. */
115	uint32_t u32Magic;
116
117	/** The MMIO handle. */
118	IOMMMIOHANDLE hMmio;
119
120	/** Registers (group 0). */
121	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
122	/** Registers (group 1). */
123	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
124
125	/** @name Register copies for a tiny bit faster and more convenient access.
126	* @{ */
127	/** Copy of CAP_REG. */
128	uint64_t fCap;
129	/** Copy of ECAP_REG. */
130	uint64_t fExtCap;
131	/** @} */
132
133	#ifdef VBOX_WITH_STATISTICS
134	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
135	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
136	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
137	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
138
139	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
140	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
141
142	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
143	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
144	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
145	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
146
147	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
148	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
149	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
150	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
151	#endif
152	} DMAR;
153	/** Pointer to the DMAR device state. */
154	typedef DMAR *PDMAR;
155	/** Pointer to the const DMAR device state. */
156	typedef const DMAR *PCDMAR;
157
158	/**
159	* The ring-3 DMAR device state.
160	*/
161	typedef struct DMARR3
162	{
163	/** Device instance. */
164	PPDMDEVINSR3 pDevInsR3;
165	/** The IOMMU helper. */
166	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
167	} DMARR3;
168	/** Pointer to the ring-3 DMAR device state. */
169	typedef DMARR3 *PDMARR3;
170	/** Pointer to the const ring-3 DMAR device state. */
171	typedef const DMARR3 *PCDMARR3;
172
173	/**
174	* The ring-0 DMAR device state.
175	*/
176	typedef struct DMARR0
177	{
178	/** Device instance. */
179	PPDMDEVINSR0 pDevInsR0;
180	/** The IOMMU helper. */
181	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
182	} DMARR0;
183	/** Pointer to the ring-0 IOMMU device state. */
184	typedef DMARR0 *PDMARR0;
185	/** Pointer to the const ring-0 IOMMU device state. */
186	typedef const DMARR0 *PCDMARR0;
187
188	/**
189	* The raw-mode DMAR device state.
190	*/
191	typedef struct DMARRC
192	{
193	/** Device instance. */
194	PPDMDEVINSRC pDevInsRC;
195	/** The IOMMU helper. */
196	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
197	} DMARRC;
198	/** Pointer to the raw-mode DMAR device state. */
199	typedef DMARRC *PDMARRC;
200	/** Pointer to the const raw-mode DMAR device state. */
201	typedef const DMARRC *PCIDMARRC;
202
203	/** The DMAR device state for the current context. */
204	typedef CTX_SUFF(DMAR) DMARCC;
205	/** Pointer to the DMAR device state for the current context. */
206	typedef CTX_SUFF(PDMAR) PDMARCC;
207
208
209	/*********************************************************************************************************************************
210	* Global Variables *
211	*********************************************************************************************************************************/
212	/**
213	* Read-write masks for DMAR registers (group 0).
214	*/
215	static const uint32_t g_au32RwMasks0[] =
216	{
217	/* Offset Register Low High */
218	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
219	/* 0x004 Reserved */ 0,
220	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
221	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
222	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
223	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
224	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
225	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
226	/* 0x030 Reserved */ 0,
227	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
228	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
229	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
230	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
231	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
232	/* 0x048 Reserved */ 0, 0,
233	/* 0x050 Reserved */ 0, 0,
234	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
235	/* 0x060 Reserved */ 0,
236	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
237	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
238	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
239	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
240	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
241	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
242	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
243	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
244	/* 0x098 Reserved */ 0,
245	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
246	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
247	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
248	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
249	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
250	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
251	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
252	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
253	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
254	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
255	/* 0x0d8 Reserved */ 0,
256	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
257	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
258	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
259	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
260	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
261	/* 0x0f0 Reserved */ 0, 0,
262	/* 0x0f8 Reserved */ 0, 0,
263	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
264	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
265	/* 0x110 Reserved */ 0, 0,
266	/* 0x118 Reserved */ 0, 0,
267	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
268	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
269	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
270	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
271	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
272	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
273	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
274	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
275	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
276	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
277	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
278	/* 0x178 Reserved */ 0, 0,
279	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
280	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
281	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
282	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
283	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
284	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
285	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
286	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
287	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
288	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
289	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
290	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
291	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
292	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
293	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
294	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
295	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
296	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
297	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
298	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
299	};
300	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
301
302	/**
303	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
304	*/
305	static const uint32_t g_au32Rw1cMasks0[] =
306	{
307	/* Offset Register Low High */
308	/* 0x000 VER_REG */ 0,
309	/* 0x004 Reserved */ 0,
310	/* 0x008 CAP_REG */ 0, 0,
311	/* 0x010 ECAP_REG */ 0, 0,
312	/* 0x018 GCMD_REG */ 0,
313	/* 0x01c GSTS_REG */ 0,
314	/* 0x020 RTADDR_REG */ 0, 0,
315	/* 0x028 CCMD_REG */ 0, 0,
316	/* 0x030 Reserved */ 0,
317	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
318	/* 0x038 FECTL_REG */ 0,
319	/* 0x03c FEDATA_REG */ 0,
320	/* 0x040 FEADDR_REG */ 0,
321	/* 0x044 FEUADDR_REG */ 0,
322	/* 0x048 Reserved */ 0, 0,
323	/* 0x050 Reserved */ 0, 0,
324	/* 0x058 AFLOG_REG */ 0, 0,
325	/* 0x060 Reserved */ 0,
326	/* 0x064 PMEN_REG */ 0,
327	/* 0x068 PLMBASE_REG */ 0,
328	/* 0x06c PLMLIMIT_REG */ 0,
329	/* 0x070 PHMBASE_REG */ 0, 0,
330	/* 0x078 PHMLIMIT_REG */ 0, 0,
331	/* 0x080 IQH_REG */ 0, 0,
332	/* 0x088 IQT_REG */ 0, 0,
333	/* 0x090 IQA_REG */ 0, 0,
334	/* 0x098 Reserved */ 0,
335	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
336	/* 0x0a0 IECTL_REG */ 0,
337	/* 0x0a4 IEDATA_REG */ 0,
338	/* 0x0a8 IEADDR_REG */ 0,
339	/* 0x0ac IEUADDR_REG */ 0,
340	/* 0x0b0 IQERCD_REG */ 0, 0,
341	/* 0x0b8 IRTA_REG */ 0, 0,
342	/* 0x0c0 PQH_REG */ 0, 0,
343	/* 0x0c8 PQT_REG */ 0, 0,
344	/* 0x0d0 PQA_REG */ 0, 0,
345	/* 0x0d8 Reserved */ 0,
346	/* 0x0dc PRS_REG */ 0,
347	/* 0x0e0 PECTL_REG */ 0,
348	/* 0x0e4 PEDATA_REG */ 0,
349	/* 0x0e8 PEADDR_REG */ 0,
350	/* 0x0ec PEUADDR_REG */ 0,
351	/* 0x0f0 Reserved */ 0, 0,
352	/* 0x0f8 Reserved */ 0, 0,
353	/* 0x100 MTRRCAP_REG */ 0, 0,
354	/* 0x108 MTRRDEF_REG */ 0, 0,
355	/* 0x110 Reserved */ 0, 0,
356	/* 0x118 Reserved */ 0, 0,
357	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
358	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
359	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
360	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
361	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
362	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
363	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
364	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
365	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
366	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
367	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
368	/* 0x178 Reserved */ 0, 0,
369	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
370	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
371	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
372	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
373	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
374	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
375	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
376	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
377	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
378	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
379	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
380	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
381	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
382	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
383	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
384	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
385	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
386	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
387	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
388	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
389	};
390	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
391
392	/**
393	* Read-write masks for DMAR registers (group 1).
394	*/
395	static const uint32_t g_au32RwMasks1[] =
396	{
397	/* Offset Register Low High */
398	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
399	/* 0xe08 Reserved */ 0, 0,
400	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
401	/* 0xe18 VCMDRSVD_REG */ 0, 0,
402	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
403	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
404	/* 0xe30 Reserved */ 0, 0,
405	/* 0xe38 Reserved */ 0, 0,
406	/* 0xe40 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
407	/* 0xe48 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
408	/* 0xe50 Reserved */ 0, 0,
409	/* 0xe58 Reserved */ 0, 0,
410	/* 0xe60 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
411	/* 0xe68 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
412	};
413	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
414	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
415
416	/**
417	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
418	*/
419	static const uint32_t g_au32Rw1cMasks1[] =
420	{
421	/* Offset Register Low High */
422	/* 0xe00 VCCAP_REG */ 0, 0,
423	/* 0xe08 Reserved */ 0, 0,
424	/* 0xe10 VCMD_REG */ 0, 0,
425	/* 0xe18 VCMDRSVD_REG */ 0, 0,
426	/* 0xe20 VCRSP_REG */ 0, 0,
427	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
428	/* 0xe30 Reserved */ 0, 0,
429	/* 0xe38 Reserved */ 0, 0,
430	/* 0xe40 IVA_REG */ 0, 0,
431	/* 0xe48 IOTLB_REG */ 0, 0,
432	/* 0xe50 Reserved */ 0, 0,
433	/* 0xe58 Reserved */ 0, 0,
434	/* 0xe60 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
435	/* 0xe68 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
436	};
437	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
438
439	/** Array of RW masks for each register group. */
440	static const uint8_t g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
441
442	/** Array of RW1C masks for each register group. */
443	static const uint8_t g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
444
445	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
446	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
447
448
449	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
450	/**
451	* Gets the number of supported adjusted guest-address width (SAGAW) in bits given a
452	* CAP_REG.SAGAW value.
453	*
454	* @returns Number of SAGAW bits.
455	* @param uSagaw The CAP_REG.SAGAW value.
456	*/
457	static uint8_t vtdGetSupGstAddrBits(uint8_t uSagaw)
458	{
459	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
460	return 30 + (uSagaw * 9);
461	return 0;
462	}
463
464
465	/**
466	* Gets the supported adjusted guest-address width (SAGAW) given the maximum guest
467	* address width (MGAW).
468	*
469	* @returns The CAP.SAGAW value.
470	* @param uMgaw The CAP_REG.MGAW value.
471	*/
472	static uint8_t vtdGetSupGstAddrWidth(uint8_t uMgaw)
473	{
474	switch (uMgaw + 1)
475	{
476	case 39: return 1;
477	case 48: return 2;
478	case 57: return 3;
479	}
480	return 0;
481	}
482
483
484	/**
485	* Gets the group the register belongs to given its MMIO offset.
486	*
487	* @returns Pointer to the first element of the register group.
488	* @param pThis The shared DMAR device state.
489	* @param offReg The MMIO offset of the register.
490	* @param cbReg The size of the access being made (for bounds checking on
491	* debug builds).
492	* @param pIdxGroup Where to store the index of the register group the register
493	* belongs to.
494	*/
495	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
496	{
497	uint16_t const offLast = offReg + cbReg - 1;
498	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
499	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
500
501	uint8_t *const apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
502	*pIdxGroup = !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
503	return apbRegs[*pIdxGroup];
504	}
505
506
507	/**
508	* Writes a 64-bit register with the exactly the supplied value.
509	*
510	* @param pThis The shared DMAR device state.
511	* @param offReg The MMIO offset of the register.
512	* @param uReg The 64-bit value to write.
513	*/
514	DECLINLINE(void) dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
515	{
516	uint8_t idxGroup;
517	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
518	NOREF(idxGroup);
519	(uint64_t )(pabRegs + offReg) = uReg;
520	}
521
522
523	/**
524	* Writes a 32-bit register with the exactly the supplied value.
525	*
526	* @param pThis The shared DMAR device state.
527	* @param offReg The MMIO offset of the register.
528	* @param uReg The 32-bit value to write.
529	*/
530	DECLINLINE(void) dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
531	{
532	uint8_t idxGroup;
533	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
534	NOREF(idxGroup);
535	(uint32_t )(pabRegs + offReg) = uReg;
536	}
537
538
539	/**
540	* Reads a 64-bit register with exactly the value it contains.
541	*
542	* @param pThis The shared DMAR device state.
543	* @param offReg The MMIO offset of the register.
544	* @param puReg Where to store the raw 64-bit register value.
545	* @param pfRwMask Where to store the RW mask corresponding to this register.
546	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
547	*/
548	DECLINLINE(void) dmarRegReadRaw64(PDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
549	{
550	uint8_t idxGroup;
551	uint8_t const *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
552	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
553	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
554	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
555	puReg = (uint64_t *)(pabRegs + offReg);
556	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
557	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
558	}
559
560
561	/**
562	* Reads a 32-bit register with exactly the value it contains.
563	*
564	* @param pThis The shared DMAR device state.
565	* @param offReg The MMIO offset of the register.
566	* @param puReg Where to store the raw 32-bit register value.
567	* @param pfRwMask Where to store the RW mask corresponding to this register.
568	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
569	*/
570	DECLINLINE(void) dmarRegReadRaw32(PDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
571	{
572	uint8_t idxGroup;
573	uint8_t const *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
574	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
575	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
576	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
577	puReg = (uint32_t *)(pabRegs + offReg);
578	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
579	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
580	}
581
582
583	/**
584	* Writes a 64-bit register as it would be when written by software.
585	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
586	*
587	* @param pThis The shared DMAR device state.
588	* @param offReg The MMIO offset of the register.
589	* @param uReg The 64-bit value to write.
590	*/
591	static void dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
592	{
593	/* Read current value from the 64-bit register. */
594	uint64_t uCurReg;
595	uint64_t fRwMask;
596	uint64_t fRw1cMask;
597	dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
598
599	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
600	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
601	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
602	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
603
604	/* Write new value to the 64-bit register. */
605	dmarRegWriteRaw64(pThis, offReg, uNewReg);
606	}
607
608
609	/**
610	* Writes a 32-bit register as it would be when written by software.
611	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
612	*
613	* @param pThis The shared DMAR device state.
614	* @param offReg The MMIO offset of the register.
615	* @param uReg The 32-bit value to write.
616	*/
617	static void dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
618	{
619	/* Read current value from the 32-bit register. */
620	uint32_t uCurReg;
621	uint32_t fRwMask;
622	uint32_t fRw1cMask;
623	dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
624
625	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
626	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
627	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
628	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
629
630	/* Write new value to the 32-bit register. */
631	dmarRegWriteRaw32(pThis, offReg, uNewReg);
632	}
633
634
635	/**
636	* Reads a 64-bit register as it would be when read by software.
637	*
638	* @returns The 64-bit register value.
639	* @param pThis The shared DMAR device state.
640	* @param offReg The MMIO offset of the register.
641	*/
642	static uint64_t dmarRegRead64(PDMAR pThis, uint16_t offReg)
643	{
644	uint64_t uCurReg;
645	uint64_t fRwMask;
646	uint64_t fRw1cMask;
647	dmarRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
648	NOREF(fRwMask); NOREF(fRw1cMask);
649	return uCurReg;
650	}
651
652
653	/**
654	* Reads a 32-bit register as it would be when read by software.
655	*
656	* @returns The 32-bit register value.
657	* @param pThis The shared DMAR device state.
658	* @param offReg The MMIO offset of the register.
659	*/
660	static uint32_t dmarRegRead32(PDMAR pThis, uint16_t offReg)
661	{
662	uint32_t uCurReg;
663	uint32_t fRwMask;
664	uint32_t fRw1cMask;
665	dmarRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
666	NOREF(fRwMask); NOREF(fRw1cMask);
667	return uCurReg;
668	}
669
670
671	/**
672	* Memory access bulk (one or more 4K pages) request from a device.
673	*
674	* @returns VBox status code.
675	* @param pDevIns The IOMMU device instance.
676	* @param idDevice The device ID (bus, device, function).
677	* @param cIovas The number of addresses being accessed.
678	* @param pauIovas The I/O virtual addresses for each page being accessed.
679	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
680	* @param paGCPhysSpa Where to store the translated physical addresses.
681	*
682	* @thread Any.
683	*/
684	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
685	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
686	{
687	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
688	return VERR_NOT_IMPLEMENTED;
689	}
690
691
692	/**
693	* Memory access transaction from a device.
694	*
695	* @returns VBox status code.
696	* @param pDevIns The IOMMU device instance.
697	* @param idDevice The device ID (bus, device, function).
698	* @param uIova The I/O virtual address being accessed.
699	* @param cbIova The size of the access.
700	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
701	* @param pGCPhysSpa Where to store the translated system physical address.
702	* @param pcbContiguous Where to store the number of contiguous bytes translated
703	* and permission-checked.
704	*
705	* @thread Any.
706	*/
707	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
708	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
709	{
710	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
711	return VERR_NOT_IMPLEMENTED;
712	}
713
714
715	/**
716	* Interrupt remap request from a device.
717	*
718	* @returns VBox status code.
719	* @param pDevIns The IOMMU device instance.
720	* @param idDevice The device ID (bus, device, function).
721	* @param pMsiIn The source MSI.
722	* @param pMsiOut Where to store the remapped MSI.
723	*/
724	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
725	{
726	RT_NOREF3(idDevice, pMsiIn, pMsiOut);
727	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
728	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap)); NOREF(pThis);
729
730	return VERR_NOT_IMPLEMENTED;
731	}
732
733
734	/**
735	* @callback_method_impl{FNIOMMMIONEWWRITE}
736	*/
737	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
738	{
739	RT_NOREF1(pvUser);
740	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
741
742	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
743	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
744
745	uint16_t const offReg = off;
746	uint16_t const offLast = offReg + cb - 1;
747	if (DMAR_IS_MMIO_OFF_VALID(offLast))
748	{
749	switch (off)
750	{
751	default:
752	{
753	if (cb == 8)
754	dmarRegWrite64(pThis, offReg, (uint64_t )pv);
755	else
756	dmarRegWrite32(pThis, offReg, (uint32_t )pv);
757	break;
758	}
759	}
760
761	LogFlowFunc(("offReg=%#x\n", offReg));
762	return VINF_SUCCESS;
763	}
764
765	return VINF_IOM_MMIO_UNUSED_FF;
766	}
767
768
769	/**
770	* @callback_method_impl{FNIOMMMIONEWREAD}
771	*/
772	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
773	{
774	RT_NOREF1(pvUser);
775	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
776
777	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
778	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
779
780	uint16_t const offReg = off;
781	uint16_t const offLast = offReg + cb - 1;
782	if (DMAR_IS_MMIO_OFF_VALID(offLast))
783	{
784	if (cb == 8)
785	(uint64_t )pv = dmarRegRead64(pThis, offReg);
786	else
787	(uint32_t )pv = dmarRegRead32(pThis, offReg);
788
789	LogFlowFunc(("offReg=%#x\n", offReg));
790	return VINF_SUCCESS;
791	}
792
793	return VINF_IOM_MMIO_UNUSED_FF;
794	}
795
796
797	#ifdef IN_RING3
798	/**
799	* Initializes all registers in the DMAR unit.
800	*
801	* @param pDevIns The IOMMU device instance.
802	*/
803	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
804	{
805	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
806	RT_ZERO(pThis->abRegs0);
807	RT_ZERO(pThis->abRegs1);
808
809	/*
810	* Initialize registers not mutable by software prior to initializing other registers.
811	*/
812	/* VER_REG */
813	{
814	uint8_t const uVer = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
815	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
816	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, uVer);
817	}
818
819	uint8_t const fFlts = 1; /* First-Level translation support. */
820	uint8_t const fSlts = 1; /* Second-Level translation support. */
821	uint8_t const fPt = 1; /* Pass-Through support. */
822	uint8_t const fNest = 0; /* Nested translation support. */
823	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
824
825	/* CAP_REG */
826	{
827	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
828	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
829	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
830	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
831	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
832	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
833	uint8_t const fMamv = (fSl2gp ? /* Maximum address mask value (for second-level invalidations). */
834	X86_PAGE_1G_SHIFT : X86_PAGE_2M_SHIFT) - X86_PAGE_4K_SHIFT;
835	uint8_t const fNd = 2; /* Number of domains (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
836	7=Reserved). */
837	uint8_t const fPsi = 1; /* Page selective invalidation. */
838	uint8_t cGstPhysAddrBits;
839	uint8_t cGstLinearAddrBits;
840	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
841	NOREF(cGstLinearAddrBits);
842	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
843	uint8_t const uSagaw = vtdGetSupGstAddrWidth(uMgaw); /* Supported adjust guest address width. */
844
845	pThis->fCap = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
846	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
847	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
848	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
849	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
850	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
851	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
852	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
853	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
854	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, DMAR_MMIO_OFF_FRCD_LO_REG >> 4)
855	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
856	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
857	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
858	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
859	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
860	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
861	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
862	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp);
863	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCap);
864	}
865
866	/* ECAP_REG */
867	{
868	uint8_t const fIr = 1; /* Interrupt remapping support. */
869	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
870	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
871	uint8_t const fSrs = 1; /* Supervisor request support. */
872	uint8_t const fEim = 1; /* Extended interrupt mode.*/
873
874	pThis->fExtCap = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
875	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, 1)
876	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
877	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fIr)
878	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
879	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
880	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
881	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
882	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
883	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
884	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
885	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
886	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
887	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
888	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
889	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as PASID not supported. */
890	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
891	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
892	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
893	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
894	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
895	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
896	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
897	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
898	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
899	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
900	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0); /* 0 as PASID not supported. */
901	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCap);
902	}
903
904	/*
905	* Initialize registers mutable by software.
906	*/
907	/* FECTL_REG */
908	{
909	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
910	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
911	}
912
913	/* ICETL_REG */
914	{
915	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
916	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
917	}
918
919	#ifdef VBOX_STRICT
920	uint64_t const fExtCap = dmarRegRead64(pThis, VTD_MMIO_OFF_ECAP_REG);
921	Assert(!RT_BF_GET(fExtCap, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
922	Assert(!RT_BF_GET(fExtCap, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
923	#endif
924	}
925
926
927	/**
928	* @interface_method_impl{PDMDEVREG,pfnReset}
929	*/
930	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
931	{
932	RT_NOREF1(pDevIns);
933	LogFlowFunc(("\n"));
934
935	dmarR3RegsInit(pDevIns);
936	}
937
938
939	/**
940	* @interface_method_impl{PDMDEVREG,pfnDestruct}
941	*/
942	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
943	{
944	RT_NOREF(pDevIns);
945	LogFlowFunc(("\n"));
946	return VINF_SUCCESS;
947	}
948
949
950	/**
951	* @interface_method_impl{PDMDEVREG,pfnConstruct}
952	*/
953	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
954	{
955	RT_NOREF(pCfg);
956
957	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
958	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
959	pThisR3->pDevInsR3 = pDevIns;
960
961	LogFlowFunc(("iInstance=%d\n", iInstance));
962	NOREF(iInstance);
963
964	/*
965	* Register the IOMMU with PDM.
966	*/
967	PDMIOMMUREGR3 IommuReg;
968	RT_ZERO(IommuReg);
969	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
970	IommuReg.pfnMemAccess = iommuIntelMemAccess;
971	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
972	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
973	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
974	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
975	if (RT_FAILURE(rc))
976	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
977	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
978	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
979	N_("IOMMU helper version mismatch; got %#x expected %#x"),
980	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
981	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
982	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
983	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
984	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
985	/*
986	* Use PDM's critical section (via helpers) for the IOMMU device.
987	*/
988	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
989	AssertRCReturn(rc, rc);
990
991	/*
992	* Initialize PCI configuration registers.
993	*/
994	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
995	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
996
997	/* Header. */
998	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
999	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
1000	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
1001	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
1002	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
1003	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
1004	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
1005	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
1006
1007	/** @todo VTD: Chipset spec says PCI Express Capability Id. Relevant for us? */
1008	PDMPciDevSetStatus(pPciDev, 0);
1009	PDMPciDevSetCapabilityList(pPciDev, 0);
1010
1011	/** @todo VTD: VTBAR at 0x180? */
1012
1013	/*
1014	* Register the PCI function with PDM.
1015	*/
1016	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
1017	AssertLogRelRCReturn(rc, rc);
1018
1019	/** @todo VTD: Register MSI but what's the MSI capability offset? */
1020	#if 0
1021	/*
1022	* Register MSI support for the PCI device.
1023	* This must be done -after- registering it as a PCI device!
1024	*/
1025	#endif
1026
1027	/*
1028	* Register MMIO region.
1029	*/
1030	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
1031	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
1032	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED,
1033	"Intel-IOMMU", &pThis->hMmio);
1034	AssertRCReturn(rc, rc);
1035
1036	#ifdef VBOX_WITH_STATISTICS
1037	/*
1038	* Statistics.
1039	*/
1040	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
1041	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
1042
1043	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
1044	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
1045
1046	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
1047	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
1048
1049	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
1050	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
1051
1052	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
1053	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
1054
1055	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
1056	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
1057
1058	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
1059	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
1060	#endif
1061
1062	/*
1063	* Initialize registers.
1064	*/
1065	dmarR3RegsInit(pDevIns);
1066
1067	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_MGAW) + 1;
1068	uint8_t const cSupGstAddrBits = vtdGetSupGstAddrBits(RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_SAGAW));
1069	LogRel(("%s: CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits)\n", DMAR_LOG_PFX, pThis->fCap, pThis->fExtCap,
1070	cMaxGstAddrBits, cSupGstAddrBits));
1071	return VINF_SUCCESS;
1072	}
1073
1074	#else
1075
1076	/**
1077	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
1078	*/
1079	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
1080	{
1081	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
1082	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1083	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
1084	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
1085
1086	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
1087	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1088	AssertRCReturn(rc, rc);
1089
1090	/* Set up the MMIO RZ handlers. */
1091	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
1092	AssertRCReturn(rc, rc);
1093
1094	/* Set up the IOMMU RZ callbacks. */
1095	PDMIOMMUREGCC IommuReg;
1096	RT_ZERO(IommuReg);
1097	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
1098	IommuReg.idxIommu = pThis->idxIommu;
1099	IommuReg.pfnMemAccess = iommuIntelMemAccess;
1100	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
1101	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
1102	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
1103
1104	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
1105	AssertRCReturn(rc, rc);
1106	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
1107	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
1108	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
1109	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
1110	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
1111
1112	return VINF_SUCCESS;
1113	}
1114
1115	#endif
1116
1117
1118	/**
1119	* The device registration structure.
1120	*/
1121	const PDMDEVREG g_DeviceIommuIntel =
1122	{
1123	/* .u32Version = */ PDM_DEVREG_VERSION,
1124	/* .uReserved0 = */ 0,
1125	/* .szName = */ "iommu-intel",
1126	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
1127	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
1128	/* .cMaxInstances = */ 1,
1129	/* .uSharedVersion = */ 42,
1130	/* .cbInstanceShared = */ sizeof(DMAR),
1131	/* .cbInstanceCC = */ sizeof(DMARCC),
1132	/* .cbInstanceRC = */ sizeof(DMARRC),
1133	/* .cMaxPciDevices = */ 1,
1134	/* .cMaxMsixVectors = */ 0,
1135	/* .pszDescription = */ "IOMMU (Intel)",
1136	#if defined(IN_RING3)
1137	/* .pszRCMod = */ "VBoxDDRC.rc",
1138	/* .pszR0Mod = */ "VBoxDDR0.r0",
1139	/* .pfnConstruct = */ iommuIntelR3Construct,
1140	/* .pfnDestruct = */ iommuIntelR3Destruct,
1141	/* .pfnRelocate = */ NULL,
1142	/* .pfnMemSetup = */ NULL,
1143	/* .pfnPowerOn = */ NULL,
1144	/* .pfnReset = */ iommuIntelR3Reset,
1145	/* .pfnSuspend = */ NULL,
1146	/* .pfnResume = */ NULL,
1147	/* .pfnAttach = */ NULL,
1148	/* .pfnDetach = */ NULL,
1149	/* .pfnQueryInterface = */ NULL,
1150	/* .pfnInitComplete = */ NULL,
1151	/* .pfnPowerOff = */ NULL,
1152	/* .pfnSoftReset = */ NULL,
1153	/* .pfnReserved0 = */ NULL,
1154	/* .pfnReserved1 = */ NULL,
1155	/* .pfnReserved2 = */ NULL,
1156	/* .pfnReserved3 = */ NULL,
1157	/* .pfnReserved4 = */ NULL,
1158	/* .pfnReserved5 = */ NULL,
1159	/* .pfnReserved6 = */ NULL,
1160	/* .pfnReserved7 = */ NULL,
1161	#elif defined(IN_RING0)
1162	/* .pfnEarlyConstruct = */ NULL,
1163	/* .pfnConstruct = */ iommuIntelRZConstruct,
1164	/* .pfnDestruct = */ NULL,
1165	/* .pfnFinalDestruct = */ NULL,
1166	/* .pfnRequest = */ NULL,
1167	/* .pfnReserved0 = */ NULL,
1168	/* .pfnReserved1 = */ NULL,
1169	/* .pfnReserved2 = */ NULL,
1170	/* .pfnReserved3 = */ NULL,
1171	/* .pfnReserved4 = */ NULL,
1172	/* .pfnReserved5 = */ NULL,
1173	/* .pfnReserved6 = */ NULL,
1174	/* .pfnReserved7 = */ NULL,
1175	#elif defined(IN_RC)
1176	/* .pfnConstruct = */ iommuIntelRZConstruct,
1177	/* .pfnReserved0 = */ NULL,
1178	/* .pfnReserved1 = */ NULL,
1179	/* .pfnReserved2 = */ NULL,
1180	/* .pfnReserved3 = */ NULL,
1181	/* .pfnReserved4 = */ NULL,
1182	/* .pfnReserved5 = */ NULL,
1183	/* .pfnReserved6 = */ NULL,
1184	/* .pfnReserved7 = */ NULL,
1185	#else
1186	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
1187	#endif
1188	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
1189	};
1190
1191	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1192

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88480

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