DevIommuIntel.cpp@ 88288

Last change on this file since 88288 was 88260, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 WIP.
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1	/* $Id: DevIommuIntel.cpp 88260 2021-03-23 13:41:27Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include <VBox/vmm/pdmdev.h>
24	#include <VBox/iommu-intel.h>
25
26	#include <iprt/string.h>
27
28	#include "VBoxDD.h"
29
30
31	/*********************************************************************************************************************************
32	* Defined Constants And Macros *
33	*********************************************************************************************************************************/
34	/** @def VTD_LO_U32
35	* Gets the low uint32_t of a uint64_t or something equivalent.
36	*
37	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
38	* used as it asserts for correctness when compiling on certain compilers). */
39	#define VTD_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
40
41	/** @def VTD_HI_U32
42	* Gets the high uint32_t of a uint64_t or something equivalent.
43	*
44	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
45	* used as it asserts for correctness when compiling on certain compilers). */
46	#define VTD_HI_U32(a) (uint32_t)((a) >> 32)
47
48	/** @def VTD_ASSERT_MMIO_ACCESS
49	* Asserts MMIO access' offset and size are valid or returns appropriate error
50	* code suitable for returning from MMIO access handlers. */
51	#define VTD_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
52	do { \
53	AssertReturn(!(off & 3), VINF_IOM_MMIO_UNUSED_FF); \
54	AssertReturn(cb == 4 \|\| cb == 8, VINF_IOM_MMIO_UNUSED_FF); \
55	} while (0);
56
57	/** @def VTD_IS_MMIO_OFF_VALID
58	* Returns @c true if the MMIO offset is valid, or @c false otherwise. */
59	#define VTD_IS_MMIO_OFF_VALID(a_off) ( (a_off) < VTD_MMIO_GROUP_0_OFF_END \
60	\|\| (a_off) - VTD_MMIO_GROUP_1_OFF_FIRST < VTD_MMIO_GROUP_1_SIZE)
61
62	/** The number of fault recording registers our implementation supports.
63	* Normal guest operation shouldn't trigger faults anyway, so we only support the
64	* minimum number of registers (which is 1).
65	*
66	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG::NFR). */
67	#define VTD_FRCD_REG_COUNT UINT32_C(1)
68
69	/** Offset of first register in group 0. */
70	#define VTD_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
71	/** Offset of last register in group 0 (inclusive). */
72	#define VTD_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
73	/** Last valid offset in group 0 (exclusive). */
74	#define VTD_MMIO_GROUP_0_OFF_END (VTD_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
75	/** Size of the group 0 (in bytes). */
76	#define VTD_MMIO_GROUP_0_SIZE (VTD_MMIO_GROUP_0_OFF_END - VTD_MMIO_GROUP_0_OFF_FIRST)
77
78	#define VTD_MMIO_OFF_IVA_REG 0xe40 /*< Implementation-specific MMIO offset of IVA_REG. /
79	#define VTD_MMIO_OFF_IOTLB_REG 0xe48 /*< Implementation-specific MMIO offset of IOTLB_REG. /
80	#define VTD_MMIO_OFF_FRCD_LO_REG 0xe60 /*< Implementation-specific MMIO offset of FRCD_LO_REG. /
81	#define VTD_MMIO_OFF_FRCD_HI_REG 0xe68 /*< Implementation-specific MMIO offset of FRCD_HI_REG. /
82	AssertCompile(!(VTD_MMIO_OFF_FRCD_LO_REG & 0xf));
83
84	/** Offset of first register in group 1. */
85	#define VTD_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
86	/** Offset of last register in group 1 (inclusive). */
87	#define VTD_MMIO_GROUP_1_OFF_LAST VTD_MMIO_OFF_FRCD_LO_REG + 8 * VTD_FRCD_REG_COUNT
88	/** Last valid offset in group 1 (exclusive). */
89	#define VTD_MMIO_GROUP_1_OFF_END (VTD_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
90	/** Size of the group 1 (in bytes). */
91	#define VTD_MMIO_GROUP_1_SIZE (VTD_MMIO_GROUP_1_OFF_END - VTD_MMIO_GROUP_1_OFF_FIRST)
92
93	/** Release log prefix string. */
94	#define IOMMU_LOG_PFX "Intel-IOMMU"
95
96	/** The current saved state version. */
97	#define IOMMU_SAVED_STATE_VERSION 1
98
99
100	/*********************************************************************************************************************************
101	* Structures and Typedefs *
102	*********************************************************************************************************************************/
103	/**
104	* The shared IOMMU device state.
105	*/
106	typedef struct IOMMU
107	{
108	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
109	uint32_t idxIommu;
110	/** IOMMU magic. */
111	uint32_t u32Magic;
112
113	/** The MMIO handle. */
114	IOMMMIOHANDLE hMmio;
115
116	/** IOMMU registers (group 0). */
117	uint8_t abRegs0[VTD_MMIO_GROUP_0_SIZE];
118	/** IOMMU registers (group 1). */
119	uint8_t abRegs1[VTD_MMIO_GROUP_1_SIZE];
120	} IOMMU;
121	/** Pointer to the IOMMU device state. */
122	typedef IOMMU *PIOMMU;
123	/** Pointer to the const IOMMU device state. */
124	typedef const IOMMU *PCIOMMU;
125
126	/**
127	* The ring-3 IOMMU device state.
128	*/
129	typedef struct IOMMUR3
130	{
131	/** Device instance. */
132	PPDMDEVINSR3 pDevInsR3;
133	/** The IOMMU helper. */
134	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
135	} IOMMUR3;
136	/** Pointer to the ring-3 IOMMU device state. */
137	typedef IOMMUR3 *PIOMMUR3;
138	/** Pointer to the const ring-3 IOMMU device state. */
139	typedef const IOMMUR3 *PCIOMMUR3;
140
141	/**
142	* The ring-0 IOMMU device state.
143	*/
144	typedef struct IOMMUR0
145	{
146	/** Device instance. */
147	PPDMDEVINSR0 pDevInsR0;
148	/** The IOMMU helper. */
149	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
150	} IOMMUR0;
151	/** Pointer to the ring-0 IOMMU device state. */
152	typedef IOMMUR0 *PIOMMUR0;
153	/** Pointer to the const ring-0 IOMMU device state. */
154	typedef const IOMMUR0 *PCIOMMUR0;
155
156	/**
157	* The raw-mode IOMMU device state.
158	*/
159	typedef struct IOMMURC
160	{
161	/** Device instance. */
162	PPDMDEVINSRC pDevInsRC;
163	/** The IOMMU helper. */
164	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
165	} IOMMURC;
166	/** Pointer to the raw-mode IOMMU device state. */
167	typedef IOMMURC *PIOMMURC;
168	/** Pointer to the const raw-mode IOMMU device state. */
169	typedef const IOMMURC *CPIOMMURC;
170
171	/** The IOMMU device state for the current context. */
172	typedef CTX_SUFF(IOMMU) IOMMUCC;
173	/** Pointer to the IOMMU device state for the current context. */
174	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
175
176
177	/*********************************************************************************************************************************
178	* Global Variables *
179	*********************************************************************************************************************************/
180	/**
181	* Read-write masks for IOMMU registers (group 0).
182	*/
183	static const uint32_t g_au32RwMasks0[] =
184	{
185	/* Offset Register Low High */
186	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
187	/* 0x004 Reserved */ 0,
188	/* 0x008 CAP_REG */ VTD_LO_U32(VTD_CAP_REG_RW_MASK), VTD_HI_U32(VTD_CAP_REG_RW_MASK),
189	/* 0x010 ECAP_REG */ VTD_LO_U32(VTD_ECAP_REG_RW_MASK), VTD_HI_U32(VTD_ECAP_REG_RW_MASK),
190	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
191	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
192	/* 0x020 RTADDR_REG */ VTD_LO_U32(VTD_RTADDR_REG_RW_MASK), VTD_HI_U32(VTD_RTADDR_REG_RW_MASK),
193	/* 0x028 CCMD_REG */ VTD_LO_U32(VTD_CCMD_REG_RW_MASK), VTD_HI_U32(VTD_CCMD_REG_RW_MASK),
194	/* 0x030 Reserved */ 0,
195	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
196	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
197	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
198	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
199	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
200	/* 0x048 Reserved */ 0, 0,
201	/* 0x050 Reserved */ 0, 0,
202	/* 0x058 AFLOG_REG */ VTD_LO_U32(VTD_AFLOG_REG_RW_MASK), VTD_HI_U32(VTD_AFLOG_REG_RW_MASK),
203	/* 0x060 Reserved */ 0,
204	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
205	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
206	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
207	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
208	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
209	/* 0x080 IQH_REG */ VTD_LO_U32(VTD_IQH_REG_RW_MASK), VTD_HI_U32(VTD_IQH_REG_RW_MASK),
210	/* 0x088 IQT_REG */ VTD_LO_U32(VTD_IQT_REG_RW_MASK), VTD_HI_U32(VTD_IQT_REG_RW_MASK),
211	/* 0x090 IQA_REG */ VTD_LO_U32(VTD_IQA_REG_RW_MASK), VTD_HI_U32(VTD_IQA_REG_RW_MASK),
212	/* 0x098 Reserved */ 0,
213	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
214	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
215	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
216	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
217	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
218	/* 0x0b0 IQERCD_REG */ VTD_LO_U32(VTD_IQERCD_REG_RW_MASK), VTD_HI_U32(VTD_IQERCD_REG_RW_MASK),
219	/* 0x0b8 IRTA_REG */ VTD_LO_U32(VTD_IRTA_REG_RW_MASK), VTD_HI_U32(VTD_IRTA_REG_RW_MASK),
220	/* 0x0c0 PQH_REG */ VTD_LO_U32(VTD_PQH_REG_RW_MASK), VTD_HI_U32(VTD_PQH_REG_RW_MASK),
221	/* 0x0c8 PQT_REG */ VTD_LO_U32(VTD_PQT_REG_RW_MASK), VTD_HI_U32(VTD_PQT_REG_RW_MASK),
222	/* 0x0d0 PQA_REG */ VTD_LO_U32(VTD_PQA_REG_RW_MASK), VTD_HI_U32(VTD_PQA_REG_RW_MASK),
223	/* 0x0d8 Reserved */ 0,
224	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
225	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
226	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
227	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
228	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
229	/* 0x0f0 Reserved */ 0, 0,
230	/* 0x0f8 Reserved */ 0, 0,
231	/* 0x100 MTRRCAP_REG */ VTD_LO_U32(VTD_MTRRCAP_REG_RW_MASK), VTD_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
232	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
233	/* 0x110 Reserved */ 0, 0,
234	/* 0x118 Reserved */ 0, 0,
235	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
236	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
237	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
238	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
239	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
240	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
241	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
242	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
243	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
244	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
245	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
246	/* 0x178 Reserved */ 0, 0,
247	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
248	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
249	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
250	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
251	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
252	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
253	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
254	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
255	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
256	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
257	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
258	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
259	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
260	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
261	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
262	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
263	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
264	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
265	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
266	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
267	};
268	AssertCompile(sizeof(g_au32RwMasks0) == VTD_MMIO_GROUP_0_SIZE);
269
270	/**
271	* Read-only Status, Write-1-to-clear masks for IOMMU registers (group 0).
272	*/
273	static const uint32_t g_au32Rw1cMasks0[] =
274	{
275	/* Offset Register Low High */
276	/* 0x000 VER_REG */ 0,
277	/* 0x004 Reserved */ 0,
278	/* 0x008 CAP_REG */ 0, 0,
279	/* 0x010 ECAP_REG */ 0, 0,
280	/* 0x018 GCMD_REG */ 0,
281	/* 0x01c GSTS_REG */ 0,
282	/* 0x020 RTADDR_REG */ 0, 0,
283	/* 0x028 CCMD_REG */ 0, 0,
284	/* 0x030 Reserved */ 0,
285	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
286	/* 0x038 FECTL_REG */ 0,
287	/* 0x03c FEDATA_REG */ 0,
288	/* 0x040 FEADDR_REG */ 0,
289	/* 0x044 FEUADDR_REG */ 0,
290	/* 0x048 Reserved */ 0, 0,
291	/* 0x050 Reserved */ 0, 0,
292	/* 0x058 AFLOG_REG */ 0, 0,
293	/* 0x060 Reserved */ 0,
294	/* 0x064 PMEN_REG */ 0,
295	/* 0x068 PLMBASE_REG */ 0,
296	/* 0x06c PLMLIMIT_REG */ 0,
297	/* 0x070 PHMBASE_REG */ 0, 0,
298	/* 0x078 PHMLIMIT_REG */ 0, 0,
299	/* 0x080 IQH_REG */ 0, 0,
300	/* 0x088 IQT_REG */ 0, 0,
301	/* 0x090 IQA_REG */ 0, 0,
302	/* 0x098 Reserved */ 0,
303	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
304	/* 0x0a0 IECTL_REG */ 0,
305	/* 0x0a4 IEDATA_REG */ 0,
306	/* 0x0a8 IEADDR_REG */ 0,
307	/* 0x0ac IEUADDR_REG */ 0,
308	/* 0x0b0 IQERCD_REG */ 0, 0,
309	/* 0x0b8 IRTA_REG */ 0, 0,
310	/* 0x0c0 PQH_REG */ 0, 0,
311	/* 0x0c8 PQT_REG */ 0, 0,
312	/* 0x0d0 PQA_REG */ 0, 0,
313	/* 0x0d8 Reserved */ 0,
314	/* 0x0dc PRS_REG */ 0,
315	/* 0x0e0 PECTL_REG */ 0,
316	/* 0x0e4 PEDATA_REG */ 0,
317	/* 0x0e8 PEADDR_REG */ 0,
318	/* 0x0ec PEUADDR_REG */ 0,
319	/* 0x0f0 Reserved */ 0, 0,
320	/* 0x0f8 Reserved */ 0, 0,
321	/* 0x100 MTRRCAP_REG */ 0, 0,
322	/* 0x108 MTRRDEF_REG */ 0, 0,
323	/* 0x110 Reserved */ 0, 0,
324	/* 0x118 Reserved */ 0, 0,
325	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
326	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
327	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
328	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
329	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
330	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
331	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
332	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
333	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
334	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
335	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
336	/* 0x178 Reserved */ 0, 0,
337	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
338	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
339	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
340	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
341	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
342	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
343	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
344	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
345	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
346	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
347	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
348	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
349	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
350	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
351	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
352	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
353	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
354	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
355	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
356	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
357	};
358	AssertCompile(sizeof(g_au32Rw1cMasks0) == VTD_MMIO_GROUP_0_SIZE);
359
360	/**
361	* Read-write masks for IOMMU registers (group 1).
362	*/
363	static const uint32_t g_au32RwMasks1[] =
364	{
365	/* Offset Register Low High */
366	/* 0xe00 VCCAP_REG */ VTD_LO_U32(VTD_VCCAP_REG_RW_MASK), VTD_HI_U32(VTD_VCCAP_REG_RW_MASK),
367	/* 0xe08 Reserved */ 0, 0,
368	/* 0xe10 VCMD_REG / 0, 0, / RO as we don't support VCS. */
369	/* 0xe18 VCMDRSVD_REG */ 0, 0,
370	/* 0xe20 VCRSP_REG / 0, 0, / RO as we don't support VCS. */
371	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
372	/* 0xe30 Reserved */ 0, 0,
373	/* 0xe38 Reserved */ 0, 0,
374	/* 0xe40 IVA_REG */ VTD_LO_U32(VTD_IVA_REG_RW_MASK), VTD_HI_U32(VTD_IVA_REG_RW_MASK),
375	/* 0xe48 IOTLB_REG */ VTD_LO_U32(VTD_IOTLB_REG_RW_MASK), VTD_HI_U32(VTD_IOTLB_REG_RW_MASK),
376	/* 0xe50 Reserved */ 0, 0,
377	/* 0xe58 Reserved */ 0, 0,
378	/* 0xe60 FRCD_REG_LO */ VTD_LO_U32(VTD_FRCD_REG_LO_RW_MASK), VTD_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
379	/* 0xe68 FRCD_REG_HI */ VTD_LO_U32(VTD_FRCD_REG_HI_RW_MASK), VTD_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
380	};
381	AssertCompile(sizeof(g_au32RwMasks1) == VTD_MMIO_GROUP_1_SIZE);
382	AssertCompile((VTD_MMIO_OFF_FRCD_LO_REG - VTD_MMIO_GROUP_1_OFF_FIRST) + VTD_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
383
384	/**
385	* Read-only Status, Write-1-to-clear masks for IOMMU registers (group 1).
386	*/
387	static const uint32_t g_au32Rw1cMasks1[] =
388	{
389	/* Offset Register Low High */
390	/* 0xe00 VCCAP_REG */ 0, 0,
391	/* 0xe08 Reserved */ 0, 0,
392	/* 0xe10 VCMD_REG */ 0, 0,
393	/* 0xe18 VCMDRSVD_REG */ 0, 0,
394	/* 0xe20 VCRSP_REG */ 0, 0,
395	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
396	/* 0xe30 Reserved */ 0, 0,
397	/* 0xe38 Reserved */ 0, 0,
398	/* 0xe40 IVA_REG */ 0, 0,
399	/* 0xe48 IOTLB_REG */ 0, 0,
400	/* 0xe50 Reserved */ 0, 0,
401	/* 0xe58 Reserved */ 0, 0,
402	/* 0xe60 FRCD_REG_LO */ VTD_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), VTD_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
403	/* 0xe68 FRCD_REG_HI */ VTD_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), VTD_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
404	};
405	AssertCompile(sizeof(g_au32Rw1cMasks1) == VTD_MMIO_GROUP_1_SIZE);
406
407	/** Array of RW masks for each register group. */
408	static const uint8_t g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
409
410	/** Array of RW1C masks for each register group. */
411	static const uint8_t g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
412
413
414	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
415
416	/**
417	* Gets the group the register belongs to given its MMIO offset.
418	*
419	* @returns Pointer to the first element of the register group.
420	* @param pThis The shared IOMMU device state.
421	* @param offReg The MMIO offset of the register.
422	* @param cbReg The size of the access being made.
423	* @param pIdxGroup Where to store the index of the register group the register
424	* belongs to.
425	*/
426	DECLINLINE(uint8_t ) iommuIntelRegGetGroup(PIOMMU pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
427	{
428	uint16_t const offLast = offReg + cbReg - 1;
429	AssertCompile(VTD_MMIO_GROUP_0_OFF_FIRST == 0);
430	AssertMsg(VTD_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
431
432	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
433	*pIdxGroup = !(offLast < VTD_MMIO_GROUP_0_OFF_END);
434	return apbRegs[*pIdxGroup];
435	}
436
437
438	/**
439	* Writes a 64-bit register with the exactly the supplied value.
440	*
441	* @param pThis The shared IOMMU device state.
442	* @param offReg The MMIO offset of the register.
443	* @param uReg The 64-bit value to write.
444	*/
445	DECLINLINE(void) iommuIntelRegWriteRaw64(PIOMMU pThis, uint16_t offReg, uint64_t uReg)
446	{
447	uint8_t idxGroup;
448	uint8_t *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
449	NOREF(idxGroup);
450	(uint64_t )(pabRegs + offReg) = uReg;
451	}
452
453
454	/**
455	* Writes a 32-bit register with the exactly the supplied value.
456	*
457	* @param pThis The shared IOMMU device state.
458	* @param offReg The MMIO offset of the register.
459	* @param uReg The 32-bit value to write.
460	*/
461	DECLINLINE(void) iommuIntelRegWriteRaw32(PIOMMU pThis, uint16_t offReg, uint32_t uReg)
462	{
463	uint8_t idxGroup;
464	uint8_t *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
465	NOREF(idxGroup);
466	(uint32_t )(pabRegs + offReg) = uReg;
467	}
468
469
470	/**
471	* Reads a 64-bit register with exactly the value it contains.
472	*
473	* @param pThis The shared IOMMU device state.
474	* @param offReg The MMIO offset of the register.
475	* @param puReg Where to store the raw 64-bit register value.
476	* @param pfRwMask Where to store the RW mask corresponding to this register.
477	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
478	*/
479	DECLINLINE(void) iommuIntelRegReadRaw64(PIOMMU pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
480	{
481	uint8_t idxGroup;
482	uint8_t const *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
483	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
484	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
485	puReg = (uint64_t *)(pabRegs + offReg);
486	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
487	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
488	}
489
490
491	/**
492	* Reads a 32-bit register with exactly the value it contains.
493	*
494	* @param pThis The shared IOMMU device state.
495	* @param offReg The MMIO offset of the register.
496	* @param puReg Where to store the raw 32-bit register value.
497	* @param pfRwMask Where to store the RW mask corresponding to this register.
498	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
499	*/
500	DECLINLINE(void) iommuIntelRegReadRaw32(PIOMMU pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
501	{
502	uint8_t idxGroup;
503	uint8_t const *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
504	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
505	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
506	puReg = (uint32_t *)(pabRegs + offReg);
507	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
508	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
509	}
510
511
512	/**
513	* Writes a 64-bit register as it would be when written by software.
514	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
515	*
516	* @param pThis The shared IOMMU device state.
517	* @param offReg The MMIO offset of the register.
518	* @param uReg The 64-bit value to write.
519	*/
520	static void iommuIntelRegWrite64(PIOMMU pThis, uint16_t offReg, uint64_t uReg)
521	{
522	/* Read current value from the 64-bit register. */
523	uint64_t uCurReg;
524	uint64_t fRwMask;
525	uint64_t fRw1cMask;
526	iommuIntelRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
527
528	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
529	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
530	uint64_t const fRw1cBits = ~(fRw1cMask & uReg); /* Clear newly written RW1C bits. */
531	uint64_t const uNewReg = (fRoBits \| fRwBits) & fRw1cBits;
532
533	/* Write new value to the 64-bit register. */
534	iommuIntelRegWriteRaw64(pThis, offReg, uNewReg);
535	}
536
537
538	/**
539	* Writes a 32-bit register as it would be when written by software.
540	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
541	*
542	* @param pThis The shared IOMMU device state.
543	* @param offReg The MMIO offset of the register.
544	* @param uReg The 32-bit value to write.
545	*/
546	static void iommuIntelRegWrite32(PIOMMU pThis, uint16_t offReg, uint64_t uReg)
547	{
548	/* Read current value from the 32-bit register. */
549	uint32_t uCurReg;
550	uint32_t fRwMask;
551	uint32_t fRw1cMask;
552	iommuIntelRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
553
554	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
555	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
556	uint32_t const fRw1cBits = ~(fRw1cMask & uReg); /* Clear newly written RW1C bits. */
557	uint32_t const uNewReg = (fRoBits \| fRwBits) & fRw1cBits;
558
559	/* Write new value to the 32-bit register. */
560	iommuIntelRegWriteRaw32(pThis, offReg, uNewReg);
561	}
562
563
564	/**
565	* Reads a 64-bit register as it would be when read by software.
566	*
567	* @returns The 64-bit register value.
568	* @param pThis The shared IOMMU device state.
569	* @param offReg The MMIO offset of the register.
570	*/
571	static uint64_t iommuIntelRegRead64(PIOMMU pThis, uint16_t offReg)
572	{
573	uint64_t uCurReg;
574	uint64_t fRwMask;
575	uint64_t fRw1cMask;
576	iommuIntelRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
577	NOREF(fRwMask); NOREF(fRw1cMask);
578	return uCurReg;
579	}
580
581
582	/**
583	* Reads a 32-bit register as it would be when read by software.
584	*
585	* @returns The 32-bit register value.
586	* @param pThis The shared IOMMU device state.
587	* @param offReg The MMIO offset of the register.
588	*/
589	static uint32_t iommuIntelRegRead32(PIOMMU pThis, uint16_t offReg)
590	{
591	uint32_t uCurReg;
592	uint32_t fRwMask;
593	uint32_t fRw1cMask;
594	iommuIntelRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
595	NOREF(fRwMask); NOREF(fRw1cMask);
596	return uCurReg;
597	}
598
599
600	/**
601	* Memory access bulk (one or more 4K pages) request from a device.
602	*
603	* @returns VBox status code.
604	* @param pDevIns The IOMMU device instance.
605	* @param idDevice The device ID (bus, device, function).
606	* @param cIovas The number of addresses being accessed.
607	* @param pauIovas The I/O virtual addresses for each page being accessed.
608	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
609	* @param paGCPhysSpa Where to store the translated physical addresses.
610	*
611	* @thread Any.
612	*/
613	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
614	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
615	{
616	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
617	return VERR_NOT_IMPLEMENTED;
618	}
619
620
621	/**
622	* Memory access transaction from a device.
623	*
624	* @returns VBox status code.
625	* @param pDevIns The IOMMU device instance.
626	* @param idDevice The device ID (bus, device, function).
627	* @param uIova The I/O virtual address being accessed.
628	* @param cbIova The size of the access.
629	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
630	* @param pGCPhysSpa Where to store the translated system physical address.
631	* @param pcbContiguous Where to store the number of contiguous bytes translated
632	* and permission-checked.
633	*
634	* @thread Any.
635	*/
636	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
637	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
638	{
639	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
640	return VERR_NOT_IMPLEMENTED;
641	}
642
643
644	/**
645	* Interrupt remap request from a device.
646	*
647	* @returns VBox status code.
648	* @param pDevIns The IOMMU device instance.
649	* @param idDevice The device ID (bus, device, function).
650	* @param pMsiIn The source MSI.
651	* @param pMsiOut Where to store the remapped MSI.
652	*/
653	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
654	{
655	RT_NOREF4(pDevIns, idDevice, pMsiIn, pMsiOut);
656	return VERR_NOT_IMPLEMENTED;
657	}
658
659
660	/**
661	* @callback_method_impl{FNIOMMMIONEWWRITE}
662	*/
663	static DECLCALLBACK(VBOXSTRICTRC) iommuIntelMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
664	{
665	RT_NOREF1(pvUser);
666	VTD_ASSERT_MMIO_ACCESS_RET(off, cb);
667
668	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
669	uint16_t const offReg = off;
670	uint16_t const offLast = offReg + cb - 1;
671	if (VTD_IS_MMIO_OFF_VALID(offLast))
672	{
673	switch (off)
674	{
675	default:
676	{
677	if (cb == 8)
678	iommuIntelRegWrite64(pThis, offReg, (uint64_t )pv);
679	else
680	iommuIntelRegWrite32(pThis, offReg, (uint32_t )pv);
681	break;
682	}
683	}
684	return VINF_SUCCESS;
685	}
686	return VINF_IOM_MMIO_UNUSED_FF;
687	}
688
689
690	/**
691	* @callback_method_impl{FNIOMMMIONEWREAD}
692	*/
693	static DECLCALLBACK(VBOXSTRICTRC) iommuIntelMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
694	{
695	RT_NOREF1(pvUser);
696	VTD_ASSERT_MMIO_ACCESS_RET(off, cb);
697
698	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
699	uint16_t const offReg = off;
700	uint16_t const offLast = offReg + cb - 1;
701	if (VTD_IS_MMIO_OFF_VALID(offLast))
702	{
703	if (cb == 8)
704	(uint64_t )pv = iommuIntelRegRead64(pThis, offReg);
705	else
706	(uint32_t )pv = iommuIntelRegRead32(pThis, offReg);
707	return VINF_SUCCESS;
708	}
709
710	return VINF_IOM_MMIO_UNUSED_FF;
711	}
712
713
714	#ifdef IN_RING3
715	/**
716	* @interface_method_impl{PDMDEVREG,pfnReset}
717	*/
718	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
719	{
720	RT_NOREF1(pDevIns);
721	}
722
723
724	/**
725	* @interface_method_impl{PDMDEVREG,pfnDestruct}
726	*/
727	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
728	{
729	RT_NOREF(pDevIns);
730	return VERR_NOT_IMPLEMENTED;
731	}
732
733
734	/**
735	* @interface_method_impl{PDMDEVREG,pfnConstruct}
736	*/
737	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
738	{
739	RT_NOREF(pCfg);
740
741	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
742	PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
743	pThisR3->pDevInsR3 = pDevIns;
744
745	LogFlowFunc(("iInstance=%d\n", iInstance));
746	NOREF(iInstance);
747
748	/*
749	* Register the IOMMU with PDM.
750	*/
751	PDMIOMMUREGR3 IommuReg;
752	RT_ZERO(IommuReg);
753	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
754	IommuReg.pfnMemAccess = iommuIntelMemAccess;
755	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
756	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
757	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
758	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
759	if (RT_FAILURE(rc))
760	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
761	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
762	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
763	N_("IOMMU helper version mismatch; got %#x expected %#x"),
764	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
765	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
766	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
767	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
768	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
769	/*
770	* Use PDM's critical section (via helpers) for the IOMMU device.
771	*/
772	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
773	AssertRCReturn(rc, rc);
774
775
776	return VERR_NOT_IMPLEMENTED;
777	}
778
779	#else
780
781	/**
782	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
783	*/
784	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
785	{
786	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
787	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
788	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
789	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
790
791	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
792	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
793	AssertRCReturn(rc, rc);
794
795	/* Set up the MMIO RZ handlers. */
796	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuIntelMmioWrite, iommuIntelMmioRead, NULL /* pvUser */);
797	AssertRCReturn(rc, rc);
798
799	/* Set up the IOMMU RZ callbacks. */
800	PDMIOMMUREGCC IommuReg;
801	RT_ZERO(IommuReg);
802	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
803	IommuReg.idxIommu = pThis->idxIommu;
804	IommuReg.pfnMemAccess = iommuIntelMemAccess;
805	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
806	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
807	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
808	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
809	AssertRCReturn(rc, rc);
810	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
811	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
812	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
813	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
814	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
815	return VINF_SUCCESS;
816	}
817
818	#endif
819
820
821	/**
822	* The device registration structure.
823	*/
824	const PDMDEVREG g_DeviceIommuIntel =
825	{
826	/* .u32Version = */ PDM_DEVREG_VERSION,
827	/* .uReserved0 = */ 0,
828	/* .szName = */ "iommu-intel",
829	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
830	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
831	/* .cMaxInstances = */ 1,
832	/* .uSharedVersion = */ 42,
833	/* .cbInstanceShared = */ sizeof(IOMMU),
834	/* .cbInstanceCC = */ sizeof(IOMMUCC),
835	/* .cbInstanceRC = */ sizeof(IOMMURC),
836	/* .cMaxPciDevices = / 1, /* @todo Make this 0 if this isn't a PCI device. */
837	/* .cMaxMsixVectors = */ 0,
838	/* .pszDescription = */ "IOMMU (Intel)",
839	#if defined(IN_RING3)
840	/* .pszRCMod = */ "VBoxDDRC.rc",
841	/* .pszR0Mod = */ "VBoxDDR0.r0",
842	/* .pfnConstruct = */ iommuIntelR3Construct,
843	/* .pfnDestruct = */ iommuIntelR3Destruct,
844	/* .pfnRelocate = */ NULL,
845	/* .pfnMemSetup = */ NULL,
846	/* .pfnPowerOn = */ NULL,
847	/* .pfnReset = */ iommuIntelR3Reset,
848	/* .pfnSuspend = */ NULL,
849	/* .pfnResume = */ NULL,
850	/* .pfnAttach = */ NULL,
851	/* .pfnDetach = */ NULL,
852	/* .pfnQueryInterface = */ NULL,
853	/* .pfnInitComplete = */ NULL,
854	/* .pfnPowerOff = */ NULL,
855	/* .pfnSoftReset = */ NULL,
856	/* .pfnReserved0 = */ NULL,
857	/* .pfnReserved1 = */ NULL,
858	/* .pfnReserved2 = */ NULL,
859	/* .pfnReserved3 = */ NULL,
860	/* .pfnReserved4 = */ NULL,
861	/* .pfnReserved5 = */ NULL,
862	/* .pfnReserved6 = */ NULL,
863	/* .pfnReserved7 = */ NULL,
864	#elif defined(IN_RING0)
865	/* .pfnEarlyConstruct = */ NULL,
866	/* .pfnConstruct = */ iommuIntelRZConstruct,
867	/* .pfnDestruct = */ NULL,
868	/* .pfnFinalDestruct = */ NULL,
869	/* .pfnRequest = */ NULL,
870	/* .pfnReserved0 = */ NULL,
871	/* .pfnReserved1 = */ NULL,
872	/* .pfnReserved2 = */ NULL,
873	/* .pfnReserved3 = */ NULL,
874	/* .pfnReserved4 = */ NULL,
875	/* .pfnReserved5 = */ NULL,
876	/* .pfnReserved6 = */ NULL,
877	/* .pfnReserved7 = */ NULL,
878	#elif defined(IN_RC)
879	/* .pfnConstruct = */ iommuIntelRZConstruct,
880	/* .pfnReserved0 = */ NULL,
881	/* .pfnReserved1 = */ NULL,
882	/* .pfnReserved2 = */ NULL,
883	/* .pfnReserved3 = */ NULL,
884	/* .pfnReserved4 = */ NULL,
885	/* .pfnReserved5 = */ NULL,
886	/* .pfnReserved6 = */ NULL,
887	/* .pfnReserved7 = */ NULL,
888	#else
889	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
890	#endif
891	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
892	};
893
894	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
895

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88288

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