DevIommuIntel.cpp@ 88310

Last change on this file since 88310 was 88310, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 WIP.
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1	/* $Id: DevIommuIntel.cpp 88310 2021-03-29 12:52:12Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/string.h>
27
28
29	/*********************************************************************************************************************************
30	* Defined Constants And Macros *
31	*********************************************************************************************************************************/
32	/** @def VTD_LO_U32
33	* Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define VTD_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** @def VTD_HI_U32
40	* Gets the high uint32_t of a uint64_t or something equivalent.
41	*
42	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
43	* used as it asserts for correctness when compiling on certain compilers). */
44	#define VTD_HI_U32(a) (uint32_t)((a) >> 32)
45
46	/** @def VTD_ASSERT_MMIO_ACCESS
47	* Asserts MMIO access' offset and size are valid or returns appropriate error
48	* code suitable for returning from MMIO access handlers. */
49	#define VTD_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
50	do { \
51	AssertReturn(!(off & 3), VINF_IOM_MMIO_UNUSED_FF); \
52	AssertReturn(cb == 4 \|\| cb == 8, VINF_IOM_MMIO_UNUSED_FF); \
53	} while (0);
54
55	/** @def VTD_IS_MMIO_OFF_VALID
56	* Returns @c true if the MMIO offset is valid, or @c false otherwise. */
57	#define VTD_IS_MMIO_OFF_VALID(a_off) ( (a_off) < VTD_MMIO_GROUP_0_OFF_END \
58	\|\| (a_off) - VTD_MMIO_GROUP_1_OFF_FIRST < VTD_MMIO_GROUP_1_SIZE)
59
60	/** The number of fault recording registers our implementation supports.
61	* Normal guest operation shouldn't trigger faults anyway, so we only support the
62	* minimum number of registers (which is 1).
63	*
64	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG::NFR). */
65	#define VTD_FRCD_REG_COUNT UINT32_C(1)
66
67	/** Offset of first register in group 0. */
68	#define VTD_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
69	/** Offset of last register in group 0 (inclusive). */
70	#define VTD_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
71	/** Last valid offset in group 0 (exclusive). */
72	#define VTD_MMIO_GROUP_0_OFF_END (VTD_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
73	/** Size of the group 0 (in bytes). */
74	#define VTD_MMIO_GROUP_0_SIZE (VTD_MMIO_GROUP_0_OFF_END - VTD_MMIO_GROUP_0_OFF_FIRST)
75
76	#define VTD_MMIO_OFF_IVA_REG 0xe40 /*< Implementation-specific MMIO offset of IVA_REG. /
77	#define VTD_MMIO_OFF_IOTLB_REG 0xe48 /*< Implementation-specific MMIO offset of IOTLB_REG. /
78	#define VTD_MMIO_OFF_FRCD_LO_REG 0xe60 /*< Implementation-specific MMIO offset of FRCD_LO_REG. /
79	#define VTD_MMIO_OFF_FRCD_HI_REG 0xe68 /*< Implementation-specific MMIO offset of FRCD_HI_REG. /
80	AssertCompile(!(VTD_MMIO_OFF_FRCD_LO_REG & 0xf));
81
82	/** Offset of first register in group 1. */
83	#define VTD_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
84	/** Offset of last register in group 1 (inclusive). */
85	#define VTD_MMIO_GROUP_1_OFF_LAST VTD_MMIO_OFF_FRCD_LO_REG + 8 * VTD_FRCD_REG_COUNT
86	/** Last valid offset in group 1 (exclusive). */
87	#define VTD_MMIO_GROUP_1_OFF_END (VTD_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
88	/** Size of the group 1 (in bytes). */
89	#define VTD_MMIO_GROUP_1_SIZE (VTD_MMIO_GROUP_1_OFF_END - VTD_MMIO_GROUP_1_OFF_FIRST)
90
91	/** Release log prefix string. */
92	#define IOMMU_LOG_PFX "Intel-IOMMU"
93
94	/** The current saved state version. */
95	#define IOMMU_SAVED_STATE_VERSION 1
96
97
98	/*********************************************************************************************************************************
99	* Structures and Typedefs *
100	*********************************************************************************************************************************/
101	/**
102	* The shared IOMMU device state.
103	*/
104	typedef struct IOMMU
105	{
106	/** IOMMU device index (0 is at the top of the PCI tree hierarchy). */
107	uint32_t idxIommu;
108	/** IOMMU magic. */
109	uint32_t u32Magic;
110
111	/** The MMIO handle. */
112	IOMMMIOHANDLE hMmio;
113
114	/** IOMMU registers (group 0). */
115	uint8_t abRegs0[VTD_MMIO_GROUP_0_SIZE];
116	/** IOMMU registers (group 1). */
117	uint8_t abRegs1[VTD_MMIO_GROUP_1_SIZE];
118	} IOMMU;
119	/** Pointer to the IOMMU device state. */
120	typedef IOMMU *PIOMMU;
121	/** Pointer to the const IOMMU device state. */
122	typedef const IOMMU *PCIOMMU;
123
124	/**
125	* The ring-3 IOMMU device state.
126	*/
127	typedef struct IOMMUR3
128	{
129	/** Device instance. */
130	PPDMDEVINSR3 pDevInsR3;
131	/** The IOMMU helper. */
132	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
133	} IOMMUR3;
134	/** Pointer to the ring-3 IOMMU device state. */
135	typedef IOMMUR3 *PIOMMUR3;
136	/** Pointer to the const ring-3 IOMMU device state. */
137	typedef const IOMMUR3 *PCIOMMUR3;
138
139	/**
140	* The ring-0 IOMMU device state.
141	*/
142	typedef struct IOMMUR0
143	{
144	/** Device instance. */
145	PPDMDEVINSR0 pDevInsR0;
146	/** The IOMMU helper. */
147	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
148	} IOMMUR0;
149	/** Pointer to the ring-0 IOMMU device state. */
150	typedef IOMMUR0 *PIOMMUR0;
151	/** Pointer to the const ring-0 IOMMU device state. */
152	typedef const IOMMUR0 *PCIOMMUR0;
153
154	/**
155	* The raw-mode IOMMU device state.
156	*/
157	typedef struct IOMMURC
158	{
159	/** Device instance. */
160	PPDMDEVINSRC pDevInsRC;
161	/** The IOMMU helper. */
162	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
163	} IOMMURC;
164	/** Pointer to the raw-mode IOMMU device state. */
165	typedef IOMMURC *PIOMMURC;
166	/** Pointer to the const raw-mode IOMMU device state. */
167	typedef const IOMMURC *CPIOMMURC;
168
169	/** The IOMMU device state for the current context. */
170	typedef CTX_SUFF(IOMMU) IOMMUCC;
171	/** Pointer to the IOMMU device state for the current context. */
172	typedef CTX_SUFF(PIOMMU) PIOMMUCC;
173
174
175	/*********************************************************************************************************************************
176	* Global Variables *
177	*********************************************************************************************************************************/
178	/**
179	* Read-write masks for IOMMU registers (group 0).
180	*/
181	static const uint32_t g_au32RwMasks0[] =
182	{
183	/* Offset Register Low High */
184	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
185	/* 0x004 Reserved */ 0,
186	/* 0x008 CAP_REG */ VTD_LO_U32(VTD_CAP_REG_RW_MASK), VTD_HI_U32(VTD_CAP_REG_RW_MASK),
187	/* 0x010 ECAP_REG */ VTD_LO_U32(VTD_ECAP_REG_RW_MASK), VTD_HI_U32(VTD_ECAP_REG_RW_MASK),
188	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
189	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
190	/* 0x020 RTADDR_REG */ VTD_LO_U32(VTD_RTADDR_REG_RW_MASK), VTD_HI_U32(VTD_RTADDR_REG_RW_MASK),
191	/* 0x028 CCMD_REG */ VTD_LO_U32(VTD_CCMD_REG_RW_MASK), VTD_HI_U32(VTD_CCMD_REG_RW_MASK),
192	/* 0x030 Reserved */ 0,
193	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
194	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
195	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
196	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
197	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
198	/* 0x048 Reserved */ 0, 0,
199	/* 0x050 Reserved */ 0, 0,
200	/* 0x058 AFLOG_REG */ VTD_LO_U32(VTD_AFLOG_REG_RW_MASK), VTD_HI_U32(VTD_AFLOG_REG_RW_MASK),
201	/* 0x060 Reserved */ 0,
202	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
203	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
204	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
205	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
206	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
207	/* 0x080 IQH_REG */ VTD_LO_U32(VTD_IQH_REG_RW_MASK), VTD_HI_U32(VTD_IQH_REG_RW_MASK),
208	/* 0x088 IQT_REG */ VTD_LO_U32(VTD_IQT_REG_RW_MASK), VTD_HI_U32(VTD_IQT_REG_RW_MASK),
209	/* 0x090 IQA_REG */ VTD_LO_U32(VTD_IQA_REG_RW_MASK), VTD_HI_U32(VTD_IQA_REG_RW_MASK),
210	/* 0x098 Reserved */ 0,
211	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
212	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
213	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
214	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
215	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
216	/* 0x0b0 IQERCD_REG */ VTD_LO_U32(VTD_IQERCD_REG_RW_MASK), VTD_HI_U32(VTD_IQERCD_REG_RW_MASK),
217	/* 0x0b8 IRTA_REG */ VTD_LO_U32(VTD_IRTA_REG_RW_MASK), VTD_HI_U32(VTD_IRTA_REG_RW_MASK),
218	/* 0x0c0 PQH_REG */ VTD_LO_U32(VTD_PQH_REG_RW_MASK), VTD_HI_U32(VTD_PQH_REG_RW_MASK),
219	/* 0x0c8 PQT_REG */ VTD_LO_U32(VTD_PQT_REG_RW_MASK), VTD_HI_U32(VTD_PQT_REG_RW_MASK),
220	/* 0x0d0 PQA_REG */ VTD_LO_U32(VTD_PQA_REG_RW_MASK), VTD_HI_U32(VTD_PQA_REG_RW_MASK),
221	/* 0x0d8 Reserved */ 0,
222	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
223	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
224	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
225	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
226	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
227	/* 0x0f0 Reserved */ 0, 0,
228	/* 0x0f8 Reserved */ 0, 0,
229	/* 0x100 MTRRCAP_REG */ VTD_LO_U32(VTD_MTRRCAP_REG_RW_MASK), VTD_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
230	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
231	/* 0x110 Reserved */ 0, 0,
232	/* 0x118 Reserved */ 0, 0,
233	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
234	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
235	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
236	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
237	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
238	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
239	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
240	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
241	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
242	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
243	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
244	/* 0x178 Reserved */ 0, 0,
245	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
246	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
247	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
248	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
249	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
250	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
251	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
252	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
253	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
254	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
255	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
256	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
257	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
258	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
259	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
260	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
261	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
262	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
263	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
264	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
265	};
266	AssertCompile(sizeof(g_au32RwMasks0) == VTD_MMIO_GROUP_0_SIZE);
267
268	/**
269	* Read-only Status, Write-1-to-clear masks for IOMMU registers (group 0).
270	*/
271	static const uint32_t g_au32Rw1cMasks0[] =
272	{
273	/* Offset Register Low High */
274	/* 0x000 VER_REG */ 0,
275	/* 0x004 Reserved */ 0,
276	/* 0x008 CAP_REG */ 0, 0,
277	/* 0x010 ECAP_REG */ 0, 0,
278	/* 0x018 GCMD_REG */ 0,
279	/* 0x01c GSTS_REG */ 0,
280	/* 0x020 RTADDR_REG */ 0, 0,
281	/* 0x028 CCMD_REG */ 0, 0,
282	/* 0x030 Reserved */ 0,
283	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
284	/* 0x038 FECTL_REG */ 0,
285	/* 0x03c FEDATA_REG */ 0,
286	/* 0x040 FEADDR_REG */ 0,
287	/* 0x044 FEUADDR_REG */ 0,
288	/* 0x048 Reserved */ 0, 0,
289	/* 0x050 Reserved */ 0, 0,
290	/* 0x058 AFLOG_REG */ 0, 0,
291	/* 0x060 Reserved */ 0,
292	/* 0x064 PMEN_REG */ 0,
293	/* 0x068 PLMBASE_REG */ 0,
294	/* 0x06c PLMLIMIT_REG */ 0,
295	/* 0x070 PHMBASE_REG */ 0, 0,
296	/* 0x078 PHMLIMIT_REG */ 0, 0,
297	/* 0x080 IQH_REG */ 0, 0,
298	/* 0x088 IQT_REG */ 0, 0,
299	/* 0x090 IQA_REG */ 0, 0,
300	/* 0x098 Reserved */ 0,
301	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
302	/* 0x0a0 IECTL_REG */ 0,
303	/* 0x0a4 IEDATA_REG */ 0,
304	/* 0x0a8 IEADDR_REG */ 0,
305	/* 0x0ac IEUADDR_REG */ 0,
306	/* 0x0b0 IQERCD_REG */ 0, 0,
307	/* 0x0b8 IRTA_REG */ 0, 0,
308	/* 0x0c0 PQH_REG */ 0, 0,
309	/* 0x0c8 PQT_REG */ 0, 0,
310	/* 0x0d0 PQA_REG */ 0, 0,
311	/* 0x0d8 Reserved */ 0,
312	/* 0x0dc PRS_REG */ 0,
313	/* 0x0e0 PECTL_REG */ 0,
314	/* 0x0e4 PEDATA_REG */ 0,
315	/* 0x0e8 PEADDR_REG */ 0,
316	/* 0x0ec PEUADDR_REG */ 0,
317	/* 0x0f0 Reserved */ 0, 0,
318	/* 0x0f8 Reserved */ 0, 0,
319	/* 0x100 MTRRCAP_REG */ 0, 0,
320	/* 0x108 MTRRDEF_REG */ 0, 0,
321	/* 0x110 Reserved */ 0, 0,
322	/* 0x118 Reserved */ 0, 0,
323	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
324	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
325	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
326	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
327	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
328	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
329	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
330	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
331	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
332	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
333	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
334	/* 0x178 Reserved */ 0, 0,
335	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
336	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
337	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
338	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
339	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
340	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
341	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
342	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
343	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
344	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
345	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
346	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
347	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
348	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
349	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
350	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
351	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
352	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
353	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
354	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
355	};
356	AssertCompile(sizeof(g_au32Rw1cMasks0) == VTD_MMIO_GROUP_0_SIZE);
357
358	/**
359	* Read-write masks for IOMMU registers (group 1).
360	*/
361	static const uint32_t g_au32RwMasks1[] =
362	{
363	/* Offset Register Low High */
364	/* 0xe00 VCCAP_REG */ VTD_LO_U32(VTD_VCCAP_REG_RW_MASK), VTD_HI_U32(VTD_VCCAP_REG_RW_MASK),
365	/* 0xe08 Reserved */ 0, 0,
366	/* 0xe10 VCMD_REG / 0, 0, / RO as we don't support VCS. */
367	/* 0xe18 VCMDRSVD_REG */ 0, 0,
368	/* 0xe20 VCRSP_REG / 0, 0, / RO as we don't support VCS. */
369	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
370	/* 0xe30 Reserved */ 0, 0,
371	/* 0xe38 Reserved */ 0, 0,
372	/* 0xe40 IVA_REG */ VTD_LO_U32(VTD_IVA_REG_RW_MASK), VTD_HI_U32(VTD_IVA_REG_RW_MASK),
373	/* 0xe48 IOTLB_REG */ VTD_LO_U32(VTD_IOTLB_REG_RW_MASK), VTD_HI_U32(VTD_IOTLB_REG_RW_MASK),
374	/* 0xe50 Reserved */ 0, 0,
375	/* 0xe58 Reserved */ 0, 0,
376	/* 0xe60 FRCD_REG_LO */ VTD_LO_U32(VTD_FRCD_REG_LO_RW_MASK), VTD_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
377	/* 0xe68 FRCD_REG_HI */ VTD_LO_U32(VTD_FRCD_REG_HI_RW_MASK), VTD_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
378	};
379	AssertCompile(sizeof(g_au32RwMasks1) == VTD_MMIO_GROUP_1_SIZE);
380	AssertCompile((VTD_MMIO_OFF_FRCD_LO_REG - VTD_MMIO_GROUP_1_OFF_FIRST) + VTD_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
381
382	/**
383	* Read-only Status, Write-1-to-clear masks for IOMMU registers (group 1).
384	*/
385	static const uint32_t g_au32Rw1cMasks1[] =
386	{
387	/* Offset Register Low High */
388	/* 0xe00 VCCAP_REG */ 0, 0,
389	/* 0xe08 Reserved */ 0, 0,
390	/* 0xe10 VCMD_REG */ 0, 0,
391	/* 0xe18 VCMDRSVD_REG */ 0, 0,
392	/* 0xe20 VCRSP_REG */ 0, 0,
393	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
394	/* 0xe30 Reserved */ 0, 0,
395	/* 0xe38 Reserved */ 0, 0,
396	/* 0xe40 IVA_REG */ 0, 0,
397	/* 0xe48 IOTLB_REG */ 0, 0,
398	/* 0xe50 Reserved */ 0, 0,
399	/* 0xe58 Reserved */ 0, 0,
400	/* 0xe60 FRCD_REG_LO */ VTD_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), VTD_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
401	/* 0xe68 FRCD_REG_HI */ VTD_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), VTD_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
402	};
403	AssertCompile(sizeof(g_au32Rw1cMasks1) == VTD_MMIO_GROUP_1_SIZE);
404
405	/** Array of RW masks for each register group. */
406	static const uint8_t g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
407
408	/** Array of RW1C masks for each register group. */
409	static const uint8_t g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
410
411
412	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
413
414	/**
415	* Gets the group the register belongs to given its MMIO offset.
416	*
417	* @returns Pointer to the first element of the register group.
418	* @param pThis The shared IOMMU device state.
419	* @param offReg The MMIO offset of the register.
420	* @param cbReg The size of the access being made.
421	* @param pIdxGroup Where to store the index of the register group the register
422	* belongs to.
423	*/
424	DECLINLINE(uint8_t ) iommuIntelRegGetGroup(PIOMMU pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
425	{
426	uint16_t const offLast = offReg + cbReg - 1;
427	AssertCompile(VTD_MMIO_GROUP_0_OFF_FIRST == 0);
428	AssertMsg(VTD_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
429
430	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
431	*pIdxGroup = !(offLast < VTD_MMIO_GROUP_0_OFF_END);
432	return apbRegs[*pIdxGroup];
433	}
434
435
436	/**
437	* Writes a 64-bit register with the exactly the supplied value.
438	*
439	* @param pThis The shared IOMMU device state.
440	* @param offReg The MMIO offset of the register.
441	* @param uReg The 64-bit value to write.
442	*/
443	DECLINLINE(void) iommuIntelRegWriteRaw64(PIOMMU pThis, uint16_t offReg, uint64_t uReg)
444	{
445	uint8_t idxGroup;
446	uint8_t *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
447	NOREF(idxGroup);
448	(uint64_t )(pabRegs + offReg) = uReg;
449	}
450
451
452	/**
453	* Writes a 32-bit register with the exactly the supplied value.
454	*
455	* @param pThis The shared IOMMU device state.
456	* @param offReg The MMIO offset of the register.
457	* @param uReg The 32-bit value to write.
458	*/
459	DECLINLINE(void) iommuIntelRegWriteRaw32(PIOMMU pThis, uint16_t offReg, uint32_t uReg)
460	{
461	uint8_t idxGroup;
462	uint8_t *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
463	NOREF(idxGroup);
464	(uint32_t )(pabRegs + offReg) = uReg;
465	}
466
467
468	/**
469	* Reads a 64-bit register with exactly the value it contains.
470	*
471	* @param pThis The shared IOMMU device state.
472	* @param offReg The MMIO offset of the register.
473	* @param puReg Where to store the raw 64-bit register value.
474	* @param pfRwMask Where to store the RW mask corresponding to this register.
475	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
476	*/
477	DECLINLINE(void) iommuIntelRegReadRaw64(PIOMMU pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
478	{
479	uint8_t idxGroup;
480	uint8_t const *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
481	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
482	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
483	puReg = (uint64_t *)(pabRegs + offReg);
484	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
485	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
486	}
487
488
489	/**
490	* Reads a 32-bit register with exactly the value it contains.
491	*
492	* @param pThis The shared IOMMU device state.
493	* @param offReg The MMIO offset of the register.
494	* @param puReg Where to store the raw 32-bit register value.
495	* @param pfRwMask Where to store the RW mask corresponding to this register.
496	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
497	*/
498	DECLINLINE(void) iommuIntelRegReadRaw32(PIOMMU pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
499	{
500	uint8_t idxGroup;
501	uint8_t const *pabRegs = iommuIntelRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
502	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
503	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
504	puReg = (uint32_t *)(pabRegs + offReg);
505	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
506	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
507	}
508
509
510	/**
511	* Writes a 64-bit register as it would be when written by software.
512	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
513	*
514	* @param pThis The shared IOMMU device state.
515	* @param offReg The MMIO offset of the register.
516	* @param uReg The 64-bit value to write.
517	*/
518	static void iommuIntelRegWrite64(PIOMMU pThis, uint16_t offReg, uint64_t uReg)
519	{
520	/* Read current value from the 64-bit register. */
521	uint64_t uCurReg;
522	uint64_t fRwMask;
523	uint64_t fRw1cMask;
524	iommuIntelRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
525
526	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
527	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
528	uint64_t const fRw1cBits = ~(fRw1cMask & uReg); /* Clear newly written RW1C bits. */
529	uint64_t const uNewReg = (fRoBits \| fRwBits) & fRw1cBits;
530
531	/* Write new value to the 64-bit register. */
532	iommuIntelRegWriteRaw64(pThis, offReg, uNewReg);
533	}
534
535
536	/**
537	* Writes a 32-bit register as it would be when written by software.
538	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
539	*
540	* @param pThis The shared IOMMU device state.
541	* @param offReg The MMIO offset of the register.
542	* @param uReg The 32-bit value to write.
543	*/
544	static void iommuIntelRegWrite32(PIOMMU pThis, uint16_t offReg, uint64_t uReg)
545	{
546	/* Read current value from the 32-bit register. */
547	uint32_t uCurReg;
548	uint32_t fRwMask;
549	uint32_t fRw1cMask;
550	iommuIntelRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
551
552	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
553	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
554	uint32_t const fRw1cBits = ~(fRw1cMask & uReg); /* Clear newly written RW1C bits. */
555	uint32_t const uNewReg = (fRoBits \| fRwBits) & fRw1cBits;
556
557	/* Write new value to the 32-bit register. */
558	iommuIntelRegWriteRaw32(pThis, offReg, uNewReg);
559	}
560
561
562	/**
563	* Reads a 64-bit register as it would be when read by software.
564	*
565	* @returns The 64-bit register value.
566	* @param pThis The shared IOMMU device state.
567	* @param offReg The MMIO offset of the register.
568	*/
569	static uint64_t iommuIntelRegRead64(PIOMMU pThis, uint16_t offReg)
570	{
571	uint64_t uCurReg;
572	uint64_t fRwMask;
573	uint64_t fRw1cMask;
574	iommuIntelRegReadRaw64(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
575	NOREF(fRwMask); NOREF(fRw1cMask);
576	return uCurReg;
577	}
578
579
580	/**
581	* Reads a 32-bit register as it would be when read by software.
582	*
583	* @returns The 32-bit register value.
584	* @param pThis The shared IOMMU device state.
585	* @param offReg The MMIO offset of the register.
586	*/
587	static uint32_t iommuIntelRegRead32(PIOMMU pThis, uint16_t offReg)
588	{
589	uint32_t uCurReg;
590	uint32_t fRwMask;
591	uint32_t fRw1cMask;
592	iommuIntelRegReadRaw32(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
593	NOREF(fRwMask); NOREF(fRw1cMask);
594	return uCurReg;
595	}
596
597
598	/**
599	* Memory access bulk (one or more 4K pages) request from a device.
600	*
601	* @returns VBox status code.
602	* @param pDevIns The IOMMU device instance.
603	* @param idDevice The device ID (bus, device, function).
604	* @param cIovas The number of addresses being accessed.
605	* @param pauIovas The I/O virtual addresses for each page being accessed.
606	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
607	* @param paGCPhysSpa Where to store the translated physical addresses.
608	*
609	* @thread Any.
610	*/
611	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
612	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
613	{
614	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
615	return VERR_NOT_IMPLEMENTED;
616	}
617
618
619	/**
620	* Memory access transaction from a device.
621	*
622	* @returns VBox status code.
623	* @param pDevIns The IOMMU device instance.
624	* @param idDevice The device ID (bus, device, function).
625	* @param uIova The I/O virtual address being accessed.
626	* @param cbIova The size of the access.
627	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
628	* @param pGCPhysSpa Where to store the translated system physical address.
629	* @param pcbContiguous Where to store the number of contiguous bytes translated
630	* and permission-checked.
631	*
632	* @thread Any.
633	*/
634	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
635	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
636	{
637	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
638	return VERR_NOT_IMPLEMENTED;
639	}
640
641
642	/**
643	* Interrupt remap request from a device.
644	*
645	* @returns VBox status code.
646	* @param pDevIns The IOMMU device instance.
647	* @param idDevice The device ID (bus, device, function).
648	* @param pMsiIn The source MSI.
649	* @param pMsiOut Where to store the remapped MSI.
650	*/
651	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
652	{
653	RT_NOREF4(pDevIns, idDevice, pMsiIn, pMsiOut);
654	return VERR_NOT_IMPLEMENTED;
655	}
656
657
658	/**
659	* @callback_method_impl{FNIOMMMIONEWWRITE}
660	*/
661	static DECLCALLBACK(VBOXSTRICTRC) iommuIntelMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
662	{
663	RT_NOREF1(pvUser);
664	VTD_ASSERT_MMIO_ACCESS_RET(off, cb);
665
666	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
667	uint16_t const offReg = off;
668	uint16_t const offLast = offReg + cb - 1;
669	if (VTD_IS_MMIO_OFF_VALID(offLast))
670	{
671	switch (off)
672	{
673	default:
674	{
675	if (cb == 8)
676	iommuIntelRegWrite64(pThis, offReg, (uint64_t )pv);
677	else
678	iommuIntelRegWrite32(pThis, offReg, (uint32_t )pv);
679	break;
680	}
681	}
682	return VINF_SUCCESS;
683	}
684	return VINF_IOM_MMIO_UNUSED_FF;
685	}
686
687
688	/**
689	* @callback_method_impl{FNIOMMMIONEWREAD}
690	*/
691	static DECLCALLBACK(VBOXSTRICTRC) iommuIntelMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
692	{
693	RT_NOREF1(pvUser);
694	VTD_ASSERT_MMIO_ACCESS_RET(off, cb);
695
696	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
697	uint16_t const offReg = off;
698	uint16_t const offLast = offReg + cb - 1;
699	if (VTD_IS_MMIO_OFF_VALID(offLast))
700	{
701	if (cb == 8)
702	(uint64_t )pv = iommuIntelRegRead64(pThis, offReg);
703	else
704	(uint32_t )pv = iommuIntelRegRead32(pThis, offReg);
705	return VINF_SUCCESS;
706	}
707
708	return VINF_IOM_MMIO_UNUSED_FF;
709	}
710
711
712	#ifdef IN_RING3
713	/**
714	* @interface_method_impl{PDMDEVREG,pfnReset}
715	*/
716	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
717	{
718	RT_NOREF1(pDevIns);
719	}
720
721
722	/**
723	* @interface_method_impl{PDMDEVREG,pfnDestruct}
724	*/
725	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
726	{
727	RT_NOREF(pDevIns);
728	return VERR_NOT_IMPLEMENTED;
729	}
730
731
732	/**
733	* @interface_method_impl{PDMDEVREG,pfnConstruct}
734	*/
735	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
736	{
737	RT_NOREF(pCfg);
738
739	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
740	PIOMMUR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUR3);
741	pThisR3->pDevInsR3 = pDevIns;
742
743	LogFlowFunc(("iInstance=%d\n", iInstance));
744	NOREF(iInstance);
745
746	/*
747	* Register the IOMMU with PDM.
748	*/
749	PDMIOMMUREGR3 IommuReg;
750	RT_ZERO(IommuReg);
751	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
752	IommuReg.pfnMemAccess = iommuIntelMemAccess;
753	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
754	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
755	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
756	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
757	if (RT_FAILURE(rc))
758	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
759	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
760	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
761	N_("IOMMU helper version mismatch; got %#x expected %#x"),
762	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
763	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
764	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
765	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
766	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
767	/*
768	* Use PDM's critical section (via helpers) for the IOMMU device.
769	*/
770	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
771	AssertRCReturn(rc, rc);
772
773
774	return VERR_NOT_IMPLEMENTED;
775	}
776
777	#else
778
779	/**
780	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
781	*/
782	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
783	{
784	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
785	PIOMMU pThis = PDMDEVINS_2_DATA(pDevIns, PIOMMU);
786	PIOMMUCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PIOMMUCC);
787	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
788
789	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
790	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
791	AssertRCReturn(rc, rc);
792
793	/* Set up the MMIO RZ handlers. */
794	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, iommuIntelMmioWrite, iommuIntelMmioRead, NULL /* pvUser */);
795	AssertRCReturn(rc, rc);
796
797	/* Set up the IOMMU RZ callbacks. */
798	PDMIOMMUREGCC IommuReg;
799	RT_ZERO(IommuReg);
800	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
801	IommuReg.idxIommu = pThis->idxIommu;
802	IommuReg.pfnMemAccess = iommuIntelMemAccess;
803	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
804	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
805	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
806	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
807	AssertRCReturn(rc, rc);
808	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
809	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
810	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_SUFF(PDM_IOMMUHLP)_VERSION, VERR_VERSION_MISMATCH);
811	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
812	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
813	return VINF_SUCCESS;
814	}
815
816	#endif
817
818
819	/**
820	* The device registration structure.
821	*/
822	const PDMDEVREG g_DeviceIommuIntel =
823	{
824	/* .u32Version = */ PDM_DEVREG_VERSION,
825	/* .uReserved0 = */ 0,
826	/* .szName = */ "iommu-intel",
827	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
828	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
829	/* .cMaxInstances = */ 1,
830	/* .uSharedVersion = */ 42,
831	/* .cbInstanceShared = */ sizeof(IOMMU),
832	/* .cbInstanceCC = */ sizeof(IOMMUCC),
833	/* .cbInstanceRC = */ sizeof(IOMMURC),
834	/* .cMaxPciDevices = / 1, /* @todo Make this 0 if this isn't a PCI device. */
835	/* .cMaxMsixVectors = */ 0,
836	/* .pszDescription = */ "IOMMU (Intel)",
837	#if defined(IN_RING3)
838	/* .pszRCMod = */ "VBoxDDRC.rc",
839	/* .pszR0Mod = */ "VBoxDDR0.r0",
840	/* .pfnConstruct = */ iommuIntelR3Construct,
841	/* .pfnDestruct = */ iommuIntelR3Destruct,
842	/* .pfnRelocate = */ NULL,
843	/* .pfnMemSetup = */ NULL,
844	/* .pfnPowerOn = */ NULL,
845	/* .pfnReset = */ iommuIntelR3Reset,
846	/* .pfnSuspend = */ NULL,
847	/* .pfnResume = */ NULL,
848	/* .pfnAttach = */ NULL,
849	/* .pfnDetach = */ NULL,
850	/* .pfnQueryInterface = */ NULL,
851	/* .pfnInitComplete = */ NULL,
852	/* .pfnPowerOff = */ NULL,
853	/* .pfnSoftReset = */ NULL,
854	/* .pfnReserved0 = */ NULL,
855	/* .pfnReserved1 = */ NULL,
856	/* .pfnReserved2 = */ NULL,
857	/* .pfnReserved3 = */ NULL,
858	/* .pfnReserved4 = */ NULL,
859	/* .pfnReserved5 = */ NULL,
860	/* .pfnReserved6 = */ NULL,
861	/* .pfnReserved7 = */ NULL,
862	#elif defined(IN_RING0)
863	/* .pfnEarlyConstruct = */ NULL,
864	/* .pfnConstruct = */ iommuIntelRZConstruct,
865	/* .pfnDestruct = */ NULL,
866	/* .pfnFinalDestruct = */ NULL,
867	/* .pfnRequest = */ NULL,
868	/* .pfnReserved0 = */ NULL,
869	/* .pfnReserved1 = */ NULL,
870	/* .pfnReserved2 = */ NULL,
871	/* .pfnReserved3 = */ NULL,
872	/* .pfnReserved4 = */ NULL,
873	/* .pfnReserved5 = */ NULL,
874	/* .pfnReserved6 = */ NULL,
875	/* .pfnReserved7 = */ NULL,
876	#elif defined(IN_RC)
877	/* .pfnConstruct = */ iommuIntelRZConstruct,
878	/* .pfnReserved0 = */ NULL,
879	/* .pfnReserved1 = */ NULL,
880	/* .pfnReserved2 = */ NULL,
881	/* .pfnReserved3 = */ NULL,
882	/* .pfnReserved4 = */ NULL,
883	/* .pfnReserved5 = */ NULL,
884	/* .pfnReserved6 = */ NULL,
885	/* .pfnReserved7 = */ NULL,
886	#else
887	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
888	#endif
889	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
890	};
891
892	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
893

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88310

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