DevIommuIntel.cpp@ 88765

Last change on this file since 88765 was 88765, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 WIP.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 108.7 KB

Line
1	/* $Id: DevIommuIntel.cpp 88765 2021-04-29 07:10:23Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock and is not expected to fail. */
67	#define DMAR_LOCK(a_pDevIns, a_pThisCC) \
68	do { \
69	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED); \
70	Assert(rcLock == VINF_SUCCESS); \
71	} while (0)
72
73	/** Release the DMAR lock. */
74	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
75
76	/** Asserts that the calling thread owns the DMAR lock. */
77	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
78	do { \
79	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
80	RT_NOREF1(a_pThisCC); \
81	} while (0)
82
83	/** The number of fault recording registers our implementation supports.
84	* Normal guest operation shouldn't trigger faults anyway, so we only support the
85	* minimum number of registers (which is 1).
86	*
87	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
88	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
89
90	/** Offset of first register in group 0. */
91	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
92	/** Offset of last register in group 0 (inclusive). */
93	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
94	/** Last valid offset in group 0 (exclusive). */
95	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
96	/** Size of the group 0 (in bytes). */
97	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
98	/*< Implementation-specific MMIO offset of IVA_REG. /
99	#define DMAR_MMIO_OFF_IVA_REG 0xe50
100	/*< Implementation-specific MMIO offset of IOTLB_REG. /
101	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
102	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
103	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
104	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
105	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
106	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
107
108	/** Offset of first register in group 1. */
109	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
110	/** Offset of last register in group 1 (inclusive). */
111	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
112	/** Last valid offset in group 1 (exclusive). */
113	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
114	/** Size of the group 1 (in bytes). */
115	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
116
117	/** DMAR implementation's major version number (exposed to software).
118	* We report 6 as the major version since we support queued-invalidations as
119	* software may make assumptions based on that.
120	*
121	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
122	#define DMAR_VER_MAJOR 6
123	/** DMAR implementation's minor version number (exposed to software). */
124	#define DMAR_VER_MINOR 0
125
126	/** Release log prefix string. */
127	#define DMAR_LOG_PFX "Intel-IOMMU"
128	/** The current saved state version. */
129	#define DMAR_SAVED_STATE_VERSION 1
130
131
132	/*********************************************************************************************************************************
133	* Structures and Typedefs *
134	*********************************************************************************************************************************/
135	/**
136	* DMAR error diagnostics.
137	*
138	* @note Members of this enum are used as array indices, so no gaps in enum
139	* values are not allowed. Update g_apszDmarDiagDesc when you modify
140	* fields in this enum.
141	*/
142	typedef enum
143	{
144	kDmarDiag_None = 0,
145	kDmarDiag_IqtReg_Qt_NotAligned,
146	kDmarDiag_IqtReg_Qt_Invalid,
147	kDmarDiag_IqaReg_Dw_Invalid,
148	kDmarDiag_IqaReg_Dsc_Fetch_Error,
149	kDmarDiag_Iqei_Dsc_Type_Invalid,
150	kDmarDiag_CcmdReg_Ttm_Invalid,
151	kDmarDiag_CcmdReg_Qi_Enabled,
152	kDmarDiag_CcmdReg_NotSupported,
153	/* Member for determining array index limit. */
154	kDmarDiag_End,
155	/* Type size hack. */
156	kDmarDiag_32Bit_Hack = 0x7fffffff
157	} DMARDIAG;
158	AssertCompileSize(DMARDIAG, 4);
159
160	/** DMAR diagnostic enum description expansion.
161	* The below construct ensures typos in the input to this macro are caught
162	* during compile time. */
163	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
164
165	/** DMAR diagnostics description. */
166	static const char *const g_apszDmarDiagDesc[] =
167	{
168	DMARDIAG_DESC(None ),
169	DMARDIAG_DESC(IqtReg_Qt_NotAligned ),
170	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
171	DMARDIAG_DESC(IqaReg_Dw_Invalid ),
172	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error),
173	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
174	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
175	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
176	DMARDIAG_DESC(CcmdReg_NotSupported )
177	/* kDmarDiag_End */
178	};
179	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
180	#undef DMARDIAG_DESC
181
182	/**
183	* The shared DMAR device state.
184	*/
185	typedef struct DMAR
186	{
187	/** IOMMU device index. */
188	uint32_t idxIommu;
189	/** DMAR magic. */
190	uint32_t u32Magic;
191
192	/** Registers (group 0). */
193	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
194	/** Registers (group 1). */
195	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
196
197	/** @name Lazily activated registers.
198	* These are the active values for lazily activated registers. Software is free to
199	* modify the actual register values while remapping/translation is enabled but they
200	* take effect only when explicitly signaled by software, hence we need to hold the
201	* active values separately.
202	* @{ */
203	/** Currently active IRTA_REG. */
204	uint64_t uIrtaReg;
205	/** Currently active RTADDR_REG. */
206	uint64_t uRtaReg;
207	/** @} */
208
209	/** @name Register copies for a tiny bit faster and more convenient access.
210	* @{ */
211	/** Copy of VER_REG. */
212	uint8_t uVerReg;
213	/** Alignment. */
214	uint8_t abPadding[7];
215	/** Copy of CAP_REG. */
216	uint64_t fCap;
217	/** Copy of ECAP_REG. */
218	uint64_t fExtCap;
219	/** @} */
220
221	/** The event semaphore the invalidation-queue thread waits on. */
222	SUPSEMEVENT hEvtInvQueue;
223	/** Whether the invalidation-queue thread has been signaled. */
224	bool volatile fInvQueueThreadSignaled;
225	/** Padding. */
226	bool afPadding0[3];
227	/** Error diagnostic. */
228	DMARDIAG enmDiag;
229	/** The MMIO handle. */
230	IOMMMIOHANDLE hMmio;
231
232	#ifdef VBOX_WITH_STATISTICS
233	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
234	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
235	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
236	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
237
238	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
239	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
240
241	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
242	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
243	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
244	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
245
246	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
247	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
248	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
249	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
250	#endif
251	} DMAR;
252	/** Pointer to the DMAR device state. */
253	typedef DMAR *PDMAR;
254	/** Pointer to the const DMAR device state. */
255	typedef DMAR const *PCDMAR;
256	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
257	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
258
259	/**
260	* The ring-3 DMAR device state.
261	*/
262	typedef struct DMARR3
263	{
264	/** Device instance. */
265	PPDMDEVINSR3 pDevInsR3;
266	/** The IOMMU helper. */
267	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
268	/** The invalidation-queue thread. */
269	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
270	} DMARR3;
271	/** Pointer to the ring-3 DMAR device state. */
272	typedef DMARR3 *PDMARR3;
273	/** Pointer to the const ring-3 DMAR device state. */
274	typedef DMARR3 const *PCDMARR3;
275
276	/**
277	* The ring-0 DMAR device state.
278	*/
279	typedef struct DMARR0
280	{
281	/** Device instance. */
282	PPDMDEVINSR0 pDevInsR0;
283	/** The IOMMU helper. */
284	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
285	} DMARR0;
286	/** Pointer to the ring-0 IOMMU device state. */
287	typedef DMARR0 *PDMARR0;
288	/** Pointer to the const ring-0 IOMMU device state. */
289	typedef DMARR0 const *PCDMARR0;
290
291	/**
292	* The raw-mode DMAR device state.
293	*/
294	typedef struct DMARRC
295	{
296	/** Device instance. */
297	PPDMDEVINSRC pDevInsRC;
298	/** The IOMMU helper. */
299	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
300	} DMARRC;
301	/** Pointer to the raw-mode DMAR device state. */
302	typedef DMARRC *PDMARRC;
303	/** Pointer to the const raw-mode DMAR device state. */
304	typedef DMARRC const *PCIDMARRC;
305
306	/** The DMAR device state for the current context. */
307	typedef CTX_SUFF(DMAR) DMARCC;
308	/** Pointer to the DMAR device state for the current context. */
309	typedef CTX_SUFF(PDMAR) PDMARCC;
310	/** Pointer to the const DMAR device state for the current context. */
311	typedef CTX_SUFF(PDMAR) const PCDMARCC;
312
313
314	/*********************************************************************************************************************************
315	* Global Variables *
316	*********************************************************************************************************************************/
317	/**
318	* Read-write masks for DMAR registers (group 0).
319	*/
320	static uint32_t const g_au32RwMasks0[] =
321	{
322	/* Offset Register Low High */
323	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
324	/* 0x004 Reserved */ 0,
325	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
326	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
327	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
328	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
329	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
330	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
331	/* 0x030 Reserved */ 0,
332	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
333	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
334	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
335	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
336	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
337	/* 0x048 Reserved */ 0, 0,
338	/* 0x050 Reserved */ 0, 0,
339	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
340	/* 0x060 Reserved */ 0,
341	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
342	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
343	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
344	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
345	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
346	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
347	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
348	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
349	/* 0x098 Reserved */ 0,
350	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
351	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
352	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
353	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
354	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
355	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
356	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
357	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
358	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
359	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
360	/* 0x0d8 Reserved */ 0,
361	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
362	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
363	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
364	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
365	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
366	/* 0x0f0 Reserved */ 0, 0,
367	/* 0x0f8 Reserved */ 0, 0,
368	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
369	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
370	/* 0x110 Reserved */ 0, 0,
371	/* 0x118 Reserved */ 0, 0,
372	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
373	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
374	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
375	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
376	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
377	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
378	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
379	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
380	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
381	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
382	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
383	/* 0x178 Reserved */ 0, 0,
384	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
385	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
386	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
387	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
388	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
389	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
390	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
391	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
392	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
393	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
394	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
395	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
396	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
397	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
398	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
399	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
400	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
401	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
402	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
403	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
404	};
405	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
406
407	/**
408	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
409	*/
410	static uint32_t const g_au32Rw1cMasks0[] =
411	{
412	/* Offset Register Low High */
413	/* 0x000 VER_REG */ 0,
414	/* 0x004 Reserved */ 0,
415	/* 0x008 CAP_REG */ 0, 0,
416	/* 0x010 ECAP_REG */ 0, 0,
417	/* 0x018 GCMD_REG */ 0,
418	/* 0x01c GSTS_REG */ 0,
419	/* 0x020 RTADDR_REG */ 0, 0,
420	/* 0x028 CCMD_REG */ 0, 0,
421	/* 0x030 Reserved */ 0,
422	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
423	/* 0x038 FECTL_REG */ 0,
424	/* 0x03c FEDATA_REG */ 0,
425	/* 0x040 FEADDR_REG */ 0,
426	/* 0x044 FEUADDR_REG */ 0,
427	/* 0x048 Reserved */ 0, 0,
428	/* 0x050 Reserved */ 0, 0,
429	/* 0x058 AFLOG_REG */ 0, 0,
430	/* 0x060 Reserved */ 0,
431	/* 0x064 PMEN_REG */ 0,
432	/* 0x068 PLMBASE_REG */ 0,
433	/* 0x06c PLMLIMIT_REG */ 0,
434	/* 0x070 PHMBASE_REG */ 0, 0,
435	/* 0x078 PHMLIMIT_REG */ 0, 0,
436	/* 0x080 IQH_REG */ 0, 0,
437	/* 0x088 IQT_REG */ 0, 0,
438	/* 0x090 IQA_REG */ 0, 0,
439	/* 0x098 Reserved */ 0,
440	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
441	/* 0x0a0 IECTL_REG */ 0,
442	/* 0x0a4 IEDATA_REG */ 0,
443	/* 0x0a8 IEADDR_REG */ 0,
444	/* 0x0ac IEUADDR_REG */ 0,
445	/* 0x0b0 IQERCD_REG */ 0, 0,
446	/* 0x0b8 IRTA_REG */ 0, 0,
447	/* 0x0c0 PQH_REG */ 0, 0,
448	/* 0x0c8 PQT_REG */ 0, 0,
449	/* 0x0d0 PQA_REG */ 0, 0,
450	/* 0x0d8 Reserved */ 0,
451	/* 0x0dc PRS_REG */ 0,
452	/* 0x0e0 PECTL_REG */ 0,
453	/* 0x0e4 PEDATA_REG */ 0,
454	/* 0x0e8 PEADDR_REG */ 0,
455	/* 0x0ec PEUADDR_REG */ 0,
456	/* 0x0f0 Reserved */ 0, 0,
457	/* 0x0f8 Reserved */ 0, 0,
458	/* 0x100 MTRRCAP_REG */ 0, 0,
459	/* 0x108 MTRRDEF_REG */ 0, 0,
460	/* 0x110 Reserved */ 0, 0,
461	/* 0x118 Reserved */ 0, 0,
462	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
463	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
464	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
465	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
466	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
467	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
468	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
469	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
470	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
471	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
472	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
473	/* 0x178 Reserved */ 0, 0,
474	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
475	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
476	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
477	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
478	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
479	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
480	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
481	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
482	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
483	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
484	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
485	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
486	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
487	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
488	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
489	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
490	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
491	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
492	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
493	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
494	};
495	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
496
497	/**
498	* Read-write masks for DMAR registers (group 1).
499	*/
500	static uint32_t const g_au32RwMasks1[] =
501	{
502	/* Offset Register Low High */
503	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
504	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
505	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
506	/* 0xe18 VCMDRSVD_REG */ 0, 0,
507	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
508	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
509	/* 0xe30 Reserved */ 0, 0,
510	/* 0xe38 Reserved */ 0, 0,
511	/* 0xe40 Reserved */ 0, 0,
512	/* 0xe48 Reserved */ 0, 0,
513	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
514	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
515	/* 0xe60 Reserved */ 0, 0,
516	/* 0xe68 Reserved */ 0, 0,
517	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
518	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
519	};
520	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
521	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
522
523	/**
524	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
525	*/
526	static uint32_t const g_au32Rw1cMasks1[] =
527	{
528	/* Offset Register Low High */
529	/* 0xe00 VCCAP_REG */ 0, 0,
530	/* 0xe08 VCMD_EO_REG */ 0, 0,
531	/* 0xe10 VCMD_REG */ 0, 0,
532	/* 0xe18 VCMDRSVD_REG */ 0, 0,
533	/* 0xe20 VCRSP_REG */ 0, 0,
534	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
535	/* 0xe30 Reserved */ 0, 0,
536	/* 0xe38 Reserved */ 0, 0,
537	/* 0xe40 Reserved */ 0, 0,
538	/* 0xe48 Reserved */ 0, 0,
539	/* 0xe50 IVA_REG */ 0, 0,
540	/* 0xe58 IOTLB_REG */ 0, 0,
541	/* 0xe60 Reserved */ 0, 0,
542	/* 0xe68 Reserved */ 0, 0,
543	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
544	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
545	};
546	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
547
548	/** Array of RW masks for each register group. */
549	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
550
551	/** Array of RW1C masks for each register group. */
552	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
553
554	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
555	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
556
557
558	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
559	/** @todo Add IOMMU struct size/alignment verification, see
560	* Devices/testcase/Makefile.kmk and
561	* Devices/testcase/tstDeviceStructSize[RC].cpp */
562
563	/**
564	* Returns the number of supported adjusted guest-address width (SAGAW) in bits
565	* given a CAP_REG.SAGAW value.
566	*
567	* @returns Number of SAGAW bits.
568	* @param uSagaw The CAP_REG.SAGAW value.
569	*/
570	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
571	{
572	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
573	return 30 + (uSagaw * 9);
574	return 0;
575	}
576
577
578	/**
579	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
580	* guest address width (MGAW).
581	*
582	* @returns The CAP_REG.SAGAW value.
583	* @param uMgaw The CAP_REG.MGAW value.
584	*/
585	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
586	{
587	switch (uMgaw + 1)
588	{
589	case 39: return 1;
590	case 48: return 2;
591	case 57: return 3;
592	}
593	return 0;
594	}
595
596
597	/**
598	* Returns table translation mode's descriptive name.
599	*
600	* @returns The descriptive name.
601	* @param uTtm The RTADDR_REG.TTM value.
602	*/
603	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
604	{
605	Assert(!(uTtm & 3));
606	static const char* s_apszTtmNames[] =
607	{
608	"Legacy Mode",
609	"Scalable Mode",
610	"Reserved",
611	"Abort-DMA Mode"
612	};
613	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
614	}
615
616
617	/**
618	* Gets the index of the group the register belongs to given its MMIO offset.
619	*
620	* @returns The group index.
621	* @param offReg The MMIO offset of the register.
622	* @param cbReg The size of the access being made (for bounds checking on
623	* debug builds).
624	*/
625	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
626	{
627	uint16_t const offLast = offReg + cbReg - 1;
628	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
629	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
630	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
631	}
632
633
634	/**
635	* Gets the group the register belongs to given its MMIO offset.
636	*
637	* @returns Pointer to the first element of the register group.
638	* @param pThis The shared DMAR device state.
639	* @param offReg The MMIO offset of the register.
640	* @param cbReg The size of the access being made (for bounds checking on
641	* debug builds).
642	* @param pIdxGroup Where to store the index of the register group the register
643	* belongs to.
644	*/
645	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
646	{
647	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
648	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
649	return apbRegs[*pIdxGroup];
650	}
651
652
653	/**
654	* Const/read-only version of dmarRegGetGroup.
655	*
656	* @copydoc dmarRegGetGroup
657	*/
658	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
659	{
660	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
661	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
662	return apbRegs[*pIdxGroup];
663	}
664
665
666	/**
667	* Writes a 32-bit register with the exactly the supplied value.
668	*
669	* @param pThis The shared DMAR device state.
670	* @param offReg The MMIO offset of the register.
671	* @param uReg The 32-bit value to write.
672	*/
673	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
674	{
675	uint8_t idxGroup;
676	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
677	NOREF(idxGroup);
678	(uint32_t )(pabRegs + offReg) = uReg;
679	}
680
681
682	/**
683	* Writes a 64-bit register with the exactly the supplied value.
684	*
685	* @param pThis The shared DMAR device state.
686	* @param offReg The MMIO offset of the register.
687	* @param uReg The 64-bit value to write.
688	*/
689	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
690	{
691	uint8_t idxGroup;
692	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
693	NOREF(idxGroup);
694	(uint64_t )(pabRegs + offReg) = uReg;
695	}
696
697
698	/**
699	* Reads a 32-bit register with exactly the value it contains.
700	*
701	* @returns The raw register value.
702	* @param pThis The shared DMAR device state.
703	* @param offReg The MMIO offset of the register.
704	*/
705	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
706	{
707	uint8_t idxGroup;
708	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
709	NOREF(idxGroup);
710	return (uint32_t )(pabRegs + offReg);
711	}
712
713
714	/**
715	* Reads a 64-bit register with exactly the value it contains.
716	*
717	* @returns The raw register value.
718	* @param pThis The shared DMAR device state.
719	* @param offReg The MMIO offset of the register.
720	*/
721	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
722	{
723	uint8_t idxGroup;
724	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
725	NOREF(idxGroup);
726	return (uint64_t )(pabRegs + offReg);
727	}
728
729
730	/**
731	* Reads a 32-bit register with exactly the value it contains along with their
732	* corresponding masks
733	*
734	* @param pThis The shared DMAR device state.
735	* @param offReg The MMIO offset of the register.
736	* @param puReg Where to store the raw 32-bit register value.
737	* @param pfRwMask Where to store the RW mask corresponding to this register.
738	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
739	*/
740	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
741	{
742	uint8_t idxGroup;
743	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
744	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
745	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
746	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
747	puReg = (uint32_t *)(pabRegs + offReg);
748	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
749	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
750	}
751
752
753	/**
754	* Reads a 64-bit register with exactly the value it contains along with their
755	* corresponding masks.
756	*
757	* @param pThis The shared DMAR device state.
758	* @param offReg The MMIO offset of the register.
759	* @param puReg Where to store the raw 64-bit register value.
760	* @param pfRwMask Where to store the RW mask corresponding to this register.
761	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
762	*/
763	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
764	{
765	uint8_t idxGroup;
766	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
767	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
768	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
769	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
770	puReg = (uint64_t *)(pabRegs + offReg);
771	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
772	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
773	}
774
775
776	/**
777	* Writes a 32-bit register as it would be when written by software.
778	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
779	*
780	* @returns The value that's actually written to the register.
781	* @param pThis The shared DMAR device state.
782	* @param offReg The MMIO offset of the register.
783	* @param uReg The 32-bit value to write.
784	*/
785	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
786	{
787	/* Read current value from the 32-bit register. */
788	uint32_t uCurReg;
789	uint32_t fRwMask;
790	uint32_t fRw1cMask;
791	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
792
793	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
794	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
795	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
796	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
797
798	/* Write new value to the 32-bit register. */
799	dmarRegWriteRaw32(pThis, offReg, uNewReg);
800	return uNewReg;
801	}
802
803
804	/**
805	* Writes a 64-bit register as it would be when written by software.
806	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
807	*
808	* @returns The value that's actually written to the register.
809	* @param pThis The shared DMAR device state.
810	* @param offReg The MMIO offset of the register.
811	* @param uReg The 64-bit value to write.
812	*/
813	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
814	{
815	/* Read current value from the 64-bit register. */
816	uint64_t uCurReg;
817	uint64_t fRwMask;
818	uint64_t fRw1cMask;
819	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
820
821	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
822	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
823	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
824	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
825
826	/* Write new value to the 64-bit register. */
827	dmarRegWriteRaw64(pThis, offReg, uNewReg);
828	return uNewReg;
829	}
830
831
832	/**
833	* Reads a 32-bit register as it would be when read by software.
834	*
835	* @returns The register value.
836	* @param pThis The shared DMAR device state.
837	* @param offReg The MMIO offset of the register.
838	*/
839	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
840	{
841	return dmarRegReadRaw32(pThis, offReg);
842	}
843
844
845	/**
846	* Reads a 64-bit register as it would be when read by software.
847	*
848	* @returns The register value.
849	* @param pThis The shared DMAR device state.
850	* @param offReg The MMIO offset of the register.
851	*/
852	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
853	{
854	return dmarRegReadRaw64(pThis, offReg);
855	}
856
857
858	/**
859	* Modifies a 32-bit register.
860	*
861	* @param pThis The shared DMAR device state.
862	* @param offReg The MMIO offset of the register.
863	* @param fAndMask The AND mask (applied first).
864	* @param fOrMask The OR mask.
865	* @remarks This does NOT apply RO or RW1C masks while modifying the
866	* register.
867	*/
868	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
869	{
870	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
871	uReg = (uReg & fAndMask) \| fOrMask;
872	dmarRegWriteRaw32(pThis, offReg, uReg);
873	}
874
875
876	/**
877	* Modifies a 64-bit register.
878	*
879	* @param pThis The shared DMAR device state.
880	* @param offReg The MMIO offset of the register.
881	* @param fAndMask The AND mask (applied first).
882	* @param fOrMask The OR mask.
883	* @remarks This does NOT apply RO or RW1C masks while modifying the
884	* register.
885	*/
886	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
887	{
888	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
889	uReg = (uReg & fAndMask) \| fOrMask;
890	dmarRegWriteRaw64(pThis, offReg, uReg);
891	}
892
893
894	/**
895	* Gets the table translation mode from the RTADDR_REG.
896	*
897	* @returns The table translation mode.
898	* @param pThis The shared DMAR device state.
899	*/
900	static uint8_t dmarRtAddrRegGetTtm(PCDMAR pThis)
901	{
902	uint64_t const uRtAddrReg = dmarRegRead64(pThis, VTD_MMIO_OFF_RTADDR_REG);
903	return RT_BF_GET(uRtAddrReg, VTD_BF_RTADDR_REG_TTM);
904	}
905
906
907	/**
908	* Checks if the invalidation-queue is empty.
909	*
910	* Extended version which optionally returns the current queue head and tail
911	* offsets.
912	*
913	* @returns @c true if empty, @c false otherwise.
914	* @param pThis The shared DMAR device state.
915	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
916	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
917	*/
918	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
919	{
920	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
921	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
922	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
923
924	/* Don't bother masking QT, QH since other bits are RsvdZ. */
925	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
926	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
927	if (poffQh)
928	*poffQh = uIqhReg;
929	if (poffQt)
930	*poffQt = uIqtReg;
931	return uIqtReg == uIqhReg;
932	}
933
934
935	/**
936	* Checks if the invalidation-queue is empty.
937	*
938	* @returns @c true if empty, @c false otherwise.
939	* @param pThis The shared DMAR device state.
940	*/
941	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
942	{
943	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
944	}
945
946
947	/**
948	* Checks if the invalidation-queue is capable of processing requests.
949	*
950	* @returns @c true if the invalidation-queue can process requests, @c false
951	* otherwise.
952	* @param pThis The shared DMAR device state.
953	*/
954	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
955	{
956	/* Check if queued-invalidation is enabled. */
957	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
958	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
959	{
960	/* Check if there are no invalidation-queue or timeout errors. */
961	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
962	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
963	return true;
964	}
965	return false;
966	}
967
968
969	/**
970	* Wakes up the invalidation-queue thread if there are requests to be processed.
971	*
972	* @param pDevIns The IOMMU device instance.
973	*/
974	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
975	{
976	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
977	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
978	Log4Func(("\n"));
979
980	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
981
982	if ( dmarInvQueueCanProcessRequests(pThis)
983	&& !dmarInvQueueIsEmpty(pThis)
984	&& !ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, true))
985	{
986	Log4Func(("Signaling the invalidation-queue thread\n"));
987	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
988	}
989	}
990
991
992	/**
993	* Raises an interrupt in response to an event.
994	*
995	* @param pDevIns The IOMMU device instance.
996	*/
997	static void dmarFaultRaiseInterrupt(PPDMDEVINS pDevIns)
998	{
999	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1000	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1001	#ifdef RT_STRICT
1002	{
1003	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1004	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1005	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1006	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1007	\| VTD_BF_FSTS_REG_IQE_MASK;
1008	Assert(uFstsReg & fFaultMask);
1009	}
1010	#endif
1011
1012	uint32_t uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
1013	if (!(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1014	{
1015	/* Software has unmasked the interrupt, raise it. */
1016	MSIMSG Msi;
1017	Msi.Addr.u64 = RT_MAKE_U64(dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG),
1018	dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG));
1019	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
1020
1021	/** @todo Assert Msi.Addr is in the MSR_IA32_APICBASE_ADDR range and ensure on
1022	* FEADD_REG write it can't be anything else. */
1023
1024	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1025
1026	/* Clear interrupt pending bit. */
1027	uFectlReg &= ~VTD_BF_FECTL_REG_IP_MASK;
1028	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1029	}
1030	else
1031	{
1032	/* Interrupt is masked, set the interrupt pending bit. */
1033	uFectlReg \|= VTD_BF_FECTL_REG_IP_MASK;
1034	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1035	}
1036	}
1037
1038
1039	#if 0
1040	/**
1041	* Checks if a primary fault can be recorded.
1042	*
1043	* @returns @c true if the fault can be recorded, @c false otherwise.
1044	* @param pDevIns The IOMMU device instance.
1045	* @param pThis The shared DMAR device state.
1046	*/
1047	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1048	{
1049	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1050	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1051
1052	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1053	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1054	return false;
1055
1056	/*
1057	* If we add more FRCD registers, we'll have to loop through them here.
1058	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1059	* nor do we need to increment FRI.
1060	*
1061	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1062	*/
1063	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1064	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1065	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1066	{
1067	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1068	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1069	return false;
1070	}
1071
1072	uFstsReg \|= VTD_BF_FSTS_REG_PPF_MASK;
1073	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1074	return true;
1075	}
1076	#endif
1077
1078
1079	/**
1080	* Records an IQE fault.
1081	*
1082	* @param pDevIns The IOMMU device instance.
1083	* @param enmIqei The IQE information.
1084	* @param enmDiag The diagnostic reason.
1085	*/
1086	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IQEI_T enmIqei)
1087	{
1088	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1089	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1090	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1091
1092	/* Update the diagnostic reason. */
1093	pThis->enmDiag = enmDiag;
1094
1095	/* Set the error bit. */
1096	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1097	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1098
1099	/* Set the error information. */
1100	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1101	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1102
1103	dmarFaultRaiseInterrupt(pDevIns);
1104	}
1105
1106
1107	/**
1108	* Handles writes to GCMD_REG.
1109	*
1110	* @returns Strict VBox status code.
1111	* @param pDevIns The IOMMU device instance.
1112	* @param uGcmdReg The value written to GCMD_REG.
1113	*/
1114	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1115	{
1116	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1117	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1118	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1119	uint64_t const fExtCap = pThis->fExtCap;
1120
1121	/*
1122	* Queued-invalidation.
1123	*/
1124	if ( (fExtCap & VTD_BF_ECAP_REG_QI_MASK)
1125	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1126	{
1127	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1128	{
1129	/* Enable the invalidation-queue. */
1130	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX /* fAndMask /, VTD_BF_GSTS_REG_QIES_MASK / fOrMask */);
1131	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1132	}
1133	else
1134	{
1135	/* Disable the invalidation-queue. */
1136	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK /* fAndMask /, 0 / fOrMask */);
1137	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1138	}
1139	}
1140
1141	/*
1142	* Set interrupt remapping table pointer.
1143	*/
1144	if ( (fExtCap & VTD_BF_ECAP_REG_IR_MASK)
1145	&& (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK))
1146	{
1147	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1148	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX /* fAndMask /, VTD_BF_GSTS_REG_IRTPS_MASK / fOrMask */);
1149	}
1150
1151	/** @todo Rest of the bits. */
1152
1153	return VINF_SUCCESS;
1154	}
1155
1156
1157	/**
1158	* Handles writes to CCMD_REG.
1159	*
1160	* @returns Strict VBox status code.
1161	* @param pDevIns The IOMMU device instance.
1162	* @param offReg The MMIO register offset.
1163	* @param cbReg The size of the MMIO access (in bytes).
1164	* @param uCcmdReg The value written to CCMD_REG.
1165	*/
1166	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1167	{
1168	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1169	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1170	{
1171	/* Check if we need to invalidate the context-context. */
1172	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1173	if (fIcc)
1174	{
1175	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1176	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1177	if (uMajorVersion < 6)
1178	{
1179	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1180	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1181	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1182	{
1183	/* Verify table translation mode is legacy. */
1184	uint8_t const fTtm = dmarRtAddrRegGetTtm(pThis);
1185	if (fTtm == VTD_TTM_LEGACY_MODE)
1186	{
1187	/** @todo Invalidate. */
1188	return VINF_SUCCESS;
1189	}
1190	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1191	}
1192	else
1193	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1194	}
1195	else
1196	pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1197	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK /* fAndMask /, 0 / fOrMask */);
1198	}
1199	}
1200	return VINF_SUCCESS;
1201	}
1202
1203
1204	/**
1205	* Handles writes to IQT_REG.
1206	*
1207	* @returns Strict VBox status code.
1208	* @param pDevIns The IOMMU device instance.
1209	* @param offReg The MMIO register offset.
1210	* @param uIqtReg The value written to IQT_REG.
1211	*/
1212	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1213	{
1214	/* We only care about the low 32-bits, high 32-bits are reserved. */
1215	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1216	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1217
1218	/* Paranoia. */
1219	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1220
1221	uint32_t const offQt = uIqtReg;
1222	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1223	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1224
1225	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1226	if ( fDw != VTD_IQA_REG_DW_256_BIT
1227	\|\| !(offQt & RT_BIT(4)))
1228	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1229	else
1230	{
1231	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1232	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4) /* fAndMask/ , 0 / fOrMask */);
1233	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, kIqei_QueueTailNotAligned);
1234	}
1235	return VINF_SUCCESS;
1236	}
1237
1238
1239	/**
1240	* Handles writes to IQA_REG.
1241	*
1242	* @returns Strict VBox status code.
1243	* @param pDevIns The IOMMU device instance.
1244	* @param offReg The MMIO register offset.
1245	* @param uIqaReg The value written to IQA_REG.
1246	*/
1247	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1248	{
1249	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1250	Assert(offReg == VTD_MMIO_OFF_IQA_REG);
1251
1252	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1253	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1254	* cannot happen or that it's ignored when it does happen. */
1255
1256	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1257	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1258	if (fDw == VTD_IQA_REG_DW_256_BIT)
1259	{
1260	bool const fSupports256BitDw = (pThis->fExtCap & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1261	if (fSupports256BitDw)
1262	{ /* likely */ }
1263	else
1264	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_Invalid, kIqei_InvalidDescriptorWidth);
1265	}
1266	return VINF_SUCCESS;
1267	}
1268
1269
1270	/**
1271	* Memory access bulk (one or more 4K pages) request from a device.
1272	*
1273	* @returns VBox status code.
1274	* @param pDevIns The IOMMU device instance.
1275	* @param idDevice The device ID (bus, device, function).
1276	* @param cIovas The number of addresses being accessed.
1277	* @param pauIovas The I/O virtual addresses for each page being accessed.
1278	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1279	* @param paGCPhysSpa Where to store the translated physical addresses.
1280	*
1281	* @thread Any.
1282	*/
1283	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1284	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1285	{
1286	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1287	return VERR_NOT_IMPLEMENTED;
1288	}
1289
1290
1291	/**
1292	* Memory access transaction from a device.
1293	*
1294	* @returns VBox status code.
1295	* @param pDevIns The IOMMU device instance.
1296	* @param idDevice The device ID (bus, device, function).
1297	* @param uIova The I/O virtual address being accessed.
1298	* @param cbIova The size of the access.
1299	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1300	* @param pGCPhysSpa Where to store the translated system physical address.
1301	* @param pcbContiguous Where to store the number of contiguous bytes translated
1302	* and permission-checked.
1303	*
1304	* @thread Any.
1305	*/
1306	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1307	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
1308	{
1309	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
1310	return VERR_NOT_IMPLEMENTED;
1311	}
1312
1313
1314	/**
1315	* Interrupt remap request from a device.
1316	*
1317	* @returns VBox status code.
1318	* @param pDevIns The IOMMU device instance.
1319	* @param idDevice The device ID (bus, device, function).
1320	* @param pMsiIn The source MSI.
1321	* @param pMsiOut Where to store the remapped MSI.
1322	*/
1323	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1324	{
1325	RT_NOREF3(idDevice, pMsiIn, pMsiOut);
1326	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1327	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap)); NOREF(pThis);
1328
1329	return VERR_NOT_IMPLEMENTED;
1330	}
1331
1332
1333	/**
1334	* @callback_method_impl{FNIOMMMIONEWWRITE}
1335	*/
1336	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1337	{
1338	RT_NOREF1(pvUser);
1339	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1340
1341	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1342	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1343
1344	uint16_t const offReg = off;
1345	uint16_t const offLast = offReg + cb - 1;
1346	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1347	{
1348	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1349	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
1350
1351	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv)
1352	: dmarRegWrite32(pThis, offReg, (uint32_t )pv);
1353	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1354	switch (off)
1355	{
1356	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
1357	{
1358	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
1359	break;
1360	}
1361
1362	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
1363	case VTD_MMIO_OFF_CCMD_REG + 4:
1364	{
1365	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
1366	break;
1367	}
1368
1369	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
1370	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
1371	{
1372	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
1373	break;
1374	}
1375
1376	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
1377	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
1378	{
1379	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
1380	break;
1381	}
1382	}
1383
1384	DMAR_UNLOCK(pDevIns, pThisCC);
1385	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
1386	return rcStrict;
1387	}
1388
1389	return VINF_IOM_MMIO_UNUSED_FF;
1390	}
1391
1392
1393	/**
1394	* @callback_method_impl{FNIOMMMIONEWREAD}
1395	*/
1396	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1397	{
1398	RT_NOREF1(pvUser);
1399	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1400
1401	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1402	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1403
1404	uint16_t const offReg = off;
1405	uint16_t const offLast = offReg + cb - 1;
1406	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1407	{
1408	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1409	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
1410
1411	if (cb == 8)
1412	{
1413	(uint64_t )pv = dmarRegRead64(pThis, offReg);
1414	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
1415	}
1416	else
1417	{
1418	(uint32_t )pv = dmarRegRead32(pThis, offReg);
1419	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
1420	}
1421
1422	DMAR_UNLOCK(pDevIns, pThisCC);
1423	return VINF_SUCCESS;
1424	}
1425
1426	return VINF_IOM_MMIO_UNUSED_FF;
1427	}
1428
1429
1430	#ifdef IN_RING3
1431	/**
1432	* Process requests in the invalidation queue.
1433	*
1434	* @param pDevIns The IOMMU device instance.
1435	* @param pvRequests The requests data.
1436	* @param cbRequests The size of all requests (in bytes).
1437	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
1438	* VTD_IQA_REG_DW_256_BIT).
1439	*/
1440	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw)
1441	{
1442	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
1443	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
1444	{
1445	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
1446	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(puDscQwords[0]);
1447	switch (fDscType)
1448	{
1449	case VTD_CC_INV_DSC_TYPE: LogRelMax(32, ("%s: CC\n", DMAR_LOG_PFX)); break;
1450	case VTD_IOTLB_INV_DSC_TYPE: LogRelMax(32, ("%s: IOTLB\n", DMAR_LOG_PFX)); break;
1451	case VTD_DEV_TLB_INV_DSC_TYPE: LogRelMax(32, ("%s: DEV_TLB\n", DMAR_LOG_PFX)); break;
1452	case VTD_IEC_INV_DSC_TYPE: LogRelMax(32, ("%s: IEC_INV\n", DMAR_LOG_PFX)); break;
1453	case VTD_INV_WAIT_DSC_TYPE: LogRelMax(32, ("%s: INV_WAIT\n", DMAR_LOG_PFX)); break;
1454	case VTD_P_IOTLB_INV_DSC_TYPE: LogRelMax(32, ("%s: P_IOTLB\n", DMAR_LOG_PFX)); break;
1455	case VTD_PC_INV_DSC_TYPE: LogRelMax(32, ("%s: PC_INV\n", DMAR_LOG_PFX)); break;
1456	case VTD_P_DEV_TLB_INV_DSC_TYPE: LogRelMax(32, ("%s: P_DEVL_TLB\n", DMAR_LOG_PFX)); break;
1457	{
1458	break;
1459	}
1460
1461	default:
1462	{
1463	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
1464	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Dsc_Type_Invalid, kIqei_InvalidDescriptorType);
1465	return;
1466	}
1467	}
1468	}
1469	}
1470
1471
1472
1473	/**
1474	* The invalidation-queue thread.
1475	*
1476	* @returns VBox status code.
1477	* @param pDevIns The IOMMU device instance.
1478	* @param pThread The command thread.
1479	*/
1480	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1481	{
1482	NOREF(pThread);
1483	LogFlowFunc(("\n"));
1484
1485	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
1486	return VINF_SUCCESS;
1487
1488	/*
1489	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
1490	* This prevents trashing the heap as well as deal with out-of-memory situations
1491	* up-front while starting the VM. It also simplifies the code from having to
1492	* dynamically grow/shrink the allocation based on how software sizes the queue.
1493	* Guests normally don't alter the queue size all the time, but that's not an
1494	* assumption we can make.
1495	*/
1496	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
1497	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
1498	void *pvRequests = RTMemAllocZ(cbMaxQs);
1499	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
1500
1501	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
1502	{
1503	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1504	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1505
1506	/*
1507	* Sleep until we are woken up.
1508	*/
1509	bool const fSignaled = ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, false);
1510	if (!fSignaled)
1511	{
1512	int rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
1513	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
1514	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
1515	break;
1516	ASMAtomicWriteBool(&pThis->fInvQueueThreadSignaled, false);
1517	}
1518
1519	DMAR_LOCK(pDevIns, pThisR3);
1520	if (dmarInvQueueCanProcessRequests(pThis))
1521	{
1522	uint32_t offQueueHead;
1523	uint32_t offQueueTail;
1524	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
1525	if (!fIsEmpty)
1526	{
1527	/** @todo Handle RTADDR_REG MMIO write first, for handling kIqei_InvalidTtm. I
1528	* don't think it needs to be checked/handled here? */
1529
1530	/*
1531	* Get the current queue size.
1532	*/
1533	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1534	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
1535	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
1536	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1537
1538	/* Paranoia. */
1539	Assert(cbQueue <= cbMaxQs);
1540	Assert(!(offQueueTail & ~VTD_IQT_REG_RW_MASK));
1541	Assert(!(offQueueHead & ~VTD_IQH_REG_RW_MASK));
1542	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
1543	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
1544	Assert(offQueueHead < cbQueue);
1545
1546	/*
1547	* Read the requests in the queue from guest memory into our buffer.
1548	*/
1549	if (offQueueTail < cbQueue)
1550	{
1551	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
1552
1553	/* Don't hold the lock while reading (potentially large amount of) requests. */
1554	DMAR_UNLOCK(pDevIns, pThisR3);
1555
1556	int rc;
1557	uint32_t cbRequests;
1558	if (offQueueTail > offQueueHead)
1559	{
1560	/* The requests have not wrapped around, read them in one go. */
1561	cbRequests = offQueueTail - offQueueHead;
1562	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbRequests);
1563	}
1564	else
1565	{
1566	/* The requests have wrapped around, read forward and wrapped-around. */
1567	uint32_t const cbForward = cbQueue - offQueueHead;
1568	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbForward);
1569
1570	uint32_t const cbWrapped = offQueueTail;
1571	if ( RT_SUCCESS(rc)
1572	&& cbWrapped > 0)
1573	{
1574	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests + cbForward,
1575	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
1576	}
1577	cbRequests = cbForward + cbWrapped;
1578	}
1579
1580	/* Re-acquire the lock since we need to update device state. */
1581	DMAR_LOCK(pDevIns, pThisR3);
1582
1583	if (RT_SUCCESS(rc))
1584	{
1585	/* Indicate to software we've fetched all requests. */
1586	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
1587
1588	/* Process all requests (in FIFO order). */
1589	Assert(cbRequests <= cbQueue);
1590	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw);
1591	}
1592	else
1593	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, kIqei_FetchDescriptorError);
1594	}
1595	else
1596	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, kIqei_InvalidTailPointer);
1597	}
1598	}
1599	DMAR_UNLOCK(pDevIns, pThisR3);
1600	}
1601
1602	RTMemFree(pvRequests);
1603	pvRequests = NULL;
1604
1605	LogFlowFunc(("Invalidation-queue thread terminating\n"));
1606	return VINF_SUCCESS;
1607	}
1608
1609
1610	/**
1611	* Wakes up the invalidation-queue thread so it can respond to a state
1612	* change.
1613	*
1614	* @returns VBox status code.
1615	* @param pDevIns The IOMMU device instance.
1616	* @param pThread The invalidation-queue thread.
1617	*
1618	* @thread EMT.
1619	*/
1620	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1621	{
1622	RT_NOREF(pThread);
1623	LogFlowFunc(("\n"));
1624	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1625	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1626	}
1627
1628
1629	/**
1630	* @callback_method_impl{FNDBGFHANDLERDEV}
1631	*/
1632	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1633	{
1634	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1635	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1636	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1637	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1638
1639	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
1640
1641	/*
1642	* We lock the device to get a consistent register state, but it is
1643	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers into
1644	* temporaries and release the lock ASAP.
1645	*
1646	* Order of register being read and outputted is in accordance with the
1647	* spec. for no particular reason.
1648	* See Intel VT-d spec. 10.4 "Register Descriptions".
1649	*/
1650	DMAR_LOCK(pDevIns, pThisR3);
1651
1652	DMARDIAG const enmDiag = pThis->enmDiag;
1653	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
1654	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
1655	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
1656	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
1657	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1658	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1659	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
1660	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1661	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
1662	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
1663	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
1664	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
1665	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
1666	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
1667	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
1668	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
1669	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
1670	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
1671	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
1672	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
1673	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1674	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1675	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
1676	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
1677	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
1678	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
1679	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
1680	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1681	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
1682	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
1683	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
1684	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
1685	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
1686	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
1687	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
1688	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
1689	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
1690	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
1691	/** @todo Do other registers as required, we don't implement them for now. */
1692
1693	DMAR_UNLOCK(pDevIns, pThisR3);
1694
1695	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
1696	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
1697	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
1698	if (!fVerbose)
1699	{
1700	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
1701	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
1702	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
1703	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
1704	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
1705	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
1706	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
1707	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
1708	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
1709	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
1710	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
1711	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
1712	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
1713	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
1714	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
1715	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
1716	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
1717	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
1718	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
1719	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
1720	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
1721	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
1722	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
1723	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
1724	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
1725	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
1726	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
1727	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
1728	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
1729	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
1730	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
1731	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
1732	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
1733	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
1734	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
1735	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
1736	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
1737	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
1738	pHlp->pfnPrintf(pHlp, "\n");
1739	}
1740	else
1741	{
1742	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
1743	{
1744	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
1745	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
1746	}
1747	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
1748	{
1749	uint8_t const uSagaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW);
1750	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
1751	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
1752	pHlp->pfnPrintf(pHlp, " ND = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
1753	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
1754	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
1755	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
1756	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
1757	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
1758	pHlp->pfnPrintf(pHlp, " SAGAW = %#x (%u bits)\n", uSagaw, vtdCapRegGetSagawBits(uSagaw));
1759	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
1760	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
1761	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
1762	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
1763	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
1764	pHlp->pfnPrintf(pHlp, " NFR = %#x (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
1765	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
1766	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
1767	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
1768	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
1769	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
1770	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
1771	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
1772	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
1773	}
1774	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
1775	{
1776	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
1777	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
1778	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
1779	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
1780	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
1781	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
1782	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
1783	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
1784	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
1785	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
1786	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
1787	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
1788	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
1789	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
1790	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
1791	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
1792	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
1793	pHlp->pfnPrintf(pHlp, " PSS = %#x (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
1794	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
1795	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
1796	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
1797	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
1798	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
1799	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
1800	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
1801	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
1802	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
1803	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
1804	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
1805	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
1806	}
1807	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
1808	{
1809	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
1810	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Bypass interrupt remapping"
1811	: "Block compatible format interrupts");
1812	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
1813	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
1814	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
1815	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
1816	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
1817	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
1818	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
1819	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
1820	}
1821	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
1822	{
1823	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
1824	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Bypass interrupt remapping"
1825	: "Block compatible format interrupts");
1826	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
1827	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
1828	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
1829	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
1830	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
1831	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
1832	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
1833	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
1834	}
1835	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
1836	{
1837	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1838	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
1839	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_RTA));
1840	}
1841	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
1842	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
1843	{
1844	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
1845	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
1846	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
1847	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
1848	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
1849	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
1850	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
1851	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
1852	}
1853
1854	/** @todo Verbose others as needed during debugging/rainy day. */
1855	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
1856	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
1857	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
1858	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
1859	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
1860	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
1861	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
1862	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
1863	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
1864	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
1865	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
1866	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
1867	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
1868	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
1869	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
1870	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
1871	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
1872	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
1873	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
1874	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
1875	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
1876	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
1877	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
1878	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
1879	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
1880	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
1881	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
1882	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
1883	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
1884	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
1885	pHlp->pfnPrintf(pHlp, "\n");
1886	}
1887	}
1888
1889
1890	/**
1891	* Initializes all registers in the DMAR unit.
1892	*
1893	* @param pDevIns The IOMMU device instance.
1894	*/
1895	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
1896	{
1897	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1898
1899	/*
1900	* Wipe all registers (required on reset).
1901	*/
1902	RT_ZERO(pThis->abRegs0);
1903	RT_ZERO(pThis->abRegs1);
1904
1905	/*
1906	* Initialize registers not mutable by software prior to initializing other registers.
1907	*/
1908	/* VER_REG */
1909	{
1910	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
1911	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
1912	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
1913	}
1914
1915	uint8_t const fFlts = 1; /* First-Level translation support. */
1916	uint8_t const fSlts = 1; /* Second-Level translation support. */
1917	uint8_t const fPt = 1; /* Pass-Through support. */
1918	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
1919	uint8_t const fNest = 0; /* Nested translation support. */
1920
1921	/* CAP_REG */
1922	{
1923	uint8_t cGstPhysAddrBits;
1924	uint8_t cGstLinearAddrBits;
1925	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
1926
1927	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
1928	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
1929	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
1930	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
1931	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
1932	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
1933	uint8_t const fMamv = (fSl2gp ? /* Maximum address mask value (for second-level invalidations). */
1934	X86_PAGE_1G_SHIFT : X86_PAGE_2M_SHIFT) - X86_PAGE_4K_SHIFT;
1935	uint8_t const fNd = 2; /* Number of domains (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
1936	7=Reserved). */
1937	uint8_t const fPsi = 1; /* Page selective invalidation. */
1938	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
1939	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
1940	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
1941
1942	pThis->fCap = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
1943	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
1944	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
1945	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
1946	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
1947	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
1948	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
1949	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
1950	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
1951	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
1952	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
1953	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
1954	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
1955	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
1956	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
1957	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
1958	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
1959	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
1960	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
1961	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, 0) /* If we invalidate interrupt cache on SIRTP flow. */
1962	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, 0); /* If we invalidate translation cache on SRTP flow. */
1963	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCap);
1964	}
1965
1966	/* ECAP_REG */
1967	{
1968	uint8_t const fQi = 1; /* Queued-invalidations. */
1969	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
1970	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
1971	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
1972	uint8_t const fSrs = 1; /* Supervisor request support. */
1973	uint8_t const fEim = 1; /* Extended interrupt mode.*/
1974	uint8_t const fAdms = 1; /* Abort DMA mode support. */
1975
1976	pThis->fExtCap = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
1977	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
1978	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
1979	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
1980	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
1981	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
1982	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
1983	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
1984	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
1985	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
1986	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
1987	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
1988	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
1989	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
1990	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
1991	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
1992	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
1993	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
1994	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
1995	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
1996	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
1997	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
1998	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
1999	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
2000	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
2001	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
2002	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
2003	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
2004	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
2005	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCap);
2006	}
2007
2008	/*
2009	* Initialize registers mutable by software.
2010	*/
2011	/* FECTL_REG */
2012	{
2013	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
2014	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
2015	}
2016
2017	/* ICETL_REG */
2018	{
2019	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
2020	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
2021	}
2022
2023	#ifdef VBOX_STRICT
2024	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
2025	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
2026	#endif
2027	}
2028
2029
2030	/**
2031	* @interface_method_impl{PDMDEVREG,pfnReset}
2032	*/
2033	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
2034	{
2035	RT_NOREF1(pDevIns);
2036	LogFlowFunc(("\n"));
2037
2038	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2039	DMAR_LOCK(pDevIns, pThisR3);
2040
2041	dmarR3RegsInit(pDevIns);
2042
2043	DMAR_UNLOCK(pDevIns, pThisR3);
2044	}
2045
2046
2047	/**
2048	* @interface_method_impl{PDMDEVREG,pfnDestruct}
2049	*/
2050	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
2051	{
2052	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2053	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2054	LogFlowFunc(("\n"));
2055
2056	DMAR_LOCK(pDevIns, pThisR3);
2057
2058	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
2059	{
2060	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
2061	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
2062	}
2063
2064	DMAR_UNLOCK(pDevIns, pThisR3);
2065	return VINF_SUCCESS;
2066	}
2067
2068
2069	/**
2070	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2071	*/
2072	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2073	{
2074	RT_NOREF(pCfg);
2075
2076	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2077	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
2078	pThisR3->pDevInsR3 = pDevIns;
2079
2080	LogFlowFunc(("iInstance=%d\n", iInstance));
2081	NOREF(iInstance);
2082
2083	/*
2084	* Register the IOMMU with PDM.
2085	*/
2086	PDMIOMMUREGR3 IommuReg;
2087	RT_ZERO(IommuReg);
2088	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2089	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2090	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2091	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2092	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2093	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
2094	if (RT_FAILURE(rc))
2095	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
2096	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
2097	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2098	N_("IOMMU helper version mismatch; got %#x expected %#x"),
2099	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
2100	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
2101	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2102	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
2103	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
2104	/*
2105	* Use PDM's critical section (via helpers) for the IOMMU device.
2106	*/
2107	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2108	AssertRCReturn(rc, rc);
2109
2110	/*
2111	* Initialize PCI configuration registers.
2112	*/
2113	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2114	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2115
2116	/* Header. */
2117	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2118	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2119	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
2120	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
2121	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
2122	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
2123	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2124	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2125
2126	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
2127	PDMPciDevSetStatus(pPciDev, 0);
2128	PDMPciDevSetCapabilityList(pPciDev, 0);
2129
2130	/** @todo VTBAR at 0x180? */
2131
2132	/*
2133	* Register the PCI function with PDM.
2134	*/
2135	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
2136	AssertLogRelRCReturn(rc, rc);
2137
2138	/** @todo Register MSI but what's the MSI capability offset? */
2139	#if 0
2140	/*
2141	* Register MSI support for the PCI device.
2142	* This must be done -after- registering it as a PCI device!
2143	*/
2144	#endif
2145
2146	/*
2147	* Register MMIO region.
2148	*/
2149	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
2150	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
2151	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
2152	&pThis->hMmio);
2153	AssertLogRelRCReturn(rc, rc);
2154
2155	/*
2156	* Register debugger info items.
2157	*/
2158	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
2159	AssertLogRelRCReturn(rc, rc);
2160
2161	#ifdef VBOX_WITH_STATISTICS
2162	/*
2163	* Statistics.
2164	*/
2165	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
2166	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
2167
2168	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
2169	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
2170
2171	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
2172	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
2173
2174	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
2175	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
2176
2177	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
2178	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
2179
2180	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
2181	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
2182
2183	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
2184	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
2185	#endif
2186
2187	/*
2188	* Initialize registers.
2189	*/
2190	dmarR3RegsInit(pDevIns);
2191
2192	/*
2193	* Create invalidation-queue thread and semaphore.
2194	*/
2195	char szInvQueueThread[32];
2196	RT_ZERO(szInvQueueThread);
2197	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
2198	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
2199	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
2200	AssertLogRelRCReturn(rc, rc);
2201
2202	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
2203	AssertLogRelRCReturn(rc, rc);
2204
2205	/*
2206	* Log some of the features exposed to software.
2207	*/
2208	uint32_t const uVerReg = pThis->uVerReg;
2209	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_MGAW) + 1;
2210	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_SAGAW));
2211	uint16_t const offFrcd = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_FRO);
2212	uint16_t const offIva = RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_IRO);
2213	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
2214	DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
2215	pThis->fCap, pThis->fExtCap, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
2216
2217	return VINF_SUCCESS;
2218	}
2219
2220	#else
2221
2222	/**
2223	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
2224	*/
2225	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
2226	{
2227	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2228	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2229	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
2230	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
2231
2232	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
2233	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2234	AssertRCReturn(rc, rc);
2235
2236	/* Set up the MMIO RZ handlers. */
2237	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
2238	AssertRCReturn(rc, rc);
2239
2240	/* Set up the IOMMU RZ callbacks. */
2241	PDMIOMMUREGCC IommuReg;
2242	RT_ZERO(IommuReg);
2243	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2244	IommuReg.idxIommu = pThis->idxIommu;
2245	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2246	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2247	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2248	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2249
2250	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
2251	AssertRCReturn(rc, rc);
2252	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
2253	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2254	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2255	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
2256	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
2257	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
2258	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
2259
2260	return VINF_SUCCESS;
2261	}
2262
2263	#endif
2264
2265
2266	/**
2267	* The device registration structure.
2268	*/
2269	PDMDEVREG const g_DeviceIommuIntel =
2270	{
2271	/* .u32Version = */ PDM_DEVREG_VERSION,
2272	/* .uReserved0 = */ 0,
2273	/* .szName = */ "iommu-intel",
2274	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
2275	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
2276	/* .cMaxInstances = */ 1,
2277	/* .uSharedVersion = */ 42,
2278	/* .cbInstanceShared = */ sizeof(DMAR),
2279	/* .cbInstanceCC = */ sizeof(DMARCC),
2280	/* .cbInstanceRC = */ sizeof(DMARRC),
2281	/* .cMaxPciDevices = */ 1,
2282	/* .cMaxMsixVectors = */ 0,
2283	/* .pszDescription = */ "IOMMU (Intel)",
2284	#if defined(IN_RING3)
2285	/* .pszRCMod = */ "VBoxDDRC.rc",
2286	/* .pszR0Mod = */ "VBoxDDR0.r0",
2287	/* .pfnConstruct = */ iommuIntelR3Construct,
2288	/* .pfnDestruct = */ iommuIntelR3Destruct,
2289	/* .pfnRelocate = */ NULL,
2290	/* .pfnMemSetup = */ NULL,
2291	/* .pfnPowerOn = */ NULL,
2292	/* .pfnReset = */ iommuIntelR3Reset,
2293	/* .pfnSuspend = */ NULL,
2294	/* .pfnResume = */ NULL,
2295	/* .pfnAttach = */ NULL,
2296	/* .pfnDetach = */ NULL,
2297	/* .pfnQueryInterface = */ NULL,
2298	/* .pfnInitComplete = */ NULL,
2299	/* .pfnPowerOff = */ NULL,
2300	/* .pfnSoftReset = */ NULL,
2301	/* .pfnReserved0 = */ NULL,
2302	/* .pfnReserved1 = */ NULL,
2303	/* .pfnReserved2 = */ NULL,
2304	/* .pfnReserved3 = */ NULL,
2305	/* .pfnReserved4 = */ NULL,
2306	/* .pfnReserved5 = */ NULL,
2307	/* .pfnReserved6 = */ NULL,
2308	/* .pfnReserved7 = */ NULL,
2309	#elif defined(IN_RING0)
2310	/* .pfnEarlyConstruct = */ NULL,
2311	/* .pfnConstruct = */ iommuIntelRZConstruct,
2312	/* .pfnDestruct = */ NULL,
2313	/* .pfnFinalDestruct = */ NULL,
2314	/* .pfnRequest = */ NULL,
2315	/* .pfnReserved0 = */ NULL,
2316	/* .pfnReserved1 = */ NULL,
2317	/* .pfnReserved2 = */ NULL,
2318	/* .pfnReserved3 = */ NULL,
2319	/* .pfnReserved4 = */ NULL,
2320	/* .pfnReserved5 = */ NULL,
2321	/* .pfnReserved6 = */ NULL,
2322	/* .pfnReserved7 = */ NULL,
2323	#elif defined(IN_RC)
2324	/* .pfnConstruct = */ iommuIntelRZConstruct,
2325	/* .pfnReserved0 = */ NULL,
2326	/* .pfnReserved1 = */ NULL,
2327	/* .pfnReserved2 = */ NULL,
2328	/* .pfnReserved3 = */ NULL,
2329	/* .pfnReserved4 = */ NULL,
2330	/* .pfnReserved5 = */ NULL,
2331	/* .pfnReserved6 = */ NULL,
2332	/* .pfnReserved7 = */ NULL,
2333	#else
2334	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
2335	#endif
2336	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
2337	};
2338
2339	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2340

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88765

Download in other formats: