DevIommuIntel.cpp@ 88786

Last change on this file since 88786 was 88784, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Nits.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 113.4 KB

Line
1	/* $Id: DevIommuIntel.cpp 88784 2021-04-29 13:41:46Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock and is not expected to fail. */
67	#define DMAR_LOCK(a_pDevIns, a_pThisCC) \
68	do { \
69	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED); \
70	Assert(rcLock == VINF_SUCCESS); \
71	} while (0)
72
73	/** Release the DMAR lock. */
74	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
75
76	/** Asserts that the calling thread owns the DMAR lock. */
77	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
78	do { \
79	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
80	RT_NOREF1(a_pThisCC); \
81	} while (0)
82
83	/** The number of fault recording registers our implementation supports.
84	* Normal guest operation shouldn't trigger faults anyway, so we only support the
85	* minimum number of registers (which is 1).
86	*
87	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
88	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
89
90	/** Offset of first register in group 0. */
91	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
92	/** Offset of last register in group 0 (inclusive). */
93	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
94	/** Last valid offset in group 0 (exclusive). */
95	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
96	/** Size of the group 0 (in bytes). */
97	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
98	/*< Implementation-specific MMIO offset of IVA_REG. /
99	#define DMAR_MMIO_OFF_IVA_REG 0xe50
100	/*< Implementation-specific MMIO offset of IOTLB_REG. /
101	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
102	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
103	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
104	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
105	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
106	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
107
108	/** Offset of first register in group 1. */
109	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
110	/** Offset of last register in group 1 (inclusive). */
111	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
112	/** Last valid offset in group 1 (exclusive). */
113	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
114	/** Size of the group 1 (in bytes). */
115	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
116
117	/** DMAR implementation's major version number (exposed to software).
118	* We report 6 as the major version since we support queued-invalidations as
119	* software may make assumptions based on that.
120	*
121	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
122	#define DMAR_VER_MAJOR 6
123	/** DMAR implementation's minor version number (exposed to software). */
124	#define DMAR_VER_MINOR 0
125
126	/** Release log prefix string. */
127	#define DMAR_LOG_PFX "Intel-IOMMU"
128	/** The current saved state version. */
129	#define DMAR_SAVED_STATE_VERSION 1
130
131
132	/*********************************************************************************************************************************
133	* Structures and Typedefs *
134	*********************************************************************************************************************************/
135	/**
136	* DMAR error diagnostics.
137	* Sorted alphabetically so it's easier to add and locate items, no other reason.
138	*
139	* @note Members of this enum are used as array indices, so no gaps in enum
140	* values are not allowed. Update g_apszDmarDiagDesc when you modify
141	* fields in this enum.
142	*/
143	typedef enum
144	{
145	kDmarDiag_None = 0,
146	kDmarDiag_CcmdReg_NotSupported,
147	kDmarDiag_CcmdReg_Qi_Enabled,
148	kDmarDiag_CcmdReg_Ttm_Invalid,
149	kDmarDiag_IqaReg_Dsc_Fetch_Error,
150	kDmarDiag_IqaReg_Dw_Invalid,
151	kDmarDiag_Iqei_Dsc_Type_Invalid,
152	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
153	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
154	kDmarDiag_Iqei_Inv_Wait_Dsc_Ttm,
155	kDmarDiag_IqtReg_Qt_Invalid,
156	kDmarDiag_IqtReg_Qt_NotAligned,
157	/* Member for determining array index limit. */
158	kDmarDiag_End,
159	/* Type size hack. */
160	kDmarDiag_32Bit_Hack = 0x7fffffff
161	} DMARDIAG;
162	AssertCompileSize(DMARDIAG, 4);
163
164	/** DMAR diagnostic enum description expansion.
165	* The below construct ensures typos in the input to this macro are caught
166	* during compile time. */
167	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
168
169	/** DMAR diagnostics description for members in DMARDIAG. */
170	static const char *const g_apszDmarDiagDesc[] =
171	{
172	DMARDIAG_DESC(None ),
173	DMARDIAG_DESC(CcmdReg_NotSupported ),
174	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
175	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
176	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
177	DMARDIAG_DESC(IqaReg_Dw_Invalid ),
178	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
179	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
180	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
181	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Ttm ),
182	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
183	DMARDIAG_DESC(IqtReg_Qt_NotAligned )
184	/* kDmarDiag_End */
185	};
186	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
187	#undef DMARDIAG_DESC
188
189	/**
190	* The shared DMAR device state.
191	*/
192	typedef struct DMAR
193	{
194	/** IOMMU device index. */
195	uint32_t idxIommu;
196	/** DMAR magic. */
197	uint32_t u32Magic;
198
199	/** Registers (group 0). */
200	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
201	/** Registers (group 1). */
202	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
203
204	/** @name Lazily activated registers.
205	* These are the active values for lazily activated registers. Software is free to
206	* modify the actual register values while remapping/translation is enabled but they
207	* take effect only when explicitly signaled by software, hence we need to hold the
208	* active values separately.
209	* @{ */
210	/** Currently active IRTA_REG. */
211	uint64_t uIrtaReg;
212	/** Currently active RTADDR_REG. */
213	uint64_t uRtaReg;
214	/** @} */
215
216	/** @name Register copies for a tiny bit faster and more convenient access.
217	* @{ */
218	/** Copy of VER_REG. */
219	uint8_t uVerReg;
220	/** Alignment. */
221	uint8_t abPadding[7];
222	/** Copy of CAP_REG. */
223	uint64_t fCap;
224	/** Copy of ECAP_REG. */
225	uint64_t fExtCap;
226	/** @} */
227
228	/** The event semaphore the invalidation-queue thread waits on. */
229	SUPSEMEVENT hEvtInvQueue;
230	/** Whether the invalidation-queue thread has been signaled. */
231	bool volatile fInvQueueThreadSignaled;
232	/** Padding. */
233	bool afPadding0[3];
234	/** Error diagnostic. */
235	DMARDIAG enmDiag;
236	/** The MMIO handle. */
237	IOMMMIOHANDLE hMmio;
238
239	#ifdef VBOX_WITH_STATISTICS
240	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
241	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
242	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
243	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
244
245	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
246	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
247
248	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
249	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
250	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
251	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
252
253	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
254	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
255	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
256	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
257	#endif
258	} DMAR;
259	/** Pointer to the DMAR device state. */
260	typedef DMAR *PDMAR;
261	/** Pointer to the const DMAR device state. */
262	typedef DMAR const *PCDMAR;
263	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
264	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
265
266	/**
267	* The ring-3 DMAR device state.
268	*/
269	typedef struct DMARR3
270	{
271	/** Device instance. */
272	PPDMDEVINSR3 pDevInsR3;
273	/** The IOMMU helper. */
274	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
275	/** The invalidation-queue thread. */
276	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
277	} DMARR3;
278	/** Pointer to the ring-3 DMAR device state. */
279	typedef DMARR3 *PDMARR3;
280	/** Pointer to the const ring-3 DMAR device state. */
281	typedef DMARR3 const *PCDMARR3;
282
283	/**
284	* The ring-0 DMAR device state.
285	*/
286	typedef struct DMARR0
287	{
288	/** Device instance. */
289	PPDMDEVINSR0 pDevInsR0;
290	/** The IOMMU helper. */
291	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
292	} DMARR0;
293	/** Pointer to the ring-0 IOMMU device state. */
294	typedef DMARR0 *PDMARR0;
295	/** Pointer to the const ring-0 IOMMU device state. */
296	typedef DMARR0 const *PCDMARR0;
297
298	/**
299	* The raw-mode DMAR device state.
300	*/
301	typedef struct DMARRC
302	{
303	/** Device instance. */
304	PPDMDEVINSRC pDevInsRC;
305	/** The IOMMU helper. */
306	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
307	} DMARRC;
308	/** Pointer to the raw-mode DMAR device state. */
309	typedef DMARRC *PDMARRC;
310	/** Pointer to the const raw-mode DMAR device state. */
311	typedef DMARRC const *PCIDMARRC;
312
313	/** The DMAR device state for the current context. */
314	typedef CTX_SUFF(DMAR) DMARCC;
315	/** Pointer to the DMAR device state for the current context. */
316	typedef CTX_SUFF(PDMAR) PDMARCC;
317	/** Pointer to the const DMAR device state for the current context. */
318	typedef CTX_SUFF(PDMAR) const PCDMARCC;
319
320
321	/*********************************************************************************************************************************
322	* Global Variables *
323	*********************************************************************************************************************************/
324	/**
325	* Read-write masks for DMAR registers (group 0).
326	*/
327	static uint32_t const g_au32RwMasks0[] =
328	{
329	/* Offset Register Low High */
330	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
331	/* 0x004 Reserved */ 0,
332	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
333	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
334	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
335	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
336	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
337	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
338	/* 0x030 Reserved */ 0,
339	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
340	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
341	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
342	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
343	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
344	/* 0x048 Reserved */ 0, 0,
345	/* 0x050 Reserved */ 0, 0,
346	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
347	/* 0x060 Reserved */ 0,
348	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
349	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
350	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
351	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
352	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
353	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
354	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
355	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
356	/* 0x098 Reserved */ 0,
357	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
358	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
359	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
360	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
361	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
362	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
363	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
364	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
365	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
366	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
367	/* 0x0d8 Reserved */ 0,
368	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
369	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
370	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
371	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
372	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
373	/* 0x0f0 Reserved */ 0, 0,
374	/* 0x0f8 Reserved */ 0, 0,
375	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
376	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
377	/* 0x110 Reserved */ 0, 0,
378	/* 0x118 Reserved */ 0, 0,
379	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
380	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
381	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
382	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
383	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
384	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
385	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
386	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
387	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
388	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
389	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
390	/* 0x178 Reserved */ 0, 0,
391	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
392	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
393	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
394	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
395	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
396	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
397	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
398	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
399	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
400	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
401	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
402	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
403	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
404	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
405	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
406	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
407	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
408	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
409	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
410	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
411	};
412	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
413
414	/**
415	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
416	*/
417	static uint32_t const g_au32Rw1cMasks0[] =
418	{
419	/* Offset Register Low High */
420	/* 0x000 VER_REG */ 0,
421	/* 0x004 Reserved */ 0,
422	/* 0x008 CAP_REG */ 0, 0,
423	/* 0x010 ECAP_REG */ 0, 0,
424	/* 0x018 GCMD_REG */ 0,
425	/* 0x01c GSTS_REG */ 0,
426	/* 0x020 RTADDR_REG */ 0, 0,
427	/* 0x028 CCMD_REG */ 0, 0,
428	/* 0x030 Reserved */ 0,
429	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
430	/* 0x038 FECTL_REG */ 0,
431	/* 0x03c FEDATA_REG */ 0,
432	/* 0x040 FEADDR_REG */ 0,
433	/* 0x044 FEUADDR_REG */ 0,
434	/* 0x048 Reserved */ 0, 0,
435	/* 0x050 Reserved */ 0, 0,
436	/* 0x058 AFLOG_REG */ 0, 0,
437	/* 0x060 Reserved */ 0,
438	/* 0x064 PMEN_REG */ 0,
439	/* 0x068 PLMBASE_REG */ 0,
440	/* 0x06c PLMLIMIT_REG */ 0,
441	/* 0x070 PHMBASE_REG */ 0, 0,
442	/* 0x078 PHMLIMIT_REG */ 0, 0,
443	/* 0x080 IQH_REG */ 0, 0,
444	/* 0x088 IQT_REG */ 0, 0,
445	/* 0x090 IQA_REG */ 0, 0,
446	/* 0x098 Reserved */ 0,
447	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
448	/* 0x0a0 IECTL_REG */ 0,
449	/* 0x0a4 IEDATA_REG */ 0,
450	/* 0x0a8 IEADDR_REG */ 0,
451	/* 0x0ac IEUADDR_REG */ 0,
452	/* 0x0b0 IQERCD_REG */ 0, 0,
453	/* 0x0b8 IRTA_REG */ 0, 0,
454	/* 0x0c0 PQH_REG */ 0, 0,
455	/* 0x0c8 PQT_REG */ 0, 0,
456	/* 0x0d0 PQA_REG */ 0, 0,
457	/* 0x0d8 Reserved */ 0,
458	/* 0x0dc PRS_REG */ 0,
459	/* 0x0e0 PECTL_REG */ 0,
460	/* 0x0e4 PEDATA_REG */ 0,
461	/* 0x0e8 PEADDR_REG */ 0,
462	/* 0x0ec PEUADDR_REG */ 0,
463	/* 0x0f0 Reserved */ 0, 0,
464	/* 0x0f8 Reserved */ 0, 0,
465	/* 0x100 MTRRCAP_REG */ 0, 0,
466	/* 0x108 MTRRDEF_REG */ 0, 0,
467	/* 0x110 Reserved */ 0, 0,
468	/* 0x118 Reserved */ 0, 0,
469	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
470	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
471	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
472	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
473	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
474	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
475	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
476	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
477	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
478	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
479	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
480	/* 0x178 Reserved */ 0, 0,
481	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
482	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
483	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
484	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
485	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
486	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
487	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
488	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
489	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
490	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
491	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
492	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
493	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
494	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
495	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
496	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
497	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
498	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
499	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
500	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
501	};
502	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
503
504	/**
505	* Read-write masks for DMAR registers (group 1).
506	*/
507	static uint32_t const g_au32RwMasks1[] =
508	{
509	/* Offset Register Low High */
510	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
511	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
512	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
513	/* 0xe18 VCMDRSVD_REG */ 0, 0,
514	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
515	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
516	/* 0xe30 Reserved */ 0, 0,
517	/* 0xe38 Reserved */ 0, 0,
518	/* 0xe40 Reserved */ 0, 0,
519	/* 0xe48 Reserved */ 0, 0,
520	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
521	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
522	/* 0xe60 Reserved */ 0, 0,
523	/* 0xe68 Reserved */ 0, 0,
524	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
525	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
526	};
527	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
528	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
529
530	/**
531	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
532	*/
533	static uint32_t const g_au32Rw1cMasks1[] =
534	{
535	/* Offset Register Low High */
536	/* 0xe00 VCCAP_REG */ 0, 0,
537	/* 0xe08 VCMD_EO_REG */ 0, 0,
538	/* 0xe10 VCMD_REG */ 0, 0,
539	/* 0xe18 VCMDRSVD_REG */ 0, 0,
540	/* 0xe20 VCRSP_REG */ 0, 0,
541	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
542	/* 0xe30 Reserved */ 0, 0,
543	/* 0xe38 Reserved */ 0, 0,
544	/* 0xe40 Reserved */ 0, 0,
545	/* 0xe48 Reserved */ 0, 0,
546	/* 0xe50 IVA_REG */ 0, 0,
547	/* 0xe58 IOTLB_REG */ 0, 0,
548	/* 0xe60 Reserved */ 0, 0,
549	/* 0xe68 Reserved */ 0, 0,
550	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
551	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
552	};
553	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
554
555	/** Array of RW masks for each register group. */
556	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
557
558	/** Array of RW1C masks for each register group. */
559	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
560
561	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
562	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
563
564
565	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
566	/** @todo Add IOMMU struct size/alignment verification, see
567	* Devices/testcase/Makefile.kmk and
568	* Devices/testcase/tstDeviceStructSize[RC].cpp */
569
570	/**
571	* Returns the number of supported adjusted guest-address width (SAGAW) in bits
572	* given a CAP_REG.SAGAW value.
573	*
574	* @returns Number of SAGAW bits.
575	* @param uSagaw The CAP_REG.SAGAW value.
576	*/
577	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
578	{
579	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
580	return 30 + (uSagaw * 9);
581	return 0;
582	}
583
584
585	/**
586	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
587	* guest address width (MGAW).
588	*
589	* @returns The CAP_REG.SAGAW value.
590	* @param uMgaw The CAP_REG.MGAW value.
591	*/
592	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
593	{
594	switch (uMgaw + 1)
595	{
596	case 39: return 1;
597	case 48: return 2;
598	case 57: return 3;
599	}
600	return 0;
601	}
602
603
604	/**
605	* Returns table translation mode's descriptive name.
606	*
607	* @returns The descriptive name.
608	* @param uTtm The RTADDR_REG.TTM value.
609	*/
610	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
611	{
612	Assert(!(uTtm & 3));
613	static const char* s_apszTtmNames[] =
614	{
615	"Legacy Mode",
616	"Scalable Mode",
617	"Reserved",
618	"Abort-DMA Mode"
619	};
620	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
621	}
622
623
624	/**
625	* Gets the index of the group the register belongs to given its MMIO offset.
626	*
627	* @returns The group index.
628	* @param offReg The MMIO offset of the register.
629	* @param cbReg The size of the access being made (for bounds checking on
630	* debug builds).
631	*/
632	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
633	{
634	uint16_t const offLast = offReg + cbReg - 1;
635	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
636	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
637	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
638	}
639
640
641	/**
642	* Gets the group the register belongs to given its MMIO offset.
643	*
644	* @returns Pointer to the first element of the register group.
645	* @param pThis The shared DMAR device state.
646	* @param offReg The MMIO offset of the register.
647	* @param cbReg The size of the access being made (for bounds checking on
648	* debug builds).
649	* @param pIdxGroup Where to store the index of the register group the register
650	* belongs to.
651	*/
652	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
653	{
654	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
655	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
656	return apbRegs[*pIdxGroup];
657	}
658
659
660	/**
661	* Const/read-only version of dmarRegGetGroup.
662	*
663	* @copydoc dmarRegGetGroup
664	*/
665	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
666	{
667	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
668	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
669	return apbRegs[*pIdxGroup];
670	}
671
672
673	/**
674	* Writes a 32-bit register with the exactly the supplied value.
675	*
676	* @param pThis The shared DMAR device state.
677	* @param offReg The MMIO offset of the register.
678	* @param uReg The 32-bit value to write.
679	*/
680	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
681	{
682	uint8_t idxGroup;
683	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
684	NOREF(idxGroup);
685	(uint32_t )(pabRegs + offReg) = uReg;
686	}
687
688
689	/**
690	* Writes a 64-bit register with the exactly the supplied value.
691	*
692	* @param pThis The shared DMAR device state.
693	* @param offReg The MMIO offset of the register.
694	* @param uReg The 64-bit value to write.
695	*/
696	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
697	{
698	uint8_t idxGroup;
699	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
700	NOREF(idxGroup);
701	(uint64_t )(pabRegs + offReg) = uReg;
702	}
703
704
705	/**
706	* Reads a 32-bit register with exactly the value it contains.
707	*
708	* @returns The raw register value.
709	* @param pThis The shared DMAR device state.
710	* @param offReg The MMIO offset of the register.
711	*/
712	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
713	{
714	uint8_t idxGroup;
715	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
716	NOREF(idxGroup);
717	return (uint32_t )(pabRegs + offReg);
718	}
719
720
721	/**
722	* Reads a 64-bit register with exactly the value it contains.
723	*
724	* @returns The raw register value.
725	* @param pThis The shared DMAR device state.
726	* @param offReg The MMIO offset of the register.
727	*/
728	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
729	{
730	uint8_t idxGroup;
731	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
732	NOREF(idxGroup);
733	return (uint64_t )(pabRegs + offReg);
734	}
735
736
737	/**
738	* Reads a 32-bit register with exactly the value it contains along with their
739	* corresponding masks
740	*
741	* @param pThis The shared DMAR device state.
742	* @param offReg The MMIO offset of the register.
743	* @param puReg Where to store the raw 32-bit register value.
744	* @param pfRwMask Where to store the RW mask corresponding to this register.
745	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
746	*/
747	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
748	{
749	uint8_t idxGroup;
750	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
751	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
752	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
753	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
754	puReg = (uint32_t *)(pabRegs + offReg);
755	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
756	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
757	}
758
759
760	/**
761	* Reads a 64-bit register with exactly the value it contains along with their
762	* corresponding masks.
763	*
764	* @param pThis The shared DMAR device state.
765	* @param offReg The MMIO offset of the register.
766	* @param puReg Where to store the raw 64-bit register value.
767	* @param pfRwMask Where to store the RW mask corresponding to this register.
768	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
769	*/
770	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
771	{
772	uint8_t idxGroup;
773	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
774	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
775	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
776	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
777	puReg = (uint64_t *)(pabRegs + offReg);
778	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
779	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
780	}
781
782
783	/**
784	* Writes a 32-bit register as it would be when written by software.
785	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
786	*
787	* @returns The value that's actually written to the register.
788	* @param pThis The shared DMAR device state.
789	* @param offReg The MMIO offset of the register.
790	* @param uReg The 32-bit value to write.
791	*/
792	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
793	{
794	/* Read current value from the 32-bit register. */
795	uint32_t uCurReg;
796	uint32_t fRwMask;
797	uint32_t fRw1cMask;
798	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
799
800	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
801	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
802	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
803	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
804
805	/* Write new value to the 32-bit register. */
806	dmarRegWriteRaw32(pThis, offReg, uNewReg);
807	return uNewReg;
808	}
809
810
811	/**
812	* Writes a 64-bit register as it would be when written by software.
813	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
814	*
815	* @returns The value that's actually written to the register.
816	* @param pThis The shared DMAR device state.
817	* @param offReg The MMIO offset of the register.
818	* @param uReg The 64-bit value to write.
819	*/
820	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
821	{
822	/* Read current value from the 64-bit register. */
823	uint64_t uCurReg;
824	uint64_t fRwMask;
825	uint64_t fRw1cMask;
826	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
827
828	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
829	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
830	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
831	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
832
833	/* Write new value to the 64-bit register. */
834	dmarRegWriteRaw64(pThis, offReg, uNewReg);
835	return uNewReg;
836	}
837
838
839	/**
840	* Reads a 32-bit register as it would be when read by software.
841	*
842	* @returns The register value.
843	* @param pThis The shared DMAR device state.
844	* @param offReg The MMIO offset of the register.
845	*/
846	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
847	{
848	return dmarRegReadRaw32(pThis, offReg);
849	}
850
851
852	/**
853	* Reads a 64-bit register as it would be when read by software.
854	*
855	* @returns The register value.
856	* @param pThis The shared DMAR device state.
857	* @param offReg The MMIO offset of the register.
858	*/
859	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
860	{
861	return dmarRegReadRaw64(pThis, offReg);
862	}
863
864
865	/**
866	* Modifies a 32-bit register.
867	*
868	* @param pThis The shared DMAR device state.
869	* @param offReg The MMIO offset of the register.
870	* @param fAndMask The AND mask (applied first).
871	* @param fOrMask The OR mask.
872	* @remarks This does NOT apply RO or RW1C masks while modifying the
873	* register.
874	*/
875	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
876	{
877	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
878	uReg = (uReg & fAndMask) \| fOrMask;
879	dmarRegWriteRaw32(pThis, offReg, uReg);
880	}
881
882
883	/**
884	* Modifies a 64-bit register.
885	*
886	* @param pThis The shared DMAR device state.
887	* @param offReg The MMIO offset of the register.
888	* @param fAndMask The AND mask (applied first).
889	* @param fOrMask The OR mask.
890	* @remarks This does NOT apply RO or RW1C masks while modifying the
891	* register.
892	*/
893	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
894	{
895	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
896	uReg = (uReg & fAndMask) \| fOrMask;
897	dmarRegWriteRaw64(pThis, offReg, uReg);
898	}
899
900
901	/**
902	* Gets the table translation mode from the RTADDR_REG.
903	*
904	* @returns The table translation mode.
905	* @param pThis The shared DMAR device state.
906	*/
907	static uint8_t dmarRtAddrRegGetTtm(PCDMAR pThis)
908	{
909	uint64_t const uRtAddrReg = dmarRegRead64(pThis, VTD_MMIO_OFF_RTADDR_REG);
910	return RT_BF_GET(uRtAddrReg, VTD_BF_RTADDR_REG_TTM);
911	}
912
913
914	/**
915	* Checks if the invalidation-queue is empty.
916	*
917	* Extended version which optionally returns the current queue head and tail
918	* offsets.
919	*
920	* @returns @c true if empty, @c false otherwise.
921	* @param pThis The shared DMAR device state.
922	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
923	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
924	*/
925	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
926	{
927	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
928	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
929	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
930
931	/* Don't bother masking QT, QH since other bits are RsvdZ. */
932	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
933	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
934	if (poffQh)
935	*poffQh = uIqhReg;
936	if (poffQt)
937	*poffQt = uIqtReg;
938	return uIqtReg == uIqhReg;
939	}
940
941
942	/**
943	* Checks if the invalidation-queue is empty.
944	*
945	* @returns @c true if empty, @c false otherwise.
946	* @param pThis The shared DMAR device state.
947	*/
948	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
949	{
950	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
951	}
952
953
954	/**
955	* Checks if the invalidation-queue is capable of processing requests.
956	*
957	* @returns @c true if the invalidation-queue can process requests, @c false
958	* otherwise.
959	* @param pThis The shared DMAR device state.
960	*/
961	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
962	{
963	/* Check if queued-invalidation is enabled. */
964	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
965	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
966	{
967	/* Check if there are no invalidation-queue or timeout errors. */
968	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
969	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
970	return true;
971	}
972	return false;
973	}
974
975
976	/**
977	* Wakes up the invalidation-queue thread if there are requests to be processed.
978	*
979	* @param pDevIns The IOMMU device instance.
980	*/
981	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
982	{
983	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
984	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
985	Log4Func(("\n"));
986
987	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
988
989	if ( dmarInvQueueCanProcessRequests(pThis)
990	&& !dmarInvQueueIsEmpty(pThis)
991	&& !ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, true))
992	{
993	Log4Func(("Signaling the invalidation-queue thread\n"));
994	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
995	}
996	}
997
998
999	/**
1000	* Raises an interrupt in response to a fault event.
1001	*
1002	* @param pDevIns The IOMMU device instance.
1003	*/
1004	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1005	{
1006	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1007	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1008	#ifdef RT_STRICT
1009	{
1010	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1011	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1012	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1013	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1014	\| VTD_BF_FSTS_REG_IQE_MASK;
1015	Assert(uFstsReg & fFaultMask);
1016	}
1017	#endif
1018
1019	uint32_t uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
1020	if (!(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1021	{
1022	/* Software has unmasked the interrupt, raise it. */
1023	MSIMSG Msi;
1024	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
1025	Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
1026	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
1027
1028	/** @todo Assert Msi.Addr is in the MSR_IA32_APICBASE_ADDR range and ensure on
1029	* FEADD_REG write it can't be anything else. */
1030	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1031
1032	/* Clear interrupt pending bit. */
1033	uFectlReg &= ~VTD_BF_FECTL_REG_IP_MASK;
1034	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1035	}
1036	else
1037	{
1038	/* Interrupt is masked, set the interrupt pending bit. */
1039	uFectlReg \|= VTD_BF_FECTL_REG_IP_MASK;
1040	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1041	}
1042	}
1043
1044
1045	#ifdef IN_RING3
1046	/**
1047	* Raises an interrupt in response to an invalidation (complete) event.
1048	*
1049	* @param pDevIns The IOMMU device instance.
1050	*/
1051	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1052	{
1053	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1054	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1055
1056	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1057	if (uIcsReg & VTD_BF_ICS_REG_IWC_MASK)
1058	return;
1059
1060	uint32_t uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
1061	if (!(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1062	{
1063	/* Software has unmasked the interrupt, raise it. */
1064	MSIMSG Msi;
1065	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
1066	Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
1067	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
1068
1069	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1070
1071	/* Clear interrupt pending bit. */
1072	uIectlReg &= ~VTD_BF_IECTL_REG_IP_MASK;
1073	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
1074	}
1075	else
1076	{
1077	/* Interrupt is masked, set the interrupt pending bit. */
1078	uIectlReg \|= VTD_BF_IECTL_REG_IP_MASK;
1079	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
1080	}
1081	}
1082	#endif /* IN_RING3 */
1083
1084
1085	#if 0
1086	/**
1087	* Checks if a primary fault can be recorded.
1088	*
1089	* @returns @c true if the fault can be recorded, @c false otherwise.
1090	* @param pDevIns The IOMMU device instance.
1091	* @param pThis The shared DMAR device state.
1092	*/
1093	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1094	{
1095	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1096	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1097
1098	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1099	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1100	return false;
1101
1102	/*
1103	* If we add more FRCD registers, we'll have to loop through them here.
1104	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1105	* nor do we need to increment FRI.
1106	*
1107	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1108	*/
1109	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1110	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1111	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1112	{
1113	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1114	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1115	return false;
1116	}
1117
1118	uFstsReg \|= VTD_BF_FSTS_REG_PPF_MASK;
1119	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1120	return true;
1121	}
1122	#endif
1123
1124
1125	/**
1126	* Records an IQE fault.
1127	*
1128	* @param pDevIns The IOMMU device instance.
1129	* @param enmIqei The IQE information.
1130	* @param enmDiag The diagnostic reason.
1131	*/
1132	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IQEI_T enmIqei)
1133	{
1134	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1135	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1136	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1137
1138	/* Update the diagnostic reason. */
1139	pThis->enmDiag = enmDiag;
1140
1141	/* Set the error bit. */
1142	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1143	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1144
1145	/* Set the error information. */
1146	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1147	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1148
1149	dmarFaultEventRaiseInterrupt(pDevIns);
1150	}
1151
1152
1153	/**
1154	* Handles writes to GCMD_REG.
1155	*
1156	* @returns Strict VBox status code.
1157	* @param pDevIns The IOMMU device instance.
1158	* @param uGcmdReg The value written to GCMD_REG.
1159	*/
1160	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1161	{
1162	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1163	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1164	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1165	uint64_t const fExtCap = pThis->fExtCap;
1166
1167	/*
1168	* Queued-invalidation.
1169	*/
1170	if ( (fExtCap & VTD_BF_ECAP_REG_QI_MASK)
1171	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1172	{
1173	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1174	{
1175	/* Enable the invalidation-queue. */
1176	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX /* fAndMask /, VTD_BF_GSTS_REG_QIES_MASK / fOrMask */);
1177	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1178	}
1179	else
1180	{
1181	/* Disable the invalidation-queue. */
1182	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK /* fAndMask /, 0 / fOrMask */);
1183	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1184	}
1185	}
1186
1187	/*
1188	* Set interrupt remapping table pointer.
1189	*/
1190	if ( (fExtCap & VTD_BF_ECAP_REG_IR_MASK)
1191	&& (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK))
1192	{
1193	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1194	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX /* fAndMask /, VTD_BF_GSTS_REG_IRTPS_MASK / fOrMask */);
1195	}
1196
1197	/** @todo Rest of the bits. */
1198
1199	return VINF_SUCCESS;
1200	}
1201
1202
1203	/**
1204	* Handles writes to CCMD_REG.
1205	*
1206	* @returns Strict VBox status code.
1207	* @param pDevIns The IOMMU device instance.
1208	* @param offReg The MMIO register offset.
1209	* @param cbReg The size of the MMIO access (in bytes).
1210	* @param uCcmdReg The value written to CCMD_REG.
1211	*/
1212	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1213	{
1214	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1215	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1216	{
1217	/* Check if we need to invalidate the context-context. */
1218	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1219	if (fIcc)
1220	{
1221	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1222	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1223	if (uMajorVersion < 6)
1224	{
1225	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1226	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1227	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1228	{
1229	/* Verify table translation mode is legacy. */
1230	uint8_t const fTtm = dmarRtAddrRegGetTtm(pThis);
1231	if (fTtm == VTD_TTM_LEGACY_MODE)
1232	{
1233	/** @todo Invalidate. */
1234	return VINF_SUCCESS;
1235	}
1236	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1237	}
1238	else
1239	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1240	}
1241	else
1242	pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1243	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK /* fAndMask /, 0 / fOrMask */);
1244	}
1245	}
1246	return VINF_SUCCESS;
1247	}
1248
1249
1250	/**
1251	* Handles writes to IQT_REG.
1252	*
1253	* @returns Strict VBox status code.
1254	* @param pDevIns The IOMMU device instance.
1255	* @param offReg The MMIO register offset.
1256	* @param uIqtReg The value written to IQT_REG.
1257	*/
1258	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1259	{
1260	/* We only care about the low 32-bits, high 32-bits are reserved. */
1261	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1262	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1263
1264	/* Paranoia. */
1265	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1266
1267	uint32_t const offQt = uIqtReg;
1268	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1269	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1270
1271	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1272	if ( fDw != VTD_IQA_REG_DW_256_BIT
1273	\|\| !(offQt & RT_BIT(4)))
1274	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1275	else
1276	{
1277	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1278	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4) /* fAndMask/ , 0 / fOrMask */);
1279	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, kIqei_QueueTailNotAligned);
1280	}
1281	return VINF_SUCCESS;
1282	}
1283
1284
1285	/**
1286	* Handles writes to IQA_REG.
1287	*
1288	* @returns Strict VBox status code.
1289	* @param pDevIns The IOMMU device instance.
1290	* @param offReg The MMIO register offset.
1291	* @param uIqaReg The value written to IQA_REG.
1292	*/
1293	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1294	{
1295	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1296	Assert(offReg == VTD_MMIO_OFF_IQA_REG);
1297
1298	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1299	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1300	* cannot happen or that it's ignored when it does happen. */
1301
1302	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1303	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1304	if (fDw == VTD_IQA_REG_DW_256_BIT)
1305	{
1306	bool const fSupports256BitDw = (pThis->fExtCap & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1307	if (fSupports256BitDw)
1308	{ /* likely */ }
1309	else
1310	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_Invalid, kIqei_InvalidDescriptorWidth);
1311	}
1312	return VINF_SUCCESS;
1313	}
1314
1315
1316	/**
1317	* Memory access bulk (one or more 4K pages) request from a device.
1318	*
1319	* @returns VBox status code.
1320	* @param pDevIns The IOMMU device instance.
1321	* @param idDevice The device ID (bus, device, function).
1322	* @param cIovas The number of addresses being accessed.
1323	* @param pauIovas The I/O virtual addresses for each page being accessed.
1324	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1325	* @param paGCPhysSpa Where to store the translated physical addresses.
1326	*
1327	* @thread Any.
1328	*/
1329	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1330	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1331	{
1332	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1333	return VERR_NOT_IMPLEMENTED;
1334	}
1335
1336
1337	/**
1338	* Memory access transaction from a device.
1339	*
1340	* @returns VBox status code.
1341	* @param pDevIns The IOMMU device instance.
1342	* @param idDevice The device ID (bus, device, function).
1343	* @param uIova The I/O virtual address being accessed.
1344	* @param cbIova The size of the access.
1345	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1346	* @param pGCPhysSpa Where to store the translated system physical address.
1347	* @param pcbContiguous Where to store the number of contiguous bytes translated
1348	* and permission-checked.
1349	*
1350	* @thread Any.
1351	*/
1352	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1353	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
1354	{
1355	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
1356	return VERR_NOT_IMPLEMENTED;
1357	}
1358
1359
1360	/**
1361	* Interrupt remap request from a device.
1362	*
1363	* @returns VBox status code.
1364	* @param pDevIns The IOMMU device instance.
1365	* @param idDevice The device ID (bus, device, function).
1366	* @param pMsiIn The source MSI.
1367	* @param pMsiOut Where to store the remapped MSI.
1368	*/
1369	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1370	{
1371	RT_NOREF3(idDevice, pMsiIn, pMsiOut);
1372	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1373	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap)); NOREF(pThis);
1374
1375	return VERR_NOT_IMPLEMENTED;
1376	}
1377
1378
1379	/**
1380	* @callback_method_impl{FNIOMMMIONEWWRITE}
1381	*/
1382	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1383	{
1384	RT_NOREF1(pvUser);
1385	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1386
1387	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1388	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1389
1390	uint16_t const offReg = off;
1391	uint16_t const offLast = offReg + cb - 1;
1392	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1393	{
1394	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1395	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
1396
1397	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv)
1398	: dmarRegWrite32(pThis, offReg, (uint32_t )pv);
1399	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1400	switch (off)
1401	{
1402	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
1403	{
1404	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
1405	break;
1406	}
1407
1408	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
1409	case VTD_MMIO_OFF_CCMD_REG + 4:
1410	{
1411	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
1412	break;
1413	}
1414
1415	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
1416	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
1417	{
1418	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
1419	break;
1420	}
1421
1422	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
1423	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
1424	{
1425	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
1426	break;
1427	}
1428	}
1429
1430	DMAR_UNLOCK(pDevIns, pThisCC);
1431	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
1432	return rcStrict;
1433	}
1434
1435	return VINF_IOM_MMIO_UNUSED_FF;
1436	}
1437
1438
1439	/**
1440	* @callback_method_impl{FNIOMMMIONEWREAD}
1441	*/
1442	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1443	{
1444	RT_NOREF1(pvUser);
1445	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1446
1447	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1448	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1449
1450	uint16_t const offReg = off;
1451	uint16_t const offLast = offReg + cb - 1;
1452	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1453	{
1454	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1455	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
1456
1457	if (cb == 8)
1458	{
1459	(uint64_t )pv = dmarRegRead64(pThis, offReg);
1460	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
1461	}
1462	else
1463	{
1464	(uint32_t )pv = dmarRegRead32(pThis, offReg);
1465	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
1466	}
1467
1468	DMAR_UNLOCK(pDevIns, pThisCC);
1469	return VINF_SUCCESS;
1470	}
1471
1472	return VINF_IOM_MMIO_UNUSED_FF;
1473	}
1474
1475
1476	#ifdef IN_RING3
1477	/**
1478	* Process requests in the invalidation queue.
1479	*
1480	* @param pDevIns The IOMMU device instance.
1481	* @param pvRequests The requests data.
1482	* @param cbRequests The size of all requests (in bytes).
1483	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
1484	* VTD_IQA_REG_DW_256_BIT).
1485	*/
1486	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw)
1487	{
1488	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1489	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1490	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisR3);
1491
1492	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
1493	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
1494	{
1495	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
1496	uint64_t const uQword0 = puDscQwords[0];
1497	uint64_t const uQword1 = puDscQwords[1];
1498	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
1499	uint8_t const fTtm = dmarRtAddrRegGetTtm(pThis);
1500	Assert(fTtm != VTD_TTM_RSVD); /* Should be guaranteed when software updates GCMD_REG.SRTP. */
1501
1502	switch (fDscType)
1503	{
1504	case VTD_CC_INV_DSC_TYPE: LogRelMax(32, ("%s: CC\n", DMAR_LOG_PFX)); break;
1505	case VTD_IOTLB_INV_DSC_TYPE: LogRelMax(32, ("%s: IOTLB\n", DMAR_LOG_PFX)); break;
1506	case VTD_DEV_TLB_INV_DSC_TYPE: LogRelMax(32, ("%s: DEV_TLB\n", DMAR_LOG_PFX)); break;
1507	case VTD_IEC_INV_DSC_TYPE: LogRelMax(32, ("%s: IEC_INV\n", DMAR_LOG_PFX)); break;
1508
1509	case VTD_INV_WAIT_DSC_TYPE:
1510	{
1511	/* Validate translation modes valid for this descriptor. */
1512	if ( fTtm == VTD_TTM_LEGACY_MODE
1513	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
1514	{ /* likely */ }
1515	else
1516	{
1517	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Inv_Wait_Dsc_Ttm, kIqei_InvalidDescriptorType);
1518	return;
1519	}
1520
1521	/* Validate reserved bits. */
1522	uint64_t const fValidMask0 = !(pThis->fExtCap & VTD_BF_ECAP_REG_PDS_MASK)
1523	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
1524	: VTD_INV_WAIT_DSC_0_VALID_MASK;
1525	if ( !(uQword0 & ~fValidMask0)
1526	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
1527	{ /* likely */ }
1528	else
1529	{
1530	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, kIqei_RsvdFieldViolation);
1531	return;
1532	}
1533	if (fDw == VTD_IQA_REG_DW_256_BIT)
1534	{
1535	uint64_t const uQword2 = puDscQwords[2];
1536	uint64_t const uQword3 = puDscQwords[3];
1537	if ( !uQword2
1538	&& !uQword3)
1539	{ /* likely */ }
1540	else
1541	{
1542	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, kIqei_RsvdFieldViolation);
1543	return;
1544	}
1545	}
1546
1547	/* Perform status write (this must be done prior to generating the completion interrupt). */
1548	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
1549	if (fSw)
1550	{
1551	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
1552	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
1553	DMAR_UNLOCK(pDevIns, pThisR3);
1554	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
1555	DMAR_LOCK(pDevIns, pThisR3);
1556	AssertRC(rc);
1557	}
1558
1559	/* Generate invalidation event interrupt. */
1560	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
1561	if (fIf)
1562	dmarR3InvEventRaiseInterrupt(pDevIns);
1563	break;
1564	}
1565
1566	case VTD_P_IOTLB_INV_DSC_TYPE: LogRelMax(32, ("%s: P_IOTLB\n", DMAR_LOG_PFX)); break;
1567	case VTD_PC_INV_DSC_TYPE: LogRelMax(32, ("%s: PC_INV\n", DMAR_LOG_PFX)); break;
1568	case VTD_P_DEV_TLB_INV_DSC_TYPE: LogRelMax(32, ("%s: P_DEVL_TLB\n", DMAR_LOG_PFX)); break;
1569	{
1570	break;
1571	}
1572
1573	default:
1574	{
1575	/* Stop processing further requests. */
1576	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
1577	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Dsc_Type_Invalid, kIqei_InvalidDescriptorType);
1578	return;
1579	}
1580	}
1581	}
1582	}
1583
1584
1585
1586	/**
1587	* The invalidation-queue thread.
1588	*
1589	* @returns VBox status code.
1590	* @param pDevIns The IOMMU device instance.
1591	* @param pThread The command thread.
1592	*/
1593	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1594	{
1595	NOREF(pThread);
1596	LogFlowFunc(("\n"));
1597
1598	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
1599	return VINF_SUCCESS;
1600
1601	/*
1602	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
1603	* This prevents trashing the heap as well as deal with out-of-memory situations
1604	* up-front while starting the VM. It also simplifies the code from having to
1605	* dynamically grow/shrink the allocation based on how software sizes the queue.
1606	* Guests normally don't alter the queue size all the time, but that's not an
1607	* assumption we can make.
1608	*/
1609	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
1610	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
1611	void *pvRequests = RTMemAllocZ(cbMaxQs);
1612	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
1613
1614	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
1615	{
1616	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1617	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1618
1619	/*
1620	* Sleep until we are woken up.
1621	*/
1622	bool const fSignaled = ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, false);
1623	if (!fSignaled)
1624	{
1625	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
1626	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
1627	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
1628	break;
1629	ASMAtomicWriteBool(&pThis->fInvQueueThreadSignaled, false);
1630	}
1631
1632	DMAR_LOCK(pDevIns, pThisR3);
1633	if (dmarInvQueueCanProcessRequests(pThis))
1634	{
1635	uint32_t offQueueHead;
1636	uint32_t offQueueTail;
1637	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
1638	if (!fIsEmpty)
1639	{
1640	/** @todo Handle RTADDR_REG MMIO write first, for handling kIqei_InvalidTtm. I
1641	* don't think it needs to be checked/handled here? */
1642
1643	/*
1644	* Get the current queue size.
1645	*/
1646	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1647	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
1648	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
1649	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1650
1651	/* Paranoia. */
1652	Assert(cbQueue <= cbMaxQs);
1653	Assert(!(offQueueTail & ~VTD_IQT_REG_RW_MASK));
1654	Assert(!(offQueueHead & ~VTD_IQH_REG_RW_MASK));
1655	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
1656	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
1657	Assert(offQueueHead < cbQueue);
1658
1659	/*
1660	* Read the requests in the queue from guest memory into our buffer.
1661	*/
1662	if (offQueueTail < cbQueue)
1663	{
1664	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
1665
1666	/* Don't hold the lock while reading (potentially large amount of) requests. */
1667	DMAR_UNLOCK(pDevIns, pThisR3);
1668
1669	int rc;
1670	uint32_t cbRequests;
1671	if (offQueueTail > offQueueHead)
1672	{
1673	/* The requests have not wrapped around, read them in one go. */
1674	cbRequests = offQueueTail - offQueueHead;
1675	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbRequests);
1676	}
1677	else
1678	{
1679	/* The requests have wrapped around, read forward and wrapped-around. */
1680	uint32_t const cbForward = cbQueue - offQueueHead;
1681	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbForward);
1682
1683	uint32_t const cbWrapped = offQueueTail;
1684	if ( RT_SUCCESS(rc)
1685	&& cbWrapped > 0)
1686	{
1687	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests + cbForward,
1688	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
1689	}
1690	cbRequests = cbForward + cbWrapped;
1691	}
1692
1693	/* Re-acquire the lock since we need to update device state. */
1694	DMAR_LOCK(pDevIns, pThisR3);
1695
1696	if (RT_SUCCESS(rc))
1697	{
1698	/* Indicate to software we've fetched all requests. */
1699	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
1700
1701	/* Process all requests (in FIFO order). */
1702	Assert(cbRequests <= cbQueue);
1703	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw);
1704	}
1705	else
1706	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, kIqei_FetchDescriptorError);
1707	}
1708	else
1709	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, kIqei_InvalidTailPointer);
1710	}
1711	}
1712	DMAR_UNLOCK(pDevIns, pThisR3);
1713	}
1714
1715	RTMemFree(pvRequests);
1716	pvRequests = NULL;
1717
1718	LogFlowFunc(("Invalidation-queue thread terminating\n"));
1719	return VINF_SUCCESS;
1720	}
1721
1722
1723	/**
1724	* Wakes up the invalidation-queue thread so it can respond to a state
1725	* change.
1726	*
1727	* @returns VBox status code.
1728	* @param pDevIns The IOMMU device instance.
1729	* @param pThread The invalidation-queue thread.
1730	*
1731	* @thread EMT.
1732	*/
1733	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1734	{
1735	RT_NOREF(pThread);
1736	LogFlowFunc(("\n"));
1737	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1738	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1739	}
1740
1741
1742	/**
1743	* @callback_method_impl{FNDBGFHANDLERDEV}
1744	*/
1745	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
1746	{
1747	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1748	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1749	PCPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1750	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
1751
1752	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
1753
1754	/*
1755	* We lock the device to get a consistent register state, but it is
1756	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers into
1757	* temporaries and release the lock ASAP.
1758	*
1759	* Order of register being read and outputted is in accordance with the
1760	* spec. for no particular reason.
1761	* See Intel VT-d spec. 10.4 "Register Descriptions".
1762	*/
1763	DMAR_LOCK(pDevIns, pThisR3);
1764
1765	DMARDIAG const enmDiag = pThis->enmDiag;
1766	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
1767	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
1768	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
1769	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
1770	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1771	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1772	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
1773	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1774	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
1775	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
1776	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
1777	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
1778	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
1779	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
1780	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
1781	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
1782	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
1783	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
1784	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
1785	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
1786	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1787	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1788	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
1789	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
1790	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
1791	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
1792	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
1793	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1794	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
1795	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
1796	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
1797	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
1798	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
1799	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
1800	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
1801	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
1802	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
1803	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
1804	/** @todo Do other registers as required, we don't implement them for now. */
1805
1806	DMAR_UNLOCK(pDevIns, pThisR3);
1807
1808	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
1809	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
1810	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
1811	if (!fVerbose)
1812	{
1813	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
1814	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
1815	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
1816	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
1817	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
1818	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
1819	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
1820	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
1821	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
1822	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
1823	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
1824	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
1825	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
1826	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
1827	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
1828	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
1829	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
1830	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
1831	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
1832	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
1833	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
1834	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
1835	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
1836	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
1837	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
1838	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
1839	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
1840	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
1841	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
1842	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
1843	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
1844	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
1845	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
1846	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
1847	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
1848	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
1849	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
1850	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
1851	pHlp->pfnPrintf(pHlp, "\n");
1852	}
1853	else
1854	{
1855	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
1856	{
1857	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
1858	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
1859	}
1860	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
1861	{
1862	uint8_t const uSagaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW);
1863	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
1864	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
1865	pHlp->pfnPrintf(pHlp, " ND = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
1866	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
1867	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
1868	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
1869	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
1870	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
1871	pHlp->pfnPrintf(pHlp, " SAGAW = %#x (%u bits)\n", uSagaw, vtdCapRegGetSagawBits(uSagaw));
1872	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
1873	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
1874	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
1875	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
1876	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
1877	pHlp->pfnPrintf(pHlp, " NFR = %#x (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
1878	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
1879	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
1880	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
1881	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
1882	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
1883	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
1884	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
1885	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
1886	}
1887	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
1888	{
1889	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
1890	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
1891	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
1892	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
1893	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
1894	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
1895	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
1896	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
1897	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
1898	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
1899	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
1900	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
1901	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
1902	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
1903	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
1904	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
1905	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
1906	pHlp->pfnPrintf(pHlp, " PSS = %#x (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
1907	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
1908	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
1909	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
1910	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
1911	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
1912	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
1913	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
1914	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
1915	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
1916	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
1917	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
1918	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
1919	}
1920	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
1921	{
1922	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
1923	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Bypass interrupt remapping"
1924	: "Block compatible format interrupts");
1925	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
1926	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
1927	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
1928	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
1929	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
1930	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
1931	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
1932	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
1933	}
1934	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
1935	{
1936	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
1937	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Bypass interrupt remapping"
1938	: "Block compatible format interrupts");
1939	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
1940	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
1941	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
1942	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
1943	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
1944	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
1945	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
1946	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
1947	}
1948	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
1949	{
1950	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1951	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
1952	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_RTA));
1953	}
1954	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
1955	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
1956	{
1957	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
1958	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
1959	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
1960	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
1961	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
1962	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
1963	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
1964	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
1965	}
1966
1967	/** @todo Verbose others as needed during debugging/rainy day. */
1968	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
1969	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
1970	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
1971	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
1972	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
1973	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
1974	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
1975	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
1976	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
1977	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
1978	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
1979	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
1980	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
1981	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
1982	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
1983	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
1984	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
1985	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
1986	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
1987	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
1988	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
1989	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
1990	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
1991	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
1992	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
1993	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
1994	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
1995	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
1996	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
1997	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
1998	pHlp->pfnPrintf(pHlp, "\n");
1999	}
2000	}
2001
2002
2003	/**
2004	* Initializes all registers in the DMAR unit.
2005	*
2006	* @param pDevIns The IOMMU device instance.
2007	*/
2008	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
2009	{
2010	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2011
2012	/*
2013	* Wipe all registers (required on reset).
2014	*/
2015	RT_ZERO(pThis->abRegs0);
2016	RT_ZERO(pThis->abRegs1);
2017
2018	/*
2019	* Initialize registers not mutable by software prior to initializing other registers.
2020	*/
2021	/* VER_REG */
2022	{
2023	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
2024	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
2025	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
2026	}
2027
2028	uint8_t const fFlts = 1; /* First-Level translation support. */
2029	uint8_t const fSlts = 1; /* Second-Level translation support. */
2030	uint8_t const fPt = 1; /* Pass-Through support. */
2031	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
2032	uint8_t const fNest = 0; /* Nested translation support. */
2033
2034	/* CAP_REG */
2035	{
2036	uint8_t cGstPhysAddrBits;
2037	uint8_t cGstLinearAddrBits;
2038	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
2039
2040	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
2041	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
2042	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
2043	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
2044	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
2045	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
2046	uint8_t const fMamv = (fSl2gp ? /* Maximum address mask value (for second-level invalidations). */
2047	X86_PAGE_1G_SHIFT : X86_PAGE_2M_SHIFT) - X86_PAGE_4K_SHIFT;
2048	uint8_t const fNd = 2; /* Number of domains (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
2049	7=Reserved). */
2050	uint8_t const fPsi = 1; /* Page selective invalidation. */
2051	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
2052	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
2053	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
2054
2055	pThis->fCap = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
2056	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
2057	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
2058	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
2059	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
2060	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
2061	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
2062	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
2063	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
2064	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
2065	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
2066	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
2067	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
2068	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
2069	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
2070	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
2071	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
2072	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
2073	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
2074	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, 0) /* If we invalidate interrupt cache on SIRTP flow. */
2075	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, 0); /* If we invalidate translation cache on SRTP flow. */
2076	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCap);
2077	}
2078
2079	/* ECAP_REG */
2080	{
2081	uint8_t const fQi = 1; /* Queued-invalidations. */
2082	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
2083	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
2084	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
2085	uint8_t const fSrs = 1; /* Supervisor request support. */
2086	uint8_t const fEim = 1; /* Extended interrupt mode.*/
2087	uint8_t const fAdms = 1; /* Abort DMA mode support. */
2088
2089	pThis->fExtCap = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
2090	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
2091	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
2092	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
2093	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
2094	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
2095	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
2096	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
2097	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
2098	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
2099	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
2100	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
2101	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
2102	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
2103	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
2104	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
2105	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
2106	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
2107	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
2108	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
2109	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
2110	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
2111	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
2112	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
2113	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
2114	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
2115	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
2116	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
2117	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
2118	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCap);
2119	}
2120
2121	/*
2122	* Initialize registers mutable by software.
2123	*/
2124	/* FECTL_REG */
2125	{
2126	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
2127	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
2128	}
2129
2130	/* ICETL_REG */
2131	{
2132	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
2133	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
2134	}
2135
2136	#ifdef VBOX_STRICT
2137	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
2138	Assert(!RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
2139	#endif
2140	}
2141
2142
2143	/**
2144	* @interface_method_impl{PDMDEVREG,pfnReset}
2145	*/
2146	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
2147	{
2148	RT_NOREF1(pDevIns);
2149	LogFlowFunc(("\n"));
2150
2151	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2152	DMAR_LOCK(pDevIns, pThisR3);
2153
2154	dmarR3RegsInit(pDevIns);
2155
2156	DMAR_UNLOCK(pDevIns, pThisR3);
2157	}
2158
2159
2160	/**
2161	* @interface_method_impl{PDMDEVREG,pfnDestruct}
2162	*/
2163	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
2164	{
2165	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2166	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2167	LogFlowFunc(("\n"));
2168
2169	DMAR_LOCK(pDevIns, pThisR3);
2170
2171	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
2172	{
2173	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
2174	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
2175	}
2176
2177	DMAR_UNLOCK(pDevIns, pThisR3);
2178	return VINF_SUCCESS;
2179	}
2180
2181
2182	/**
2183	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2184	*/
2185	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2186	{
2187	RT_NOREF(pCfg);
2188
2189	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2190	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
2191	pThisR3->pDevInsR3 = pDevIns;
2192
2193	LogFlowFunc(("iInstance=%d\n", iInstance));
2194	NOREF(iInstance);
2195
2196	/*
2197	* Register the IOMMU with PDM.
2198	*/
2199	PDMIOMMUREGR3 IommuReg;
2200	RT_ZERO(IommuReg);
2201	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2202	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2203	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2204	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2205	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2206	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
2207	if (RT_FAILURE(rc))
2208	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
2209	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
2210	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2211	N_("IOMMU helper version mismatch; got %#x expected %#x"),
2212	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
2213	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
2214	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2215	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
2216	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
2217	/*
2218	* Use PDM's critical section (via helpers) for the IOMMU device.
2219	*/
2220	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2221	AssertRCReturn(rc, rc);
2222
2223	/*
2224	* Initialize PCI configuration registers.
2225	*/
2226	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2227	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2228
2229	/* Header. */
2230	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2231	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2232	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
2233	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
2234	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
2235	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
2236	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2237	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2238
2239	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
2240	PDMPciDevSetStatus(pPciDev, 0);
2241	PDMPciDevSetCapabilityList(pPciDev, 0);
2242
2243	/** @todo VTBAR at 0x180? */
2244
2245	/*
2246	* Register the PCI function with PDM.
2247	*/
2248	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
2249	AssertLogRelRCReturn(rc, rc);
2250
2251	/** @todo Register MSI but what's the MSI capability offset? */
2252	#if 0
2253	/*
2254	* Register MSI support for the PCI device.
2255	* This must be done -after- registering it as a PCI device!
2256	*/
2257	#endif
2258
2259	/*
2260	* Register MMIO region.
2261	*/
2262	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
2263	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
2264	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
2265	&pThis->hMmio);
2266	AssertLogRelRCReturn(rc, rc);
2267
2268	/*
2269	* Register debugger info items.
2270	*/
2271	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
2272	AssertLogRelRCReturn(rc, rc);
2273
2274	#ifdef VBOX_WITH_STATISTICS
2275	/*
2276	* Statistics.
2277	*/
2278	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
2279	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
2280
2281	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
2282	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
2283
2284	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
2285	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
2286
2287	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
2288	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
2289
2290	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
2291	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
2292
2293	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
2294	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
2295
2296	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
2297	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
2298	#endif
2299
2300	/*
2301	* Initialize registers.
2302	*/
2303	dmarR3RegsInit(pDevIns);
2304
2305	/*
2306	* Create invalidation-queue thread and semaphore.
2307	*/
2308	char szInvQueueThread[32];
2309	RT_ZERO(szInvQueueThread);
2310	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
2311	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
2312	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
2313	AssertLogRelRCReturn(rc, rc);
2314
2315	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
2316	AssertLogRelRCReturn(rc, rc);
2317
2318	/*
2319	* Log some of the features exposed to software.
2320	*/
2321	uint32_t const uVerReg = pThis->uVerReg;
2322	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_MGAW) + 1;
2323	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_SAGAW));
2324	uint16_t const offFrcd = RT_BF_GET(pThis->fCap, VTD_BF_CAP_REG_FRO);
2325	uint16_t const offIva = RT_BF_GET(pThis->fExtCap, VTD_BF_ECAP_REG_IRO);
2326	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
2327	DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
2328	pThis->fCap, pThis->fExtCap, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
2329
2330	return VINF_SUCCESS;
2331	}
2332
2333	#else
2334
2335	/**
2336	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
2337	*/
2338	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
2339	{
2340	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2341	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2342	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
2343	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
2344
2345	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
2346	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2347	AssertRCReturn(rc, rc);
2348
2349	/* Set up the MMIO RZ handlers. */
2350	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
2351	AssertRCReturn(rc, rc);
2352
2353	/* Set up the IOMMU RZ callbacks. */
2354	PDMIOMMUREGCC IommuReg;
2355	RT_ZERO(IommuReg);
2356	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2357	IommuReg.idxIommu = pThis->idxIommu;
2358	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2359	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2360	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2361	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2362
2363	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
2364	AssertRCReturn(rc, rc);
2365	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
2366	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2367	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2368	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
2369	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
2370	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
2371	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
2372
2373	return VINF_SUCCESS;
2374	}
2375
2376	#endif
2377
2378
2379	/**
2380	* The device registration structure.
2381	*/
2382	PDMDEVREG const g_DeviceIommuIntel =
2383	{
2384	/* .u32Version = */ PDM_DEVREG_VERSION,
2385	/* .uReserved0 = */ 0,
2386	/* .szName = */ "iommu-intel",
2387	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
2388	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
2389	/* .cMaxInstances = */ 1,
2390	/* .uSharedVersion = */ 42,
2391	/* .cbInstanceShared = */ sizeof(DMAR),
2392	/* .cbInstanceCC = */ sizeof(DMARCC),
2393	/* .cbInstanceRC = */ sizeof(DMARRC),
2394	/* .cMaxPciDevices = */ 1,
2395	/* .cMaxMsixVectors = */ 0,
2396	/* .pszDescription = */ "IOMMU (Intel)",
2397	#if defined(IN_RING3)
2398	/* .pszRCMod = */ "VBoxDDRC.rc",
2399	/* .pszR0Mod = */ "VBoxDDR0.r0",
2400	/* .pfnConstruct = */ iommuIntelR3Construct,
2401	/* .pfnDestruct = */ iommuIntelR3Destruct,
2402	/* .pfnRelocate = */ NULL,
2403	/* .pfnMemSetup = */ NULL,
2404	/* .pfnPowerOn = */ NULL,
2405	/* .pfnReset = */ iommuIntelR3Reset,
2406	/* .pfnSuspend = */ NULL,
2407	/* .pfnResume = */ NULL,
2408	/* .pfnAttach = */ NULL,
2409	/* .pfnDetach = */ NULL,
2410	/* .pfnQueryInterface = */ NULL,
2411	/* .pfnInitComplete = */ NULL,
2412	/* .pfnPowerOff = */ NULL,
2413	/* .pfnSoftReset = */ NULL,
2414	/* .pfnReserved0 = */ NULL,
2415	/* .pfnReserved1 = */ NULL,
2416	/* .pfnReserved2 = */ NULL,
2417	/* .pfnReserved3 = */ NULL,
2418	/* .pfnReserved4 = */ NULL,
2419	/* .pfnReserved5 = */ NULL,
2420	/* .pfnReserved6 = */ NULL,
2421	/* .pfnReserved7 = */ NULL,
2422	#elif defined(IN_RING0)
2423	/* .pfnEarlyConstruct = */ NULL,
2424	/* .pfnConstruct = */ iommuIntelRZConstruct,
2425	/* .pfnDestruct = */ NULL,
2426	/* .pfnFinalDestruct = */ NULL,
2427	/* .pfnRequest = */ NULL,
2428	/* .pfnReserved0 = */ NULL,
2429	/* .pfnReserved1 = */ NULL,
2430	/* .pfnReserved2 = */ NULL,
2431	/* .pfnReserved3 = */ NULL,
2432	/* .pfnReserved4 = */ NULL,
2433	/* .pfnReserved5 = */ NULL,
2434	/* .pfnReserved6 = */ NULL,
2435	/* .pfnReserved7 = */ NULL,
2436	#elif defined(IN_RC)
2437	/* .pfnConstruct = */ iommuIntelRZConstruct,
2438	/* .pfnReserved0 = */ NULL,
2439	/* .pfnReserved1 = */ NULL,
2440	/* .pfnReserved2 = */ NULL,
2441	/* .pfnReserved3 = */ NULL,
2442	/* .pfnReserved4 = */ NULL,
2443	/* .pfnReserved5 = */ NULL,
2444	/* .pfnReserved6 = */ NULL,
2445	/* .pfnReserved7 = */ NULL,
2446	#else
2447	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
2448	#endif
2449	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
2450	};
2451
2452	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2453

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88786

Download in other formats: