DevIommuIntel.cpp@ 88859

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1	/* $Id: DevIommuIntel.cpp 88859 2021-05-04 14:58:30Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock (not expected to fail). */
67	#ifdef IN_RING3
68	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69	#else
70	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71	do { \
72	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73	AssertRC(rcLock); \
74	} while (0)
75	#endif
76
77	/** Release the DMAR lock. */
78	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80	/** Asserts that the calling thread owns the DMAR lock. */
81	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82	do { \
83	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84	RT_NOREF1(a_pThisCC); \
85	} while (0)
86
87	/** Asserts that the calling thread does not own the DMAR lock. */
88	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89	do { \
90	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91	RT_NOREF1(a_pThisCC); \
92	} while (0)
93
94	/** The number of fault recording registers our implementation supports.
95	* Normal guest operation shouldn't trigger faults anyway, so we only support the
96	* minimum number of registers (which is 1).
97	*
98	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101	/** Offset of first register in group 0. */
102	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
103	/** Offset of last register in group 0 (inclusive). */
104	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
105	/** Last valid offset in group 0 (exclusive). */
106	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
107	/** Size of the group 0 (in bytes). */
108	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
109	/*< Implementation-specific MMIO offset of IVA_REG. /
110	#define DMAR_MMIO_OFF_IVA_REG 0xe50
111	/*< Implementation-specific MMIO offset of IOTLB_REG. /
112	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
113	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
114	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
115	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
116	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
117	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
118
119	/** Offset of first register in group 1. */
120	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
121	/** Offset of last register in group 1 (inclusive). */
122	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
123	/** Last valid offset in group 1 (exclusive). */
124	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
125	/** Size of the group 1 (in bytes). */
126	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
127
128	/** DMAR implementation's major version number (exposed to software).
129	* We report 6 as the major version since we support queued-invalidations as
130	* software may make assumptions based on that.
131	*
132	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
133	#define DMAR_VER_MAJOR 6
134	/** DMAR implementation's minor version number (exposed to software). */
135	#define DMAR_VER_MINOR 0
136
137	/** Release log prefix string. */
138	#define DMAR_LOG_PFX "Intel-IOMMU"
139	/** The current saved state version. */
140	#define DMAR_SAVED_STATE_VERSION 1
141
142
143	/*********************************************************************************************************************************
144	* Structures and Typedefs *
145	*********************************************************************************************************************************/
146	/**
147	* DMAR error diagnostics.
148	* Sorted alphabetically so it's easier to add and locate items, no other reason.
149	*
150	* @note Members of this enum are used as array indices, so no gaps in enum
151	* values are not allowed. Update g_apszDmarDiagDesc when you modify
152	* fields in this enum.
153	*/
154	typedef enum
155	{
156	kDmarDiag_None = 0,
157	kDmarDiag_CcmdReg_NotSupported,
158	kDmarDiag_CcmdReg_Qi_Enabled,
159	kDmarDiag_CcmdReg_Ttm_Invalid,
160	kDmarDiag_IqaReg_Dsc_Fetch_Error,
161	kDmarDiag_IqaReg_Dw_128_Invalid,
162	kDmarDiag_IqaReg_Dw_256_Invalid,
163	kDmarDiag_Iqei_Dsc_Type_Invalid,
164	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
165	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
166	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
167	kDmarDiag_Iqei_Ttm_Rsvd,
168	kDmarDiag_IqtReg_Qt_Invalid,
169	kDmarDiag_IqtReg_Qt_NotAligned,
170	kDmarDiag_Ir_Cfi_Blocked,
171	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
172	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
173	kDmarDiag_Ir_Rfi_Irte_Not_Present,
174	kDmarDiag_Ir_Rfi_Irte_Rsvd,
175	kDmarDiag_Ir_Rfi_Rsvd,
176	/* Member for determining array index limit. */
177	kDmarDiag_End,
178	/* Type size hack. */
179	kDmarDiag_32Bit_Hack = 0x7fffffff
180	} DMARDIAG;
181	AssertCompileSize(DMARDIAG, 4);
182
183	/** DMAR diagnostic enum description expansion.
184	* The below construct ensures typos in the input to this macro are caught
185	* during compile time. */
186	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
187
188	/** DMAR diagnostics description for members in DMARDIAG. */
189	static const char *const g_apszDmarDiagDesc[] =
190	{
191	DMARDIAG_DESC(None ),
192	DMARDIAG_DESC(CcmdReg_NotSupported ),
193	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
194	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
195	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
196	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
197	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
198	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
199	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
200	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
201	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
202	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
203	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
204	DMARDIAG_DESC(IqtReg_Qt_NotAligned ),
205	DMARDIAG_DESC(Ir_Cfi_Blocked ),
206	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
207	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
208	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
209	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
210	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
211	/* kDmarDiag_End */
212	};
213	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
214	#undef DMARDIAG_DESC
215
216	/**
217	* The shared DMAR device state.
218	*/
219	typedef struct DMAR
220	{
221	/** IOMMU device index. */
222	uint32_t idxIommu;
223	/** DMAR magic. */
224	uint32_t u32Magic;
225
226	/** Registers (group 0). */
227	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
228	/** Registers (group 1). */
229	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
230
231	/** @name Lazily activated registers.
232	* These are the active values for lazily activated registers. Software is free to
233	* modify the actual register values while remapping/translation is enabled but they
234	* take effect only when explicitly signaled by software, hence we need to hold the
235	* active values separately.
236	* @{ */
237	/** Currently active IRTA_REG. */
238	uint64_t uIrtaReg;
239	/** Currently active RTADDR_REG. */
240	uint64_t uRtaddrReg;
241	/** @} */
242
243	/** @name Register copies for a tiny bit faster and more convenient access.
244	* @{ */
245	/** Copy of VER_REG. */
246	uint8_t uVerReg;
247	/** Alignment. */
248	uint8_t abPadding[7];
249	/** Copy of CAP_REG. */
250	uint64_t fCapReg;
251	/** Copy of ECAP_REG. */
252	uint64_t fExtCapReg;
253	/** @} */
254
255	/** The event semaphore the invalidation-queue thread waits on. */
256	SUPSEMEVENT hEvtInvQueue;
257	/** Whether the invalidation-queue thread has been signaled. */
258	bool volatile fInvQueueThreadSignaled;
259	/** Padding. */
260	bool afPadding0[3];
261	/** Error diagnostic. */
262	DMARDIAG enmDiag;
263	/** The MMIO handle. */
264	IOMMMIOHANDLE hMmio;
265
266	#ifdef VBOX_WITH_STATISTICS
267	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
268	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
269	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
270	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
271
272	STAMCOUNTER StatMsiRemapR3; /*< Number of MSI remap requests in R3. /
273	STAMCOUNTER StatMsiRemapRZ; /*< Number of MSI remap requests in RZ. /
274
275	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
276	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
277	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
278	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
279
280	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
281	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
282	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
283	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
284
285	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
286	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
287	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
288	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
289	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
290	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
291	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
292	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
293	#endif
294	} DMAR;
295	/** Pointer to the DMAR device state. */
296	typedef DMAR *PDMAR;
297	/** Pointer to the const DMAR device state. */
298	typedef DMAR const *PCDMAR;
299	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
300	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
301
302	/**
303	* The ring-3 DMAR device state.
304	*/
305	typedef struct DMARR3
306	{
307	/** Device instance. */
308	PPDMDEVINSR3 pDevInsR3;
309	/** The IOMMU helper. */
310	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
311	/** The invalidation-queue thread. */
312	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
313	} DMARR3;
314	/** Pointer to the ring-3 DMAR device state. */
315	typedef DMARR3 *PDMARR3;
316	/** Pointer to the const ring-3 DMAR device state. */
317	typedef DMARR3 const *PCDMARR3;
318
319	/**
320	* The ring-0 DMAR device state.
321	*/
322	typedef struct DMARR0
323	{
324	/** Device instance. */
325	PPDMDEVINSR0 pDevInsR0;
326	/** The IOMMU helper. */
327	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
328	} DMARR0;
329	/** Pointer to the ring-0 IOMMU device state. */
330	typedef DMARR0 *PDMARR0;
331	/** Pointer to the const ring-0 IOMMU device state. */
332	typedef DMARR0 const *PCDMARR0;
333
334	/**
335	* The raw-mode DMAR device state.
336	*/
337	typedef struct DMARRC
338	{
339	/** Device instance. */
340	PPDMDEVINSRC pDevInsRC;
341	/** The IOMMU helper. */
342	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
343	} DMARRC;
344	/** Pointer to the raw-mode DMAR device state. */
345	typedef DMARRC *PDMARRC;
346	/** Pointer to the const raw-mode DMAR device state. */
347	typedef DMARRC const *PCIDMARRC;
348
349	/** The DMAR device state for the current context. */
350	typedef CTX_SUFF(DMAR) DMARCC;
351	/** Pointer to the DMAR device state for the current context. */
352	typedef CTX_SUFF(PDMAR) PDMARCC;
353	/** Pointer to the const DMAR device state for the current context. */
354	typedef CTX_SUFF(PDMAR) const PCDMARCC;
355
356
357	/*********************************************************************************************************************************
358	* Global Variables *
359	*********************************************************************************************************************************/
360	/**
361	* Read-write masks for DMAR registers (group 0).
362	*/
363	static uint32_t const g_au32RwMasks0[] =
364	{
365	/* Offset Register Low High */
366	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
367	/* 0x004 Reserved */ 0,
368	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
369	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
370	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
371	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
372	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
373	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
374	/* 0x030 Reserved */ 0,
375	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
376	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
377	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
378	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
379	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
380	/* 0x048 Reserved */ 0, 0,
381	/* 0x050 Reserved */ 0, 0,
382	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
383	/* 0x060 Reserved */ 0,
384	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
385	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
386	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
387	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
388	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
389	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
390	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
391	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
392	/* 0x098 Reserved */ 0,
393	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
394	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
395	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
396	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
397	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
398	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
399	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
400	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
401	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
402	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
403	/* 0x0d8 Reserved */ 0,
404	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
405	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
406	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
407	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
408	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
409	/* 0x0f0 Reserved */ 0, 0,
410	/* 0x0f8 Reserved */ 0, 0,
411	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
412	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
413	/* 0x110 Reserved */ 0, 0,
414	/* 0x118 Reserved */ 0, 0,
415	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
416	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
417	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
418	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
419	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
420	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
421	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
422	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
423	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
424	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
425	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
426	/* 0x178 Reserved */ 0, 0,
427	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
428	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
429	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
430	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
431	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
432	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
433	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
434	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
435	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
436	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
437	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
438	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
439	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
440	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
441	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
442	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
443	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
444	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
445	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
446	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
447	};
448	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
449
450	/**
451	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
452	*/
453	static uint32_t const g_au32Rw1cMasks0[] =
454	{
455	/* Offset Register Low High */
456	/* 0x000 VER_REG */ 0,
457	/* 0x004 Reserved */ 0,
458	/* 0x008 CAP_REG */ 0, 0,
459	/* 0x010 ECAP_REG */ 0, 0,
460	/* 0x018 GCMD_REG */ 0,
461	/* 0x01c GSTS_REG */ 0,
462	/* 0x020 RTADDR_REG */ 0, 0,
463	/* 0x028 CCMD_REG */ 0, 0,
464	/* 0x030 Reserved */ 0,
465	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
466	/* 0x038 FECTL_REG */ 0,
467	/* 0x03c FEDATA_REG */ 0,
468	/* 0x040 FEADDR_REG */ 0,
469	/* 0x044 FEUADDR_REG */ 0,
470	/* 0x048 Reserved */ 0, 0,
471	/* 0x050 Reserved */ 0, 0,
472	/* 0x058 AFLOG_REG */ 0, 0,
473	/* 0x060 Reserved */ 0,
474	/* 0x064 PMEN_REG */ 0,
475	/* 0x068 PLMBASE_REG */ 0,
476	/* 0x06c PLMLIMIT_REG */ 0,
477	/* 0x070 PHMBASE_REG */ 0, 0,
478	/* 0x078 PHMLIMIT_REG */ 0, 0,
479	/* 0x080 IQH_REG */ 0, 0,
480	/* 0x088 IQT_REG */ 0, 0,
481	/* 0x090 IQA_REG */ 0, 0,
482	/* 0x098 Reserved */ 0,
483	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
484	/* 0x0a0 IECTL_REG */ 0,
485	/* 0x0a4 IEDATA_REG */ 0,
486	/* 0x0a8 IEADDR_REG */ 0,
487	/* 0x0ac IEUADDR_REG */ 0,
488	/* 0x0b0 IQERCD_REG */ 0, 0,
489	/* 0x0b8 IRTA_REG */ 0, 0,
490	/* 0x0c0 PQH_REG */ 0, 0,
491	/* 0x0c8 PQT_REG */ 0, 0,
492	/* 0x0d0 PQA_REG */ 0, 0,
493	/* 0x0d8 Reserved */ 0,
494	/* 0x0dc PRS_REG */ 0,
495	/* 0x0e0 PECTL_REG */ 0,
496	/* 0x0e4 PEDATA_REG */ 0,
497	/* 0x0e8 PEADDR_REG */ 0,
498	/* 0x0ec PEUADDR_REG */ 0,
499	/* 0x0f0 Reserved */ 0, 0,
500	/* 0x0f8 Reserved */ 0, 0,
501	/* 0x100 MTRRCAP_REG */ 0, 0,
502	/* 0x108 MTRRDEF_REG */ 0, 0,
503	/* 0x110 Reserved */ 0, 0,
504	/* 0x118 Reserved */ 0, 0,
505	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
506	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
507	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
508	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
509	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
510	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
511	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
512	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
513	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
514	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
515	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
516	/* 0x178 Reserved */ 0, 0,
517	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
518	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
519	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
520	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
521	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
522	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
523	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
524	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
525	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
526	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
527	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
528	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
529	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
530	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
531	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
532	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
533	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
534	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
535	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
536	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
537	};
538	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
539
540	/**
541	* Read-write masks for DMAR registers (group 1).
542	*/
543	static uint32_t const g_au32RwMasks1[] =
544	{
545	/* Offset Register Low High */
546	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
547	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
548	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
549	/* 0xe18 VCMDRSVD_REG */ 0, 0,
550	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
551	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
552	/* 0xe30 Reserved */ 0, 0,
553	/* 0xe38 Reserved */ 0, 0,
554	/* 0xe40 Reserved */ 0, 0,
555	/* 0xe48 Reserved */ 0, 0,
556	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
557	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
558	/* 0xe60 Reserved */ 0, 0,
559	/* 0xe68 Reserved */ 0, 0,
560	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
561	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
562	};
563	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
564	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
565
566	/**
567	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
568	*/
569	static uint32_t const g_au32Rw1cMasks1[] =
570	{
571	/* Offset Register Low High */
572	/* 0xe00 VCCAP_REG */ 0, 0,
573	/* 0xe08 VCMD_EO_REG */ 0, 0,
574	/* 0xe10 VCMD_REG */ 0, 0,
575	/* 0xe18 VCMDRSVD_REG */ 0, 0,
576	/* 0xe20 VCRSP_REG */ 0, 0,
577	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
578	/* 0xe30 Reserved */ 0, 0,
579	/* 0xe38 Reserved */ 0, 0,
580	/* 0xe40 Reserved */ 0, 0,
581	/* 0xe48 Reserved */ 0, 0,
582	/* 0xe50 IVA_REG */ 0, 0,
583	/* 0xe58 IOTLB_REG */ 0, 0,
584	/* 0xe60 Reserved */ 0, 0,
585	/* 0xe68 Reserved */ 0, 0,
586	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
587	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
588	};
589	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
590
591	/** Array of RW masks for each register group. */
592	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
593
594	/** Array of RW1C masks for each register group. */
595	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
596
597	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
598	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
599
600
601	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
602	/** @todo Add IOMMU struct size/alignment verification, see
603	* Devices/testcase/Makefile.kmk and
604	* Devices/testcase/tstDeviceStructSize[RC].cpp */
605
606	/**
607	* Returns the number of supported adjusted guest-address width (SAGAW) in bits
608	* given a CAP_REG.SAGAW value.
609	*
610	* @returns Number of SAGAW bits.
611	* @param uSagaw The CAP_REG.SAGAW value.
612	*/
613	static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
614	{
615	if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
616	return 30 + (uSagaw * 9);
617	return 0;
618	}
619
620
621	/**
622	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
623	* guest address width (MGAW).
624	*
625	* @returns The CAP_REG.SAGAW value.
626	* @param uMgaw The CAP_REG.MGAW value.
627	*/
628	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
629	{
630	switch (uMgaw + 1)
631	{
632	case 39: return 1;
633	case 48: return 2;
634	case 57: return 3;
635	}
636	return 0;
637	}
638
639
640	/**
641	* Returns whether the interrupt remapping fault is qualified or not.
642	*
643	* @returns @c true if qualified, @c false otherwise.
644	* @param enmIrFault The interrupt remapping fault condition.
645	*/
646	static bool vtdIrFaultIsQualified(VTD_IR_FAULT_T enmIrFault)
647	{
648	switch (enmIrFault)
649	{
650	case kIrf_Irte_Not_Present:
651	case kIrf_Irte_Present_Rsvd:
652	case kIrf_Irte_Present_Invalid:
653	case kIrf_Pid_Read_Failed:
654	case kIrf_Pid_Rsvd:
655	return true;
656	default:
657	return false;
658	}
659	}
660
661
662	/**
663	* Returns table translation mode's descriptive name.
664	*
665	* @returns The descriptive name.
666	* @param uTtm The RTADDR_REG.TTM value.
667	*/
668	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
669	{
670	Assert(!(uTtm & 3));
671	static const char* s_apszTtmNames[] =
672	{
673	"Legacy Mode",
674	"Scalable Mode",
675	"Reserved",
676	"Abort-DMA Mode"
677	};
678	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
679	}
680
681
682	/**
683	* Gets the index of the group the register belongs to given its MMIO offset.
684	*
685	* @returns The group index.
686	* @param offReg The MMIO offset of the register.
687	* @param cbReg The size of the access being made (for bounds checking on
688	* debug builds).
689	*/
690	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
691	{
692	uint16_t const offLast = offReg + cbReg - 1;
693	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
694	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
695	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
696	}
697
698
699	/**
700	* Gets the group the register belongs to given its MMIO offset.
701	*
702	* @returns Pointer to the first element of the register group.
703	* @param pThis The shared DMAR device state.
704	* @param offReg The MMIO offset of the register.
705	* @param cbReg The size of the access being made (for bounds checking on
706	* debug builds).
707	* @param pIdxGroup Where to store the index of the register group the register
708	* belongs to.
709	*/
710	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
711	{
712	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
713	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
714	return apbRegs[*pIdxGroup];
715	}
716
717
718	/**
719	* Const/read-only version of dmarRegGetGroup.
720	*
721	* @copydoc dmarRegGetGroup
722	*/
723	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
724	{
725	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
726	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
727	return apbRegs[*pIdxGroup];
728	}
729
730
731	/**
732	* Writes a 32-bit register with the exactly the supplied value.
733	*
734	* @param pThis The shared DMAR device state.
735	* @param offReg The MMIO offset of the register.
736	* @param uReg The 32-bit value to write.
737	*/
738	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
739	{
740	uint8_t idxGroup;
741	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
742	NOREF(idxGroup);
743	(uint32_t )(pabRegs + offReg) = uReg;
744	}
745
746
747	/**
748	* Writes a 64-bit register with the exactly the supplied value.
749	*
750	* @param pThis The shared DMAR device state.
751	* @param offReg The MMIO offset of the register.
752	* @param uReg The 64-bit value to write.
753	*/
754	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
755	{
756	uint8_t idxGroup;
757	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
758	NOREF(idxGroup);
759	(uint64_t )(pabRegs + offReg) = uReg;
760	}
761
762
763	/**
764	* Reads a 32-bit register with exactly the value it contains.
765	*
766	* @returns The raw register value.
767	* @param pThis The shared DMAR device state.
768	* @param offReg The MMIO offset of the register.
769	*/
770	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
771	{
772	uint8_t idxGroup;
773	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
774	NOREF(idxGroup);
775	return (uint32_t )(pabRegs + offReg);
776	}
777
778
779	/**
780	* Reads a 64-bit register with exactly the value it contains.
781	*
782	* @returns The raw register value.
783	* @param pThis The shared DMAR device state.
784	* @param offReg The MMIO offset of the register.
785	*/
786	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
787	{
788	uint8_t idxGroup;
789	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
790	NOREF(idxGroup);
791	return (uint64_t )(pabRegs + offReg);
792	}
793
794
795	/**
796	* Reads a 32-bit register with exactly the value it contains along with their
797	* corresponding masks
798	*
799	* @param pThis The shared DMAR device state.
800	* @param offReg The MMIO offset of the register.
801	* @param puReg Where to store the raw 32-bit register value.
802	* @param pfRwMask Where to store the RW mask corresponding to this register.
803	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
804	*/
805	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
806	{
807	uint8_t idxGroup;
808	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
809	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
810	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
811	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
812	puReg = (uint32_t *)(pabRegs + offReg);
813	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
814	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
815	}
816
817
818	/**
819	* Reads a 64-bit register with exactly the value it contains along with their
820	* corresponding masks.
821	*
822	* @param pThis The shared DMAR device state.
823	* @param offReg The MMIO offset of the register.
824	* @param puReg Where to store the raw 64-bit register value.
825	* @param pfRwMask Where to store the RW mask corresponding to this register.
826	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
827	*/
828	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
829	{
830	uint8_t idxGroup;
831	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
832	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
833	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
834	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
835	puReg = (uint64_t *)(pabRegs + offReg);
836	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
837	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
838	}
839
840
841	/**
842	* Writes a 32-bit register as it would be when written by software.
843	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
844	*
845	* @returns The value that's actually written to the register.
846	* @param pThis The shared DMAR device state.
847	* @param offReg The MMIO offset of the register.
848	* @param uReg The 32-bit value to write.
849	*/
850	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
851	{
852	/* Read current value from the 32-bit register. */
853	uint32_t uCurReg;
854	uint32_t fRwMask;
855	uint32_t fRw1cMask;
856	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
857
858	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
859	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
860	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
861	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
862
863	/* Write new value to the 32-bit register. */
864	dmarRegWriteRaw32(pThis, offReg, uNewReg);
865	return uNewReg;
866	}
867
868
869	/**
870	* Writes a 64-bit register as it would be when written by software.
871	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
872	*
873	* @returns The value that's actually written to the register.
874	* @param pThis The shared DMAR device state.
875	* @param offReg The MMIO offset of the register.
876	* @param uReg The 64-bit value to write.
877	*/
878	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
879	{
880	/* Read current value from the 64-bit register. */
881	uint64_t uCurReg;
882	uint64_t fRwMask;
883	uint64_t fRw1cMask;
884	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
885
886	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
887	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
888	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
889	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
890
891	/* Write new value to the 64-bit register. */
892	dmarRegWriteRaw64(pThis, offReg, uNewReg);
893	return uNewReg;
894	}
895
896
897	/**
898	* Reads a 32-bit register as it would be when read by software.
899	*
900	* @returns The register value.
901	* @param pThis The shared DMAR device state.
902	* @param offReg The MMIO offset of the register.
903	*/
904	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
905	{
906	return dmarRegReadRaw32(pThis, offReg);
907	}
908
909
910	/**
911	* Reads a 64-bit register as it would be when read by software.
912	*
913	* @returns The register value.
914	* @param pThis The shared DMAR device state.
915	* @param offReg The MMIO offset of the register.
916	*/
917	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
918	{
919	return dmarRegReadRaw64(pThis, offReg);
920	}
921
922
923	/**
924	* Modifies a 32-bit register.
925	*
926	* @param pThis The shared DMAR device state.
927	* @param offReg The MMIO offset of the register.
928	* @param fAndMask The AND mask (applied first).
929	* @param fOrMask The OR mask.
930	* @remarks This does NOT apply RO or RW1C masks while modifying the
931	* register.
932	*/
933	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
934	{
935	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
936	uReg = (uReg & fAndMask) \| fOrMask;
937	dmarRegWriteRaw32(pThis, offReg, uReg);
938	}
939
940
941	/**
942	* Modifies a 64-bit register.
943	*
944	* @param pThis The shared DMAR device state.
945	* @param offReg The MMIO offset of the register.
946	* @param fAndMask The AND mask (applied first).
947	* @param fOrMask The OR mask.
948	* @remarks This does NOT apply RO or RW1C masks while modifying the
949	* register.
950	*/
951	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
952	{
953	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
954	uReg = (uReg & fAndMask) \| fOrMask;
955	dmarRegWriteRaw64(pThis, offReg, uReg);
956	}
957
958
959	/**
960	* Checks if the invalidation-queue is empty.
961	*
962	* Extended version which optionally returns the current queue head and tail
963	* offsets.
964	*
965	* @returns @c true if empty, @c false otherwise.
966	* @param pThis The shared DMAR device state.
967	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
968	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
969	*/
970	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
971	{
972	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
973	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
974	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
975
976	/* Don't bother masking QT, QH since other bits are RsvdZ. */
977	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
978	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
979	if (poffQh)
980	*poffQh = uIqhReg;
981	if (poffQt)
982	*poffQt = uIqtReg;
983	return uIqtReg == uIqhReg;
984	}
985
986
987	/**
988	* Checks if the invalidation-queue is empty.
989	*
990	* @returns @c true if empty, @c false otherwise.
991	* @param pThis The shared DMAR device state.
992	*/
993	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
994	{
995	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
996	}
997
998
999	/**
1000	* Checks if the invalidation-queue is capable of processing requests.
1001	*
1002	* @returns @c true if the invalidation-queue can process requests, @c false
1003	* otherwise.
1004	* @param pThis The shared DMAR device state.
1005	*/
1006	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1007	{
1008	/* Check if queued-invalidation is enabled. */
1009	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1010	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1011	{
1012	/* Check if there are no invalidation-queue or timeout errors. */
1013	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1014	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1015	return true;
1016	}
1017	return false;
1018	}
1019
1020
1021	/**
1022	* Wakes up the invalidation-queue thread if there are requests to be processed.
1023	*
1024	* @param pDevIns The IOMMU device instance.
1025	*/
1026	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1027	{
1028	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1029	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1030	Log4Func(("\n"));
1031
1032	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1033
1034	if ( dmarInvQueueCanProcessRequests(pThis)
1035	&& !dmarInvQueueIsEmpty(pThis)
1036	&& !ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, true))
1037	{
1038	Log4Func(("Signaling the invalidation-queue thread\n"));
1039	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1040	}
1041	}
1042
1043
1044	/**
1045	* Raises an interrupt in response to a fault event.
1046	*
1047	* @param pDevIns The IOMMU device instance.
1048	*
1049	* @remarks This assumes the caller has already set the required status bits in the
1050	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1051	*/
1052	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1053	{
1054	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1055	#ifdef RT_STRICT
1056	{
1057	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1058	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1059	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1060	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1061	\| VTD_BF_FSTS_REG_IQE_MASK;
1062	Assert(uFstsReg & fFaultMask);
1063	}
1064	#endif
1065
1066	uint32_t uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
1067	if (!(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1068	{
1069	/* Software has unmasked the interrupt, raise it. */
1070	MSIMSG Msi;
1071	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
1072	Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
1073	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
1074
1075	/** @todo Assert Msi.Addr is in the MSR_IA32_APICBASE_ADDR range and ensure on
1076	* FEADD_REG write it can't be anything else? */
1077	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1078	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1079
1080	/* Clear interrupt pending bit. */
1081	uFectlReg &= ~VTD_BF_FECTL_REG_IP_MASK;
1082	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1083	}
1084	else
1085	{
1086	/* Interrupt is masked, set the interrupt pending bit. */
1087	uFectlReg \|= VTD_BF_FECTL_REG_IP_MASK;
1088	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uFectlReg);
1089	}
1090	}
1091
1092
1093	#ifdef IN_RING3
1094	/**
1095	* Raises an interrupt in response to an invalidation (complete) event.
1096	*
1097	* @param pDevIns The IOMMU device instance.
1098	*/
1099	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1100	{
1101	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1102	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1103	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1104
1105	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1106	if (uIcsReg & VTD_BF_ICS_REG_IWC_MASK)
1107	return;
1108
1109	uint32_t uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
1110	if (!(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1111	{
1112	/* Software has unmasked the interrupt, raise it. */
1113	MSIMSG Msi;
1114	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
1115	Msi.Addr.au32[1] = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
1116	Msi.Data.u32 = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
1117
1118	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1119
1120	/* Clear interrupt pending bit. */
1121	uIectlReg &= ~VTD_BF_IECTL_REG_IP_MASK;
1122	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
1123	}
1124	else
1125	{
1126	/* Interrupt is masked, set the interrupt pending bit. */
1127	uIectlReg \|= VTD_BF_IECTL_REG_IP_MASK;
1128	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uIectlReg);
1129	}
1130	}
1131	#endif /* IN_RING3 */
1132
1133
1134	/**
1135	* Checks if a primary fault can be recorded.
1136	*
1137	* @returns @c true if the fault can be recorded, @c false otherwise.
1138	* @param pDevIns The IOMMU device instance.
1139	* @param pThis The shared DMAR device state.
1140	*
1141	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1142	* NOT call it unless there is a fault condition!
1143	*/
1144	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1145	{
1146	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1147	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1148
1149	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1150	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1151	return false;
1152
1153	/*
1154	* If we add more FRCD registers, we'll have to loop through them here.
1155	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1156	* nor do we need to increment FRI.
1157	*
1158	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1159	*/
1160	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1161	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1162	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1163	{
1164	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1165	dmarRegWrite32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1166	return false;
1167	}
1168
1169	return true;
1170	}
1171
1172
1173	/**
1174	* Records an interrupt request fault.
1175	*
1176	* @param pDevIns The IOMMU device instance.
1177	* @param enmDiag The diagnostic reason.
1178	* @param enmIrFault The interrupt fault reason.
1179	* @param idDevice The device ID (bus, device, function).
1180	* @param idxIntr The interrupt index.
1181	*/
1182	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IR_FAULT_T enmIrFault, uint16_t idDevice,
1183	uint16_t idxIntr)
1184	{
1185	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1186	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1187	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1188
1189	/* Update the diagnostic reason. */
1190	pThis->enmDiag = enmDiag;
1191
1192	/* We don't support advance fault logging. */
1193	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1194
1195	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1196	{
1197	/* Update the fault recording registers with the fault information. */
1198	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1199	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1200	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1201	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1202	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1203	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1204
1205	/* Set the Pending Primary Fault (PPF) field in the status register. */
1206	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1207
1208	/* Raise interrupt if necessary. */
1209	dmarFaultEventRaiseInterrupt(pDevIns);
1210	}
1211	}
1212
1213
1214	/**
1215	* Records a qualified interrupt request fault.
1216	*
1217	* Qualified faults are those that can be suppressed by software using the FPD bit
1218	* in the IRTE.
1219	*
1220	* @param pDevIns The IOMMU device instance.
1221	* @param enmDiag The diagnostic reason.
1222	* @param enmIrFault The interrupt fault reason.
1223	* @param idDevice The device ID (bus, device, function).
1224	* @param idxIntr The interrupt index.
1225	* @param pIrte The IRTE that caused this fault.
1226	*/
1227	static void dmarIrFaultRecordQualified(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IR_FAULT_T enmIrFault, uint16_t idDevice,
1228	uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1229	{
1230	Assert(vtdIrFaultIsQualified(enmIrFault));
1231	Assert(pIrte);
1232	if (!(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK))
1233	return dmarIrFaultRecord(pDevIns, enmDiag, enmIrFault, idDevice, idxIntr);
1234	}
1235
1236
1237	/**
1238	* Records an IQE fault.
1239	*
1240	* @param pDevIns The IOMMU device instance.
1241	* @param enmIqei The IQE information.
1242	* @param enmDiag The diagnostic reason.
1243	*/
1244	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTD_IQEI_T enmIqei)
1245	{
1246	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1247	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1248	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1249
1250	/* Update the diagnostic reason. */
1251	pThis->enmDiag = enmDiag;
1252
1253	/* Set the error bit. */
1254	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1255	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1256
1257	/* Set the error information. */
1258	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1259	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1260
1261	dmarFaultEventRaiseInterrupt(pDevIns);
1262	}
1263
1264
1265	/**
1266	* Handles writes to GCMD_REG.
1267	*
1268	* @returns Strict VBox status code.
1269	* @param pDevIns The IOMMU device instance.
1270	* @param uGcmdReg The value written to GCMD_REG.
1271	*/
1272	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1273	{
1274	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1275	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1276	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1277	uint64_t const fExtCapReg = pThis->fExtCapReg;
1278
1279	/*
1280	* Queued-invalidation.
1281	*/
1282	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1283	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1284	{
1285	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1286	{
1287	/* Enable the invalidation-queue. */
1288	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1289	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1290	}
1291	else
1292	{
1293	/* Disable the invalidation-queue. */
1294	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1295	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1296	}
1297	}
1298
1299	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1300	{
1301	/*
1302	* Set Interrupt Remapping Table Pointer (SIRTP).
1303	*/
1304	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1305	{
1306	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1307	* supported. */
1308	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1309	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1310	}
1311
1312	/*
1313	* Interrupt remapping.
1314	*/
1315	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1316	{
1317	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1318	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1319	else
1320	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1321	}
1322	}
1323
1324	/*
1325	* Set Root Table Pointer (SRTP).
1326	*/
1327	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1328	{
1329	/** @todo Perform global invalidation of all remapping translation caches when
1330	* ESRTPS is supported. */
1331	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1332	}
1333
1334	/** @todo Rest of the bits. */
1335
1336	return VINF_SUCCESS;
1337	}
1338
1339
1340	/**
1341	* Handles writes to CCMD_REG.
1342	*
1343	* @returns Strict VBox status code.
1344	* @param pDevIns The IOMMU device instance.
1345	* @param offReg The MMIO register offset.
1346	* @param cbReg The size of the MMIO access (in bytes).
1347	* @param uCcmdReg The value written to CCMD_REG.
1348	*/
1349	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1350	{
1351	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1352	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1353	{
1354	/* Check if we need to invalidate the context-context. */
1355	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1356	if (fIcc)
1357	{
1358	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1359	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1360	if (uMajorVersion < 6)
1361	{
1362	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1363	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1364	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1365	{
1366	/* Verify table translation mode is legacy. */
1367	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1368	if (fTtm == VTD_TTM_LEGACY_MODE)
1369	{
1370	/** @todo Invalidate. */
1371	return VINF_SUCCESS;
1372	}
1373	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1374	}
1375	else
1376	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1377	}
1378	else
1379	pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1380	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1381	}
1382	}
1383	return VINF_SUCCESS;
1384	}
1385
1386
1387	/**
1388	* Handles writes to IQT_REG.
1389	*
1390	* @returns Strict VBox status code.
1391	* @param pDevIns The IOMMU device instance.
1392	* @param offReg The MMIO register offset.
1393	* @param uIqtReg The value written to IQT_REG.
1394	*/
1395	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1396	{
1397	/* We only care about the low 32-bits, high 32-bits are reserved. */
1398	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1399	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1400
1401	/* Paranoia. */
1402	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1403
1404	uint32_t const offQt = uIqtReg;
1405	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1406	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1407
1408	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1409	if ( fDw != VTD_IQA_REG_DW_256_BIT
1410	\|\| !(offQt & RT_BIT(4)))
1411	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1412	else
1413	{
1414	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1415	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1416	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, kIqei_QueueTailNotAligned);
1417	}
1418	return VINF_SUCCESS;
1419	}
1420
1421
1422	/**
1423	* Handles writes to IQA_REG.
1424	*
1425	* @returns Strict VBox status code.
1426	* @param pDevIns The IOMMU device instance.
1427	* @param offReg The MMIO register offset.
1428	* @param uIqaReg The value written to IQA_REG.
1429	*/
1430	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1431	{
1432	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1433	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1434
1435	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1436	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1437	* cannot happen or that it's ignored when it does happen. */
1438
1439	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1440	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1441	if (fDw == VTD_IQA_REG_DW_256_BIT)
1442	{
1443	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1444	if (fSupports256BitDw)
1445	{ /* likely */ }
1446	else
1447	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, kIqei_InvalidDescriptorWidth);
1448	}
1449	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1450
1451	return VINF_SUCCESS;
1452	}
1453
1454
1455	/**
1456	* Memory access bulk (one or more 4K pages) request from a device.
1457	*
1458	* @returns VBox status code.
1459	* @param pDevIns The IOMMU device instance.
1460	* @param idDevice The device ID (bus, device, function).
1461	* @param cIovas The number of addresses being accessed.
1462	* @param pauIovas The I/O virtual addresses for each page being accessed.
1463	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1464	* @param paGCPhysSpa Where to store the translated physical addresses.
1465	*
1466	* @thread Any.
1467	*/
1468	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1469	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1470	{
1471	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1472	return VERR_NOT_IMPLEMENTED;
1473	}
1474
1475
1476	/**
1477	* Memory access transaction from a device.
1478	*
1479	* @returns VBox status code.
1480	* @param pDevIns The IOMMU device instance.
1481	* @param idDevice The device ID (bus, device, function).
1482	* @param uIova The I/O virtual address being accessed.
1483	* @param cbIova The size of the access.
1484	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1485	* @param pGCPhysSpa Where to store the translated system physical address.
1486	* @param pcbContiguous Where to store the number of contiguous bytes translated
1487	* and permission-checked.
1488	*
1489	* @thread Any.
1490	*/
1491	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1492	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
1493	{
1494	RT_NOREF7(pDevIns, idDevice, uIova, cbIova, fFlags, pGCPhysSpa, pcbContiguous);
1495	return VERR_NOT_IMPLEMENTED;
1496	}
1497
1498
1499	/**
1500	* Reads an IRTE from guest memory.
1501	*
1502	* @returns VBox status code.
1503	* @param pDevIns The IOMMU device instance.
1504	* @param uIrtaReg The IRTA_REG.
1505	* @param idxIntr The interrupt index.
1506	* @param pIrte Where to store the read IRTE.
1507	*/
1508	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
1509	{
1510	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRIES(uIrtaReg));
1511
1512	size_t const cbIrte = sizeof(*pIrte);
1513	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
1514	int rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
1515	if (RT_SUCCESS(rc))
1516	return VINF_SUCCESS;
1517	return rc;
1518	}
1519
1520
1521	/**
1522	* Handles remapping of interrupts in remappable interrupt format.
1523	*
1524	* @returns VBox status code.
1525	* @param pDevIns The IOMMU device instance.
1526	* @param uIrtaReg The IRTA_REG.
1527	* @param idDevice The device ID (bus, device, function).
1528	* @param pMsiIn The source MSI.
1529	* @param pMsiOut Where to store the remapped MSI.
1530	*/
1531	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1532	{
1533	Assert(VTD_MSI_ADDR_GET_INTR_FORMAT(pMsiIn->Addr.u64) == VTD_INTR_FORMAT_REMAPPABLE);
1534
1535	/* Validate reserved bits in the interrupt request. */
1536	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
1537	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
1538	{ /* likely */ }
1539	else
1540	{
1541	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, kIrf_Remappable_Intr_Rsvd, idDevice, 0 /* idxIntr */);
1542	return VERR_IOMMU_INTR_REMAP_DENIED;
1543	}
1544
1545	/* Compute the index into the interrupt remap table. */
1546	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
1547	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
1548	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
1549	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
1550	uint32_t const idxIntr = fSubHandleValid
1551	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
1552	: uHandle;
1553
1554	/* Validate the index. */
1555	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRIES(uIrtaReg);
1556	if (idxIntr < cEntries)
1557	{ /* likely */ }
1558	else
1559	{
1560	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, kIrf_Intr_Index_Invalid, idDevice, idxIntr);
1561	return VERR_IOMMU_INTR_REMAP_DENIED;
1562	}
1563
1564	/** @todo Implement and read IRTE from interrupt-entry cache here. */
1565
1566	/* Read the interrupt remap table entry (IRTE). */
1567	VTD_IRTE_T Irte;
1568	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
1569	if (RT_SUCCESS(rc))
1570	{ /* likely */ }
1571	else
1572	{
1573	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, kIrf_Irte_Read_Failed, idDevice, idxIntr);
1574	return VERR_IOMMU_INTR_REMAP_DENIED;
1575	}
1576
1577	/* Validate IRTE. */
1578	uint64_t const uIrteQword0 = Irte.au64[0];
1579	uint64_t const uIrteQword1 = Irte.au64[1];
1580	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
1581	if (fPresent)
1582	{ /* likely */ }
1583	else
1584	{
1585	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, kIrf_Irte_Not_Present, idDevice, idxIntr, &Irte);
1586	return VERR_IOMMU_INTR_REMAP_DENIED;
1587	}
1588	if ( !(uIrteQword0 & ~VTD_IRTE_0_VALID_MASK)
1589	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
1590	{ /* likely */ }
1591	else
1592	{
1593	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, kIrf_Irte_Present_Rsvd, idDevice, idxIntr, &Irte);
1594	return VERR_IOMMU_INTR_REMAP_DENIED;
1595	}
1596
1597	/** @todo rest of validation using SVT and SQ. */
1598	pMsiOut = pMsiIn; // This is just temporary to shut up the compiler!
1599	return VERR_NOT_IMPLEMENTED;
1600	}
1601
1602
1603	/**
1604	* Interrupt remap request from a device.
1605	*
1606	* @returns VBox status code.
1607	* @param pDevIns The IOMMU device instance.
1608	* @param idDevice The device ID (bus, device, function).
1609	* @param pMsiIn The source MSI.
1610	* @param pMsiOut Where to store the remapped MSI.
1611	*/
1612	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1613	{
1614	/* Validate. */
1615	Assert(pDevIns);
1616	Assert(pMsiIn);
1617	Assert(pMsiOut);
1618	RT_NOREF1(idDevice);
1619
1620	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1621	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1622
1623	/* Lock and read all registers required for interrupt remapping up-front. */
1624	DMAR_LOCK(pDevIns, pThisCC);
1625	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1626	uint64_t const uIrtaReg = pThis->uIrtaReg;
1627	DMAR_UNLOCK(pDevIns, pThisCC);
1628
1629	/* Check if interrupt remapping is enabled. */
1630	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
1631	{
1632	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemap));
1633
1634	/* Handle compatibility format interrupts. */
1635	uint8_t const fIntrFormat = VTD_MSI_ADDR_GET_INTR_FORMAT(pMsiIn->Addr.u64);
1636	if (fIntrFormat == VTD_INTR_FORMAT_COMPAT)
1637	{
1638	/* If in Extended Interrupt Mode (EIM) or compatibility format interrupts are disabled, block the interrupt. */
1639	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
1640	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
1641	{
1642	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, kIrf_Cfi_Blocked, idDevice, 0 /* idxIntr */);
1643	return VERR_IOMMU_INTR_REMAP_DENIED;
1644	}
1645
1646	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
1647	pMsiOut = pMsiIn;
1648	return VINF_SUCCESS;
1649	}
1650
1651	/* Handle remappable format interrupts. */
1652	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
1653	}
1654
1655	/* If interrupt-remapping isn't enabled, all interrupts are pass-through. */
1656	pMsiOut = pMsiIn;
1657	return VINF_SUCCESS;
1658	}
1659
1660
1661	/**
1662	* @callback_method_impl{FNIOMMMIONEWWRITE}
1663	*/
1664	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
1665	{
1666	RT_NOREF1(pvUser);
1667	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1668
1669	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1670	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
1671
1672	uint16_t const offReg = off;
1673	uint16_t const offLast = offReg + cb - 1;
1674	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1675	{
1676	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1677	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
1678
1679	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv)
1680	: dmarRegWrite32(pThis, offReg, (uint32_t )pv);
1681	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1682	switch (off)
1683	{
1684	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
1685	{
1686	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
1687	break;
1688	}
1689
1690	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
1691	case VTD_MMIO_OFF_CCMD_REG + 4:
1692	{
1693	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
1694	break;
1695	}
1696
1697	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
1698	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
1699	{
1700	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
1701	break;
1702	}
1703
1704	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
1705	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
1706	{
1707	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
1708	break;
1709	}
1710	}
1711
1712	DMAR_UNLOCK(pDevIns, pThisCC);
1713	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
1714	return rcStrict;
1715	}
1716
1717	return VINF_IOM_MMIO_UNUSED_FF;
1718	}
1719
1720
1721	/**
1722	* @callback_method_impl{FNIOMMMIONEWREAD}
1723	*/
1724	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
1725	{
1726	RT_NOREF1(pvUser);
1727	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
1728
1729	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1730	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
1731
1732	uint16_t const offReg = off;
1733	uint16_t const offLast = offReg + cb - 1;
1734	if (DMAR_IS_MMIO_OFF_VALID(offLast))
1735	{
1736	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1737	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
1738
1739	if (cb == 8)
1740	{
1741	(uint64_t )pv = dmarRegRead64(pThis, offReg);
1742	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
1743	}
1744	else
1745	{
1746	(uint32_t )pv = dmarRegRead32(pThis, offReg);
1747	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
1748	}
1749
1750	DMAR_UNLOCK(pDevIns, pThisCC);
1751	return VINF_SUCCESS;
1752	}
1753
1754	return VINF_IOM_MMIO_UNUSED_FF;
1755	}
1756
1757
1758	#ifdef IN_RING3
1759	/**
1760	* Process requests in the invalidation queue.
1761	*
1762	* @param pDevIns The IOMMU device instance.
1763	* @param pvRequests The requests to process.
1764	* @param cbRequests The size of all requests (in bytes).
1765	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
1766	* VTD_IQA_REG_DW_256_BIT).
1767	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
1768	*/
1769	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
1770	uint8_t fTtm)
1771	{
1772	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
1773	do \
1774	{ \
1775	DMAR_LOCK(pDevIns, pThisR3); \
1776	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
1777	DMAR_UNLOCK(pDevIns, pThisR3); \
1778	return; \
1779	} while (0)
1780
1781	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1782	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1783
1784	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
1785	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
1786
1787	/*
1788	* The below check is redundant since we check both TTM and DW for each
1789	* descriptor type we process. However, the error reported by hardware
1790	* may differ hence this is kept commented out but not removed from the code
1791	* if we need to change this in the future.
1792	*
1793	* In our implementation, we would report the descriptor type as invalid,
1794	* while on real hardware it may report descriptor width as invalid.
1795	* The Intel VT-d spec. is not clear which error takes preceedence.
1796	*/
1797	#if 0
1798	/*
1799	* Verify that 128-bit descriptors are not used when operating in scalable mode.
1800	* We don't check this while software writes IQA_REG but defer it until now because
1801	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
1802	* -IS- performed when software writes IQA_REG since it only requires checking against
1803	* immutable hardware features.
1804	*/
1805	if ( fTtm != VTD_TTM_SCALABLE_MODE
1806	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
1807	{ /* likely */ }
1808	else
1809	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, kIqei_InvalidDescriptorWidth);
1810	#endif
1811
1812	/*
1813	* Process requests in FIFO order.
1814	*/
1815	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
1816	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
1817	{
1818	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
1819	uint64_t const uQword0 = puDscQwords[0];
1820	uint64_t const uQword1 = puDscQwords[1];
1821	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
1822	switch (fDscType)
1823	{
1824	case VTD_INV_WAIT_DSC_TYPE:
1825	{
1826	/* Validate descriptor type. */
1827	if ( fTtm == VTD_TTM_LEGACY_MODE
1828	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
1829	{ /* likely */ }
1830	else
1831	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, kIqei_InvalidDescriptorType);
1832
1833	/* Validate reserved bits. */
1834	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
1835	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
1836	: VTD_INV_WAIT_DSC_0_VALID_MASK;
1837	if ( !(uQword0 & ~fValidMask0)
1838	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
1839	{ /* likely */ }
1840	else
1841	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, kIqei_RsvdFieldViolation);
1842
1843	if (fDw == VTD_IQA_REG_DW_256_BIT)
1844	{
1845	if ( !puDscQwords[2]
1846	&& !puDscQwords[3])
1847	{ /* likely */ }
1848	else
1849	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, kIqei_RsvdFieldViolation);
1850	}
1851
1852	/* Perform status write (this must be done prior to generating the completion interrupt). */
1853	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
1854	if (fSw)
1855	{
1856	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
1857	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
1858	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
1859	AssertRC(rc);
1860	}
1861
1862	/* Generate invalidation event interrupt. */
1863	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
1864	if (fIf)
1865	{
1866	DMAR_LOCK(pDevIns, pThisR3);
1867	dmarR3InvEventRaiseInterrupt(pDevIns);
1868	DMAR_UNLOCK(pDevIns, pThisR3);
1869	}
1870
1871	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
1872	break;
1873	}
1874
1875	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
1876	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
1877	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
1878	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
1879	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
1880	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
1881	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
1882	default:
1883	{
1884	/* Stop processing further requests. */
1885	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
1886	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, kIqei_InvalidDescriptorType);
1887	}
1888	}
1889	}
1890	#undef DMAR_IQE_FAULT_RECORD_RET
1891	}
1892
1893
1894	/**
1895	* The invalidation-queue thread.
1896	*
1897	* @returns VBox status code.
1898	* @param pDevIns The IOMMU device instance.
1899	* @param pThread The command thread.
1900	*/
1901	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
1902	{
1903	NOREF(pThread);
1904	LogFlowFunc(("\n"));
1905
1906	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
1907	return VINF_SUCCESS;
1908
1909	/*
1910	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
1911	* This prevents trashing the heap as well as deal with out-of-memory situations
1912	* up-front while starting the VM. It also simplifies the code from having to
1913	* dynamically grow/shrink the allocation based on how software sizes the queue.
1914	* Guests normally don't alter the queue size all the time, but that's not an
1915	* assumption we can make.
1916	*/
1917	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
1918	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
1919	void *pvRequests = RTMemAllocZ(cbMaxQs);
1920	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
1921
1922	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1923	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
1924
1925	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
1926	{
1927	/*
1928	* Sleep until we are woken up.
1929	*/
1930	bool const fSignaled = ASMAtomicXchgBool(&pThis->fInvQueueThreadSignaled, false);
1931	if (!fSignaled)
1932	{
1933	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
1934	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
1935	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
1936	break;
1937	ASMAtomicWriteBool(&pThis->fInvQueueThreadSignaled, false);
1938	}
1939
1940	DMAR_LOCK(pDevIns, pThisR3);
1941	if (dmarInvQueueCanProcessRequests(pThis))
1942	{
1943	uint32_t offQueueHead;
1944	uint32_t offQueueTail;
1945	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
1946	if (!fIsEmpty)
1947	{
1948	/*
1949	* Get the current queue size, descriptor width, queue base address and the
1950	* table translation mode while the lock is still held.
1951	*/
1952	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1953	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
1954	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
1955	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1956	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1957	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
1958
1959	/* Paranoia. */
1960	Assert(cbQueue <= cbMaxQs);
1961	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
1962	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
1963	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
1964	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
1965	Assert(offQueueHead < cbQueue);
1966
1967	/*
1968	* A table translation mode of "reserved" isn't valid for any descriptor type.
1969	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
1970	* but if ESRTPS is support, we will perform a global invalidation when software
1971	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
1972	* So caching TTM while reading all descriptors should not be a problem.
1973	*
1974	* Also, validate the queue tail offset as it's mutable by software.
1975	*/
1976	if ( fTtm != VTD_TTM_RSVD
1977	&& offQueueTail < cbQueue)
1978	{
1979	/* Don't hold the lock while reading (a potentially large amount of) requests */
1980	DMAR_UNLOCK(pDevIns, pThisR3);
1981
1982	int rc;
1983	uint32_t cbRequests;
1984	if (offQueueTail > offQueueHead)
1985	{
1986	/* The requests have not wrapped around, read them in one go. */
1987	cbRequests = offQueueTail - offQueueHead;
1988	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbRequests);
1989	}
1990	else
1991	{
1992	/* The requests have wrapped around, read forward and wrapped-around. */
1993	uint32_t const cbForward = cbQueue - offQueueHead;
1994	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests, pvRequests, cbForward);
1995
1996	uint32_t const cbWrapped = offQueueTail;
1997	if ( RT_SUCCESS(rc)
1998	&& cbWrapped > 0)
1999	{
2000	rc = PDMDevHlpPhysRead(pDevIns, GCPhysRequests + cbForward,
2001	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
2002	}
2003	cbRequests = cbForward + cbWrapped;
2004	}
2005
2006	/* Re-acquire the lock since we need to update device state. */
2007	DMAR_LOCK(pDevIns, pThisR3);
2008
2009	if (RT_SUCCESS(rc))
2010	{
2011	/* Indicate to software we've fetched all requests. */
2012	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
2013
2014	/* Don't hold the lock while processing requests. */
2015	DMAR_UNLOCK(pDevIns, pThisR3);
2016
2017	/* Process all requests. */
2018	Assert(cbRequests <= cbQueue);
2019	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
2020
2021	/*
2022	* We've processed all requests and the lock shouldn't be held at this point.
2023	* Using 'continue' here allows us to skip re-acquiring the lock just to release
2024	* it again before going back to the thread loop. It's a bit ugly but it certainly
2025	* helps with performance.
2026	*/
2027	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2028	continue;
2029	}
2030	else
2031	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, kIqei_FetchDescriptorError);
2032	}
2033	else
2034	{
2035	if (fTtm == VTD_TTM_RSVD)
2036	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, kIqei_InvalidTtm);
2037	else
2038	{
2039	Assert(offQueueTail >= cbQueue);
2040	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, kIqei_InvalidTailPointer);
2041	}
2042	}
2043	}
2044	}
2045	DMAR_UNLOCK(pDevIns, pThisR3);
2046	}
2047
2048	RTMemFree(pvRequests);
2049	pvRequests = NULL;
2050
2051	LogFlowFunc(("Invalidation-queue thread terminating\n"));
2052	return VINF_SUCCESS;
2053	}
2054
2055
2056	/**
2057	* Wakes up the invalidation-queue thread so it can respond to a state
2058	* change.
2059	*
2060	* @returns VBox status code.
2061	* @param pDevIns The IOMMU device instance.
2062	* @param pThread The invalidation-queue thread.
2063	*
2064	* @thread EMT.
2065	*/
2066	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2067	{
2068	RT_NOREF(pThread);
2069	LogFlowFunc(("\n"));
2070	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2071	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
2072	}
2073
2074
2075	/**
2076	* @callback_method_impl{FNDBGFHANDLERDEV}
2077	*/
2078	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2079	{
2080	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2081	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2082	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
2083
2084	/*
2085	* We lock the device to get a consistent register state as it is
2086	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
2087	* ones we care about here) into temporaries and release the lock ASAP.
2088	*
2089	* Order of register being read and outputted is in accordance with the
2090	* spec. for no particular reason.
2091	* See Intel VT-d spec. 10.4 "Register Descriptions".
2092	*/
2093	DMAR_LOCK(pDevIns, pThisR3);
2094
2095	DMARDIAG const enmDiag = pThis->enmDiag;
2096	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
2097	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
2098	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
2099	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
2100	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2101	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
2102	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
2103	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
2104	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
2105	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
2106	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
2107	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
2108	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
2109	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
2110	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
2111	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
2112	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
2113	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
2114	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
2115	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
2116	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2117	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
2118	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
2119	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
2120	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
2121	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
2122	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
2123	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
2124	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
2125	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
2126	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
2127	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
2128	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
2129	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
2130	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
2131	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
2132	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
2133	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
2134
2135	DMAR_UNLOCK(pDevIns, pThisR3);
2136
2137	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
2138	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
2139	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
2140
2141	/*
2142	* Non-verbose output.
2143	*/
2144	if (!fVerbose)
2145	{
2146	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2147	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2148	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2149	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2150	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2151	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2152	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2153	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2154	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2155	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2156	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2157	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2158	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2159	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2160	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2161	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2162	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2163	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2164	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2165	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2166	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2167	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2168	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2169	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2170	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2171	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2172	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2173	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2174	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2175	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2176	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2177	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2178	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2179	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2180	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2181	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2182	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2183	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2184	pHlp->pfnPrintf(pHlp, "\n");
2185	return;
2186	}
2187
2188	/*
2189	* Verbose output.
2190	*/
2191	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2192	{
2193	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
2194	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
2195	}
2196	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2197	{
2198	uint8_t const uSagaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW);
2199	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
2200	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
2201	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
2202	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
2203	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
2204	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
2205	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
2206	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
2207	pHlp->pfnPrintf(pHlp, " SAGAW = %#x (%u bits)\n", uSagaw, vtdCapRegGetSagawBits(uSagaw));
2208	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
2209	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
2210	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
2211	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
2212	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
2213	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
2214	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
2215	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
2216	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
2217	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
2218	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
2219	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
2220	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
2221	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
2222	}
2223	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2224	{
2225	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
2226	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
2227	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
2228	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
2229	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
2230	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
2231	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
2232	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
2233	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
2234	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
2235	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
2236	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
2237	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
2238	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
2239	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
2240	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
2241	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
2242	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
2243	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
2244	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
2245	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
2246	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
2247	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
2248	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
2249	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
2250	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
2251	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
2252	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
2253	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
2254	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
2255	}
2256	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2257	{
2258	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
2259	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Bypass interrupt remapping"
2260	: "Block compatible format interrupts");
2261	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
2262	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
2263	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
2264	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
2265	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2266	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2267	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
2268	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
2269	}
2270	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2271	{
2272	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
2273	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Bypass interrupt remapping"
2274	: "Block compatible format interrupts");
2275	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
2276	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
2277	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
2278	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
2279	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
2280	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
2281	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
2282	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
2283	}
2284	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2285	{
2286	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2287	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
2288	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_RTA));
2289	}
2290	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2291	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2292	{
2293	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
2294	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
2295	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
2296	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
2297	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
2298	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
2299	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
2300	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
2301	}
2302	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2303	{
2304	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
2305	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
2306	}
2307	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2308	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2309	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2310	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2311	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2312	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2313	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2314	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2315	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2316	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2317	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2318	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2319	{
2320	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2321	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
2322	uint8_t const cQueuePages = 1 << fQs;
2323	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
2324	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
2325	}
2326	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2327	{
2328	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
2329	}
2330	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2331	{
2332	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
2333	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
2334	}
2335	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2336	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2337	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2338	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2339	{
2340	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
2341	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
2342	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
2343	}
2344	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2345	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2346	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2347	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2348	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2349	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2350	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2351	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2352	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2353	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2354	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2355	pHlp->pfnPrintf(pHlp, "\n");
2356	}
2357
2358
2359	/**
2360	* Initializes all registers in the DMAR unit.
2361	*
2362	* @param pDevIns The IOMMU device instance.
2363	*/
2364	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
2365	{
2366	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2367
2368	/*
2369	* Wipe all registers (required on reset).
2370	*/
2371	RT_ZERO(pThis->abRegs0);
2372	RT_ZERO(pThis->abRegs1);
2373
2374	/*
2375	* Initialize registers not mutable by software prior to initializing other registers.
2376	*/
2377	/* VER_REG */
2378	{
2379	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
2380	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
2381	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
2382	}
2383
2384	uint8_t const fFlts = 1; /* First-Level translation support. */
2385	uint8_t const fSlts = 1; /* Second-Level translation support. */
2386	uint8_t const fPt = 1; /* Pass-Through support. */
2387	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
2388	uint8_t const fNest = 0; /* Nested translation support. */
2389
2390	/* CAP_REG */
2391	{
2392	uint8_t cGstPhysAddrBits;
2393	uint8_t cGstLinearAddrBits;
2394	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
2395
2396	uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
2397	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
2398	uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
2399	uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
2400	uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
2401	\| ((fSl2mp & fFl1gp) & RT_BIT(1));
2402	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
2403	: X86_PAGE_2M_SHIFT)
2404	- X86_PAGE_4K_SHIFT;
2405	uint8_t const fNd = 2; /* Number of domains supported (0=16, 1=64, 2=256, 3=1K, 4=4K,
2406	5=16K, 6=64K, 7=Reserved). */
2407	uint8_t const fPsi = 1; /* Page selective invalidation. */
2408	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
2409	uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
2410	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
2411	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
2412	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
2413
2414	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
2415	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
2416	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
2417	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
2418	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
2419	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /** @todo Figure out if required when we impl. caching. */
2420	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
2421	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
2422	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
2423	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
2424	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
2425	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
2426	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
2427	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
2428	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
2429	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
2430	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
2431	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
2432	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
2433	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
2434	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
2435	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
2436	}
2437
2438	/* ECAP_REG */
2439	{
2440	uint8_t const fQi = 1; /* Queued-invalidations. */
2441	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
2442	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
2443	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
2444	uint8_t const fSrs = 1; /* Supervisor request support. */
2445	uint8_t const fEim = 1; /* Extended interrupt mode.*/
2446	uint8_t const fAdms = 1; /* Abort DMA mode support. */
2447
2448	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
2449	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
2450	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
2451	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
2452	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
2453	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
2454	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
2455	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
2456	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
2457	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
2458	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
2459	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
2460	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
2461	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, fSmts & fSrs)
2462	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
2463	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
2464	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
2465	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
2466	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
2467	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
2468	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
2469	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
2470	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
2471	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
2472	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
2473	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
2474	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
2475	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
2476	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /** @todo figure out if we should/can support this? */
2477	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
2478	}
2479
2480	/*
2481	* Initialize registers mutable by software.
2482	*/
2483	/* FECTL_REG */
2484	{
2485	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
2486	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
2487	}
2488
2489	/* ICETL_REG */
2490	{
2491	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
2492	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
2493	}
2494
2495	#ifdef VBOX_STRICT
2496	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
2497	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
2498	#endif
2499	}
2500
2501
2502	/**
2503	* @interface_method_impl{PDMDEVREG,pfnReset}
2504	*/
2505	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
2506	{
2507	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2508	LogFlowFunc(("\n"));
2509
2510	DMAR_LOCK(pDevIns, pThisR3);
2511	dmarR3RegsInit(pDevIns);
2512	DMAR_UNLOCK(pDevIns, pThisR3);
2513	}
2514
2515
2516	/**
2517	* @interface_method_impl{PDMDEVREG,pfnDestruct}
2518	*/
2519	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
2520	{
2521	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2522	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2523	LogFlowFunc(("\n"));
2524
2525	DMAR_LOCK(pDevIns, pThisR3);
2526
2527	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
2528	{
2529	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
2530	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
2531	}
2532
2533	DMAR_UNLOCK(pDevIns, pThisR3);
2534	return VINF_SUCCESS;
2535	}
2536
2537
2538	/**
2539	* @interface_method_impl{PDMDEVREG,pfnConstruct}
2540	*/
2541	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
2542	{
2543	RT_NOREF(pCfg);
2544
2545	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2546	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
2547	pThisR3->pDevInsR3 = pDevIns;
2548
2549	LogFlowFunc(("iInstance=%d\n", iInstance));
2550	NOREF(iInstance);
2551
2552	/*
2553	* Register the IOMMU with PDM.
2554	*/
2555	PDMIOMMUREGR3 IommuReg;
2556	RT_ZERO(IommuReg);
2557	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2558	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2559	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2560	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2561	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2562	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
2563	if (RT_FAILURE(rc))
2564	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
2565	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
2566	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2567	N_("IOMMU helper version mismatch; got %#x expected %#x"),
2568	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
2569	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
2570	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
2571	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
2572	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
2573	/*
2574	* Use PDM's critical section (via helpers) for the IOMMU device.
2575	*/
2576	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2577	AssertRCReturn(rc, rc);
2578
2579	/*
2580	* Initialize PCI configuration registers.
2581	*/
2582	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2583	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
2584
2585	/* Header. */
2586	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2587	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2588	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
2589	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
2590	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
2591	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
2592	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
2593	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
2594
2595	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
2596	PDMPciDevSetStatus(pPciDev, 0);
2597	PDMPciDevSetCapabilityList(pPciDev, 0);
2598
2599	/** @todo VTBAR at 0x180? */
2600
2601	/*
2602	* Register the PCI function with PDM.
2603	*/
2604	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
2605	AssertLogRelRCReturn(rc, rc);
2606
2607	/** @todo Register MSI but what's the MSI capability offset? */
2608	#if 0
2609	/*
2610	* Register MSI support for the PCI device.
2611	* This must be done -after- registering it as a PCI device!
2612	*/
2613	#endif
2614
2615	/*
2616	* Register MMIO region.
2617	*/
2618	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
2619	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
2620	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
2621	&pThis->hMmio);
2622	AssertLogRelRCReturn(rc, rc);
2623
2624	/*
2625	* Register debugger info items.
2626	*/
2627	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
2628	AssertLogRelRCReturn(rc, rc);
2629
2630	#ifdef VBOX_WITH_STATISTICS
2631	/*
2632	* Statistics.
2633	*/
2634	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
2635	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
2636
2637	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
2638	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
2639
2640	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapR3, STAMTYPE_COUNTER, "R3/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in R3.");
2641	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRZ, STAMTYPE_COUNTER, "RZ/MsiRemap", STAMUNIT_OCCURENCES, "Number of interrupt remap requests in RZ.");
2642
2643	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
2644	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
2645
2646	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
2647	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
2648
2649	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
2650	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
2651
2652	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
2653	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
2654
2655	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
2656	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
2657	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
2658	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
2659	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
2660	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
2661	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
2662	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
2663	#endif
2664
2665	/*
2666	* Initialize registers.
2667	*/
2668	dmarR3RegsInit(pDevIns);
2669
2670	/*
2671	* Create invalidation-queue thread and semaphore.
2672	*/
2673	char szInvQueueThread[32];
2674	RT_ZERO(szInvQueueThread);
2675	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
2676	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
2677	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
2678	AssertLogRelRCReturn(rc, rc);
2679
2680	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
2681	AssertLogRelRCReturn(rc, rc);
2682
2683	/*
2684	* Log some of the features exposed to software.
2685	*/
2686	uint32_t const uVerReg = pThis->uVerReg;
2687	uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
2688	uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW));
2689	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
2690	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
2691	LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
2692	DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
2693	pThis->fCapReg, pThis->fExtCapReg, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
2694
2695	return VINF_SUCCESS;
2696	}
2697
2698	#else
2699
2700	/**
2701	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
2702	*/
2703	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
2704	{
2705	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
2706	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2707	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
2708	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
2709
2710	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
2711	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
2712	AssertRCReturn(rc, rc);
2713
2714	/* Set up the MMIO RZ handlers. */
2715	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
2716	AssertRCReturn(rc, rc);
2717
2718	/* Set up the IOMMU RZ callbacks. */
2719	PDMIOMMUREGCC IommuReg;
2720	RT_ZERO(IommuReg);
2721	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
2722	IommuReg.idxIommu = pThis->idxIommu;
2723	IommuReg.pfnMemAccess = iommuIntelMemAccess;
2724	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
2725	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
2726	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
2727
2728	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
2729	AssertRCReturn(rc, rc);
2730	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
2731	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2732	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
2733	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock, VERR_INVALID_POINTER);
2734	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock, VERR_INVALID_POINTER);
2735	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner, VERR_INVALID_POINTER);
2736	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi, VERR_INVALID_POINTER);
2737
2738	return VINF_SUCCESS;
2739	}
2740
2741	#endif
2742
2743
2744	/**
2745	* The device registration structure.
2746	*/
2747	PDMDEVREG const g_DeviceIommuIntel =
2748	{
2749	/* .u32Version = */ PDM_DEVREG_VERSION,
2750	/* .uReserved0 = */ 0,
2751	/* .szName = */ "iommu-intel",
2752	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
2753	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
2754	/* .cMaxInstances = */ 1,
2755	/* .uSharedVersion = */ 42,
2756	/* .cbInstanceShared = */ sizeof(DMAR),
2757	/* .cbInstanceCC = */ sizeof(DMARCC),
2758	/* .cbInstanceRC = */ sizeof(DMARRC),
2759	/* .cMaxPciDevices = */ 1,
2760	/* .cMaxMsixVectors = */ 0,
2761	/* .pszDescription = */ "IOMMU (Intel)",
2762	#if defined(IN_RING3)
2763	/* .pszRCMod = */ "VBoxDDRC.rc",
2764	/* .pszR0Mod = */ "VBoxDDR0.r0",
2765	/* .pfnConstruct = */ iommuIntelR3Construct,
2766	/* .pfnDestruct = */ iommuIntelR3Destruct,
2767	/* .pfnRelocate = */ NULL,
2768	/* .pfnMemSetup = */ NULL,
2769	/* .pfnPowerOn = */ NULL,
2770	/* .pfnReset = */ iommuIntelR3Reset,
2771	/* .pfnSuspend = */ NULL,
2772	/* .pfnResume = */ NULL,
2773	/* .pfnAttach = */ NULL,
2774	/* .pfnDetach = */ NULL,
2775	/* .pfnQueryInterface = */ NULL,
2776	/* .pfnInitComplete = */ NULL,
2777	/* .pfnPowerOff = */ NULL,
2778	/* .pfnSoftReset = */ NULL,
2779	/* .pfnReserved0 = */ NULL,
2780	/* .pfnReserved1 = */ NULL,
2781	/* .pfnReserved2 = */ NULL,
2782	/* .pfnReserved3 = */ NULL,
2783	/* .pfnReserved4 = */ NULL,
2784	/* .pfnReserved5 = */ NULL,
2785	/* .pfnReserved6 = */ NULL,
2786	/* .pfnReserved7 = */ NULL,
2787	#elif defined(IN_RING0)
2788	/* .pfnEarlyConstruct = */ NULL,
2789	/* .pfnConstruct = */ iommuIntelRZConstruct,
2790	/* .pfnDestruct = */ NULL,
2791	/* .pfnFinalDestruct = */ NULL,
2792	/* .pfnRequest = */ NULL,
2793	/* .pfnReserved0 = */ NULL,
2794	/* .pfnReserved1 = */ NULL,
2795	/* .pfnReserved2 = */ NULL,
2796	/* .pfnReserved3 = */ NULL,
2797	/* .pfnReserved4 = */ NULL,
2798	/* .pfnReserved5 = */ NULL,
2799	/* .pfnReserved6 = */ NULL,
2800	/* .pfnReserved7 = */ NULL,
2801	#elif defined(IN_RC)
2802	/* .pfnConstruct = */ iommuIntelRZConstruct,
2803	/* .pfnReserved0 = */ NULL,
2804	/* .pfnReserved1 = */ NULL,
2805	/* .pfnReserved2 = */ NULL,
2806	/* .pfnReserved3 = */ NULL,
2807	/* .pfnReserved4 = */ NULL,
2808	/* .pfnReserved5 = */ NULL,
2809	/* .pfnReserved6 = */ NULL,
2810	/* .pfnReserved7 = */ NULL,
2811	#else
2812	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
2813	#endif
2814	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
2815	};
2816
2817	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
2818

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 88859

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