VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89238

Last change on this file since 89238 was 89238, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Address translation, WIP.
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1/* $Id: DevIommuIntel.cpp 89238 2021-05-24 13:53:16Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - Intel implementation.
4 */
5
6/*
7 * Copyright (C) 2021 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include "VBoxDD.h"
24#include "DevIommuIntel.h"
25
26#include <iprt/mem.h>
27#include <iprt/string.h>
28
29
30/*********************************************************************************************************************************
31* Defined Constants And Macros *
32*********************************************************************************************************************************/
33/** Gets the low uint32_t of a uint64_t or something equivalent.
34 *
35 * This is suitable for casting constants outside code (since RT_LO_U32 can't be
36 * used as it asserts for correctness when compiling on certain compilers). */
37#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39/** Gets the high uint32_t of a uint64_t or something equivalent.
40 *
41 * This is suitable for casting constants outside code (since RT_HI_U32 can't be
42 * used as it asserts for correctness when compiling on certain compilers). */
43#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45/** Asserts MMIO access' offset and size are valid or returns appropriate error
46 * code suitable for returning from MMIO access handlers. */
47#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48 do { \
49 AssertReturn((a_cb) == 4 || (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50 AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51 } while (0)
52
53/** Checks if the MMIO offset is valid. */
54#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55 || (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59 do { \
60 if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61 { /* likely */ } \
62 else \
63 return (a_rcBusy); \
64 } while (0)
65
66/** Acquires the DMAR lock (not expected to fail). */
67#ifdef IN_RING3
68# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69#else
70# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71 do { \
72 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73 AssertRC(rcLock); \
74 } while (0)
75#endif
76
77/** Release the DMAR lock. */
78#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80/** Asserts that the calling thread owns the DMAR lock. */
81#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82 do { \
83 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84 RT_NOREF1(a_pThisCC); \
85 } while (0)
86
87/** Asserts that the calling thread does not own the DMAR lock. */
88#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89 do { \
90 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91 RT_NOREF1(a_pThisCC); \
92 } while (0)
93
94/** The number of fault recording registers our implementation supports.
95 * Normal guest operation shouldn't trigger faults anyway, so we only support the
96 * minimum number of registers (which is 1).
97 *
98 * See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101/** Offset of first register in group 0. */
102#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
103/** Offset of last register in group 0 (inclusive). */
104#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
105/** Last valid offset in group 0 (exclusive). */
106#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
107/** Size of the group 0 (in bytes). */
108#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
109/**< Implementation-specific MMIO offset of IVA_REG. */
110#define DMAR_MMIO_OFF_IVA_REG 0xe50
111/**< Implementation-specific MMIO offset of IOTLB_REG. */
112#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
113/**< Implementation-specific MMIO offset of FRCD_LO_REG. */
114#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
115/**< Implementation-specific MMIO offset of FRCD_HI_REG. */
116#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
117AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
118
119/** Offset of first register in group 1. */
120#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
121/** Offset of last register in group 1 (inclusive). */
122#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
123/** Last valid offset in group 1 (exclusive). */
124#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
125/** Size of the group 1 (in bytes). */
126#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
127
128/** DMAR implementation's major version number (exposed to software).
129 * We report 6 as the major version since we support queued-invalidations as
130 * software may make assumptions based on that.
131 *
132 * See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
133#define DMAR_VER_MAJOR 6
134/** DMAR implementation's minor version number (exposed to software). */
135#define DMAR_VER_MINOR 0
136
137/** Release log prefix string. */
138#define DMAR_LOG_PFX "Intel-IOMMU"
139/** The current saved state version. */
140#define DMAR_SAVED_STATE_VERSION 1
141
142
143/*********************************************************************************************************************************
144* Structures and Typedefs *
145*********************************************************************************************************************************/
146/**
147 * DMAR error diagnostics.
148 * Sorted alphabetically so it's easier to add and locate items, no other reason.
149 *
150 * @note Members of this enum are used as array indices, so no gaps in enum
151 * values are not allowed. Update g_apszDmarDiagDesc when you modify
152 * fields in this enum.
153 */
154typedef enum
155{
156 /* No error, this must be zero! */
157 kDmarDiag_None = 0,
158
159 /* Address Translation Faults. */
160 kDmarDiag_Atf_Rta_1_1,
161 kDmarDiag_Atf_Rta_1_2,
162 kDmarDiag_Atf_Rta_1_3,
163
164 /* CCMD_REG faults. */
165 kDmarDiag_CcmdReg_NotSupported,
166 kDmarDiag_CcmdReg_Qi_Enabled,
167 kDmarDiag_CcmdReg_Ttm_Invalid,
168
169 /* IQA_REG faults. */
170 kDmarDiag_IqaReg_Dsc_Fetch_Error,
171 kDmarDiag_IqaReg_Dw_128_Invalid,
172 kDmarDiag_IqaReg_Dw_256_Invalid,
173
174 /* Invalidation Queue Error Info. */
175 kDmarDiag_Iqei_Dsc_Type_Invalid,
176 kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
177 kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
178 kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
179 kDmarDiag_Iqei_Ttm_Rsvd,
180
181 /* IQT_REG faults. */
182 kDmarDiag_IqtReg_Qt_Invalid,
183 kDmarDiag_IqtReg_Qt_NotAligned,
184
185 /* Compatibility Format Interrupt Faults. */
186 kDmarDiag_Ir_Cfi_Blocked,
187
188 /* Remappable Format Interrupt Faults. */
189 kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
190 kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
191 kDmarDiag_Ir_Rfi_Irte_Not_Present,
192 kDmarDiag_Ir_Rfi_Irte_Read_Failed,
193 kDmarDiag_Ir_Rfi_Irte_Rsvd,
194 kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
195 kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
196 kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
197 kDmarDiag_Ir_Rfi_Rsvd,
198
199 /* Member for determining array index limit. */
200 kDmarDiag_End,
201
202 /* Usual 32-bit type size hack. */
203 kDmarDiag_32Bit_Hack = 0x7fffffff
204} DMARDIAG;
205AssertCompileSize(DMARDIAG, 4);
206
207/** DMAR diagnostic enum description expansion.
208 * The below construct ensures typos in the input to this macro are caught
209 * during compile time. */
210#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
211
212/** DMAR diagnostics description for members in DMARDIAG. */
213static const char *const g_apszDmarDiagDesc[] =
214{
215 DMARDIAG_DESC(None ),
216 DMARDIAG_DESC(Atf_Rta_1_1 ),
217 DMARDIAG_DESC(Atf_Rta_1_2 ),
218 DMARDIAG_DESC(Atf_Rta_1_3 ),
219 DMARDIAG_DESC(CcmdReg_NotSupported ),
220 DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
221 DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
222 DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
223 DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
224 DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
225 DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
226 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
227 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
228 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
229 DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
230 DMARDIAG_DESC(IqtReg_Qt_Invalid ),
231 DMARDIAG_DESC(IqtReg_Qt_NotAligned ),
232 DMARDIAG_DESC(Ir_Cfi_Blocked ),
233 DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
234 DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
235 DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
236 DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
237 DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
238 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
239 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
240 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
241 DMARDIAG_DESC(Ir_Rfi_Rsvd ),
242 /* kDmarDiag_End */
243};
244AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
245#undef DMARDIAG_DESC
246
247/**
248 * The shared DMAR device state.
249 */
250typedef struct DMAR
251{
252 /** IOMMU device index. */
253 uint32_t idxIommu;
254 /** DMAR magic. */
255 uint32_t u32Magic;
256
257 /** Registers (group 0). */
258 uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
259 /** Registers (group 1). */
260 uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
261
262 /** @name Lazily activated registers.
263 * These are the active values for lazily activated registers. Software is free to
264 * modify the actual register values while remapping/translation is enabled but they
265 * take effect only when explicitly signaled by software, hence we need to hold the
266 * active values separately.
267 * @{ */
268 /** Currently active IRTA_REG. */
269 uint64_t uIrtaReg;
270 /** Currently active RTADDR_REG. */
271 uint64_t uRtaddrReg;
272 /** @} */
273
274 /** @name Register copies for a tiny bit faster and more convenient access.
275 * @{ */
276 /** Copy of VER_REG. */
277 uint8_t uVerReg;
278 /** Alignment. */
279 uint8_t abPadding[7];
280 /** Copy of CAP_REG. */
281 uint64_t fCapReg;
282 /** Copy of ECAP_REG. */
283 uint64_t fExtCapReg;
284 /** @} */
285
286 /** The event semaphore the invalidation-queue thread waits on. */
287 SUPSEMEVENT hEvtInvQueue;
288 /** Padding. */
289 uint32_t uPadding0;
290 /** Error diagnostic. */
291 DMARDIAG enmDiag;
292 /** The MMIO handle. */
293 IOMMMIOHANDLE hMmio;
294
295#ifdef VBOX_WITH_STATISTICS
296 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
297 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
298 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
299 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
300
301 STAMCOUNTER StatMsiRemapCfiR3; /**< Number of compatibility-format interrupts remap requests in R3. */
302 STAMCOUNTER StatMsiRemapCfiRZ; /**< Number of compatibility-format interrupts remap requests in RZ. */
303 STAMCOUNTER StatMsiRemapRfiR3; /**< Number of remappable-format interrupts remap requests in R3. */
304 STAMCOUNTER StatMsiRemapRfiRZ; /**< Number of remappable-format interrupts remap requests in RZ. */
305
306 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
307 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
308 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
309 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
310
311 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
312 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
313 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
314 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
315
316 STAMCOUNTER StatCcInvDsc; /**< Number of Context-cache descriptors processed. */
317 STAMCOUNTER StatIotlbInvDsc; /**< Number of IOTLB descriptors processed. */
318 STAMCOUNTER StatDevtlbInvDsc; /**< Number of Device-TLB descriptors processed. */
319 STAMCOUNTER StatIecInvDsc; /**< Number of Interrupt-Entry cache descriptors processed. */
320 STAMCOUNTER StatInvWaitDsc; /**< Number of Invalidation wait descriptors processed. */
321 STAMCOUNTER StatPasidIotlbInvDsc; /**< Number of PASID-based IOTLB descriptors processed. */
322 STAMCOUNTER StatPasidCacheInvDsc; /**< Number of PASID-cache descriptors processed. */
323 STAMCOUNTER StatPasidDevtlbInvDsc; /**< Number of PASID-based device-TLB descriptors processed. */
324#endif
325} DMAR;
326/** Pointer to the DMAR device state. */
327typedef DMAR *PDMAR;
328/** Pointer to the const DMAR device state. */
329typedef DMAR const *PCDMAR;
330AssertCompileMemberAlignment(DMAR, abRegs0, 8);
331AssertCompileMemberAlignment(DMAR, abRegs1, 8);
332
333/**
334 * The ring-3 DMAR device state.
335 */
336typedef struct DMARR3
337{
338 /** Device instance. */
339 PPDMDEVINSR3 pDevInsR3;
340 /** The IOMMU helper. */
341 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
342 /** The invalidation-queue thread. */
343 R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
344} DMARR3;
345/** Pointer to the ring-3 DMAR device state. */
346typedef DMARR3 *PDMARR3;
347/** Pointer to the const ring-3 DMAR device state. */
348typedef DMARR3 const *PCDMARR3;
349
350/**
351 * The ring-0 DMAR device state.
352 */
353typedef struct DMARR0
354{
355 /** Device instance. */
356 PPDMDEVINSR0 pDevInsR0;
357 /** The IOMMU helper. */
358 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
359} DMARR0;
360/** Pointer to the ring-0 IOMMU device state. */
361typedef DMARR0 *PDMARR0;
362/** Pointer to the const ring-0 IOMMU device state. */
363typedef DMARR0 const *PCDMARR0;
364
365/**
366 * The raw-mode DMAR device state.
367 */
368typedef struct DMARRC
369{
370 /** Device instance. */
371 PPDMDEVINSRC pDevInsRC;
372 /** The IOMMU helper. */
373 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
374} DMARRC;
375/** Pointer to the raw-mode DMAR device state. */
376typedef DMARRC *PDMARRC;
377/** Pointer to the const raw-mode DMAR device state. */
378typedef DMARRC const *PCIDMARRC;
379
380/** The DMAR device state for the current context. */
381typedef CTX_SUFF(DMAR) DMARCC;
382/** Pointer to the DMAR device state for the current context. */
383typedef CTX_SUFF(PDMAR) PDMARCC;
384/** Pointer to the const DMAR device state for the current context. */
385typedef CTX_SUFF(PDMAR) const PCDMARCC;
386
387/**
388 * Type of DMAR originated events that generate interrupts.
389 */
390typedef enum DMAREVENTTYPE
391{
392 /** Invalidation completion event. */
393 DMAREVENTTYPE_INV_COMPLETE = 0,
394 /** Fault event. */
395 DMAREVENTTYPE_FAULT
396} DMAREVENTTYPE;
397
398
399/**
400 * DMA address map.
401 * This structure holds information about a DMA address translation.
402 */
403typedef struct DMARADDRMAP
404{
405 /** The device ID (bus, device, function). */
406 uint16_t idDevice;
407 uint16_t uPadding0;
408 /** The DMA remapping operation request type. */
409 VTDREQTYPE enmReqType;
410 /** The DMA address being accessed. */
411 uint64_t uDmaAddr;
412 /** The size of the DMA access (in bytes). */
413 size_t cbDma;
414 /** The translated system-physical address (HPA). */
415 RTGCPHYS GCPhysSpa;
416 /** The size of the contiguous translated region (in bytes). */
417 size_t cbContiguous;
418} DMARADDRMAP;
419/** Pointer to a DMA address map. */
420typedef DMARADDRMAP *PDMARADDRMAP;
421/** Pointer to a const DMA address map. */
422typedef DMARADDRMAP const *PCDMARADDRMAP;
423
424
425/*********************************************************************************************************************************
426* Global Variables *
427*********************************************************************************************************************************/
428/**
429 * Read-write masks for DMAR registers (group 0).
430 */
431static uint32_t const g_au32RwMasks0[] =
432{
433 /* Offset Register Low High */
434 /* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
435 /* 0x004 Reserved */ 0,
436 /* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
437 /* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
438 /* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
439 /* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
440 /* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
441 /* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
442 /* 0x030 Reserved */ 0,
443 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
444 /* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
445 /* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
446 /* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
447 /* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
448 /* 0x048 Reserved */ 0, 0,
449 /* 0x050 Reserved */ 0, 0,
450 /* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
451 /* 0x060 Reserved */ 0,
452 /* 0x064 PMEN_REG */ 0, /* RO as we don't support PLMR and PHMR. */
453 /* 0x068 PLMBASE_REG */ 0, /* RO as we don't support PLMR. */
454 /* 0x06c PLMLIMIT_REG */ 0, /* RO as we don't support PLMR. */
455 /* 0x070 PHMBASE_REG */ 0, 0, /* RO as we don't support PHMR. */
456 /* 0x078 PHMLIMIT_REG */ 0, 0, /* RO as we don't support PHMR. */
457 /* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
458 /* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
459 /* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
460 /* 0x098 Reserved */ 0,
461 /* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
462 /* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
463 /* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
464 /* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
465 /* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
466 /* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
467 /* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
468 /* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
469 /* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
470 /* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
471 /* 0x0d8 Reserved */ 0,
472 /* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
473 /* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
474 /* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
475 /* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
476 /* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
477 /* 0x0f0 Reserved */ 0, 0,
478 /* 0x0f8 Reserved */ 0, 0,
479 /* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
480 /* 0x108 MTRRDEF_REG */ 0, 0, /* RO as we don't support MTS. */
481 /* 0x110 Reserved */ 0, 0,
482 /* 0x118 Reserved */ 0, 0,
483 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0, /* RO as we don't support MTS. */
484 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
485 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
486 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
487 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
488 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
489 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
490 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
491 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
492 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
493 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
494 /* 0x178 Reserved */ 0, 0,
495 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0, /* RO as we don't support MTS. */
496 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
497 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
498 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
499 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
500 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
501 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
502 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
503 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
504 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
505 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
506 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
507 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
508 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
509 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
510 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
511 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
512 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
513 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
514 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
515};
516AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
517
518/**
519 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
520 */
521static uint32_t const g_au32Rw1cMasks0[] =
522{
523 /* Offset Register Low High */
524 /* 0x000 VER_REG */ 0,
525 /* 0x004 Reserved */ 0,
526 /* 0x008 CAP_REG */ 0, 0,
527 /* 0x010 ECAP_REG */ 0, 0,
528 /* 0x018 GCMD_REG */ 0,
529 /* 0x01c GSTS_REG */ 0,
530 /* 0x020 RTADDR_REG */ 0, 0,
531 /* 0x028 CCMD_REG */ 0, 0,
532 /* 0x030 Reserved */ 0,
533 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
534 /* 0x038 FECTL_REG */ 0,
535 /* 0x03c FEDATA_REG */ 0,
536 /* 0x040 FEADDR_REG */ 0,
537 /* 0x044 FEUADDR_REG */ 0,
538 /* 0x048 Reserved */ 0, 0,
539 /* 0x050 Reserved */ 0, 0,
540 /* 0x058 AFLOG_REG */ 0, 0,
541 /* 0x060 Reserved */ 0,
542 /* 0x064 PMEN_REG */ 0,
543 /* 0x068 PLMBASE_REG */ 0,
544 /* 0x06c PLMLIMIT_REG */ 0,
545 /* 0x070 PHMBASE_REG */ 0, 0,
546 /* 0x078 PHMLIMIT_REG */ 0, 0,
547 /* 0x080 IQH_REG */ 0, 0,
548 /* 0x088 IQT_REG */ 0, 0,
549 /* 0x090 IQA_REG */ 0, 0,
550 /* 0x098 Reserved */ 0,
551 /* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
552 /* 0x0a0 IECTL_REG */ 0,
553 /* 0x0a4 IEDATA_REG */ 0,
554 /* 0x0a8 IEADDR_REG */ 0,
555 /* 0x0ac IEUADDR_REG */ 0,
556 /* 0x0b0 IQERCD_REG */ 0, 0,
557 /* 0x0b8 IRTA_REG */ 0, 0,
558 /* 0x0c0 PQH_REG */ 0, 0,
559 /* 0x0c8 PQT_REG */ 0, 0,
560 /* 0x0d0 PQA_REG */ 0, 0,
561 /* 0x0d8 Reserved */ 0,
562 /* 0x0dc PRS_REG */ 0,
563 /* 0x0e0 PECTL_REG */ 0,
564 /* 0x0e4 PEDATA_REG */ 0,
565 /* 0x0e8 PEADDR_REG */ 0,
566 /* 0x0ec PEUADDR_REG */ 0,
567 /* 0x0f0 Reserved */ 0, 0,
568 /* 0x0f8 Reserved */ 0, 0,
569 /* 0x100 MTRRCAP_REG */ 0, 0,
570 /* 0x108 MTRRDEF_REG */ 0, 0,
571 /* 0x110 Reserved */ 0, 0,
572 /* 0x118 Reserved */ 0, 0,
573 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
574 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
575 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
576 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
577 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
578 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
579 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
580 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
581 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
582 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
583 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
584 /* 0x178 Reserved */ 0, 0,
585 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
586 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
587 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
588 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
589 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
590 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
591 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
592 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
593 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
594 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
595 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
596 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
597 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
598 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
599 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
600 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
601 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
602 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
603 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
604 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
605};
606AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
607
608/**
609 * Read-write masks for DMAR registers (group 1).
610 */
611static uint32_t const g_au32RwMasks1[] =
612{
613 /* Offset Register Low High */
614 /* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
615 /* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
616 /* 0xe10 VCMD_REG */ 0, 0, /* RO: VCS not supported. */
617 /* 0xe18 VCMDRSVD_REG */ 0, 0,
618 /* 0xe20 VCRSP_REG */ 0, 0, /* RO: VCS not supported. */
619 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
620 /* 0xe30 Reserved */ 0, 0,
621 /* 0xe38 Reserved */ 0, 0,
622 /* 0xe40 Reserved */ 0, 0,
623 /* 0xe48 Reserved */ 0, 0,
624 /* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
625 /* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
626 /* 0xe60 Reserved */ 0, 0,
627 /* 0xe68 Reserved */ 0, 0,
628 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
629 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
630};
631AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
632AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
633
634/**
635 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
636 */
637static uint32_t const g_au32Rw1cMasks1[] =
638{
639 /* Offset Register Low High */
640 /* 0xe00 VCCAP_REG */ 0, 0,
641 /* 0xe08 VCMD_EO_REG */ 0, 0,
642 /* 0xe10 VCMD_REG */ 0, 0,
643 /* 0xe18 VCMDRSVD_REG */ 0, 0,
644 /* 0xe20 VCRSP_REG */ 0, 0,
645 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
646 /* 0xe30 Reserved */ 0, 0,
647 /* 0xe38 Reserved */ 0, 0,
648 /* 0xe40 Reserved */ 0, 0,
649 /* 0xe48 Reserved */ 0, 0,
650 /* 0xe50 IVA_REG */ 0, 0,
651 /* 0xe58 IOTLB_REG */ 0, 0,
652 /* 0xe60 Reserved */ 0, 0,
653 /* 0xe68 Reserved */ 0, 0,
654 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
655 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
656};
657AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
658
659/** Array of RW masks for each register group. */
660static uint8_t const *g_apbRwMasks[] = { (uint8_t *)&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
661
662/** Array of RW1C masks for each register group. */
663static uint8_t const *g_apbRw1cMasks[] = { (uint8_t *)&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
664
665/* Masks arrays must be identical in size (even bounds checking code assumes this). */
666AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
667
668
669#ifndef VBOX_DEVICE_STRUCT_TESTCASE
670/** @todo Add IOMMU struct size/alignment verification, see
671 * Devices/testcase/Makefile.kmk and
672 * Devices/testcase/tstDeviceStructSize[RC].cpp */
673
674/**
675 * Returns the number of supported adjusted guest-address width (SAGAW) in bits
676 * given a CAP_REG.SAGAW value.
677 *
678 * @returns Number of SAGAW bits.
679 * @param uSagaw The CAP_REG.SAGAW value.
680 */
681static uint8_t vtdCapRegGetSagawBits(uint8_t uSagaw)
682{
683 if (RT_LIKELY(uSagaw > 0 && uSagaw < 4))
684 return 30 + (uSagaw * 9);
685 return 0;
686}
687
688
689/**
690 * Returns the supported adjusted guest-address width (SAGAW) given the maximum
691 * guest address width (MGAW).
692 *
693 * @returns The CAP_REG.SAGAW value.
694 * @param uMgaw The CAP_REG.MGAW value.
695 */
696static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
697{
698 switch (uMgaw + 1)
699 {
700 case 39: return 1;
701 case 48: return 2;
702 case 57: return 3;
703 }
704 return 0;
705}
706
707
708/**
709 * Returns whether the interrupt remapping (IR) fault is qualified or not.
710 *
711 * @returns @c true if qualified, @c false otherwise.
712 * @param enmIrFault The interrupt remapping fault condition.
713 */
714static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
715{
716 switch (enmIrFault)
717 {
718 case VTDIRFAULT_IRTE_NOT_PRESENT:
719 case VTDIRFAULT_IRTE_PRESENT_RSVD:
720 case VTDIRFAULT_IRTE_PRESENT_INVALID:
721 case VTDIRFAULT_PID_READ_FAILED:
722 case VTDIRFAULT_PID_RSVD:
723 return true;
724 default:
725 return false;
726 }
727}
728
729
730/**
731 * Returns table translation mode's descriptive name.
732 *
733 * @returns The descriptive name.
734 * @param uTtm The RTADDR_REG.TTM value.
735 */
736static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
737{
738 Assert(!(uTtm & 3));
739 static const char* s_apszTtmNames[] =
740 {
741 "Legacy Mode",
742 "Scalable Mode",
743 "Reserved",
744 "Abort-DMA Mode"
745 };
746 return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
747}
748
749
750/**
751 * Gets the index of the group the register belongs to given its MMIO offset.
752 *
753 * @returns The group index.
754 * @param offReg The MMIO offset of the register.
755 * @param cbReg The size of the access being made (for bounds checking on
756 * debug builds).
757 */
758DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
759{
760 uint16_t const offLast = offReg + cbReg - 1;
761 AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
762 AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
763 return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
764}
765
766
767/**
768 * Gets the group the register belongs to given its MMIO offset.
769 *
770 * @returns Pointer to the first element of the register group.
771 * @param pThis The shared DMAR device state.
772 * @param offReg The MMIO offset of the register.
773 * @param cbReg The size of the access being made (for bounds checking on
774 * debug builds).
775 * @param pIdxGroup Where to store the index of the register group the register
776 * belongs to.
777 */
778DECLINLINE(uint8_t *) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
779{
780 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
781 uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
782 return apbRegs[*pIdxGroup];
783}
784
785
786/**
787 * Const/read-only version of dmarRegGetGroup.
788 *
789 * @copydoc dmarRegGetGroup
790 */
791DECLINLINE(uint8_t const*) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
792{
793 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
794 uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
795 return apbRegs[*pIdxGroup];
796}
797
798
799/**
800 * Writes a 32-bit register with the exactly the supplied value.
801 *
802 * @param pThis The shared DMAR device state.
803 * @param offReg The MMIO offset of the register.
804 * @param uReg The 32-bit value to write.
805 */
806static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
807{
808 uint8_t idxGroup;
809 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
810 NOREF(idxGroup);
811 *(uint32_t *)(pabRegs + offReg) = uReg;
812}
813
814
815/**
816 * Writes a 64-bit register with the exactly the supplied value.
817 *
818 * @param pThis The shared DMAR device state.
819 * @param offReg The MMIO offset of the register.
820 * @param uReg The 64-bit value to write.
821 */
822static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
823{
824 uint8_t idxGroup;
825 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
826 NOREF(idxGroup);
827 *(uint64_t *)(pabRegs + offReg) = uReg;
828}
829
830
831/**
832 * Reads a 32-bit register with exactly the value it contains.
833 *
834 * @returns The raw register value.
835 * @param pThis The shared DMAR device state.
836 * @param offReg The MMIO offset of the register.
837 */
838static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
839{
840 uint8_t idxGroup;
841 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
842 NOREF(idxGroup);
843 return *(uint32_t *)(pabRegs + offReg);
844}
845
846
847/**
848 * Reads a 64-bit register with exactly the value it contains.
849 *
850 * @returns The raw register value.
851 * @param pThis The shared DMAR device state.
852 * @param offReg The MMIO offset of the register.
853 */
854static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
855{
856 uint8_t idxGroup;
857 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
858 NOREF(idxGroup);
859 return *(uint64_t *)(pabRegs + offReg);
860}
861
862
863/**
864 * Reads a 32-bit register with exactly the value it contains along with their
865 * corresponding masks
866 *
867 * @param pThis The shared DMAR device state.
868 * @param offReg The MMIO offset of the register.
869 * @param puReg Where to store the raw 32-bit register value.
870 * @param pfRwMask Where to store the RW mask corresponding to this register.
871 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
872 */
873static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask)
874{
875 uint8_t idxGroup;
876 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
877 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
878 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
879 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
880 *puReg = *(uint32_t *)(pabRegs + offReg);
881 *pfRwMask = *(uint32_t *)(pabRwMasks + offReg);
882 *pfRw1cMask = *(uint32_t *)(pabRw1cMasks + offReg);
883}
884
885
886/**
887 * Reads a 64-bit register with exactly the value it contains along with their
888 * corresponding masks.
889 *
890 * @param pThis The shared DMAR device state.
891 * @param offReg The MMIO offset of the register.
892 * @param puReg Where to store the raw 64-bit register value.
893 * @param pfRwMask Where to store the RW mask corresponding to this register.
894 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
895 */
896static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask)
897{
898 uint8_t idxGroup;
899 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
900 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
901 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
902 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
903 *puReg = *(uint64_t *)(pabRegs + offReg);
904 *pfRwMask = *(uint64_t *)(pabRwMasks + offReg);
905 *pfRw1cMask = *(uint64_t *)(pabRw1cMasks + offReg);
906}
907
908
909/**
910 * Writes a 32-bit register as it would be when written by software.
911 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
912 *
913 * @returns The value that's actually written to the register.
914 * @param pThis The shared DMAR device state.
915 * @param offReg The MMIO offset of the register.
916 * @param uReg The 32-bit value to write.
917 * @param puPrev Where to store the register value prior to writing.
918 */
919static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
920{
921 /* Read current value from the 32-bit register. */
922 uint32_t uCurReg;
923 uint32_t fRwMask;
924 uint32_t fRw1cMask;
925 dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
926 *puPrev = uCurReg;
927
928 uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
929 uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
930 uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
931 uint32_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
932
933 /* Write new value to the 32-bit register. */
934 dmarRegWriteRaw32(pThis, offReg, uNewReg);
935 return uNewReg;
936}
937
938
939/**
940 * Writes a 64-bit register as it would be when written by software.
941 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
942 *
943 * @returns The value that's actually written to the register.
944 * @param pThis The shared DMAR device state.
945 * @param offReg The MMIO offset of the register.
946 * @param uReg The 64-bit value to write.
947 * @param puPrev Where to store the register value prior to writing.
948 */
949static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
950{
951 /* Read current value from the 64-bit register. */
952 uint64_t uCurReg;
953 uint64_t fRwMask;
954 uint64_t fRw1cMask;
955 dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
956 *puPrev = uCurReg;
957
958 uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
959 uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
960 uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
961 uint64_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
962
963 /* Write new value to the 64-bit register. */
964 dmarRegWriteRaw64(pThis, offReg, uNewReg);
965 return uNewReg;
966}
967
968
969/**
970 * Reads a 32-bit register as it would be when read by software.
971 *
972 * @returns The register value.
973 * @param pThis The shared DMAR device state.
974 * @param offReg The MMIO offset of the register.
975 */
976static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
977{
978 return dmarRegReadRaw32(pThis, offReg);
979}
980
981
982/**
983 * Reads a 64-bit register as it would be when read by software.
984 *
985 * @returns The register value.
986 * @param pThis The shared DMAR device state.
987 * @param offReg The MMIO offset of the register.
988 */
989static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
990{
991 return dmarRegReadRaw64(pThis, offReg);
992}
993
994
995/**
996 * Modifies a 32-bit register.
997 *
998 * @param pThis The shared DMAR device state.
999 * @param offReg The MMIO offset of the register.
1000 * @param fAndMask The AND mask (applied first).
1001 * @param fOrMask The OR mask.
1002 * @remarks This does NOT apply RO or RW1C masks while modifying the
1003 * register.
1004 */
1005static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1006{
1007 uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1008 uReg = (uReg & fAndMask) | fOrMask;
1009 dmarRegWriteRaw32(pThis, offReg, uReg);
1010}
1011
1012
1013/**
1014 * Modifies a 64-bit register.
1015 *
1016 * @param pThis The shared DMAR device state.
1017 * @param offReg The MMIO offset of the register.
1018 * @param fAndMask The AND mask (applied first).
1019 * @param fOrMask The OR mask.
1020 * @remarks This does NOT apply RO or RW1C masks while modifying the
1021 * register.
1022 */
1023static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1024{
1025 uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1026 uReg = (uReg & fAndMask) | fOrMask;
1027 dmarRegWriteRaw64(pThis, offReg, uReg);
1028}
1029
1030
1031/**
1032 * Checks if the invalidation-queue is empty.
1033 *
1034 * Extended version which optionally returns the current queue head and tail
1035 * offsets.
1036 *
1037 * @returns @c true if empty, @c false otherwise.
1038 * @param pThis The shared DMAR device state.
1039 * @param poffQh Where to store the queue head offset. Optional, can be NULL.
1040 * @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1041 */
1042static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t *poffQh, uint32_t *poffQt)
1043{
1044 /* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1045 uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1046 uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1047
1048 /* Don't bother masking QT, QH since other bits are RsvdZ. */
1049 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1050 Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1051 if (poffQh)
1052 *poffQh = uIqhReg;
1053 if (poffQt)
1054 *poffQt = uIqtReg;
1055 return uIqtReg == uIqhReg;
1056}
1057
1058
1059/**
1060 * Checks if the invalidation-queue is empty.
1061 *
1062 * @returns @c true if empty, @c false otherwise.
1063 * @param pThis The shared DMAR device state.
1064 */
1065static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1066{
1067 return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh */, NULL /* poffQt */);
1068}
1069
1070
1071/**
1072 * Checks if the invalidation-queue is capable of processing requests.
1073 *
1074 * @returns @c true if the invalidation-queue can process requests, @c false
1075 * otherwise.
1076 * @param pThis The shared DMAR device state.
1077 */
1078static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1079{
1080 /* Check if queued-invalidation is enabled. */
1081 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1082 if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1083 {
1084 /* Check if there are no invalidation-queue or timeout errors. */
1085 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1086 if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_ITE_MASK)))
1087 return true;
1088 }
1089 return false;
1090}
1091
1092
1093/**
1094 * Wakes up the invalidation-queue thread if there are requests to be processed.
1095 *
1096 * @param pDevIns The IOMMU device instance.
1097 */
1098static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1099{
1100 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1101 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1102 Log4Func(("\n"));
1103
1104 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1105
1106 if ( dmarInvQueueCanProcessRequests(pThis)
1107 && !dmarInvQueueIsEmpty(pThis))
1108 {
1109 Log4Func(("Signaling the invalidation-queue thread\n"));
1110 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1111 }
1112}
1113
1114
1115/**
1116 * Raises an event on behalf of the DMAR.
1117 *
1118 * These are events that are generated by the DMAR itself (like faults and
1119 * invalidation completion notifications).
1120 *
1121 * @param pDevIns The IOMMU device instance.
1122 * @param enmEventType The DMAR event type.
1123 *
1124 * @remarks The DMAR lock must be held while calling this function.
1125 */
1126static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1127{
1128 uint16_t offCtlReg;
1129 uint32_t fIntrMaskedMask;
1130 uint32_t fIntrPendingMask;
1131 uint16_t offMsiAddrLoReg;
1132 uint16_t offMsiAddrHiReg;
1133 uint16_t offMsiDataReg;
1134 switch (enmEventType)
1135 {
1136 case DMAREVENTTYPE_INV_COMPLETE:
1137 {
1138 offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1139 fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1140 fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1141 offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1142 offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1143 offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1144 break;
1145 }
1146
1147 case DMAREVENTTYPE_FAULT:
1148 {
1149 offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1150 fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1151 fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1152 offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1153 offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1154 offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1155 break;
1156 }
1157
1158 default:
1159 {
1160 /* Shouldn't ever happen. */
1161 AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1162 }
1163 }
1164
1165 /* Check if software has masked the interrupt. */
1166 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1167 uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1168 if (!(uCtlReg & fIntrMaskedMask))
1169 {
1170 /*
1171 * Interrupt is unmasked, raise it.
1172 * Interrupts generated by the DMAR have trigger mode and level as 0.
1173 * See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1174 */
1175 MSIMSG Msi;
1176 Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1177 Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1178 Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1179 Assert(Msi.Data.n.u1Level == 0);
1180 Assert(Msi.Data.n.u1TriggerMode == 0);
1181
1182 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1183 pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1184
1185 /* Clear interrupt pending bit. */
1186 uCtlReg &= ~fIntrPendingMask;
1187 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1188 }
1189 else
1190 {
1191 /* Interrupt is masked, set the interrupt pending bit. */
1192 uCtlReg |= fIntrPendingMask;
1193 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1194 }
1195}
1196
1197
1198/**
1199 * Raises an interrupt in response to a fault event.
1200 *
1201 * @param pDevIns The IOMMU device instance.
1202 *
1203 * @remarks This assumes the caller has already set the required status bits in the
1204 * FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1205 */
1206static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1207{
1208 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1209 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1210 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1211
1212#ifdef RT_STRICT
1213 {
1214 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1215 uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK | VTD_BF_FSTS_REG_PFO_MASK
1216 /* | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_AFO_MASK */ /* AFL not supported */
1217 /* | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK */ /* Device-TLBs not supported */
1218 | VTD_BF_FSTS_REG_IQE_MASK;
1219 Assert(uFstsReg & fFaultMask);
1220 }
1221#endif
1222 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1223}
1224
1225
1226#ifdef IN_RING3
1227/**
1228 * Raises an interrupt in response to an invalidation (complete) event.
1229 *
1230 * @param pDevIns The IOMMU device instance.
1231 */
1232static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1233{
1234 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1235 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1236 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1237
1238 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1239 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1240 {
1241 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1242 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1243 }
1244}
1245#endif /* IN_RING3 */
1246
1247
1248/**
1249 * Checks if a primary fault can be recorded.
1250 *
1251 * @returns @c true if the fault can be recorded, @c false otherwise.
1252 * @param pDevIns The IOMMU device instance.
1253 * @param pThis The shared DMAR device state.
1254 *
1255 * @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1256 * NOT call it unless there is a fault condition!
1257 */
1258static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1259{
1260 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1261 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1262
1263 uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1264 if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1265 return false;
1266
1267 /*
1268 * If we add more FRCD registers, we'll have to loop through them here.
1269 * Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1270 * nor do we need to increment FRI.
1271 *
1272 * See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1273 */
1274 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1275 uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1276 if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1277 {
1278 uFstsReg |= VTD_BF_FSTS_REG_PFO_MASK;
1279 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1280 return false;
1281 }
1282
1283 return true;
1284}
1285
1286
1287/**
1288 * Records a primary fault.
1289 *
1290 * @param pDevIns The IOMMU device instance.
1291 * @param enmDiag The diagnostic reason.
1292 * @param uFrcdHi The FRCD_HI_REG value for this fault.
1293 * @param uFrcdLo The FRCD_LO_REG value for this fault.
1294 */
1295static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint64_t uFrcdHi, uint64_t uFrcdLo)
1296{
1297 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1298 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1299
1300 DMAR_LOCK(pDevIns, pThisCC);
1301
1302 /* Update the diagnostic reason. */
1303 pThis->enmDiag = enmDiag;
1304
1305 /* We don't support advance fault logging. */
1306 Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1307
1308 if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1309 {
1310 /* Update the fault recording registers with the fault information. */
1311 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1312 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1313
1314 /* Set the Pending Primary Fault (PPF) field in the status register. */
1315 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1316
1317 /* Raise interrupt if necessary. */
1318 dmarFaultEventRaiseInterrupt(pDevIns);
1319 }
1320
1321 DMAR_UNLOCK(pDevIns, pThisCC);
1322}
1323
1324
1325/**
1326 * Records an interrupt request fault.
1327 *
1328 * @param pDevIns The IOMMU device instance.
1329 * @param enmDiag The diagnostic reason.
1330 * @param enmIrFault The interrupt fault reason.
1331 * @param idDevice The device ID (bus, device, function).
1332 * @param idxIntr The interrupt index.
1333 */
1334static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIRFAULT enmIrFault, uint16_t idDevice, uint16_t idxIntr)
1335{
1336 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1337 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1338 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1339 uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1340 dmarPrimaryFaultRecord(pDevIns, enmDiag, uFrcdHi, uFrcdLo);
1341}
1342
1343
1344/**
1345 * Records a qualified interrupt request fault.
1346 *
1347 * Qualified faults are those that can be suppressed by software using the FPD bit
1348 * in the IRTE.
1349 *
1350 * @param pDevIns The IOMMU device instance.
1351 * @param enmDiag The diagnostic reason.
1352 * @param enmIrFault The interrupt fault reason.
1353 * @param idDevice The device ID (bus, device, function).
1354 * @param idxIntr The interrupt index.
1355 * @param pIrte The IRTE that caused this fault.
1356 */
1357static void dmarIrFaultRecordQualified(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIRFAULT enmIrFault, uint16_t idDevice,
1358 uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1359{
1360 Assert(vtdIrFaultIsQualified(enmIrFault));
1361 Assert(pIrte);
1362 if (!(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK))
1363 return dmarIrFaultRecord(pDevIns, enmDiag, enmIrFault, idDevice, idxIntr);
1364}
1365
1366
1367/**
1368 * Records an address translation fault (extensive version).
1369 *
1370 * @param pDevIns The IOMMU device instance.
1371 * @param enmDiag The diagnostic reason.
1372 * @param enmAtFault The address translation fault reason.
1373 * @param idDevice The device ID (bus, device, function).
1374 * @param uFaultAddr The page address of the faulted request.
1375 * @param enmReqType The type of the faulted request.
1376 * @param uAddrType The address type of the faulted request (only applicable
1377 * when device-TLB is supported).
1378 * @param fHasPasid Whether the faulted request has a PASID TLP prefix.
1379 * @param uPasid The PASID value when a PASID TLP prefix is present.
1380 * @param fReqAttr The attributes of the faulted requested (VTD_REQ_ATTR_XXX).
1381 */
1382static void dmarAtFaultRecordEx(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDATFAULT enmAtFault, uint16_t idDevice,
1383 uint64_t uFaultAddr, VTDREQTYPE enmReqType, uint8_t uAddrType, bool fHasPasid, uint32_t uPasid,
1384 uint8_t fReqAttr)
1385{
1386 uint8_t const fType1 = enmReqType & RT_BIT(1);
1387 uint8_t const fType2 = enmReqType & RT_BIT(0);
1388 uint8_t const fExec = fReqAttr & VTD_REQ_ATTR_EXE;
1389 uint8_t const fPriv = fReqAttr & VTD_REQ_ATTR_PRIV;
1390 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1391 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1392 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1393 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1394 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1395 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1396 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1397 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, uAddrType)
1398 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1399 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1400 uint64_t const uFrcdLo = uFaultAddr & X86_PAGE_BASE_MASK;
1401 dmarPrimaryFaultRecord(pDevIns, enmDiag, uFrcdHi, uFrcdLo);
1402}
1403
1404
1405/**
1406 * Records an address translation fault.
1407 *
1408 * This is to be used when Device-TLB, and PASIDs are not supported or for requests
1409 * where the device-TLB and PASID is not relevant/present.
1410 *
1411 * @param pDevIns The IOMMU device instance.
1412 * @param enmDiag The diagnostic reason.
1413 * @param enmAtFault The address translation fault reason.
1414 * @param idDevice The device ID (bus, device, function).
1415 * @param uFaultAddr The page address of the faulted request.
1416 * @param enmReqType The type of the faulted request.
1417 */
1418static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDATFAULT enmAtFault, uint16_t idDevice,
1419 uint64_t uFaultAddr, VTDREQTYPE enmReqType)
1420{
1421 dmarAtFaultRecordEx(pDevIns, enmDiag, enmAtFault, idDevice, uFaultAddr, enmReqType, 0 /* uAddrType */,
1422 false /* fHasPasid */, 0 /* uPasid */, 0 /* fReqAttr */);
1423}
1424
1425
1426/**
1427 * Records an IQE fault.
1428 *
1429 * @param pDevIns The IOMMU device instance.
1430 * @param enmIqei The IQE information.
1431 * @param enmDiag The diagnostic reason.
1432 */
1433static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1434{
1435 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1436 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1437
1438 DMAR_LOCK(pDevIns, pThisCC);
1439
1440 /* Update the diagnostic reason. */
1441 pThis->enmDiag = enmDiag;
1442
1443 /* Set the error bit. */
1444 uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1445 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1446
1447 /* Set the error information. */
1448 uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1449 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1450
1451 dmarFaultEventRaiseInterrupt(pDevIns);
1452
1453 DMAR_UNLOCK(pDevIns, pThisCC);
1454}
1455
1456
1457/**
1458 * Handles writes to GCMD_REG.
1459 *
1460 * @returns Strict VBox status code.
1461 * @param pDevIns The IOMMU device instance.
1462 * @param uGcmdReg The value written to GCMD_REG.
1463 */
1464static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1465{
1466 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1467 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1468 uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1469 uint64_t const fExtCapReg = pThis->fExtCapReg;
1470
1471 /* Queued-invalidation. */
1472 if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1473 && (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1474 {
1475 if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1476 {
1477 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1478 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1479 }
1480 else
1481 {
1482 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1483 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1484 }
1485 }
1486
1487 if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1488 {
1489 /* Set Interrupt Remapping Table Pointer (SIRTP). */
1490 if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1491 {
1492 /** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1493 * supported. */
1494 pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1495 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1496 }
1497
1498 /* Interrupt remapping. */
1499 if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1500 {
1501 if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1502 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1503 else
1504 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1505 }
1506
1507 /* Compatibility format interrupts. */
1508 if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1509 {
1510 if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1511 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1512 else
1513 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1514 }
1515 }
1516
1517 /* Set Root Table Pointer (SRTP). */
1518 if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1519 {
1520 /** @todo Perform global invalidation of all remapping translation caches when
1521 * ESRTPS is supported. */
1522 pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1523 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1524 }
1525
1526 /* Translation (DMA remapping). */
1527 if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1528 {
1529 if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1530 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1531 else
1532 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1533 }
1534
1535 return VINF_SUCCESS;
1536}
1537
1538
1539/**
1540 * Handles writes to CCMD_REG.
1541 *
1542 * @returns Strict VBox status code.
1543 * @param pDevIns The IOMMU device instance.
1544 * @param offReg The MMIO register offset.
1545 * @param cbReg The size of the MMIO access (in bytes).
1546 * @param uCcmdReg The value written to CCMD_REG.
1547 */
1548static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1549{
1550 /* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1551 if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1552 {
1553 /* Check if we need to invalidate the context-context. */
1554 bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1555 if (fIcc)
1556 {
1557 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1558 uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1559 if (uMajorVersion < 6)
1560 {
1561 /* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1562 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1563 if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1564 {
1565 /* Verify table translation mode is legacy. */
1566 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1567 if (fTtm == VTD_TTM_LEGACY_MODE)
1568 {
1569 /** @todo Invalidate. */
1570 return VINF_SUCCESS;
1571 }
1572 pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1573 }
1574 else
1575 pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1576 }
1577 else
1578 pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1579 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1580 }
1581 }
1582 return VINF_SUCCESS;
1583}
1584
1585
1586/**
1587 * Handles writes to FECTL_REG.
1588 *
1589 * @returns Strict VBox status code.
1590 * @param pDevIns The IOMMU device instance.
1591 * @param uFectlReg The value written to FECTL_REG.
1592 */
1593static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1594{
1595 /*
1596 * If software unmasks the interrupt when the interrupt is pending, we must raise
1597 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1598 */
1599 if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1600 && ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1601 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1602 return VINF_SUCCESS;
1603}
1604
1605
1606/**
1607 * Handles writes to FSTS_REG.
1608 *
1609 * @returns Strict VBox status code.
1610 * @param pDevIns The IOMMU device instance.
1611 * @param uFstsReg The value written to FSTS_REG.
1612 * @param uPrev The value in FSTS_REG prior to writing it.
1613 */
1614static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1615{
1616 /*
1617 * If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1618 * the interrupt pending (IP) bit must be cleared.
1619 *
1620 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1621 */
1622 uint32_t const fChanged = uPrev ^ uFstsReg;
1623 if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK
1624 | VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_PFO_MASK))
1625 {
1626 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1627 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1628 }
1629 return VINF_SUCCESS;
1630}
1631
1632
1633/**
1634 * Handles writes to IQT_REG.
1635 *
1636 * @returns Strict VBox status code.
1637 * @param pDevIns The IOMMU device instance.
1638 * @param offReg The MMIO register offset.
1639 * @param uIqtReg The value written to IQT_REG.
1640 */
1641static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1642{
1643 /* We only care about the low 32-bits, high 32-bits are reserved. */
1644 Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1645 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1646
1647 /* Paranoia. */
1648 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1649
1650 uint32_t const offQt = uIqtReg;
1651 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1652 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1653
1654 /* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1655 if ( fDw != VTD_IQA_REG_DW_256_BIT
1656 || !(offQt & RT_BIT(4)))
1657 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1658 else
1659 {
1660 /* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1661 dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1662 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1663 }
1664 return VINF_SUCCESS;
1665}
1666
1667
1668/**
1669 * Handles writes to IQA_REG.
1670 *
1671 * @returns Strict VBox status code.
1672 * @param pDevIns The IOMMU device instance.
1673 * @param offReg The MMIO register offset.
1674 * @param uIqaReg The value written to IQA_REG.
1675 */
1676static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1677{
1678 /* At present, we only care about the low 32-bits, high 32-bits are data. */
1679 Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1680
1681 /** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1682 * returns true? The Intel VT-d spec. doesn't state anywhere that it
1683 * cannot happen or that it's ignored when it does happen. */
1684
1685 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1686 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1687 if (fDw == VTD_IQA_REG_DW_256_BIT)
1688 {
1689 bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK | VTD_BF_ECAP_REG_ADMS_MASK));
1690 if (fSupports256BitDw)
1691 { /* likely */ }
1692 else
1693 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1694 }
1695 /* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1696
1697 return VINF_SUCCESS;
1698}
1699
1700
1701/**
1702 * Handles writes to ICS_REG.
1703 *
1704 * @returns Strict VBox status code.
1705 * @param pDevIns The IOMMU device instance.
1706 * @param uIcsReg The value written to ICS_REG.
1707 */
1708static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1709{
1710 /*
1711 * If the IP field is set when software services the interrupt condition,
1712 * (by clearing the IWC field), the IP field must be cleared.
1713 */
1714 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1715 {
1716 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1717 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1718 }
1719 return VINF_SUCCESS;
1720}
1721
1722
1723/**
1724 * Handles writes to IECTL_REG.
1725 *
1726 * @returns Strict VBox status code.
1727 * @param pDevIns The IOMMU device instance.
1728 * @param uIectlReg The value written to IECTL_REG.
1729 */
1730static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1731{
1732 /*
1733 * If software unmasks the interrupt when the interrupt is pending, we must raise
1734 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1735 */
1736 if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1737 && ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1738 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1739 return VINF_SUCCESS;
1740}
1741
1742
1743/**
1744 * Handles writes to FRCD_REG (High 64-bits).
1745 *
1746 * @returns Strict VBox status code.
1747 * @param pDevIns The IOMMU device instance.
1748 * @param offReg The MMIO register offset.
1749 * @param cbReg The size of the MMIO access (in bytes).
1750 * @param uFrcdHiReg The value written to FRCD_REG.
1751 * @param uPrev The value in FRCD_REG prior to writing it.
1752 */
1753static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
1754{
1755 /* We only care about responding to high 32-bits, low 32-bits are read-only. */
1756 if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
1757 {
1758 /*
1759 * If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
1760 * Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
1761 * has only 1 FRCD register.
1762 *
1763 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1764 */
1765 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1766 uint64_t const fChanged = uPrev ^ uFrcdHiReg;
1767 if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
1768 {
1769 Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
1770 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1771 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
1772 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1773 }
1774 }
1775 return VINF_SUCCESS;
1776}
1777
1778
1779/**
1780 * Performs a PCI target abort for a DMA remapping (DR) operation.
1781 *
1782 * @param pDevIns The IOMMU device instance.
1783 */
1784static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
1785{
1786 /** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
1787 * as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
1788 * who knows. */
1789 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1790 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1791 PDMPciDevSetStatus(pPciDev, u16Status);
1792}
1793
1794
1795/**
1796 * Handles remapping of DMA address requests in legacy mode.
1797 *
1798 * @returns VBox status code.
1799 * @param pDevIns The IOMMU device instance.
1800 * @param uRtaddrReg The current RTADDR_REG value.
1801 * @param pAddrRemap The DMA address remap info.
1802 */
1803static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARADDRMAP pAddrRemap)
1804{
1805 RT_NOREF3(pDevIns, uRtaddrReg, pAddrRemap);
1806 return VERR_NOT_IMPLEMENTED;
1807}
1808
1809
1810/**
1811 * Handles remapping of DMA address requests in scalable mode.
1812 *
1813 * @returns VBox status code.
1814 * @param pDevIns The IOMMU device instance.
1815 * @param uRtaddrReg The current RTADDR_REG value.
1816 * @param pAddrRemap The DMA address remap info.
1817 */
1818static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARADDRMAP pAddrRemap)
1819{
1820 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1821 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
1822 {
1823 RT_NOREF1(uRtaddrReg);
1824 return VERR_NOT_IMPLEMENTED;
1825 }
1826
1827 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_3, VTDATFAULT_RTA_1_3, pAddrRemap->idDevice, pAddrRemap->uDmaAddr,
1828 pAddrRemap->enmReqType);
1829 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
1830}
1831
1832
1833/**
1834 * Reads a root entry from guest memory.
1835 *
1836 * @returns VBox status code.
1837 * @param idDevice The device ID (bus, device, function).
1838 * @param pRootEntry Where to store the read root entry.
1839 */
1840static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxEntry, PVTD_ROOT_ENTRY_T pRootEntry)
1841{
1842 size_t const cbEntry = sizeof(*pRootEntry);
1843 RTGCPHYS const GCPhysEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxEntry * cbEntry);
1844 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysEntry, pRootEntry, cbEntry);
1845}
1846
1847
1848/**
1849 * Memory access bulk (one or more 4K pages) request from a device.
1850 *
1851 * @returns VBox status code.
1852 * @param pDevIns The IOMMU device instance.
1853 * @param idDevice The device ID (bus, device, function).
1854 * @param cIovas The number of addresses being accessed.
1855 * @param pauIovas The I/O virtual addresses for each page being accessed.
1856 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1857 * @param paGCPhysSpa Where to store the translated physical addresses.
1858 *
1859 * @thread Any.
1860 */
1861static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
1862 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
1863{
1864 RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
1865 return VERR_NOT_IMPLEMENTED;
1866}
1867
1868
1869/**
1870 * Memory access transaction from a device.
1871 *
1872 * @returns VBox status code.
1873 * @param pDevIns The IOMMU device instance.
1874 * @param idDevice The device ID (bus, device, function).
1875 * @param uIova The I/O virtual address being accessed.
1876 * @param cbIova The size of the access.
1877 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
1878 * @param pGCPhysSpa Where to store the translated system physical address.
1879 * @param pcbContiguous Where to store the number of contiguous bytes translated
1880 * and permission-checked.
1881 *
1882 * @thread Any.
1883 */
1884static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
1885 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
1886{
1887 /* Validate. */
1888 AssertPtr(pDevIns);
1889 AssertPtr(pGCPhysSpa);
1890 AssertPtr(pcbContiguous);
1891 Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
1892 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
1893
1894 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1895 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1896
1897 DMAR_LOCK(pDevIns, pThisCC);
1898 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1899 uint64_t const uRtaddrReg = pThis->uRtaddrReg;
1900 DMAR_UNLOCK(pDevIns, pThisCC);
1901
1902 if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
1903 {
1904 VTDREQTYPE enmReqType;
1905 if (fFlags & PDMIOMMU_MEM_F_READ)
1906 {
1907 enmReqType = VTDREQTYPE_READ;
1908 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
1909 }
1910 else
1911 {
1912 enmReqType = VTDREQTYPE_WRITE;
1913 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
1914 }
1915
1916 DMARADDRMAP AddrRemap;
1917 AddrRemap.idDevice = idDevice;
1918 AddrRemap.enmReqType = enmReqType;
1919 AddrRemap.uDmaAddr = uIova;
1920 AddrRemap.cbDma = cbIova;
1921 AddrRemap.GCPhysSpa = NIL_RTGCPHYS;
1922 AddrRemap.cbContiguous = 0;
1923
1924 int rc;
1925 uint8_t const fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1926 switch (fTtm)
1927 {
1928 case VTD_TTM_LEGACY_MODE:
1929 {
1930 rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, &AddrRemap);
1931 break;
1932 }
1933
1934 case VTD_TTM_SCALABLE_MODE:
1935 {
1936 rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, &AddrRemap);
1937 break;
1938 }
1939
1940 case VTD_TTM_ABORT_DMA_MODE:
1941 {
1942 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
1943 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
1944 dmarDrTargetAbort(pDevIns);
1945 else
1946 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_1, VTDATFAULT_RTA_1_1, idDevice, uIova, enmReqType);
1947 break;
1948 }
1949
1950 default:
1951 {
1952 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
1953 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_2, VTDATFAULT_RTA_1_2, idDevice, uIova, enmReqType);
1954 break;
1955 }
1956 }
1957
1958 *pcbContiguous = AddrRemap.cbContiguous;
1959 *pGCPhysSpa = AddrRemap.GCPhysSpa;
1960 return rc;
1961 }
1962
1963 *pGCPhysSpa = uIova;
1964 *pcbContiguous = cbIova;
1965 return VINF_SUCCESS;
1966}
1967
1968
1969/**
1970 * Reads an IRTE from guest memory.
1971 *
1972 * @returns VBox status code.
1973 * @param pDevIns The IOMMU device instance.
1974 * @param uIrtaReg The IRTA_REG.
1975 * @param idxIntr The interrupt index.
1976 * @param pIrte Where to store the read IRTE.
1977 */
1978static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
1979{
1980 Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
1981
1982 size_t const cbIrte = sizeof(*pIrte);
1983 RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
1984 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
1985}
1986
1987
1988/**
1989 * Remaps the source MSI to the destination MSI given the IRTE.
1990 *
1991 * @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
1992 * IRTA_REG.EIME).
1993 * @param pIrte The IRTE used for the remapping.
1994 * @param pMsiIn The source MSI (currently unused).
1995 * @param pMsiOut Where to store the remapped MSI.
1996 */
1997static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1998{
1999 NOREF(pMsiIn);
2000 uint64_t const uIrteQword0 = pIrte->au64[0];
2001
2002 /*
2003 * Let's start with a clean slate and preserve unspecified bits if the need arises.
2004 * For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2005 * but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2006 * it copies it from the source MSI.
2007 */
2008 RT_ZERO(*pMsiOut);
2009 pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2010 pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2011 pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2012 if (fExtIntrMode)
2013 {
2014 /*
2015 * Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2016 * high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2017 */
2018 uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2019 pMsiOut->Addr.n.u8DestId = idDest;
2020 pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2021 }
2022 else
2023 pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2024
2025 pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2026 pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2027 pMsiOut->Data.n.u1Level = 1;
2028 pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2029}
2030
2031
2032/**
2033 * Handles remapping of interrupts in remappable interrupt format.
2034 *
2035 * @returns VBox status code.
2036 * @param pDevIns The IOMMU device instance.
2037 * @param uIrtaReg The IRTA_REG.
2038 * @param idDevice The device ID (bus, device, function).
2039 * @param pMsiIn The source MSI.
2040 * @param pMsiOut Where to store the remapped MSI.
2041 */
2042static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2043{
2044 Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2045
2046 /* Validate reserved bits in the interrupt request. */
2047 AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2048 if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2049 {
2050 /* Compute the index into the interrupt remap table. */
2051 uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2052 uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2053 uint16_t const uHandle = uHandleLo | (uHandleHi << 15);
2054 bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2055 uint16_t const idxIntr = fSubHandleValid
2056 ? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2057 : uHandle;
2058
2059 /* Validate the index. */
2060 uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2061 if (idxIntr < cEntries)
2062 {
2063 /** @todo Implement and read IRTE from interrupt-entry cache here. */
2064
2065 /* Read the interrupt remap table entry (IRTE) at the index. */
2066 VTD_IRTE_T Irte;
2067 int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2068 if (RT_SUCCESS(rc))
2069 {
2070 /* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2071 uint64_t const uIrteQword0 = Irte.au64[0];
2072 uint64_t const uIrteQword1 = Irte.au64[1];
2073 bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2074 if (fPresent)
2075 {
2076 /* Validate reserved bits in the IRTE. */
2077 bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2078 uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2079 if ( !(uIrteQword0 & ~fQw0ValidMask)
2080 && !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2081 {
2082 /* Validate requester id (the device ID) as configured in the IRTE. */
2083 bool fSrcValid;
2084 DMARDIAG enmIrDiag;
2085 uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2086 switch (fSvt)
2087 {
2088 case VTD_IRTE_SVT_NONE:
2089 {
2090 fSrcValid = true;
2091 enmIrDiag = kDmarDiag_None;
2092 break;
2093 }
2094
2095 case VTD_IRTE_SVT_VALIDATE_MASK:
2096 {
2097 static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2098 uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2099 uint16_t const fValidMask = s_afValidMasks[idxMask];
2100 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2101 fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2102 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2103 break;
2104 }
2105
2106 case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2107 {
2108 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2109 uint8_t const uBusFirst = RT_HI_U8(idSource);
2110 uint8_t const uBusLast = RT_LO_U8(idSource);
2111 uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2112 fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2113 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2114 break;
2115 }
2116
2117 default:
2118 {
2119 fSrcValid = false;
2120 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2121 break;
2122 }
2123 }
2124
2125 if (fSrcValid)
2126 {
2127 uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2128 if (!fPostedMode)
2129 {
2130 dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2131 return VINF_SUCCESS;
2132 }
2133 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
2134 VTDIRFAULT_IRTE_PRESENT_RSVD, idDevice, idxIntr, &Irte);
2135 }
2136 else
2137 dmarIrFaultRecordQualified(pDevIns, enmIrDiag, VTDIRFAULT_IRTE_PRESENT_RSVD, idDevice, idxIntr,
2138 &Irte);
2139 }
2140 else
2141 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, VTDIRFAULT_IRTE_PRESENT_RSVD,
2142 idDevice, idxIntr, &Irte);
2143 }
2144 else
2145 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, VTDIRFAULT_IRTE_NOT_PRESENT,
2146 idDevice, idxIntr, &Irte);
2147 }
2148 else
2149 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, VTDIRFAULT_IRTE_READ_FAILED, idDevice, idxIntr);
2150 }
2151 else
2152 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, VTDIRFAULT_INTR_INDEX_INVALID, idDevice, idxIntr);
2153 }
2154 else
2155 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, VTDIRFAULT_REMAPPABLE_INTR_RSVD, idDevice, 0 /* idxIntr */);
2156 return VERR_IOMMU_INTR_REMAP_DENIED;
2157}
2158
2159
2160/**
2161 * Interrupt remap request from a device.
2162 *
2163 * @returns VBox status code.
2164 * @param pDevIns The IOMMU device instance.
2165 * @param idDevice The device ID (bus, device, function).
2166 * @param pMsiIn The source MSI.
2167 * @param pMsiOut Where to store the remapped MSI.
2168 */
2169static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2170{
2171 /* Validate. */
2172 Assert(pDevIns);
2173 Assert(pMsiIn);
2174 Assert(pMsiOut);
2175 RT_NOREF1(idDevice);
2176
2177 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2178 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2179
2180 /* Lock and read all registers required for interrupt remapping up-front. */
2181 DMAR_LOCK(pDevIns, pThisCC);
2182 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2183 uint64_t const uIrtaReg = pThis->uIrtaReg;
2184 DMAR_UNLOCK(pDevIns, pThisCC);
2185
2186 /* Check if interrupt remapping is enabled. */
2187 if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
2188 {
2189 bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
2190 if (!fIsRemappable)
2191 {
2192 /* Handle compatibility format interrupts. */
2193 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
2194
2195 /* If EIME is enabled or CFIs are disabled, block the interrupt. */
2196 if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
2197 || !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
2198 {
2199 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
2200 return VERR_IOMMU_INTR_REMAP_DENIED;
2201 }
2202
2203 /* Interrupt isn't subject to remapping, pass-through the interrupt. */
2204 *pMsiOut = *pMsiIn;
2205 return VINF_SUCCESS;
2206 }
2207
2208 /* Handle remappable format interrupts. */
2209 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
2210 return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
2211 }
2212
2213 /* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
2214 *pMsiOut = *pMsiIn;
2215 return VINF_SUCCESS;
2216}
2217
2218
2219/**
2220 * @callback_method_impl{FNIOMMMIONEWWRITE}
2221 */
2222static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
2223{
2224 RT_NOREF1(pvUser);
2225 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2226
2227 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2228 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
2229
2230 uint16_t const offReg = off;
2231 uint16_t const offLast = offReg + cb - 1;
2232 if (DMAR_IS_MMIO_OFF_VALID(offLast))
2233 {
2234 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2235 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2236
2237 uint64_t uPrev = 0;
2238 uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, *(uint64_t *)pv, &uPrev)
2239 : dmarRegWrite32(pThis, offReg, *(uint32_t *)pv, (uint32_t *)&uPrev);
2240 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2241 switch (off)
2242 {
2243 case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
2244 {
2245 rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
2246 break;
2247 }
2248
2249 case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
2250 case VTD_MMIO_OFF_CCMD_REG + 4:
2251 {
2252 rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
2253 break;
2254 }
2255
2256 case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
2257 {
2258 rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
2259 break;
2260 }
2261
2262 case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
2263 {
2264 rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
2265 break;
2266 }
2267
2268 case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
2269 /* VTD_MMIO_OFF_IQT_REG + 4: */ /* High 32-bits reserved. */
2270 {
2271 rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
2272 break;
2273 }
2274
2275 case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
2276 /* VTD_MMIO_OFF_IQA_REG + 4: */ /* High 32-bits data. */
2277 {
2278 rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
2279 break;
2280 }
2281
2282 case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
2283 {
2284 rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
2285 break;
2286 }
2287
2288 case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
2289 {
2290 rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
2291 break;
2292 }
2293
2294 case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
2295 case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
2296 {
2297 rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
2298 break;
2299 }
2300 }
2301
2302 DMAR_UNLOCK(pDevIns, pThisCC);
2303 LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
2304 return rcStrict;
2305 }
2306
2307 return VINF_IOM_MMIO_UNUSED_FF;
2308}
2309
2310
2311/**
2312 * @callback_method_impl{FNIOMMMIONEWREAD}
2313 */
2314static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
2315{
2316 RT_NOREF1(pvUser);
2317 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2318
2319 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2320 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
2321
2322 uint16_t const offReg = off;
2323 uint16_t const offLast = offReg + cb - 1;
2324 if (DMAR_IS_MMIO_OFF_VALID(offLast))
2325 {
2326 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2327 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2328
2329 if (cb == 8)
2330 {
2331 *(uint64_t *)pv = dmarRegRead64(pThis, offReg);
2332 LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, *(uint64_t *)pv));
2333 }
2334 else
2335 {
2336 *(uint32_t *)pv = dmarRegRead32(pThis, offReg);
2337 LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, *(uint32_t *)pv));
2338 }
2339
2340 DMAR_UNLOCK(pDevIns, pThisCC);
2341 return VINF_SUCCESS;
2342 }
2343
2344 return VINF_IOM_MMIO_UNUSED_FF;
2345}
2346
2347
2348#ifdef IN_RING3
2349/**
2350 * Process requests in the invalidation queue.
2351 *
2352 * @param pDevIns The IOMMU device instance.
2353 * @param pvRequests The requests to process.
2354 * @param cbRequests The size of all requests (in bytes).
2355 * @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
2356 * VTD_IQA_REG_DW_256_BIT).
2357 * @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
2358 */
2359static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
2360 uint8_t fTtm)
2361{
2362#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
2363 do \
2364 { \
2365 dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
2366 return; \
2367 } while (0)
2368
2369 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2370 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2371
2372 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2373 Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
2374
2375 /*
2376 * The below check is redundant since we check both TTM and DW for each
2377 * descriptor type we process. However, the error reported by hardware
2378 * may differ hence this is kept commented out but not removed from the code
2379 * if we need to change this in the future.
2380 *
2381 * In our implementation, we would report the descriptor type as invalid,
2382 * while on real hardware it may report descriptor width as invalid.
2383 * The Intel VT-d spec. is not clear which error takes preceedence.
2384 */
2385#if 0
2386 /*
2387 * Verify that 128-bit descriptors are not used when operating in scalable mode.
2388 * We don't check this while software writes IQA_REG but defer it until now because
2389 * RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
2390 * -IS- performed when software writes IQA_REG since it only requires checking against
2391 * immutable hardware features.
2392 */
2393 if ( fTtm != VTD_TTM_SCALABLE_MODE
2394 || fDw != VTD_IQA_REG_DW_128_BIT)
2395 { /* likely */ }
2396 else
2397 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
2398#endif
2399
2400 /*
2401 * Process requests in FIFO order.
2402 */
2403 uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
2404 for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
2405 {
2406 uint64_t const *puDscQwords = (uint64_t const *)((uintptr_t)pvRequests + offDsc);
2407 uint64_t const uQword0 = puDscQwords[0];
2408 uint64_t const uQword1 = puDscQwords[1];
2409 uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
2410 switch (fDscType)
2411 {
2412 case VTD_INV_WAIT_DSC_TYPE:
2413 {
2414 /* Validate descriptor type. */
2415 if ( fTtm == VTD_TTM_LEGACY_MODE
2416 || fDw == VTD_IQA_REG_DW_256_BIT)
2417 { /* likely */ }
2418 else
2419 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
2420
2421 /* Validate reserved bits. */
2422 uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
2423 ? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
2424 : VTD_INV_WAIT_DSC_0_VALID_MASK;
2425 if ( !(uQword0 & ~fValidMask0)
2426 && !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
2427 { /* likely */ }
2428 else
2429 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
2430
2431 if (fDw == VTD_IQA_REG_DW_256_BIT)
2432 {
2433 if ( !puDscQwords[2]
2434 && !puDscQwords[3])
2435 { /* likely */ }
2436 else
2437 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
2438 }
2439
2440 /* Perform status write (this must be done prior to generating the completion interrupt). */
2441 bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
2442 if (fSw)
2443 {
2444 uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
2445 RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
2446 int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
2447 AssertRC(rc);
2448 }
2449
2450 /* Generate invalidation event interrupt. */
2451 bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
2452 if (fIf)
2453 {
2454 DMAR_LOCK(pDevIns, pThisR3);
2455 dmarR3InvEventRaiseInterrupt(pDevIns);
2456 DMAR_UNLOCK(pDevIns, pThisR3);
2457 }
2458
2459 STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
2460 break;
2461 }
2462
2463 case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
2464 case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
2465 case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
2466 case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
2467 case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
2468 case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
2469 case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
2470 default:
2471 {
2472 /* Stop processing further requests. */
2473 LogFunc(("Invalid descriptor type: %#x\n", fDscType));
2474 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
2475 }
2476 }
2477 }
2478#undef DMAR_IQE_FAULT_RECORD_RET
2479}
2480
2481
2482/**
2483 * The invalidation-queue thread.
2484 *
2485 * @returns VBox status code.
2486 * @param pDevIns The IOMMU device instance.
2487 * @param pThread The command thread.
2488 */
2489static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2490{
2491 NOREF(pThread);
2492 LogFlowFunc(("\n"));
2493
2494 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2495 return VINF_SUCCESS;
2496
2497 /*
2498 * Pre-allocate the maximum size of the invalidation queue allowed by the spec.
2499 * This prevents trashing the heap as well as deal with out-of-memory situations
2500 * up-front while starting the VM. It also simplifies the code from having to
2501 * dynamically grow/shrink the allocation based on how software sizes the queue.
2502 * Guests normally don't alter the queue size all the time, but that's not an
2503 * assumption we can make.
2504 */
2505 uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
2506 size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
2507 void *pvRequests = RTMemAllocZ(cbMaxQs);
2508 AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
2509
2510 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2511 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2512
2513 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2514 {
2515 /*
2516 * Sleep until we are woken up.
2517 */
2518 {
2519 int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
2520 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2521 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2522 break;
2523 }
2524
2525 DMAR_LOCK(pDevIns, pThisR3);
2526 if (dmarInvQueueCanProcessRequests(pThis))
2527 {
2528 uint32_t offQueueHead;
2529 uint32_t offQueueTail;
2530 bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
2531 if (!fIsEmpty)
2532 {
2533 /*
2534 * Get the current queue size, descriptor width, queue base address and the
2535 * table translation mode while the lock is still held.
2536 */
2537 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2538 uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
2539 uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
2540 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2541 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2542 RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
2543
2544 /* Paranoia. */
2545 Assert(cbQueue <= cbMaxQs);
2546 Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
2547 Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
2548 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueTail & RT_BIT(4)));
2549 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueHead & RT_BIT(4)));
2550 Assert(offQueueHead < cbQueue);
2551
2552 /*
2553 * A table translation mode of "reserved" isn't valid for any descriptor type.
2554 * However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
2555 * but if ESRTPS is support, we will perform a global invalidation when software
2556 * changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
2557 * So caching TTM while reading all descriptors should not be a problem.
2558 *
2559 * Also, validate the queue tail offset as it's mutable by software.
2560 */
2561 if ( fTtm != VTD_TTM_RSVD
2562 && offQueueTail < cbQueue)
2563 {
2564 /* Don't hold the lock while reading (a potentially large amount of) requests */
2565 DMAR_UNLOCK(pDevIns, pThisR3);
2566
2567 int rc;
2568 uint32_t cbRequests;
2569 if (offQueueTail > offQueueHead)
2570 {
2571 /* The requests have not wrapped around, read them in one go. */
2572 cbRequests = offQueueTail - offQueueHead;
2573 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
2574 }
2575 else
2576 {
2577 /* The requests have wrapped around, read forward and wrapped-around. */
2578 uint32_t const cbForward = cbQueue - offQueueHead;
2579 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
2580
2581 uint32_t const cbWrapped = offQueueTail;
2582 if ( RT_SUCCESS(rc)
2583 && cbWrapped > 0)
2584 {
2585 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
2586 (void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
2587 }
2588 cbRequests = cbForward + cbWrapped;
2589 }
2590
2591 /* Re-acquire the lock since we need to update device state. */
2592 DMAR_LOCK(pDevIns, pThisR3);
2593
2594 if (RT_SUCCESS(rc))
2595 {
2596 /* Indicate to software we've fetched all requests. */
2597 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
2598
2599 /* Don't hold the lock while processing requests. */
2600 DMAR_UNLOCK(pDevIns, pThisR3);
2601
2602 /* Process all requests. */
2603 Assert(cbRequests <= cbQueue);
2604 dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
2605
2606 /*
2607 * We've processed all requests and the lock shouldn't be held at this point.
2608 * Using 'continue' here allows us to skip re-acquiring the lock just to release
2609 * it again before going back to the thread loop. It's a bit ugly but it certainly
2610 * helps with performance.
2611 */
2612 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2613 continue;
2614 }
2615 else
2616 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
2617 }
2618 else
2619 {
2620 if (fTtm == VTD_TTM_RSVD)
2621 dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
2622 else
2623 {
2624 Assert(offQueueTail >= cbQueue);
2625 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
2626 }
2627 }
2628 }
2629 }
2630 DMAR_UNLOCK(pDevIns, pThisR3);
2631 }
2632
2633 RTMemFree(pvRequests);
2634 pvRequests = NULL;
2635
2636 LogFlowFunc(("Invalidation-queue thread terminating\n"));
2637 return VINF_SUCCESS;
2638}
2639
2640
2641/**
2642 * Wakes up the invalidation-queue thread so it can respond to a state
2643 * change.
2644 *
2645 * @returns VBox status code.
2646 * @param pDevIns The IOMMU device instance.
2647 * @param pThread The invalidation-queue thread.
2648 *
2649 * @thread EMT.
2650 */
2651static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2652{
2653 RT_NOREF(pThread);
2654 LogFlowFunc(("\n"));
2655 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2656 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
2657}
2658
2659
2660/**
2661 * @callback_method_impl{FNDBGFHANDLERDEV}
2662 */
2663static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
2664{
2665 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2666 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2667 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
2668
2669 /*
2670 * We lock the device to get a consistent register state as it is
2671 * ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
2672 * ones we care about here) into temporaries and release the lock ASAP.
2673 *
2674 * Order of register being read and outputted is in accordance with the
2675 * spec. for no particular reason.
2676 * See Intel VT-d spec. 10.4 "Register Descriptions".
2677 */
2678 DMAR_LOCK(pDevIns, pThisR3);
2679
2680 DMARDIAG const enmDiag = pThis->enmDiag;
2681 uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
2682 uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
2683 uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
2684 uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
2685 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2686 uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
2687 uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
2688 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
2689 uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
2690 uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
2691 uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
2692 uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
2693 uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
2694 uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
2695 uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
2696 uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
2697 uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
2698 uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
2699 uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
2700 uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
2701 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2702 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
2703 uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
2704 uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
2705 uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
2706 uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
2707 uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
2708 uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
2709 uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
2710 uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
2711 uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
2712 uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
2713 uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
2714 uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
2715 uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
2716 uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
2717 uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
2718 uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
2719
2720 DMAR_UNLOCK(pDevIns, pThisR3);
2721
2722 const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
2723 pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
2724 pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
2725
2726 /*
2727 * Non-verbose output.
2728 */
2729 if (!fVerbose)
2730 {
2731 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2732 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2733 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2734 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2735 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2736 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2737 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2738 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2739 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2740 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2741 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2742 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2743 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2744 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2745 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2746 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2747 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2748 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2749 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2750 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2751 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2752 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2753 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2754 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2755 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2756 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2757 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2758 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2759 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2760 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2761 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2762 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2763 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2764 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2765 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2766 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2767 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2768 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2769 pHlp->pfnPrintf(pHlp, "\n");
2770 return;
2771 }
2772
2773 /*
2774 * Verbose output.
2775 */
2776 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
2777 {
2778 pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
2779 pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
2780 }
2781 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
2782 {
2783 uint8_t const uSagaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW);
2784 uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
2785 uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
2786 pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
2787 pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
2788 pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
2789 pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
2790 pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
2791 pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
2792 pHlp->pfnPrintf(pHlp, " SAGAW = %#x (%u bits)\n", uSagaw, vtdCapRegGetSagawBits(uSagaw));
2793 pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
2794 pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
2795 pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
2796 pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
2797 pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
2798 pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
2799 pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
2800 pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
2801 pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
2802 pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
2803 pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
2804 pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
2805 pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
2806 pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
2807 }
2808 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
2809 {
2810 uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
2811 pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
2812 pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
2813 pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
2814 pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
2815 pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
2816 pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
2817 pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
2818 pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
2819 pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
2820 pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
2821 pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
2822 pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
2823 pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
2824 pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
2825 pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
2826 pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
2827 pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
2828 pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
2829 pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
2830 pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
2831 pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
2832 pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
2833 pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
2834 pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
2835 pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
2836 pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
2837 pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
2838 pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
2839 pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
2840 }
2841 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
2842 {
2843 uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
2844 pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
2845 pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
2846 pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
2847 pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
2848 pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
2849 pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2850 pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
2851 pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
2852 pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
2853 }
2854 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
2855 {
2856 uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
2857 pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
2858 pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
2859 pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
2860 pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
2861 pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
2862 pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
2863 pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
2864 pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
2865 pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
2866 }
2867 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
2868 {
2869 uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2870 pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
2871 pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
2872 }
2873 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
2874 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
2875 {
2876 pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
2877 pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
2878 pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
2879 pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
2880 pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
2881 pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
2882 pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
2883 pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
2884 }
2885 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
2886 {
2887 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
2888 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
2889 }
2890 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
2891 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
2892 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
2893 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
2894 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
2895 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
2896 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
2897 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
2898 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
2899 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
2900 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
2901 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
2902 {
2903 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2904 uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
2905 uint8_t const cQueuePages = 1 << fQs;
2906 pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
2907 pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
2908 }
2909 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
2910 {
2911 pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
2912 }
2913 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
2914 {
2915 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
2916 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
2917 }
2918 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
2919 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
2920 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
2921 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
2922 {
2923 pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
2924 pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
2925 pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
2926 }
2927 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
2928 {
2929 uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2930 uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
2931 pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
2932 pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
2933 pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
2934 }
2935 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
2936 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
2937 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
2938 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
2939 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
2940 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
2941 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
2942 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
2943 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
2944 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
2945 pHlp->pfnPrintf(pHlp, "\n");
2946}
2947
2948
2949/**
2950 * Initializes all registers in the DMAR unit.
2951 *
2952 * @param pDevIns The IOMMU device instance.
2953 */
2954static void dmarR3RegsInit(PPDMDEVINS pDevIns)
2955{
2956 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2957
2958 /*
2959 * Wipe all registers (required on reset).
2960 */
2961 RT_ZERO(pThis->abRegs0);
2962 RT_ZERO(pThis->abRegs1);
2963
2964 /*
2965 * Initialize registers not mutable by software prior to initializing other registers.
2966 */
2967 /* VER_REG */
2968 {
2969 pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
2970 | RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
2971 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
2972 }
2973
2974 uint8_t const fFlts = 1; /* First-Level translation support. */
2975 uint8_t const fSlts = 1; /* Second-Level translation support. */
2976 uint8_t const fPt = 1; /* Pass-Through support. */
2977 uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
2978 uint8_t const fNest = 0; /* Nested translation support. */
2979
2980 /* CAP_REG */
2981 {
2982 uint8_t cGstPhysAddrBits;
2983 uint8_t cGstLinearAddrBits;
2984 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
2985
2986 uint8_t const fFl1gp = 1; /* First-Level 1GB pages support. */
2987 uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
2988 uint8_t const fSl2mp = fSlts & 1; /* Second-Level 2MB pages support. */
2989 uint8_t const fSl2gp = fSlts & 1; /* Second-Level 1GB pages support. */
2990 uint8_t const fSllps = fSl2mp /* Second-Level large page Support. */
2991 | ((fSl2mp & fFl1gp) & RT_BIT(1));
2992 uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
2993 : X86_PAGE_2M_SHIFT)
2994 - X86_PAGE_4K_SHIFT;
2995 uint8_t const fNd = 2; /* Number of domains supported (0=16, 1=64, 2=256, 3=1K, 4=4K,
2996 5=16K, 6=64K, 7=Reserved). */
2997 uint8_t const fPsi = 1; /* Page selective invalidation. */
2998 uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
2999 uint8_t const uSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3000 uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3001 uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3002 uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3003
3004 pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3005 | RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3006 | RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3007 | RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3008 | RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3009 | RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3010 | RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & uSagaw)
3011 | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3012 | RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3013 | RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3014 | RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3015 | RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3016 | RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3017 | RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3018 | RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3019 | RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3020 | RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3021 | RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3022 | RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3023 | RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3024 | RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3025 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3026 }
3027
3028 /* ECAP_REG */
3029 {
3030 uint8_t const fQi = 1; /* Queued-invalidations. */
3031 uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3032 uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3033 uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3034 uint8_t const fEim = 1; /* Extended interrupt mode.*/
3035 uint8_t const fAdms = 1; /* Abort DMA mode support. */
3036
3037 pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3038 | RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3039 | RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3040 | RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3041 | RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3042 | RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3043 | RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3044 | RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3045 | RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3046 | RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3047 | RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3048 | RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3049 | RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, 0) /* Execute request not supported. */
3050 | RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3051 | RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3052 | RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
3053 | RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3054 | RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
3055 | RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3056 | RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3057 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3058 | RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3059 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3060 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3061 | RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3062 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3063 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3064 | RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3065 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3066 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3067 }
3068
3069 /*
3070 * Initialize registers mutable by software.
3071 */
3072 /* FECTL_REG */
3073 {
3074 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3075 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3076 }
3077
3078 /* ICETL_REG */
3079 {
3080 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3081 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3082 }
3083
3084#ifdef VBOX_STRICT
3085 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3086 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3087#endif
3088}
3089
3090
3091/**
3092 * @interface_method_impl{PDMDEVREG,pfnReset}
3093 */
3094static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
3095{
3096 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3097 LogFlowFunc(("\n"));
3098
3099 DMAR_LOCK(pDevIns, pThisR3);
3100 dmarR3RegsInit(pDevIns);
3101 DMAR_UNLOCK(pDevIns, pThisR3);
3102}
3103
3104
3105/**
3106 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3107 */
3108static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
3109{
3110 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3111 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3112 LogFlowFunc(("\n"));
3113
3114 DMAR_LOCK(pDevIns, pThisR3);
3115
3116 if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
3117 {
3118 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
3119 pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
3120 }
3121
3122 DMAR_UNLOCK(pDevIns, pThisR3);
3123 return VINF_SUCCESS;
3124}
3125
3126
3127/**
3128 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3129 */
3130static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3131{
3132 RT_NOREF(pCfg);
3133
3134 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3135 PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
3136 pThisR3->pDevInsR3 = pDevIns;
3137
3138 LogFlowFunc(("iInstance=%d\n", iInstance));
3139 NOREF(iInstance);
3140
3141 /*
3142 * Register the IOMMU with PDM.
3143 */
3144 PDMIOMMUREGR3 IommuReg;
3145 RT_ZERO(IommuReg);
3146 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3147 IommuReg.pfnMemAccess = iommuIntelMemAccess;
3148 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3149 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3150 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3151 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3152 if (RT_FAILURE(rc))
3153 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3154 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3155 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3156 N_("IOMMU helper version mismatch; got %#x expected %#x"),
3157 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3158 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3159 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3160 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3161 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3162 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
3163 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
3164 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
3165 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
3166
3167 /*
3168 * Use PDM's critical section (via helpers) for the IOMMU device.
3169 */
3170 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3171 AssertRCReturn(rc, rc);
3172
3173 /*
3174 * Initialize PCI configuration registers.
3175 */
3176 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3177 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3178
3179 /* Header. */
3180 PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3181 PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3182 PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3183 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
3184 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
3185 PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
3186 PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3187 PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3188
3189 /** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
3190 PDMPciDevSetStatus(pPciDev, 0);
3191 PDMPciDevSetCapabilityList(pPciDev, 0);
3192
3193 /** @todo VTBAR at 0x180? */
3194
3195 /*
3196 * Register the PCI function with PDM.
3197 */
3198 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3199 AssertLogRelRCReturn(rc, rc);
3200
3201 /** @todo Register MSI but what's the MSI capability offset? */
3202#if 0
3203 /*
3204 * Register MSI support for the PCI device.
3205 * This must be done -after- registering it as a PCI device!
3206 */
3207#endif
3208
3209 /*
3210 * Register MMIO region.
3211 */
3212 AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
3213 rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
3214 IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
3215 &pThis->hMmio);
3216 AssertLogRelRCReturn(rc, rc);
3217
3218 /*
3219 * Register debugger info items.
3220 */
3221 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
3222 AssertLogRelRCReturn(rc, rc);
3223
3224#ifdef VBOX_WITH_STATISTICS
3225 /*
3226 * Statistics.
3227 */
3228 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
3229 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
3230
3231 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
3232 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
3233
3234 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
3235 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
3236 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
3237 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
3238
3239 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
3240 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
3241
3242 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
3243 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
3244
3245 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
3246 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
3247
3248 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
3249 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
3250
3251 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
3252 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
3253 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
3254 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
3255 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
3256 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
3257 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
3258 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
3259#endif
3260
3261 /*
3262 * Initialize registers.
3263 */
3264 dmarR3RegsInit(pDevIns);
3265
3266 /*
3267 * Create invalidation-queue thread and semaphore.
3268 */
3269 char szInvQueueThread[32];
3270 RT_ZERO(szInvQueueThread);
3271 RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
3272 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
3273 0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
3274 AssertLogRelRCReturn(rc, rc);
3275
3276 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
3277 AssertLogRelRCReturn(rc, rc);
3278
3279 /*
3280 * Log some of the features exposed to software.
3281 */
3282 uint32_t const uVerReg = pThis->uVerReg;
3283 uint8_t const cMaxGstAddrBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
3284 uint8_t const cSupGstAddrBits = vtdCapRegGetSagawBits(RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW));
3285 uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
3286 uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
3287 LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%u bits, FRO=%#x, IRO=%#x) mapped at %#RGp\n",
3288 DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
3289 pThis->fCapReg, pThis->fExtCapReg, cMaxGstAddrBits, cSupGstAddrBits, offFrcd, offIva, DMAR_MMIO_BASE_PHYSADDR));
3290
3291 return VINF_SUCCESS;
3292}
3293
3294#else
3295
3296/**
3297 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
3298 */
3299static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
3300{
3301 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3302 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3303 PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
3304 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
3305
3306 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
3307 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3308 AssertRCReturn(rc, rc);
3309
3310 /* Set up the MMIO RZ handlers. */
3311 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
3312 AssertRCReturn(rc, rc);
3313
3314 /* Set up the IOMMU RZ callbacks. */
3315 PDMIOMMUREGCC IommuReg;
3316 RT_ZERO(IommuReg);
3317 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3318 IommuReg.idxIommu = pThis->idxIommu;
3319 IommuReg.pfnMemAccess = iommuIntelMemAccess;
3320 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3321 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3322 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3323
3324 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
3325 AssertRCReturn(rc, rc);
3326 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
3327 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
3328 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
3329 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
3330 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
3331 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
3332 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
3333
3334 return VINF_SUCCESS;
3335}
3336
3337#endif
3338
3339
3340/**
3341 * The device registration structure.
3342 */
3343PDMDEVREG const g_DeviceIommuIntel =
3344{
3345 /* .u32Version = */ PDM_DEVREG_VERSION,
3346 /* .uReserved0 = */ 0,
3347 /* .szName = */ "iommu-intel",
3348 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
3349 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
3350 /* .cMaxInstances = */ 1,
3351 /* .uSharedVersion = */ 42,
3352 /* .cbInstanceShared = */ sizeof(DMAR),
3353 /* .cbInstanceCC = */ sizeof(DMARCC),
3354 /* .cbInstanceRC = */ sizeof(DMARRC),
3355 /* .cMaxPciDevices = */ 1,
3356 /* .cMaxMsixVectors = */ 0,
3357 /* .pszDescription = */ "IOMMU (Intel)",
3358#if defined(IN_RING3)
3359 /* .pszRCMod = */ "VBoxDDRC.rc",
3360 /* .pszR0Mod = */ "VBoxDDR0.r0",
3361 /* .pfnConstruct = */ iommuIntelR3Construct,
3362 /* .pfnDestruct = */ iommuIntelR3Destruct,
3363 /* .pfnRelocate = */ NULL,
3364 /* .pfnMemSetup = */ NULL,
3365 /* .pfnPowerOn = */ NULL,
3366 /* .pfnReset = */ iommuIntelR3Reset,
3367 /* .pfnSuspend = */ NULL,
3368 /* .pfnResume = */ NULL,
3369 /* .pfnAttach = */ NULL,
3370 /* .pfnDetach = */ NULL,
3371 /* .pfnQueryInterface = */ NULL,
3372 /* .pfnInitComplete = */ NULL,
3373 /* .pfnPowerOff = */ NULL,
3374 /* .pfnSoftReset = */ NULL,
3375 /* .pfnReserved0 = */ NULL,
3376 /* .pfnReserved1 = */ NULL,
3377 /* .pfnReserved2 = */ NULL,
3378 /* .pfnReserved3 = */ NULL,
3379 /* .pfnReserved4 = */ NULL,
3380 /* .pfnReserved5 = */ NULL,
3381 /* .pfnReserved6 = */ NULL,
3382 /* .pfnReserved7 = */ NULL,
3383#elif defined(IN_RING0)
3384 /* .pfnEarlyConstruct = */ NULL,
3385 /* .pfnConstruct = */ iommuIntelRZConstruct,
3386 /* .pfnDestruct = */ NULL,
3387 /* .pfnFinalDestruct = */ NULL,
3388 /* .pfnRequest = */ NULL,
3389 /* .pfnReserved0 = */ NULL,
3390 /* .pfnReserved1 = */ NULL,
3391 /* .pfnReserved2 = */ NULL,
3392 /* .pfnReserved3 = */ NULL,
3393 /* .pfnReserved4 = */ NULL,
3394 /* .pfnReserved5 = */ NULL,
3395 /* .pfnReserved6 = */ NULL,
3396 /* .pfnReserved7 = */ NULL,
3397#elif defined(IN_RC)
3398 /* .pfnConstruct = */ iommuIntelRZConstruct,
3399 /* .pfnReserved0 = */ NULL,
3400 /* .pfnReserved1 = */ NULL,
3401 /* .pfnReserved2 = */ NULL,
3402 /* .pfnReserved3 = */ NULL,
3403 /* .pfnReserved4 = */ NULL,
3404 /* .pfnReserved5 = */ NULL,
3405 /* .pfnReserved6 = */ NULL,
3406 /* .pfnReserved7 = */ NULL,
3407#else
3408# error "Not in IN_RING3, IN_RING0 or IN_RC!"
3409#endif
3410 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
3411};
3412
3413#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
3414
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