VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89418

Last change on this file since 89418 was 89418, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Address translation, WIP.
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1/* $Id: DevIommuIntel.cpp 89418 2021-06-01 06:52:41Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - Intel implementation.
4 */
5
6/*
7 * Copyright (C) 2021 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include "VBoxDD.h"
24#include "DevIommuIntel.h"
25
26#include <iprt/mem.h>
27#include <iprt/string.h>
28
29
30/*********************************************************************************************************************************
31* Defined Constants And Macros *
32*********************************************************************************************************************************/
33/** Gets the low uint32_t of a uint64_t or something equivalent.
34 *
35 * This is suitable for casting constants outside code (since RT_LO_U32 can't be
36 * used as it asserts for correctness when compiling on certain compilers). */
37#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39/** Gets the high uint32_t of a uint64_t or something equivalent.
40 *
41 * This is suitable for casting constants outside code (since RT_HI_U32 can't be
42 * used as it asserts for correctness when compiling on certain compilers). */
43#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45/** Asserts MMIO access' offset and size are valid or returns appropriate error
46 * code suitable for returning from MMIO access handlers. */
47#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48 do { \
49 AssertReturn((a_cb) == 4 || (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50 AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51 } while (0)
52
53/** Checks if the MMIO offset is valid. */
54#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55 || (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57/** Gets the page offset mask given the number of bits to shift. */
58#define DMAR_GET_PAGE_OFF_MASK(a_cShift) (~(UINT64_C(0xffffffffffffffff) << (a_cShift)))
59
60/** Acquires the DMAR lock but returns with the given busy error code on failure. */
61#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
62 do { \
63 if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
64 { /* likely */ } \
65 else \
66 return (a_rcBusy); \
67 } while (0)
68
69/** Acquires the DMAR lock (not expected to fail). */
70#ifdef IN_RING3
71# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
72#else
73# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
74 do { \
75 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
76 AssertRC(rcLock); \
77 } while (0)
78#endif
79
80/** Release the DMAR lock. */
81#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
82
83/** Asserts that the calling thread owns the DMAR lock. */
84#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
85 do { \
86 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
87 RT_NOREF1(a_pThisCC); \
88 } while (0)
89
90/** Asserts that the calling thread does not own the DMAR lock. */
91#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
92 do { \
93 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
94 RT_NOREF1(a_pThisCC); \
95 } while (0)
96
97/** The number of fault recording registers our implementation supports.
98 * Normal guest operation shouldn't trigger faults anyway, so we only support the
99 * minimum number of registers (which is 1).
100 *
101 * See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
102#define DMAR_FRCD_REG_COUNT UINT32_C(1)
103
104/** Offset of first register in group 0. */
105#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
106/** Offset of last register in group 0 (inclusive). */
107#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
108/** Last valid offset in group 0 (exclusive). */
109#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
110/** Size of the group 0 (in bytes). */
111#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
112/**< Implementation-specific MMIO offset of IVA_REG. */
113#define DMAR_MMIO_OFF_IVA_REG 0xe50
114/**< Implementation-specific MMIO offset of IOTLB_REG. */
115#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
116/**< Implementation-specific MMIO offset of FRCD_LO_REG. */
117#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
118/**< Implementation-specific MMIO offset of FRCD_HI_REG. */
119#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
120AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
121
122/** Offset of first register in group 1. */
123#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
124/** Offset of last register in group 1 (inclusive). */
125#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
126/** Last valid offset in group 1 (exclusive). */
127#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
128/** Size of the group 1 (in bytes). */
129#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
130
131/** DMAR implementation's major version number (exposed to software).
132 * We report 6 as the major version since we support queued-invalidations as
133 * software may make assumptions based on that.
134 *
135 * See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
136#define DMAR_VER_MAJOR 6
137/** DMAR implementation's minor version number (exposed to software). */
138#define DMAR_VER_MINOR 0
139
140/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
141 * 7=Reserved). */
142#define DMAR_ND 6
143
144/** @name DMAR_PERM_XXX: DMA request permissions.
145 * The order of R, W, X bits is important as it corresponds to those bits in
146 * page-table entries.
147 *
148 * @{ */
149/** DMA request permission: Read. */
150#define DMAR_PERM_READ RT_BIT(0)
151/** DMA request permission: Write. */
152#define DMAR_PERM_WRITE RT_BIT(1)
153/** DMA request permission: Execute (ER). */
154#define DMAR_PERM_EXE RT_BIT(2)
155/** DMA request permission: Supervisor privilege (PR). */
156#define DMAR_PERM_PRIV RT_BIT(3)
157/** DMA request permissions: All. */
158#define DMAR_PERM_ALL (DMAR_PERM_READ | DMAR_PERM_WRITE | DMAR_PERM_EXE | DMAR_PERM_PRIV)
159/** @} */
160
161/** Release log prefix string. */
162#define DMAR_LOG_PFX "Intel-IOMMU"
163/** The current saved state version. */
164#define DMAR_SAVED_STATE_VERSION 1
165
166
167/*********************************************************************************************************************************
168* Structures and Typedefs *
169*********************************************************************************************************************************/
170/**
171 * DMAR error diagnostics.
172 * Sorted alphabetically so it's easier to add and locate items, no other reason.
173 *
174 * @note Members of this enum are used as array indices, so no gaps in enum
175 * values are not allowed. Update g_apszDmarDiagDesc when you modify
176 * fields in this enum.
177 */
178typedef enum
179{
180 /* No error, this must be zero! */
181 kDmarDiag_None = 0,
182
183 /* Address Translation Faults. */
184 kDmarDiag_Atf_Lct_1,
185 kDmarDiag_Atf_Lct_2,
186 kDmarDiag_Atf_Lct_3,
187 kDmarDiag_Atf_Lct_4_1,
188 kDmarDiag_Atf_Lct_4_2,
189 kDmarDiag_Atf_Lct_4_3,
190 kDmarDiag_Atf_Lct_5,
191 kDmarDiag_Atf_Lgn_1_1,
192 kDmarDiag_Atf_Lgn_1_2,
193 kDmarDiag_Atf_Lgn_1_3,
194 kDmarDiag_Atf_Lrt_1,
195 kDmarDiag_Atf_Lrt_2,
196 kDmarDiag_Atf_Lrt_3,
197 kDmarDiag_Atf_Lsl_1,
198 kDmarDiag_Atf_Lsl_2,
199 kDmarDiag_Atf_Lsl_2_LargePage,
200 kDmarDiag_Atf_Rta_1_1,
201 kDmarDiag_Atf_Rta_1_2,
202 kDmarDiag_Atf_Rta_1_3,
203 kDmarDiag_Atf_Sgn_5,
204 kDmarDiag_Atf_Ssl_1,
205 kDmarDiag_Atf_Ssl_2,
206 kDmarDiag_Atf_Ssl_3,
207 kDmarDiag_Atf_Ssl_3_LargePage,
208
209 /* CCMD_REG faults. */
210 kDmarDiag_CcmdReg_NotSupported,
211 kDmarDiag_CcmdReg_Qi_Enabled,
212 kDmarDiag_CcmdReg_Ttm_Invalid,
213
214 /* IQA_REG faults. */
215 kDmarDiag_IqaReg_Dsc_Fetch_Error,
216 kDmarDiag_IqaReg_Dw_128_Invalid,
217 kDmarDiag_IqaReg_Dw_256_Invalid,
218
219 /* Invalidation Queue Error Info. */
220 kDmarDiag_Iqei_Dsc_Type_Invalid,
221 kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
222 kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
223 kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
224 kDmarDiag_Iqei_Ttm_Rsvd,
225
226 /* IQT_REG faults. */
227 kDmarDiag_IqtReg_Qt_Invalid,
228 kDmarDiag_IqtReg_Qt_NotAligned,
229
230 /* Compatibility Format Interrupt Faults. */
231 kDmarDiag_Ir_Cfi_Blocked,
232
233 /* Remappable Format Interrupt Faults. */
234 kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
235 kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
236 kDmarDiag_Ir_Rfi_Irte_Not_Present,
237 kDmarDiag_Ir_Rfi_Irte_Read_Failed,
238 kDmarDiag_Ir_Rfi_Irte_Rsvd,
239 kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
240 kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
241 kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
242 kDmarDiag_Ir_Rfi_Rsvd,
243
244 /* Member for determining array index limit. */
245 kDmarDiag_End,
246
247 /* Usual 32-bit type size hack. */
248 kDmarDiag_32Bit_Hack = 0x7fffffff
249} DMARDIAG;
250AssertCompileSize(DMARDIAG, 4);
251
252/** DMAR diagnostic enum description expansion.
253 * The below construct ensures typos in the input to this macro are caught
254 * during compile time. */
255#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
256
257/** DMAR diagnostics description for members in DMARDIAG. */
258static const char *const g_apszDmarDiagDesc[] =
259{
260 DMARDIAG_DESC(None ),
261 DMARDIAG_DESC(Atf_Lct_1 ),
262 DMARDIAG_DESC(Atf_Lct_2 ),
263 DMARDIAG_DESC(Atf_Lct_3 ),
264 DMARDIAG_DESC(Atf_Lct_4_1 ),
265 DMARDIAG_DESC(Atf_Lct_4_2 ),
266 DMARDIAG_DESC(Atf_Lct_4_3 ),
267 DMARDIAG_DESC(Atf_Lct_5 ),
268 DMARDIAG_DESC(Atf_Lgn_1_1 ),
269 DMARDIAG_DESC(Atf_Lgn_1_2 ),
270 DMARDIAG_DESC(Atf_Lgn_1_3 ),
271 DMARDIAG_DESC(Atf_Lrt_1 ),
272 DMARDIAG_DESC(Atf_Lrt_2 ),
273 DMARDIAG_DESC(Atf_Lrt_3 ),
274 DMARDIAG_DESC(Atf_Lsl_1 ),
275 DMARDIAG_DESC(Atf_Lsl_2 ),
276 DMARDIAG_DESC(Atf_Lsl_2_LargePage ),
277 DMARDIAG_DESC(Atf_Rta_1_1 ),
278 DMARDIAG_DESC(Atf_Rta_1_2 ),
279 DMARDIAG_DESC(Atf_Rta_1_3 ),
280 DMARDIAG_DESC(Atf_Sgn_5 ),
281 DMARDIAG_DESC(Atf_Ssl_1 ),
282 DMARDIAG_DESC(Atf_Ssl_2 ),
283 DMARDIAG_DESC(Atf_Ssl_3 ),
284 DMARDIAG_DESC(Atf_Ssl_3_LargePage ),
285 DMARDIAG_DESC(CcmdReg_NotSupported ),
286 DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
287 DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
288 DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
289 DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
290 DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
291 DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
292 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
293 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
294 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
295 DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
296 DMARDIAG_DESC(IqtReg_Qt_Invalid ),
297 DMARDIAG_DESC(IqtReg_Qt_NotAligned ),
298 DMARDIAG_DESC(Ir_Cfi_Blocked ),
299 DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
300 DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
301 DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
302 DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
303 DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
304 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
305 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
306 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
307 DMARDIAG_DESC(Ir_Rfi_Rsvd ),
308 /* kDmarDiag_End */
309};
310AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
311#undef DMARDIAG_DESC
312
313/**
314 * The shared DMAR device state.
315 */
316typedef struct DMAR
317{
318 /** IOMMU device index. */
319 uint32_t idxIommu;
320 /** DMAR magic. */
321 uint32_t u32Magic;
322
323 /** Registers (group 0). */
324 uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
325 /** Registers (group 1). */
326 uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
327
328 /** @name Lazily activated registers.
329 * These are the active values for lazily activated registers. Software is free to
330 * modify the actual register values while remapping/translation is enabled but they
331 * take effect only when explicitly signaled by software, hence we need to hold the
332 * active values separately.
333 * @{ */
334 /** Currently active IRTA_REG. */
335 uint64_t uIrtaReg;
336 /** Currently active RTADDR_REG. */
337 uint64_t uRtaddrReg;
338 /** @} */
339
340 /** @name Register copies for a tiny bit faster and more convenient access.
341 * @{ */
342 /** Copy of VER_REG. */
343 uint8_t uVerReg;
344 /** Alignment. */
345 uint8_t abPadding[7];
346 /** Copy of CAP_REG. */
347 uint64_t fCapReg;
348 /** Copy of ECAP_REG. */
349 uint64_t fExtCapReg;
350 /** @} */
351
352 /** Host-address width (HAW) base address mask. */
353 uint64_t fHawBaseMask;
354 /** Maximum guest-address width (MGAW) invalid address mask. */
355 uint64_t fInvMgawMask;
356 /** Maximum supported paging level (3, 4 or 5). */
357 uint8_t cMaxPagingLevel;
358 /** DMA request valid permissions mask. */
359 uint8_t fPermValidMask;
360
361 /** The event semaphore the invalidation-queue thread waits on. */
362 SUPSEMEVENT hEvtInvQueue;
363 /** Padding. */
364 uint32_t uPadding0;
365 /** Error diagnostic. */
366 DMARDIAG enmDiag;
367 /** The MMIO handle. */
368 IOMMMIOHANDLE hMmio;
369
370#ifdef VBOX_WITH_STATISTICS
371 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
372 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
373 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
374 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
375
376 STAMCOUNTER StatMsiRemapCfiR3; /**< Number of compatibility-format interrupts remap requests in R3. */
377 STAMCOUNTER StatMsiRemapCfiRZ; /**< Number of compatibility-format interrupts remap requests in RZ. */
378 STAMCOUNTER StatMsiRemapRfiR3; /**< Number of remappable-format interrupts remap requests in R3. */
379 STAMCOUNTER StatMsiRemapRfiRZ; /**< Number of remappable-format interrupts remap requests in RZ. */
380
381 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
382 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
383 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
384 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
385
386 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
387 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
388 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
389 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
390
391 STAMCOUNTER StatCcInvDsc; /**< Number of Context-cache descriptors processed. */
392 STAMCOUNTER StatIotlbInvDsc; /**< Number of IOTLB descriptors processed. */
393 STAMCOUNTER StatDevtlbInvDsc; /**< Number of Device-TLB descriptors processed. */
394 STAMCOUNTER StatIecInvDsc; /**< Number of Interrupt-Entry cache descriptors processed. */
395 STAMCOUNTER StatInvWaitDsc; /**< Number of Invalidation wait descriptors processed. */
396 STAMCOUNTER StatPasidIotlbInvDsc; /**< Number of PASID-based IOTLB descriptors processed. */
397 STAMCOUNTER StatPasidCacheInvDsc; /**< Number of PASID-cache descriptors processed. */
398 STAMCOUNTER StatPasidDevtlbInvDsc; /**< Number of PASID-based device-TLB descriptors processed. */
399#endif
400} DMAR;
401/** Pointer to the DMAR device state. */
402typedef DMAR *PDMAR;
403/** Pointer to the const DMAR device state. */
404typedef DMAR const *PCDMAR;
405AssertCompileMemberAlignment(DMAR, abRegs0, 8);
406AssertCompileMemberAlignment(DMAR, abRegs1, 8);
407
408/**
409 * The ring-3 DMAR device state.
410 */
411typedef struct DMARR3
412{
413 /** Device instance. */
414 PPDMDEVINSR3 pDevInsR3;
415 /** The IOMMU helper. */
416 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
417 /** The invalidation-queue thread. */
418 R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
419} DMARR3;
420/** Pointer to the ring-3 DMAR device state. */
421typedef DMARR3 *PDMARR3;
422/** Pointer to the const ring-3 DMAR device state. */
423typedef DMARR3 const *PCDMARR3;
424
425/**
426 * The ring-0 DMAR device state.
427 */
428typedef struct DMARR0
429{
430 /** Device instance. */
431 PPDMDEVINSR0 pDevInsR0;
432 /** The IOMMU helper. */
433 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
434} DMARR0;
435/** Pointer to the ring-0 IOMMU device state. */
436typedef DMARR0 *PDMARR0;
437/** Pointer to the const ring-0 IOMMU device state. */
438typedef DMARR0 const *PCDMARR0;
439
440/**
441 * The raw-mode DMAR device state.
442 */
443typedef struct DMARRC
444{
445 /** Device instance. */
446 PPDMDEVINSRC pDevInsRC;
447 /** The IOMMU helper. */
448 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
449} DMARRC;
450/** Pointer to the raw-mode DMAR device state. */
451typedef DMARRC *PDMARRC;
452/** Pointer to the const raw-mode DMAR device state. */
453typedef DMARRC const *PCIDMARRC;
454
455/** The DMAR device state for the current context. */
456typedef CTX_SUFF(DMAR) DMARCC;
457/** Pointer to the DMAR device state for the current context. */
458typedef CTX_SUFF(PDMAR) PDMARCC;
459/** Pointer to the const DMAR device state for the current context. */
460typedef CTX_SUFF(PDMAR) const PCDMARCC;
461
462/**
463 * Type of DMAR originated events that generate interrupts.
464 */
465typedef enum DMAREVENTTYPE
466{
467 /** Invalidation completion event. */
468 DMAREVENTTYPE_INV_COMPLETE = 0,
469 /** Fault event. */
470 DMAREVENTTYPE_FAULT
471} DMAREVENTTYPE;
472
473/**
474 * I/O TLB entry.
475 */
476typedef struct DMARIOTLBE
477{
478 RTGCPHYS GCPhysBase;
479 uint8_t cShift;
480 uint8_t fPerm;
481 uint16_t idDomain;
482 uint16_t uPadding0;
483} DMARIOTLBE;
484/** Pointer to an IOTLB entry. */
485typedef DMARIOTLBE *PDMARIOTLBE;
486/** Pointer to a const IOTLB entry. */
487typedef DMARIOTLBE const *PCDMARIOTLBE;
488
489/**
490 * DMA Address Remapping Information.
491 */
492typedef struct DMARADDRMAP
493{
494 /** The device ID (bus, device, function). */
495 uint16_t idDevice;
496 /** The requested permissions (DMAR_PERM_XXX). */
497 uint8_t fReqPerm;
498 /** The fault processing disabled (FPD) bit. */
499 uint8_t fFpd;
500 /** The PASID if present, can be NIL_PCIPASID. */
501 PCIPASID Pasid;
502 /* The address type of the memory request. */
503 PCIADDRTYPE enmAddrType;
504 /** The type of the translation request. */
505 VTDREQTYPE enmReqType;
506 /** The table translation mode (VTD_TTM_XXX). */
507 uint8_t fTtm;
508 uint8_t uPadding[7];
509 /** The DMA address being accessed. */
510 uint64_t uDmaAddr;
511 /** The size of the DMA access (in bytes). */
512 size_t cbDma;
513
514 /** The IOTLBE for this remapping. */
515 DMARIOTLBE Iotlbe;
516 /** The size of the contiguous translated region (in bytes). */
517 size_t cbContiguous;
518} DMARADDRMAP;
519/** Pointer to a DMA address remapping object. */
520typedef DMARADDRMAP *PDMARADDRMAP;
521/** Pointer to a const DMA address remapping object. */
522typedef DMARADDRMAP const *PCDMARADDRMAP;
523
524
525/*********************************************************************************************************************************
526* Global Variables *
527*********************************************************************************************************************************/
528/**
529 * Read-write masks for DMAR registers (group 0).
530 */
531static uint32_t const g_au32RwMasks0[] =
532{
533 /* Offset Register Low High */
534 /* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
535 /* 0x004 Reserved */ 0,
536 /* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
537 /* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
538 /* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
539 /* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
540 /* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
541 /* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
542 /* 0x030 Reserved */ 0,
543 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
544 /* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
545 /* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
546 /* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
547 /* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
548 /* 0x048 Reserved */ 0, 0,
549 /* 0x050 Reserved */ 0, 0,
550 /* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
551 /* 0x060 Reserved */ 0,
552 /* 0x064 PMEN_REG */ 0, /* RO as we don't support PLMR and PHMR. */
553 /* 0x068 PLMBASE_REG */ 0, /* RO as we don't support PLMR. */
554 /* 0x06c PLMLIMIT_REG */ 0, /* RO as we don't support PLMR. */
555 /* 0x070 PHMBASE_REG */ 0, 0, /* RO as we don't support PHMR. */
556 /* 0x078 PHMLIMIT_REG */ 0, 0, /* RO as we don't support PHMR. */
557 /* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
558 /* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
559 /* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
560 /* 0x098 Reserved */ 0,
561 /* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
562 /* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
563 /* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
564 /* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
565 /* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
566 /* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
567 /* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
568 /* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
569 /* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
570 /* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
571 /* 0x0d8 Reserved */ 0,
572 /* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
573 /* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
574 /* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
575 /* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
576 /* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
577 /* 0x0f0 Reserved */ 0, 0,
578 /* 0x0f8 Reserved */ 0, 0,
579 /* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
580 /* 0x108 MTRRDEF_REG */ 0, 0, /* RO as we don't support MTS. */
581 /* 0x110 Reserved */ 0, 0,
582 /* 0x118 Reserved */ 0, 0,
583 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0, /* RO as we don't support MTS. */
584 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
585 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
586 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
587 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
588 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
589 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
590 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
591 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
592 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
593 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
594 /* 0x178 Reserved */ 0, 0,
595 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0, /* RO as we don't support MTS. */
596 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
597 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
598 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
599 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
600 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
601 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
602 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
603 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
604 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
605 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
606 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
607 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
608 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
609 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
610 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
611 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
612 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
613 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
614 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
615};
616AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
617
618/**
619 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
620 */
621static uint32_t const g_au32Rw1cMasks0[] =
622{
623 /* Offset Register Low High */
624 /* 0x000 VER_REG */ 0,
625 /* 0x004 Reserved */ 0,
626 /* 0x008 CAP_REG */ 0, 0,
627 /* 0x010 ECAP_REG */ 0, 0,
628 /* 0x018 GCMD_REG */ 0,
629 /* 0x01c GSTS_REG */ 0,
630 /* 0x020 RTADDR_REG */ 0, 0,
631 /* 0x028 CCMD_REG */ 0, 0,
632 /* 0x030 Reserved */ 0,
633 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
634 /* 0x038 FECTL_REG */ 0,
635 /* 0x03c FEDATA_REG */ 0,
636 /* 0x040 FEADDR_REG */ 0,
637 /* 0x044 FEUADDR_REG */ 0,
638 /* 0x048 Reserved */ 0, 0,
639 /* 0x050 Reserved */ 0, 0,
640 /* 0x058 AFLOG_REG */ 0, 0,
641 /* 0x060 Reserved */ 0,
642 /* 0x064 PMEN_REG */ 0,
643 /* 0x068 PLMBASE_REG */ 0,
644 /* 0x06c PLMLIMIT_REG */ 0,
645 /* 0x070 PHMBASE_REG */ 0, 0,
646 /* 0x078 PHMLIMIT_REG */ 0, 0,
647 /* 0x080 IQH_REG */ 0, 0,
648 /* 0x088 IQT_REG */ 0, 0,
649 /* 0x090 IQA_REG */ 0, 0,
650 /* 0x098 Reserved */ 0,
651 /* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
652 /* 0x0a0 IECTL_REG */ 0,
653 /* 0x0a4 IEDATA_REG */ 0,
654 /* 0x0a8 IEADDR_REG */ 0,
655 /* 0x0ac IEUADDR_REG */ 0,
656 /* 0x0b0 IQERCD_REG */ 0, 0,
657 /* 0x0b8 IRTA_REG */ 0, 0,
658 /* 0x0c0 PQH_REG */ 0, 0,
659 /* 0x0c8 PQT_REG */ 0, 0,
660 /* 0x0d0 PQA_REG */ 0, 0,
661 /* 0x0d8 Reserved */ 0,
662 /* 0x0dc PRS_REG */ 0,
663 /* 0x0e0 PECTL_REG */ 0,
664 /* 0x0e4 PEDATA_REG */ 0,
665 /* 0x0e8 PEADDR_REG */ 0,
666 /* 0x0ec PEUADDR_REG */ 0,
667 /* 0x0f0 Reserved */ 0, 0,
668 /* 0x0f8 Reserved */ 0, 0,
669 /* 0x100 MTRRCAP_REG */ 0, 0,
670 /* 0x108 MTRRDEF_REG */ 0, 0,
671 /* 0x110 Reserved */ 0, 0,
672 /* 0x118 Reserved */ 0, 0,
673 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
674 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
675 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
676 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
677 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
678 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
679 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
680 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
681 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
682 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
683 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
684 /* 0x178 Reserved */ 0, 0,
685 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
686 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
687 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
688 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
689 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
690 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
691 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
692 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
693 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
694 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
695 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
696 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
697 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
698 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
699 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
700 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
701 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
702 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
703 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
704 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
705};
706AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
707
708/**
709 * Read-write masks for DMAR registers (group 1).
710 */
711static uint32_t const g_au32RwMasks1[] =
712{
713 /* Offset Register Low High */
714 /* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
715 /* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
716 /* 0xe10 VCMD_REG */ 0, 0, /* RO: VCS not supported. */
717 /* 0xe18 VCMDRSVD_REG */ 0, 0,
718 /* 0xe20 VCRSP_REG */ 0, 0, /* RO: VCS not supported. */
719 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
720 /* 0xe30 Reserved */ 0, 0,
721 /* 0xe38 Reserved */ 0, 0,
722 /* 0xe40 Reserved */ 0, 0,
723 /* 0xe48 Reserved */ 0, 0,
724 /* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
725 /* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
726 /* 0xe60 Reserved */ 0, 0,
727 /* 0xe68 Reserved */ 0, 0,
728 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
729 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
730};
731AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
732AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
733
734/**
735 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
736 */
737static uint32_t const g_au32Rw1cMasks1[] =
738{
739 /* Offset Register Low High */
740 /* 0xe00 VCCAP_REG */ 0, 0,
741 /* 0xe08 VCMD_EO_REG */ 0, 0,
742 /* 0xe10 VCMD_REG */ 0, 0,
743 /* 0xe18 VCMDRSVD_REG */ 0, 0,
744 /* 0xe20 VCRSP_REG */ 0, 0,
745 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
746 /* 0xe30 Reserved */ 0, 0,
747 /* 0xe38 Reserved */ 0, 0,
748 /* 0xe40 Reserved */ 0, 0,
749 /* 0xe48 Reserved */ 0, 0,
750 /* 0xe50 IVA_REG */ 0, 0,
751 /* 0xe58 IOTLB_REG */ 0, 0,
752 /* 0xe60 Reserved */ 0, 0,
753 /* 0xe68 Reserved */ 0, 0,
754 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
755 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
756};
757AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
758
759/** Array of RW masks for each register group. */
760static uint8_t const *g_apbRwMasks[] = { (uint8_t *)&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
761
762/** Array of RW1C masks for each register group. */
763static uint8_t const *g_apbRw1cMasks[] = { (uint8_t *)&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
764
765/* Masks arrays must be identical in size (even bounds checking code assumes this). */
766AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
767
768/** Array of valid domain-ID bits. */
769static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
770AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
771
772
773#ifndef VBOX_DEVICE_STRUCT_TESTCASE
774/** @todo Add IOMMU struct size/alignment verification, see
775 * Devices/testcase/Makefile.kmk and
776 * Devices/testcase/tstDeviceStructSize[RC].cpp */
777
778/**
779 * Returns the supported adjusted guest-address width (SAGAW) given the maximum
780 * guest address width (MGAW).
781 *
782 * @returns The CAP_REG.SAGAW value.
783 * @param uMgaw The CAP_REG.MGAW value.
784 */
785static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
786{
787 /*
788 * It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
789 * 5-level paging but not 4 or 3-level paging. So smaller page-table levels
790 * are always OR'ed in below.
791 *
792 * The bit values below (57, 48, 39 bits) represents the levels of page-table walks
793 * for 4KB base page size (5-level, 4-level and 3-level paging respectively).
794 *
795 * See Intel VT-d spec. 10.4.2 "Capability Register".
796 */
797 ++uMgaw;
798 uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) | RT_BIT(2) | RT_BIT(1)
799 : uMgaw >= 48 ? RT_BIT(2) | RT_BIT(1)
800 : uMgaw >= 39 ? RT_BIT(1)
801 : 0;
802 return fSagaw;
803}
804
805
806/**
807 * Returns the maximum supported paging level given the supported adjusted
808 * guest-address width (SAGAW) field.
809 *
810 * @returns The highest paging level supported, 0 if invalid.
811 * @param fSagaw The CAP_REG.SAGAW value.
812 */
813static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
814{
815 uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
816 : fSagaw & RT_BIT(2) ? 4
817 : fSagaw & RT_BIT(1) ? 3
818 : 0;
819 return cMaxPagingLevel;
820}
821
822
823/**
824 * Returns whether the interrupt remapping (IR) fault is qualified or not.
825 *
826 * @returns @c true if qualified, @c false otherwise.
827 * @param enmIrFault The interrupt remapping fault condition.
828 */
829static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
830{
831 switch (enmIrFault)
832 {
833 case VTDIRFAULT_IRTE_NOT_PRESENT:
834 case VTDIRFAULT_IRTE_PRESENT_RSVD:
835 case VTDIRFAULT_IRTE_PRESENT_INVALID:
836 case VTDIRFAULT_PID_READ_FAILED:
837 case VTDIRFAULT_PID_RSVD:
838 return true;
839 default:
840 return false;
841 }
842}
843
844
845/**
846 * Returns table translation mode's descriptive name.
847 *
848 * @returns The descriptive name.
849 * @param uTtm The RTADDR_REG.TTM value.
850 */
851static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
852{
853 Assert(!(uTtm & 3));
854 static const char* s_apszTtmNames[] =
855 {
856 "Legacy Mode",
857 "Scalable Mode",
858 "Reserved",
859 "Abort-DMA Mode"
860 };
861 return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
862}
863
864
865/**
866 * Gets the index of the group the register belongs to given its MMIO offset.
867 *
868 * @returns The group index.
869 * @param offReg The MMIO offset of the register.
870 * @param cbReg The size of the access being made (for bounds checking on
871 * debug builds).
872 */
873DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
874{
875 uint16_t const offLast = offReg + cbReg - 1;
876 AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
877 AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
878 return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
879}
880
881
882/**
883 * Gets the group the register belongs to given its MMIO offset.
884 *
885 * @returns Pointer to the first element of the register group.
886 * @param pThis The shared DMAR device state.
887 * @param offReg The MMIO offset of the register.
888 * @param cbReg The size of the access being made (for bounds checking on
889 * debug builds).
890 * @param pIdxGroup Where to store the index of the register group the register
891 * belongs to.
892 */
893DECLINLINE(uint8_t *) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
894{
895 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
896 uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
897 return apbRegs[*pIdxGroup];
898}
899
900
901/**
902 * Const/read-only version of dmarRegGetGroup.
903 *
904 * @copydoc dmarRegGetGroup
905 */
906DECLINLINE(uint8_t const*) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
907{
908 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
909 uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
910 return apbRegs[*pIdxGroup];
911}
912
913
914/**
915 * Writes a 32-bit register with the exactly the supplied value.
916 *
917 * @param pThis The shared DMAR device state.
918 * @param offReg The MMIO offset of the register.
919 * @param uReg The 32-bit value to write.
920 */
921static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
922{
923 uint8_t idxGroup;
924 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
925 NOREF(idxGroup);
926 *(uint32_t *)(pabRegs + offReg) = uReg;
927}
928
929
930/**
931 * Writes a 64-bit register with the exactly the supplied value.
932 *
933 * @param pThis The shared DMAR device state.
934 * @param offReg The MMIO offset of the register.
935 * @param uReg The 64-bit value to write.
936 */
937static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
938{
939 uint8_t idxGroup;
940 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
941 NOREF(idxGroup);
942 *(uint64_t *)(pabRegs + offReg) = uReg;
943}
944
945
946/**
947 * Reads a 32-bit register with exactly the value it contains.
948 *
949 * @returns The raw register value.
950 * @param pThis The shared DMAR device state.
951 * @param offReg The MMIO offset of the register.
952 */
953static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
954{
955 uint8_t idxGroup;
956 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
957 NOREF(idxGroup);
958 return *(uint32_t *)(pabRegs + offReg);
959}
960
961
962/**
963 * Reads a 64-bit register with exactly the value it contains.
964 *
965 * @returns The raw register value.
966 * @param pThis The shared DMAR device state.
967 * @param offReg The MMIO offset of the register.
968 */
969static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
970{
971 uint8_t idxGroup;
972 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
973 NOREF(idxGroup);
974 return *(uint64_t *)(pabRegs + offReg);
975}
976
977
978/**
979 * Reads a 32-bit register with exactly the value it contains along with their
980 * corresponding masks
981 *
982 * @param pThis The shared DMAR device state.
983 * @param offReg The MMIO offset of the register.
984 * @param puReg Where to store the raw 32-bit register value.
985 * @param pfRwMask Where to store the RW mask corresponding to this register.
986 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
987 */
988static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask)
989{
990 uint8_t idxGroup;
991 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
992 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
993 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
994 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
995 *puReg = *(uint32_t *)(pabRegs + offReg);
996 *pfRwMask = *(uint32_t *)(pabRwMasks + offReg);
997 *pfRw1cMask = *(uint32_t *)(pabRw1cMasks + offReg);
998}
999
1000
1001/**
1002 * Reads a 64-bit register with exactly the value it contains along with their
1003 * corresponding masks.
1004 *
1005 * @param pThis The shared DMAR device state.
1006 * @param offReg The MMIO offset of the register.
1007 * @param puReg Where to store the raw 64-bit register value.
1008 * @param pfRwMask Where to store the RW mask corresponding to this register.
1009 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1010 */
1011static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask)
1012{
1013 uint8_t idxGroup;
1014 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1015 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1016 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1017 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1018 *puReg = *(uint64_t *)(pabRegs + offReg);
1019 *pfRwMask = *(uint64_t *)(pabRwMasks + offReg);
1020 *pfRw1cMask = *(uint64_t *)(pabRw1cMasks + offReg);
1021}
1022
1023
1024/**
1025 * Writes a 32-bit register as it would be when written by software.
1026 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1027 *
1028 * @returns The value that's actually written to the register.
1029 * @param pThis The shared DMAR device state.
1030 * @param offReg The MMIO offset of the register.
1031 * @param uReg The 32-bit value to write.
1032 * @param puPrev Where to store the register value prior to writing.
1033 */
1034static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1035{
1036 /* Read current value from the 32-bit register. */
1037 uint32_t uCurReg;
1038 uint32_t fRwMask;
1039 uint32_t fRw1cMask;
1040 dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1041 *puPrev = uCurReg;
1042
1043 uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1044 uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1045 uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1046 uint32_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
1047
1048 /* Write new value to the 32-bit register. */
1049 dmarRegWriteRaw32(pThis, offReg, uNewReg);
1050 return uNewReg;
1051}
1052
1053
1054/**
1055 * Writes a 64-bit register as it would be when written by software.
1056 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1057 *
1058 * @returns The value that's actually written to the register.
1059 * @param pThis The shared DMAR device state.
1060 * @param offReg The MMIO offset of the register.
1061 * @param uReg The 64-bit value to write.
1062 * @param puPrev Where to store the register value prior to writing.
1063 */
1064static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1065{
1066 /* Read current value from the 64-bit register. */
1067 uint64_t uCurReg;
1068 uint64_t fRwMask;
1069 uint64_t fRw1cMask;
1070 dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1071 *puPrev = uCurReg;
1072
1073 uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1074 uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1075 uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1076 uint64_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
1077
1078 /* Write new value to the 64-bit register. */
1079 dmarRegWriteRaw64(pThis, offReg, uNewReg);
1080 return uNewReg;
1081}
1082
1083
1084/**
1085 * Reads a 32-bit register as it would be when read by software.
1086 *
1087 * @returns The register value.
1088 * @param pThis The shared DMAR device state.
1089 * @param offReg The MMIO offset of the register.
1090 */
1091static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1092{
1093 return dmarRegReadRaw32(pThis, offReg);
1094}
1095
1096
1097/**
1098 * Reads a 64-bit register as it would be when read by software.
1099 *
1100 * @returns The register value.
1101 * @param pThis The shared DMAR device state.
1102 * @param offReg The MMIO offset of the register.
1103 */
1104static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1105{
1106 return dmarRegReadRaw64(pThis, offReg);
1107}
1108
1109
1110/**
1111 * Modifies a 32-bit register.
1112 *
1113 * @param pThis The shared DMAR device state.
1114 * @param offReg The MMIO offset of the register.
1115 * @param fAndMask The AND mask (applied first).
1116 * @param fOrMask The OR mask.
1117 * @remarks This does NOT apply RO or RW1C masks while modifying the
1118 * register.
1119 */
1120static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1121{
1122 uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1123 uReg = (uReg & fAndMask) | fOrMask;
1124 dmarRegWriteRaw32(pThis, offReg, uReg);
1125}
1126
1127
1128/**
1129 * Modifies a 64-bit register.
1130 *
1131 * @param pThis The shared DMAR device state.
1132 * @param offReg The MMIO offset of the register.
1133 * @param fAndMask The AND mask (applied first).
1134 * @param fOrMask The OR mask.
1135 * @remarks This does NOT apply RO or RW1C masks while modifying the
1136 * register.
1137 */
1138static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1139{
1140 uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1141 uReg = (uReg & fAndMask) | fOrMask;
1142 dmarRegWriteRaw64(pThis, offReg, uReg);
1143}
1144
1145
1146/**
1147 * Checks if the invalidation-queue is empty.
1148 *
1149 * Extended version which optionally returns the current queue head and tail
1150 * offsets.
1151 *
1152 * @returns @c true if empty, @c false otherwise.
1153 * @param pThis The shared DMAR device state.
1154 * @param poffQh Where to store the queue head offset. Optional, can be NULL.
1155 * @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1156 */
1157static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t *poffQh, uint32_t *poffQt)
1158{
1159 /* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1160 uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1161 uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1162
1163 /* Don't bother masking QT, QH since other bits are RsvdZ. */
1164 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1165 Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1166 if (poffQh)
1167 *poffQh = uIqhReg;
1168 if (poffQt)
1169 *poffQt = uIqtReg;
1170 return uIqtReg == uIqhReg;
1171}
1172
1173
1174/**
1175 * Checks if the invalidation-queue is empty.
1176 *
1177 * @returns @c true if empty, @c false otherwise.
1178 * @param pThis The shared DMAR device state.
1179 */
1180static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1181{
1182 return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh */, NULL /* poffQt */);
1183}
1184
1185
1186/**
1187 * Checks if the invalidation-queue is capable of processing requests.
1188 *
1189 * @returns @c true if the invalidation-queue can process requests, @c false
1190 * otherwise.
1191 * @param pThis The shared DMAR device state.
1192 */
1193static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1194{
1195 /* Check if queued-invalidation is enabled. */
1196 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1197 if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1198 {
1199 /* Check if there are no invalidation-queue or timeout errors. */
1200 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1201 if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_ITE_MASK)))
1202 return true;
1203 }
1204 return false;
1205}
1206
1207
1208/**
1209 * Wakes up the invalidation-queue thread if there are requests to be processed.
1210 *
1211 * @param pDevIns The IOMMU device instance.
1212 */
1213static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1214{
1215 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1216 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1217 Log4Func(("\n"));
1218
1219 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1220
1221 if ( dmarInvQueueCanProcessRequests(pThis)
1222 && !dmarInvQueueIsEmpty(pThis))
1223 {
1224 Log4Func(("Signaling the invalidation-queue thread\n"));
1225 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1226 }
1227}
1228
1229
1230/**
1231 * Raises an event on behalf of the DMAR.
1232 *
1233 * These are events that are generated by the DMAR itself (like faults and
1234 * invalidation completion notifications).
1235 *
1236 * @param pDevIns The IOMMU device instance.
1237 * @param enmEventType The DMAR event type.
1238 *
1239 * @remarks The DMAR lock must be held while calling this function.
1240 */
1241static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1242{
1243 uint16_t offCtlReg;
1244 uint32_t fIntrMaskedMask;
1245 uint32_t fIntrPendingMask;
1246 uint16_t offMsiAddrLoReg;
1247 uint16_t offMsiAddrHiReg;
1248 uint16_t offMsiDataReg;
1249 switch (enmEventType)
1250 {
1251 case DMAREVENTTYPE_INV_COMPLETE:
1252 {
1253 offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1254 fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1255 fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1256 offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1257 offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1258 offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1259 break;
1260 }
1261
1262 case DMAREVENTTYPE_FAULT:
1263 {
1264 offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1265 fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1266 fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1267 offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1268 offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1269 offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1270 break;
1271 }
1272
1273 default:
1274 {
1275 /* Shouldn't ever happen. */
1276 AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1277 }
1278 }
1279
1280 /* Check if software has masked the interrupt. */
1281 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1282 uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1283 if (!(uCtlReg & fIntrMaskedMask))
1284 {
1285 /*
1286 * Interrupt is unmasked, raise it.
1287 * Interrupts generated by the DMAR have trigger mode and level as 0.
1288 * See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1289 */
1290 MSIMSG Msi;
1291 Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1292 Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1293 Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1294 Assert(Msi.Data.n.u1Level == 0);
1295 Assert(Msi.Data.n.u1TriggerMode == 0);
1296
1297 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1298 pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1299
1300 /* Clear interrupt pending bit. */
1301 uCtlReg &= ~fIntrPendingMask;
1302 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1303 }
1304 else
1305 {
1306 /* Interrupt is masked, set the interrupt pending bit. */
1307 uCtlReg |= fIntrPendingMask;
1308 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1309 }
1310}
1311
1312
1313/**
1314 * Raises an interrupt in response to a fault event.
1315 *
1316 * @param pDevIns The IOMMU device instance.
1317 *
1318 * @remarks This assumes the caller has already set the required status bits in the
1319 * FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1320 */
1321static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1322{
1323 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1324 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1325 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1326
1327#ifdef RT_STRICT
1328 {
1329 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1330 uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK | VTD_BF_FSTS_REG_PFO_MASK
1331 /* | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_AFO_MASK */ /* AFL not supported */
1332 /* | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK */ /* Device-TLBs not supported */
1333 | VTD_BF_FSTS_REG_IQE_MASK;
1334 Assert(uFstsReg & fFaultMask);
1335 }
1336#endif
1337 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1338}
1339
1340
1341#ifdef IN_RING3
1342/**
1343 * Raises an interrupt in response to an invalidation (complete) event.
1344 *
1345 * @param pDevIns The IOMMU device instance.
1346 */
1347static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1348{
1349 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1350 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1351 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1352
1353 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1354 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1355 {
1356 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1357 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1358 }
1359}
1360#endif /* IN_RING3 */
1361
1362
1363/**
1364 * Checks if a primary fault can be recorded.
1365 *
1366 * @returns @c true if the fault can be recorded, @c false otherwise.
1367 * @param pDevIns The IOMMU device instance.
1368 * @param pThis The shared DMAR device state.
1369 *
1370 * @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1371 * NOT call it unless there is a fault condition!
1372 */
1373static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1374{
1375 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1376 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1377
1378 uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1379 if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1380 return false;
1381
1382 /*
1383 * If we add more FRCD registers, we'll have to loop through them here.
1384 * Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1385 * nor do we need to increment FRI.
1386 *
1387 * See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1388 */
1389 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1390 uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1391 if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1392 {
1393 uFstsReg |= VTD_BF_FSTS_REG_PFO_MASK;
1394 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1395 return false;
1396 }
1397
1398 return true;
1399}
1400
1401
1402/**
1403 * Records a primary fault.
1404 *
1405 * @param pDevIns The IOMMU device instance.
1406 * @param enmDiag The diagnostic reason.
1407 * @param uFrcdHi The FRCD_HI_REG value for this fault.
1408 * @param uFrcdLo The FRCD_LO_REG value for this fault.
1409 */
1410static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint64_t uFrcdHi, uint64_t uFrcdLo)
1411{
1412 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1413 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1414
1415 DMAR_LOCK(pDevIns, pThisCC);
1416
1417 /* Update the diagnostic reason. */
1418 pThis->enmDiag = enmDiag;
1419
1420 /* We don't support advance fault logging. */
1421 Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1422
1423 if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1424 {
1425 /* Update the fault recording registers with the fault information. */
1426 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1427 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1428
1429 /* Set the Pending Primary Fault (PPF) field in the status register. */
1430 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1431
1432 /* Raise interrupt if necessary. */
1433 dmarFaultEventRaiseInterrupt(pDevIns);
1434 }
1435
1436 DMAR_UNLOCK(pDevIns, pThisCC);
1437}
1438
1439
1440/**
1441 * Records an interrupt request fault.
1442 *
1443 * @param pDevIns The IOMMU device instance.
1444 * @param enmDiag The diagnostic reason.
1445 * @param enmIrFault The interrupt fault reason.
1446 * @param idDevice The device ID (bus, device, function).
1447 * @param idxIntr The interrupt index.
1448 */
1449static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIRFAULT enmIrFault, uint16_t idDevice, uint16_t idxIntr)
1450{
1451 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1452 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1453 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1454 uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1455 dmarPrimaryFaultRecord(pDevIns, enmDiag, uFrcdHi, uFrcdLo);
1456}
1457
1458
1459/**
1460 * Records a qualified interrupt request fault.
1461 *
1462 * Qualified faults are those that can be suppressed by software using the FPD bit
1463 * in the IRTE.
1464 *
1465 * @param pDevIns The IOMMU device instance.
1466 * @param enmDiag The diagnostic reason.
1467 * @param enmIrFault The interrupt fault reason.
1468 * @param idDevice The device ID (bus, device, function).
1469 * @param idxIntr The interrupt index.
1470 * @param pIrte The IRTE that caused this fault.
1471 */
1472static void dmarIrFaultRecordQualified(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIRFAULT enmIrFault, uint16_t idDevice,
1473 uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1474{
1475 Assert(vtdIrFaultIsQualified(enmIrFault));
1476 Assert(pIrte);
1477 if (!(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK))
1478 return dmarIrFaultRecord(pDevIns, enmDiag, enmIrFault, idDevice, idxIntr);
1479}
1480
1481
1482/**
1483 * Records an address translation fault.
1484 *
1485 * @param pDevIns The IOMMU device instance.
1486 * @param enmDiag The diagnostic reason.
1487 * @param enmAtFault The address translation fault reason.
1488 * @param pAddrRemap The DMA address remap info.
1489 */
1490static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDATFAULT enmAtFault, PCDMARADDRMAP pAddrRemap)
1491{
1492 /*
1493 * Qualified faults are those that can be suppressed by software using the FPD bit
1494 * in the contex entry, scalable-mode context entry etc.
1495 */
1496 if (!pAddrRemap->fFpd)
1497 {
1498 uint8_t const fType1 = pAddrRemap->enmReqType & RT_BIT(1);
1499 uint8_t const fType2 = pAddrRemap->enmReqType & RT_BIT(0);
1500 uint8_t const fExec = pAddrRemap->fReqPerm & DMAR_PERM_EXE;
1501 uint8_t const fPriv = pAddrRemap->fReqPerm & DMAR_PERM_PRIV;
1502 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, pAddrRemap->idDevice)
1503 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1504 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, PCIPASID_IS_VALID(pAddrRemap->Pasid))
1505 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1506 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1507 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1508 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, PCIPASID_VAL(pAddrRemap->Pasid))
1509 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, pAddrRemap->enmAddrType)
1510 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1511 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1512 uint64_t const uFrcdLo = pAddrRemap->uDmaAddr & X86_PAGE_BASE_MASK;
1513 dmarPrimaryFaultRecord(pDevIns, enmDiag, uFrcdHi, uFrcdLo);
1514 }
1515}
1516
1517
1518/**
1519 * Records an IQE fault.
1520 *
1521 * @param pDevIns The IOMMU device instance.
1522 * @param enmIqei The IQE information.
1523 * @param enmDiag The diagnostic reason.
1524 */
1525static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1526{
1527 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1528 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1529
1530 DMAR_LOCK(pDevIns, pThisCC);
1531
1532 /* Update the diagnostic reason. */
1533 pThis->enmDiag = enmDiag;
1534
1535 /* Set the error bit. */
1536 uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1537 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1538
1539 /* Set the error information. */
1540 uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1541 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1542
1543 dmarFaultEventRaiseInterrupt(pDevIns);
1544
1545 DMAR_UNLOCK(pDevIns, pThisCC);
1546}
1547
1548
1549/**
1550 * Handles writes to GCMD_REG.
1551 *
1552 * @returns Strict VBox status code.
1553 * @param pDevIns The IOMMU device instance.
1554 * @param uGcmdReg The value written to GCMD_REG.
1555 */
1556static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1557{
1558 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1559 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1560 uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1561 uint64_t const fExtCapReg = pThis->fExtCapReg;
1562
1563 /* Queued-invalidation. */
1564 if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1565 && (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1566 {
1567 if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1568 {
1569 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1570 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1571 }
1572 else
1573 {
1574 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1575 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1576 }
1577 }
1578
1579 if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1580 {
1581 /* Set Interrupt Remapping Table Pointer (SIRTP). */
1582 if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1583 {
1584 /** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1585 * supported. */
1586 pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1587 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1588 }
1589
1590 /* Interrupt remapping. */
1591 if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1592 {
1593 if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1594 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1595 else
1596 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1597 }
1598
1599 /* Compatibility format interrupts. */
1600 if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1601 {
1602 if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1603 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1604 else
1605 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1606 }
1607 }
1608
1609 /* Set Root Table Pointer (SRTP). */
1610 if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1611 {
1612 /** @todo Perform global invalidation of all remapping translation caches when
1613 * ESRTPS is supported. */
1614 pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1615 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1616 }
1617
1618 /* Translation (DMA remapping). */
1619 if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1620 {
1621 if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1622 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1623 else
1624 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1625 }
1626
1627 return VINF_SUCCESS;
1628}
1629
1630
1631/**
1632 * Handles writes to CCMD_REG.
1633 *
1634 * @returns Strict VBox status code.
1635 * @param pDevIns The IOMMU device instance.
1636 * @param offReg The MMIO register offset.
1637 * @param cbReg The size of the MMIO access (in bytes).
1638 * @param uCcmdReg The value written to CCMD_REG.
1639 */
1640static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1641{
1642 /* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1643 if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1644 {
1645 /* Check if we need to invalidate the context-context. */
1646 bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1647 if (fIcc)
1648 {
1649 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1650 uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1651 if (uMajorVersion < 6)
1652 {
1653 /* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1654 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1655 if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1656 {
1657 /* Verify table translation mode is legacy. */
1658 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1659 if (fTtm == VTD_TTM_LEGACY_MODE)
1660 {
1661 /** @todo Invalidate. */
1662 return VINF_SUCCESS;
1663 }
1664 pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1665 }
1666 else
1667 pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1668 }
1669 else
1670 pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1671 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1672 }
1673 }
1674 return VINF_SUCCESS;
1675}
1676
1677
1678/**
1679 * Handles writes to FECTL_REG.
1680 *
1681 * @returns Strict VBox status code.
1682 * @param pDevIns The IOMMU device instance.
1683 * @param uFectlReg The value written to FECTL_REG.
1684 */
1685static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1686{
1687 /*
1688 * If software unmasks the interrupt when the interrupt is pending, we must raise
1689 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1690 */
1691 if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1692 && ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1693 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1694 return VINF_SUCCESS;
1695}
1696
1697
1698/**
1699 * Handles writes to FSTS_REG.
1700 *
1701 * @returns Strict VBox status code.
1702 * @param pDevIns The IOMMU device instance.
1703 * @param uFstsReg The value written to FSTS_REG.
1704 * @param uPrev The value in FSTS_REG prior to writing it.
1705 */
1706static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1707{
1708 /*
1709 * If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1710 * the interrupt pending (IP) bit must be cleared.
1711 *
1712 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1713 */
1714 uint32_t const fChanged = uPrev ^ uFstsReg;
1715 if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK
1716 | VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_PFO_MASK))
1717 {
1718 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1719 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1720 }
1721 return VINF_SUCCESS;
1722}
1723
1724
1725/**
1726 * Handles writes to IQT_REG.
1727 *
1728 * @returns Strict VBox status code.
1729 * @param pDevIns The IOMMU device instance.
1730 * @param offReg The MMIO register offset.
1731 * @param uIqtReg The value written to IQT_REG.
1732 */
1733static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1734{
1735 /* We only care about the low 32-bits, high 32-bits are reserved. */
1736 Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1737 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1738
1739 /* Paranoia. */
1740 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1741
1742 uint32_t const offQt = uIqtReg;
1743 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1744 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1745
1746 /* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1747 if ( fDw != VTD_IQA_REG_DW_256_BIT
1748 || !(offQt & RT_BIT(4)))
1749 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1750 else
1751 {
1752 /* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1753 dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1754 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1755 }
1756 return VINF_SUCCESS;
1757}
1758
1759
1760/**
1761 * Handles writes to IQA_REG.
1762 *
1763 * @returns Strict VBox status code.
1764 * @param pDevIns The IOMMU device instance.
1765 * @param offReg The MMIO register offset.
1766 * @param uIqaReg The value written to IQA_REG.
1767 */
1768static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1769{
1770 /* At present, we only care about the low 32-bits, high 32-bits are data. */
1771 Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1772
1773 /** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1774 * returns true? The Intel VT-d spec. doesn't state anywhere that it
1775 * cannot happen or that it's ignored when it does happen. */
1776
1777 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1778 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1779 if (fDw == VTD_IQA_REG_DW_256_BIT)
1780 {
1781 bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK | VTD_BF_ECAP_REG_ADMS_MASK));
1782 if (fSupports256BitDw)
1783 { /* likely */ }
1784 else
1785 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1786 }
1787 /* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1788
1789 return VINF_SUCCESS;
1790}
1791
1792
1793/**
1794 * Handles writes to ICS_REG.
1795 *
1796 * @returns Strict VBox status code.
1797 * @param pDevIns The IOMMU device instance.
1798 * @param uIcsReg The value written to ICS_REG.
1799 */
1800static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1801{
1802 /*
1803 * If the IP field is set when software services the interrupt condition,
1804 * (by clearing the IWC field), the IP field must be cleared.
1805 */
1806 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1807 {
1808 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1809 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1810 }
1811 return VINF_SUCCESS;
1812}
1813
1814
1815/**
1816 * Handles writes to IECTL_REG.
1817 *
1818 * @returns Strict VBox status code.
1819 * @param pDevIns The IOMMU device instance.
1820 * @param uIectlReg The value written to IECTL_REG.
1821 */
1822static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1823{
1824 /*
1825 * If software unmasks the interrupt when the interrupt is pending, we must raise
1826 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1827 */
1828 if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1829 && ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1830 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1831 return VINF_SUCCESS;
1832}
1833
1834
1835/**
1836 * Handles writes to FRCD_REG (High 64-bits).
1837 *
1838 * @returns Strict VBox status code.
1839 * @param pDevIns The IOMMU device instance.
1840 * @param offReg The MMIO register offset.
1841 * @param cbReg The size of the MMIO access (in bytes).
1842 * @param uFrcdHiReg The value written to FRCD_REG.
1843 * @param uPrev The value in FRCD_REG prior to writing it.
1844 */
1845static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
1846{
1847 /* We only care about responding to high 32-bits, low 32-bits are read-only. */
1848 if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
1849 {
1850 /*
1851 * If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
1852 * Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
1853 * has only 1 FRCD register.
1854 *
1855 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1856 */
1857 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1858 uint64_t const fChanged = uPrev ^ uFrcdHiReg;
1859 if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
1860 {
1861 Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
1862 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1863 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
1864 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1865 }
1866 }
1867 return VINF_SUCCESS;
1868}
1869
1870
1871/**
1872 * Performs a PCI target abort for a DMA remapping (DR) operation.
1873 *
1874 * @param pDevIns The IOMMU device instance.
1875 */
1876static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
1877{
1878 /** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
1879 * as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
1880 * who knows. */
1881 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1882 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1883 PDMPciDevSetStatus(pPciDev, u16Status);
1884}
1885
1886
1887/**
1888 * Checks whether the address width (AW) is supported by our hardware
1889 * implementation for legacy mode address translation.
1890 *
1891 * @returns @c true if it's supported, @c false otherwise.
1892 * @param pThis The shared DMAR device state.
1893 * @param pCtxEntry The context entry.
1894 * @param pcPagingLevel Where to store the paging level.
1895 */
1896static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
1897{
1898 uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
1899 uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
1900 uint8_t const fAwMask = RT_BIT(fAw);
1901 uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
1902 Assert(!(fSagaw & ~(RT_BIT(1) | RT_BIT(2) | RT_BIT(3))));
1903
1904 *pcPagingLevel = fAw + 2;
1905
1906 /* With pass-through, the address width must be the largest AGAW supported by hardware. */
1907 if (fTt == VTD_TT_UNTRANSLATED_PT)
1908 {
1909 Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
1910 return *pcPagingLevel == pThis->cMaxPagingLevel;
1911 }
1912
1913 /* The address width must be any of the ones supported by hardware. */
1914 if (fAw < 4)
1915 return (fSagaw & fAwMask) != 0;
1916
1917 return false;
1918}
1919
1920
1921/**
1922 * Reads a root entry from guest memory.
1923 *
1924 * @returns VBox status code.
1925 * @param pDevIns The IOMMU device instance.
1926 * @param uRtaddrReg The current RTADDR_REG value.
1927 * @param idxRootEntry The index of the root entry to read.
1928 * @param pRootEntry Where to store the read root entry.
1929 */
1930static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
1931{
1932 size_t const cbRootEntry = sizeof(*pRootEntry);
1933 RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
1934 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
1935}
1936
1937
1938/**
1939 * Reads a context entry from guest memory.
1940 *
1941 * @returns VBox status code.
1942 * @param pDevIns The IOMMU device instance.
1943 * @param GCPhysCtxTable The physical address of the context table.
1944 * @param idxCtxEntry The index of the context entry to read.
1945 * @param pCtxEntry Where to store the read context entry.
1946 */
1947static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
1948{
1949 /* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
1950 size_t const cbCtxEntry = sizeof(*pCtxEntry);
1951 RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
1952 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
1953}
1954
1955
1956/**
1957 * Reads a second-level paging entry from guest memory.
1958 *
1959 * @returns VBox status code.
1960 * @param pDevIns The IOMMU device instance.
1961 * @param GCPhysSlptPtr The physical address of the SLPTPTR.
1962 * @param pSlpEntry Where to store the read SLPTPTR.
1963 */
1964static int dmarDrReadSlpPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhysSlptPtr, PVTD_SLP_ENTRY_T pSlpEntry)
1965{
1966 /* We don't verify bits 63:HAW of GCPhysSlptPtr is 0 since reading from such an address should fail anyway. */
1967 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysSlptPtr, pSlpEntry, sizeof(*pSlpEntry));
1968}
1969
1970
1971/**
1972 * Performs second level translation.
1973 *
1974 * @returns VBox status code.
1975 * @param pDevIns The IOMMU device instance.
1976 * @param SlpEntry The second-level paging entry.
1977 * @param cPagingLevel The paging level.
1978 * @param idDomain The domain ID for the translation.
1979 * @param pAddrRemap The DMA address remap info.
1980 */
1981static int dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, VTD_SLP_ENTRY_T SlpEntry, uint8_t cPagingLevel, uint16_t idDomain,
1982 PDMARADDRMAP pAddrRemap)
1983{
1984 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
1985
1986 /* Mask of valid paging entry bits. */
1987 static uint64_t const s_auPtEntityRsvd[] = { VTD_SL_PTE_VALID_MASK,
1988 VTD_SL_PDE_VALID_MASK,
1989 VTD_SL_PDPE_VALID_MASK,
1990 VTD_SL_PML4E_VALID_MASK,
1991 VTD_SL_PML5E_VALID_MASK };
1992
1993 /* Mask of valid large-page (1GB, 2MB) paging entries. */
1994 static uint64_t const s_auLargePageRsvd[] = { 0,
1995 VTD_SL_PDE2M_VALID_MASK,
1996 VTD_SL_PDPE1G_VALID_MASK,
1997 0,
1998 0 };
1999
2000 /* Paranoia. */
2001 Assert(cPagingLevel >= 3 && cPagingLevel <= 5);
2002 AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == RT_ELEMENTS(s_auLargePageRsvd));
2003 AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == 5);
2004
2005 /* Second-level translations restricts input address to an implementation-specific MGAW. */
2006 uint64_t const uDmaAddr = pAddrRemap->uDmaAddr;
2007 if (!(uDmaAddr & pThis->fInvMgawMask))
2008 { /* likely */ }
2009 else
2010 {
2011 if (pAddrRemap->fTtm == VTD_TTM_LEGACY_MODE)
2012 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lgn_1_1, VTDATFAULT_LGN_1_1, pAddrRemap);
2013 else
2014 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Sgn_5, VTDATFAULT_SGN_5, pAddrRemap);
2015 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2016 }
2017
2018 /*
2019 * Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2020 * Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2021 */
2022 uint64_t uPtEntity = SlpEntry;
2023 for (int8_t iLevel = cPagingLevel - 1; iLevel >= 0; iLevel--)
2024 {
2025 /*
2026 * Read the paging entry for the current level.
2027 */
2028 uint8_t const cLevelShift = 12 + ((iLevel - 1) * 9);
2029 {
2030 uint16_t const idxPte = (uDmaAddr >> cLevelShift) & UINT64_C(0x1ff);
2031 uint64_t const offPte = idxPte << 3;
2032 RTGCPHYS const GCPhysPtEntity = uPtEntity | offPte;
2033 int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2034 if (RT_SUCCESS(rc))
2035 { /* likely */ }
2036 else
2037 {
2038 if (pAddrRemap->fTtm == VTD_TTM_LEGACY_MODE)
2039 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lsl_1, VTDATFAULT_LSL_1, pAddrRemap);
2040 else
2041 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Ssl_1, VTDATFAULT_SSL_1, pAddrRemap);
2042 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2043 }
2044 }
2045
2046 /*
2047 * Check I/O permissions.
2048 * This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2049 *
2050 * See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2051 */
2052 uint8_t const fReqPerm = pAddrRemap->fReqPerm & pThis->fPermValidMask;
2053 uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2054 if ((fPtPerm & fReqPerm) == fReqPerm)
2055 { /* likely */ }
2056 else
2057 {
2058 if (pAddrRemap->fTtm == VTD_TTM_LEGACY_MODE)
2059 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lsl_2, VTDATFAULT_LSL_2, pAddrRemap);
2060 else
2061 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Ssl_2, VTDATFAULT_SSL_2, pAddrRemap);
2062 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2063 }
2064
2065 /*
2066 * Validate reserved bits of the current paging entry.
2067 */
2068 if (!(uPtEntity & ~s_auPtEntityRsvd[iLevel]))
2069 { /* likely */ }
2070 else
2071 {
2072 if (pAddrRemap->fTtm == VTD_TTM_LEGACY_MODE)
2073 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lsl_2, VTDATFAULT_LSL_2, pAddrRemap);
2074 else
2075 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Ssl_3, VTDATFAULT_SSL_3, pAddrRemap);
2076 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2077 }
2078
2079 /*
2080 * Check if this is a 1GB page or a 2MB page.
2081 */
2082 AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2083 uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2084 if (fLargePage && iLevel > 0)
2085 {
2086 Assert(iLevel == 1 || iLevel == 2);
2087 uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2088 if (fSllpsMask & RT_BIT(iLevel - 1))
2089 {
2090 pAddrRemap->Iotlbe.GCPhysBase = uPtEntity & ~(RT_BIT_64(cLevelShift) - 1);
2091 pAddrRemap->Iotlbe.cShift = cLevelShift;
2092 pAddrRemap->Iotlbe.fPerm = fPtPerm;
2093 pAddrRemap->Iotlbe.idDomain = idDomain;
2094 return VINF_SUCCESS;
2095 }
2096
2097 if (pAddrRemap->fTtm == VTD_TTM_LEGACY_MODE)
2098 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lsl_2_LargePage, VTDATFAULT_LSL_2, pAddrRemap);
2099 else
2100 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Ssl_3_LargePage, VTDATFAULT_SSL_3, pAddrRemap);
2101 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2102 }
2103
2104 /*
2105 * If this is the final PTE, compute the translation address and we're done.
2106 */
2107 if (iLevel == 0)
2108 {
2109 pAddrRemap->Iotlbe.GCPhysBase = uPtEntity & ~(RT_BIT_64(cLevelShift) - 1);
2110 pAddrRemap->Iotlbe.cShift = cLevelShift;
2111 pAddrRemap->Iotlbe.fPerm = fPtPerm;
2112 pAddrRemap->Iotlbe.idDomain = idDomain;
2113 return VINF_SUCCESS;
2114 }
2115 }
2116
2117 /* Shouldn't ever reach here. */
2118 return VERR_IOMMU_IPE_0;
2119}
2120
2121
2122/**
2123 * Handles remapping of DMA address requests in legacy mode.
2124 *
2125 * @returns VBox status code.
2126 * @param pDevIns The IOMMU device instance.
2127 * @param uRtaddrReg The current RTADDR_REG value.
2128 * @param pAddrRemap The DMA address remap info.
2129 */
2130static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARADDRMAP pAddrRemap)
2131{
2132 Assert(pAddrRemap->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2133
2134 /* Read the root-entry from guest memory. */
2135 uint8_t const idxRootEntry = RT_HI_U8(pAddrRemap->idDevice);
2136 VTD_ROOT_ENTRY_T RootEntry;
2137 int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2138 if (RT_SUCCESS(rc))
2139 {
2140 /* Check if the root entry is present (must be done before validating reserved bits). */
2141 uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2142 uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2143 bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2144 if (fRootEntryPresent)
2145 {
2146 /* Validate reserved bits in the root entry. */
2147 if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2148 && !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2149 {
2150 /* Read the context-entry from guest memory. */
2151 RTGCPHYS const GCPhysCtxTable = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_CTP);
2152 uint8_t const idxCtxEntry = RT_LO_U8(pAddrRemap->idDevice);
2153 VTD_CONTEXT_ENTRY_T CtxEntry;
2154 rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2155 if (RT_SUCCESS(rc))
2156 {
2157 uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2158 uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2159
2160 /* Note the FPD bit which software can use to supress translation faults from here on in. */
2161 pAddrRemap->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2162
2163 /* Check if the context-entry is present (must be done before validating reserved bits). */
2164 bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2165 if (fCtxEntryPresent)
2166 {
2167 /* Validate reserved bits in the context-entry. */
2168 if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2169 && !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
2170 {
2171 /* Get the domain ID for this mapping. */
2172 uint16_t const idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2173
2174 /* Validate the translation type (TT). */
2175 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2176 uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2177 switch (fTt)
2178 {
2179 case VTD_TT_UNTRANSLATED_SLP:
2180 {
2181 /*
2182 * Untranslated requests are translated using second-level paging structures referenced
2183 * through SLPTPTR. Translated requests and Translation Requests are blocked.
2184 */
2185 if (pAddrRemap->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2186 {
2187 /* Validate the address width and get the paging level. */
2188 uint8_t cPagingLevel;
2189 if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2190 {
2191 /* Read the SLPTPTR from guest memory. */
2192 RTGCPHYS const GCPhysSlptPtr = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2193 VTD_SLP_ENTRY_T SlpEntry;
2194 rc = dmarDrReadSlpPtr(pDevIns, GCPhysSlptPtr, &SlpEntry);
2195 if (RT_SUCCESS(rc))
2196 {
2197 /* Finally... perform second-level translation. */
2198 return dmarDrSecondLevelTranslate(pDevIns, SlpEntry, cPagingLevel, idDomain,
2199 pAddrRemap);
2200 }
2201 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_4_3, VTDATFAULT_LCT_4_3, pAddrRemap);
2202 }
2203 else
2204 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_4_1, VTDATFAULT_LCT_4_1, pAddrRemap);
2205 }
2206 else
2207 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_5, VTDATFAULT_LCT_5, pAddrRemap);
2208 break;
2209 }
2210
2211 case VTD_TT_UNTRANSLATED_PT:
2212 {
2213 /*
2214 * Untranslated requests are processed as pass-through (PT) if PT is supported.
2215 * Translated and translation requests are blocked. If PT isn't supported this TT value
2216 * is reserved which I assume raises a fault (hence fallthru below).
2217 */
2218 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2219 {
2220 if (pAddrRemap->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2221 {
2222 /** @todo Check AW == maximum SAGAW bit? */
2223 pAddrRemap->Iotlbe.GCPhysBase = pAddrRemap->uDmaAddr & X86_PAGE_4K_BASE_MASK;
2224 pAddrRemap->Iotlbe.cShift = X86_PAGE_4K_SHIFT;
2225 pAddrRemap->Iotlbe.fPerm = DMAR_PERM_ALL;
2226 pAddrRemap->Iotlbe.idDomain = idDomain;
2227 pAddrRemap->cbContiguous = pAddrRemap->cbDma;
2228 return VINF_SUCCESS;
2229 }
2230 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_5, VTDATFAULT_LCT_5, pAddrRemap);
2231 break;
2232 }
2233 RT_FALL_THRU();
2234 }
2235
2236 case VTD_TT_UNTRANSLATED_DEV_TLB:
2237 {
2238 /*
2239 * Untranslated, translated and translation requests are supported but requires
2240 * device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2241 */
2242 Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2243 RT_FALL_THRU();
2244 }
2245
2246 default:
2247 {
2248 /* Any other TT value is reserved. */
2249 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_4_2, VTDATFAULT_LCT_4_2, pAddrRemap);
2250 break;
2251 }
2252 }
2253 }
2254 else
2255 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_3, VTDATFAULT_LCT_3, pAddrRemap);
2256 }
2257 else
2258 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_2, VTDATFAULT_LCT_2, pAddrRemap);
2259 }
2260 else
2261 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_1, VTDATFAULT_LCT_1, pAddrRemap);
2262 }
2263 else
2264 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_3, VTDATFAULT_LRT_3, pAddrRemap);
2265 }
2266 else
2267 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_2, VTDATFAULT_LRT_2, pAddrRemap);
2268 }
2269 else
2270 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_1, VTDATFAULT_LRT_1, pAddrRemap);
2271 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2272}
2273
2274
2275/**
2276 * Handles remapping of DMA address requests in scalable mode.
2277 *
2278 * @returns VBox status code.
2279 * @param pDevIns The IOMMU device instance.
2280 * @param uRtaddrReg The current RTADDR_REG value.
2281 * @param pAddrRemap The DMA address remap info.
2282 */
2283static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARADDRMAP pAddrRemap)
2284{
2285 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2286 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2287 {
2288 RT_NOREF1(uRtaddrReg);
2289 return VERR_NOT_IMPLEMENTED;
2290 }
2291
2292 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_3, VTDATFAULT_RTA_1_3, pAddrRemap);
2293 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2294}
2295
2296
2297/**
2298 * Memory access bulk (one or more 4K pages) request from a device.
2299 *
2300 * @returns VBox status code.
2301 * @param pDevIns The IOMMU device instance.
2302 * @param idDevice The device ID (bus, device, function).
2303 * @param cIovas The number of addresses being accessed.
2304 * @param pauIovas The I/O virtual addresses for each page being accessed.
2305 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2306 * @param paGCPhysSpa Where to store the translated physical addresses.
2307 *
2308 * @thread Any.
2309 */
2310static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2311 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2312{
2313 RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
2314 return VERR_NOT_IMPLEMENTED;
2315}
2316
2317
2318/**
2319 * Memory access transaction from a device.
2320 *
2321 * @returns VBox status code.
2322 * @param pDevIns The IOMMU device instance.
2323 * @param idDevice The device ID (bus, device, function).
2324 * @param uIova The I/O virtual address being accessed.
2325 * @param cbIova The size of the access.
2326 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2327 * @param pGCPhysSpa Where to store the translated system physical address.
2328 * @param pcbContiguous Where to store the number of contiguous bytes translated
2329 * and permission-checked.
2330 *
2331 * @thread Any.
2332 */
2333static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2334 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2335{
2336 /* Validate. */
2337 AssertPtr(pDevIns);
2338 AssertPtr(pGCPhysSpa);
2339 AssertPtr(pcbContiguous);
2340 Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2341 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2342
2343 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2344 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2345
2346 DMAR_LOCK(pDevIns, pThisCC);
2347 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2348 uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2349 DMAR_UNLOCK(pDevIns, pThisCC);
2350
2351 if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2352 {
2353 VTDREQTYPE enmReqType;
2354 uint8_t fReqPerm;
2355 if (fFlags & PDMIOMMU_MEM_F_READ)
2356 {
2357 enmReqType = VTDREQTYPE_READ;
2358 fReqPerm = DMAR_PERM_READ;
2359 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2360 }
2361 else
2362 {
2363 enmReqType = VTDREQTYPE_WRITE;
2364 fReqPerm = DMAR_PERM_WRITE;
2365 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2366 }
2367
2368 uint8_t const fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2369 DMARADDRMAP AddrRemap;
2370 RT_ZERO(AddrRemap);
2371 AddrRemap.idDevice = idDevice;
2372 AddrRemap.fReqPerm = fReqPerm;
2373 AddrRemap.Pasid = NIL_PCIPASID;
2374 AddrRemap.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2375 AddrRemap.enmReqType = enmReqType;
2376 AddrRemap.fTtm = fTtm;
2377 AddrRemap.uDmaAddr = uIova;
2378 AddrRemap.cbDma = cbIova;
2379 AddrRemap.Iotlbe.GCPhysBase = NIL_RTGCPHYS;
2380
2381 int rc;
2382 switch (fTtm)
2383 {
2384 case VTD_TTM_LEGACY_MODE:
2385 {
2386 rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, &AddrRemap);
2387 break;
2388 }
2389
2390 case VTD_TTM_SCALABLE_MODE:
2391 {
2392 rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, &AddrRemap);
2393 break;
2394 }
2395
2396 case VTD_TTM_ABORT_DMA_MODE:
2397 {
2398 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2399 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2400 dmarDrTargetAbort(pDevIns);
2401 else
2402 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_1, VTDATFAULT_RTA_1_1, &AddrRemap);
2403 break;
2404 }
2405
2406 default:
2407 {
2408 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2409 dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_2, VTDATFAULT_RTA_1_2, &AddrRemap);
2410 break;
2411 }
2412 }
2413
2414 *pcbContiguous = AddrRemap.cbContiguous;
2415 *pGCPhysSpa = AddrRemap.Iotlbe.GCPhysBase | DMAR_GET_PAGE_OFF_MASK(AddrRemap.Iotlbe.cShift);
2416 return rc;
2417 }
2418
2419 *pGCPhysSpa = uIova;
2420 *pcbContiguous = cbIova;
2421 return VINF_SUCCESS;
2422}
2423
2424
2425/**
2426 * Reads an IRTE from guest memory.
2427 *
2428 * @returns VBox status code.
2429 * @param pDevIns The IOMMU device instance.
2430 * @param uIrtaReg The IRTA_REG.
2431 * @param idxIntr The interrupt index.
2432 * @param pIrte Where to store the read IRTE.
2433 */
2434static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2435{
2436 Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2437
2438 size_t const cbIrte = sizeof(*pIrte);
2439 RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2440 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2441}
2442
2443
2444/**
2445 * Remaps the source MSI to the destination MSI given the IRTE.
2446 *
2447 * @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2448 * IRTA_REG.EIME).
2449 * @param pIrte The IRTE used for the remapping.
2450 * @param pMsiIn The source MSI (currently unused).
2451 * @param pMsiOut Where to store the remapped MSI.
2452 */
2453static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2454{
2455 NOREF(pMsiIn);
2456 uint64_t const uIrteQword0 = pIrte->au64[0];
2457
2458 /*
2459 * Let's start with a clean slate and preserve unspecified bits if the need arises.
2460 * For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2461 * but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2462 * it copies it from the source MSI.
2463 */
2464 RT_ZERO(*pMsiOut);
2465 pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2466 pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2467 pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2468 if (fExtIntrMode)
2469 {
2470 /*
2471 * Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2472 * high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2473 */
2474 uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2475 pMsiOut->Addr.n.u8DestId = idDest;
2476 pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2477 }
2478 else
2479 pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2480
2481 pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2482 pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2483 pMsiOut->Data.n.u1Level = 1;
2484 pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2485}
2486
2487
2488/**
2489 * Handles remapping of interrupts in remappable interrupt format.
2490 *
2491 * @returns VBox status code.
2492 * @param pDevIns The IOMMU device instance.
2493 * @param uIrtaReg The IRTA_REG.
2494 * @param idDevice The device ID (bus, device, function).
2495 * @param pMsiIn The source MSI.
2496 * @param pMsiOut Where to store the remapped MSI.
2497 */
2498static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2499{
2500 Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2501
2502 /* Validate reserved bits in the interrupt request. */
2503 AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2504 if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2505 {
2506 /* Compute the index into the interrupt remap table. */
2507 uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2508 uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2509 uint16_t const uHandle = uHandleLo | (uHandleHi << 15);
2510 bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2511 uint16_t const idxIntr = fSubHandleValid
2512 ? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2513 : uHandle;
2514
2515 /* Validate the index. */
2516 uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2517 if (idxIntr < cEntries)
2518 {
2519 /** @todo Implement and read IRTE from interrupt-entry cache here. */
2520
2521 /* Read the interrupt remap table entry (IRTE) at the index. */
2522 VTD_IRTE_T Irte;
2523 int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2524 if (RT_SUCCESS(rc))
2525 {
2526 /* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2527 uint64_t const uIrteQword0 = Irte.au64[0];
2528 uint64_t const uIrteQword1 = Irte.au64[1];
2529 bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2530 if (fPresent)
2531 {
2532 /* Validate reserved bits in the IRTE. */
2533 bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2534 uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2535 if ( !(uIrteQword0 & ~fQw0ValidMask)
2536 && !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2537 {
2538 /* Validate requester id (the device ID) as configured in the IRTE. */
2539 bool fSrcValid;
2540 DMARDIAG enmIrDiag;
2541 uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2542 switch (fSvt)
2543 {
2544 case VTD_IRTE_SVT_NONE:
2545 {
2546 fSrcValid = true;
2547 enmIrDiag = kDmarDiag_None;
2548 break;
2549 }
2550
2551 case VTD_IRTE_SVT_VALIDATE_MASK:
2552 {
2553 static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2554 uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2555 uint16_t const fValidMask = s_afValidMasks[idxMask];
2556 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2557 fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2558 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2559 break;
2560 }
2561
2562 case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2563 {
2564 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2565 uint8_t const uBusFirst = RT_HI_U8(idSource);
2566 uint8_t const uBusLast = RT_LO_U8(idSource);
2567 uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2568 fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2569 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2570 break;
2571 }
2572
2573 default:
2574 {
2575 fSrcValid = false;
2576 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2577 break;
2578 }
2579 }
2580
2581 if (fSrcValid)
2582 {
2583 uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2584 if (!fPostedMode)
2585 {
2586 dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2587 return VINF_SUCCESS;
2588 }
2589 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
2590 VTDIRFAULT_IRTE_PRESENT_RSVD, idDevice, idxIntr, &Irte);
2591 }
2592 else
2593 dmarIrFaultRecordQualified(pDevIns, enmIrDiag, VTDIRFAULT_IRTE_PRESENT_RSVD, idDevice, idxIntr,
2594 &Irte);
2595 }
2596 else
2597 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, VTDIRFAULT_IRTE_PRESENT_RSVD,
2598 idDevice, idxIntr, &Irte);
2599 }
2600 else
2601 dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, VTDIRFAULT_IRTE_NOT_PRESENT,
2602 idDevice, idxIntr, &Irte);
2603 }
2604 else
2605 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, VTDIRFAULT_IRTE_READ_FAILED, idDevice, idxIntr);
2606 }
2607 else
2608 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, VTDIRFAULT_INTR_INDEX_INVALID, idDevice, idxIntr);
2609 }
2610 else
2611 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, VTDIRFAULT_REMAPPABLE_INTR_RSVD, idDevice, 0 /* idxIntr */);
2612 return VERR_IOMMU_INTR_REMAP_DENIED;
2613}
2614
2615
2616/**
2617 * Interrupt remap request from a device.
2618 *
2619 * @returns VBox status code.
2620 * @param pDevIns The IOMMU device instance.
2621 * @param idDevice The device ID (bus, device, function).
2622 * @param pMsiIn The source MSI.
2623 * @param pMsiOut Where to store the remapped MSI.
2624 */
2625static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2626{
2627 /* Validate. */
2628 Assert(pDevIns);
2629 Assert(pMsiIn);
2630 Assert(pMsiOut);
2631 RT_NOREF1(idDevice);
2632
2633 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2634 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2635
2636 /* Lock and read all registers required for interrupt remapping up-front. */
2637 DMAR_LOCK(pDevIns, pThisCC);
2638 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2639 uint64_t const uIrtaReg = pThis->uIrtaReg;
2640 DMAR_UNLOCK(pDevIns, pThisCC);
2641
2642 /* Check if interrupt remapping is enabled. */
2643 if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
2644 {
2645 bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
2646 if (!fIsRemappable)
2647 {
2648 /* Handle compatibility format interrupts. */
2649 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
2650
2651 /* If EIME is enabled or CFIs are disabled, block the interrupt. */
2652 if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
2653 || !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
2654 {
2655 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
2656 return VERR_IOMMU_INTR_REMAP_DENIED;
2657 }
2658
2659 /* Interrupt isn't subject to remapping, pass-through the interrupt. */
2660 *pMsiOut = *pMsiIn;
2661 return VINF_SUCCESS;
2662 }
2663
2664 /* Handle remappable format interrupts. */
2665 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
2666 return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
2667 }
2668
2669 /* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
2670 *pMsiOut = *pMsiIn;
2671 return VINF_SUCCESS;
2672}
2673
2674
2675/**
2676 * @callback_method_impl{FNIOMMMIONEWWRITE}
2677 */
2678static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
2679{
2680 RT_NOREF1(pvUser);
2681 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2682
2683 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2684 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
2685
2686 uint16_t const offReg = off;
2687 uint16_t const offLast = offReg + cb - 1;
2688 if (DMAR_IS_MMIO_OFF_VALID(offLast))
2689 {
2690 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2691 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2692
2693 uint64_t uPrev = 0;
2694 uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, *(uint64_t *)pv, &uPrev)
2695 : dmarRegWrite32(pThis, offReg, *(uint32_t *)pv, (uint32_t *)&uPrev);
2696 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2697 switch (off)
2698 {
2699 case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
2700 {
2701 rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
2702 break;
2703 }
2704
2705 case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
2706 case VTD_MMIO_OFF_CCMD_REG + 4:
2707 {
2708 rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
2709 break;
2710 }
2711
2712 case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
2713 {
2714 rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
2715 break;
2716 }
2717
2718 case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
2719 {
2720 rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
2721 break;
2722 }
2723
2724 case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
2725 /* VTD_MMIO_OFF_IQT_REG + 4: */ /* High 32-bits reserved. */
2726 {
2727 rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
2728 break;
2729 }
2730
2731 case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
2732 /* VTD_MMIO_OFF_IQA_REG + 4: */ /* High 32-bits data. */
2733 {
2734 rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
2735 break;
2736 }
2737
2738 case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
2739 {
2740 rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
2741 break;
2742 }
2743
2744 case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
2745 {
2746 rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
2747 break;
2748 }
2749
2750 case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
2751 case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
2752 {
2753 rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
2754 break;
2755 }
2756 }
2757
2758 DMAR_UNLOCK(pDevIns, pThisCC);
2759 LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
2760 return rcStrict;
2761 }
2762
2763 return VINF_IOM_MMIO_UNUSED_FF;
2764}
2765
2766
2767/**
2768 * @callback_method_impl{FNIOMMMIONEWREAD}
2769 */
2770static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
2771{
2772 RT_NOREF1(pvUser);
2773 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2774
2775 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2776 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
2777
2778 uint16_t const offReg = off;
2779 uint16_t const offLast = offReg + cb - 1;
2780 if (DMAR_IS_MMIO_OFF_VALID(offLast))
2781 {
2782 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2783 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
2784
2785 if (cb == 8)
2786 {
2787 *(uint64_t *)pv = dmarRegRead64(pThis, offReg);
2788 LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, *(uint64_t *)pv));
2789 }
2790 else
2791 {
2792 *(uint32_t *)pv = dmarRegRead32(pThis, offReg);
2793 LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, *(uint32_t *)pv));
2794 }
2795
2796 DMAR_UNLOCK(pDevIns, pThisCC);
2797 return VINF_SUCCESS;
2798 }
2799
2800 return VINF_IOM_MMIO_UNUSED_FF;
2801}
2802
2803
2804#ifdef IN_RING3
2805/**
2806 * Process requests in the invalidation queue.
2807 *
2808 * @param pDevIns The IOMMU device instance.
2809 * @param pvRequests The requests to process.
2810 * @param cbRequests The size of all requests (in bytes).
2811 * @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
2812 * VTD_IQA_REG_DW_256_BIT).
2813 * @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
2814 */
2815static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
2816 uint8_t fTtm)
2817{
2818#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
2819 do \
2820 { \
2821 dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
2822 return; \
2823 } while (0)
2824
2825 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2826 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2827
2828 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
2829 Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
2830
2831 /*
2832 * The below check is redundant since we check both TTM and DW for each
2833 * descriptor type we process. However, the error reported by hardware
2834 * may differ hence this is kept commented out but not removed from the code
2835 * if we need to change this in the future.
2836 *
2837 * In our implementation, we would report the descriptor type as invalid,
2838 * while on real hardware it may report descriptor width as invalid.
2839 * The Intel VT-d spec. is not clear which error takes preceedence.
2840 */
2841#if 0
2842 /*
2843 * Verify that 128-bit descriptors are not used when operating in scalable mode.
2844 * We don't check this while software writes IQA_REG but defer it until now because
2845 * RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
2846 * -IS- performed when software writes IQA_REG since it only requires checking against
2847 * immutable hardware features.
2848 */
2849 if ( fTtm != VTD_TTM_SCALABLE_MODE
2850 || fDw != VTD_IQA_REG_DW_128_BIT)
2851 { /* likely */ }
2852 else
2853 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
2854#endif
2855
2856 /*
2857 * Process requests in FIFO order.
2858 */
2859 uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
2860 for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
2861 {
2862 uint64_t const *puDscQwords = (uint64_t const *)((uintptr_t)pvRequests + offDsc);
2863 uint64_t const uQword0 = puDscQwords[0];
2864 uint64_t const uQword1 = puDscQwords[1];
2865 uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
2866 switch (fDscType)
2867 {
2868 case VTD_INV_WAIT_DSC_TYPE:
2869 {
2870 /* Validate descriptor type. */
2871 if ( fTtm == VTD_TTM_LEGACY_MODE
2872 || fDw == VTD_IQA_REG_DW_256_BIT)
2873 { /* likely */ }
2874 else
2875 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
2876
2877 /* Validate reserved bits. */
2878 uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
2879 ? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
2880 : VTD_INV_WAIT_DSC_0_VALID_MASK;
2881 if ( !(uQword0 & ~fValidMask0)
2882 && !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
2883 { /* likely */ }
2884 else
2885 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
2886
2887 if (fDw == VTD_IQA_REG_DW_256_BIT)
2888 {
2889 if ( !puDscQwords[2]
2890 && !puDscQwords[3])
2891 { /* likely */ }
2892 else
2893 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
2894 }
2895
2896 /* Perform status write (this must be done prior to generating the completion interrupt). */
2897 bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
2898 if (fSw)
2899 {
2900 uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
2901 RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
2902 int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
2903 AssertRC(rc);
2904 }
2905
2906 /* Generate invalidation event interrupt. */
2907 bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
2908 if (fIf)
2909 {
2910 DMAR_LOCK(pDevIns, pThisR3);
2911 dmarR3InvEventRaiseInterrupt(pDevIns);
2912 DMAR_UNLOCK(pDevIns, pThisR3);
2913 }
2914
2915 STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
2916 break;
2917 }
2918
2919 case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
2920 case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
2921 case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
2922 case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
2923 case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
2924 case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
2925 case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
2926 default:
2927 {
2928 /* Stop processing further requests. */
2929 LogFunc(("Invalid descriptor type: %#x\n", fDscType));
2930 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
2931 }
2932 }
2933 }
2934#undef DMAR_IQE_FAULT_RECORD_RET
2935}
2936
2937
2938/**
2939 * The invalidation-queue thread.
2940 *
2941 * @returns VBox status code.
2942 * @param pDevIns The IOMMU device instance.
2943 * @param pThread The command thread.
2944 */
2945static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
2946{
2947 NOREF(pThread);
2948 LogFlowFunc(("\n"));
2949
2950 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
2951 return VINF_SUCCESS;
2952
2953 /*
2954 * Pre-allocate the maximum size of the invalidation queue allowed by the spec.
2955 * This prevents trashing the heap as well as deal with out-of-memory situations
2956 * up-front while starting the VM. It also simplifies the code from having to
2957 * dynamically grow/shrink the allocation based on how software sizes the queue.
2958 * Guests normally don't alter the queue size all the time, but that's not an
2959 * assumption we can make.
2960 */
2961 uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
2962 size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
2963 void *pvRequests = RTMemAllocZ(cbMaxQs);
2964 AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
2965
2966 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2967 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
2968
2969 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
2970 {
2971 /*
2972 * Sleep until we are woken up.
2973 */
2974 {
2975 int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
2976 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
2977 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
2978 break;
2979 }
2980
2981 DMAR_LOCK(pDevIns, pThisR3);
2982 if (dmarInvQueueCanProcessRequests(pThis))
2983 {
2984 uint32_t offQueueHead;
2985 uint32_t offQueueTail;
2986 bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
2987 if (!fIsEmpty)
2988 {
2989 /*
2990 * Get the current queue size, descriptor width, queue base address and the
2991 * table translation mode while the lock is still held.
2992 */
2993 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
2994 uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
2995 uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
2996 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
2997 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2998 RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
2999
3000 /* Paranoia. */
3001 Assert(cbQueue <= cbMaxQs);
3002 Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3003 Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3004 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueTail & RT_BIT(4)));
3005 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueHead & RT_BIT(4)));
3006 Assert(offQueueHead < cbQueue);
3007
3008 /*
3009 * A table translation mode of "reserved" isn't valid for any descriptor type.
3010 * However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3011 * but if ESRTPS is support, we will perform a global invalidation when software
3012 * changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3013 * So caching TTM while reading all descriptors should not be a problem.
3014 *
3015 * Also, validate the queue tail offset as it's mutable by software.
3016 */
3017 if ( fTtm != VTD_TTM_RSVD
3018 && offQueueTail < cbQueue)
3019 {
3020 /* Don't hold the lock while reading (a potentially large amount of) requests */
3021 DMAR_UNLOCK(pDevIns, pThisR3);
3022
3023 int rc;
3024 uint32_t cbRequests;
3025 if (offQueueTail > offQueueHead)
3026 {
3027 /* The requests have not wrapped around, read them in one go. */
3028 cbRequests = offQueueTail - offQueueHead;
3029 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3030 }
3031 else
3032 {
3033 /* The requests have wrapped around, read forward and wrapped-around. */
3034 uint32_t const cbForward = cbQueue - offQueueHead;
3035 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3036
3037 uint32_t const cbWrapped = offQueueTail;
3038 if ( RT_SUCCESS(rc)
3039 && cbWrapped > 0)
3040 {
3041 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3042 (void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3043 }
3044 cbRequests = cbForward + cbWrapped;
3045 }
3046
3047 /* Re-acquire the lock since we need to update device state. */
3048 DMAR_LOCK(pDevIns, pThisR3);
3049
3050 if (RT_SUCCESS(rc))
3051 {
3052 /* Indicate to software we've fetched all requests. */
3053 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3054
3055 /* Don't hold the lock while processing requests. */
3056 DMAR_UNLOCK(pDevIns, pThisR3);
3057
3058 /* Process all requests. */
3059 Assert(cbRequests <= cbQueue);
3060 dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3061
3062 /*
3063 * We've processed all requests and the lock shouldn't be held at this point.
3064 * Using 'continue' here allows us to skip re-acquiring the lock just to release
3065 * it again before going back to the thread loop. It's a bit ugly but it certainly
3066 * helps with performance.
3067 */
3068 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3069 continue;
3070 }
3071 else
3072 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3073 }
3074 else
3075 {
3076 if (fTtm == VTD_TTM_RSVD)
3077 dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3078 else
3079 {
3080 Assert(offQueueTail >= cbQueue);
3081 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3082 }
3083 }
3084 }
3085 }
3086 DMAR_UNLOCK(pDevIns, pThisR3);
3087 }
3088
3089 RTMemFree(pvRequests);
3090 pvRequests = NULL;
3091
3092 LogFlowFunc(("Invalidation-queue thread terminating\n"));
3093 return VINF_SUCCESS;
3094}
3095
3096
3097/**
3098 * Wakes up the invalidation-queue thread so it can respond to a state
3099 * change.
3100 *
3101 * @returns VBox status code.
3102 * @param pDevIns The IOMMU device instance.
3103 * @param pThread The invalidation-queue thread.
3104 *
3105 * @thread EMT.
3106 */
3107static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3108{
3109 RT_NOREF(pThread);
3110 LogFlowFunc(("\n"));
3111 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3112 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3113}
3114
3115
3116/**
3117 * @callback_method_impl{FNDBGFHANDLERDEV}
3118 */
3119static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3120{
3121 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3122 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3123 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3124
3125 /*
3126 * We lock the device to get a consistent register state as it is
3127 * ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3128 * ones we care about here) into temporaries and release the lock ASAP.
3129 *
3130 * Order of register being read and outputted is in accordance with the
3131 * spec. for no particular reason.
3132 * See Intel VT-d spec. 10.4 "Register Descriptions".
3133 */
3134 DMAR_LOCK(pDevIns, pThisR3);
3135
3136 DMARDIAG const enmDiag = pThis->enmDiag;
3137 uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3138 uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3139 uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3140 uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3141 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3142 uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3143 uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3144 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3145 uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3146 uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3147 uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3148 uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3149 uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3150 uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3151 uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3152 uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3153 uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3154 uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3155 uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3156 uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3157 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3158 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3159 uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3160 uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3161 uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3162 uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3163 uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3164 uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3165 uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3166 uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3167 uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3168 uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3169 uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3170 uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3171 uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3172 uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3173 uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3174 uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3175
3176 DMAR_UNLOCK(pDevIns, pThisR3);
3177
3178 const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3179 pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3180 pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3181
3182 /*
3183 * Non-verbose output.
3184 */
3185 if (!fVerbose)
3186 {
3187 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3188 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3189 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3190 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3191 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3192 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3193 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3194 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3195 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3196 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3197 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3198 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3199 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3200 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3201 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3202 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3203 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3204 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3205 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3206 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3207 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3208 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3209 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3210 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3211 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3212 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3213 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3214 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3215 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3216 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3217 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3218 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3219 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3220 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3221 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3222 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3223 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3224 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3225 pHlp->pfnPrintf(pHlp, "\n");
3226 return;
3227 }
3228
3229 /*
3230 * Verbose output.
3231 */
3232 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3233 {
3234 pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3235 pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3236 }
3237 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3238 {
3239 uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3240 uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3241 pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3242 pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3243 pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3244 pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3245 pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3246 pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3247 pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3248 pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3249 pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3250 pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3251 pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3252 pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3253 pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3254 pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3255 pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3256 pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3257 pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3258 pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3259 pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3260 pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3261 pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3262 }
3263 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3264 {
3265 uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3266 pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3267 pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3268 pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3269 pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3270 pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3271 pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3272 pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3273 pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3274 pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3275 pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3276 pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3277 pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3278 pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3279 pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3280 pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3281 pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3282 pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3283 pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3284 pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3285 pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3286 pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3287 pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3288 pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3289 pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3290 pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3291 pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3292 pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3293 pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3294 pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3295 }
3296 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3297 {
3298 uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3299 pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3300 pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3301 pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3302 pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3303 pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3304 pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3305 pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3306 pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3307 pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3308 }
3309 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3310 {
3311 uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3312 pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3313 pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3314 pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3315 pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3316 pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3317 pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3318 pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3319 pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3320 pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3321 }
3322 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3323 {
3324 uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3325 pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3326 pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3327 }
3328 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3329 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3330 {
3331 pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3332 pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3333 pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3334 pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3335 pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3336 pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3337 pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3338 pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3339 }
3340 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3341 {
3342 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3343 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3344 }
3345 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3346 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3347 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3348 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3349 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3350 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3351 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3352 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3353 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3354 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3355 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3356 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3357 {
3358 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3359 uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3360 uint8_t const cQueuePages = 1 << fQs;
3361 pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3362 pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3363 }
3364 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3365 {
3366 pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3367 }
3368 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3369 {
3370 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3371 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3372 }
3373 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3374 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3375 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3376 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3377 {
3378 pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3379 pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3380 pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3381 }
3382 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3383 {
3384 uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3385 uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3386 pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3387 pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3388 pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3389 }
3390 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3391 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3392 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3393 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3394 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3395 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3396 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3397 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3398 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3399 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3400 pHlp->pfnPrintf(pHlp, "\n");
3401}
3402
3403
3404/**
3405 * Initializes all registers in the DMAR unit.
3406 *
3407 * @param pDevIns The IOMMU device instance.
3408 */
3409static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3410{
3411 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3412
3413 /*
3414 * Wipe all registers (required on reset).
3415 */
3416 RT_ZERO(pThis->abRegs0);
3417 RT_ZERO(pThis->abRegs1);
3418
3419 /*
3420 * Initialize registers not mutable by software prior to initializing other registers.
3421 */
3422 /* VER_REG */
3423 {
3424 pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3425 | RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3426 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3427 }
3428
3429 uint8_t const fFlts = 1; /* First-level translation support. */
3430 uint8_t const fSlts = 1; /* Second-level translation support. */
3431 uint8_t const fPt = 1; /* Pass-Through support. */
3432 uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3433 uint8_t const fNest = 0; /* Nested translation support. */
3434
3435 /* CAP_REG */
3436 {
3437 uint8_t cGstPhysAddrBits;
3438 uint8_t cGstLinearAddrBits;
3439 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3440
3441 uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3442 uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3443 uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3444 uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3445 uint8_t const fSllps = fSl2mp | (fSl2gp << 1); /* Second-level large page support. */
3446 uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3447 : X86_PAGE_2M_SHIFT)
3448 - X86_PAGE_4K_SHIFT;
3449 uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3450 uint8_t const fPsi = 1; /* Page selective invalidation. */
3451 uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3452 uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3453 uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3454 uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3455 uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3456 AssertCompile(DMAR_ND <= 6);
3457
3458 pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3459 | RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3460 | RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3461 | RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3462 | RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3463 | RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3464 | RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts & fSagaw)
3465 | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3466 | RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3467 | RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3468 | RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3469 | RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3470 | RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3471 | RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3472 | RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3473 | RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3474 | RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3475 | RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3476 | RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3477 | RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3478 | RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3479 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3480
3481 pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3482 pThis->fInvMgawMask = UINT64_MAX << cGstPhysAddrBits;
3483 pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3484 }
3485
3486 /* ECAP_REG */
3487 {
3488 uint8_t const fQi = 1; /* Queued-invalidations. */
3489 uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3490 uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3491 uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3492 uint8_t const fEim = 1; /* Extended interrupt mode.*/
3493 uint8_t const fAdms = 1; /* Abort DMA mode support. */
3494 uint8_t const fErs = 0; /* Execute Request (not supported). */
3495
3496 pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3497 | RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3498 | RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3499 | RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3500 | RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3501 | RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3502 | RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3503 | RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3504 | RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3505 | RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3506 | RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3507 | RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3508 | RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3509 | RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3510 | RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3511 | RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /** @todo figure out if EAFS is required? */
3512 | RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3513 | RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID support. */
3514 | RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3515 | RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3516 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3517 | RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3518 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3519 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3520 | RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3521 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3522 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3523 | RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3524 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3525 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3526
3527 pThis->fPermValidMask = DMAR_PERM_READ | DMAR_PERM_WRITE;
3528 if (fErs)
3529 pThis->fPermValidMask = DMAR_PERM_EXE;
3530 }
3531
3532 /*
3533 * Initialize registers mutable by software.
3534 */
3535 /* FECTL_REG */
3536 {
3537 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3538 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3539 }
3540
3541 /* ICETL_REG */
3542 {
3543 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3544 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3545 }
3546
3547#ifdef VBOX_STRICT
3548 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3549 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3550#endif
3551}
3552
3553
3554/**
3555 * @interface_method_impl{PDMDEVREG,pfnReset}
3556 */
3557static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
3558{
3559 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3560 LogFlowFunc(("\n"));
3561
3562 DMAR_LOCK(pDevIns, pThisR3);
3563 dmarR3RegsInit(pDevIns);
3564 DMAR_UNLOCK(pDevIns, pThisR3);
3565}
3566
3567
3568/**
3569 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3570 */
3571static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
3572{
3573 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3574 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3575 LogFlowFunc(("\n"));
3576
3577 DMAR_LOCK(pDevIns, pThisR3);
3578
3579 if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
3580 {
3581 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
3582 pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
3583 }
3584
3585 DMAR_UNLOCK(pDevIns, pThisR3);
3586 return VINF_SUCCESS;
3587}
3588
3589
3590/**
3591 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3592 */
3593static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3594{
3595 RT_NOREF(pCfg);
3596
3597 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3598 PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
3599 pThisR3->pDevInsR3 = pDevIns;
3600
3601 LogFlowFunc(("iInstance=%d\n", iInstance));
3602 NOREF(iInstance);
3603
3604 /*
3605 * Register the IOMMU with PDM.
3606 */
3607 PDMIOMMUREGR3 IommuReg;
3608 RT_ZERO(IommuReg);
3609 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3610 IommuReg.pfnMemAccess = iommuIntelMemAccess;
3611 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3612 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3613 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3614 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3615 if (RT_FAILURE(rc))
3616 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3617 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3618 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3619 N_("IOMMU helper version mismatch; got %#x expected %#x"),
3620 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3621 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3622 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3623 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3624 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3625 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
3626 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
3627 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
3628 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
3629
3630 /*
3631 * Use PDM's critical section (via helpers) for the IOMMU device.
3632 */
3633 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3634 AssertRCReturn(rc, rc);
3635
3636 /*
3637 * Initialize PCI configuration registers.
3638 */
3639 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3640 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3641
3642 /* Header. */
3643 PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3644 PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3645 PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3646 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
3647 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
3648 PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
3649 PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3650 PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3651
3652 /** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
3653 PDMPciDevSetStatus(pPciDev, 0);
3654 PDMPciDevSetCapabilityList(pPciDev, 0);
3655
3656 /** @todo VTBAR at 0x180? */
3657
3658 /*
3659 * Register the PCI function with PDM.
3660 */
3661 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3662 AssertLogRelRCReturn(rc, rc);
3663
3664 /** @todo Register MSI but what's the MSI capability offset? */
3665#if 0
3666 /*
3667 * Register MSI support for the PCI device.
3668 * This must be done -after- registering it as a PCI device!
3669 */
3670#endif
3671
3672 /*
3673 * Register MMIO region.
3674 */
3675 AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
3676 rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
3677 IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
3678 &pThis->hMmio);
3679 AssertLogRelRCReturn(rc, rc);
3680
3681 /*
3682 * Register debugger info items.
3683 */
3684 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
3685 AssertLogRelRCReturn(rc, rc);
3686
3687#ifdef VBOX_WITH_STATISTICS
3688 /*
3689 * Statistics.
3690 */
3691 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
3692 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
3693
3694 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
3695 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
3696
3697 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
3698 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
3699 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
3700 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
3701
3702 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
3703 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
3704
3705 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
3706 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
3707
3708 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
3709 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
3710
3711 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
3712 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
3713
3714 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
3715 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
3716 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
3717 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
3718 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
3719 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
3720 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
3721 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
3722#endif
3723
3724 /*
3725 * Initialize registers.
3726 */
3727 dmarR3RegsInit(pDevIns);
3728
3729 /*
3730 * Create invalidation-queue thread and semaphore.
3731 */
3732 char szInvQueueThread[32];
3733 RT_ZERO(szInvQueueThread);
3734 RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
3735 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
3736 0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
3737 AssertLogRelRCReturn(rc, rc);
3738
3739 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
3740 AssertLogRelRCReturn(rc, rc);
3741
3742 /*
3743 * Log some of the features exposed to software.
3744 */
3745 uint32_t const uVerReg = pThis->uVerReg;
3746 uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
3747 uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
3748 uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
3749 uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
3750 LogRel(("%s: VER=%u.%u CAP=%#RX64 ECAP=%#RX64 (MGAW=%u bits, SAGAW=%#x HAW_Base=%#RX64 MGAW_Inv=%#RX64 FRO=%#x IRO=%#x) mapped at %#RGp\n",
3751 DMAR_LOG_PFX, RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX), RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN),
3752 pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask, pThis->fInvMgawMask, offFrcd, offIva,
3753 DMAR_MMIO_BASE_PHYSADDR));
3754
3755 return VINF_SUCCESS;
3756}
3757
3758#else
3759
3760/**
3761 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
3762 */
3763static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
3764{
3765 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
3766 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3767 PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
3768 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
3769
3770 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
3771 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3772 AssertRCReturn(rc, rc);
3773
3774 /* Set up the MMIO RZ handlers. */
3775 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
3776 AssertRCReturn(rc, rc);
3777
3778 /* Set up the IOMMU RZ callbacks. */
3779 PDMIOMMUREGCC IommuReg;
3780 RT_ZERO(IommuReg);
3781 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3782 IommuReg.idxIommu = pThis->idxIommu;
3783 IommuReg.pfnMemAccess = iommuIntelMemAccess;
3784 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3785 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3786 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3787
3788 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
3789 AssertRCReturn(rc, rc);
3790 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
3791 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
3792 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
3793 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
3794 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
3795 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
3796 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
3797
3798 return VINF_SUCCESS;
3799}
3800
3801#endif
3802
3803
3804/**
3805 * The device registration structure.
3806 */
3807PDMDEVREG const g_DeviceIommuIntel =
3808{
3809 /* .u32Version = */ PDM_DEVREG_VERSION,
3810 /* .uReserved0 = */ 0,
3811 /* .szName = */ "iommu-intel",
3812 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
3813 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
3814 /* .cMaxInstances = */ 1,
3815 /* .uSharedVersion = */ 42,
3816 /* .cbInstanceShared = */ sizeof(DMAR),
3817 /* .cbInstanceCC = */ sizeof(DMARCC),
3818 /* .cbInstanceRC = */ sizeof(DMARRC),
3819 /* .cMaxPciDevices = */ 1,
3820 /* .cMaxMsixVectors = */ 0,
3821 /* .pszDescription = */ "IOMMU (Intel)",
3822#if defined(IN_RING3)
3823 /* .pszRCMod = */ "VBoxDDRC.rc",
3824 /* .pszR0Mod = */ "VBoxDDR0.r0",
3825 /* .pfnConstruct = */ iommuIntelR3Construct,
3826 /* .pfnDestruct = */ iommuIntelR3Destruct,
3827 /* .pfnRelocate = */ NULL,
3828 /* .pfnMemSetup = */ NULL,
3829 /* .pfnPowerOn = */ NULL,
3830 /* .pfnReset = */ iommuIntelR3Reset,
3831 /* .pfnSuspend = */ NULL,
3832 /* .pfnResume = */ NULL,
3833 /* .pfnAttach = */ NULL,
3834 /* .pfnDetach = */ NULL,
3835 /* .pfnQueryInterface = */ NULL,
3836 /* .pfnInitComplete = */ NULL,
3837 /* .pfnPowerOff = */ NULL,
3838 /* .pfnSoftReset = */ NULL,
3839 /* .pfnReserved0 = */ NULL,
3840 /* .pfnReserved1 = */ NULL,
3841 /* .pfnReserved2 = */ NULL,
3842 /* .pfnReserved3 = */ NULL,
3843 /* .pfnReserved4 = */ NULL,
3844 /* .pfnReserved5 = */ NULL,
3845 /* .pfnReserved6 = */ NULL,
3846 /* .pfnReserved7 = */ NULL,
3847#elif defined(IN_RING0)
3848 /* .pfnEarlyConstruct = */ NULL,
3849 /* .pfnConstruct = */ iommuIntelRZConstruct,
3850 /* .pfnDestruct = */ NULL,
3851 /* .pfnFinalDestruct = */ NULL,
3852 /* .pfnRequest = */ NULL,
3853 /* .pfnReserved0 = */ NULL,
3854 /* .pfnReserved1 = */ NULL,
3855 /* .pfnReserved2 = */ NULL,
3856 /* .pfnReserved3 = */ NULL,
3857 /* .pfnReserved4 = */ NULL,
3858 /* .pfnReserved5 = */ NULL,
3859 /* .pfnReserved6 = */ NULL,
3860 /* .pfnReserved7 = */ NULL,
3861#elif defined(IN_RC)
3862 /* .pfnConstruct = */ iommuIntelRZConstruct,
3863 /* .pfnReserved0 = */ NULL,
3864 /* .pfnReserved1 = */ NULL,
3865 /* .pfnReserved2 = */ NULL,
3866 /* .pfnReserved3 = */ NULL,
3867 /* .pfnReserved4 = */ NULL,
3868 /* .pfnReserved5 = */ NULL,
3869 /* .pfnReserved6 = */ NULL,
3870 /* .pfnReserved7 = */ NULL,
3871#else
3872# error "Not in IN_RING3, IN_RING0 or IN_RC!"
3873#endif
3874 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
3875};
3876
3877#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
3878
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