DevIommuIntel.cpp@ 89499

Last change on this file since 89499 was 89499, checked in by vboxsync, 3 years ago
Intel IOMMU: bugref:9967 Nits.
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1	/* $Id: DevIommuIntel.cpp 89499 2021-06-04 09:36:58Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock (not expected to fail). */
67	#ifdef IN_RING3
68	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69	#else
70	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71	do { \
72	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73	AssertRC(rcLock); \
74	} while (0)
75	#endif
76
77	/** Release the DMAR lock. */
78	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80	/** Asserts that the calling thread owns the DMAR lock. */
81	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82	do { \
83	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84	RT_NOREF1(a_pThisCC); \
85	} while (0)
86
87	/** Asserts that the calling thread does not own the DMAR lock. */
88	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89	do { \
90	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91	RT_NOREF1(a_pThisCC); \
92	} while (0)
93
94	/** The number of fault recording registers our implementation supports.
95	* Normal guest operation shouldn't trigger faults anyway, so we only support the
96	* minimum number of registers (which is 1).
97	*
98	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101	/** Offset of first register in group 0. */
102	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
103	/** Offset of last register in group 0 (inclusive). */
104	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
105	/** Last valid offset in group 0 (exclusive). */
106	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
107	/** Size of the group 0 (in bytes). */
108	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
109	/*< Implementation-specific MMIO offset of IVA_REG. /
110	#define DMAR_MMIO_OFF_IVA_REG 0xe50
111	/*< Implementation-specific MMIO offset of IOTLB_REG. /
112	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
113	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
114	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
115	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
116	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
117	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
118
119	/** Offset of first register in group 1. */
120	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
121	/** Offset of last register in group 1 (inclusive). */
122	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
123	/** Last valid offset in group 1 (exclusive). */
124	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
125	/** Size of the group 1 (in bytes). */
126	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
127
128	/** DMAR implementation's major version number (exposed to software).
129	* We report 6 as the major version since we support queued-invalidations as
130	* software may make assumptions based on that.
131	*
132	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
133	#define DMAR_VER_MAJOR 6
134	/** DMAR implementation's minor version number (exposed to software). */
135	#define DMAR_VER_MINOR 0
136
137	/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
138	* 7=Reserved). */
139	#define DMAR_ND 6
140
141	/** @name DMAR_PERM_XXX: DMA request permissions.
142	* The order of R, W, X bits is important as it corresponds to those bits in
143	* page-table entries.
144	*
145	* @{ */
146	/** DMA request permission: Read. */
147	#define DMAR_PERM_READ RT_BIT(0)
148	/** DMA request permission: Write. */
149	#define DMAR_PERM_WRITE RT_BIT(1)
150	/** DMA request permission: Execute (ER). */
151	#define DMAR_PERM_EXE RT_BIT(2)
152	/** DMA request permission: Supervisor privilege (PR). */
153	#define DMAR_PERM_PRIV RT_BIT(3)
154	/** DMA request permissions: All. */
155	#define DMAR_PERM_ALL (DMAR_PERM_READ \| DMAR_PERM_WRITE \| DMAR_PERM_EXE \| DMAR_PERM_PRIV)
156	/** @} */
157
158	/** Release log prefix string. */
159	#define DMAR_LOG_PFX "Intel-IOMMU"
160	/** The current saved state version. */
161	#define DMAR_SAVED_STATE_VERSION 1
162
163
164	/*********************************************************************************************************************************
165	* Structures and Typedefs *
166	*********************************************************************************************************************************/
167	/**
168	* DMAR error diagnostics.
169	* Sorted alphabetically so it's easier to add and locate items, no other reason.
170	*
171	* @note Members of this enum are used as array indices, so no gaps in enum
172	* values are not allowed. Update g_apszDmarDiagDesc when you modify
173	* fields in this enum.
174	*/
175	typedef enum
176	{
177	/* No error, this must be zero! */
178	kDmarDiag_None = 0,
179
180	/* Address Translation Faults. */
181	kDmarDiag_Atf_Lct_1,
182	kDmarDiag_Atf_Lct_2,
183	kDmarDiag_Atf_Lct_3,
184	kDmarDiag_Atf_Lct_4_1,
185	kDmarDiag_Atf_Lct_4_2,
186	kDmarDiag_Atf_Lct_4_3,
187	kDmarDiag_Atf_Lct_5,
188	kDmarDiag_Atf_Lgn_1_1,
189	kDmarDiag_Atf_Lgn_1_2,
190	kDmarDiag_Atf_Lgn_1_3,
191	kDmarDiag_Atf_Lgn_4,
192	kDmarDiag_Atf_Lrt_1,
193	kDmarDiag_Atf_Lrt_2,
194	kDmarDiag_Atf_Lrt_3,
195	kDmarDiag_Atf_Lsl_1,
196	kDmarDiag_Atf_Lsl_2,
197	kDmarDiag_Atf_Lsl_2_LargePage,
198	kDmarDiag_Atf_Rta_1_1,
199	kDmarDiag_Atf_Rta_1_2,
200	kDmarDiag_Atf_Rta_1_3,
201	kDmarDiag_Atf_Sgn_5,
202	kDmarDiag_Atf_Sgn_8,
203	kDmarDiag_Atf_Ssl_1,
204	kDmarDiag_Atf_Ssl_2,
205	kDmarDiag_Atf_Ssl_3,
206	kDmarDiag_Atf_Ssl_3_LargePage,
207
208	/* CCMD_REG faults. */
209	kDmarDiag_CcmdReg_NotSupported,
210	kDmarDiag_CcmdReg_Qi_Enabled,
211	kDmarDiag_CcmdReg_Ttm_Invalid,
212
213	/* IQA_REG faults. */
214	kDmarDiag_IqaReg_Dsc_Fetch_Error,
215	kDmarDiag_IqaReg_Dw_128_Invalid,
216	kDmarDiag_IqaReg_Dw_256_Invalid,
217
218	/* Invalidation Queue Error Info. */
219	kDmarDiag_Iqei_Dsc_Type_Invalid,
220	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
221	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
222	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
223	kDmarDiag_Iqei_Ttm_Rsvd,
224
225	/* IQT_REG faults. */
226	kDmarDiag_IqtReg_Qt_Invalid,
227	kDmarDiag_IqtReg_Qt_NotAligned,
228
229	/* Compatibility Format Interrupt Faults. */
230	kDmarDiag_Ir_Cfi_Blocked,
231
232	/* Remappable Format Interrupt Faults. */
233	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
234	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
235	kDmarDiag_Ir_Rfi_Irte_Not_Present,
236	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
237	kDmarDiag_Ir_Rfi_Irte_Rsvd,
238	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
239	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
240	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
241	kDmarDiag_Ir_Rfi_Rsvd,
242
243	/* Member for determining array index limit. */
244	kDmarDiag_End,
245
246	/* Usual 32-bit type size hack. */
247	kDmarDiag_32Bit_Hack = 0x7fffffff
248	} DMARDIAG;
249	AssertCompileSize(DMARDIAG, 4);
250
251	/** DMAR diagnostic enum description expansion.
252	* The below construct ensures typos in the input to this macro are caught
253	* during compile time. */
254	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
255
256	/** DMAR diagnostics description for members in DMARDIAG. */
257	static const char *const g_apszDmarDiagDesc[] =
258	{
259	DMARDIAG_DESC(None ),
260	DMARDIAG_DESC(Atf_Lct_1 ),
261	DMARDIAG_DESC(Atf_Lct_2 ),
262	DMARDIAG_DESC(Atf_Lct_3 ),
263	DMARDIAG_DESC(Atf_Lct_4_1 ),
264	DMARDIAG_DESC(Atf_Lct_4_2 ),
265	DMARDIAG_DESC(Atf_Lct_4_3 ),
266	DMARDIAG_DESC(Atf_Lct_5 ),
267	DMARDIAG_DESC(Atf_Lgn_1_1 ),
268	DMARDIAG_DESC(Atf_Lgn_1_2 ),
269	DMARDIAG_DESC(Atf_Lgn_1_3 ),
270	DMARDIAG_DESC(Atf_Lgn_4 ),
271	DMARDIAG_DESC(Atf_Lrt_1 ),
272	DMARDIAG_DESC(Atf_Lrt_2 ),
273	DMARDIAG_DESC(Atf_Lrt_3 ),
274	DMARDIAG_DESC(Atf_Lsl_1 ),
275	DMARDIAG_DESC(Atf_Lsl_2 ),
276	DMARDIAG_DESC(Atf_Lsl_2_LargePage ),
277	DMARDIAG_DESC(Atf_Rta_1_1 ),
278	DMARDIAG_DESC(Atf_Rta_1_2 ),
279	DMARDIAG_DESC(Atf_Rta_1_3 ),
280	DMARDIAG_DESC(Atf_Sgn_5 ),
281	DMARDIAG_DESC(Atf_Sgn_8 ),
282	DMARDIAG_DESC(Atf_Ssl_1 ),
283	DMARDIAG_DESC(Atf_Ssl_2 ),
284	DMARDIAG_DESC(Atf_Ssl_3 ),
285	DMARDIAG_DESC(Atf_Ssl_3_LargePage ),
286	DMARDIAG_DESC(CcmdReg_NotSupported ),
287	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
288	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
289	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
290	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
291	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
292	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
293	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd),
294	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd),
295	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
296	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
297	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
298	DMARDIAG_DESC(IqtReg_Qt_NotAligned ),
299	DMARDIAG_DESC(Ir_Cfi_Blocked ),
300	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
301	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
302	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
303	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
304	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
305	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
306	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
307	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
308	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
309	/* kDmarDiag_End */
310	};
311	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
312	#undef DMARDIAG_DESC
313
314	/**
315	* The shared DMAR device state.
316	*/
317	typedef struct DMAR
318	{
319	/** IOMMU device index. */
320	uint32_t idxIommu;
321	/** DMAR magic. */
322	uint32_t u32Magic;
323
324	/** Registers (group 0). */
325	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
326	/** Registers (group 1). */
327	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
328
329	/** @name Lazily activated registers.
330	* These are the active values for lazily activated registers. Software is free to
331	* modify the actual register values while remapping/translation is enabled but they
332	* take effect only when explicitly signaled by software, hence we need to hold the
333	* active values separately.
334	* @{ */
335	/** Currently active IRTA_REG. */
336	uint64_t uIrtaReg;
337	/** Currently active RTADDR_REG. */
338	uint64_t uRtaddrReg;
339	/** @} */
340
341	/** @name Register copies for a tiny bit faster and more convenient access.
342	* @{ */
343	/** Copy of VER_REG. */
344	uint8_t uVerReg;
345	/** Alignment. */
346	uint8_t abPadding[7];
347	/** Copy of CAP_REG. */
348	uint64_t fCapReg;
349	/** Copy of ECAP_REG. */
350	uint64_t fExtCapReg;
351	/** @} */
352
353	/** Host-address width (HAW) base address mask. */
354	uint64_t fHawBaseMask;
355	/** Maximum guest-address width (MGAW) invalid address mask. */
356	uint64_t fMgawInvMask;
357	/** Maximum supported paging level (3, 4 or 5). */
358	uint8_t cMaxPagingLevel;
359	/** DMA request valid permissions mask. */
360	uint8_t fPermValidMask;
361
362	/** The event semaphore the invalidation-queue thread waits on. */
363	SUPSEMEVENT hEvtInvQueue;
364	/** Padding. */
365	uint32_t uPadding0;
366	/** Error diagnostic. */
367	DMARDIAG enmDiag;
368	/** The MMIO handle. */
369	IOMMMIOHANDLE hMmio;
370
371	#ifdef VBOX_WITH_STATISTICS
372	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
373	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
374	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
375	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
376
377	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
378	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
379	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
380	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
381
382	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
383	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
384	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
385	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
386
387	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
388	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
389	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
390	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
391
392	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
393	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
394	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
395	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
396	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
397	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
398	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
399	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
400	#endif
401	} DMAR;
402	/** Pointer to the DMAR device state. */
403	typedef DMAR *PDMAR;
404	/** Pointer to the const DMAR device state. */
405	typedef DMAR const *PCDMAR;
406	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
407	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
408
409	/**
410	* The ring-3 DMAR device state.
411	*/
412	typedef struct DMARR3
413	{
414	/** Device instance. */
415	PPDMDEVINSR3 pDevInsR3;
416	/** The IOMMU helper. */
417	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
418	/** The invalidation-queue thread. */
419	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
420	} DMARR3;
421	/** Pointer to the ring-3 DMAR device state. */
422	typedef DMARR3 *PDMARR3;
423	/** Pointer to the const ring-3 DMAR device state. */
424	typedef DMARR3 const *PCDMARR3;
425
426	/**
427	* The ring-0 DMAR device state.
428	*/
429	typedef struct DMARR0
430	{
431	/** Device instance. */
432	PPDMDEVINSR0 pDevInsR0;
433	/** The IOMMU helper. */
434	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
435	} DMARR0;
436	/** Pointer to the ring-0 IOMMU device state. */
437	typedef DMARR0 *PDMARR0;
438	/** Pointer to the const ring-0 IOMMU device state. */
439	typedef DMARR0 const *PCDMARR0;
440
441	/**
442	* The raw-mode DMAR device state.
443	*/
444	typedef struct DMARRC
445	{
446	/** Device instance. */
447	PPDMDEVINSRC pDevInsRC;
448	/** The IOMMU helper. */
449	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
450	} DMARRC;
451	/** Pointer to the raw-mode DMAR device state. */
452	typedef DMARRC *PDMARRC;
453	/** Pointer to the const raw-mode DMAR device state. */
454	typedef DMARRC const *PCIDMARRC;
455
456	/** The DMAR device state for the current context. */
457	typedef CTX_SUFF(DMAR) DMARCC;
458	/** Pointer to the DMAR device state for the current context. */
459	typedef CTX_SUFF(PDMAR) PDMARCC;
460	/** Pointer to the const DMAR device state for the current context. */
461	typedef CTX_SUFF(PDMAR) const PCDMARCC;
462
463	/**
464	* DMAR originated events that generate interrupts.
465	*/
466	typedef enum DMAREVENTTYPE
467	{
468	/** Invalidation completion event. */
469	DMAREVENTTYPE_INV_COMPLETE = 0,
470	/** Fault event. */
471	DMAREVENTTYPE_FAULT
472	} DMAREVENTTYPE;
473
474	/**
475	* I/O Page.
476	*/
477	typedef struct DMARIOPAGE
478	{
479	/** The base DMA address of a page. */
480	RTGCPHYS GCPhysBase;
481	/** The page shift. */
482	uint8_t cShift;
483	/** The permissions of this page (DMAR_PERM_XXX). */
484	uint8_t fPerm;
485	} DMARIOPAGE;
486	/** Pointer to an I/O page. */
487	typedef DMARIOPAGE *PDMARIOPAGE;
488	/** Pointer to a const I/O address range. */
489	typedef DMARIOPAGE const *PCDMARIOPAGE;
490
491	/**
492	* I/O Address Range.
493	*/
494	typedef struct DMARIOADDRRANGE
495	{
496	/** The starting DMA address of this range. */
497	uint64_t uAddr;
498	/** The size of the range (in bytes). */
499	size_t cb;
500	/** The permissions of this range (DMAR_PERM_XXX). */
501	uint8_t fPerm;
502	} DMARIOADDRRANGE;
503	/** Pointer to an I/O address range. */
504	typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
505	/** Pointer to a const I/O address range. */
506	typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
507
508	/**
509	* DMA Memory Request (Input).
510	*/
511	typedef struct DMARMEMREQIN
512	{
513	/** The address range being accessed. */
514	DMARIOADDRRANGE AddrRange;
515	/** The source device ID (bus, device, function). */
516	uint16_t idDevice;
517	/** The PASID if present (can be NIL_PCIPASID). */
518	PCIPASID Pasid;
519	/* The address translation type. */
520	PCIADDRTYPE enmAddrType;
521	/** The request type. */
522	VTDREQTYPE enmReqType;
523	} DMARMEMREQIN;
524	/** Pointer to a DMA memory request input. */
525	typedef DMARMEMREQIN *PDMARMEMREQIN;
526	/** Pointer to a const DMA memory input. */
527	typedef DMARMEMREQIN const *PCDMARMEMREQIN;
528
529	/**
530	* DMA Memory Request (Output).
531	*/
532	typedef struct DMARMEMREQOUT
533	{
534	/** The address range of the translated region. */
535	DMARIOADDRRANGE AddrRange;
536	/** The domain ID of the translated region. */
537	uint16_t idDomain;
538	} DMARMEMREQOUT;
539	/** Pointer to a DMA memory request output. */
540	typedef DMARMEMREQOUT *PDMARMEMREQOUT;
541	/** Pointer to a const DMA memory request output. */
542	typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
543
544	/**
545	* DMA Memory Request (Auxiliary Info).
546	* These get updated and used as part of the translation process.
547	*/
548	typedef struct DMARMEMREQAUX
549	{
550	/** The table translation mode (VTD_TTM_XXX). */
551	uint8_t fTtm;
552	/** The fault processing disabled (FPD) bit. */
553	uint8_t fFpd;
554	/** The paging level of the translation. */
555	uint8_t cPagingLevel;
556	uint8_t afPadding[5];
557	/** The first-level page-table pointer. */
558	uint64_t uFlptPtr;
559	/** The second-level page-table pointer. */
560	uint64_t uSlptPtr;
561	} DMARMEMREQAUX;
562	/** Pointer to a DMA memory request output. */
563	typedef DMARMEMREQAUX *PDMARMEMREQAUX;
564	/** Pointer to a const DMA memory request output. */
565	typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
566
567	/**
568	* DMA Memory Request Remapping Information.
569	*/
570	typedef struct DMARMEMREQREMAP
571	{
572	/** The DMA memory request input. */
573	DMARMEMREQIN In;
574	/** DMA memory request auxiliary information. */
575	DMARMEMREQAUX Aux;
576	/** The DMA memory request output. */
577	DMARMEMREQOUT Out;
578	} DMARMEMREQREMAP;
579	/** Pointer to a DMA remap info. */
580	typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
581	/** Pointer to a const DMA remap info. */
582	typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
583
584	typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
585	PDMARIOPAGE pIoPageOut));
586	typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
587
588
589	/*********************************************************************************************************************************
590	* Global Variables *
591	*********************************************************************************************************************************/
592	/**
593	* Read-write masks for DMAR registers (group 0).
594	*/
595	static uint32_t const g_au32RwMasks0[] =
596	{
597	/* Offset Register Low High */
598	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
599	/* 0x004 Reserved */ 0,
600	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
601	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
602	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
603	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
604	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
605	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
606	/* 0x030 Reserved */ 0,
607	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
608	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
609	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
610	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
611	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
612	/* 0x048 Reserved */ 0, 0,
613	/* 0x050 Reserved */ 0, 0,
614	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
615	/* 0x060 Reserved */ 0,
616	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
617	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
618	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
619	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
620	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
621	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
622	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
623	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
624	/* 0x098 Reserved */ 0,
625	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
626	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
627	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
628	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
629	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
630	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
631	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
632	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
633	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
634	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
635	/* 0x0d8 Reserved */ 0,
636	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
637	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
638	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
639	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
640	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
641	/* 0x0f0 Reserved */ 0, 0,
642	/* 0x0f8 Reserved */ 0, 0,
643	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
644	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
645	/* 0x110 Reserved */ 0, 0,
646	/* 0x118 Reserved */ 0, 0,
647	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
648	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
649	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
650	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
651	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
652	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
653	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
654	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
655	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
656	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
657	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
658	/* 0x178 Reserved */ 0, 0,
659	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
660	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
661	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
662	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
663	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
664	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
665	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
666	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
667	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
668	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
669	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
670	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
671	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
672	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
673	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
674	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
675	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
676	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
677	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
678	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
679	};
680	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
681
682	/**
683	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
684	*/
685	static uint32_t const g_au32Rw1cMasks0[] =
686	{
687	/* Offset Register Low High */
688	/* 0x000 VER_REG */ 0,
689	/* 0x004 Reserved */ 0,
690	/* 0x008 CAP_REG */ 0, 0,
691	/* 0x010 ECAP_REG */ 0, 0,
692	/* 0x018 GCMD_REG */ 0,
693	/* 0x01c GSTS_REG */ 0,
694	/* 0x020 RTADDR_REG */ 0, 0,
695	/* 0x028 CCMD_REG */ 0, 0,
696	/* 0x030 Reserved */ 0,
697	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
698	/* 0x038 FECTL_REG */ 0,
699	/* 0x03c FEDATA_REG */ 0,
700	/* 0x040 FEADDR_REG */ 0,
701	/* 0x044 FEUADDR_REG */ 0,
702	/* 0x048 Reserved */ 0, 0,
703	/* 0x050 Reserved */ 0, 0,
704	/* 0x058 AFLOG_REG */ 0, 0,
705	/* 0x060 Reserved */ 0,
706	/* 0x064 PMEN_REG */ 0,
707	/* 0x068 PLMBASE_REG */ 0,
708	/* 0x06c PLMLIMIT_REG */ 0,
709	/* 0x070 PHMBASE_REG */ 0, 0,
710	/* 0x078 PHMLIMIT_REG */ 0, 0,
711	/* 0x080 IQH_REG */ 0, 0,
712	/* 0x088 IQT_REG */ 0, 0,
713	/* 0x090 IQA_REG */ 0, 0,
714	/* 0x098 Reserved */ 0,
715	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
716	/* 0x0a0 IECTL_REG */ 0,
717	/* 0x0a4 IEDATA_REG */ 0,
718	/* 0x0a8 IEADDR_REG */ 0,
719	/* 0x0ac IEUADDR_REG */ 0,
720	/* 0x0b0 IQERCD_REG */ 0, 0,
721	/* 0x0b8 IRTA_REG */ 0, 0,
722	/* 0x0c0 PQH_REG */ 0, 0,
723	/* 0x0c8 PQT_REG */ 0, 0,
724	/* 0x0d0 PQA_REG */ 0, 0,
725	/* 0x0d8 Reserved */ 0,
726	/* 0x0dc PRS_REG */ 0,
727	/* 0x0e0 PECTL_REG */ 0,
728	/* 0x0e4 PEDATA_REG */ 0,
729	/* 0x0e8 PEADDR_REG */ 0,
730	/* 0x0ec PEUADDR_REG */ 0,
731	/* 0x0f0 Reserved */ 0, 0,
732	/* 0x0f8 Reserved */ 0, 0,
733	/* 0x100 MTRRCAP_REG */ 0, 0,
734	/* 0x108 MTRRDEF_REG */ 0, 0,
735	/* 0x110 Reserved */ 0, 0,
736	/* 0x118 Reserved */ 0, 0,
737	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
738	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
739	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
740	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
741	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
742	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
743	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
744	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
745	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
746	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
747	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
748	/* 0x178 Reserved */ 0, 0,
749	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
750	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
751	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
752	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
753	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
754	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
755	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
756	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
757	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
758	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
759	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
760	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
761	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
762	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
763	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
764	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
765	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
766	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
767	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
768	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
769	};
770	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
771
772	/**
773	* Read-write masks for DMAR registers (group 1).
774	*/
775	static uint32_t const g_au32RwMasks1[] =
776	{
777	/* Offset Register Low High */
778	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
779	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
780	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
781	/* 0xe18 VCMDRSVD_REG */ 0, 0,
782	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
783	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
784	/* 0xe30 Reserved */ 0, 0,
785	/* 0xe38 Reserved */ 0, 0,
786	/* 0xe40 Reserved */ 0, 0,
787	/* 0xe48 Reserved */ 0, 0,
788	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
789	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
790	/* 0xe60 Reserved */ 0, 0,
791	/* 0xe68 Reserved */ 0, 0,
792	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
793	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
794	};
795	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
796	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
797
798	/**
799	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
800	*/
801	static uint32_t const g_au32Rw1cMasks1[] =
802	{
803	/* Offset Register Low High */
804	/* 0xe00 VCCAP_REG */ 0, 0,
805	/* 0xe08 VCMD_EO_REG */ 0, 0,
806	/* 0xe10 VCMD_REG */ 0, 0,
807	/* 0xe18 VCMDRSVD_REG */ 0, 0,
808	/* 0xe20 VCRSP_REG */ 0, 0,
809	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
810	/* 0xe30 Reserved */ 0, 0,
811	/* 0xe38 Reserved */ 0, 0,
812	/* 0xe40 Reserved */ 0, 0,
813	/* 0xe48 Reserved */ 0, 0,
814	/* 0xe50 IVA_REG */ 0, 0,
815	/* 0xe58 IOTLB_REG */ 0, 0,
816	/* 0xe60 Reserved */ 0, 0,
817	/* 0xe68 Reserved */ 0, 0,
818	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
819	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
820	};
821	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
822
823	/** Array of RW masks for each register group. */
824	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
825
826	/** Array of RW1C masks for each register group. */
827	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
828
829	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
830	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
831
832	/** Array of valid domain-ID bits. */
833	static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
834	AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
835
836
837	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
838	/** @todo Add IOMMU struct size/alignment verification, see
839	* Devices/testcase/Makefile.kmk and
840	* Devices/testcase/tstDeviceStructSize[RC].cpp */
841
842	/**
843	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
844	* guest address width (MGAW).
845	*
846	* @returns The CAP_REG.SAGAW value.
847	* @param uMgaw The CAP_REG.MGAW value.
848	*/
849	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
850	{
851	/*
852	* It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
853	* 5-level paging but not 4 or 3-level paging. So smaller page-table levels
854	* are always OR'ed in below.
855	*
856	* The bit values below (57, 48, 39 bits) represents the levels of page-table walks
857	* for 4KB base page size (5-level, 4-level and 3-level paging respectively).
858	*
859	* See Intel VT-d spec. 10.4.2 "Capability Register".
860	*/
861	++uMgaw;
862	uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1)
863	: uMgaw >= 48 ? RT_BIT(2) \| RT_BIT(1)
864	: uMgaw >= 39 ? RT_BIT(1)
865	: 0;
866	return fSagaw;
867	}
868
869
870	/**
871	* Returns the maximum supported paging level given the supported adjusted
872	* guest-address width (SAGAW) field.
873	*
874	* @returns The highest paging level supported, 0 if invalid.
875	* @param fSagaw The CAP_REG.SAGAW value.
876	*/
877	static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
878	{
879	uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
880	: fSagaw & RT_BIT(2) ? 4
881	: fSagaw & RT_BIT(1) ? 3
882	: 0;
883	return cMaxPagingLevel;
884	}
885
886
887	/**
888	* Returns whether the interrupt remapping (IR) fault is qualified or not.
889	*
890	* @returns @c true if qualified, @c false otherwise.
891	* @param enmIrFault The interrupt remapping fault condition.
892	*/
893	static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
894	{
895	switch (enmIrFault)
896	{
897	case VTDIRFAULT_IRTE_NOT_PRESENT:
898	case VTDIRFAULT_IRTE_PRESENT_RSVD:
899	case VTDIRFAULT_IRTE_PRESENT_INVALID:
900	case VTDIRFAULT_PID_READ_FAILED:
901	case VTDIRFAULT_PID_RSVD:
902	return true;
903	default:
904	return false;
905	}
906	}
907
908
909	/**
910	* Returns table translation mode's descriptive name.
911	*
912	* @returns The descriptive name.
913	* @param uTtm The RTADDR_REG.TTM value.
914	*/
915	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
916	{
917	Assert(!(uTtm & 3));
918	static const char* s_apszTtmNames[] =
919	{
920	"Legacy Mode",
921	"Scalable Mode",
922	"Reserved",
923	"Abort-DMA Mode"
924	};
925	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
926	}
927
928
929	/**
930	* Gets the index of the group the register belongs to given its MMIO offset.
931	*
932	* @returns The group index.
933	* @param offReg The MMIO offset of the register.
934	* @param cbReg The size of the access being made (for bounds checking on
935	* debug builds).
936	*/
937	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
938	{
939	uint16_t const offLast = offReg + cbReg - 1;
940	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
941	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
942	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
943	}
944
945
946	/**
947	* Gets the group the register belongs to given its MMIO offset.
948	*
949	* @returns Pointer to the first element of the register group.
950	* @param pThis The shared DMAR device state.
951	* @param offReg The MMIO offset of the register.
952	* @param cbReg The size of the access being made (for bounds checking on
953	* debug builds).
954	* @param pIdxGroup Where to store the index of the register group the register
955	* belongs to.
956	*/
957	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
958	{
959	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
960	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
961	return apbRegs[*pIdxGroup];
962	}
963
964
965	/**
966	* Const/read-only version of dmarRegGetGroup.
967	*
968	* @copydoc dmarRegGetGroup
969	*/
970	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
971	{
972	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
973	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
974	return apbRegs[*pIdxGroup];
975	}
976
977
978	/**
979	* Writes a 32-bit register with the exactly the supplied value.
980	*
981	* @param pThis The shared DMAR device state.
982	* @param offReg The MMIO offset of the register.
983	* @param uReg The 32-bit value to write.
984	*/
985	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
986	{
987	uint8_t idxGroup;
988	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
989	NOREF(idxGroup);
990	(uint32_t )(pabRegs + offReg) = uReg;
991	}
992
993
994	/**
995	* Writes a 64-bit register with the exactly the supplied value.
996	*
997	* @param pThis The shared DMAR device state.
998	* @param offReg The MMIO offset of the register.
999	* @param uReg The 64-bit value to write.
1000	*/
1001	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1002	{
1003	uint8_t idxGroup;
1004	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1005	NOREF(idxGroup);
1006	(uint64_t )(pabRegs + offReg) = uReg;
1007	}
1008
1009
1010	/**
1011	* Reads a 32-bit register with exactly the value it contains.
1012	*
1013	* @returns The raw register value.
1014	* @param pThis The shared DMAR device state.
1015	* @param offReg The MMIO offset of the register.
1016	*/
1017	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1018	{
1019	uint8_t idxGroup;
1020	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1021	NOREF(idxGroup);
1022	return (uint32_t )(pabRegs + offReg);
1023	}
1024
1025
1026	/**
1027	* Reads a 64-bit register with exactly the value it contains.
1028	*
1029	* @returns The raw register value.
1030	* @param pThis The shared DMAR device state.
1031	* @param offReg The MMIO offset of the register.
1032	*/
1033	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1034	{
1035	uint8_t idxGroup;
1036	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1037	NOREF(idxGroup);
1038	return (uint64_t )(pabRegs + offReg);
1039	}
1040
1041
1042	/**
1043	* Reads a 32-bit register with exactly the value it contains along with their
1044	* corresponding masks
1045	*
1046	* @param pThis The shared DMAR device state.
1047	* @param offReg The MMIO offset of the register.
1048	* @param puReg Where to store the raw 32-bit register value.
1049	* @param pfRwMask Where to store the RW mask corresponding to this register.
1050	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1051	*/
1052	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
1053	{
1054	uint8_t idxGroup;
1055	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1056	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1057	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1058	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1059	puReg = (uint32_t *)(pabRegs + offReg);
1060	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
1061	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
1062	}
1063
1064
1065	/**
1066	* Reads a 64-bit register with exactly the value it contains along with their
1067	* corresponding masks.
1068	*
1069	* @param pThis The shared DMAR device state.
1070	* @param offReg The MMIO offset of the register.
1071	* @param puReg Where to store the raw 64-bit register value.
1072	* @param pfRwMask Where to store the RW mask corresponding to this register.
1073	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1074	*/
1075	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
1076	{
1077	uint8_t idxGroup;
1078	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1079	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1080	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1081	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1082	puReg = (uint64_t *)(pabRegs + offReg);
1083	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
1084	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
1085	}
1086
1087
1088	/**
1089	* Writes a 32-bit register as it would be when written by software.
1090	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1091	*
1092	* @returns The value that's actually written to the register.
1093	* @param pThis The shared DMAR device state.
1094	* @param offReg The MMIO offset of the register.
1095	* @param uReg The 32-bit value to write.
1096	* @param puPrev Where to store the register value prior to writing.
1097	*/
1098	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1099	{
1100	/* Read current value from the 32-bit register. */
1101	uint32_t uCurReg;
1102	uint32_t fRwMask;
1103	uint32_t fRw1cMask;
1104	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1105	*puPrev = uCurReg;
1106
1107	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1108	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1109	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1110	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1111
1112	/* Write new value to the 32-bit register. */
1113	dmarRegWriteRaw32(pThis, offReg, uNewReg);
1114	return uNewReg;
1115	}
1116
1117
1118	/**
1119	* Writes a 64-bit register as it would be when written by software.
1120	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1121	*
1122	* @returns The value that's actually written to the register.
1123	* @param pThis The shared DMAR device state.
1124	* @param offReg The MMIO offset of the register.
1125	* @param uReg The 64-bit value to write.
1126	* @param puPrev Where to store the register value prior to writing.
1127	*/
1128	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1129	{
1130	/* Read current value from the 64-bit register. */
1131	uint64_t uCurReg;
1132	uint64_t fRwMask;
1133	uint64_t fRw1cMask;
1134	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1135	*puPrev = uCurReg;
1136
1137	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1138	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1139	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1140	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1141
1142	/* Write new value to the 64-bit register. */
1143	dmarRegWriteRaw64(pThis, offReg, uNewReg);
1144	return uNewReg;
1145	}
1146
1147
1148	/**
1149	* Reads a 32-bit register as it would be when read by software.
1150	*
1151	* @returns The register value.
1152	* @param pThis The shared DMAR device state.
1153	* @param offReg The MMIO offset of the register.
1154	*/
1155	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1156	{
1157	return dmarRegReadRaw32(pThis, offReg);
1158	}
1159
1160
1161	/**
1162	* Reads a 64-bit register as it would be when read by software.
1163	*
1164	* @returns The register value.
1165	* @param pThis The shared DMAR device state.
1166	* @param offReg The MMIO offset of the register.
1167	*/
1168	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1169	{
1170	return dmarRegReadRaw64(pThis, offReg);
1171	}
1172
1173
1174	/**
1175	* Modifies a 32-bit register.
1176	*
1177	* @param pThis The shared DMAR device state.
1178	* @param offReg The MMIO offset of the register.
1179	* @param fAndMask The AND mask (applied first).
1180	* @param fOrMask The OR mask.
1181	* @remarks This does NOT apply RO or RW1C masks while modifying the
1182	* register.
1183	*/
1184	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1185	{
1186	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1187	uReg = (uReg & fAndMask) \| fOrMask;
1188	dmarRegWriteRaw32(pThis, offReg, uReg);
1189	}
1190
1191
1192	/**
1193	* Modifies a 64-bit register.
1194	*
1195	* @param pThis The shared DMAR device state.
1196	* @param offReg The MMIO offset of the register.
1197	* @param fAndMask The AND mask (applied first).
1198	* @param fOrMask The OR mask.
1199	* @remarks This does NOT apply RO or RW1C masks while modifying the
1200	* register.
1201	*/
1202	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1203	{
1204	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1205	uReg = (uReg & fAndMask) \| fOrMask;
1206	dmarRegWriteRaw64(pThis, offReg, uReg);
1207	}
1208
1209
1210	/**
1211	* Checks if the invalidation-queue is empty.
1212	*
1213	* Extended version which optionally returns the current queue head and tail
1214	* offsets.
1215	*
1216	* @returns @c true if empty, @c false otherwise.
1217	* @param pThis The shared DMAR device state.
1218	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
1219	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1220	*/
1221	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
1222	{
1223	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1224	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1225	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1226
1227	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1228	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1229	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1230	if (poffQh)
1231	*poffQh = uIqhReg;
1232	if (poffQt)
1233	*poffQt = uIqtReg;
1234	return uIqtReg == uIqhReg;
1235	}
1236
1237
1238	/**
1239	* Checks if the invalidation-queue is empty.
1240	*
1241	* @returns @c true if empty, @c false otherwise.
1242	* @param pThis The shared DMAR device state.
1243	*/
1244	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1245	{
1246	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1247	}
1248
1249
1250	/**
1251	* Checks if the invalidation-queue is capable of processing requests.
1252	*
1253	* @returns @c true if the invalidation-queue can process requests, @c false
1254	* otherwise.
1255	* @param pThis The shared DMAR device state.
1256	*/
1257	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1258	{
1259	/* Check if queued-invalidation is enabled. */
1260	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1261	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1262	{
1263	/* Check if there are no invalidation-queue or timeout errors. */
1264	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1265	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1266	return true;
1267	}
1268	return false;
1269	}
1270
1271
1272	/**
1273	* Wakes up the invalidation-queue thread if there are requests to be processed.
1274	*
1275	* @param pDevIns The IOMMU device instance.
1276	*/
1277	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1278	{
1279	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1280	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1281	Log4Func(("\n"));
1282
1283	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1284
1285	if ( dmarInvQueueCanProcessRequests(pThis)
1286	&& !dmarInvQueueIsEmpty(pThis))
1287	{
1288	Log4Func(("Signaling the invalidation-queue thread\n"));
1289	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1290	}
1291	}
1292
1293
1294	/**
1295	* Raises an event on behalf of the DMAR.
1296	*
1297	* These are events that are generated by the DMAR itself (like faults and
1298	* invalidation completion notifications).
1299	*
1300	* @param pDevIns The IOMMU device instance.
1301	* @param enmEventType The DMAR event type.
1302	*
1303	* @remarks The DMAR lock must be held while calling this function.
1304	*/
1305	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1306	{
1307	uint16_t offCtlReg;
1308	uint32_t fIntrMaskedMask;
1309	uint32_t fIntrPendingMask;
1310	uint16_t offMsiAddrLoReg;
1311	uint16_t offMsiAddrHiReg;
1312	uint16_t offMsiDataReg;
1313	switch (enmEventType)
1314	{
1315	case DMAREVENTTYPE_INV_COMPLETE:
1316	{
1317	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1318	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1319	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1320	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1321	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1322	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1323	break;
1324	}
1325
1326	case DMAREVENTTYPE_FAULT:
1327	{
1328	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1329	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1330	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1331	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1332	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1333	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1334	break;
1335	}
1336
1337	default:
1338	{
1339	/* Shouldn't ever happen. */
1340	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1341	}
1342	}
1343
1344	/* Check if software has masked the interrupt. */
1345	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1346	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1347	if (!(uCtlReg & fIntrMaskedMask))
1348	{
1349	/*
1350	* Interrupt is unmasked, raise it.
1351	* Interrupts generated by the DMAR have trigger mode and level as 0.
1352	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1353	*/
1354	MSIMSG Msi;
1355	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1356	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1357	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1358	Assert(Msi.Data.n.u1Level == 0);
1359	Assert(Msi.Data.n.u1TriggerMode == 0);
1360
1361	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1362	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1363
1364	/* Clear interrupt pending bit. */
1365	uCtlReg &= ~fIntrPendingMask;
1366	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1367	}
1368	else
1369	{
1370	/* Interrupt is masked, set the interrupt pending bit. */
1371	uCtlReg \|= fIntrPendingMask;
1372	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1373	}
1374	}
1375
1376
1377	/**
1378	* Raises an interrupt in response to a fault event.
1379	*
1380	* @param pDevIns The IOMMU device instance.
1381	*
1382	* @remarks This assumes the caller has already set the required status bits in the
1383	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1384	*/
1385	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1386	{
1387	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1388	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1389	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1390
1391	#ifdef RT_STRICT
1392	{
1393	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1394	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1395	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1396	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1397	\| VTD_BF_FSTS_REG_IQE_MASK;
1398	Assert(uFstsReg & fFaultMask);
1399	}
1400	#endif
1401	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1402	}
1403
1404
1405	#ifdef IN_RING3
1406	/**
1407	* Raises an interrupt in response to an invalidation (complete) event.
1408	*
1409	* @param pDevIns The IOMMU device instance.
1410	*/
1411	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1412	{
1413	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1414	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1415	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1416
1417	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1418	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1419	{
1420	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1421	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1422	}
1423	}
1424	#endif /* IN_RING3 */
1425
1426
1427	/**
1428	* Checks if a primary fault can be recorded.
1429	*
1430	* @returns @c true if the fault can be recorded, @c false otherwise.
1431	* @param pDevIns The IOMMU device instance.
1432	* @param pThis The shared DMAR device state.
1433	*
1434	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1435	* NOT call it unless there is a fault condition!
1436	*/
1437	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1438	{
1439	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1440	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1441
1442	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1443	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1444	return false;
1445
1446	/*
1447	* If we add more FRCD registers, we'll have to loop through them here.
1448	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1449	* nor do we need to increment FRI.
1450	*
1451	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1452	*/
1453	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1454	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1455	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1456	{
1457	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1458	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1459	return false;
1460	}
1461
1462	return true;
1463	}
1464
1465
1466	/**
1467	* Records a primary fault.
1468	*
1469	* @param pDevIns The IOMMU device instance.
1470	* @param enmDiag The diagnostic reason.
1471	* @param uFrcdHi The FRCD_HI_REG value for this fault.
1472	* @param uFrcdLo The FRCD_LO_REG value for this fault.
1473	*/
1474	static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint64_t uFrcdHi, uint64_t uFrcdLo)
1475	{
1476	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1477	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1478
1479	DMAR_LOCK(pDevIns, pThisCC);
1480
1481	/* Update the diagnostic reason. */
1482	pThis->enmDiag = enmDiag;
1483
1484	/* We don't support advance fault logging. */
1485	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1486
1487	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1488	{
1489	/* Update the fault recording registers with the fault information. */
1490	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1491	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1492
1493	/* Set the Pending Primary Fault (PPF) field in the status register. */
1494	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1495
1496	/* Raise interrupt if necessary. */
1497	dmarFaultEventRaiseInterrupt(pDevIns);
1498	}
1499
1500	DMAR_UNLOCK(pDevIns, pThisCC);
1501	}
1502
1503
1504	/**
1505	* Records an interrupt request fault.
1506	*
1507	* @param pDevIns The IOMMU device instance.
1508	* @param enmDiag The diagnostic reason.
1509	* @param enmIrFault The interrupt fault reason.
1510	* @param idDevice The device ID (bus, device, function).
1511	* @param idxIntr The interrupt index.
1512	*/
1513	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIRFAULT enmIrFault, uint16_t idDevice, uint16_t idxIntr)
1514	{
1515	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1516	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1517	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1518	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1519	dmarPrimaryFaultRecord(pDevIns, enmDiag, uFrcdHi, uFrcdLo);
1520	}
1521
1522
1523	/**
1524	* Records a qualified interrupt request fault.
1525	*
1526	* Qualified faults are those that can be suppressed by software using the FPD bit
1527	* in the IRTE.
1528	*
1529	* @param pDevIns The IOMMU device instance.
1530	* @param enmDiag The diagnostic reason.
1531	* @param enmIrFault The interrupt fault reason.
1532	* @param idDevice The device ID (bus, device, function).
1533	* @param idxIntr The interrupt index.
1534	* @param pIrte The IRTE that caused this fault.
1535	*/
1536	static void dmarIrFaultRecordQualified(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIRFAULT enmIrFault, uint16_t idDevice,
1537	uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1538	{
1539	Assert(vtdIrFaultIsQualified(enmIrFault));
1540	Assert(pIrte);
1541	if (!(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK))
1542	return dmarIrFaultRecord(pDevIns, enmDiag, enmIrFault, idDevice, idxIntr);
1543	}
1544
1545
1546	/**
1547	* Records an address translation fault (extended version).
1548	*
1549	* @param pDevIns The IOMMU device instance.
1550	* @param enmDiag The diagnostic reason.
1551	* @param enmAtFault The address translation fault reason.
1552	* @param pMemReqIn The DMA memory request input.
1553	* @param pMemReqAux The DMA memory request auxiliary info.
1554	*/
1555	static void dmarAtFaultRecordEx(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDATFAULT enmAtFault, PCDMARMEMREQIN pMemReqIn,
1556	PCDMARMEMREQAUX pMemReqAux)
1557	{
1558	/*
1559	* Qualified faults are those that can be suppressed by software using the FPD bit
1560	* in the contex entry, scalable-mode context entry etc.
1561	*/
1562	if (!pMemReqAux->fFpd)
1563	{
1564	uint16_t const idDevice = pMemReqIn->idDevice;
1565	uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1566	uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1567	uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1568	uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1569	bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1570	uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1571	PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1572
1573	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1574	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1575	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1576	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1577	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1578	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1579	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1580	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1581	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1582	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1583	uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1584	dmarPrimaryFaultRecord(pDevIns, enmDiag, uFrcdHi, uFrcdLo);
1585	}
1586	}
1587
1588
1589	/**
1590	* Records an address translation fault.
1591	*
1592	* @param pDevIns The IOMMU device instance.
1593	* @param enmDiag The diagnostic reason.
1594	* @param enmAtFault The address translation fault reason.
1595	* @param pMemReqRemap The DMA memory request remapping info.
1596	*/
1597	static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDATFAULT enmAtFault, PCDMARMEMREQREMAP pMemReqRemap)
1598	{
1599	dmarAtFaultRecordEx(pDevIns, enmDiag, enmAtFault, &pMemReqRemap->In, &pMemReqRemap->Aux);
1600	}
1601
1602
1603	/**
1604	* Records an IQE fault.
1605	*
1606	* @param pDevIns The IOMMU device instance.
1607	* @param enmIqei The IQE information.
1608	* @param enmDiag The diagnostic reason.
1609	*/
1610	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1611	{
1612	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1613	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1614
1615	DMAR_LOCK(pDevIns, pThisCC);
1616
1617	/* Update the diagnostic reason. */
1618	pThis->enmDiag = enmDiag;
1619
1620	/* Set the error bit. */
1621	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1622	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1623
1624	/* Set the error information. */
1625	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1626	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1627
1628	dmarFaultEventRaiseInterrupt(pDevIns);
1629
1630	DMAR_UNLOCK(pDevIns, pThisCC);
1631	}
1632
1633
1634	/**
1635	* Handles writes to GCMD_REG.
1636	*
1637	* @returns Strict VBox status code.
1638	* @param pDevIns The IOMMU device instance.
1639	* @param uGcmdReg The value written to GCMD_REG.
1640	*/
1641	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1642	{
1643	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1644	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1645	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1646	uint64_t const fExtCapReg = pThis->fExtCapReg;
1647
1648	/* Queued-invalidation. */
1649	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1650	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1651	{
1652	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1653	{
1654	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1655	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1656	}
1657	else
1658	{
1659	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1660	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1661	}
1662	}
1663
1664	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1665	{
1666	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1667	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1668	{
1669	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1670	* supported. */
1671	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1672	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1673	}
1674
1675	/* Interrupt remapping. */
1676	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1677	{
1678	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1679	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1680	else
1681	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1682	}
1683
1684	/* Compatibility format interrupts. */
1685	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1686	{
1687	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1688	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1689	else
1690	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1691	}
1692	}
1693
1694	/* Set Root Table Pointer (SRTP). */
1695	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1696	{
1697	/** @todo Perform global invalidation of all remapping translation caches when
1698	* ESRTPS is supported. */
1699	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1700	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1701	}
1702
1703	/* Translation (DMA remapping). */
1704	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1705	{
1706	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1707	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1708	else
1709	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1710	}
1711
1712	return VINF_SUCCESS;
1713	}
1714
1715
1716	/**
1717	* Handles writes to CCMD_REG.
1718	*
1719	* @returns Strict VBox status code.
1720	* @param pDevIns The IOMMU device instance.
1721	* @param offReg The MMIO register offset.
1722	* @param cbReg The size of the MMIO access (in bytes).
1723	* @param uCcmdReg The value written to CCMD_REG.
1724	*/
1725	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1726	{
1727	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1728	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1729	{
1730	/* Check if we need to invalidate the context-context. */
1731	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1732	if (fIcc)
1733	{
1734	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1735	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1736	if (uMajorVersion < 6)
1737	{
1738	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1739	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1740	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1741	{
1742	/* Verify table translation mode is legacy. */
1743	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1744	if (fTtm == VTD_TTM_LEGACY_MODE)
1745	{
1746	/** @todo Invalidate. */
1747	return VINF_SUCCESS;
1748	}
1749	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1750	}
1751	else
1752	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1753	}
1754	else
1755	pThis->enmDiag = kDmarDiag_CcmdReg_NotSupported;
1756	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1757	}
1758	}
1759	return VINF_SUCCESS;
1760	}
1761
1762
1763	/**
1764	* Handles writes to FECTL_REG.
1765	*
1766	* @returns Strict VBox status code.
1767	* @param pDevIns The IOMMU device instance.
1768	* @param uFectlReg The value written to FECTL_REG.
1769	*/
1770	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1771	{
1772	/*
1773	* If software unmasks the interrupt when the interrupt is pending, we must raise
1774	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1775	*/
1776	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1777	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1778	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1779	return VINF_SUCCESS;
1780	}
1781
1782
1783	/**
1784	* Handles writes to FSTS_REG.
1785	*
1786	* @returns Strict VBox status code.
1787	* @param pDevIns The IOMMU device instance.
1788	* @param uFstsReg The value written to FSTS_REG.
1789	* @param uPrev The value in FSTS_REG prior to writing it.
1790	*/
1791	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1792	{
1793	/*
1794	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1795	* the interrupt pending (IP) bit must be cleared.
1796	*
1797	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1798	*/
1799	uint32_t const fChanged = uPrev ^ uFstsReg;
1800	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1801	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1802	{
1803	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1804	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1805	}
1806	return VINF_SUCCESS;
1807	}
1808
1809
1810	/**
1811	* Handles writes to IQT_REG.
1812	*
1813	* @returns Strict VBox status code.
1814	* @param pDevIns The IOMMU device instance.
1815	* @param offReg The MMIO register offset.
1816	* @param uIqtReg The value written to IQT_REG.
1817	*/
1818	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1819	{
1820	/* We only care about the low 32-bits, high 32-bits are reserved. */
1821	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1822	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1823
1824	/* Paranoia. */
1825	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1826
1827	uint32_t const offQt = uIqtReg;
1828	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1829	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1830
1831	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1832	if ( fDw != VTD_IQA_REG_DW_256_BIT
1833	\|\| !(offQt & RT_BIT(4)))
1834	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1835	else
1836	{
1837	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1838	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1839	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_NotAligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1840	}
1841	return VINF_SUCCESS;
1842	}
1843
1844
1845	/**
1846	* Handles writes to IQA_REG.
1847	*
1848	* @returns Strict VBox status code.
1849	* @param pDevIns The IOMMU device instance.
1850	* @param offReg The MMIO register offset.
1851	* @param uIqaReg The value written to IQA_REG.
1852	*/
1853	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1854	{
1855	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1856	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1857
1858	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1859	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1860	* cannot happen or that it's ignored when it does happen. */
1861
1862	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1863	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1864	if (fDw == VTD_IQA_REG_DW_256_BIT)
1865	{
1866	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1867	if (fSupports256BitDw)
1868	{ /* likely */ }
1869	else
1870	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1871	}
1872	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1873
1874	return VINF_SUCCESS;
1875	}
1876
1877
1878	/**
1879	* Handles writes to ICS_REG.
1880	*
1881	* @returns Strict VBox status code.
1882	* @param pDevIns The IOMMU device instance.
1883	* @param uIcsReg The value written to ICS_REG.
1884	*/
1885	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1886	{
1887	/*
1888	* If the IP field is set when software services the interrupt condition,
1889	* (by clearing the IWC field), the IP field must be cleared.
1890	*/
1891	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1892	{
1893	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1894	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1895	}
1896	return VINF_SUCCESS;
1897	}
1898
1899
1900	/**
1901	* Handles writes to IECTL_REG.
1902	*
1903	* @returns Strict VBox status code.
1904	* @param pDevIns The IOMMU device instance.
1905	* @param uIectlReg The value written to IECTL_REG.
1906	*/
1907	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1908	{
1909	/*
1910	* If software unmasks the interrupt when the interrupt is pending, we must raise
1911	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1912	*/
1913	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1914	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1915	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1916	return VINF_SUCCESS;
1917	}
1918
1919
1920	/**
1921	* Handles writes to FRCD_REG (High 64-bits).
1922	*
1923	* @returns Strict VBox status code.
1924	* @param pDevIns The IOMMU device instance.
1925	* @param offReg The MMIO register offset.
1926	* @param cbReg The size of the MMIO access (in bytes).
1927	* @param uFrcdHiReg The value written to FRCD_REG.
1928	* @param uPrev The value in FRCD_REG prior to writing it.
1929	*/
1930	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
1931	{
1932	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
1933	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
1934	{
1935	/*
1936	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
1937	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
1938	* has only 1 FRCD register.
1939	*
1940	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1941	*/
1942	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1943	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
1944	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
1945	{
1946	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
1947	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1948	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
1949	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1950	}
1951	}
1952	return VINF_SUCCESS;
1953	}
1954
1955
1956	/**
1957	* Performs a PCI target abort for a DMA remapping (DR) operation.
1958	*
1959	* @param pDevIns The IOMMU device instance.
1960	*/
1961	static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
1962	{
1963	/** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
1964	* as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
1965	* who knows. */
1966	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
1967	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
1968	PDMPciDevSetStatus(pPciDev, u16Status);
1969	}
1970
1971
1972	/**
1973	* Checks whether the address width (AW) is supported by our hardware
1974	* implementation for legacy mode address translation.
1975	*
1976	* @returns @c true if it's supported, @c false otherwise.
1977	* @param pThis The shared DMAR device state.
1978	* @param pCtxEntry The context entry.
1979	* @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
1980	*/
1981	static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
1982	{
1983	uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
1984	uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
1985	uint8_t const fAwMask = RT_BIT(fAw);
1986	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
1987	Assert(!(fSagaw & ~(RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3))));
1988
1989	uint8_t const cPagingLevel = fAw + 2;
1990	if (pcPagingLevel)
1991	*pcPagingLevel = cPagingLevel;
1992
1993	/* With pass-through, the address width must be the largest AGAW supported by hardware. */
1994	if (fTt == VTD_TT_UNTRANSLATED_PT)
1995	{
1996	Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
1997	return cPagingLevel == pThis->cMaxPagingLevel;
1998	}
1999
2000	/* The address width must be any of the ones supported by hardware. */
2001	if (fAw < 4)
2002	return (fSagaw & fAwMask) != 0;
2003
2004	return false;
2005	}
2006
2007
2008	/**
2009	* Reads a root entry from guest memory.
2010	*
2011	* @returns VBox status code.
2012	* @param pDevIns The IOMMU device instance.
2013	* @param uRtaddrReg The current RTADDR_REG value.
2014	* @param idxRootEntry The index of the root entry to read.
2015	* @param pRootEntry Where to store the read root entry.
2016	*/
2017	static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2018	{
2019	size_t const cbRootEntry = sizeof(*pRootEntry);
2020	RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2021	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2022	}
2023
2024
2025	/**
2026	* Reads a context entry from guest memory.
2027	*
2028	* @returns VBox status code.
2029	* @param pDevIns The IOMMU device instance.
2030	* @param GCPhysCtxTable The physical address of the context table.
2031	* @param idxCtxEntry The index of the context entry to read.
2032	* @param pCtxEntry Where to store the read context entry.
2033	*/
2034	static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2035	{
2036	/* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2037	size_t const cbCtxEntry = sizeof(*pCtxEntry);
2038	RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2039	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2040	}
2041
2042
2043	/**
2044	* Reads a second-level paging entry from guest memory.
2045	*
2046	* @returns VBox status code.
2047	* @param pDevIns The IOMMU device instance.
2048	* @param GCPhysSlptPtr The physical address of the SLPTPTR.
2049	* @param pSlpEntry Where to store the read SLPTPTR.
2050	*/
2051	static int dmarDrReadSlpPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhysSlptPtr, PVTD_SLP_ENTRY_T pSlpEntry)
2052	{
2053	/* We don't verify bits 63:HAW of GCPhysSlptPtr is 0 since reading from such an address should fail anyway. */
2054	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysSlptPtr, pSlpEntry, sizeof(*pSlpEntry));
2055	}
2056
2057
2058	/**
2059	* Validates and updates the output I/O page of a translation.
2060	*
2061	* @returns VBox status code.
2062	* @param pDevIns The IOMMU device instance.
2063	* @param GCPhysBase The output address of the translation.
2064	* @param cShift The page shift of the translated address.
2065	* @param fPerm The permissions granted for the translated region.
2066	* @param pMemReqIn The DMA memory request input.
2067	* @param pMemReqAux The DMA memory request auxiliary info.
2068	* @param pIoPageOut Where to store the output of the translation.
2069	*/
2070	static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2071	PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2072	{
2073	Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2074
2075	/* Ensure the output address is not in the interrupt address range. */
2076	if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2077	{
2078	pIoPageOut->GCPhysBase = GCPhysBase;
2079	pIoPageOut->cShift = cShift;
2080	pIoPageOut->fPerm = fPerm;
2081	return VINF_SUCCESS;
2082	}
2083
2084	if (pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE)
2085	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Lgn_4, VTDATFAULT_LGN_4, pMemReqIn, pMemReqAux);
2086	else
2087	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Sgn_8, VTDATFAULT_SGN_8, pMemReqIn, pMemReqAux);
2088	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2089	}
2090
2091
2092	/**
2093	* Performs second level translation.
2094	*
2095	* This is a DMA address lookup callback function which performs the translation
2096	* (and access control) as part of the lookup.
2097	*
2098	* @returns VBox status code.
2099	* @param pDevIns The IOMMU device instance.
2100	* @param pMemReqIn The DMA memory request input.
2101	* @param pMemReqAux The DMA memory request auxiliary info.
2102	* @param pIoPageOut Where to store the output of the translation.
2103	*/
2104	static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2105	PDMARIOPAGE pIoPageOut)
2106	{
2107	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2108
2109	/* Sanity. */
2110	Assert(pIoPageOut);
2111	Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ \| DMAR_PERM_WRITE));
2112	Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2113	\|\| pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2114
2115	/* Mask of valid paging entry bits. */
2116	static uint64_t const s_auPtEntityRsvd[] = { VTD_SL_PTE_VALID_MASK,
2117	VTD_SL_PDE_VALID_MASK,
2118	VTD_SL_PDPE_VALID_MASK,
2119	VTD_SL_PML4E_VALID_MASK,
2120	VTD_SL_PML5E_VALID_MASK };
2121
2122	/* Paranoia. */
2123	Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2124	AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == 5);
2125
2126	/* Second-level translations restricts input address to an implementation-specific MGAW. */
2127	uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2128	if (!(uAddrIn & pThis->fMgawInvMask))
2129	{ /* likely */ }
2130	else
2131	{
2132	if (pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE)
2133	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Lgn_1_1, VTDATFAULT_LGN_1_1, pMemReqIn, pMemReqAux);
2134	else
2135	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Sgn_5, VTDATFAULT_SGN_5, pMemReqIn, pMemReqAux);
2136	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2137	}
2138
2139	/*
2140	* Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2141	* Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2142	*/
2143	uint64_t uPtEntity = pMemReqAux->uSlptPtr;
2144	int8_t iLevel = pMemReqAux->cPagingLevel - 1;
2145	uint8_t cLevelShift = X86_PAGE_4K_SHIFT + (iLevel * 9);
2146	Assert(iLevel >= 2);
2147	for (;;)
2148	{
2149	/*
2150	* Check I/O permissions.
2151	* This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2152	*
2153	* See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2154	*/
2155	uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2156	uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2157	Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2158	Assert(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK); /* No Second-level access/dirty support. */
2159	if ((fPtPerm & fReqPerm) == fReqPerm)
2160	{ /* likely */ }
2161	else
2162	{
2163	if (pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE)
2164	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Lsl_2, VTDATFAULT_LSL_2, pMemReqIn, pMemReqAux);
2165	else
2166	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Ssl_2, VTDATFAULT_SSL_2, pMemReqIn, pMemReqAux);
2167	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2168	}
2169
2170	/*
2171	* Validate reserved bits of the current paging entry.
2172	*/
2173	if (!(uPtEntity & ~s_auPtEntityRsvd[iLevel]))
2174	{ /* likely */ }
2175	else
2176	{
2177	if (pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE)
2178	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Lsl_2, VTDATFAULT_LSL_2, pMemReqIn, pMemReqAux);
2179	else
2180	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Ssl_3, VTDATFAULT_SSL_3, pMemReqIn, pMemReqAux);
2181	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2182	}
2183
2184	/*
2185	* Check if this is a 1GB page or a 2MB page.
2186	*/
2187	AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2188	uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2189	if (fLargePage && iLevel > 0)
2190	{
2191	Assert(iLevel == 1 \|\| iLevel == 2); /* Is guaranteed by the reserved bits check above. */
2192	uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2193	if (fSllpsMask & RT_BIT(iLevel - 1))
2194	{
2195	/*
2196	* We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2197	* All other reserved bits are identical to the regular page-size paging entity which we've already
2198	* checked above.
2199	*/
2200	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2201
2202	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2203	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2204	}
2205
2206	if (pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE)
2207	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Lsl_2_LargePage, VTDATFAULT_LSL_2, pMemReqIn, pMemReqAux);
2208	else
2209	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Ssl_3_LargePage, VTDATFAULT_SSL_3, pMemReqIn, pMemReqAux);
2210	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2211	}
2212
2213	/*
2214	* If this is the final PTE, compute the translation address and we're done.
2215	*/
2216	if (iLevel == 0)
2217	{
2218	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2219	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2220	}
2221
2222	/*
2223	* Move to the next level.
2224	*/
2225	--iLevel;
2226	cLevelShift = X86_PAGE_4K_SHIFT + (iLevel * 9);
2227
2228	/*
2229	* Read the paging entry for the next level.
2230	*/
2231	{
2232	uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2233	uint64_t const offPte = idxPte << 3;
2234	RTGCPHYS const GCPhysPtEntity = uPtEntity \| offPte;
2235	int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2236	if (RT_SUCCESS(rc))
2237	{ /* likely */ }
2238	else
2239	{
2240	if (pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE)
2241	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Lsl_1, VTDATFAULT_LSL_1, pMemReqIn, pMemReqAux);
2242	else
2243	dmarAtFaultRecordEx(pDevIns, kDmarDiag_Atf_Ssl_1, VTDATFAULT_SSL_1, pMemReqIn, pMemReqAux);
2244	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2245	}
2246	}
2247	}
2248	}
2249
2250
2251	/**
2252	* Checks whether two consecutive I/O page results of a DMA memory request
2253	* translates to a physically contiguous region.
2254	*
2255	* @returns @c true if the I/O pages are contiguous, @c false otherwise.
2256	* @param pIoPagePrev The previous I/O page.
2257	* @param pIoPage The current I/O page.
2258	*/
2259	static bool dmarIsIoPageAccessContig(PCDMARIOPAGE pIoPagePrev, PCDMARIOPAGE pIoPage)
2260	{
2261	/* Paranoia: Permissions for pages of a DMA memory request must be identical. */
2262	Assert(pIoPagePrev->fPerm == pIoPage->fPerm);
2263
2264	size_t const cbPrev = RT_BIT_64(pIoPagePrev->cShift);
2265	RTGCPHYS const GCPhysPrev = pIoPagePrev->GCPhysBase;
2266	RTGCPHYS const GCPhys = pIoPage->GCPhysBase;
2267	#ifdef RT_STRICT
2268	/* Paranoia: Ensure offset bits are 0. */
2269	{
2270	uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pIoPagePrev->cShift);
2271	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pIoPage->cShift);
2272	Assert(!(GCPhysPrev & fOffMaskPrev));
2273	Assert(!(GCPhys & fOffMask));
2274	}
2275	#endif
2276	return GCPhysPrev + cbPrev == GCPhys;
2277	}
2278
2279
2280	/**
2281	* Looks up the range of addresses for a DMA memory request remapping.
2282	*
2283	* @returns VBox status code.
2284	* @param pDevIns The IOMMU device instance.
2285	* @param pfnLookup The DMA address lookup function.
2286	* @param pMemReqRemap The DMA memory request remapping info.
2287	*/
2288	static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2289	{
2290	RTGCPHYS GCPhysAddr = NIL_RTGCPHYS;
2291	DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2292	uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2293	size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2294	uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2295	uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2296	size_t cbRemaining = cbAddrIn;
2297
2298	int rc;
2299	DMARIOPAGE IoPagePrev;
2300	RT_ZERO(IoPagePrev);
2301	for (;;)
2302	{
2303	/* Update the input memory request with the next address in our range that needs translation. */
2304	MemReqIn.AddrRange.uAddr = uAddrInBase;
2305	MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2306
2307	DMARIOPAGE IoPage;
2308	rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2309	if (RT_SUCCESS(rc))
2310	{
2311	Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2312
2313	/* Store the translated address before continuing to access more pages. */
2314	if (cbRemaining == cbAddrIn)
2315	{
2316	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2317	uint64_t const offAddrOut = uAddrIn & fOffMask;
2318	Assert(!(IoPage.GCPhysBase & fOffMask));
2319	GCPhysAddr = IoPage.GCPhysBase \| offAddrOut;
2320	}
2321	/* Check if addresses translated so far result in a physically contiguous region. */
2322	else if (!dmarIsIoPageAccessContig(&IoPagePrev, &IoPage))
2323	{
2324	rc = VERR_OUT_OF_RANGE;
2325	break;
2326	}
2327
2328	/* Store the I/O page lookup from the first/previous access. */
2329	IoPagePrev = IoPage;
2330
2331	/* Check if we need to access more pages. */
2332	size_t const cbPage = RT_BIT_64(IoPage.cShift);
2333	if (cbRemaining > cbPage - offAddrIn)
2334	{
2335	cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2336	uAddrInBase += cbPage; /* Update address of the next access. */
2337	offAddrIn = 0; /* After first page, all pages are accessed from offset 0. */
2338	}
2339	else
2340	{
2341	/* Caller (PDM) doesn't expect more data accessed than what was requested. */
2342	cbRemaining = 0;
2343	break;
2344	}
2345	}
2346	else
2347	break;
2348	}
2349
2350	pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddr;
2351	pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2352	pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2353	return rc;
2354	}
2355
2356
2357	/**
2358	* Handles legacy mode DMA address remapping.
2359	*
2360	* @returns VBox status code.
2361	* @param pDevIns The IOMMU device instance.
2362	* @param uRtaddrReg The current RTADDR_REG value.
2363	* @param pMemReqRemap The DMA memory request remapping info.
2364	*/
2365	static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2366	{
2367	Assert(pMemReqRemap->Aux.fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2368
2369	/* Read the root-entry from guest memory. */
2370	uint8_t const idxRootEntry = RT_HI_U8(pMemReqRemap->In.idDevice);
2371	VTD_ROOT_ENTRY_T RootEntry;
2372	int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2373	if (RT_SUCCESS(rc))
2374	{
2375	/* Check if the root entry is present (must be done before validating reserved bits). */
2376	uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2377	uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2378	bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2379	if (fRootEntryPresent)
2380	{
2381	/* Validate reserved bits in the root entry. */
2382	if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2383	&& !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2384	{
2385	/* Read the context-entry from guest memory. */
2386	RTGCPHYS const GCPhysCtxTable = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_CTP);
2387	uint8_t const idxCtxEntry = RT_LO_U8(pMemReqRemap->In.idDevice);
2388	VTD_CONTEXT_ENTRY_T CtxEntry;
2389	rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2390	if (RT_SUCCESS(rc))
2391	{
2392	uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2393	uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2394
2395	/* Note the FPD bit which software can use to supress translation faults from here on in. */
2396	pMemReqRemap->Aux.fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2397
2398	/* Check if the context-entry is present (must be done before validating reserved bits). */
2399	bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2400	if (fCtxEntryPresent)
2401	{
2402	/* Validate reserved bits in the context-entry. */
2403	if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2404	&& !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
2405	{
2406	/* Get the domain ID for this mapping. */
2407	pMemReqRemap->Out.idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2408
2409	/* Validate the translation type (TT). */
2410	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2411	uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2412	switch (fTt)
2413	{
2414	case VTD_TT_UNTRANSLATED_SLP:
2415	{
2416	/*
2417	* Untranslated requests are translated using second-level paging structures referenced
2418	* through SLPTPTR. Translated requests and Translation Requests are blocked.
2419	*/
2420	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2421	{
2422	/* Validate the address width and get the paging level. */
2423	uint8_t cPagingLevel;
2424	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2425	{
2426	/* Read the SLPTPTR from guest memory. */
2427	VTD_SLP_ENTRY_T SlptPtr;
2428	RTGCPHYS const GCPhysSlptPtr = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2429	rc = dmarDrReadSlpPtr(pDevIns, GCPhysSlptPtr, &SlptPtr);
2430	if (RT_SUCCESS(rc))
2431	{
2432	/* Finally... perform second-level translation. */
2433	pMemReqRemap->Aux.uSlptPtr = SlptPtr;
2434	pMemReqRemap->Aux.cPagingLevel = cPagingLevel;
2435	return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2436	}
2437	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_4_3, VTDATFAULT_LCT_4_3, pMemReqRemap);
2438	}
2439	else
2440	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_4_1, VTDATFAULT_LCT_4_1, pMemReqRemap);
2441	}
2442	else
2443	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_5, VTDATFAULT_LCT_5, pMemReqRemap);
2444	break;
2445	}
2446
2447	case VTD_TT_UNTRANSLATED_PT:
2448	{
2449	/*
2450	* Untranslated requests are processed as pass-through (PT) if PT is supported.
2451	* Translated and translation requests are blocked. If PT isn't supported this TT value
2452	* is reserved which I assume raises a fault (hence fallthru below).
2453	*/
2454	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2455	{
2456	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2457	{
2458	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2459	{
2460	PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2461	PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2462	pOut->AddrRange.uAddr = pIn->AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2463	pOut->AddrRange.cb = pIn->AddrRange.cb;
2464	pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2465	return VINF_SUCCESS;
2466	}
2467	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lgn_1_3, VTDATFAULT_LGN_1_3, pMemReqRemap);
2468	}
2469	else
2470	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_5, VTDATFAULT_LCT_5, pMemReqRemap);
2471	break;
2472	}
2473	RT_FALL_THRU();
2474	}
2475
2476	case VTD_TT_UNTRANSLATED_DEV_TLB:
2477	{
2478	/*
2479	* Untranslated, translated and translation requests are supported but requires
2480	* device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2481	*/
2482	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2483	RT_FALL_THRU();
2484	}
2485
2486	default:
2487	{
2488	/* Any other TT value is reserved. */
2489	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_4_2, VTDATFAULT_LCT_4_2, pMemReqRemap);
2490	break;
2491	}
2492	}
2493	}
2494	else
2495	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_3, VTDATFAULT_LCT_3, pMemReqRemap);
2496	}
2497	else
2498	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_2, VTDATFAULT_LCT_2, pMemReqRemap);
2499	}
2500	else
2501	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lct_1, VTDATFAULT_LCT_1, pMemReqRemap);
2502	}
2503	else
2504	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_3, VTDATFAULT_LRT_3, pMemReqRemap);
2505	}
2506	else
2507	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_2, VTDATFAULT_LRT_2, pMemReqRemap);
2508	}
2509	else
2510	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Lrt_1, VTDATFAULT_LRT_1, pMemReqRemap);
2511	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2512	}
2513
2514
2515	/**
2516	* Handles remapping of DMA address requests in scalable mode.
2517	*
2518	* @returns VBox status code.
2519	* @param pDevIns The IOMMU device instance.
2520	* @param uRtaddrReg The current RTADDR_REG value.
2521	* @param pMemReqRemap The DMA memory request remapping info.
2522	*/
2523	static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2524	{
2525	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2526	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2527	{
2528	RT_NOREF1(uRtaddrReg);
2529	return VERR_NOT_IMPLEMENTED;
2530	}
2531
2532	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_3, VTDATFAULT_RTA_1_3, pMemReqRemap);
2533	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2534	}
2535
2536
2537	/**
2538	* Memory access bulk (one or more 4K pages) request from a device.
2539	*
2540	* @returns VBox status code.
2541	* @param pDevIns The IOMMU device instance.
2542	* @param idDevice The device ID (bus, device, function).
2543	* @param cIovas The number of addresses being accessed.
2544	* @param pauIovas The I/O virtual addresses for each page being accessed.
2545	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2546	* @param paGCPhysSpa Where to store the translated physical addresses.
2547	*
2548	* @thread Any.
2549	*/
2550	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2551	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2552	{
2553	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
2554	return VERR_NOT_IMPLEMENTED;
2555	}
2556
2557
2558	/**
2559	* Memory access transaction from a device.
2560	*
2561	* @returns VBox status code.
2562	* @param pDevIns The IOMMU device instance.
2563	* @param idDevice The device ID (bus, device, function).
2564	* @param uIova The I/O virtual address being accessed.
2565	* @param cbIova The size of the access.
2566	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2567	* @param pGCPhysSpa Where to store the translated system physical address.
2568	* @param pcbContiguous Where to store the number of contiguous bytes translated
2569	* and permission-checked.
2570	*
2571	* @thread Any.
2572	*/
2573	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2574	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2575	{
2576	/* Validate. */
2577	AssertPtr(pDevIns);
2578	AssertPtr(pGCPhysSpa);
2579	AssertPtr(pcbContiguous);
2580	Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2581	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2582
2583	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2584	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2585
2586	DMAR_LOCK(pDevIns, pThisCC);
2587	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2588	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2589	DMAR_UNLOCK(pDevIns, pThisCC);
2590
2591	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2592	{
2593	VTDREQTYPE enmReqType;
2594	uint8_t fReqPerm;
2595	if (fFlags & PDMIOMMU_MEM_F_READ)
2596	{
2597	enmReqType = VTDREQTYPE_READ;
2598	fReqPerm = DMAR_PERM_READ;
2599	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2600	}
2601	else
2602	{
2603	enmReqType = VTDREQTYPE_WRITE;
2604	fReqPerm = DMAR_PERM_WRITE;
2605	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2606	}
2607
2608	uint8_t const fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2609	DMARMEMREQREMAP MemReqRemap;
2610	RT_ZERO(MemReqRemap);
2611	MemReqRemap.In.AddrRange.uAddr = uIova;
2612	MemReqRemap.In.AddrRange.cb = cbIova;
2613	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2614	MemReqRemap.In.idDevice = idDevice;
2615	MemReqRemap.In.Pasid = NIL_PCIPASID;
2616	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2617	MemReqRemap.In.enmReqType = enmReqType;
2618	MemReqRemap.Aux.fTtm = fTtm;
2619	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2620
2621	int rc;
2622	switch (fTtm)
2623	{
2624	case VTD_TTM_LEGACY_MODE:
2625	{
2626	rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, &MemReqRemap);
2627	break;
2628	}
2629
2630	case VTD_TTM_SCALABLE_MODE:
2631	{
2632	rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, &MemReqRemap);
2633	break;
2634	}
2635
2636	case VTD_TTM_ABORT_DMA_MODE:
2637	{
2638	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2639	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2640	dmarDrTargetAbort(pDevIns);
2641	else
2642	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_1, VTDATFAULT_RTA_1_1, &MemReqRemap);
2643	break;
2644	}
2645
2646	default:
2647	{
2648	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2649	dmarAtFaultRecord(pDevIns, kDmarDiag_Atf_Rta_1_2, VTDATFAULT_RTA_1_2, &MemReqRemap);
2650	break;
2651	}
2652	}
2653
2654	*pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2655	*pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2656	return rc;
2657	}
2658
2659	*pGCPhysSpa = uIova;
2660	*pcbContiguous = cbIova;
2661	return VINF_SUCCESS;
2662	}
2663
2664
2665	/**
2666	* Reads an IRTE from guest memory.
2667	*
2668	* @returns VBox status code.
2669	* @param pDevIns The IOMMU device instance.
2670	* @param uIrtaReg The IRTA_REG.
2671	* @param idxIntr The interrupt index.
2672	* @param pIrte Where to store the read IRTE.
2673	*/
2674	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2675	{
2676	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2677
2678	size_t const cbIrte = sizeof(*pIrte);
2679	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2680	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2681	}
2682
2683
2684	/**
2685	* Remaps the source MSI to the destination MSI given the IRTE.
2686	*
2687	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2688	* IRTA_REG.EIME).
2689	* @param pIrte The IRTE used for the remapping.
2690	* @param pMsiIn The source MSI (currently unused).
2691	* @param pMsiOut Where to store the remapped MSI.
2692	*/
2693	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2694	{
2695	NOREF(pMsiIn);
2696	uint64_t const uIrteQword0 = pIrte->au64[0];
2697
2698	/*
2699	* Let's start with a clean slate and preserve unspecified bits if the need arises.
2700	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2701	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2702	* it copies it from the source MSI.
2703	*/
2704	RT_ZERO(*pMsiOut);
2705	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2706	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2707	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2708	if (fExtIntrMode)
2709	{
2710	/*
2711	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2712	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2713	*/
2714	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2715	pMsiOut->Addr.n.u8DestId = idDest;
2716	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2717	}
2718	else
2719	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2720
2721	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2722	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2723	pMsiOut->Data.n.u1Level = 1;
2724	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2725	}
2726
2727
2728	/**
2729	* Handles remapping of interrupts in remappable interrupt format.
2730	*
2731	* @returns VBox status code.
2732	* @param pDevIns The IOMMU device instance.
2733	* @param uIrtaReg The IRTA_REG.
2734	* @param idDevice The device ID (bus, device, function).
2735	* @param pMsiIn The source MSI.
2736	* @param pMsiOut Where to store the remapped MSI.
2737	*/
2738	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2739	{
2740	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2741
2742	/* Validate reserved bits in the interrupt request. */
2743	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2744	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2745	{
2746	/* Compute the index into the interrupt remap table. */
2747	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2748	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2749	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
2750	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2751	uint16_t const idxIntr = fSubHandleValid
2752	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2753	: uHandle;
2754
2755	/* Validate the index. */
2756	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2757	if (idxIntr < cEntries)
2758	{
2759	/** @todo Implement and read IRTE from interrupt-entry cache here. */
2760
2761	/* Read the interrupt remap table entry (IRTE) at the index. */
2762	VTD_IRTE_T Irte;
2763	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2764	if (RT_SUCCESS(rc))
2765	{
2766	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2767	uint64_t const uIrteQword0 = Irte.au64[0];
2768	uint64_t const uIrteQword1 = Irte.au64[1];
2769	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2770	if (fPresent)
2771	{
2772	/* Validate reserved bits in the IRTE. */
2773	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2774	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2775	if ( !(uIrteQword0 & ~fQw0ValidMask)
2776	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2777	{
2778	/* Validate requester id (the device ID) as configured in the IRTE. */
2779	bool fSrcValid;
2780	DMARDIAG enmIrDiag;
2781	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2782	switch (fSvt)
2783	{
2784	case VTD_IRTE_SVT_NONE:
2785	{
2786	fSrcValid = true;
2787	enmIrDiag = kDmarDiag_None;
2788	break;
2789	}
2790
2791	case VTD_IRTE_SVT_VALIDATE_MASK:
2792	{
2793	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2794	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2795	uint16_t const fValidMask = s_afValidMasks[idxMask];
2796	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2797	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2798	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2799	break;
2800	}
2801
2802	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2803	{
2804	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2805	uint8_t const uBusFirst = RT_HI_U8(idSource);
2806	uint8_t const uBusLast = RT_LO_U8(idSource);
2807	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2808	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2809	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2810	break;
2811	}
2812
2813	default:
2814	{
2815	fSrcValid = false;
2816	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2817	break;
2818	}
2819	}
2820
2821	if (fSrcValid)
2822	{
2823	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2824	if (!fPostedMode)
2825	{
2826	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2827	return VINF_SUCCESS;
2828	}
2829	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
2830	VTDIRFAULT_IRTE_PRESENT_RSVD, idDevice, idxIntr, &Irte);
2831	}
2832	else
2833	dmarIrFaultRecordQualified(pDevIns, enmIrDiag, VTDIRFAULT_IRTE_PRESENT_RSVD, idDevice, idxIntr,
2834	&Irte);
2835	}
2836	else
2837	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, VTDIRFAULT_IRTE_PRESENT_RSVD,
2838	idDevice, idxIntr, &Irte);
2839	}
2840	else
2841	dmarIrFaultRecordQualified(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, VTDIRFAULT_IRTE_NOT_PRESENT,
2842	idDevice, idxIntr, &Irte);
2843	}
2844	else
2845	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, VTDIRFAULT_IRTE_READ_FAILED, idDevice, idxIntr);
2846	}
2847	else
2848	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, VTDIRFAULT_INTR_INDEX_INVALID, idDevice, idxIntr);
2849	}
2850	else
2851	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, VTDIRFAULT_REMAPPABLE_INTR_RSVD, idDevice, 0 /* idxIntr */);
2852	return VERR_IOMMU_INTR_REMAP_DENIED;
2853	}
2854
2855
2856	/**
2857	* Interrupt remap request from a device.
2858	*
2859	* @returns VBox status code.
2860	* @param pDevIns The IOMMU device instance.
2861	* @param idDevice The device ID (bus, device, function).
2862	* @param pMsiIn The source MSI.
2863	* @param pMsiOut Where to store the remapped MSI.
2864	*/
2865	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2866	{
2867	/* Validate. */
2868	Assert(pDevIns);
2869	Assert(pMsiIn);
2870	Assert(pMsiOut);
2871	RT_NOREF1(idDevice);
2872
2873	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2874	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2875
2876	/* Lock and read all registers required for interrupt remapping up-front. */
2877	DMAR_LOCK(pDevIns, pThisCC);
2878	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2879	uint64_t const uIrtaReg = pThis->uIrtaReg;
2880	DMAR_UNLOCK(pDevIns, pThisCC);
2881
2882	/* Check if interrupt remapping is enabled. */
2883	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
2884	{
2885	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
2886	if (!fIsRemappable)
2887	{
2888	/* Handle compatibility format interrupts. */
2889	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
2890
2891	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
2892	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
2893	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
2894	{
2895	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
2896	return VERR_IOMMU_INTR_REMAP_DENIED;
2897	}
2898
2899	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
2900	pMsiOut = pMsiIn;
2901	return VINF_SUCCESS;
2902	}
2903
2904	/* Handle remappable format interrupts. */
2905	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
2906	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
2907	}
2908
2909	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
2910	pMsiOut = pMsiIn;
2911	return VINF_SUCCESS;
2912	}
2913
2914
2915	/**
2916	* @callback_method_impl{FNIOMMMIONEWWRITE}
2917	*/
2918	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
2919	{
2920	RT_NOREF1(pvUser);
2921	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2922
2923	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2924	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
2925
2926	uint16_t const offReg = off;
2927	uint16_t const offLast = offReg + cb - 1;
2928	if (DMAR_IS_MMIO_OFF_VALID(offLast))
2929	{
2930	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2931	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2932
2933	uint64_t uPrev = 0;
2934	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
2935	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
2936	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2937	switch (off)
2938	{
2939	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
2940	{
2941	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
2942	break;
2943	}
2944
2945	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
2946	case VTD_MMIO_OFF_CCMD_REG + 4:
2947	{
2948	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
2949	break;
2950	}
2951
2952	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
2953	{
2954	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
2955	break;
2956	}
2957
2958	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
2959	{
2960	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
2961	break;
2962	}
2963
2964	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
2965	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
2966	{
2967	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
2968	break;
2969	}
2970
2971	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
2972	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
2973	{
2974	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
2975	break;
2976	}
2977
2978	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
2979	{
2980	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
2981	break;
2982	}
2983
2984	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
2985	{
2986	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
2987	break;
2988	}
2989
2990	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
2991	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
2992	{
2993	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
2994	break;
2995	}
2996	}
2997
2998	DMAR_UNLOCK(pDevIns, pThisCC);
2999	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3000	return rcStrict;
3001	}
3002
3003	return VINF_IOM_MMIO_UNUSED_FF;
3004	}
3005
3006
3007	/**
3008	* @callback_method_impl{FNIOMMMIONEWREAD}
3009	*/
3010	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3011	{
3012	RT_NOREF1(pvUser);
3013	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3014
3015	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3016	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3017
3018	uint16_t const offReg = off;
3019	uint16_t const offLast = offReg + cb - 1;
3020	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3021	{
3022	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3023	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3024
3025	if (cb == 8)
3026	{
3027	(uint64_t )pv = dmarRegRead64(pThis, offReg);
3028	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
3029	}
3030	else
3031	{
3032	(uint32_t )pv = dmarRegRead32(pThis, offReg);
3033	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
3034	}
3035
3036	DMAR_UNLOCK(pDevIns, pThisCC);
3037	return VINF_SUCCESS;
3038	}
3039
3040	return VINF_IOM_MMIO_UNUSED_FF;
3041	}
3042
3043
3044	#ifdef IN_RING3
3045	/**
3046	* Process requests in the invalidation queue.
3047	*
3048	* @param pDevIns The IOMMU device instance.
3049	* @param pvRequests The requests to process.
3050	* @param cbRequests The size of all requests (in bytes).
3051	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3052	* VTD_IQA_REG_DW_256_BIT).
3053	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3054	*/
3055	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3056	uint8_t fTtm)
3057	{
3058	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3059	do \
3060	{ \
3061	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3062	return; \
3063	} while (0)
3064
3065	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3066	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3067
3068	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3069	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3070
3071	/*
3072	* The below check is redundant since we check both TTM and DW for each
3073	* descriptor type we process. However, the error reported by hardware
3074	* may differ hence this is kept commented out but not removed from the code
3075	* if we need to change this in the future.
3076	*
3077	* In our implementation, we would report the descriptor type as invalid,
3078	* while on real hardware it may report descriptor width as invalid.
3079	* The Intel VT-d spec. is not clear which error takes preceedence.
3080	*/
3081	#if 0
3082	/*
3083	* Verify that 128-bit descriptors are not used when operating in scalable mode.
3084	* We don't check this while software writes IQA_REG but defer it until now because
3085	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3086	* -IS- performed when software writes IQA_REG since it only requires checking against
3087	* immutable hardware features.
3088	*/
3089	if ( fTtm != VTD_TTM_SCALABLE_MODE
3090	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
3091	{ /* likely */ }
3092	else
3093	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3094	#endif
3095
3096	/*
3097	* Process requests in FIFO order.
3098	*/
3099	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3100	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3101	{
3102	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
3103	uint64_t const uQword0 = puDscQwords[0];
3104	uint64_t const uQword1 = puDscQwords[1];
3105	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3106	switch (fDscType)
3107	{
3108	case VTD_INV_WAIT_DSC_TYPE:
3109	{
3110	/* Validate descriptor type. */
3111	if ( fTtm == VTD_TTM_LEGACY_MODE
3112	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
3113	{ /* likely */ }
3114	else
3115	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3116
3117	/* Validate reserved bits. */
3118	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3119	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3120	: VTD_INV_WAIT_DSC_0_VALID_MASK;
3121	if ( !(uQword0 & ~fValidMask0)
3122	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3123	{ /* likely */ }
3124	else
3125	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3126
3127	if (fDw == VTD_IQA_REG_DW_256_BIT)
3128	{
3129	if ( !puDscQwords[2]
3130	&& !puDscQwords[3])
3131	{ /* likely */ }
3132	else
3133	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3134	}
3135
3136	/* Perform status write (this must be done prior to generating the completion interrupt). */
3137	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3138	if (fSw)
3139	{
3140	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3141	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3142	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3143	AssertRC(rc);
3144	}
3145
3146	/* Generate invalidation event interrupt. */
3147	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3148	if (fIf)
3149	{
3150	DMAR_LOCK(pDevIns, pThisR3);
3151	dmarR3InvEventRaiseInterrupt(pDevIns);
3152	DMAR_UNLOCK(pDevIns, pThisR3);
3153	}
3154
3155	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3156	break;
3157	}
3158
3159	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3160	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3161	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3162	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3163	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3164	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3165	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3166	default:
3167	{
3168	/* Stop processing further requests. */
3169	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3170	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3171	}
3172	}
3173	}
3174	#undef DMAR_IQE_FAULT_RECORD_RET
3175	}
3176
3177
3178	/**
3179	* The invalidation-queue thread.
3180	*
3181	* @returns VBox status code.
3182	* @param pDevIns The IOMMU device instance.
3183	* @param pThread The command thread.
3184	*/
3185	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3186	{
3187	NOREF(pThread);
3188	LogFlowFunc(("\n"));
3189
3190	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3191	return VINF_SUCCESS;
3192
3193	/*
3194	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3195	* This prevents trashing the heap as well as deal with out-of-memory situations
3196	* up-front while starting the VM. It also simplifies the code from having to
3197	* dynamically grow/shrink the allocation based on how software sizes the queue.
3198	* Guests normally don't alter the queue size all the time, but that's not an
3199	* assumption we can make.
3200	*/
3201	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3202	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3203	void *pvRequests = RTMemAllocZ(cbMaxQs);
3204	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3205
3206	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3207	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3208
3209	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3210	{
3211	/*
3212	* Sleep until we are woken up.
3213	*/
3214	{
3215	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3216	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3217	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3218	break;
3219	}
3220
3221	DMAR_LOCK(pDevIns, pThisR3);
3222	if (dmarInvQueueCanProcessRequests(pThis))
3223	{
3224	uint32_t offQueueHead;
3225	uint32_t offQueueTail;
3226	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3227	if (!fIsEmpty)
3228	{
3229	/*
3230	* Get the current queue size, descriptor width, queue base address and the
3231	* table translation mode while the lock is still held.
3232	*/
3233	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3234	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3235	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3236	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3237	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3238	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3239
3240	/* Paranoia. */
3241	Assert(cbQueue <= cbMaxQs);
3242	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3243	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3244	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
3245	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
3246	Assert(offQueueHead < cbQueue);
3247
3248	/*
3249	* A table translation mode of "reserved" isn't valid for any descriptor type.
3250	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3251	* but if ESRTPS is support, we will perform a global invalidation when software
3252	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3253	* So caching TTM while reading all descriptors should not be a problem.
3254	*
3255	* Also, validate the queue tail offset as it's mutable by software.
3256	*/
3257	if ( fTtm != VTD_TTM_RSVD
3258	&& offQueueTail < cbQueue)
3259	{
3260	/* Don't hold the lock while reading (a potentially large amount of) requests */
3261	DMAR_UNLOCK(pDevIns, pThisR3);
3262
3263	int rc;
3264	uint32_t cbRequests;
3265	if (offQueueTail > offQueueHead)
3266	{
3267	/* The requests have not wrapped around, read them in one go. */
3268	cbRequests = offQueueTail - offQueueHead;
3269	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3270	}
3271	else
3272	{
3273	/* The requests have wrapped around, read forward and wrapped-around. */
3274	uint32_t const cbForward = cbQueue - offQueueHead;
3275	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3276
3277	uint32_t const cbWrapped = offQueueTail;
3278	if ( RT_SUCCESS(rc)
3279	&& cbWrapped > 0)
3280	{
3281	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3282	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3283	}
3284	cbRequests = cbForward + cbWrapped;
3285	}
3286
3287	/* Re-acquire the lock since we need to update device state. */
3288	DMAR_LOCK(pDevIns, pThisR3);
3289
3290	if (RT_SUCCESS(rc))
3291	{
3292	/* Indicate to software we've fetched all requests. */
3293	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3294
3295	/* Don't hold the lock while processing requests. */
3296	DMAR_UNLOCK(pDevIns, pThisR3);
3297
3298	/* Process all requests. */
3299	Assert(cbRequests <= cbQueue);
3300	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3301
3302	/*
3303	* We've processed all requests and the lock shouldn't be held at this point.
3304	* Using 'continue' here allows us to skip re-acquiring the lock just to release
3305	* it again before going back to the thread loop. It's a bit ugly but it certainly
3306	* helps with performance.
3307	*/
3308	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3309	continue;
3310	}
3311	else
3312	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3313	}
3314	else
3315	{
3316	if (fTtm == VTD_TTM_RSVD)
3317	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3318	else
3319	{
3320	Assert(offQueueTail >= cbQueue);
3321	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3322	}
3323	}
3324	}
3325	}
3326	DMAR_UNLOCK(pDevIns, pThisR3);
3327	}
3328
3329	RTMemFree(pvRequests);
3330	pvRequests = NULL;
3331
3332	LogFlowFunc(("Invalidation-queue thread terminating\n"));
3333	return VINF_SUCCESS;
3334	}
3335
3336
3337	/**
3338	* Wakes up the invalidation-queue thread so it can respond to a state
3339	* change.
3340	*
3341	* @returns VBox status code.
3342	* @param pDevIns The IOMMU device instance.
3343	* @param pThread The invalidation-queue thread.
3344	*
3345	* @thread EMT.
3346	*/
3347	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3348	{
3349	RT_NOREF(pThread);
3350	LogFlowFunc(("\n"));
3351	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3352	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3353	}
3354
3355
3356	/**
3357	* @callback_method_impl{FNDBGFHANDLERDEV}
3358	*/
3359	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3360	{
3361	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3362	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3363	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3364
3365	/*
3366	* We lock the device to get a consistent register state as it is
3367	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3368	* ones we care about here) into temporaries and release the lock ASAP.
3369	*
3370	* Order of register being read and outputted is in accordance with the
3371	* spec. for no particular reason.
3372	* See Intel VT-d spec. 10.4 "Register Descriptions".
3373	*/
3374	DMAR_LOCK(pDevIns, pThisR3);
3375
3376	DMARDIAG const enmDiag = pThis->enmDiag;
3377	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3378	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3379	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3380	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3381	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3382	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3383	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3384	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3385	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3386	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3387	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3388	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3389	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3390	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3391	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3392	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3393	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3394	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3395	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3396	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3397	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3398	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3399	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3400	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3401	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3402	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3403	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3404	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3405	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3406	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3407	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3408	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3409	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3410	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3411	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3412	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3413	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3414	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3415
3416	DMAR_UNLOCK(pDevIns, pThisR3);
3417
3418	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3419	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3420	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3421
3422	/*
3423	* Non-verbose output.
3424	*/
3425	if (!fVerbose)
3426	{
3427	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3428	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3429	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3430	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3431	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3432	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3433	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3434	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3435	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3436	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3437	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3438	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3439	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3440	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3441	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3442	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3443	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3444	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3445	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3446	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3447	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3448	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3449	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3450	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3451	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3452	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3453	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3454	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3455	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3456	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3457	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3458	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3459	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3460	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3461	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3462	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3463	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3464	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3465	pHlp->pfnPrintf(pHlp, "\n");
3466	return;
3467	}
3468
3469	/*
3470	* Verbose output.
3471	*/
3472	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3473	{
3474	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3475	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3476	}
3477	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3478	{
3479	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3480	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3481	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3482	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3483	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3484	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3485	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3486	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3487	pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3488	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3489	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3490	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3491	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3492	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3493	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3494	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3495	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3496	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3497	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3498	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3499	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3500	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3501	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3502	}
3503	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3504	{
3505	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3506	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3507	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3508	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3509	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3510	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3511	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3512	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3513	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3514	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3515	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3516	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3517	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3518	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3519	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3520	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3521	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3522	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3523	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3524	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3525	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3526	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3527	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3528	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3529	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3530	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3531	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3532	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3533	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3534	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3535	}
3536	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3537	{
3538	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3539	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3540	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3541	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3542	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3543	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3544	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3545	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3546	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3547	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3548	}
3549	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3550	{
3551	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3552	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3553	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3554	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3555	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3556	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3557	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3558	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3559	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3560	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3561	}
3562	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3563	{
3564	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3565	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3566	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3567	}
3568	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3569	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3570	{
3571	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3572	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3573	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3574	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3575	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3576	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3577	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3578	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3579	}
3580	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3581	{
3582	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3583	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3584	}
3585	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3586	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3587	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3588	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3589	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3590	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3591	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3592	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3593	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3594	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3595	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3596	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3597	{
3598	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3599	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3600	uint8_t const cQueuePages = 1 << fQs;
3601	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3602	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3603	}
3604	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3605	{
3606	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3607	}
3608	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3609	{
3610	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3611	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3612	}
3613	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3614	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3615	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3616	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3617	{
3618	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3619	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3620	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3621	}
3622	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3623	{
3624	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3625	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3626	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3627	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3628	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3629	}
3630	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3631	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3632	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3633	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3634	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3635	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3636	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3637	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3638	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3639	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3640	pHlp->pfnPrintf(pHlp, "\n");
3641	}
3642
3643
3644	/**
3645	* Initializes all registers in the DMAR unit.
3646	*
3647	* @param pDevIns The IOMMU device instance.
3648	*/
3649	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3650	{
3651	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3652
3653	/*
3654	* Wipe all registers (required on reset).
3655	*/
3656	RT_ZERO(pThis->abRegs0);
3657	RT_ZERO(pThis->abRegs1);
3658
3659	/*
3660	* Initialize registers not mutable by software prior to initializing other registers.
3661	*/
3662	/* VER_REG */
3663	{
3664	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3665	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3666	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3667	}
3668
3669	uint8_t const fFlts = 1; /* First-level translation support. */
3670	uint8_t const fSlts = 1; /* Second-level translation support. */
3671	uint8_t const fPt = 1; /* Pass-Through support. */
3672	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3673	uint8_t const fNest = 0; /* Nested translation support. */
3674
3675	/* CAP_REG */
3676	{
3677	uint8_t cGstPhysAddrBits;
3678	uint8_t cGstLinearAddrBits;
3679	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3680
3681	uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3682	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3683	uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3684	uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3685	uint8_t const fSllps = fSl2mp \| (fSl2gp << 1); /* Second-level large page support. */
3686	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3687	: X86_PAGE_2M_SHIFT)
3688	- X86_PAGE_4K_SHIFT;
3689	uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3690	uint8_t const fPsi = 1; /* Page selective invalidation. */
3691	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3692	uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3693	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3694	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3695	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3696	AssertCompile(DMAR_ND <= 6);
3697
3698	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3699	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3700	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3701	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3702	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3703	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3704	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3705	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3706	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3707	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3708	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3709	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3710	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3711	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3712	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3713	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3714	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3715	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3716	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3717	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3718	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3719	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3720
3721	pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3722	pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3723	pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3724	}
3725
3726	/* ECAP_REG */
3727	{
3728	uint8_t const fQi = 1; /* Queued-invalidations. */
3729	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3730	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3731	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3732	uint8_t const fEim = 1; /* Extended interrupt mode.*/
3733	uint8_t const fAdms = 1; /* Abort DMA mode support. */
3734	uint8_t const fErs = 0; /* Execute Request (not supported). */
3735
3736	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3737	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3738	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3739	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3740	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3741	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3742	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3743	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3744	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3745	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3746	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3747	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3748	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3749	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3750	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3751	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3752	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3753	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3754	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3755	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3756	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3757	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3758	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3759	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3760	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3761	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3762	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3763	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3764	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3765	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3766
3767	pThis->fPermValidMask = DMAR_PERM_READ \| DMAR_PERM_WRITE;
3768	if (fErs)
3769	pThis->fPermValidMask = DMAR_PERM_EXE;
3770	}
3771
3772	/*
3773	* Initialize registers mutable by software.
3774	*/
3775	/* FECTL_REG */
3776	{
3777	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3778	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3779	}
3780
3781	/* ICETL_REG */
3782	{
3783	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3784	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3785	}
3786
3787	#ifdef VBOX_STRICT
3788	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3789	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3790	#endif
3791	}
3792
3793
3794	/**
3795	* @interface_method_impl{PDMDEVREG,pfnReset}
3796	*/
3797	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
3798	{
3799	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3800	LogFlowFunc(("\n"));
3801
3802	DMAR_LOCK(pDevIns, pThisR3);
3803	dmarR3RegsInit(pDevIns);
3804	DMAR_UNLOCK(pDevIns, pThisR3);
3805	}
3806
3807
3808	/**
3809	* @interface_method_impl{PDMDEVREG,pfnDestruct}
3810	*/
3811	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
3812	{
3813	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3814	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3815	LogFlowFunc(("\n"));
3816
3817	DMAR_LOCK(pDevIns, pThisR3);
3818
3819	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
3820	{
3821	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
3822	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
3823	}
3824
3825	DMAR_UNLOCK(pDevIns, pThisR3);
3826	return VINF_SUCCESS;
3827	}
3828
3829
3830	/**
3831	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3832	*/
3833	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3834	{
3835	RT_NOREF(pCfg);
3836
3837	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3838	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
3839	pThisR3->pDevInsR3 = pDevIns;
3840
3841	LogFlowFunc(("iInstance=%d\n", iInstance));
3842	NOREF(iInstance);
3843
3844	/*
3845	* Register the IOMMU with PDM.
3846	*/
3847	PDMIOMMUREGR3 IommuReg;
3848	RT_ZERO(IommuReg);
3849	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3850	IommuReg.pfnMemAccess = iommuIntelMemAccess;
3851	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3852	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3853	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3854	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3855	if (RT_FAILURE(rc))
3856	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3857	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3858	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3859	N_("IOMMU helper version mismatch; got %#x expected %#x"),
3860	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3861	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3862	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3863	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3864	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3865	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
3866	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
3867	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
3868	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
3869
3870	/*
3871	* Use PDM's critical section (via helpers) for the IOMMU device.
3872	*/
3873	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3874	AssertRCReturn(rc, rc);
3875
3876	/*
3877	* Initialize PCI configuration registers.
3878	*/
3879	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3880	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3881
3882	/* Header. */
3883	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3884	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3885	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3886	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
3887	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
3888	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
3889	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3890	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3891
3892	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
3893	PDMPciDevSetStatus(pPciDev, 0);
3894	PDMPciDevSetCapabilityList(pPciDev, 0);
3895
3896	/** @todo VTBAR at 0x180? */
3897
3898	/*
3899	* Register the PCI function with PDM.
3900	*/
3901	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3902	AssertLogRelRCReturn(rc, rc);
3903
3904	/** @todo Register MSI but what's the MSI capability offset? */
3905	#if 0
3906	/*
3907	* Register MSI support for the PCI device.
3908	* This must be done -after- registering it as a PCI device!
3909	*/
3910	#endif
3911
3912	/*
3913	* Register MMIO region.
3914	*/
3915	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
3916	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
3917	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
3918	&pThis->hMmio);
3919	AssertLogRelRCReturn(rc, rc);
3920
3921	/*
3922	* Register debugger info items.
3923	*/
3924	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
3925	AssertLogRelRCReturn(rc, rc);
3926
3927	#ifdef VBOX_WITH_STATISTICS
3928	/*
3929	* Statistics.
3930	*/
3931	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
3932	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
3933
3934	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
3935	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
3936
3937	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
3938	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
3939	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
3940	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
3941
3942	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
3943	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
3944
3945	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
3946	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
3947
3948	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
3949	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
3950
3951	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
3952	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
3953
3954	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
3955	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
3956	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
3957	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
3958	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
3959	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
3960	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
3961	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
3962	#endif
3963
3964	/*
3965	* Initialize registers.
3966	*/
3967	dmarR3RegsInit(pDevIns);
3968
3969	/*
3970	* Create invalidation-queue thread and semaphore.
3971	*/
3972	char szInvQueueThread[32];
3973	RT_ZERO(szInvQueueThread);
3974	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
3975	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
3976	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
3977	AssertLogRelRCReturn(rc, rc);
3978
3979	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
3980	AssertLogRelRCReturn(rc, rc);
3981
3982	/*
3983	* Log some of the features exposed to software.
3984	*/
3985	uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
3986	uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
3987	uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
3988	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
3989	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
3990	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
3991	LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
3992	DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
3993	LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
3994	DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
3995	pThis->fMgawInvMask, offFrcd, offIva));
3996	return VINF_SUCCESS;
3997	}
3998
3999	#else
4000
4001	/**
4002	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4003	*/
4004	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4005	{
4006	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4007	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4008	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4009	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4010
4011	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
4012	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4013	AssertRCReturn(rc, rc);
4014
4015	/* Set up the MMIO RZ handlers. */
4016	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4017	AssertRCReturn(rc, rc);
4018
4019	/* Set up the IOMMU RZ callbacks. */
4020	PDMIOMMUREGCC IommuReg;
4021	RT_ZERO(IommuReg);
4022	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4023	IommuReg.idxIommu = pThis->idxIommu;
4024	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4025	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4026	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4027	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4028
4029	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4030	AssertRCReturn(rc, rc);
4031	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4032	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4033	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4034	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4035	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4036	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4037	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4038
4039	return VINF_SUCCESS;
4040	}
4041
4042	#endif
4043
4044
4045	/**
4046	* The device registration structure.
4047	*/
4048	PDMDEVREG const g_DeviceIommuIntel =
4049	{
4050	/* .u32Version = */ PDM_DEVREG_VERSION,
4051	/* .uReserved0 = */ 0,
4052	/* .szName = */ "iommu-intel",
4053	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4054	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4055	/* .cMaxInstances = */ 1,
4056	/* .uSharedVersion = */ 42,
4057	/* .cbInstanceShared = */ sizeof(DMAR),
4058	/* .cbInstanceCC = */ sizeof(DMARCC),
4059	/* .cbInstanceRC = */ sizeof(DMARRC),
4060	/* .cMaxPciDevices = */ 1,
4061	/* .cMaxMsixVectors = */ 0,
4062	/* .pszDescription = */ "IOMMU (Intel)",
4063	#if defined(IN_RING3)
4064	/* .pszRCMod = */ "VBoxDDRC.rc",
4065	/* .pszR0Mod = */ "VBoxDDR0.r0",
4066	/* .pfnConstruct = */ iommuIntelR3Construct,
4067	/* .pfnDestruct = */ iommuIntelR3Destruct,
4068	/* .pfnRelocate = */ NULL,
4069	/* .pfnMemSetup = */ NULL,
4070	/* .pfnPowerOn = */ NULL,
4071	/* .pfnReset = */ iommuIntelR3Reset,
4072	/* .pfnSuspend = */ NULL,
4073	/* .pfnResume = */ NULL,
4074	/* .pfnAttach = */ NULL,
4075	/* .pfnDetach = */ NULL,
4076	/* .pfnQueryInterface = */ NULL,
4077	/* .pfnInitComplete = */ NULL,
4078	/* .pfnPowerOff = */ NULL,
4079	/* .pfnSoftReset = */ NULL,
4080	/* .pfnReserved0 = */ NULL,
4081	/* .pfnReserved1 = */ NULL,
4082	/* .pfnReserved2 = */ NULL,
4083	/* .pfnReserved3 = */ NULL,
4084	/* .pfnReserved4 = */ NULL,
4085	/* .pfnReserved5 = */ NULL,
4086	/* .pfnReserved6 = */ NULL,
4087	/* .pfnReserved7 = */ NULL,
4088	#elif defined(IN_RING0)
4089	/* .pfnEarlyConstruct = */ NULL,
4090	/* .pfnConstruct = */ iommuIntelRZConstruct,
4091	/* .pfnDestruct = */ NULL,
4092	/* .pfnFinalDestruct = */ NULL,
4093	/* .pfnRequest = */ NULL,
4094	/* .pfnReserved0 = */ NULL,
4095	/* .pfnReserved1 = */ NULL,
4096	/* .pfnReserved2 = */ NULL,
4097	/* .pfnReserved3 = */ NULL,
4098	/* .pfnReserved4 = */ NULL,
4099	/* .pfnReserved5 = */ NULL,
4100	/* .pfnReserved6 = */ NULL,
4101	/* .pfnReserved7 = */ NULL,
4102	#elif defined(IN_RC)
4103	/* .pfnConstruct = */ iommuIntelRZConstruct,
4104	/* .pfnReserved0 = */ NULL,
4105	/* .pfnReserved1 = */ NULL,
4106	/* .pfnReserved2 = */ NULL,
4107	/* .pfnReserved3 = */ NULL,
4108	/* .pfnReserved4 = */ NULL,
4109	/* .pfnReserved5 = */ NULL,
4110	/* .pfnReserved6 = */ NULL,
4111	/* .pfnReserved7 = */ NULL,
4112	#else
4113	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4114	#endif
4115	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4116	};
4117
4118	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4119

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89499

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