VirtualBox

source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89532

Last change on this file since 89532 was 89524, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 Address translation and interrupt remapping fault handling cleanup.
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1/* $Id: DevIommuIntel.cpp 89524 2021-06-05 07:34:32Z vboxsync $ */
2/** @file
3 * IOMMU - Input/Output Memory Management Unit - Intel implementation.
4 */
5
6/*
7 * Copyright (C) 2021 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23#include "VBoxDD.h"
24#include "DevIommuIntel.h"
25
26#include <iprt/mem.h>
27#include <iprt/string.h>
28
29
30/*********************************************************************************************************************************
31* Defined Constants And Macros *
32*********************************************************************************************************************************/
33/** Gets the low uint32_t of a uint64_t or something equivalent.
34 *
35 * This is suitable for casting constants outside code (since RT_LO_U32 can't be
36 * used as it asserts for correctness when compiling on certain compilers). */
37#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39/** Gets the high uint32_t of a uint64_t or something equivalent.
40 *
41 * This is suitable for casting constants outside code (since RT_HI_U32 can't be
42 * used as it asserts for correctness when compiling on certain compilers). */
43#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45/** Asserts MMIO access' offset and size are valid or returns appropriate error
46 * code suitable for returning from MMIO access handlers. */
47#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48 do { \
49 AssertReturn((a_cb) == 4 || (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50 AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51 } while (0)
52
53/** Checks if the MMIO offset is valid. */
54#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55 || (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59 do { \
60 if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61 { /* likely */ } \
62 else \
63 return (a_rcBusy); \
64 } while (0)
65
66/** Acquires the DMAR lock (not expected to fail). */
67#ifdef IN_RING3
68# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69#else
70# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71 do { \
72 int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73 AssertRC(rcLock); \
74 } while (0)
75#endif
76
77/** Release the DMAR lock. */
78#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80/** Asserts that the calling thread owns the DMAR lock. */
81#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82 do { \
83 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84 RT_NOREF1(a_pThisCC); \
85 } while (0)
86
87/** Asserts that the calling thread does not own the DMAR lock. */
88#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89 do { \
90 Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91 RT_NOREF1(a_pThisCC); \
92 } while (0)
93
94/** The number of fault recording registers our implementation supports.
95 * Normal guest operation shouldn't trigger faults anyway, so we only support the
96 * minimum number of registers (which is 1).
97 *
98 * See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101/** Offset of first register in group 0. */
102#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
103/** Offset of last register in group 0 (inclusive). */
104#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
105/** Last valid offset in group 0 (exclusive). */
106#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
107/** Size of the group 0 (in bytes). */
108#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
109/**< Implementation-specific MMIO offset of IVA_REG. */
110#define DMAR_MMIO_OFF_IVA_REG 0xe50
111/**< Implementation-specific MMIO offset of IOTLB_REG. */
112#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
113/**< Implementation-specific MMIO offset of FRCD_LO_REG. */
114#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
115/**< Implementation-specific MMIO offset of FRCD_HI_REG. */
116#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
117AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
118
119/** Offset of first register in group 1. */
120#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
121/** Offset of last register in group 1 (inclusive). */
122#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
123/** Last valid offset in group 1 (exclusive). */
124#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
125/** Size of the group 1 (in bytes). */
126#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
127
128/** DMAR implementation's major version number (exposed to software).
129 * We report 6 as the major version since we support queued-invalidations as
130 * software may make assumptions based on that.
131 *
132 * See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
133#define DMAR_VER_MAJOR 6
134/** DMAR implementation's minor version number (exposed to software). */
135#define DMAR_VER_MINOR 0
136
137/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
138 * 7=Reserved). */
139#define DMAR_ND 6
140
141/** @name DMAR_PERM_XXX: DMA request permissions.
142 * The order of R, W, X bits is important as it corresponds to those bits in
143 * page-table entries.
144 *
145 * @{ */
146/** DMA request permission: Read. */
147#define DMAR_PERM_READ RT_BIT(0)
148/** DMA request permission: Write. */
149#define DMAR_PERM_WRITE RT_BIT(1)
150/** DMA request permission: Execute (ER). */
151#define DMAR_PERM_EXE RT_BIT(2)
152/** DMA request permission: Supervisor privilege (PR). */
153#define DMAR_PERM_PRIV RT_BIT(3)
154/** DMA request permissions: All. */
155#define DMAR_PERM_ALL (DMAR_PERM_READ | DMAR_PERM_WRITE | DMAR_PERM_EXE | DMAR_PERM_PRIV)
156/** @} */
157
158/** Release log prefix string. */
159#define DMAR_LOG_PFX "Intel-IOMMU"
160/** The current saved state version. */
161#define DMAR_SAVED_STATE_VERSION 1
162
163
164/*********************************************************************************************************************************
165* Structures and Typedefs *
166*********************************************************************************************************************************/
167/**
168 * DMAR error diagnostics.
169 * Sorted alphabetically so it's easier to add and locate items, no other reason.
170 *
171 * @note Members of this enum are used as array indices, so no gaps in enum
172 * values are not allowed. Update g_apszDmarDiagDesc when you modify
173 * fields in this enum.
174 */
175typedef enum
176{
177 /* No error, this must be zero! */
178 kDmarDiag_None = 0,
179
180 /* Address Translation Faults. */
181 kDmarDiag_At_Lm_CtxEntry_Not_Present,
182 kDmarDiag_At_Lm_CtxEntry_Read_Failed,
183 kDmarDiag_At_Lm_CtxEntry_Rsvd,
184 kDmarDiag_At_Lm_Pt_At_Block,
185 kDmarDiag_At_Lm_Pt_Aw_Invalid,
186 kDmarDiag_At_Lm_RootEntry_Not_Present,
187 kDmarDiag_At_Lm_RootEntry_Read_Failed,
188 kDmarDiag_At_Lm_RootEntry_Rsvd,
189 kDmarDiag_At_Lm_Slpptr_Read_Failed,
190 kDmarDiag_At_Lm_Tt_Invalid,
191 kDmarDiag_At_Lm_Ut_At_Block,
192 kDmarDiag_At_Lm_Ut_Aw_Invalid,
193 kDmarDiag_At_Rta_Adms_Not_Supported,
194 kDmarDiag_At_Rta_Rsvd,
195 kDmarDiag_At_Rta_Smts_Not_Supported,
196 kDmarDiag_At_Xm_AddrIn_Invalid,
197 kDmarDiag_At_Xm_AddrOut_Invalid,
198 kDmarDiag_At_Xm_Perm_Denied,
199 kDmarDiag_At_Xm_Pte_Rsvd,
200 kDmarDiag_At_Xm_Pte_Sllps_Invalid,
201 kDmarDiag_At_Xm_Read_Pte_Failed,
202
203 /* CCMD_REG faults. */
204 kDmarDiag_CcmdReg_Not_Supported,
205 kDmarDiag_CcmdReg_Qi_Enabled,
206 kDmarDiag_CcmdReg_Ttm_Invalid,
207
208 /* IQA_REG faults. */
209 kDmarDiag_IqaReg_Dsc_Fetch_Error,
210 kDmarDiag_IqaReg_Dw_128_Invalid,
211 kDmarDiag_IqaReg_Dw_256_Invalid,
212
213 /* Invalidation Queue Error Info. */
214 kDmarDiag_Iqei_Dsc_Type_Invalid,
215 kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
216 kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
217 kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
218 kDmarDiag_Iqei_Ttm_Rsvd,
219
220 /* IQT_REG faults. */
221 kDmarDiag_IqtReg_Qt_Invalid,
222 kDmarDiag_IqtReg_Qt_Not_Aligned,
223
224 /* Interrupt Remapping Faults. */
225 kDmarDiag_Ir_Cfi_Blocked,
226 kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
227 kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
228 kDmarDiag_Ir_Rfi_Irte_Not_Present,
229 kDmarDiag_Ir_Rfi_Irte_Read_Failed,
230 kDmarDiag_Ir_Rfi_Irte_Rsvd,
231 kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
232 kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
233 kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
234 kDmarDiag_Ir_Rfi_Rsvd,
235
236 /* Member for determining array index limit. */
237 kDmarDiag_End,
238
239 /* Usual 32-bit type size hack. */
240 kDmarDiag_32Bit_Hack = 0x7fffffff
241} DMARDIAG;
242AssertCompileSize(DMARDIAG, 4);
243
244/** DMAR diagnostic enum description expansion.
245 * The below construct ensures typos in the input to this macro are caught
246 * during compile time. */
247#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
248
249/** DMAR diagnostics description for members in DMARDIAG. */
250static const char *const g_apszDmarDiagDesc[] =
251{
252 DMARDIAG_DESC(None ),
253
254 /* Address Translation Faults. */
255 DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
256 DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
257 DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
258 DMARDIAG_DESC(At_Lm_Pt_At_Block ),
259 DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
260 DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
261 DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
262 DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
263 DMARDIAG_DESC(At_Lm_Slpptr_Read_Failed ),
264 DMARDIAG_DESC(At_Lm_Tt_Invalid ),
265 DMARDIAG_DESC(At_Lm_Ut_At_Block ),
266 DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
267 DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
268 DMARDIAG_DESC(At_Rta_Rsvd ),
269 DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
270 DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
271 DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
272 DMARDIAG_DESC(At_Xm_Perm_Denied ),
273 DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
274 DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
275 DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
276
277 /* CCMD_REG faults. */
278 DMARDIAG_DESC(CcmdReg_Not_Supported ),
279 DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
280 DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
281
282 /* IQA_REG faults. */
283 DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
284 DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
285 DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
286
287 /* Invalidation Queue Error Info. */
288 DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
289 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
290 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
291 DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
292 DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
293
294 /* IQT_REG faults. */
295 DMARDIAG_DESC(IqtReg_Qt_Invalid ),
296 DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
297
298 /* Interrupt remapping faults. */
299 DMARDIAG_DESC(Ir_Cfi_Blocked ),
300 DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
301 DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
302 DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
303 DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
304 DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
305 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
306 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
307 DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
308 DMARDIAG_DESC(Ir_Rfi_Rsvd ),
309 /* kDmarDiag_End */
310};
311AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
312#undef DMARDIAG_DESC
313
314/**
315 * The shared DMAR device state.
316 */
317typedef struct DMAR
318{
319 /** IOMMU device index. */
320 uint32_t idxIommu;
321 /** DMAR magic. */
322 uint32_t u32Magic;
323
324 /** Registers (group 0). */
325 uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
326 /** Registers (group 1). */
327 uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
328
329 /** @name Lazily activated registers.
330 * These are the active values for lazily activated registers. Software is free to
331 * modify the actual register values while remapping/translation is enabled but they
332 * take effect only when explicitly signaled by software, hence we need to hold the
333 * active values separately.
334 * @{ */
335 /** Currently active IRTA_REG. */
336 uint64_t uIrtaReg;
337 /** Currently active RTADDR_REG. */
338 uint64_t uRtaddrReg;
339 /** @} */
340
341 /** @name Register copies for a tiny bit faster and more convenient access.
342 * @{ */
343 /** Copy of VER_REG. */
344 uint8_t uVerReg;
345 /** Alignment. */
346 uint8_t abPadding[7];
347 /** Copy of CAP_REG. */
348 uint64_t fCapReg;
349 /** Copy of ECAP_REG. */
350 uint64_t fExtCapReg;
351 /** @} */
352
353 /** Host-address width (HAW) base address mask. */
354 uint64_t fHawBaseMask;
355 /** Maximum guest-address width (MGAW) invalid address mask. */
356 uint64_t fMgawInvMask;
357 /** Maximum supported paging level (3, 4 or 5). */
358 uint8_t cMaxPagingLevel;
359 /** DMA request valid permissions mask. */
360 uint8_t fPermValidMask;
361
362 /** The event semaphore the invalidation-queue thread waits on. */
363 SUPSEMEVENT hEvtInvQueue;
364 /** Padding. */
365 uint32_t uPadding0;
366 /** Error diagnostic. */
367 DMARDIAG enmDiag;
368 /** The MMIO handle. */
369 IOMMMIOHANDLE hMmio;
370
371#ifdef VBOX_WITH_STATISTICS
372 STAMCOUNTER StatMmioReadR3; /**< Number of MMIO reads in R3. */
373 STAMCOUNTER StatMmioReadRZ; /**< Number of MMIO reads in RZ. */
374 STAMCOUNTER StatMmioWriteR3; /**< Number of MMIO writes in R3. */
375 STAMCOUNTER StatMmioWriteRZ; /**< Number of MMIO writes in RZ. */
376
377 STAMCOUNTER StatMsiRemapCfiR3; /**< Number of compatibility-format interrupts remap requests in R3. */
378 STAMCOUNTER StatMsiRemapCfiRZ; /**< Number of compatibility-format interrupts remap requests in RZ. */
379 STAMCOUNTER StatMsiRemapRfiR3; /**< Number of remappable-format interrupts remap requests in R3. */
380 STAMCOUNTER StatMsiRemapRfiRZ; /**< Number of remappable-format interrupts remap requests in RZ. */
381
382 STAMCOUNTER StatMemReadR3; /**< Number of memory read translation requests in R3. */
383 STAMCOUNTER StatMemReadRZ; /**< Number of memory read translation requests in RZ. */
384 STAMCOUNTER StatMemWriteR3; /**< Number of memory write translation requests in R3. */
385 STAMCOUNTER StatMemWriteRZ; /**< Number of memory write translation requests in RZ. */
386
387 STAMCOUNTER StatMemBulkReadR3; /**< Number of memory read bulk translation requests in R3. */
388 STAMCOUNTER StatMemBulkReadRZ; /**< Number of memory read bulk translation requests in RZ. */
389 STAMCOUNTER StatMemBulkWriteR3; /**< Number of memory write bulk translation requests in R3. */
390 STAMCOUNTER StatMemBulkWriteRZ; /**< Number of memory write bulk translation requests in RZ. */
391
392 STAMCOUNTER StatCcInvDsc; /**< Number of Context-cache descriptors processed. */
393 STAMCOUNTER StatIotlbInvDsc; /**< Number of IOTLB descriptors processed. */
394 STAMCOUNTER StatDevtlbInvDsc; /**< Number of Device-TLB descriptors processed. */
395 STAMCOUNTER StatIecInvDsc; /**< Number of Interrupt-Entry cache descriptors processed. */
396 STAMCOUNTER StatInvWaitDsc; /**< Number of Invalidation wait descriptors processed. */
397 STAMCOUNTER StatPasidIotlbInvDsc; /**< Number of PASID-based IOTLB descriptors processed. */
398 STAMCOUNTER StatPasidCacheInvDsc; /**< Number of PASID-cache descriptors processed. */
399 STAMCOUNTER StatPasidDevtlbInvDsc; /**< Number of PASID-based device-TLB descriptors processed. */
400#endif
401} DMAR;
402/** Pointer to the DMAR device state. */
403typedef DMAR *PDMAR;
404/** Pointer to the const DMAR device state. */
405typedef DMAR const *PCDMAR;
406AssertCompileMemberAlignment(DMAR, abRegs0, 8);
407AssertCompileMemberAlignment(DMAR, abRegs1, 8);
408
409/**
410 * The ring-3 DMAR device state.
411 */
412typedef struct DMARR3
413{
414 /** Device instance. */
415 PPDMDEVINSR3 pDevInsR3;
416 /** The IOMMU helper. */
417 R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
418 /** The invalidation-queue thread. */
419 R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
420} DMARR3;
421/** Pointer to the ring-3 DMAR device state. */
422typedef DMARR3 *PDMARR3;
423/** Pointer to the const ring-3 DMAR device state. */
424typedef DMARR3 const *PCDMARR3;
425
426/**
427 * The ring-0 DMAR device state.
428 */
429typedef struct DMARR0
430{
431 /** Device instance. */
432 PPDMDEVINSR0 pDevInsR0;
433 /** The IOMMU helper. */
434 R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
435} DMARR0;
436/** Pointer to the ring-0 IOMMU device state. */
437typedef DMARR0 *PDMARR0;
438/** Pointer to the const ring-0 IOMMU device state. */
439typedef DMARR0 const *PCDMARR0;
440
441/**
442 * The raw-mode DMAR device state.
443 */
444typedef struct DMARRC
445{
446 /** Device instance. */
447 PPDMDEVINSRC pDevInsRC;
448 /** The IOMMU helper. */
449 RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
450} DMARRC;
451/** Pointer to the raw-mode DMAR device state. */
452typedef DMARRC *PDMARRC;
453/** Pointer to the const raw-mode DMAR device state. */
454typedef DMARRC const *PCIDMARRC;
455
456/** The DMAR device state for the current context. */
457typedef CTX_SUFF(DMAR) DMARCC;
458/** Pointer to the DMAR device state for the current context. */
459typedef CTX_SUFF(PDMAR) PDMARCC;
460/** Pointer to the const DMAR device state for the current context. */
461typedef CTX_SUFF(PDMAR) const PCDMARCC;
462
463/**
464 * DMAR originated events that generate interrupts.
465 */
466typedef enum DMAREVENTTYPE
467{
468 /** Invalidation completion event. */
469 DMAREVENTTYPE_INV_COMPLETE = 0,
470 /** Fault event. */
471 DMAREVENTTYPE_FAULT
472} DMAREVENTTYPE;
473
474/**
475 * I/O Page.
476 */
477typedef struct DMARIOPAGE
478{
479 /** The base DMA address of a page. */
480 RTGCPHYS GCPhysBase;
481 /** The page shift. */
482 uint8_t cShift;
483 /** The permissions of this page (DMAR_PERM_XXX). */
484 uint8_t fPerm;
485} DMARIOPAGE;
486/** Pointer to an I/O page. */
487typedef DMARIOPAGE *PDMARIOPAGE;
488/** Pointer to a const I/O address range. */
489typedef DMARIOPAGE const *PCDMARIOPAGE;
490
491/**
492 * I/O Address Range.
493 */
494typedef struct DMARIOADDRRANGE
495{
496 /** The starting DMA address of this range. */
497 uint64_t uAddr;
498 /** The size of the range (in bytes). */
499 size_t cb;
500 /** The permissions of this range (DMAR_PERM_XXX). */
501 uint8_t fPerm;
502} DMARIOADDRRANGE;
503/** Pointer to an I/O address range. */
504typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
505/** Pointer to a const I/O address range. */
506typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
507
508/**
509 * DMA Memory Request (Input).
510 */
511typedef struct DMARMEMREQIN
512{
513 /** The address range being accessed. */
514 DMARIOADDRRANGE AddrRange;
515 /** The source device ID (bus, device, function). */
516 uint16_t idDevice;
517 /** The PASID if present (can be NIL_PCIPASID). */
518 PCIPASID Pasid;
519 /* The address translation type. */
520 PCIADDRTYPE enmAddrType;
521 /** The request type. */
522 VTDREQTYPE enmReqType;
523} DMARMEMREQIN;
524/** Pointer to a DMA memory request input. */
525typedef DMARMEMREQIN *PDMARMEMREQIN;
526/** Pointer to a const DMA memory input. */
527typedef DMARMEMREQIN const *PCDMARMEMREQIN;
528
529/**
530 * DMA Memory Request (Output).
531 */
532typedef struct DMARMEMREQOUT
533{
534 /** The address range of the translated region. */
535 DMARIOADDRRANGE AddrRange;
536 /** The domain ID of the translated region. */
537 uint16_t idDomain;
538} DMARMEMREQOUT;
539/** Pointer to a DMA memory request output. */
540typedef DMARMEMREQOUT *PDMARMEMREQOUT;
541/** Pointer to a const DMA memory request output. */
542typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
543
544/**
545 * DMA Memory Request (Auxiliary Info).
546 * These get updated and used as part of the translation process.
547 */
548typedef struct DMARMEMREQAUX
549{
550 /** The table translation mode (VTD_TTM_XXX). */
551 uint8_t fTtm;
552 /** The fault processing disabled (FPD) bit. */
553 uint8_t fFpd;
554 /** The paging level of the translation. */
555 uint8_t cPagingLevel;
556 uint8_t afPadding[5];
557 /** The first-level page-table pointer. */
558 uint64_t uFlptPtr;
559 /** The second-level page-table pointer. */
560 uint64_t uSlptPtr;
561} DMARMEMREQAUX;
562/** Pointer to a DMA memory request output. */
563typedef DMARMEMREQAUX *PDMARMEMREQAUX;
564/** Pointer to a const DMA memory request output. */
565typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
566
567/**
568 * DMA Memory Request Remapping Information.
569 */
570typedef struct DMARMEMREQREMAP
571{
572 /** The DMA memory request input. */
573 DMARMEMREQIN In;
574 /** DMA memory request auxiliary information. */
575 DMARMEMREQAUX Aux;
576 /** The DMA memory request output. */
577 DMARMEMREQOUT Out;
578} DMARMEMREQREMAP;
579/** Pointer to a DMA remap info. */
580typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
581/** Pointer to a const DMA remap info. */
582typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
583
584typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
585 PDMARIOPAGE pIoPageOut));
586typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
587
588
589/*********************************************************************************************************************************
590* Global Variables *
591*********************************************************************************************************************************/
592/**
593 * Read-write masks for DMAR registers (group 0).
594 */
595static uint32_t const g_au32RwMasks0[] =
596{
597 /* Offset Register Low High */
598 /* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
599 /* 0x004 Reserved */ 0,
600 /* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
601 /* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
602 /* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
603 /* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
604 /* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
605 /* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
606 /* 0x030 Reserved */ 0,
607 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
608 /* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
609 /* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
610 /* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
611 /* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
612 /* 0x048 Reserved */ 0, 0,
613 /* 0x050 Reserved */ 0, 0,
614 /* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
615 /* 0x060 Reserved */ 0,
616 /* 0x064 PMEN_REG */ 0, /* RO as we don't support PLMR and PHMR. */
617 /* 0x068 PLMBASE_REG */ 0, /* RO as we don't support PLMR. */
618 /* 0x06c PLMLIMIT_REG */ 0, /* RO as we don't support PLMR. */
619 /* 0x070 PHMBASE_REG */ 0, 0, /* RO as we don't support PHMR. */
620 /* 0x078 PHMLIMIT_REG */ 0, 0, /* RO as we don't support PHMR. */
621 /* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
622 /* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
623 /* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
624 /* 0x098 Reserved */ 0,
625 /* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
626 /* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
627 /* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
628 /* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
629 /* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
630 /* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
631 /* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
632 /* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
633 /* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
634 /* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
635 /* 0x0d8 Reserved */ 0,
636 /* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
637 /* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
638 /* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
639 /* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
640 /* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
641 /* 0x0f0 Reserved */ 0, 0,
642 /* 0x0f8 Reserved */ 0, 0,
643 /* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
644 /* 0x108 MTRRDEF_REG */ 0, 0, /* RO as we don't support MTS. */
645 /* 0x110 Reserved */ 0, 0,
646 /* 0x118 Reserved */ 0, 0,
647 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0, /* RO as we don't support MTS. */
648 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
649 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
650 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
651 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
652 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
653 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
654 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
655 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
656 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
657 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
658 /* 0x178 Reserved */ 0, 0,
659 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0, /* RO as we don't support MTS. */
660 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
661 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
662 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
663 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
664 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
665 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
666 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
667 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
668 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
669 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
670 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
671 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
672 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
673 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
674 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
675 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
676 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
677 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
678 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
679};
680AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
681
682/**
683 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
684 */
685static uint32_t const g_au32Rw1cMasks0[] =
686{
687 /* Offset Register Low High */
688 /* 0x000 VER_REG */ 0,
689 /* 0x004 Reserved */ 0,
690 /* 0x008 CAP_REG */ 0, 0,
691 /* 0x010 ECAP_REG */ 0, 0,
692 /* 0x018 GCMD_REG */ 0,
693 /* 0x01c GSTS_REG */ 0,
694 /* 0x020 RTADDR_REG */ 0, 0,
695 /* 0x028 CCMD_REG */ 0, 0,
696 /* 0x030 Reserved */ 0,
697 /* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
698 /* 0x038 FECTL_REG */ 0,
699 /* 0x03c FEDATA_REG */ 0,
700 /* 0x040 FEADDR_REG */ 0,
701 /* 0x044 FEUADDR_REG */ 0,
702 /* 0x048 Reserved */ 0, 0,
703 /* 0x050 Reserved */ 0, 0,
704 /* 0x058 AFLOG_REG */ 0, 0,
705 /* 0x060 Reserved */ 0,
706 /* 0x064 PMEN_REG */ 0,
707 /* 0x068 PLMBASE_REG */ 0,
708 /* 0x06c PLMLIMIT_REG */ 0,
709 /* 0x070 PHMBASE_REG */ 0, 0,
710 /* 0x078 PHMLIMIT_REG */ 0, 0,
711 /* 0x080 IQH_REG */ 0, 0,
712 /* 0x088 IQT_REG */ 0, 0,
713 /* 0x090 IQA_REG */ 0, 0,
714 /* 0x098 Reserved */ 0,
715 /* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
716 /* 0x0a0 IECTL_REG */ 0,
717 /* 0x0a4 IEDATA_REG */ 0,
718 /* 0x0a8 IEADDR_REG */ 0,
719 /* 0x0ac IEUADDR_REG */ 0,
720 /* 0x0b0 IQERCD_REG */ 0, 0,
721 /* 0x0b8 IRTA_REG */ 0, 0,
722 /* 0x0c0 PQH_REG */ 0, 0,
723 /* 0x0c8 PQT_REG */ 0, 0,
724 /* 0x0d0 PQA_REG */ 0, 0,
725 /* 0x0d8 Reserved */ 0,
726 /* 0x0dc PRS_REG */ 0,
727 /* 0x0e0 PECTL_REG */ 0,
728 /* 0x0e4 PEDATA_REG */ 0,
729 /* 0x0e8 PEADDR_REG */ 0,
730 /* 0x0ec PEUADDR_REG */ 0,
731 /* 0x0f0 Reserved */ 0, 0,
732 /* 0x0f8 Reserved */ 0, 0,
733 /* 0x100 MTRRCAP_REG */ 0, 0,
734 /* 0x108 MTRRDEF_REG */ 0, 0,
735 /* 0x110 Reserved */ 0, 0,
736 /* 0x118 Reserved */ 0, 0,
737 /* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
738 /* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
739 /* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
740 /* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
741 /* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
742 /* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
743 /* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
744 /* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
745 /* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
746 /* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
747 /* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
748 /* 0x178 Reserved */ 0, 0,
749 /* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
750 /* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
751 /* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
752 /* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
753 /* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
754 /* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
755 /* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
756 /* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
757 /* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
758 /* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
759 /* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
760 /* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
761 /* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
762 /* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
763 /* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
764 /* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
765 /* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
766 /* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
767 /* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
768 /* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
769};
770AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
771
772/**
773 * Read-write masks for DMAR registers (group 1).
774 */
775static uint32_t const g_au32RwMasks1[] =
776{
777 /* Offset Register Low High */
778 /* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
779 /* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
780 /* 0xe10 VCMD_REG */ 0, 0, /* RO: VCS not supported. */
781 /* 0xe18 VCMDRSVD_REG */ 0, 0,
782 /* 0xe20 VCRSP_REG */ 0, 0, /* RO: VCS not supported. */
783 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
784 /* 0xe30 Reserved */ 0, 0,
785 /* 0xe38 Reserved */ 0, 0,
786 /* 0xe40 Reserved */ 0, 0,
787 /* 0xe48 Reserved */ 0, 0,
788 /* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
789 /* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
790 /* 0xe60 Reserved */ 0, 0,
791 /* 0xe68 Reserved */ 0, 0,
792 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
793 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
794};
795AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
796AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
797
798/**
799 * Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
800 */
801static uint32_t const g_au32Rw1cMasks1[] =
802{
803 /* Offset Register Low High */
804 /* 0xe00 VCCAP_REG */ 0, 0,
805 /* 0xe08 VCMD_EO_REG */ 0, 0,
806 /* 0xe10 VCMD_REG */ 0, 0,
807 /* 0xe18 VCMDRSVD_REG */ 0, 0,
808 /* 0xe20 VCRSP_REG */ 0, 0,
809 /* 0xe28 VCRSPRSVD_REG */ 0, 0,
810 /* 0xe30 Reserved */ 0, 0,
811 /* 0xe38 Reserved */ 0, 0,
812 /* 0xe40 Reserved */ 0, 0,
813 /* 0xe48 Reserved */ 0, 0,
814 /* 0xe50 IVA_REG */ 0, 0,
815 /* 0xe58 IOTLB_REG */ 0, 0,
816 /* 0xe60 Reserved */ 0, 0,
817 /* 0xe68 Reserved */ 0, 0,
818 /* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
819 /* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
820};
821AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
822
823/** Array of RW masks for each register group. */
824static uint8_t const *g_apbRwMasks[] = { (uint8_t *)&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
825
826/** Array of RW1C masks for each register group. */
827static uint8_t const *g_apbRw1cMasks[] = { (uint8_t *)&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
828
829/* Masks arrays must be identical in size (even bounds checking code assumes this). */
830AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
831
832/** Array of valid domain-ID bits. */
833static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
834AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
835
836
837#ifndef VBOX_DEVICE_STRUCT_TESTCASE
838/** @todo Add IOMMU struct size/alignment verification, see
839 * Devices/testcase/Makefile.kmk and
840 * Devices/testcase/tstDeviceStructSize[RC].cpp */
841
842/**
843 * Returns the supported adjusted guest-address width (SAGAW) given the maximum
844 * guest address width (MGAW).
845 *
846 * @returns The CAP_REG.SAGAW value.
847 * @param uMgaw The CAP_REG.MGAW value.
848 */
849static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
850{
851 /*
852 * It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
853 * 5-level paging but not 4 or 3-level paging. So smaller page-table levels
854 * are always OR'ed in below.
855 *
856 * The bit values below (57, 48, 39 bits) represents the levels of page-table walks
857 * for 4KB base page size (5-level, 4-level and 3-level paging respectively).
858 *
859 * See Intel VT-d spec. 10.4.2 "Capability Register".
860 */
861 ++uMgaw;
862 uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) | RT_BIT(2) | RT_BIT(1)
863 : uMgaw >= 48 ? RT_BIT(2) | RT_BIT(1)
864 : uMgaw >= 39 ? RT_BIT(1)
865 : 0;
866 return fSagaw;
867}
868
869
870/**
871 * Returns the maximum supported paging level given the supported adjusted
872 * guest-address width (SAGAW) field.
873 *
874 * @returns The highest paging level supported, 0 if invalid.
875 * @param fSagaw The CAP_REG.SAGAW value.
876 */
877static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
878{
879 uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
880 : fSagaw & RT_BIT(2) ? 4
881 : fSagaw & RT_BIT(1) ? 3
882 : 0;
883 return cMaxPagingLevel;
884}
885
886
887/**
888 * Returns whether the interrupt remapping (IR) fault is qualified or not.
889 *
890 * @returns @c true if qualified, @c false otherwise.
891 * @param enmIrFault The interrupt remapping fault condition.
892 */
893static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
894{
895 switch (enmIrFault)
896 {
897 case VTDIRFAULT_IRTE_NOT_PRESENT:
898 case VTDIRFAULT_IRTE_PRESENT_RSVD:
899 case VTDIRFAULT_IRTE_PRESENT_INVALID:
900 case VTDIRFAULT_PID_READ_FAILED:
901 case VTDIRFAULT_PID_RSVD:
902 return true;
903 default:
904 return false;
905 }
906}
907
908
909/**
910 * Returns table translation mode's descriptive name.
911 *
912 * @returns The descriptive name.
913 * @param uTtm The RTADDR_REG.TTM value.
914 */
915static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
916{
917 Assert(!(uTtm & 3));
918 static const char* s_apszTtmNames[] =
919 {
920 "Legacy Mode",
921 "Scalable Mode",
922 "Reserved",
923 "Abort-DMA Mode"
924 };
925 return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
926}
927
928
929/**
930 * Gets the index of the group the register belongs to given its MMIO offset.
931 *
932 * @returns The group index.
933 * @param offReg The MMIO offset of the register.
934 * @param cbReg The size of the access being made (for bounds checking on
935 * debug builds).
936 */
937DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
938{
939 uint16_t const offLast = offReg + cbReg - 1;
940 AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
941 AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
942 return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
943}
944
945
946/**
947 * Gets the group the register belongs to given its MMIO offset.
948 *
949 * @returns Pointer to the first element of the register group.
950 * @param pThis The shared DMAR device state.
951 * @param offReg The MMIO offset of the register.
952 * @param cbReg The size of the access being made (for bounds checking on
953 * debug builds).
954 * @param pIdxGroup Where to store the index of the register group the register
955 * belongs to.
956 */
957DECLINLINE(uint8_t *) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
958{
959 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
960 uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
961 return apbRegs[*pIdxGroup];
962}
963
964
965/**
966 * Const/read-only version of dmarRegGetGroup.
967 *
968 * @copydoc dmarRegGetGroup
969 */
970DECLINLINE(uint8_t const*) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t *pIdxGroup)
971{
972 *pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
973 uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
974 return apbRegs[*pIdxGroup];
975}
976
977
978/**
979 * Writes a 32-bit register with the exactly the supplied value.
980 *
981 * @param pThis The shared DMAR device state.
982 * @param offReg The MMIO offset of the register.
983 * @param uReg The 32-bit value to write.
984 */
985static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
986{
987 uint8_t idxGroup;
988 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
989 NOREF(idxGroup);
990 *(uint32_t *)(pabRegs + offReg) = uReg;
991}
992
993
994/**
995 * Writes a 64-bit register with the exactly the supplied value.
996 *
997 * @param pThis The shared DMAR device state.
998 * @param offReg The MMIO offset of the register.
999 * @param uReg The 64-bit value to write.
1000 */
1001static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1002{
1003 uint8_t idxGroup;
1004 uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1005 NOREF(idxGroup);
1006 *(uint64_t *)(pabRegs + offReg) = uReg;
1007}
1008
1009
1010/**
1011 * Reads a 32-bit register with exactly the value it contains.
1012 *
1013 * @returns The raw register value.
1014 * @param pThis The shared DMAR device state.
1015 * @param offReg The MMIO offset of the register.
1016 */
1017static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1018{
1019 uint8_t idxGroup;
1020 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1021 NOREF(idxGroup);
1022 return *(uint32_t *)(pabRegs + offReg);
1023}
1024
1025
1026/**
1027 * Reads a 64-bit register with exactly the value it contains.
1028 *
1029 * @returns The raw register value.
1030 * @param pThis The shared DMAR device state.
1031 * @param offReg The MMIO offset of the register.
1032 */
1033static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1034{
1035 uint8_t idxGroup;
1036 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1037 NOREF(idxGroup);
1038 return *(uint64_t *)(pabRegs + offReg);
1039}
1040
1041
1042/**
1043 * Reads a 32-bit register with exactly the value it contains along with their
1044 * corresponding masks
1045 *
1046 * @param pThis The shared DMAR device state.
1047 * @param offReg The MMIO offset of the register.
1048 * @param puReg Where to store the raw 32-bit register value.
1049 * @param pfRwMask Where to store the RW mask corresponding to this register.
1050 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1051 */
1052static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t *puReg, uint32_t *pfRwMask, uint32_t *pfRw1cMask)
1053{
1054 uint8_t idxGroup;
1055 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1056 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1057 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1058 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1059 *puReg = *(uint32_t *)(pabRegs + offReg);
1060 *pfRwMask = *(uint32_t *)(pabRwMasks + offReg);
1061 *pfRw1cMask = *(uint32_t *)(pabRw1cMasks + offReg);
1062}
1063
1064
1065/**
1066 * Reads a 64-bit register with exactly the value it contains along with their
1067 * corresponding masks.
1068 *
1069 * @param pThis The shared DMAR device state.
1070 * @param offReg The MMIO offset of the register.
1071 * @param puReg Where to store the raw 64-bit register value.
1072 * @param pfRwMask Where to store the RW mask corresponding to this register.
1073 * @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1074 */
1075static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t *puReg, uint64_t *pfRwMask, uint64_t *pfRw1cMask)
1076{
1077 uint8_t idxGroup;
1078 uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1079 Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1080 uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1081 uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1082 *puReg = *(uint64_t *)(pabRegs + offReg);
1083 *pfRwMask = *(uint64_t *)(pabRwMasks + offReg);
1084 *pfRw1cMask = *(uint64_t *)(pabRw1cMasks + offReg);
1085}
1086
1087
1088/**
1089 * Writes a 32-bit register as it would be when written by software.
1090 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1091 *
1092 * @returns The value that's actually written to the register.
1093 * @param pThis The shared DMAR device state.
1094 * @param offReg The MMIO offset of the register.
1095 * @param uReg The 32-bit value to write.
1096 * @param puPrev Where to store the register value prior to writing.
1097 */
1098static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1099{
1100 /* Read current value from the 32-bit register. */
1101 uint32_t uCurReg;
1102 uint32_t fRwMask;
1103 uint32_t fRw1cMask;
1104 dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1105 *puPrev = uCurReg;
1106
1107 uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1108 uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1109 uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1110 uint32_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
1111
1112 /* Write new value to the 32-bit register. */
1113 dmarRegWriteRaw32(pThis, offReg, uNewReg);
1114 return uNewReg;
1115}
1116
1117
1118/**
1119 * Writes a 64-bit register as it would be when written by software.
1120 * This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1121 *
1122 * @returns The value that's actually written to the register.
1123 * @param pThis The shared DMAR device state.
1124 * @param offReg The MMIO offset of the register.
1125 * @param uReg The 64-bit value to write.
1126 * @param puPrev Where to store the register value prior to writing.
1127 */
1128static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1129{
1130 /* Read current value from the 64-bit register. */
1131 uint64_t uCurReg;
1132 uint64_t fRwMask;
1133 uint64_t fRw1cMask;
1134 dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1135 *puPrev = uCurReg;
1136
1137 uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1138 uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1139 uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1140 uint64_t const uNewReg = (fRoBits | fRwBits) & ~fRw1cBits;
1141
1142 /* Write new value to the 64-bit register. */
1143 dmarRegWriteRaw64(pThis, offReg, uNewReg);
1144 return uNewReg;
1145}
1146
1147
1148/**
1149 * Reads a 32-bit register as it would be when read by software.
1150 *
1151 * @returns The register value.
1152 * @param pThis The shared DMAR device state.
1153 * @param offReg The MMIO offset of the register.
1154 */
1155static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1156{
1157 return dmarRegReadRaw32(pThis, offReg);
1158}
1159
1160
1161/**
1162 * Reads a 64-bit register as it would be when read by software.
1163 *
1164 * @returns The register value.
1165 * @param pThis The shared DMAR device state.
1166 * @param offReg The MMIO offset of the register.
1167 */
1168static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1169{
1170 return dmarRegReadRaw64(pThis, offReg);
1171}
1172
1173
1174/**
1175 * Modifies a 32-bit register.
1176 *
1177 * @param pThis The shared DMAR device state.
1178 * @param offReg The MMIO offset of the register.
1179 * @param fAndMask The AND mask (applied first).
1180 * @param fOrMask The OR mask.
1181 * @remarks This does NOT apply RO or RW1C masks while modifying the
1182 * register.
1183 */
1184static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1185{
1186 uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1187 uReg = (uReg & fAndMask) | fOrMask;
1188 dmarRegWriteRaw32(pThis, offReg, uReg);
1189}
1190
1191
1192/**
1193 * Modifies a 64-bit register.
1194 *
1195 * @param pThis The shared DMAR device state.
1196 * @param offReg The MMIO offset of the register.
1197 * @param fAndMask The AND mask (applied first).
1198 * @param fOrMask The OR mask.
1199 * @remarks This does NOT apply RO or RW1C masks while modifying the
1200 * register.
1201 */
1202static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1203{
1204 uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1205 uReg = (uReg & fAndMask) | fOrMask;
1206 dmarRegWriteRaw64(pThis, offReg, uReg);
1207}
1208
1209
1210/**
1211 * Checks if the invalidation-queue is empty.
1212 *
1213 * Extended version which optionally returns the current queue head and tail
1214 * offsets.
1215 *
1216 * @returns @c true if empty, @c false otherwise.
1217 * @param pThis The shared DMAR device state.
1218 * @param poffQh Where to store the queue head offset. Optional, can be NULL.
1219 * @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1220 */
1221static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t *poffQh, uint32_t *poffQt)
1222{
1223 /* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1224 uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1225 uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1226
1227 /* Don't bother masking QT, QH since other bits are RsvdZ. */
1228 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1229 Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1230 if (poffQh)
1231 *poffQh = uIqhReg;
1232 if (poffQt)
1233 *poffQt = uIqtReg;
1234 return uIqtReg == uIqhReg;
1235}
1236
1237
1238/**
1239 * Checks if the invalidation-queue is empty.
1240 *
1241 * @returns @c true if empty, @c false otherwise.
1242 * @param pThis The shared DMAR device state.
1243 */
1244static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1245{
1246 return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh */, NULL /* poffQt */);
1247}
1248
1249
1250/**
1251 * Checks if the invalidation-queue is capable of processing requests.
1252 *
1253 * @returns @c true if the invalidation-queue can process requests, @c false
1254 * otherwise.
1255 * @param pThis The shared DMAR device state.
1256 */
1257static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1258{
1259 /* Check if queued-invalidation is enabled. */
1260 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1261 if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1262 {
1263 /* Check if there are no invalidation-queue or timeout errors. */
1264 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1265 if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_ITE_MASK)))
1266 return true;
1267 }
1268 return false;
1269}
1270
1271
1272/**
1273 * Wakes up the invalidation-queue thread if there are requests to be processed.
1274 *
1275 * @param pDevIns The IOMMU device instance.
1276 */
1277static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1278{
1279 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1280 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1281 Log4Func(("\n"));
1282
1283 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1284
1285 if ( dmarInvQueueCanProcessRequests(pThis)
1286 && !dmarInvQueueIsEmpty(pThis))
1287 {
1288 Log4Func(("Signaling the invalidation-queue thread\n"));
1289 PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1290 }
1291}
1292
1293
1294/**
1295 * Raises an event on behalf of the DMAR.
1296 *
1297 * These are events that are generated by the DMAR itself (like faults and
1298 * invalidation completion notifications).
1299 *
1300 * @param pDevIns The IOMMU device instance.
1301 * @param enmEventType The DMAR event type.
1302 *
1303 * @remarks The DMAR lock must be held while calling this function.
1304 */
1305static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1306{
1307 uint16_t offCtlReg;
1308 uint32_t fIntrMaskedMask;
1309 uint32_t fIntrPendingMask;
1310 uint16_t offMsiAddrLoReg;
1311 uint16_t offMsiAddrHiReg;
1312 uint16_t offMsiDataReg;
1313 switch (enmEventType)
1314 {
1315 case DMAREVENTTYPE_INV_COMPLETE:
1316 {
1317 offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1318 fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1319 fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1320 offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1321 offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1322 offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1323 break;
1324 }
1325
1326 case DMAREVENTTYPE_FAULT:
1327 {
1328 offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1329 fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1330 fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1331 offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1332 offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1333 offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1334 break;
1335 }
1336
1337 default:
1338 {
1339 /* Shouldn't ever happen. */
1340 AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1341 }
1342 }
1343
1344 /* Check if software has masked the interrupt. */
1345 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1346 uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1347 if (!(uCtlReg & fIntrMaskedMask))
1348 {
1349 /*
1350 * Interrupt is unmasked, raise it.
1351 * Interrupts generated by the DMAR have trigger mode and level as 0.
1352 * See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1353 */
1354 MSIMSG Msi;
1355 Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1356 Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1357 Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1358 Assert(Msi.Data.n.u1Level == 0);
1359 Assert(Msi.Data.n.u1TriggerMode == 0);
1360
1361 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1362 pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1363
1364 /* Clear interrupt pending bit. */
1365 uCtlReg &= ~fIntrPendingMask;
1366 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1367 }
1368 else
1369 {
1370 /* Interrupt is masked, set the interrupt pending bit. */
1371 uCtlReg |= fIntrPendingMask;
1372 dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1373 }
1374}
1375
1376
1377/**
1378 * Raises an interrupt in response to a fault event.
1379 *
1380 * @param pDevIns The IOMMU device instance.
1381 *
1382 * @remarks This assumes the caller has already set the required status bits in the
1383 * FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1384 */
1385static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1386{
1387 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1388 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1389 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1390
1391#ifdef RT_STRICT
1392 {
1393 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1394 uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK | VTD_BF_FSTS_REG_PFO_MASK
1395 /* | VTD_BF_FSTS_REG_APF_MASK | VTD_BF_FSTS_REG_AFO_MASK */ /* AFL not supported */
1396 /* | VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK */ /* Device-TLBs not supported */
1397 | VTD_BF_FSTS_REG_IQE_MASK;
1398 Assert(uFstsReg & fFaultMask);
1399 }
1400#endif
1401 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1402}
1403
1404
1405#ifdef IN_RING3
1406/**
1407 * Raises an interrupt in response to an invalidation (complete) event.
1408 *
1409 * @param pDevIns The IOMMU device instance.
1410 */
1411static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1412{
1413 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1414 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1415 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1416
1417 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1418 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1419 {
1420 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1421 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1422 }
1423}
1424#endif /* IN_RING3 */
1425
1426
1427/**
1428 * Checks if a primary fault can be recorded.
1429 *
1430 * @returns @c true if the fault can be recorded, @c false otherwise.
1431 * @param pDevIns The IOMMU device instance.
1432 * @param pThis The shared DMAR device state.
1433 *
1434 * @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1435 * NOT call it unless there is a fault condition!
1436 */
1437static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1438{
1439 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1440 DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1441
1442 uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1443 if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1444 return false;
1445
1446 /*
1447 * If we add more FRCD registers, we'll have to loop through them here.
1448 * Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1449 * nor do we need to increment FRI.
1450 *
1451 * See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1452 */
1453 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1454 uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1455 if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1456 {
1457 uFstsReg |= VTD_BF_FSTS_REG_PFO_MASK;
1458 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1459 return false;
1460 }
1461
1462 return true;
1463}
1464
1465
1466/**
1467 * Records a primary fault.
1468 *
1469 * @param pDevIns The IOMMU device instance.
1470 * @param uFrcdHi The FRCD_HI_REG value for this fault.
1471 * @param uFrcdLo The FRCD_LO_REG value for this fault.
1472 */
1473static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1474{
1475 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1476 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1477
1478 DMAR_LOCK(pDevIns, pThisCC);
1479
1480 /* We don't support advance fault logging. */
1481 Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1482
1483 if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1484 {
1485 /* Update the fault recording registers with the fault information. */
1486 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1487 dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1488
1489 /* Set the Pending Primary Fault (PPF) field in the status register. */
1490 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1491
1492 /* Raise interrupt if necessary. */
1493 dmarFaultEventRaiseInterrupt(pDevIns);
1494 }
1495
1496 DMAR_UNLOCK(pDevIns, pThisCC);
1497}
1498
1499
1500/**
1501 * Records an interrupt request fault.
1502 *
1503 * @param pDevIns The IOMMU device instance.
1504 * @param enmDiag The diagnostic reason.
1505 * @param idDevice The device ID (bus, device, function).
1506 * @param idxIntr The interrupt index.
1507 * @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1508 * not qualified.
1509 */
1510static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1511{
1512 /*
1513 * Update the diagnostic reason (even if software wants to supress faults).
1514 */
1515 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1516 pThis->enmDiag = enmDiag;
1517
1518 /*
1519 * Figure out the fault reason to report to software from our diagnostic code.
1520 * The case labels below are sorted alphabetically for convenience.
1521 */
1522 VTDIRFAULT enmIrFault;
1523 switch (enmDiag)
1524 {
1525 case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1526 case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1527 case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1528 case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1529 case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1530 case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1531 case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1532 case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1533 case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1534 case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1535
1536 /* Shouldn't ever happen. */
1537 default:
1538 {
1539 AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1540 enmDiag));
1541 }
1542 }
1543
1544 /*
1545 * Qualified faults are those that can be suppressed by software using the FPD bit
1546 * in the interrupt-remapping table entry.
1547 */
1548 bool fFpd;
1549 bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1550 if (fQualifiedFault)
1551 {
1552 AssertReturnVoid(pIrte);
1553 fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1554 }
1555 else
1556 fFpd = false;
1557
1558 if (!fFpd)
1559 {
1560 /* Construct and record the error. */
1561 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1562 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1563 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1564 uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1565 dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1566 }
1567}
1568
1569
1570/**
1571 * Records an address translation fault.
1572 *
1573 * @param pDevIns The IOMMU device instance.
1574 * @param enmDiag The diagnostic reason.
1575 * @param pMemReqIn The DMA memory request input.
1576 * @param pMemReqAux The DMA memory request auxiliary info.
1577 */
1578static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1579{
1580 /*
1581 * Update the diagnostic reason (even if software wants to supress faults).
1582 */
1583 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1584 pThis->enmDiag = enmDiag;
1585
1586 /*
1587 * Qualified faults are those that can be suppressed by software using the FPD bit
1588 * in the context entry, scalable-mode context entry etc.
1589 */
1590 if (!pMemReqAux->fFpd)
1591 {
1592 /*
1593 * Figure out the fault reason to report to software from our diagnostic code.
1594 * The case labels below are sorted alphabetically for convenience.
1595 */
1596 VTDATFAULT enmAtFault;
1597 bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1598 switch (enmDiag)
1599 {
1600 /* LM (Legacy Mode) faults. */
1601 case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1602 case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1603 case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1604 case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1605 case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1606 case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1607 case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1608 case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1609 case kDmarDiag_At_Lm_Slpptr_Read_Failed: enmAtFault = VTDATFAULT_LCT_4_3; break;
1610 case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1611 case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1612 case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1613
1614 /* RTA (Root Table Address) faults. */
1615 case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1616 case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1617 case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1618
1619 /* XM (Legacy mode or Scalable Mode) faults. */
1620 case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1621 case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1622 case kDmarDiag_At_Xm_Perm_Denied: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1623 case kDmarDiag_At_Xm_Pte_Rsvd:
1624 case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1625 case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1626
1627 /* Shouldn't ever happen. */
1628 default:
1629 {
1630 AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1631 DMAR_LOG_PFX, enmDiag));
1632 }
1633 }
1634
1635 /* Construct and record the error. */
1636 uint16_t const idDevice = pMemReqIn->idDevice;
1637 uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1638 uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1639 uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1640 uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1641 bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1642 uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1643 PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1644
1645 uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1646 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1647 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1648 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1649 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1650 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1651 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1652 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1653 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1654 | RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1655 uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1656 dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1657 }
1658}
1659
1660
1661/**
1662 * Records an IQE fault.
1663 *
1664 * @param pDevIns The IOMMU device instance.
1665 * @param enmIqei The IQE information.
1666 * @param enmDiag The diagnostic reason.
1667 */
1668static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1669{
1670 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1671 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1672
1673 DMAR_LOCK(pDevIns, pThisCC);
1674
1675 /* Update the diagnostic reason. */
1676 pThis->enmDiag = enmDiag;
1677
1678 /* Set the error bit. */
1679 uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1680 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1681
1682 /* Set the error information. */
1683 uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1684 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1685
1686 dmarFaultEventRaiseInterrupt(pDevIns);
1687
1688 DMAR_UNLOCK(pDevIns, pThisCC);
1689}
1690
1691
1692/**
1693 * Handles writes to GCMD_REG.
1694 *
1695 * @returns Strict VBox status code.
1696 * @param pDevIns The IOMMU device instance.
1697 * @param uGcmdReg The value written to GCMD_REG.
1698 */
1699static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1700{
1701 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1702 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1703 uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1704 uint64_t const fExtCapReg = pThis->fExtCapReg;
1705
1706 /* Queued-invalidation. */
1707 if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1708 && (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1709 {
1710 if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1711 {
1712 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1713 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1714 }
1715 else
1716 {
1717 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1718 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1719 }
1720 }
1721
1722 if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1723 {
1724 /* Set Interrupt Remapping Table Pointer (SIRTP). */
1725 if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1726 {
1727 /** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1728 * supported. */
1729 pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1730 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1731 }
1732
1733 /* Interrupt remapping. */
1734 if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1735 {
1736 if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1737 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1738 else
1739 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1740 }
1741
1742 /* Compatibility format interrupts. */
1743 if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1744 {
1745 if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1746 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1747 else
1748 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1749 }
1750 }
1751
1752 /* Set Root Table Pointer (SRTP). */
1753 if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1754 {
1755 /** @todo Perform global invalidation of all remapping translation caches when
1756 * ESRTPS is supported. */
1757 pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1758 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1759 }
1760
1761 /* Translation (DMA remapping). */
1762 if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1763 {
1764 if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1765 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1766 else
1767 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1768 }
1769
1770 return VINF_SUCCESS;
1771}
1772
1773
1774/**
1775 * Handles writes to CCMD_REG.
1776 *
1777 * @returns Strict VBox status code.
1778 * @param pDevIns The IOMMU device instance.
1779 * @param offReg The MMIO register offset.
1780 * @param cbReg The size of the MMIO access (in bytes).
1781 * @param uCcmdReg The value written to CCMD_REG.
1782 */
1783static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1784{
1785 /* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1786 if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1787 {
1788 /* Check if we need to invalidate the context-context. */
1789 bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1790 if (fIcc)
1791 {
1792 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1793 uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1794 if (uMajorVersion < 6)
1795 {
1796 /* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1797 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1798 if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1799 {
1800 /* Verify table translation mode is legacy. */
1801 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1802 if (fTtm == VTD_TTM_LEGACY_MODE)
1803 {
1804 /** @todo Invalidate. */
1805 return VINF_SUCCESS;
1806 }
1807 pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1808 }
1809 else
1810 pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1811 }
1812 else
1813 pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1814 dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1815 }
1816 }
1817 return VINF_SUCCESS;
1818}
1819
1820
1821/**
1822 * Handles writes to FECTL_REG.
1823 *
1824 * @returns Strict VBox status code.
1825 * @param pDevIns The IOMMU device instance.
1826 * @param uFectlReg The value written to FECTL_REG.
1827 */
1828static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1829{
1830 /*
1831 * If software unmasks the interrupt when the interrupt is pending, we must raise
1832 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1833 */
1834 if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1835 && ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1836 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1837 return VINF_SUCCESS;
1838}
1839
1840
1841/**
1842 * Handles writes to FSTS_REG.
1843 *
1844 * @returns Strict VBox status code.
1845 * @param pDevIns The IOMMU device instance.
1846 * @param uFstsReg The value written to FSTS_REG.
1847 * @param uPrev The value in FSTS_REG prior to writing it.
1848 */
1849static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1850{
1851 /*
1852 * If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1853 * the interrupt pending (IP) bit must be cleared.
1854 *
1855 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1856 */
1857 uint32_t const fChanged = uPrev ^ uFstsReg;
1858 if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK | VTD_BF_FSTS_REG_ITE_MASK
1859 | VTD_BF_FSTS_REG_IQE_MASK | VTD_BF_FSTS_REG_PFO_MASK))
1860 {
1861 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1862 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1863 }
1864 return VINF_SUCCESS;
1865}
1866
1867
1868/**
1869 * Handles writes to IQT_REG.
1870 *
1871 * @returns Strict VBox status code.
1872 * @param pDevIns The IOMMU device instance.
1873 * @param offReg The MMIO register offset.
1874 * @param uIqtReg The value written to IQT_REG.
1875 */
1876static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1877{
1878 /* We only care about the low 32-bits, high 32-bits are reserved. */
1879 Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1880 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1881
1882 /* Paranoia. */
1883 Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1884
1885 uint32_t const offQt = uIqtReg;
1886 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1887 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1888
1889 /* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1890 if ( fDw != VTD_IQA_REG_DW_256_BIT
1891 || !(offQt & RT_BIT(4)))
1892 dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1893 else
1894 {
1895 /* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1896 dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1897 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1898 }
1899 return VINF_SUCCESS;
1900}
1901
1902
1903/**
1904 * Handles writes to IQA_REG.
1905 *
1906 * @returns Strict VBox status code.
1907 * @param pDevIns The IOMMU device instance.
1908 * @param offReg The MMIO register offset.
1909 * @param uIqaReg The value written to IQA_REG.
1910 */
1911static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1912{
1913 /* At present, we only care about the low 32-bits, high 32-bits are data. */
1914 Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1915
1916 /** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1917 * returns true? The Intel VT-d spec. doesn't state anywhere that it
1918 * cannot happen or that it's ignored when it does happen. */
1919
1920 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1921 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1922 if (fDw == VTD_IQA_REG_DW_256_BIT)
1923 {
1924 bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK | VTD_BF_ECAP_REG_ADMS_MASK));
1925 if (fSupports256BitDw)
1926 { /* likely */ }
1927 else
1928 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1929 }
1930 /* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1931
1932 return VINF_SUCCESS;
1933}
1934
1935
1936/**
1937 * Handles writes to ICS_REG.
1938 *
1939 * @returns Strict VBox status code.
1940 * @param pDevIns The IOMMU device instance.
1941 * @param uIcsReg The value written to ICS_REG.
1942 */
1943static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1944{
1945 /*
1946 * If the IP field is set when software services the interrupt condition,
1947 * (by clearing the IWC field), the IP field must be cleared.
1948 */
1949 if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1950 {
1951 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1952 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1953 }
1954 return VINF_SUCCESS;
1955}
1956
1957
1958/**
1959 * Handles writes to IECTL_REG.
1960 *
1961 * @returns Strict VBox status code.
1962 * @param pDevIns The IOMMU device instance.
1963 * @param uIectlReg The value written to IECTL_REG.
1964 */
1965static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1966{
1967 /*
1968 * If software unmasks the interrupt when the interrupt is pending, we must raise
1969 * the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1970 */
1971 if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1972 && ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1973 dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1974 return VINF_SUCCESS;
1975}
1976
1977
1978/**
1979 * Handles writes to FRCD_REG (High 64-bits).
1980 *
1981 * @returns Strict VBox status code.
1982 * @param pDevIns The IOMMU device instance.
1983 * @param offReg The MMIO register offset.
1984 * @param cbReg The size of the MMIO access (in bytes).
1985 * @param uFrcdHiReg The value written to FRCD_REG.
1986 * @param uPrev The value in FRCD_REG prior to writing it.
1987 */
1988static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
1989{
1990 /* We only care about responding to high 32-bits, low 32-bits are read-only. */
1991 if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
1992 {
1993 /*
1994 * If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
1995 * Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
1996 * has only 1 FRCD register.
1997 *
1998 * See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1999 */
2000 AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2001 uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2002 if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2003 {
2004 Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2005 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2006 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2007 dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2008 }
2009 }
2010 return VINF_SUCCESS;
2011}
2012
2013
2014/**
2015 * Performs a PCI target abort for a DMA remapping (DR) operation.
2016 *
2017 * @param pDevIns The IOMMU device instance.
2018 */
2019static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2020{
2021 /** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2022 * as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2023 * who knows. */
2024 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2025 uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) | VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2026 PDMPciDevSetStatus(pPciDev, u16Status);
2027}
2028
2029
2030/**
2031 * Checks whether the address width (AW) is supported by our hardware
2032 * implementation for legacy mode address translation.
2033 *
2034 * @returns @c true if it's supported, @c false otherwise.
2035 * @param pThis The shared DMAR device state.
2036 * @param pCtxEntry The context entry.
2037 * @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2038 */
2039static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2040{
2041 uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2042 uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2043 uint8_t const fAwMask = RT_BIT(fAw);
2044 uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2045 Assert(!(fSagaw & ~(RT_BIT(1) | RT_BIT(2) | RT_BIT(3))));
2046
2047 uint8_t const cPagingLevel = fAw + 2;
2048 if (pcPagingLevel)
2049 *pcPagingLevel = cPagingLevel;
2050
2051 /* With pass-through, the address width must be the largest AGAW supported by hardware. */
2052 if (fTt == VTD_TT_UNTRANSLATED_PT)
2053 {
2054 Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2055 return cPagingLevel == pThis->cMaxPagingLevel;
2056 }
2057
2058 /* The address width must be any of the ones supported by hardware. */
2059 if (fAw < 4)
2060 return (fSagaw & fAwMask) != 0;
2061
2062 return false;
2063}
2064
2065
2066/**
2067 * Reads a root entry from guest memory.
2068 *
2069 * @returns VBox status code.
2070 * @param pDevIns The IOMMU device instance.
2071 * @param uRtaddrReg The current RTADDR_REG value.
2072 * @param idxRootEntry The index of the root entry to read.
2073 * @param pRootEntry Where to store the read root entry.
2074 */
2075static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2076{
2077 size_t const cbRootEntry = sizeof(*pRootEntry);
2078 RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2079 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2080}
2081
2082
2083/**
2084 * Reads a context entry from guest memory.
2085 *
2086 * @returns VBox status code.
2087 * @param pDevIns The IOMMU device instance.
2088 * @param GCPhysCtxTable The physical address of the context table.
2089 * @param idxCtxEntry The index of the context entry to read.
2090 * @param pCtxEntry Where to store the read context entry.
2091 */
2092static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2093{
2094 /* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2095 size_t const cbCtxEntry = sizeof(*pCtxEntry);
2096 RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2097 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2098}
2099
2100
2101/**
2102 * Reads a second-level paging entry from guest memory.
2103 *
2104 * @returns VBox status code.
2105 * @param pDevIns The IOMMU device instance.
2106 * @param GCPhysSlptPtr The physical address of the SLPTPTR.
2107 * @param pSlpEntry Where to store the read SLPTPTR.
2108 */
2109static int dmarDrReadSlpPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhysSlptPtr, PVTD_SLP_ENTRY_T pSlpEntry)
2110{
2111 /* We don't verify bits 63:HAW of GCPhysSlptPtr is 0 since reading from such an address should fail anyway. */
2112 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysSlptPtr, pSlpEntry, sizeof(*pSlpEntry));
2113}
2114
2115
2116/**
2117 * Validates and updates the output I/O page of a translation.
2118 *
2119 * @returns VBox status code.
2120 * @param pDevIns The IOMMU device instance.
2121 * @param GCPhysBase The output address of the translation.
2122 * @param cShift The page shift of the translated address.
2123 * @param fPerm The permissions granted for the translated region.
2124 * @param pMemReqIn The DMA memory request input.
2125 * @param pMemReqAux The DMA memory request auxiliary info.
2126 * @param pIoPageOut Where to store the output of the translation.
2127 */
2128static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2129 PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2130{
2131 Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2132
2133 /* Ensure the output address is not in the interrupt address range. */
2134 if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2135 {
2136 pIoPageOut->GCPhysBase = GCPhysBase;
2137 pIoPageOut->cShift = cShift;
2138 pIoPageOut->fPerm = fPerm;
2139 return VINF_SUCCESS;
2140 }
2141
2142 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2143 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2144}
2145
2146
2147/**
2148 * Performs second level translation.
2149 *
2150 * This is a DMA address lookup callback function which performs the translation
2151 * (and access control) as part of the lookup.
2152 *
2153 * @returns VBox status code.
2154 * @param pDevIns The IOMMU device instance.
2155 * @param pMemReqIn The DMA memory request input.
2156 * @param pMemReqAux The DMA memory request auxiliary info.
2157 * @param pIoPageOut Where to store the output of the translation.
2158 */
2159static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2160 PDMARIOPAGE pIoPageOut)
2161{
2162 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2163
2164 /* Sanity. */
2165 Assert(pIoPageOut);
2166 Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ | DMAR_PERM_WRITE));
2167 Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2168 || pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2169
2170 /* Mask of valid paging entry bits. */
2171 static uint64_t const s_auPtEntityRsvd[] = { VTD_SL_PTE_VALID_MASK,
2172 VTD_SL_PDE_VALID_MASK,
2173 VTD_SL_PDPE_VALID_MASK,
2174 VTD_SL_PML4E_VALID_MASK,
2175 VTD_SL_PML5E_VALID_MASK };
2176
2177 /* Paranoia. */
2178 Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2179 AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == 5);
2180
2181 /* Second-level translations restricts input address to an implementation-specific MGAW. */
2182 uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2183 if (!(uAddrIn & pThis->fMgawInvMask))
2184 { /* likely */ }
2185 else
2186 {
2187 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2188 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2189 }
2190
2191 /*
2192 * Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2193 * Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2194 */
2195 uint64_t uPtEntity = pMemReqAux->uSlptPtr;
2196 int8_t iLevel = pMemReqAux->cPagingLevel - 1;
2197 uint8_t cLevelShift = X86_PAGE_4K_SHIFT + (iLevel * 9);
2198 Assert(iLevel >= 2);
2199 for (;;)
2200 {
2201 /*
2202 * Check I/O permissions.
2203 * This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2204 *
2205 * See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2206 */
2207 uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2208 uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2209 Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2210 Assert(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK); /* No Second-level access/dirty support. */
2211 if ((fPtPerm & fReqPerm) == fReqPerm)
2212 { /* likely */ }
2213 else
2214 {
2215 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Denied, pMemReqIn, pMemReqAux);
2216 break;
2217 }
2218
2219 /*
2220 * Validate reserved bits of the current paging entry.
2221 */
2222 if (!(uPtEntity & ~s_auPtEntityRsvd[iLevel]))
2223 { /* likely */ }
2224 else
2225 {
2226 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2227 break;
2228 }
2229
2230 /*
2231 * Check if this is a 1GB page or a 2MB page.
2232 */
2233 AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2234 uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2235 if (fLargePage && iLevel > 0)
2236 {
2237 Assert(iLevel == 1 || iLevel == 2); /* Is guaranteed by the reserved bits check above. */
2238 uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2239 if (fSllpsMask & RT_BIT(iLevel - 1))
2240 {
2241 /*
2242 * We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2243 * All other reserved bits are identical to the regular page-size paging entity which we've already
2244 * checked above.
2245 */
2246 Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2247
2248 RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2249 return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2250 }
2251
2252 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2253 break;
2254 }
2255
2256 /*
2257 * If this is the final PTE, compute the translation address and we're done.
2258 */
2259 if (iLevel == 0)
2260 {
2261 RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2262 return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2263 }
2264
2265 /*
2266 * Move to the next level.
2267 */
2268 --iLevel;
2269 cLevelShift = X86_PAGE_4K_SHIFT + (iLevel * 9);
2270
2271 /*
2272 * Read the paging entry for the next level.
2273 */
2274 {
2275 uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2276 uint64_t const offPte = idxPte << 3;
2277 RTGCPHYS const GCPhysPtEntity = uPtEntity | offPte;
2278 int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2279 if (RT_SUCCESS(rc))
2280 { /* likely */ }
2281 else
2282 {
2283 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2284 break;
2285 }
2286 }
2287 }
2288
2289 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2290}
2291
2292
2293/**
2294 * Checks whether two consecutive I/O page results of a DMA memory request
2295 * translates to a physically contiguous region.
2296 *
2297 * @returns @c true if the I/O pages are contiguous, @c false otherwise.
2298 * @param pIoPagePrev The previous I/O page.
2299 * @param pIoPage The current I/O page.
2300 */
2301static bool dmarIsIoPageAccessContig(PCDMARIOPAGE pIoPagePrev, PCDMARIOPAGE pIoPage)
2302{
2303 /* Paranoia: Permissions for pages of a DMA memory request must be identical. */
2304 Assert(pIoPagePrev->fPerm == pIoPage->fPerm);
2305
2306 size_t const cbPrev = RT_BIT_64(pIoPagePrev->cShift);
2307 RTGCPHYS const GCPhysPrev = pIoPagePrev->GCPhysBase;
2308 RTGCPHYS const GCPhys = pIoPage->GCPhysBase;
2309#ifdef RT_STRICT
2310 /* Paranoia: Ensure offset bits are 0. */
2311 {
2312 uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pIoPagePrev->cShift);
2313 uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pIoPage->cShift);
2314 Assert(!(GCPhysPrev & fOffMaskPrev));
2315 Assert(!(GCPhys & fOffMask));
2316 }
2317#endif
2318 return GCPhysPrev + cbPrev == GCPhys;
2319}
2320
2321
2322/**
2323 * Looks up the range of addresses for a DMA memory request remapping.
2324 *
2325 * @returns VBox status code.
2326 * @param pDevIns The IOMMU device instance.
2327 * @param pfnLookup The DMA address lookup function.
2328 * @param pMemReqRemap The DMA memory request remapping info.
2329 */
2330static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2331{
2332 RTGCPHYS GCPhysAddr = NIL_RTGCPHYS;
2333 DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2334 uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2335 size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2336 uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2337 uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2338 size_t cbRemaining = cbAddrIn;
2339
2340 int rc;
2341 DMARIOPAGE IoPagePrev;
2342 RT_ZERO(IoPagePrev);
2343 for (;;)
2344 {
2345 /* Update the input memory request with the next address in our range that needs translation. */
2346 MemReqIn.AddrRange.uAddr = uAddrInBase;
2347 MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2348
2349 DMARIOPAGE IoPage;
2350 rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2351 if (RT_SUCCESS(rc))
2352 {
2353 Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2354
2355 /* Store the translated address before continuing to access more pages. */
2356 if (cbRemaining == cbAddrIn)
2357 {
2358 uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2359 uint64_t const offAddrOut = uAddrIn & fOffMask;
2360 Assert(!(IoPage.GCPhysBase & fOffMask));
2361 GCPhysAddr = IoPage.GCPhysBase | offAddrOut;
2362 }
2363 /* Check if addresses translated so far result in a physically contiguous region. */
2364 else if (!dmarIsIoPageAccessContig(&IoPagePrev, &IoPage))
2365 {
2366 rc = VERR_OUT_OF_RANGE;
2367 break;
2368 }
2369
2370 /* Store the I/O page lookup from the first/previous access. */
2371 IoPagePrev = IoPage;
2372
2373 /* Check if we need to access more pages. */
2374 size_t const cbPage = RT_BIT_64(IoPage.cShift);
2375 if (cbRemaining > cbPage - offAddrIn)
2376 {
2377 cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2378 uAddrInBase += cbPage; /* Update address of the next access. */
2379 offAddrIn = 0; /* After first page, all pages are accessed from offset 0. */
2380 }
2381 else
2382 {
2383 /* Caller (PDM) doesn't expect more data accessed than what was requested. */
2384 cbRemaining = 0;
2385 break;
2386 }
2387 }
2388 else
2389 break;
2390 }
2391
2392 pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddr;
2393 pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2394 pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2395 return rc;
2396}
2397
2398
2399/**
2400 * Handles legacy mode DMA address remapping.
2401 *
2402 * @returns VBox status code.
2403 * @param pDevIns The IOMMU device instance.
2404 * @param uRtaddrReg The current RTADDR_REG value.
2405 * @param pMemReqRemap The DMA memory request remapping info.
2406 */
2407static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2408{
2409 PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2410 PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2411 PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2412 Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2413
2414 /* Read the root-entry from guest memory. */
2415 uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2416 VTD_ROOT_ENTRY_T RootEntry;
2417 int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2418 if (RT_SUCCESS(rc))
2419 {
2420 /* Check if the root entry is present (must be done before validating reserved bits). */
2421 uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2422 uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2423 bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2424 if (fRootEntryPresent)
2425 {
2426 /* Validate reserved bits in the root entry. */
2427 if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2428 && !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2429 {
2430 /* Read the context-entry from guest memory. */
2431 RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2432 uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2433 VTD_CONTEXT_ENTRY_T CtxEntry;
2434 rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2435 if (RT_SUCCESS(rc))
2436 {
2437 uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2438 uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2439
2440 /* Note the FPD bit which software can use to supress translation faults from here on in. */
2441 pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2442
2443 /* Check if the context-entry is present (must be done before validating reserved bits). */
2444 bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2445 if (fCtxEntryPresent)
2446 {
2447 /* Validate reserved bits in the context-entry. */
2448 if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2449 && !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
2450 {
2451 /* Get the domain ID for this mapping. */
2452 pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2453
2454 /* Validate the translation type (TT). */
2455 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2456 uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2457 switch (fTt)
2458 {
2459 case VTD_TT_UNTRANSLATED_SLP:
2460 {
2461 /*
2462 * Untranslated requests are translated using second-level paging structures referenced
2463 * through SLPTPTR. Translated requests and Translation Requests are blocked.
2464 */
2465 if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2466 {
2467 /* Validate the address width and get the paging level. */
2468 uint8_t cPagingLevel;
2469 if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2470 {
2471 /* Read the SLPTPTR from guest memory. */
2472 VTD_SLP_ENTRY_T SlptPtr;
2473 RTGCPHYS const GCPhysSlptPtr = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2474 rc = dmarDrReadSlpPtr(pDevIns, GCPhysSlptPtr, &SlptPtr);
2475 if (RT_SUCCESS(rc))
2476 {
2477 /* Finally... perform second-level translation. */
2478 pMemReqAux->uSlptPtr = SlptPtr;
2479 pMemReqAux->cPagingLevel = cPagingLevel;
2480 return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2481 }
2482 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2483 }
2484 else
2485 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2486 }
2487 else
2488 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2489 break;
2490 }
2491
2492 case VTD_TT_UNTRANSLATED_PT:
2493 {
2494 /*
2495 * Untranslated requests are processed as pass-through (PT) if PT is supported.
2496 * Translated and translation requests are blocked. If PT isn't supported this TT value
2497 * is reserved which I assume raises a fault (hence fallthru below).
2498 */
2499 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2500 {
2501 if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2502 {
2503 if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2504 {
2505 PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2506 PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2507 pOut->AddrRange.uAddr = pIn->AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2508 pOut->AddrRange.cb = pIn->AddrRange.cb;
2509 pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2510 return VINF_SUCCESS;
2511 }
2512 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2513 }
2514 else
2515 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2516 break;
2517 }
2518 RT_FALL_THRU();
2519 }
2520
2521 case VTD_TT_UNTRANSLATED_DEV_TLB:
2522 {
2523 /*
2524 * Untranslated, translated and translation requests are supported but requires
2525 * device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2526 */
2527 Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2528 RT_FALL_THRU();
2529 }
2530
2531 default:
2532 {
2533 /* Any other TT value is reserved. */
2534 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2535 break;
2536 }
2537 }
2538 }
2539 else
2540 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2541 }
2542 else
2543 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2544 }
2545 else
2546 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2547 }
2548 else
2549 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2550 }
2551 else
2552 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2553 }
2554 else
2555 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2556 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2557}
2558
2559
2560/**
2561 * Handles remapping of DMA address requests in scalable mode.
2562 *
2563 * @returns VBox status code.
2564 * @param pDevIns The IOMMU device instance.
2565 * @param uRtaddrReg The current RTADDR_REG value.
2566 * @param pMemReqRemap The DMA memory request remapping info.
2567 */
2568static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2569{
2570 NOREF(pMemReqRemap);
2571
2572 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2573 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2574 {
2575 RT_NOREF1(uRtaddrReg);
2576 return VERR_NOT_IMPLEMENTED;
2577 }
2578
2579 return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2580}
2581
2582
2583/**
2584 * Memory access bulk (one or more 4K pages) request from a device.
2585 *
2586 * @returns VBox status code.
2587 * @param pDevIns The IOMMU device instance.
2588 * @param idDevice The device ID (bus, device, function).
2589 * @param cIovas The number of addresses being accessed.
2590 * @param pauIovas The I/O virtual addresses for each page being accessed.
2591 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2592 * @param paGCPhysSpa Where to store the translated physical addresses.
2593 *
2594 * @thread Any.
2595 */
2596static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2597 uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2598{
2599 RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
2600 return VERR_NOT_IMPLEMENTED;
2601}
2602
2603
2604/**
2605 * Memory access transaction from a device.
2606 *
2607 * @returns VBox status code.
2608 * @param pDevIns The IOMMU device instance.
2609 * @param idDevice The device ID (bus, device, function).
2610 * @param uIova The I/O virtual address being accessed.
2611 * @param cbIova The size of the access.
2612 * @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2613 * @param pGCPhysSpa Where to store the translated system physical address.
2614 * @param pcbContiguous Where to store the number of contiguous bytes translated
2615 * and permission-checked.
2616 *
2617 * @thread Any.
2618 */
2619static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2620 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2621{
2622 /* Validate. */
2623 AssertPtr(pDevIns);
2624 AssertPtr(pGCPhysSpa);
2625 AssertPtr(pcbContiguous);
2626 Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2627 Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2628
2629 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2630 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2631
2632 DMAR_LOCK(pDevIns, pThisCC);
2633 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2634 uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2635 DMAR_UNLOCK(pDevIns, pThisCC);
2636
2637 if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2638 {
2639 VTDREQTYPE enmReqType;
2640 uint8_t fReqPerm;
2641 if (fFlags & PDMIOMMU_MEM_F_READ)
2642 {
2643 enmReqType = VTDREQTYPE_READ;
2644 fReqPerm = DMAR_PERM_READ;
2645 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2646 }
2647 else
2648 {
2649 enmReqType = VTDREQTYPE_WRITE;
2650 fReqPerm = DMAR_PERM_WRITE;
2651 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2652 }
2653
2654 uint8_t const fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2655 DMARMEMREQREMAP MemReqRemap;
2656 RT_ZERO(MemReqRemap);
2657 MemReqRemap.In.AddrRange.uAddr = uIova;
2658 MemReqRemap.In.AddrRange.cb = cbIova;
2659 MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2660 MemReqRemap.In.idDevice = idDevice;
2661 MemReqRemap.In.Pasid = NIL_PCIPASID;
2662 MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2663 MemReqRemap.In.enmReqType = enmReqType;
2664 MemReqRemap.Aux.fTtm = fTtm;
2665 MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2666
2667 int rc;
2668 switch (fTtm)
2669 {
2670 case VTD_TTM_LEGACY_MODE:
2671 {
2672 rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, &MemReqRemap);
2673 break;
2674 }
2675
2676 case VTD_TTM_SCALABLE_MODE:
2677 {
2678 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2679 rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, &MemReqRemap);
2680 else
2681 {
2682 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2683 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &MemReqRemap.In, &MemReqRemap.Aux);
2684 }
2685 break;
2686 }
2687
2688 case VTD_TTM_ABORT_DMA_MODE:
2689 {
2690 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2691 if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2692 dmarDrTargetAbort(pDevIns);
2693 else
2694 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &MemReqRemap.In, &MemReqRemap.Aux);
2695 break;
2696 }
2697
2698 default:
2699 {
2700 rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2701 dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &MemReqRemap.In, &MemReqRemap.Aux);
2702 break;
2703 }
2704 }
2705
2706 *pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2707 *pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2708 return rc;
2709 }
2710
2711 *pGCPhysSpa = uIova;
2712 *pcbContiguous = cbIova;
2713 return VINF_SUCCESS;
2714}
2715
2716
2717/**
2718 * Reads an IRTE from guest memory.
2719 *
2720 * @returns VBox status code.
2721 * @param pDevIns The IOMMU device instance.
2722 * @param uIrtaReg The IRTA_REG.
2723 * @param idxIntr The interrupt index.
2724 * @param pIrte Where to store the read IRTE.
2725 */
2726static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2727{
2728 Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2729
2730 size_t const cbIrte = sizeof(*pIrte);
2731 RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2732 return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2733}
2734
2735
2736/**
2737 * Remaps the source MSI to the destination MSI given the IRTE.
2738 *
2739 * @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2740 * IRTA_REG.EIME).
2741 * @param pIrte The IRTE used for the remapping.
2742 * @param pMsiIn The source MSI (currently unused).
2743 * @param pMsiOut Where to store the remapped MSI.
2744 */
2745static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2746{
2747 NOREF(pMsiIn);
2748 uint64_t const uIrteQword0 = pIrte->au64[0];
2749
2750 /*
2751 * Let's start with a clean slate and preserve unspecified bits if the need arises.
2752 * For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2753 * but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2754 * it copies it from the source MSI.
2755 */
2756 RT_ZERO(*pMsiOut);
2757 pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2758 pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2759 pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2760 if (fExtIntrMode)
2761 {
2762 /*
2763 * Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2764 * high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2765 */
2766 uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2767 pMsiOut->Addr.n.u8DestId = idDest;
2768 pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2769 }
2770 else
2771 pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2772
2773 pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2774 pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2775 pMsiOut->Data.n.u1Level = 1;
2776 pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2777}
2778
2779
2780/**
2781 * Handles remapping of interrupts in remappable interrupt format.
2782 *
2783 * @returns VBox status code.
2784 * @param pDevIns The IOMMU device instance.
2785 * @param uIrtaReg The IRTA_REG.
2786 * @param idDevice The device ID (bus, device, function).
2787 * @param pMsiIn The source MSI.
2788 * @param pMsiOut Where to store the remapped MSI.
2789 */
2790static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2791{
2792 Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2793
2794 /* Validate reserved bits in the interrupt request. */
2795 AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2796 if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2797 {
2798 /* Compute the index into the interrupt remap table. */
2799 uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2800 uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2801 uint16_t const uHandle = uHandleLo | (uHandleHi << 15);
2802 bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2803 uint16_t const idxIntr = fSubHandleValid
2804 ? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2805 : uHandle;
2806
2807 /* Validate the index. */
2808 uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2809 if (idxIntr < cEntries)
2810 {
2811 /** @todo Implement and read IRTE from interrupt-entry cache here. */
2812
2813 /* Read the interrupt remap table entry (IRTE) at the index. */
2814 VTD_IRTE_T Irte;
2815 int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2816 if (RT_SUCCESS(rc))
2817 {
2818 /* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2819 uint64_t const uIrteQword0 = Irte.au64[0];
2820 uint64_t const uIrteQword1 = Irte.au64[1];
2821 bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2822 if (fPresent)
2823 {
2824 /* Validate reserved bits in the IRTE. */
2825 bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2826 uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2827 if ( !(uIrteQword0 & ~fQw0ValidMask)
2828 && !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2829 {
2830 /* Validate requester id (the device ID) as configured in the IRTE. */
2831 bool fSrcValid;
2832 DMARDIAG enmIrDiag;
2833 uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2834 switch (fSvt)
2835 {
2836 case VTD_IRTE_SVT_NONE:
2837 {
2838 fSrcValid = true;
2839 enmIrDiag = kDmarDiag_None;
2840 break;
2841 }
2842
2843 case VTD_IRTE_SVT_VALIDATE_MASK:
2844 {
2845 static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2846 uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2847 uint16_t const fValidMask = s_afValidMasks[idxMask];
2848 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2849 fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2850 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2851 break;
2852 }
2853
2854 case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2855 {
2856 uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2857 uint8_t const uBusFirst = RT_HI_U8(idSource);
2858 uint8_t const uBusLast = RT_LO_U8(idSource);
2859 uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2860 fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2861 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2862 break;
2863 }
2864
2865 default:
2866 {
2867 fSrcValid = false;
2868 enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2869 break;
2870 }
2871 }
2872
2873 if (fSrcValid)
2874 {
2875 uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2876 if (!fPostedMode)
2877 {
2878 dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2879 return VINF_SUCCESS;
2880 }
2881 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2882 }
2883 else
2884 dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2885 }
2886 else
2887 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2888 }
2889 else
2890 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2891 }
2892 else
2893 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2894 }
2895 else
2896 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2897 }
2898 else
2899 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr */, NULL /* pIrte */);
2900 return VERR_IOMMU_INTR_REMAP_DENIED;
2901}
2902
2903
2904/**
2905 * Interrupt remap request from a device.
2906 *
2907 * @returns VBox status code.
2908 * @param pDevIns The IOMMU device instance.
2909 * @param idDevice The device ID (bus, device, function).
2910 * @param pMsiIn The source MSI.
2911 * @param pMsiOut Where to store the remapped MSI.
2912 */
2913static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2914{
2915 /* Validate. */
2916 Assert(pDevIns);
2917 Assert(pMsiIn);
2918 Assert(pMsiOut);
2919 RT_NOREF1(idDevice);
2920
2921 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2922 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2923
2924 /* Lock and read all registers required for interrupt remapping up-front. */
2925 DMAR_LOCK(pDevIns, pThisCC);
2926 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2927 uint64_t const uIrtaReg = pThis->uIrtaReg;
2928 DMAR_UNLOCK(pDevIns, pThisCC);
2929
2930 /* Check if interrupt remapping is enabled. */
2931 if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
2932 {
2933 bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
2934 if (!fIsRemappable)
2935 {
2936 /* Handle compatibility format interrupts. */
2937 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
2938
2939 /* If EIME is enabled or CFIs are disabled, block the interrupt. */
2940 if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
2941 || !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
2942 {
2943 dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
2944 return VERR_IOMMU_INTR_REMAP_DENIED;
2945 }
2946
2947 /* Interrupt isn't subject to remapping, pass-through the interrupt. */
2948 *pMsiOut = *pMsiIn;
2949 return VINF_SUCCESS;
2950 }
2951
2952 /* Handle remappable format interrupts. */
2953 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
2954 return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
2955 }
2956
2957 /* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
2958 *pMsiOut = *pMsiIn;
2959 return VINF_SUCCESS;
2960}
2961
2962
2963/**
2964 * @callback_method_impl{FNIOMMMIONEWWRITE}
2965 */
2966static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
2967{
2968 RT_NOREF1(pvUser);
2969 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2970
2971 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2972 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
2973
2974 uint16_t const offReg = off;
2975 uint16_t const offLast = offReg + cb - 1;
2976 if (DMAR_IS_MMIO_OFF_VALID(offLast))
2977 {
2978 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2979 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2980
2981 uint64_t uPrev = 0;
2982 uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, *(uint64_t *)pv, &uPrev)
2983 : dmarRegWrite32(pThis, offReg, *(uint32_t *)pv, (uint32_t *)&uPrev);
2984 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2985 switch (off)
2986 {
2987 case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
2988 {
2989 rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
2990 break;
2991 }
2992
2993 case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
2994 case VTD_MMIO_OFF_CCMD_REG + 4:
2995 {
2996 rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
2997 break;
2998 }
2999
3000 case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
3001 {
3002 rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
3003 break;
3004 }
3005
3006 case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
3007 {
3008 rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
3009 break;
3010 }
3011
3012 case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
3013 /* VTD_MMIO_OFF_IQT_REG + 4: */ /* High 32-bits reserved. */
3014 {
3015 rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
3016 break;
3017 }
3018
3019 case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3020 /* VTD_MMIO_OFF_IQA_REG + 4: */ /* High 32-bits data. */
3021 {
3022 rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3023 break;
3024 }
3025
3026 case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3027 {
3028 rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3029 break;
3030 }
3031
3032 case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3033 {
3034 rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3035 break;
3036 }
3037
3038 case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3039 case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3040 {
3041 rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3042 break;
3043 }
3044 }
3045
3046 DMAR_UNLOCK(pDevIns, pThisCC);
3047 LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3048 return rcStrict;
3049 }
3050
3051 return VINF_IOM_MMIO_UNUSED_FF;
3052}
3053
3054
3055/**
3056 * @callback_method_impl{FNIOMMMIONEWREAD}
3057 */
3058static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
3059{
3060 RT_NOREF1(pvUser);
3061 DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3062
3063 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3064 STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3065
3066 uint16_t const offReg = off;
3067 uint16_t const offLast = offReg + cb - 1;
3068 if (DMAR_IS_MMIO_OFF_VALID(offLast))
3069 {
3070 PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3071 DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3072
3073 if (cb == 8)
3074 {
3075 *(uint64_t *)pv = dmarRegRead64(pThis, offReg);
3076 LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, *(uint64_t *)pv));
3077 }
3078 else
3079 {
3080 *(uint32_t *)pv = dmarRegRead32(pThis, offReg);
3081 LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, *(uint32_t *)pv));
3082 }
3083
3084 DMAR_UNLOCK(pDevIns, pThisCC);
3085 return VINF_SUCCESS;
3086 }
3087
3088 return VINF_IOM_MMIO_UNUSED_FF;
3089}
3090
3091
3092#ifdef IN_RING3
3093/**
3094 * Process requests in the invalidation queue.
3095 *
3096 * @param pDevIns The IOMMU device instance.
3097 * @param pvRequests The requests to process.
3098 * @param cbRequests The size of all requests (in bytes).
3099 * @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3100 * VTD_IQA_REG_DW_256_BIT).
3101 * @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3102 */
3103static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3104 uint8_t fTtm)
3105{
3106#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3107 do \
3108 { \
3109 dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3110 return; \
3111 } while (0)
3112
3113 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3114 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3115
3116 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3117 Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3118
3119 /*
3120 * The below check is redundant since we check both TTM and DW for each
3121 * descriptor type we process. However, the error reported by hardware
3122 * may differ hence this is kept commented out but not removed from the code
3123 * if we need to change this in the future.
3124 *
3125 * In our implementation, we would report the descriptor type as invalid,
3126 * while on real hardware it may report descriptor width as invalid.
3127 * The Intel VT-d spec. is not clear which error takes preceedence.
3128 */
3129#if 0
3130 /*
3131 * Verify that 128-bit descriptors are not used when operating in scalable mode.
3132 * We don't check this while software writes IQA_REG but defer it until now because
3133 * RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3134 * -IS- performed when software writes IQA_REG since it only requires checking against
3135 * immutable hardware features.
3136 */
3137 if ( fTtm != VTD_TTM_SCALABLE_MODE
3138 || fDw != VTD_IQA_REG_DW_128_BIT)
3139 { /* likely */ }
3140 else
3141 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3142#endif
3143
3144 /*
3145 * Process requests in FIFO order.
3146 */
3147 uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3148 for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3149 {
3150 uint64_t const *puDscQwords = (uint64_t const *)((uintptr_t)pvRequests + offDsc);
3151 uint64_t const uQword0 = puDscQwords[0];
3152 uint64_t const uQword1 = puDscQwords[1];
3153 uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3154 switch (fDscType)
3155 {
3156 case VTD_INV_WAIT_DSC_TYPE:
3157 {
3158 /* Validate descriptor type. */
3159 if ( fTtm == VTD_TTM_LEGACY_MODE
3160 || fDw == VTD_IQA_REG_DW_256_BIT)
3161 { /* likely */ }
3162 else
3163 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3164
3165 /* Validate reserved bits. */
3166 uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3167 ? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3168 : VTD_INV_WAIT_DSC_0_VALID_MASK;
3169 if ( !(uQword0 & ~fValidMask0)
3170 && !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3171 { /* likely */ }
3172 else
3173 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3174
3175 if (fDw == VTD_IQA_REG_DW_256_BIT)
3176 {
3177 if ( !puDscQwords[2]
3178 && !puDscQwords[3])
3179 { /* likely */ }
3180 else
3181 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3182 }
3183
3184 /* Perform status write (this must be done prior to generating the completion interrupt). */
3185 bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3186 if (fSw)
3187 {
3188 uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3189 RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3190 int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3191 AssertRC(rc);
3192 }
3193
3194 /* Generate invalidation event interrupt. */
3195 bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3196 if (fIf)
3197 {
3198 DMAR_LOCK(pDevIns, pThisR3);
3199 dmarR3InvEventRaiseInterrupt(pDevIns);
3200 DMAR_UNLOCK(pDevIns, pThisR3);
3201 }
3202
3203 STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3204 break;
3205 }
3206
3207 case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3208 case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3209 case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3210 case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3211 case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3212 case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3213 case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3214 default:
3215 {
3216 /* Stop processing further requests. */
3217 LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3218 DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3219 }
3220 }
3221 }
3222#undef DMAR_IQE_FAULT_RECORD_RET
3223}
3224
3225
3226/**
3227 * The invalidation-queue thread.
3228 *
3229 * @returns VBox status code.
3230 * @param pDevIns The IOMMU device instance.
3231 * @param pThread The command thread.
3232 */
3233static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3234{
3235 NOREF(pThread);
3236 LogFlowFunc(("\n"));
3237
3238 if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3239 return VINF_SUCCESS;
3240
3241 /*
3242 * Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3243 * This prevents trashing the heap as well as deal with out-of-memory situations
3244 * up-front while starting the VM. It also simplifies the code from having to
3245 * dynamically grow/shrink the allocation based on how software sizes the queue.
3246 * Guests normally don't alter the queue size all the time, but that's not an
3247 * assumption we can make.
3248 */
3249 uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3250 size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3251 void *pvRequests = RTMemAllocZ(cbMaxQs);
3252 AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3253
3254 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3255 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3256
3257 while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3258 {
3259 /*
3260 * Sleep until we are woken up.
3261 */
3262 {
3263 int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3264 AssertLogRelMsgReturn(RT_SUCCESS(rc) || rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3265 if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3266 break;
3267 }
3268
3269 DMAR_LOCK(pDevIns, pThisR3);
3270 if (dmarInvQueueCanProcessRequests(pThis))
3271 {
3272 uint32_t offQueueHead;
3273 uint32_t offQueueTail;
3274 bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3275 if (!fIsEmpty)
3276 {
3277 /*
3278 * Get the current queue size, descriptor width, queue base address and the
3279 * table translation mode while the lock is still held.
3280 */
3281 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3282 uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3283 uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3284 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3285 uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3286 RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3287
3288 /* Paranoia. */
3289 Assert(cbQueue <= cbMaxQs);
3290 Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3291 Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3292 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueTail & RT_BIT(4)));
3293 Assert(fDw != VTD_IQA_REG_DW_256_BIT || !(offQueueHead & RT_BIT(4)));
3294 Assert(offQueueHead < cbQueue);
3295
3296 /*
3297 * A table translation mode of "reserved" isn't valid for any descriptor type.
3298 * However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3299 * but if ESRTPS is support, we will perform a global invalidation when software
3300 * changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3301 * So caching TTM while reading all descriptors should not be a problem.
3302 *
3303 * Also, validate the queue tail offset as it's mutable by software.
3304 */
3305 if ( fTtm != VTD_TTM_RSVD
3306 && offQueueTail < cbQueue)
3307 {
3308 /* Don't hold the lock while reading (a potentially large amount of) requests */
3309 DMAR_UNLOCK(pDevIns, pThisR3);
3310
3311 int rc;
3312 uint32_t cbRequests;
3313 if (offQueueTail > offQueueHead)
3314 {
3315 /* The requests have not wrapped around, read them in one go. */
3316 cbRequests = offQueueTail - offQueueHead;
3317 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3318 }
3319 else
3320 {
3321 /* The requests have wrapped around, read forward and wrapped-around. */
3322 uint32_t const cbForward = cbQueue - offQueueHead;
3323 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3324
3325 uint32_t const cbWrapped = offQueueTail;
3326 if ( RT_SUCCESS(rc)
3327 && cbWrapped > 0)
3328 {
3329 rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3330 (void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3331 }
3332 cbRequests = cbForward + cbWrapped;
3333 }
3334
3335 /* Re-acquire the lock since we need to update device state. */
3336 DMAR_LOCK(pDevIns, pThisR3);
3337
3338 if (RT_SUCCESS(rc))
3339 {
3340 /* Indicate to software we've fetched all requests. */
3341 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3342
3343 /* Don't hold the lock while processing requests. */
3344 DMAR_UNLOCK(pDevIns, pThisR3);
3345
3346 /* Process all requests. */
3347 Assert(cbRequests <= cbQueue);
3348 dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3349
3350 /*
3351 * We've processed all requests and the lock shouldn't be held at this point.
3352 * Using 'continue' here allows us to skip re-acquiring the lock just to release
3353 * it again before going back to the thread loop. It's a bit ugly but it certainly
3354 * helps with performance.
3355 */
3356 DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3357 continue;
3358 }
3359 else
3360 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3361 }
3362 else
3363 {
3364 if (fTtm == VTD_TTM_RSVD)
3365 dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3366 else
3367 {
3368 Assert(offQueueTail >= cbQueue);
3369 dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3370 }
3371 }
3372 }
3373 }
3374 DMAR_UNLOCK(pDevIns, pThisR3);
3375 }
3376
3377 RTMemFree(pvRequests);
3378 pvRequests = NULL;
3379
3380 LogFlowFunc(("Invalidation-queue thread terminating\n"));
3381 return VINF_SUCCESS;
3382}
3383
3384
3385/**
3386 * Wakes up the invalidation-queue thread so it can respond to a state
3387 * change.
3388 *
3389 * @returns VBox status code.
3390 * @param pDevIns The IOMMU device instance.
3391 * @param pThread The invalidation-queue thread.
3392 *
3393 * @thread EMT.
3394 */
3395static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3396{
3397 RT_NOREF(pThread);
3398 LogFlowFunc(("\n"));
3399 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3400 return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3401}
3402
3403
3404/**
3405 * @callback_method_impl{FNDBGFHANDLERDEV}
3406 */
3407static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3408{
3409 PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3410 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3411 bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3412
3413 /*
3414 * We lock the device to get a consistent register state as it is
3415 * ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3416 * ones we care about here) into temporaries and release the lock ASAP.
3417 *
3418 * Order of register being read and outputted is in accordance with the
3419 * spec. for no particular reason.
3420 * See Intel VT-d spec. 10.4 "Register Descriptions".
3421 */
3422 DMAR_LOCK(pDevIns, pThisR3);
3423
3424 DMARDIAG const enmDiag = pThis->enmDiag;
3425 uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3426 uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3427 uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3428 uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3429 uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3430 uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3431 uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3432 uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3433 uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3434 uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3435 uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3436 uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3437 uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3438 uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3439 uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3440 uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3441 uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3442 uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3443 uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3444 uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3445 uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3446 uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3447 uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3448 uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3449 uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3450 uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3451 uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3452 uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3453 uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3454 uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3455 uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3456 uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3457 uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3458 uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3459 uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3460 uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3461 uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3462 uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3463
3464 DMAR_UNLOCK(pDevIns, pThisR3);
3465
3466 const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3467 pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3468 pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3469
3470 /*
3471 * Non-verbose output.
3472 */
3473 if (!fVerbose)
3474 {
3475 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3476 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3477 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3478 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3479 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3480 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3481 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3482 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3483 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3484 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3485 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3486 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3487 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3488 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3489 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3490 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3491 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3492 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3493 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3494 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3495 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3496 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3497 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3498 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3499 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3500 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3501 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3502 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3503 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3504 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3505 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3506 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3507 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3508 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3509 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3510 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3511 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3512 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3513 pHlp->pfnPrintf(pHlp, "\n");
3514 return;
3515 }
3516
3517 /*
3518 * Verbose output.
3519 */
3520 pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3521 {
3522 pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3523 pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3524 }
3525 pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3526 {
3527 uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3528 uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3529 pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3530 pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3531 pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3532 pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3533 pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3534 pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3535 pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3536 pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3537 pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3538 pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3539 pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3540 pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3541 pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3542 pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3543 pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3544 pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3545 pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3546 pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3547 pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3548 pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3549 pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3550 }
3551 pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3552 {
3553 uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3554 pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3555 pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3556 pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3557 pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3558 pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3559 pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3560 pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3561 pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3562 pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3563 pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3564 pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3565 pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3566 pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3567 pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3568 pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3569 pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3570 pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3571 pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3572 pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3573 pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3574 pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3575 pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3576 pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3577 pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3578 pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3579 pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3580 pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3581 pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3582 pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3583 }
3584 pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3585 {
3586 uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3587 pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3588 pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3589 pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3590 pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3591 pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3592 pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3593 pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3594 pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3595 pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3596 }
3597 pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3598 {
3599 uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3600 pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3601 pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3602 pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3603 pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3604 pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3605 pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3606 pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3607 pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3608 pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3609 }
3610 pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3611 {
3612 uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3613 pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3614 pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3615 }
3616 pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3617 pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3618 {
3619 pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3620 pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3621 pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3622 pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3623 pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3624 pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3625 pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3626 pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3627 }
3628 pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3629 {
3630 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3631 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3632 }
3633 pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3634 pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3635 pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3636 pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3637 pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3638 pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3639 pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3640 pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3641 pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3642 pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3643 pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3644 pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3645 {
3646 uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3647 uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3648 uint8_t const cQueuePages = 1 << fQs;
3649 pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3650 pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3651 }
3652 pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3653 {
3654 pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3655 }
3656 pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3657 {
3658 pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3659 pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3660 }
3661 pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3662 pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3663 pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3664 pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3665 {
3666 pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3667 pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3668 pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3669 }
3670 pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3671 {
3672 uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3673 uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3674 pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3675 pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3676 pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3677 }
3678 pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3679 pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3680 pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3681 pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3682 pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3683 pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3684 pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3685 pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3686 pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3687 pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3688 pHlp->pfnPrintf(pHlp, "\n");
3689}
3690
3691
3692/**
3693 * Initializes all registers in the DMAR unit.
3694 *
3695 * @param pDevIns The IOMMU device instance.
3696 */
3697static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3698{
3699 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3700
3701 /*
3702 * Wipe all registers (required on reset).
3703 */
3704 RT_ZERO(pThis->abRegs0);
3705 RT_ZERO(pThis->abRegs1);
3706
3707 /*
3708 * Initialize registers not mutable by software prior to initializing other registers.
3709 */
3710 /* VER_REG */
3711 {
3712 pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3713 | RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3714 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3715 }
3716
3717 uint8_t const fFlts = 1; /* First-level translation support. */
3718 uint8_t const fSlts = 1; /* Second-level translation support. */
3719 uint8_t const fPt = 1; /* Pass-Through support. */
3720 uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3721 uint8_t const fNest = 0; /* Nested translation support. */
3722
3723 /* CAP_REG */
3724 {
3725 uint8_t cGstPhysAddrBits;
3726 uint8_t cGstLinearAddrBits;
3727 PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3728
3729 uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3730 uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3731 uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3732 uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3733 uint8_t const fSllps = fSl2mp | (fSl2gp << 1); /* Second-level large page support. */
3734 uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3735 : X86_PAGE_2M_SHIFT)
3736 - X86_PAGE_4K_SHIFT;
3737 uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3738 uint8_t const fPsi = 1; /* Page selective invalidation. */
3739 uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3740 uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3741 uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3742 uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3743 uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3744 AssertCompile(DMAR_ND <= 6);
3745
3746 pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3747 | RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3748 | RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3749 | RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3750 | RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3751 | RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3752 | RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3753 | RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3754 | RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3755 | RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3756 | RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3757 | RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3758 | RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3759 | RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3760 | RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3761 | RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3762 | RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3763 | RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3764 | RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3765 | RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3766 | RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3767 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3768
3769 pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3770 pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3771 pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3772 }
3773
3774 /* ECAP_REG */
3775 {
3776 uint8_t const fQi = 1; /* Queued-invalidations. */
3777 uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3778 uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3779 uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3780 uint8_t const fEim = 1; /* Extended interrupt mode.*/
3781 uint8_t const fAdms = 1; /* Abort DMA mode support. */
3782 uint8_t const fErs = 0; /* Execute Request (not supported). */
3783
3784 pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3785 | RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3786 | RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3787 | RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3788 | RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3789 | RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3790 | RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3791 | RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3792 | RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3793 | RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3794 | RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3795 | RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3796 | RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3797 | RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3798 | RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3799 | RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3800 | RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3801 | RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3802 | RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3803 | RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3804 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3805 | RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3806 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3807 | RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3808 | RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3809 | RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3810 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3811 | RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3812 | RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3813 dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3814
3815 pThis->fPermValidMask = DMAR_PERM_READ | DMAR_PERM_WRITE;
3816 if (fErs)
3817 pThis->fPermValidMask = DMAR_PERM_EXE;
3818 }
3819
3820 /*
3821 * Initialize registers mutable by software.
3822 */
3823 /* FECTL_REG */
3824 {
3825 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3826 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3827 }
3828
3829 /* ICETL_REG */
3830 {
3831 uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3832 dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3833 }
3834
3835#ifdef VBOX_STRICT
3836 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3837 Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3838#endif
3839}
3840
3841
3842/**
3843 * @interface_method_impl{PDMDEVREG,pfnReset}
3844 */
3845static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
3846{
3847 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3848 LogFlowFunc(("\n"));
3849
3850 DMAR_LOCK(pDevIns, pThisR3);
3851 dmarR3RegsInit(pDevIns);
3852 DMAR_UNLOCK(pDevIns, pThisR3);
3853}
3854
3855
3856/**
3857 * @interface_method_impl{PDMDEVREG,pfnDestruct}
3858 */
3859static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
3860{
3861 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3862 PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3863 LogFlowFunc(("\n"));
3864
3865 DMAR_LOCK(pDevIns, pThisR3);
3866
3867 if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
3868 {
3869 PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
3870 pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
3871 }
3872
3873 DMAR_UNLOCK(pDevIns, pThisR3);
3874 return VINF_SUCCESS;
3875}
3876
3877
3878/**
3879 * @interface_method_impl{PDMDEVREG,pfnConstruct}
3880 */
3881static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3882{
3883 RT_NOREF(pCfg);
3884
3885 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3886 PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
3887 pThisR3->pDevInsR3 = pDevIns;
3888
3889 LogFlowFunc(("iInstance=%d\n", iInstance));
3890 NOREF(iInstance);
3891
3892 /*
3893 * Register the IOMMU with PDM.
3894 */
3895 PDMIOMMUREGR3 IommuReg;
3896 RT_ZERO(IommuReg);
3897 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3898 IommuReg.pfnMemAccess = iommuIntelMemAccess;
3899 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3900 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3901 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3902 int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3903 if (RT_FAILURE(rc))
3904 return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3905 if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3906 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3907 N_("IOMMU helper version mismatch; got %#x expected %#x"),
3908 pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3909 if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3910 return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3911 N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3912 pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3913 AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
3914 AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
3915 AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
3916 AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
3917
3918 /*
3919 * Use PDM's critical section (via helpers) for the IOMMU device.
3920 */
3921 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3922 AssertRCReturn(rc, rc);
3923
3924 /*
3925 * Initialize PCI configuration registers.
3926 */
3927 PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3928 PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3929
3930 /* Header. */
3931 PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3932 PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3933 PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3934 PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
3935 PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
3936 PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
3937 PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3938 PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3939
3940 /** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
3941 PDMPciDevSetStatus(pPciDev, 0);
3942 PDMPciDevSetCapabilityList(pPciDev, 0);
3943
3944 /** @todo VTBAR at 0x180? */
3945
3946 /*
3947 * Register the PCI function with PDM.
3948 */
3949 rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3950 AssertLogRelRCReturn(rc, rc);
3951
3952 /** @todo Register MSI but what's the MSI capability offset? */
3953#if 0
3954 /*
3955 * Register MSI support for the PCI device.
3956 * This must be done -after- registering it as a PCI device!
3957 */
3958#endif
3959
3960 /*
3961 * Register MMIO region.
3962 */
3963 AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
3964 rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
3965 IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
3966 &pThis->hMmio);
3967 AssertLogRelRCReturn(rc, rc);
3968
3969 /*
3970 * Register debugger info items.
3971 */
3972 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
3973 AssertLogRelRCReturn(rc, rc);
3974
3975#ifdef VBOX_WITH_STATISTICS
3976 /*
3977 * Statistics.
3978 */
3979 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
3980 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
3981
3982 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
3983 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
3984
3985 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
3986 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
3987 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
3988 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
3989
3990 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
3991 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
3992
3993 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
3994 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
3995
3996 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
3997 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
3998
3999 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
4000 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
4001
4002 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
4003 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
4004 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
4005 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
4006 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
4007 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
4008 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
4009 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
4010#endif
4011
4012 /*
4013 * Initialize registers.
4014 */
4015 dmarR3RegsInit(pDevIns);
4016
4017 /*
4018 * Create invalidation-queue thread and semaphore.
4019 */
4020 char szInvQueueThread[32];
4021 RT_ZERO(szInvQueueThread);
4022 RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4023 rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4024 0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4025 AssertLogRelRCReturn(rc, rc);
4026
4027 rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4028 AssertLogRelRCReturn(rc, rc);
4029
4030 /*
4031 * Log some of the features exposed to software.
4032 */
4033 uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4034 uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4035 uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4036 uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4037 uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4038 uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4039 LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4040 DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4041 LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4042 DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4043 pThis->fMgawInvMask, offFrcd, offIva));
4044 return VINF_SUCCESS;
4045}
4046
4047#else
4048
4049/**
4050 * @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4051 */
4052static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4053{
4054 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4055 PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4056 PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4057 pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4058
4059 /* We will use PDM's critical section (via helpers) for the IOMMU device. */
4060 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4061 AssertRCReturn(rc, rc);
4062
4063 /* Set up the MMIO RZ handlers. */
4064 rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4065 AssertRCReturn(rc, rc);
4066
4067 /* Set up the IOMMU RZ callbacks. */
4068 PDMIOMMUREGCC IommuReg;
4069 RT_ZERO(IommuReg);
4070 IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4071 IommuReg.idxIommu = pThis->idxIommu;
4072 IommuReg.pfnMemAccess = iommuIntelMemAccess;
4073 IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4074 IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4075 IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4076
4077 rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4078 AssertRCReturn(rc, rc);
4079 AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4080 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4081 AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4082 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4083 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4084 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4085 AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4086
4087 return VINF_SUCCESS;
4088}
4089
4090#endif
4091
4092
4093/**
4094 * The device registration structure.
4095 */
4096PDMDEVREG const g_DeviceIommuIntel =
4097{
4098 /* .u32Version = */ PDM_DEVREG_VERSION,
4099 /* .uReserved0 = */ 0,
4100 /* .szName = */ "iommu-intel",
4101 /* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RZ | PDM_DEVREG_FLAGS_NEW_STYLE,
4102 /* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4103 /* .cMaxInstances = */ 1,
4104 /* .uSharedVersion = */ 42,
4105 /* .cbInstanceShared = */ sizeof(DMAR),
4106 /* .cbInstanceCC = */ sizeof(DMARCC),
4107 /* .cbInstanceRC = */ sizeof(DMARRC),
4108 /* .cMaxPciDevices = */ 1,
4109 /* .cMaxMsixVectors = */ 0,
4110 /* .pszDescription = */ "IOMMU (Intel)",
4111#if defined(IN_RING3)
4112 /* .pszRCMod = */ "VBoxDDRC.rc",
4113 /* .pszR0Mod = */ "VBoxDDR0.r0",
4114 /* .pfnConstruct = */ iommuIntelR3Construct,
4115 /* .pfnDestruct = */ iommuIntelR3Destruct,
4116 /* .pfnRelocate = */ NULL,
4117 /* .pfnMemSetup = */ NULL,
4118 /* .pfnPowerOn = */ NULL,
4119 /* .pfnReset = */ iommuIntelR3Reset,
4120 /* .pfnSuspend = */ NULL,
4121 /* .pfnResume = */ NULL,
4122 /* .pfnAttach = */ NULL,
4123 /* .pfnDetach = */ NULL,
4124 /* .pfnQueryInterface = */ NULL,
4125 /* .pfnInitComplete = */ NULL,
4126 /* .pfnPowerOff = */ NULL,
4127 /* .pfnSoftReset = */ NULL,
4128 /* .pfnReserved0 = */ NULL,
4129 /* .pfnReserved1 = */ NULL,
4130 /* .pfnReserved2 = */ NULL,
4131 /* .pfnReserved3 = */ NULL,
4132 /* .pfnReserved4 = */ NULL,
4133 /* .pfnReserved5 = */ NULL,
4134 /* .pfnReserved6 = */ NULL,
4135 /* .pfnReserved7 = */ NULL,
4136#elif defined(IN_RING0)
4137 /* .pfnEarlyConstruct = */ NULL,
4138 /* .pfnConstruct = */ iommuIntelRZConstruct,
4139 /* .pfnDestruct = */ NULL,
4140 /* .pfnFinalDestruct = */ NULL,
4141 /* .pfnRequest = */ NULL,
4142 /* .pfnReserved0 = */ NULL,
4143 /* .pfnReserved1 = */ NULL,
4144 /* .pfnReserved2 = */ NULL,
4145 /* .pfnReserved3 = */ NULL,
4146 /* .pfnReserved4 = */ NULL,
4147 /* .pfnReserved5 = */ NULL,
4148 /* .pfnReserved6 = */ NULL,
4149 /* .pfnReserved7 = */ NULL,
4150#elif defined(IN_RC)
4151 /* .pfnConstruct = */ iommuIntelRZConstruct,
4152 /* .pfnReserved0 = */ NULL,
4153 /* .pfnReserved1 = */ NULL,
4154 /* .pfnReserved2 = */ NULL,
4155 /* .pfnReserved3 = */ NULL,
4156 /* .pfnReserved4 = */ NULL,
4157 /* .pfnReserved5 = */ NULL,
4158 /* .pfnReserved6 = */ NULL,
4159 /* .pfnReserved7 = */ NULL,
4160#else
4161# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4162#endif
4163 /* .u32VersionEnd = */ PDM_DEVREG_VERSION
4164};
4165
4166#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4167
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