DevIommuIntel.cpp@ 89553

Last change on this file since 89553 was 89553, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 Use uint16_t since the page table entity index is at most 11 bits (for all levels).
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1	/* $Id: DevIommuIntel.cpp 89553 2021-06-08 05:42:46Z vboxsync $ */
2	/** @file
3	* IOMMU - Input/Output Memory Management Unit - Intel implementation.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_IOMMU
23	#include "VBoxDD.h"
24	#include "DevIommuIntel.h"
25
26	#include <iprt/mem.h>
27	#include <iprt/string.h>
28
29
30	/*********************************************************************************************************************************
31	* Defined Constants And Macros *
32	*********************************************************************************************************************************/
33	/** Gets the low uint32_t of a uint64_t or something equivalent.
34	*
35	* This is suitable for casting constants outside code (since RT_LO_U32 can't be
36	* used as it asserts for correctness when compiling on certain compilers). */
37	#define DMAR_LO_U32(a) (uint32_t)(UINT32_MAX & (a))
38
39	/** Gets the high uint32_t of a uint64_t or something equivalent.
40	*
41	* This is suitable for casting constants outside code (since RT_HI_U32 can't be
42	* used as it asserts for correctness when compiling on certain compilers). */
43	#define DMAR_HI_U32(a) (uint32_t)((a) >> 32)
44
45	/** Asserts MMIO access' offset and size are valid or returns appropriate error
46	* code suitable for returning from MMIO access handlers. */
47	#define DMAR_ASSERT_MMIO_ACCESS_RET(a_off, a_cb) \
48	do { \
49	AssertReturn((a_cb) == 4 \|\| (a_cb) == 8, VINF_IOM_MMIO_UNUSED_FF); \
50	AssertReturn(!((a_off) & ((a_cb) - 1)), VINF_IOM_MMIO_UNUSED_FF); \
51	} while (0)
52
53	/** Checks if the MMIO offset is valid. */
54	#define DMAR_IS_MMIO_OFF_VALID(a_off) ( (a_off) < DMAR_MMIO_GROUP_0_OFF_END \
55	\|\| (a_off) - DMAR_MMIO_GROUP_1_OFF_FIRST < DMAR_MMIO_GROUP_1_SIZE)
56
57	/** Acquires the DMAR lock but returns with the given busy error code on failure. */
58	#define DMAR_LOCK_RET(a_pDevIns, a_pThisCC, a_rcBusy) \
59	do { \
60	if ((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), (a_rcBusy)) == VINF_SUCCESS) \
61	{ /* likely */ } \
62	else \
63	return (a_rcBusy); \
64	} while (0)
65
66	/** Acquires the DMAR lock (not expected to fail). */
67	#ifdef IN_RING3
68	# define DMAR_LOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VERR_IGNORED)
69	#else
70	# define DMAR_LOCK(a_pDevIns, a_pThisCC) \
71	do { \
72	int const rcLock = (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLock((a_pDevIns), VINF_SUCCESS); \
73	AssertRC(rcLock); \
74	} while (0)
75	#endif
76
77	/** Release the DMAR lock. */
78	#define DMAR_UNLOCK(a_pDevIns, a_pThisCC) (a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnUnlock(a_pDevIns)
79
80	/** Asserts that the calling thread owns the DMAR lock. */
81	#define DMAR_ASSERT_LOCK_IS_OWNER(a_pDevIns, a_pThisCC) \
82	do { \
83	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns)); \
84	RT_NOREF1(a_pThisCC); \
85	} while (0)
86
87	/** Asserts that the calling thread does not own the DMAR lock. */
88	#define DMAR_ASSERT_LOCK_IS_NOT_OWNER(a_pDevIns, a_pThisCC) \
89	do { \
90	Assert((a_pThisCC)->CTX_SUFF(pIommuHlp)->pfnLockIsOwner(a_pDevIns) == false); \
91	RT_NOREF1(a_pThisCC); \
92	} while (0)
93
94	/** The number of fault recording registers our implementation supports.
95	* Normal guest operation shouldn't trigger faults anyway, so we only support the
96	* minimum number of registers (which is 1).
97	*
98	* See Intel VT-d spec. 10.4.2 "Capability Register" (CAP_REG.NFR). */
99	#define DMAR_FRCD_REG_COUNT UINT32_C(1)
100
101	/** Offset of first register in group 0. */
102	#define DMAR_MMIO_GROUP_0_OFF_FIRST VTD_MMIO_OFF_VER_REG
103	/** Offset of last register in group 0 (inclusive). */
104	#define DMAR_MMIO_GROUP_0_OFF_LAST VTD_MMIO_OFF_MTRR_PHYSMASK9_REG
105	/** Last valid offset in group 0 (exclusive). */
106	#define DMAR_MMIO_GROUP_0_OFF_END (DMAR_MMIO_GROUP_0_OFF_LAST + 8 /* sizeof MTRR_PHYSMASK9_REG */)
107	/** Size of the group 0 (in bytes). */
108	#define DMAR_MMIO_GROUP_0_SIZE (DMAR_MMIO_GROUP_0_OFF_END - DMAR_MMIO_GROUP_0_OFF_FIRST)
109	/*< Implementation-specific MMIO offset of IVA_REG. /
110	#define DMAR_MMIO_OFF_IVA_REG 0xe50
111	/*< Implementation-specific MMIO offset of IOTLB_REG. /
112	#define DMAR_MMIO_OFF_IOTLB_REG 0xe58
113	/*< Implementation-specific MMIO offset of FRCD_LO_REG. /
114	#define DMAR_MMIO_OFF_FRCD_LO_REG 0xe70
115	/*< Implementation-specific MMIO offset of FRCD_HI_REG. /
116	#define DMAR_MMIO_OFF_FRCD_HI_REG 0xe78
117	AssertCompile(!(DMAR_MMIO_OFF_FRCD_LO_REG & 0xf));
118
119	/** Offset of first register in group 1. */
120	#define DMAR_MMIO_GROUP_1_OFF_FIRST VTD_MMIO_OFF_VCCAP_REG
121	/** Offset of last register in group 1 (inclusive). */
122	#define DMAR_MMIO_GROUP_1_OFF_LAST (DMAR_MMIO_OFF_FRCD_LO_REG + 8) * DMAR_FRCD_REG_COUNT
123	/** Last valid offset in group 1 (exclusive). */
124	#define DMAR_MMIO_GROUP_1_OFF_END (DMAR_MMIO_GROUP_1_OFF_LAST + 8 /* sizeof FRCD_HI_REG */)
125	/** Size of the group 1 (in bytes). */
126	#define DMAR_MMIO_GROUP_1_SIZE (DMAR_MMIO_GROUP_1_OFF_END - DMAR_MMIO_GROUP_1_OFF_FIRST)
127
128	/** DMAR implementation's major version number (exposed to software).
129	* We report 6 as the major version since we support queued-invalidations as
130	* software may make assumptions based on that.
131	*
132	* See Intel VT-d spec. 10.4.7 "Context Command Register" (CCMD_REG.CAIG). */
133	#define DMAR_VER_MAJOR 6
134	/** DMAR implementation's minor version number (exposed to software). */
135	#define DMAR_VER_MINOR 0
136
137	/** Number of domain supported (0=16, 1=64, 2=256, 3=1K, 4=4K, 5=16K, 6=64K,
138	* 7=Reserved). */
139	#define DMAR_ND 6
140
141	/** @name DMAR_PERM_XXX: DMA request permissions.
142	* The order of R, W, X bits is important as it corresponds to those bits in
143	* page-table entries.
144	*
145	* @{ */
146	/** DMA request permission: Read. */
147	#define DMAR_PERM_READ RT_BIT(0)
148	/** DMA request permission: Write. */
149	#define DMAR_PERM_WRITE RT_BIT(1)
150	/** DMA request permission: Execute (ER). */
151	#define DMAR_PERM_EXE RT_BIT(2)
152	/** DMA request permission: Supervisor privilege (PR). */
153	#define DMAR_PERM_PRIV RT_BIT(3)
154	/** DMA request permissions: All. */
155	#define DMAR_PERM_ALL (DMAR_PERM_READ \| DMAR_PERM_WRITE \| DMAR_PERM_EXE \| DMAR_PERM_PRIV)
156	/** @} */
157
158	/** Release log prefix string. */
159	#define DMAR_LOG_PFX "Intel-IOMMU"
160	/** The current saved state version. */
161	#define DMAR_SAVED_STATE_VERSION 1
162
163
164	/*********************************************************************************************************************************
165	* Structures and Typedefs *
166	*********************************************************************************************************************************/
167	/**
168	* DMAR error diagnostics.
169	* Sorted alphabetically so it's easier to add and locate items, no other reason.
170	*
171	* @note Members of this enum are used as array indices, so no gaps in enum
172	* values are not allowed. Update g_apszDmarDiagDesc when you modify
173	* fields in this enum.
174	*/
175	typedef enum
176	{
177	/* No error, this must be zero! */
178	kDmarDiag_None = 0,
179
180	/* Address Translation Faults. */
181	kDmarDiag_At_Lm_CtxEntry_Not_Present,
182	kDmarDiag_At_Lm_CtxEntry_Read_Failed,
183	kDmarDiag_At_Lm_CtxEntry_Rsvd,
184	kDmarDiag_At_Lm_Pt_At_Block,
185	kDmarDiag_At_Lm_Pt_Aw_Invalid,
186	kDmarDiag_At_Lm_RootEntry_Not_Present,
187	kDmarDiag_At_Lm_RootEntry_Read_Failed,
188	kDmarDiag_At_Lm_RootEntry_Rsvd,
189	kDmarDiag_At_Lm_Tt_Invalid,
190	kDmarDiag_At_Lm_Ut_At_Block,
191	kDmarDiag_At_Lm_Ut_Aw_Invalid,
192	kDmarDiag_At_Rta_Adms_Not_Supported,
193	kDmarDiag_At_Rta_Rsvd,
194	kDmarDiag_At_Rta_Smts_Not_Supported,
195	kDmarDiag_At_Xm_AddrIn_Invalid,
196	kDmarDiag_At_Xm_AddrOut_Invalid,
197	kDmarDiag_At_Xm_Perm_Denied,
198	kDmarDiag_At_Xm_Pte_Rsvd,
199	kDmarDiag_At_Xm_Pte_Sllps_Invalid,
200	kDmarDiag_At_Xm_Read_Pte_Failed,
201	kDmarDiag_At_Xm_Slpptr_Read_Failed,
202
203	/* CCMD_REG faults. */
204	kDmarDiag_CcmdReg_Not_Supported,
205	kDmarDiag_CcmdReg_Qi_Enabled,
206	kDmarDiag_CcmdReg_Ttm_Invalid,
207
208	/* IQA_REG faults. */
209	kDmarDiag_IqaReg_Dsc_Fetch_Error,
210	kDmarDiag_IqaReg_Dw_128_Invalid,
211	kDmarDiag_IqaReg_Dw_256_Invalid,
212
213	/* Invalidation Queue Error Info. */
214	kDmarDiag_Iqei_Dsc_Type_Invalid,
215	kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd,
216	kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd,
217	kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid,
218	kDmarDiag_Iqei_Ttm_Rsvd,
219
220	/* IQT_REG faults. */
221	kDmarDiag_IqtReg_Qt_Invalid,
222	kDmarDiag_IqtReg_Qt_Not_Aligned,
223
224	/* Interrupt Remapping Faults. */
225	kDmarDiag_Ir_Cfi_Blocked,
226	kDmarDiag_Ir_Rfi_Intr_Index_Invalid,
227	kDmarDiag_Ir_Rfi_Irte_Mode_Invalid,
228	kDmarDiag_Ir_Rfi_Irte_Not_Present,
229	kDmarDiag_Ir_Rfi_Irte_Read_Failed,
230	kDmarDiag_Ir_Rfi_Irte_Rsvd,
231	kDmarDiag_Ir_Rfi_Irte_Svt_Bus,
232	kDmarDiag_Ir_Rfi_Irte_Svt_Masked,
233	kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd,
234	kDmarDiag_Ir_Rfi_Rsvd,
235
236	/* Member for determining array index limit. */
237	kDmarDiag_End,
238
239	/* Usual 32-bit type size hack. */
240	kDmarDiag_32Bit_Hack = 0x7fffffff
241	} DMARDIAG;
242	AssertCompileSize(DMARDIAG, 4);
243
244	/** DMAR diagnostic enum description expansion.
245	* The below construct ensures typos in the input to this macro are caught
246	* during compile time. */
247	#define DMARDIAG_DESC(a_Name) RT_CONCAT(kDmarDiag_, a_Name) < kDmarDiag_End ? RT_STR(a_Name) : "Ignored"
248
249	/** DMAR diagnostics description for members in DMARDIAG. */
250	static const char *const g_apszDmarDiagDesc[] =
251	{
252	DMARDIAG_DESC(None ),
253
254	/* Address Translation Faults. */
255	DMARDIAG_DESC(At_Lm_CtxEntry_Not_Present ),
256	DMARDIAG_DESC(At_Lm_CtxEntry_Read_Failed ),
257	DMARDIAG_DESC(At_Lm_CtxEntry_Rsvd ),
258	DMARDIAG_DESC(At_Lm_Pt_At_Block ),
259	DMARDIAG_DESC(At_Lm_Pt_Aw_Invalid ),
260	DMARDIAG_DESC(At_Lm_RootEntry_Not_Present),
261	DMARDIAG_DESC(At_Lm_RootEntry_Read_Failed),
262	DMARDIAG_DESC(At_Lm_RootEntry_Rsvd ),
263	DMARDIAG_DESC(At_Lm_Tt_Invalid ),
264	DMARDIAG_DESC(At_Lm_Ut_At_Block ),
265	DMARDIAG_DESC(At_Lm_Ut_Aw_Invalid ),
266	DMARDIAG_DESC(At_Rta_Adms_Not_Supported ),
267	DMARDIAG_DESC(At_Rta_Rsvd ),
268	DMARDIAG_DESC(At_Rta_Smts_Not_Supported ),
269	DMARDIAG_DESC(At_Xm_AddrIn_Invalid ),
270	DMARDIAG_DESC(At_Xm_AddrOut_Invalid ),
271	DMARDIAG_DESC(At_Xm_Perm_Denied ),
272	DMARDIAG_DESC(At_Xm_Pte_Rsvd ),
273	DMARDIAG_DESC(At_Xm_Pte_Sllps_Invalid ),
274	DMARDIAG_DESC(At_Xm_Read_Pte_Failed ),
275	DMARDIAG_DESC(At_Xm_Slpptr_Read_Failed ),
276
277	/* CCMD_REG faults. */
278	DMARDIAG_DESC(CcmdReg_Not_Supported ),
279	DMARDIAG_DESC(CcmdReg_Qi_Enabled ),
280	DMARDIAG_DESC(CcmdReg_Ttm_Invalid ),
281
282	/* IQA_REG faults. */
283	DMARDIAG_DESC(IqaReg_Dsc_Fetch_Error ),
284	DMARDIAG_DESC(IqaReg_Dw_128_Invalid ),
285	DMARDIAG_DESC(IqaReg_Dw_256_Invalid ),
286
287	/* Invalidation Queue Error Info. */
288	DMARDIAG_DESC(Iqei_Dsc_Type_Invalid ),
289	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_0_1_Rsvd ),
290	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_2_3_Rsvd ),
291	DMARDIAG_DESC(Iqei_Inv_Wait_Dsc_Invalid ),
292	DMARDIAG_DESC(Iqei_Ttm_Rsvd ),
293
294	/* IQT_REG faults. */
295	DMARDIAG_DESC(IqtReg_Qt_Invalid ),
296	DMARDIAG_DESC(IqtReg_Qt_Not_Aligned ),
297
298	/* Interrupt remapping faults. */
299	DMARDIAG_DESC(Ir_Cfi_Blocked ),
300	DMARDIAG_DESC(Ir_Rfi_Intr_Index_Invalid ),
301	DMARDIAG_DESC(Ir_Rfi_Irte_Mode_Invalid ),
302	DMARDIAG_DESC(Ir_Rfi_Irte_Not_Present ),
303	DMARDIAG_DESC(Ir_Rfi_Irte_Read_Failed ),
304	DMARDIAG_DESC(Ir_Rfi_Irte_Rsvd ),
305	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Bus ),
306	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Masked ),
307	DMARDIAG_DESC(Ir_Rfi_Irte_Svt_Rsvd ),
308	DMARDIAG_DESC(Ir_Rfi_Rsvd ),
309	/* kDmarDiag_End */
310	};
311	AssertCompile(RT_ELEMENTS(g_apszDmarDiagDesc) == kDmarDiag_End);
312	#undef DMARDIAG_DESC
313
314	/**
315	* The shared DMAR device state.
316	*/
317	typedef struct DMAR
318	{
319	/** IOMMU device index. */
320	uint32_t idxIommu;
321	/** DMAR magic. */
322	uint32_t u32Magic;
323
324	/** Registers (group 0). */
325	uint8_t abRegs0[DMAR_MMIO_GROUP_0_SIZE];
326	/** Registers (group 1). */
327	uint8_t abRegs1[DMAR_MMIO_GROUP_1_SIZE];
328
329	/** @name Lazily activated registers.
330	* These are the active values for lazily activated registers. Software is free to
331	* modify the actual register values while remapping/translation is enabled but they
332	* take effect only when explicitly signaled by software, hence we need to hold the
333	* active values separately.
334	* @{ */
335	/** Currently active IRTA_REG. */
336	uint64_t uIrtaReg;
337	/** Currently active RTADDR_REG. */
338	uint64_t uRtaddrReg;
339	/** @} */
340
341	/** @name Register copies for a tiny bit faster and more convenient access.
342	* @{ */
343	/** Copy of VER_REG. */
344	uint8_t uVerReg;
345	/** Alignment. */
346	uint8_t abPadding[7];
347	/** Copy of CAP_REG. */
348	uint64_t fCapReg;
349	/** Copy of ECAP_REG. */
350	uint64_t fExtCapReg;
351	/** @} */
352
353	/** Host-address width (HAW) base address mask. */
354	uint64_t fHawBaseMask;
355	/** Maximum guest-address width (MGAW) invalid address mask. */
356	uint64_t fMgawInvMask;
357	/** Maximum supported paging level (3, 4 or 5). */
358	uint8_t cMaxPagingLevel;
359	/** DMA request valid permissions mask. */
360	uint8_t fPermValidMask;
361
362	/** The event semaphore the invalidation-queue thread waits on. */
363	SUPSEMEVENT hEvtInvQueue;
364	/** Padding. */
365	uint32_t uPadding0;
366	/** Error diagnostic. */
367	DMARDIAG enmDiag;
368	/** The MMIO handle. */
369	IOMMMIOHANDLE hMmio;
370
371	#ifdef VBOX_WITH_STATISTICS
372	STAMCOUNTER StatMmioReadR3; /*< Number of MMIO reads in R3. /
373	STAMCOUNTER StatMmioReadRZ; /*< Number of MMIO reads in RZ. /
374	STAMCOUNTER StatMmioWriteR3; /*< Number of MMIO writes in R3. /
375	STAMCOUNTER StatMmioWriteRZ; /*< Number of MMIO writes in RZ. /
376
377	STAMCOUNTER StatMsiRemapCfiR3; /*< Number of compatibility-format interrupts remap requests in R3. /
378	STAMCOUNTER StatMsiRemapCfiRZ; /*< Number of compatibility-format interrupts remap requests in RZ. /
379	STAMCOUNTER StatMsiRemapRfiR3; /*< Number of remappable-format interrupts remap requests in R3. /
380	STAMCOUNTER StatMsiRemapRfiRZ; /*< Number of remappable-format interrupts remap requests in RZ. /
381
382	STAMCOUNTER StatMemReadR3; /*< Number of memory read translation requests in R3. /
383	STAMCOUNTER StatMemReadRZ; /*< Number of memory read translation requests in RZ. /
384	STAMCOUNTER StatMemWriteR3; /*< Number of memory write translation requests in R3. /
385	STAMCOUNTER StatMemWriteRZ; /*< Number of memory write translation requests in RZ. /
386
387	STAMCOUNTER StatMemBulkReadR3; /*< Number of memory read bulk translation requests in R3. /
388	STAMCOUNTER StatMemBulkReadRZ; /*< Number of memory read bulk translation requests in RZ. /
389	STAMCOUNTER StatMemBulkWriteR3; /*< Number of memory write bulk translation requests in R3. /
390	STAMCOUNTER StatMemBulkWriteRZ; /*< Number of memory write bulk translation requests in RZ. /
391
392	STAMCOUNTER StatCcInvDsc; /*< Number of Context-cache descriptors processed. /
393	STAMCOUNTER StatIotlbInvDsc; /*< Number of IOTLB descriptors processed. /
394	STAMCOUNTER StatDevtlbInvDsc; /*< Number of Device-TLB descriptors processed. /
395	STAMCOUNTER StatIecInvDsc; /*< Number of Interrupt-Entry cache descriptors processed. /
396	STAMCOUNTER StatInvWaitDsc; /*< Number of Invalidation wait descriptors processed. /
397	STAMCOUNTER StatPasidIotlbInvDsc; /*< Number of PASID-based IOTLB descriptors processed. /
398	STAMCOUNTER StatPasidCacheInvDsc; /*< Number of PASID-cache descriptors processed. /
399	STAMCOUNTER StatPasidDevtlbInvDsc; /*< Number of PASID-based device-TLB descriptors processed. /
400	#endif
401	} DMAR;
402	/** Pointer to the DMAR device state. */
403	typedef DMAR *PDMAR;
404	/** Pointer to the const DMAR device state. */
405	typedef DMAR const *PCDMAR;
406	AssertCompileMemberAlignment(DMAR, abRegs0, 8);
407	AssertCompileMemberAlignment(DMAR, abRegs1, 8);
408
409	/**
410	* The ring-3 DMAR device state.
411	*/
412	typedef struct DMARR3
413	{
414	/** Device instance. */
415	PPDMDEVINSR3 pDevInsR3;
416	/** The IOMMU helper. */
417	R3PTRTYPE(PCPDMIOMMUHLPR3) pIommuHlpR3;
418	/** The invalidation-queue thread. */
419	R3PTRTYPE(PPDMTHREAD) pInvQueueThread;
420	} DMARR3;
421	/** Pointer to the ring-3 DMAR device state. */
422	typedef DMARR3 *PDMARR3;
423	/** Pointer to the const ring-3 DMAR device state. */
424	typedef DMARR3 const *PCDMARR3;
425
426	/**
427	* The ring-0 DMAR device state.
428	*/
429	typedef struct DMARR0
430	{
431	/** Device instance. */
432	PPDMDEVINSR0 pDevInsR0;
433	/** The IOMMU helper. */
434	R0PTRTYPE(PCPDMIOMMUHLPR0) pIommuHlpR0;
435	} DMARR0;
436	/** Pointer to the ring-0 IOMMU device state. */
437	typedef DMARR0 *PDMARR0;
438	/** Pointer to the const ring-0 IOMMU device state. */
439	typedef DMARR0 const *PCDMARR0;
440
441	/**
442	* The raw-mode DMAR device state.
443	*/
444	typedef struct DMARRC
445	{
446	/** Device instance. */
447	PPDMDEVINSRC pDevInsRC;
448	/** The IOMMU helper. */
449	RCPTRTYPE(PCPDMIOMMUHLPRC) pIommuHlpRC;
450	} DMARRC;
451	/** Pointer to the raw-mode DMAR device state. */
452	typedef DMARRC *PDMARRC;
453	/** Pointer to the const raw-mode DMAR device state. */
454	typedef DMARRC const *PCIDMARRC;
455
456	/** The DMAR device state for the current context. */
457	typedef CTX_SUFF(DMAR) DMARCC;
458	/** Pointer to the DMAR device state for the current context. */
459	typedef CTX_SUFF(PDMAR) PDMARCC;
460	/** Pointer to the const DMAR device state for the current context. */
461	typedef CTX_SUFF(PDMAR) const PCDMARCC;
462
463	/**
464	* DMAR originated events that generate interrupts.
465	*/
466	typedef enum DMAREVENTTYPE
467	{
468	/** Invalidation completion event. */
469	DMAREVENTTYPE_INV_COMPLETE = 0,
470	/** Fault event. */
471	DMAREVENTTYPE_FAULT
472	} DMAREVENTTYPE;
473
474	/**
475	* I/O Page.
476	*/
477	typedef struct DMARIOPAGE
478	{
479	/** The base DMA address of a page. */
480	RTGCPHYS GCPhysBase;
481	/** The page shift. */
482	uint8_t cShift;
483	/** The permissions of this page (DMAR_PERM_XXX). */
484	uint8_t fPerm;
485	} DMARIOPAGE;
486	/** Pointer to an I/O page. */
487	typedef DMARIOPAGE *PDMARIOPAGE;
488	/** Pointer to a const I/O address range. */
489	typedef DMARIOPAGE const *PCDMARIOPAGE;
490
491	/**
492	* I/O Address Range.
493	*/
494	typedef struct DMARIOADDRRANGE
495	{
496	/** The starting DMA address of this range. */
497	uint64_t uAddr;
498	/** The size of the range (in bytes). */
499	size_t cb;
500	/** The permissions of this range (DMAR_PERM_XXX). */
501	uint8_t fPerm;
502	} DMARIOADDRRANGE;
503	/** Pointer to an I/O address range. */
504	typedef DMARIOADDRRANGE *PDMARIOADDRRANGE;
505	/** Pointer to a const I/O address range. */
506	typedef DMARIOADDRRANGE const *PCDMARIOADDRRANGE;
507
508	/**
509	* DMA Memory Request (Input).
510	*/
511	typedef struct DMARMEMREQIN
512	{
513	/** The address range being accessed. */
514	DMARIOADDRRANGE AddrRange;
515	/** The source device ID (bus, device, function). */
516	uint16_t idDevice;
517	/** The PASID if present (can be NIL_PCIPASID). */
518	PCIPASID Pasid;
519	/* The address translation type. */
520	PCIADDRTYPE enmAddrType;
521	/** The request type. */
522	VTDREQTYPE enmReqType;
523	} DMARMEMREQIN;
524	/** Pointer to a DMA memory request input. */
525	typedef DMARMEMREQIN *PDMARMEMREQIN;
526	/** Pointer to a const DMA memory input. */
527	typedef DMARMEMREQIN const *PCDMARMEMREQIN;
528
529	/**
530	* DMA Memory Request (Output).
531	*/
532	typedef struct DMARMEMREQOUT
533	{
534	/** The address range of the translated region. */
535	DMARIOADDRRANGE AddrRange;
536	/** The domain ID of the translated region. */
537	uint16_t idDomain;
538	} DMARMEMREQOUT;
539	/** Pointer to a DMA memory request output. */
540	typedef DMARMEMREQOUT *PDMARMEMREQOUT;
541	/** Pointer to a const DMA memory request output. */
542	typedef DMARMEMREQOUT const *PCDMARMEMREQOUT;
543
544	/**
545	* DMA Memory Request (Auxiliary Info).
546	* These get updated and used as part of the translation process.
547	*/
548	typedef struct DMARMEMREQAUX
549	{
550	/** The table translation mode (VTD_TTM_XXX). */
551	uint8_t fTtm;
552	/** The fault processing disabled (FPD) bit. */
553	uint8_t fFpd;
554	/** The paging level of the translation. */
555	uint8_t cPagingLevel;
556	uint8_t afPadding[5];
557	/** The address of the first-level page-table. */
558	uint64_t GCPhysFlPt;
559	/** The address of second-level page-table. */
560	uint64_t GCPhysSlPt;
561	} DMARMEMREQAUX;
562	/** Pointer to a DMA memory request output. */
563	typedef DMARMEMREQAUX *PDMARMEMREQAUX;
564	/** Pointer to a const DMA memory request output. */
565	typedef DMARMEMREQAUX const *PCDMARMEMREQAUX;
566
567	/**
568	* DMA Memory Request Remapping Information.
569	*/
570	typedef struct DMARMEMREQREMAP
571	{
572	/** The DMA memory request input. */
573	DMARMEMREQIN In;
574	/** DMA memory request auxiliary information. */
575	DMARMEMREQAUX Aux;
576	/** The DMA memory request output. */
577	DMARMEMREQOUT Out;
578	} DMARMEMREQREMAP;
579	/** Pointer to a DMA remap info. */
580	typedef DMARMEMREQREMAP *PDMARMEMREQREMAP;
581	/** Pointer to a const DMA remap info. */
582	typedef DMARMEMREQREMAP const *PCDMARMEMREQREMAP;
583
584	/**
585	* Callback function to lookup a DMA address.
586	*
587	* @returns VBox status code.
588	* @param pDevIns The IOMMU device instance.
589	* @param pMemReqIn The DMA memory request input.
590	* @param pMemReqAux The DMA memory request auxiliary info.
591	* @param pIoPageOut Where to store the output of the lookup.
592	*/
593	typedef DECLCALLBACKTYPE(int, FNDMADDRLOOKUP,(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
594	PDMARIOPAGE pIoPageOut));
595	/** Pointer to a DMA address-lookup function. */
596	typedef FNDMADDRLOOKUP *PFNDMADDRLOOKUP;
597
598
599	/*********************************************************************************************************************************
600	* Global Variables *
601	*********************************************************************************************************************************/
602	/**
603	* Read-write masks for DMAR registers (group 0).
604	*/
605	static uint32_t const g_au32RwMasks0[] =
606	{
607	/* Offset Register Low High */
608	/* 0x000 VER_REG */ VTD_VER_REG_RW_MASK,
609	/* 0x004 Reserved */ 0,
610	/* 0x008 CAP_REG */ DMAR_LO_U32(VTD_CAP_REG_RW_MASK), DMAR_HI_U32(VTD_CAP_REG_RW_MASK),
611	/* 0x010 ECAP_REG */ DMAR_LO_U32(VTD_ECAP_REG_RW_MASK), DMAR_HI_U32(VTD_ECAP_REG_RW_MASK),
612	/* 0x018 GCMD_REG */ VTD_GCMD_REG_RW_MASK,
613	/* 0x01c GSTS_REG */ VTD_GSTS_REG_RW_MASK,
614	/* 0x020 RTADDR_REG */ DMAR_LO_U32(VTD_RTADDR_REG_RW_MASK), DMAR_HI_U32(VTD_RTADDR_REG_RW_MASK),
615	/* 0x028 CCMD_REG */ DMAR_LO_U32(VTD_CCMD_REG_RW_MASK), DMAR_HI_U32(VTD_CCMD_REG_RW_MASK),
616	/* 0x030 Reserved */ 0,
617	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW_MASK,
618	/* 0x038 FECTL_REG */ VTD_FECTL_REG_RW_MASK,
619	/* 0x03c FEDATA_REG */ VTD_FEDATA_REG_RW_MASK,
620	/* 0x040 FEADDR_REG */ VTD_FEADDR_REG_RW_MASK,
621	/* 0x044 FEUADDR_REG */ VTD_FEUADDR_REG_RW_MASK,
622	/* 0x048 Reserved */ 0, 0,
623	/* 0x050 Reserved */ 0, 0,
624	/* 0x058 AFLOG_REG */ DMAR_LO_U32(VTD_AFLOG_REG_RW_MASK), DMAR_HI_U32(VTD_AFLOG_REG_RW_MASK),
625	/* 0x060 Reserved */ 0,
626	/* 0x064 PMEN_REG / 0, / RO as we don't support PLMR and PHMR. */
627	/* 0x068 PLMBASE_REG / 0, / RO as we don't support PLMR. */
628	/* 0x06c PLMLIMIT_REG / 0, / RO as we don't support PLMR. */
629	/* 0x070 PHMBASE_REG / 0, 0, / RO as we don't support PHMR. */
630	/* 0x078 PHMLIMIT_REG / 0, 0, / RO as we don't support PHMR. */
631	/* 0x080 IQH_REG */ DMAR_LO_U32(VTD_IQH_REG_RW_MASK), DMAR_HI_U32(VTD_IQH_REG_RW_MASK),
632	/* 0x088 IQT_REG */ DMAR_LO_U32(VTD_IQT_REG_RW_MASK), DMAR_HI_U32(VTD_IQT_REG_RW_MASK),
633	/* 0x090 IQA_REG */ DMAR_LO_U32(VTD_IQA_REG_RW_MASK), DMAR_HI_U32(VTD_IQA_REG_RW_MASK),
634	/* 0x098 Reserved */ 0,
635	/* 0x09c ICS_REG */ VTD_ICS_REG_RW_MASK,
636	/* 0x0a0 IECTL_REG */ VTD_IECTL_REG_RW_MASK,
637	/* 0x0a4 IEDATA_REG */ VTD_IEDATA_REG_RW_MASK,
638	/* 0x0a8 IEADDR_REG */ VTD_IEADDR_REG_RW_MASK,
639	/* 0x0ac IEUADDR_REG */ VTD_IEUADDR_REG_RW_MASK,
640	/* 0x0b0 IQERCD_REG */ DMAR_LO_U32(VTD_IQERCD_REG_RW_MASK), DMAR_HI_U32(VTD_IQERCD_REG_RW_MASK),
641	/* 0x0b8 IRTA_REG */ DMAR_LO_U32(VTD_IRTA_REG_RW_MASK), DMAR_HI_U32(VTD_IRTA_REG_RW_MASK),
642	/* 0x0c0 PQH_REG */ DMAR_LO_U32(VTD_PQH_REG_RW_MASK), DMAR_HI_U32(VTD_PQH_REG_RW_MASK),
643	/* 0x0c8 PQT_REG */ DMAR_LO_U32(VTD_PQT_REG_RW_MASK), DMAR_HI_U32(VTD_PQT_REG_RW_MASK),
644	/* 0x0d0 PQA_REG */ DMAR_LO_U32(VTD_PQA_REG_RW_MASK), DMAR_HI_U32(VTD_PQA_REG_RW_MASK),
645	/* 0x0d8 Reserved */ 0,
646	/* 0x0dc PRS_REG */ VTD_PRS_REG_RW_MASK,
647	/* 0x0e0 PECTL_REG */ VTD_PECTL_REG_RW_MASK,
648	/* 0x0e4 PEDATA_REG */ VTD_PEDATA_REG_RW_MASK,
649	/* 0x0e8 PEADDR_REG */ VTD_PEADDR_REG_RW_MASK,
650	/* 0x0ec PEUADDR_REG */ VTD_PEUADDR_REG_RW_MASK,
651	/* 0x0f0 Reserved */ 0, 0,
652	/* 0x0f8 Reserved */ 0, 0,
653	/* 0x100 MTRRCAP_REG */ DMAR_LO_U32(VTD_MTRRCAP_REG_RW_MASK), DMAR_HI_U32(VTD_MTRRCAP_REG_RW_MASK),
654	/* 0x108 MTRRDEF_REG / 0, 0, / RO as we don't support MTS. */
655	/* 0x110 Reserved */ 0, 0,
656	/* 0x118 Reserved */ 0, 0,
657	/* 0x120 MTRR_FIX64_00000_REG / 0, 0, / RO as we don't support MTS. */
658	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
659	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
660	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
661	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
662	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
663	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
664	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
665	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
666	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
667	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
668	/* 0x178 Reserved */ 0, 0,
669	/* 0x180 MTRR_PHYSBASE0_REG / 0, 0, / RO as we don't support MTS. */
670	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
671	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
672	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
673	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
674	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
675	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
676	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
677	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
678	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
679	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
680	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
681	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
682	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
683	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
684	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
685	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
686	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
687	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
688	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
689	};
690	AssertCompile(sizeof(g_au32RwMasks0) == DMAR_MMIO_GROUP_0_SIZE);
691
692	/**
693	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 0).
694	*/
695	static uint32_t const g_au32Rw1cMasks0[] =
696	{
697	/* Offset Register Low High */
698	/* 0x000 VER_REG */ 0,
699	/* 0x004 Reserved */ 0,
700	/* 0x008 CAP_REG */ 0, 0,
701	/* 0x010 ECAP_REG */ 0, 0,
702	/* 0x018 GCMD_REG */ 0,
703	/* 0x01c GSTS_REG */ 0,
704	/* 0x020 RTADDR_REG */ 0, 0,
705	/* 0x028 CCMD_REG */ 0, 0,
706	/* 0x030 Reserved */ 0,
707	/* 0x034 FSTS_REG */ VTD_FSTS_REG_RW1C_MASK,
708	/* 0x038 FECTL_REG */ 0,
709	/* 0x03c FEDATA_REG */ 0,
710	/* 0x040 FEADDR_REG */ 0,
711	/* 0x044 FEUADDR_REG */ 0,
712	/* 0x048 Reserved */ 0, 0,
713	/* 0x050 Reserved */ 0, 0,
714	/* 0x058 AFLOG_REG */ 0, 0,
715	/* 0x060 Reserved */ 0,
716	/* 0x064 PMEN_REG */ 0,
717	/* 0x068 PLMBASE_REG */ 0,
718	/* 0x06c PLMLIMIT_REG */ 0,
719	/* 0x070 PHMBASE_REG */ 0, 0,
720	/* 0x078 PHMLIMIT_REG */ 0, 0,
721	/* 0x080 IQH_REG */ 0, 0,
722	/* 0x088 IQT_REG */ 0, 0,
723	/* 0x090 IQA_REG */ 0, 0,
724	/* 0x098 Reserved */ 0,
725	/* 0x09c ICS_REG */ VTD_ICS_REG_RW1C_MASK,
726	/* 0x0a0 IECTL_REG */ 0,
727	/* 0x0a4 IEDATA_REG */ 0,
728	/* 0x0a8 IEADDR_REG */ 0,
729	/* 0x0ac IEUADDR_REG */ 0,
730	/* 0x0b0 IQERCD_REG */ 0, 0,
731	/* 0x0b8 IRTA_REG */ 0, 0,
732	/* 0x0c0 PQH_REG */ 0, 0,
733	/* 0x0c8 PQT_REG */ 0, 0,
734	/* 0x0d0 PQA_REG */ 0, 0,
735	/* 0x0d8 Reserved */ 0,
736	/* 0x0dc PRS_REG */ 0,
737	/* 0x0e0 PECTL_REG */ 0,
738	/* 0x0e4 PEDATA_REG */ 0,
739	/* 0x0e8 PEADDR_REG */ 0,
740	/* 0x0ec PEUADDR_REG */ 0,
741	/* 0x0f0 Reserved */ 0, 0,
742	/* 0x0f8 Reserved */ 0, 0,
743	/* 0x100 MTRRCAP_REG */ 0, 0,
744	/* 0x108 MTRRDEF_REG */ 0, 0,
745	/* 0x110 Reserved */ 0, 0,
746	/* 0x118 Reserved */ 0, 0,
747	/* 0x120 MTRR_FIX64_00000_REG */ 0, 0,
748	/* 0x128 MTRR_FIX16K_80000_REG */ 0, 0,
749	/* 0x130 MTRR_FIX16K_A0000_REG */ 0, 0,
750	/* 0x138 MTRR_FIX4K_C0000_REG */ 0, 0,
751	/* 0x140 MTRR_FIX4K_C8000_REG */ 0, 0,
752	/* 0x148 MTRR_FIX4K_D0000_REG */ 0, 0,
753	/* 0x150 MTRR_FIX4K_D8000_REG */ 0, 0,
754	/* 0x158 MTRR_FIX4K_E0000_REG */ 0, 0,
755	/* 0x160 MTRR_FIX4K_E8000_REG */ 0, 0,
756	/* 0x168 MTRR_FIX4K_F0000_REG */ 0, 0,
757	/* 0x170 MTRR_FIX4K_F8000_REG */ 0, 0,
758	/* 0x178 Reserved */ 0, 0,
759	/* 0x180 MTRR_PHYSBASE0_REG */ 0, 0,
760	/* 0x188 MTRR_PHYSMASK0_REG */ 0, 0,
761	/* 0x190 MTRR_PHYSBASE1_REG */ 0, 0,
762	/* 0x198 MTRR_PHYSMASK1_REG */ 0, 0,
763	/* 0x1a0 MTRR_PHYSBASE2_REG */ 0, 0,
764	/* 0x1a8 MTRR_PHYSMASK2_REG */ 0, 0,
765	/* 0x1b0 MTRR_PHYSBASE3_REG */ 0, 0,
766	/* 0x1b8 MTRR_PHYSMASK3_REG */ 0, 0,
767	/* 0x1c0 MTRR_PHYSBASE4_REG */ 0, 0,
768	/* 0x1c8 MTRR_PHYSMASK4_REG */ 0, 0,
769	/* 0x1d0 MTRR_PHYSBASE5_REG */ 0, 0,
770	/* 0x1d8 MTRR_PHYSMASK5_REG */ 0, 0,
771	/* 0x1e0 MTRR_PHYSBASE6_REG */ 0, 0,
772	/* 0x1e8 MTRR_PHYSMASK6_REG */ 0, 0,
773	/* 0x1f0 MTRR_PHYSBASE7_REG */ 0, 0,
774	/* 0x1f8 MTRR_PHYSMASK7_REG */ 0, 0,
775	/* 0x200 MTRR_PHYSBASE8_REG */ 0, 0,
776	/* 0x208 MTRR_PHYSMASK8_REG */ 0, 0,
777	/* 0x210 MTRR_PHYSBASE9_REG */ 0, 0,
778	/* 0x218 MTRR_PHYSMASK9_REG */ 0, 0,
779	};
780	AssertCompile(sizeof(g_au32Rw1cMasks0) == DMAR_MMIO_GROUP_0_SIZE);
781
782	/**
783	* Read-write masks for DMAR registers (group 1).
784	*/
785	static uint32_t const g_au32RwMasks1[] =
786	{
787	/* Offset Register Low High */
788	/* 0xe00 VCCAP_REG */ DMAR_LO_U32(VTD_VCCAP_REG_RW_MASK), DMAR_HI_U32(VTD_VCCAP_REG_RW_MASK),
789	/* 0xe08 VCMD_EO_REG */ DMAR_LO_U32(VTD_VCMD_EO_REG_RW_MASK), DMAR_HI_U32(VTD_VCMD_EO_REG_RW_MASK),
790	/* 0xe10 VCMD_REG / 0, 0, / RO: VCS not supported. */
791	/* 0xe18 VCMDRSVD_REG */ 0, 0,
792	/* 0xe20 VCRSP_REG / 0, 0, / RO: VCS not supported. */
793	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
794	/* 0xe30 Reserved */ 0, 0,
795	/* 0xe38 Reserved */ 0, 0,
796	/* 0xe40 Reserved */ 0, 0,
797	/* 0xe48 Reserved */ 0, 0,
798	/* 0xe50 IVA_REG */ DMAR_LO_U32(VTD_IVA_REG_RW_MASK), DMAR_HI_U32(VTD_IVA_REG_RW_MASK),
799	/* 0xe58 IOTLB_REG */ DMAR_LO_U32(VTD_IOTLB_REG_RW_MASK), DMAR_HI_U32(VTD_IOTLB_REG_RW_MASK),
800	/* 0xe60 Reserved */ 0, 0,
801	/* 0xe68 Reserved */ 0, 0,
802	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW_MASK),
803	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW_MASK),
804	};
805	AssertCompile(sizeof(g_au32RwMasks1) == DMAR_MMIO_GROUP_1_SIZE);
806	AssertCompile((DMAR_MMIO_OFF_FRCD_LO_REG - DMAR_MMIO_GROUP_1_OFF_FIRST) + DMAR_FRCD_REG_COUNT * 2 * sizeof(uint64_t) );
807
808	/**
809	* Read-only Status, Write-1-to-clear masks for DMAR registers (group 1).
810	*/
811	static uint32_t const g_au32Rw1cMasks1[] =
812	{
813	/* Offset Register Low High */
814	/* 0xe00 VCCAP_REG */ 0, 0,
815	/* 0xe08 VCMD_EO_REG */ 0, 0,
816	/* 0xe10 VCMD_REG */ 0, 0,
817	/* 0xe18 VCMDRSVD_REG */ 0, 0,
818	/* 0xe20 VCRSP_REG */ 0, 0,
819	/* 0xe28 VCRSPRSVD_REG */ 0, 0,
820	/* 0xe30 Reserved */ 0, 0,
821	/* 0xe38 Reserved */ 0, 0,
822	/* 0xe40 Reserved */ 0, 0,
823	/* 0xe48 Reserved */ 0, 0,
824	/* 0xe50 IVA_REG */ 0, 0,
825	/* 0xe58 IOTLB_REG */ 0, 0,
826	/* 0xe60 Reserved */ 0, 0,
827	/* 0xe68 Reserved */ 0, 0,
828	/* 0xe70 FRCD_REG_LO */ DMAR_LO_U32(VTD_FRCD_REG_LO_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_LO_RW1C_MASK),
829	/* 0xe78 FRCD_REG_HI */ DMAR_LO_U32(VTD_FRCD_REG_HI_RW1C_MASK), DMAR_HI_U32(VTD_FRCD_REG_HI_RW1C_MASK),
830	};
831	AssertCompile(sizeof(g_au32Rw1cMasks1) == DMAR_MMIO_GROUP_1_SIZE);
832
833	/** Array of RW masks for each register group. */
834	static uint8_t const g_apbRwMasks[] = { (uint8_t )&g_au32RwMasks0[0], (uint8_t *)&g_au32RwMasks1[0] };
835
836	/** Array of RW1C masks for each register group. */
837	static uint8_t const g_apbRw1cMasks[] = { (uint8_t )&g_au32Rw1cMasks0[0], (uint8_t *)&g_au32Rw1cMasks1[0] };
838
839	/* Masks arrays must be identical in size (even bounds checking code assumes this). */
840	AssertCompile(sizeof(g_apbRw1cMasks) == sizeof(g_apbRwMasks));
841
842	/** Array of valid domain-ID bits. */
843	static uint16_t const g_auNdMask[] = { 0xf, 0x3f, 0xff, 0x3ff, 0xfff, 0x3fff, 0xffff, 0 };
844	AssertCompile(RT_ELEMENTS(g_auNdMask) >= DMAR_ND);
845
846
847	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
848	/** @todo Add IOMMU struct size/alignment verification, see
849	* Devices/testcase/Makefile.kmk and
850	* Devices/testcase/tstDeviceStructSize[RC].cpp */
851
852	/**
853	* Returns the supported adjusted guest-address width (SAGAW) given the maximum
854	* guest address width (MGAW).
855	*
856	* @returns The CAP_REG.SAGAW value.
857	* @param uMgaw The CAP_REG.MGAW value.
858	*/
859	static uint8_t vtdCapRegGetSagaw(uint8_t uMgaw)
860	{
861	/*
862	* It doesn't make sense to me that a CPU (or IOMMU hardware) will ever support
863	* 5-level paging but not 4 or 3-level paging. So smaller page-table levels
864	* are always OR'ed in below.
865	*
866	* The bit values below (57, 48, 39 bits) represents the levels of page-table walks
867	* for 4KB base page size (5-level, 4-level and 3-level paging respectively).
868	*
869	* See Intel VT-d spec. 10.4.2 "Capability Register".
870	*/
871	++uMgaw;
872	uint8_t const fSagaw = uMgaw >= 57 ? RT_BIT(3) \| RT_BIT(2) \| RT_BIT(1)
873	: uMgaw >= 48 ? RT_BIT(2) \| RT_BIT(1)
874	: uMgaw >= 39 ? RT_BIT(1)
875	: 0;
876	return fSagaw;
877	}
878
879
880	/**
881	* Returns the maximum supported paging level given the supported adjusted
882	* guest-address width (SAGAW) field.
883	*
884	* @returns The highest paging level supported, 0 if invalid.
885	* @param fSagaw The CAP_REG.SAGAW value.
886	*/
887	static uint8_t vtdCapRegGetMaxPagingLevel(uint8_t fSagaw)
888	{
889	uint8_t const cMaxPagingLevel = fSagaw & RT_BIT(3) ? 5
890	: fSagaw & RT_BIT(2) ? 4
891	: fSagaw & RT_BIT(1) ? 3
892	: 0;
893	return cMaxPagingLevel;
894	}
895
896
897	/**
898	* Returns whether the interrupt remapping (IR) fault is qualified or not.
899	*
900	* @returns @c true if qualified, @c false otherwise.
901	* @param enmIrFault The interrupt remapping fault condition.
902	*/
903	static bool vtdIrFaultIsQualified(VTDIRFAULT enmIrFault)
904	{
905	switch (enmIrFault)
906	{
907	case VTDIRFAULT_IRTE_NOT_PRESENT:
908	case VTDIRFAULT_IRTE_PRESENT_RSVD:
909	case VTDIRFAULT_IRTE_PRESENT_INVALID:
910	case VTDIRFAULT_PID_READ_FAILED:
911	case VTDIRFAULT_PID_RSVD:
912	return true;
913	default:
914	return false;
915	}
916	}
917
918
919	/**
920	* Returns table translation mode's descriptive name.
921	*
922	* @returns The descriptive name.
923	* @param uTtm The RTADDR_REG.TTM value.
924	*/
925	static const char* vtdRtaddrRegGetTtmDesc(uint8_t uTtm)
926	{
927	Assert(!(uTtm & 3));
928	static const char* s_apszTtmNames[] =
929	{
930	"Legacy Mode",
931	"Scalable Mode",
932	"Reserved",
933	"Abort-DMA Mode"
934	};
935	return s_apszTtmNames[uTtm & (RT_ELEMENTS(s_apszTtmNames) - 1)];
936	}
937
938
939	/**
940	* Gets the index of the group the register belongs to given its MMIO offset.
941	*
942	* @returns The group index.
943	* @param offReg The MMIO offset of the register.
944	* @param cbReg The size of the access being made (for bounds checking on
945	* debug builds).
946	*/
947	DECLINLINE(uint8_t) dmarRegGetGroupIndex(uint16_t offReg, uint8_t cbReg)
948	{
949	uint16_t const offLast = offReg + cbReg - 1;
950	AssertCompile(DMAR_MMIO_GROUP_0_OFF_FIRST == 0);
951	AssertMsg(DMAR_IS_MMIO_OFF_VALID(offLast), ("off=%#x cb=%u\n", offReg, cbReg));
952	return !(offLast < DMAR_MMIO_GROUP_0_OFF_END);
953	}
954
955
956	/**
957	* Gets the group the register belongs to given its MMIO offset.
958	*
959	* @returns Pointer to the first element of the register group.
960	* @param pThis The shared DMAR device state.
961	* @param offReg The MMIO offset of the register.
962	* @param cbReg The size of the access being made (for bounds checking on
963	* debug builds).
964	* @param pIdxGroup Where to store the index of the register group the register
965	* belongs to.
966	*/
967	DECLINLINE(uint8_t ) dmarRegGetGroup(PDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
968	{
969	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
970	uint8_t *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
971	return apbRegs[*pIdxGroup];
972	}
973
974
975	/**
976	* Const/read-only version of dmarRegGetGroup.
977	*
978	* @copydoc dmarRegGetGroup
979	*/
980	DECLINLINE(uint8_t const) dmarRegGetGroupRo(PCDMAR pThis, uint16_t offReg, uint8_t cbReg, uint8_t pIdxGroup)
981	{
982	*pIdxGroup = dmarRegGetGroupIndex(offReg, cbReg);
983	uint8_t const *apbRegs[] = { &pThis->abRegs0[0], &pThis->abRegs1[0] };
984	return apbRegs[*pIdxGroup];
985	}
986
987
988	/**
989	* Writes a 32-bit register with the exactly the supplied value.
990	*
991	* @param pThis The shared DMAR device state.
992	* @param offReg The MMIO offset of the register.
993	* @param uReg The 32-bit value to write.
994	*/
995	static void dmarRegWriteRaw32(PDMAR pThis, uint16_t offReg, uint32_t uReg)
996	{
997	uint8_t idxGroup;
998	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint32_t), &idxGroup);
999	NOREF(idxGroup);
1000	(uint32_t )(pabRegs + offReg) = uReg;
1001	}
1002
1003
1004	/**
1005	* Writes a 64-bit register with the exactly the supplied value.
1006	*
1007	* @param pThis The shared DMAR device state.
1008	* @param offReg The MMIO offset of the register.
1009	* @param uReg The 64-bit value to write.
1010	*/
1011	static void dmarRegWriteRaw64(PDMAR pThis, uint16_t offReg, uint64_t uReg)
1012	{
1013	uint8_t idxGroup;
1014	uint8_t *pabRegs = dmarRegGetGroup(pThis, offReg, sizeof(uint64_t), &idxGroup);
1015	NOREF(idxGroup);
1016	(uint64_t )(pabRegs + offReg) = uReg;
1017	}
1018
1019
1020	/**
1021	* Reads a 32-bit register with exactly the value it contains.
1022	*
1023	* @returns The raw register value.
1024	* @param pThis The shared DMAR device state.
1025	* @param offReg The MMIO offset of the register.
1026	*/
1027	static uint32_t dmarRegReadRaw32(PCDMAR pThis, uint16_t offReg)
1028	{
1029	uint8_t idxGroup;
1030	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1031	NOREF(idxGroup);
1032	return (uint32_t )(pabRegs + offReg);
1033	}
1034
1035
1036	/**
1037	* Reads a 64-bit register with exactly the value it contains.
1038	*
1039	* @returns The raw register value.
1040	* @param pThis The shared DMAR device state.
1041	* @param offReg The MMIO offset of the register.
1042	*/
1043	static uint64_t dmarRegReadRaw64(PCDMAR pThis, uint16_t offReg)
1044	{
1045	uint8_t idxGroup;
1046	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1047	NOREF(idxGroup);
1048	return (uint64_t )(pabRegs + offReg);
1049	}
1050
1051
1052	/**
1053	* Reads a 32-bit register with exactly the value it contains along with their
1054	* corresponding masks
1055	*
1056	* @param pThis The shared DMAR device state.
1057	* @param offReg The MMIO offset of the register.
1058	* @param puReg Where to store the raw 32-bit register value.
1059	* @param pfRwMask Where to store the RW mask corresponding to this register.
1060	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1061	*/
1062	static void dmarRegReadRaw32Ex(PCDMAR pThis, uint16_t offReg, uint32_t puReg, uint32_t pfRwMask, uint32_t *pfRw1cMask)
1063	{
1064	uint8_t idxGroup;
1065	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint32_t), &idxGroup);
1066	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1067	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1068	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1069	puReg = (uint32_t *)(pabRegs + offReg);
1070	pfRwMask = (uint32_t *)(pabRwMasks + offReg);
1071	pfRw1cMask = (uint32_t *)(pabRw1cMasks + offReg);
1072	}
1073
1074
1075	/**
1076	* Reads a 64-bit register with exactly the value it contains along with their
1077	* corresponding masks.
1078	*
1079	* @param pThis The shared DMAR device state.
1080	* @param offReg The MMIO offset of the register.
1081	* @param puReg Where to store the raw 64-bit register value.
1082	* @param pfRwMask Where to store the RW mask corresponding to this register.
1083	* @param pfRw1cMask Where to store the RW1C mask corresponding to this register.
1084	*/
1085	static void dmarRegReadRaw64Ex(PCDMAR pThis, uint16_t offReg, uint64_t puReg, uint64_t pfRwMask, uint64_t *pfRw1cMask)
1086	{
1087	uint8_t idxGroup;
1088	uint8_t const *pabRegs = dmarRegGetGroupRo(pThis, offReg, sizeof(uint64_t), &idxGroup);
1089	Assert(idxGroup < RT_ELEMENTS(g_apbRwMasks));
1090	uint8_t const *pabRwMasks = g_apbRwMasks[idxGroup];
1091	uint8_t const *pabRw1cMasks = g_apbRw1cMasks[idxGroup];
1092	puReg = (uint64_t *)(pabRegs + offReg);
1093	pfRwMask = (uint64_t *)(pabRwMasks + offReg);
1094	pfRw1cMask = (uint64_t *)(pabRw1cMasks + offReg);
1095	}
1096
1097
1098	/**
1099	* Writes a 32-bit register as it would be when written by software.
1100	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1101	*
1102	* @returns The value that's actually written to the register.
1103	* @param pThis The shared DMAR device state.
1104	* @param offReg The MMIO offset of the register.
1105	* @param uReg The 32-bit value to write.
1106	* @param puPrev Where to store the register value prior to writing.
1107	*/
1108	static uint32_t dmarRegWrite32(PDMAR pThis, uint16_t offReg, uint32_t uReg, uint32_t *puPrev)
1109	{
1110	/* Read current value from the 32-bit register. */
1111	uint32_t uCurReg;
1112	uint32_t fRwMask;
1113	uint32_t fRw1cMask;
1114	dmarRegReadRaw32Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1115	*puPrev = uCurReg;
1116
1117	uint32_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1118	uint32_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1119	uint32_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1120	uint32_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1121
1122	/* Write new value to the 32-bit register. */
1123	dmarRegWriteRaw32(pThis, offReg, uNewReg);
1124	return uNewReg;
1125	}
1126
1127
1128	/**
1129	* Writes a 64-bit register as it would be when written by software.
1130	* This will preserve read-only bits, mask off reserved bits and clear RW1C bits.
1131	*
1132	* @returns The value that's actually written to the register.
1133	* @param pThis The shared DMAR device state.
1134	* @param offReg The MMIO offset of the register.
1135	* @param uReg The 64-bit value to write.
1136	* @param puPrev Where to store the register value prior to writing.
1137	*/
1138	static uint64_t dmarRegWrite64(PDMAR pThis, uint16_t offReg, uint64_t uReg, uint64_t *puPrev)
1139	{
1140	/* Read current value from the 64-bit register. */
1141	uint64_t uCurReg;
1142	uint64_t fRwMask;
1143	uint64_t fRw1cMask;
1144	dmarRegReadRaw64Ex(pThis, offReg, &uCurReg, &fRwMask, &fRw1cMask);
1145	*puPrev = uCurReg;
1146
1147	uint64_t const fRoBits = uCurReg & ~fRwMask; /* Preserve current read-only and reserved bits. */
1148	uint64_t const fRwBits = uReg & fRwMask; /* Merge newly written read/write bits. */
1149	uint64_t const fRw1cBits = uReg & fRw1cMask; /* Clear 1s written to RW1C bits. */
1150	uint64_t const uNewReg = (fRoBits \| fRwBits) & ~fRw1cBits;
1151
1152	/* Write new value to the 64-bit register. */
1153	dmarRegWriteRaw64(pThis, offReg, uNewReg);
1154	return uNewReg;
1155	}
1156
1157
1158	/**
1159	* Reads a 32-bit register as it would be when read by software.
1160	*
1161	* @returns The register value.
1162	* @param pThis The shared DMAR device state.
1163	* @param offReg The MMIO offset of the register.
1164	*/
1165	static uint32_t dmarRegRead32(PCDMAR pThis, uint16_t offReg)
1166	{
1167	return dmarRegReadRaw32(pThis, offReg);
1168	}
1169
1170
1171	/**
1172	* Reads a 64-bit register as it would be when read by software.
1173	*
1174	* @returns The register value.
1175	* @param pThis The shared DMAR device state.
1176	* @param offReg The MMIO offset of the register.
1177	*/
1178	static uint64_t dmarRegRead64(PCDMAR pThis, uint16_t offReg)
1179	{
1180	return dmarRegReadRaw64(pThis, offReg);
1181	}
1182
1183
1184	/**
1185	* Modifies a 32-bit register.
1186	*
1187	* @param pThis The shared DMAR device state.
1188	* @param offReg The MMIO offset of the register.
1189	* @param fAndMask The AND mask (applied first).
1190	* @param fOrMask The OR mask.
1191	* @remarks This does NOT apply RO or RW1C masks while modifying the
1192	* register.
1193	*/
1194	static void dmarRegChangeRaw32(PDMAR pThis, uint16_t offReg, uint32_t fAndMask, uint32_t fOrMask)
1195	{
1196	uint32_t uReg = dmarRegReadRaw32(pThis, offReg);
1197	uReg = (uReg & fAndMask) \| fOrMask;
1198	dmarRegWriteRaw32(pThis, offReg, uReg);
1199	}
1200
1201
1202	/**
1203	* Modifies a 64-bit register.
1204	*
1205	* @param pThis The shared DMAR device state.
1206	* @param offReg The MMIO offset of the register.
1207	* @param fAndMask The AND mask (applied first).
1208	* @param fOrMask The OR mask.
1209	* @remarks This does NOT apply RO or RW1C masks while modifying the
1210	* register.
1211	*/
1212	static void dmarRegChangeRaw64(PDMAR pThis, uint16_t offReg, uint64_t fAndMask, uint64_t fOrMask)
1213	{
1214	uint64_t uReg = dmarRegReadRaw64(pThis, offReg);
1215	uReg = (uReg & fAndMask) \| fOrMask;
1216	dmarRegWriteRaw64(pThis, offReg, uReg);
1217	}
1218
1219
1220	/**
1221	* Checks if the invalidation-queue is empty.
1222	*
1223	* Extended version which optionally returns the current queue head and tail
1224	* offsets.
1225	*
1226	* @returns @c true if empty, @c false otherwise.
1227	* @param pThis The shared DMAR device state.
1228	* @param poffQh Where to store the queue head offset. Optional, can be NULL.
1229	* @param poffQt Where to store the queue tail offset. Optional, can be NULL.
1230	*/
1231	static bool dmarInvQueueIsEmptyEx(PCDMAR pThis, uint32_t poffQh, uint32_t poffQt)
1232	{
1233	/* Read only the low-32 bits of the queue head and queue tail as high bits are all RsvdZ.*/
1234	uint32_t const uIqtReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQT_REG);
1235	uint32_t const uIqhReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IQH_REG);
1236
1237	/* Don't bother masking QT, QH since other bits are RsvdZ. */
1238	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1239	Assert(!(uIqhReg & ~VTD_BF_IQH_REG_QH_MASK));
1240	if (poffQh)
1241	*poffQh = uIqhReg;
1242	if (poffQt)
1243	*poffQt = uIqtReg;
1244	return uIqtReg == uIqhReg;
1245	}
1246
1247
1248	/**
1249	* Checks if the invalidation-queue is empty.
1250	*
1251	* @returns @c true if empty, @c false otherwise.
1252	* @param pThis The shared DMAR device state.
1253	*/
1254	static bool dmarInvQueueIsEmpty(PCDMAR pThis)
1255	{
1256	return dmarInvQueueIsEmptyEx(pThis, NULL /* poffQh /, NULL / poffQt */);
1257	}
1258
1259
1260	/**
1261	* Checks if the invalidation-queue is capable of processing requests.
1262	*
1263	* @returns @c true if the invalidation-queue can process requests, @c false
1264	* otherwise.
1265	* @param pThis The shared DMAR device state.
1266	*/
1267	static bool dmarInvQueueCanProcessRequests(PCDMAR pThis)
1268	{
1269	/* Check if queued-invalidation is enabled. */
1270	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1271	if (uGstsReg & VTD_BF_GSTS_REG_QIES_MASK)
1272	{
1273	/* Check if there are no invalidation-queue or timeout errors. */
1274	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1275	if (!(uFstsReg & (VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_ITE_MASK)))
1276	return true;
1277	}
1278	return false;
1279	}
1280
1281
1282	/**
1283	* Wakes up the invalidation-queue thread if there are requests to be processed.
1284	*
1285	* @param pDevIns The IOMMU device instance.
1286	*/
1287	static void dmarInvQueueThreadWakeUpIfNeeded(PPDMDEVINS pDevIns)
1288	{
1289	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1290	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1291	Log4Func(("\n"));
1292
1293	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1294
1295	if ( dmarInvQueueCanProcessRequests(pThis)
1296	&& !dmarInvQueueIsEmpty(pThis))
1297	{
1298	Log4Func(("Signaling the invalidation-queue thread\n"));
1299	PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
1300	}
1301	}
1302
1303
1304	/**
1305	* Raises an event on behalf of the DMAR.
1306	*
1307	* These are events that are generated by the DMAR itself (like faults and
1308	* invalidation completion notifications).
1309	*
1310	* @param pDevIns The IOMMU device instance.
1311	* @param enmEventType The DMAR event type.
1312	*
1313	* @remarks The DMAR lock must be held while calling this function.
1314	*/
1315	static void dmarEventRaiseInterrupt(PPDMDEVINS pDevIns, DMAREVENTTYPE enmEventType)
1316	{
1317	uint16_t offCtlReg;
1318	uint32_t fIntrMaskedMask;
1319	uint32_t fIntrPendingMask;
1320	uint16_t offMsiAddrLoReg;
1321	uint16_t offMsiAddrHiReg;
1322	uint16_t offMsiDataReg;
1323	switch (enmEventType)
1324	{
1325	case DMAREVENTTYPE_INV_COMPLETE:
1326	{
1327	offCtlReg = VTD_MMIO_OFF_IECTL_REG;
1328	fIntrMaskedMask = VTD_BF_IECTL_REG_IM_MASK;
1329	fIntrPendingMask = VTD_BF_IECTL_REG_IP_MASK;
1330	offMsiAddrLoReg = VTD_MMIO_OFF_IEADDR_REG;
1331	offMsiAddrHiReg = VTD_MMIO_OFF_IEUADDR_REG;
1332	offMsiDataReg = VTD_MMIO_OFF_IEDATA_REG;
1333	break;
1334	}
1335
1336	case DMAREVENTTYPE_FAULT:
1337	{
1338	offCtlReg = VTD_MMIO_OFF_FECTL_REG;
1339	fIntrMaskedMask = VTD_BF_FECTL_REG_IM_MASK;
1340	fIntrPendingMask = VTD_BF_FECTL_REG_IP_MASK;
1341	offMsiAddrLoReg = VTD_MMIO_OFF_FEADDR_REG;
1342	offMsiAddrHiReg = VTD_MMIO_OFF_FEUADDR_REG;
1343	offMsiDataReg = VTD_MMIO_OFF_FEDATA_REG;
1344	break;
1345	}
1346
1347	default:
1348	{
1349	/* Shouldn't ever happen. */
1350	AssertMsgFailedReturnVoid(("DMAR event type %#x unknown!\n", enmEventType));
1351	}
1352	}
1353
1354	/* Check if software has masked the interrupt. */
1355	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1356	uint32_t uCtlReg = dmarRegReadRaw32(pThis, offCtlReg);
1357	if (!(uCtlReg & fIntrMaskedMask))
1358	{
1359	/*
1360	* Interrupt is unmasked, raise it.
1361	* Interrupts generated by the DMAR have trigger mode and level as 0.
1362	* See Intel spec. 5.1.6 "Remapping Hardware Event Interrupt Programming".
1363	*/
1364	MSIMSG Msi;
1365	Msi.Addr.au32[0] = dmarRegReadRaw32(pThis, offMsiAddrLoReg);
1366	Msi.Addr.au32[1] = (pThis->fExtCapReg & VTD_BF_ECAP_REG_EIM_MASK) ? dmarRegReadRaw32(pThis, offMsiAddrHiReg) : 0;
1367	Msi.Data.u32 = dmarRegReadRaw32(pThis, offMsiDataReg);
1368	Assert(Msi.Data.n.u1Level == 0);
1369	Assert(Msi.Data.n.u1TriggerMode == 0);
1370
1371	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1372	pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi(pDevIns, &Msi, 0 /* uTagSrc */);
1373
1374	/* Clear interrupt pending bit. */
1375	uCtlReg &= ~fIntrPendingMask;
1376	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1377	}
1378	else
1379	{
1380	/* Interrupt is masked, set the interrupt pending bit. */
1381	uCtlReg \|= fIntrPendingMask;
1382	dmarRegWriteRaw32(pThis, offCtlReg, uCtlReg);
1383	}
1384	}
1385
1386
1387	/**
1388	* Raises an interrupt in response to a fault event.
1389	*
1390	* @param pDevIns The IOMMU device instance.
1391	*
1392	* @remarks This assumes the caller has already set the required status bits in the
1393	* FSTS_REG (namely one or more of PPF, PFO, IQE, ICE or ITE bits).
1394	*/
1395	static void dmarFaultEventRaiseInterrupt(PPDMDEVINS pDevIns)
1396	{
1397	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1398	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1399	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1400
1401	#ifdef RT_STRICT
1402	{
1403	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1404	uint32_t const fFaultMask = VTD_BF_FSTS_REG_PPF_MASK \| VTD_BF_FSTS_REG_PFO_MASK
1405	/* \| VTD_BF_FSTS_REG_APF_MASK \| VTD_BF_FSTS_REG_AFO_MASK / / AFL not supported */
1406	/* \| VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK / / Device-TLBs not supported */
1407	\| VTD_BF_FSTS_REG_IQE_MASK;
1408	Assert(uFstsReg & fFaultMask);
1409	}
1410	#endif
1411	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1412	}
1413
1414
1415	#ifdef IN_RING3
1416	/**
1417	* Raises an interrupt in response to an invalidation (complete) event.
1418	*
1419	* @param pDevIns The IOMMU device instance.
1420	*/
1421	static void dmarR3InvEventRaiseInterrupt(PPDMDEVINS pDevIns)
1422	{
1423	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1424	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1425	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1426
1427	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
1428	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1429	{
1430	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_ICS_REG, UINT32_MAX, VTD_BF_ICS_REG_IWC_MASK);
1431	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1432	}
1433	}
1434	#endif /* IN_RING3 */
1435
1436
1437	/**
1438	* Checks if a primary fault can be recorded.
1439	*
1440	* @returns @c true if the fault can be recorded, @c false otherwise.
1441	* @param pDevIns The IOMMU device instance.
1442	* @param pThis The shared DMAR device state.
1443	*
1444	* @remarks Warning: This function has side-effects wrt the DMAR register state. Do
1445	* NOT call it unless there is a fault condition!
1446	*/
1447	static bool dmarPrimaryFaultCanRecord(PPDMDEVINS pDevIns, PDMAR pThis)
1448	{
1449	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1450	DMAR_ASSERT_LOCK_IS_OWNER(pDevIns, pThisCC);
1451
1452	uint32_t uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
1453	if (uFstsReg & VTD_BF_FSTS_REG_PFO_MASK)
1454	return false;
1455
1456	/*
1457	* If we add more FRCD registers, we'll have to loop through them here.
1458	* Since we support only one FRCD_REG, we don't support "compression of multiple faults",
1459	* nor do we need to increment FRI.
1460	*
1461	* See Intel VT-d spec. 7.2.1 "Primary Fault Logging".
1462	*/
1463	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
1464	uint64_t const uFrcdRegHi = dmarRegReadRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG);
1465	if (uFrcdRegHi & VTD_BF_1_FRCD_REG_F_MASK)
1466	{
1467	uFstsReg \|= VTD_BF_FSTS_REG_PFO_MASK;
1468	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, uFstsReg);
1469	return false;
1470	}
1471
1472	return true;
1473	}
1474
1475
1476	/**
1477	* Records a primary fault.
1478	*
1479	* @param pDevIns The IOMMU device instance.
1480	* @param uFrcdHi The FRCD_HI_REG value for this fault.
1481	* @param uFrcdLo The FRCD_LO_REG value for this fault.
1482	*/
1483	static void dmarPrimaryFaultRecord(PPDMDEVINS pDevIns, uint64_t uFrcdHi, uint64_t uFrcdLo)
1484	{
1485	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1486	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1487
1488	DMAR_LOCK(pDevIns, pThisCC);
1489
1490	/* We don't support advance fault logging. */
1491	Assert(!(dmarRegRead32(pThis, VTD_MMIO_OFF_GSTS_REG) & VTD_BF_GSTS_REG_AFLS_MASK));
1492
1493	if (dmarPrimaryFaultCanRecord(pDevIns, pThis))
1494	{
1495	/* Update the fault recording registers with the fault information. */
1496	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_HI_REG, uFrcdHi);
1497	dmarRegWriteRaw64(pThis, DMAR_MMIO_OFF_FRCD_LO_REG, uFrcdLo);
1498
1499	/* Set the Pending Primary Fault (PPF) field in the status register. */
1500	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, VTD_BF_FSTS_REG_PPF_MASK);
1501
1502	/* Raise interrupt if necessary. */
1503	dmarFaultEventRaiseInterrupt(pDevIns);
1504	}
1505
1506	DMAR_UNLOCK(pDevIns, pThisCC);
1507	}
1508
1509
1510	/**
1511	* Records an interrupt request fault.
1512	*
1513	* @param pDevIns The IOMMU device instance.
1514	* @param enmDiag The diagnostic reason.
1515	* @param idDevice The device ID (bus, device, function).
1516	* @param idxIntr The interrupt index.
1517	* @param pIrte The IRTE that caused this fault. Can be NULL if the fault is
1518	* not qualified.
1519	*/
1520	static void dmarIrFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, uint16_t idDevice, uint16_t idxIntr, PCVTD_IRTE_T pIrte)
1521	{
1522	/*
1523	* Update the diagnostic reason (even if software wants to supress faults).
1524	*/
1525	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1526	pThis->enmDiag = enmDiag;
1527
1528	/*
1529	* Figure out the fault reason to report to software from our diagnostic code.
1530	* The case labels below are sorted alphabetically for convenience.
1531	*/
1532	VTDIRFAULT enmIrFault;
1533	switch (enmDiag)
1534	{
1535	case kDmarDiag_Ir_Cfi_Blocked: enmIrFault = VTDIRFAULT_CFI_BLOCKED; break;
1536	case kDmarDiag_Ir_Rfi_Intr_Index_Invalid: enmIrFault = VTDIRFAULT_INTR_INDEX_INVALID; break;
1537	case kDmarDiag_Ir_Rfi_Irte_Mode_Invalid: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1538	case kDmarDiag_Ir_Rfi_Irte_Not_Present: enmIrFault = VTDIRFAULT_IRTE_NOT_PRESENT; break;
1539	case kDmarDiag_Ir_Rfi_Irte_Read_Failed: enmIrFault = VTDIRFAULT_IRTE_READ_FAILED; break;
1540	case kDmarDiag_Ir_Rfi_Irte_Rsvd:
1541	case kDmarDiag_Ir_Rfi_Irte_Svt_Bus:
1542	case kDmarDiag_Ir_Rfi_Irte_Svt_Masked:
1543	case kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd: enmIrFault = VTDIRFAULT_IRTE_PRESENT_RSVD; break;
1544	case kDmarDiag_Ir_Rfi_Rsvd: enmIrFault = VTDIRFAULT_REMAPPABLE_INTR_RSVD; break;
1545
1546	/* Shouldn't ever happen. */
1547	default:
1548	{
1549	AssertLogRelMsgFailedReturnVoid(("%s: Invalid interrupt remapping fault diagnostic code %#x\n", DMAR_LOG_PFX,
1550	enmDiag));
1551	}
1552	}
1553
1554	/*
1555	* Qualified faults are those that can be suppressed by software using the FPD bit
1556	* in the interrupt-remapping table entry.
1557	*/
1558	bool fFpd;
1559	bool const fQualifiedFault = vtdIrFaultIsQualified(enmIrFault);
1560	if (fQualifiedFault)
1561	{
1562	AssertReturnVoid(pIrte);
1563	fFpd = RT_BOOL(pIrte->au64[0] & VTD_BF_0_IRTE_FPD_MASK);
1564	}
1565	else
1566	fFpd = false;
1567
1568	if (!fFpd)
1569	{
1570	/* Construct and record the error. */
1571	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1572	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmIrFault)
1573	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1574	uint64_t const uFrcdLo = (uint64_t)idxIntr << 48;
1575	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1576	}
1577	}
1578
1579
1580	/**
1581	* Records an address translation fault.
1582	*
1583	* @param pDevIns The IOMMU device instance.
1584	* @param enmDiag The diagnostic reason.
1585	* @param pMemReqIn The DMA memory request input.
1586	* @param pMemReqAux The DMA memory request auxiliary info.
1587	*/
1588	static void dmarAtFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux)
1589	{
1590	/*
1591	* Update the diagnostic reason (even if software wants to supress faults).
1592	*/
1593	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1594	pThis->enmDiag = enmDiag;
1595
1596	/*
1597	* Qualified faults are those that can be suppressed by software using the FPD bit
1598	* in the context entry, scalable-mode context entry etc.
1599	*/
1600	if (!pMemReqAux->fFpd)
1601	{
1602	/*
1603	* Figure out the fault reason to report to software from our diagnostic code.
1604	* The case labels below are sorted alphabetically for convenience.
1605	*/
1606	VTDATFAULT enmAtFault;
1607	bool const fLm = pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE;
1608	switch (enmDiag)
1609	{
1610	/* LM (Legacy Mode) faults. */
1611	case kDmarDiag_At_Lm_CtxEntry_Not_Present: enmAtFault = VTDATFAULT_LCT_2; break;
1612	case kDmarDiag_At_Lm_CtxEntry_Read_Failed: enmAtFault = VTDATFAULT_LCT_1; break;
1613	case kDmarDiag_At_Lm_CtxEntry_Rsvd: enmAtFault = VTDATFAULT_LCT_3; break;
1614	case kDmarDiag_At_Lm_Pt_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1615	case kDmarDiag_At_Lm_Pt_Aw_Invalid: enmAtFault = VTDATFAULT_LGN_1_3; break;
1616	case kDmarDiag_At_Lm_RootEntry_Not_Present: enmAtFault = VTDATFAULT_LRT_2; break;
1617	case kDmarDiag_At_Lm_RootEntry_Read_Failed: enmAtFault = VTDATFAULT_LRT_1; break;
1618	case kDmarDiag_At_Lm_RootEntry_Rsvd: enmAtFault = VTDATFAULT_LRT_3; break;
1619	case kDmarDiag_At_Lm_Tt_Invalid: enmAtFault = VTDATFAULT_LCT_4_2; break;
1620	case kDmarDiag_At_Lm_Ut_At_Block: enmAtFault = VTDATFAULT_LCT_5; break;
1621	case kDmarDiag_At_Lm_Ut_Aw_Invalid: enmAtFault = VTDATFAULT_LCT_4_1; break;
1622
1623	/* RTA (Root Table Address) faults. */
1624	case kDmarDiag_At_Rta_Adms_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_1; break;
1625	case kDmarDiag_At_Rta_Rsvd: enmAtFault = VTDATFAULT_RTA_1_2; break;
1626	case kDmarDiag_At_Rta_Smts_Not_Supported: enmAtFault = VTDATFAULT_RTA_1_3; break;
1627
1628	/* XM (Legacy mode or Scalable Mode) faults. */
1629	case kDmarDiag_At_Xm_AddrIn_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_1_1 : VTDATFAULT_SGN_5; break;
1630	case kDmarDiag_At_Xm_AddrOut_Invalid: enmAtFault = fLm ? VTDATFAULT_LGN_4 : VTDATFAULT_SGN_8; break;
1631	case kDmarDiag_At_Xm_Perm_Denied: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_2; break;
1632	case kDmarDiag_At_Xm_Pte_Rsvd:
1633	case kDmarDiag_At_Xm_Pte_Sllps_Invalid: enmAtFault = fLm ? VTDATFAULT_LSL_2 : VTDATFAULT_SSL_3; break;
1634	case kDmarDiag_At_Xm_Read_Pte_Failed: enmAtFault = fLm ? VTDATFAULT_LSL_1 : VTDATFAULT_SSL_1; break;
1635	case kDmarDiag_At_Xm_Slpptr_Read_Failed: enmAtFault = fLm ? VTDATFAULT_LCT_4_3 : VTDATFAULT_SSL_4; break;
1636
1637	/* Shouldn't ever happen. */
1638	default:
1639	{
1640	AssertLogRelMsgFailedReturnVoid(("%s: Invalid address translation fault diagnostic code %#x\n",
1641	DMAR_LOG_PFX, enmDiag));
1642	}
1643	}
1644
1645	/* Construct and record the error. */
1646	uint16_t const idDevice = pMemReqIn->idDevice;
1647	uint8_t const fType1 = pMemReqIn->enmReqType & RT_BIT(1);
1648	uint8_t const fType2 = pMemReqIn->enmReqType & RT_BIT(0);
1649	uint8_t const fExec = pMemReqIn->AddrRange.fPerm & DMAR_PERM_EXE;
1650	uint8_t const fPriv = pMemReqIn->AddrRange.fPerm & DMAR_PERM_PRIV;
1651	bool const fHasPasid = PCIPASID_IS_VALID(pMemReqIn->Pasid);
1652	uint32_t const uPasid = PCIPASID_VAL(pMemReqIn->Pasid);
1653	PCIADDRTYPE const enmAt = pMemReqIn->enmAddrType;
1654
1655	uint64_t const uFrcdHi = RT_BF_MAKE(VTD_BF_1_FRCD_REG_SID, idDevice)
1656	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T2, fType2)
1657	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PP, fHasPasid)
1658	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_EXE, fExec)
1659	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PRIV, fPriv)
1660	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_FR, enmAtFault)
1661	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_PV, uPasid)
1662	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_AT, enmAt)
1663	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_T1, fType1)
1664	\| RT_BF_MAKE(VTD_BF_1_FRCD_REG_F, 1);
1665	uint64_t const uFrcdLo = pMemReqIn->AddrRange.uAddr & X86_PAGE_BASE_MASK;
1666	dmarPrimaryFaultRecord(pDevIns, uFrcdHi, uFrcdLo);
1667	}
1668	}
1669
1670
1671	/**
1672	* Records an IQE fault.
1673	*
1674	* @param pDevIns The IOMMU device instance.
1675	* @param enmIqei The IQE information.
1676	* @param enmDiag The diagnostic reason.
1677	*/
1678	static void dmarIqeFaultRecord(PPDMDEVINS pDevIns, DMARDIAG enmDiag, VTDIQEI enmIqei)
1679	{
1680	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1681	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
1682
1683	DMAR_LOCK(pDevIns, pThisCC);
1684
1685	/* Update the diagnostic reason. */
1686	pThis->enmDiag = enmDiag;
1687
1688	/* Set the error bit. */
1689	uint32_t const fIqe = RT_BF_MAKE(VTD_BF_FSTS_REG_IQE, 1);
1690	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, UINT32_MAX, fIqe);
1691
1692	/* Set the error information. */
1693	uint64_t const fIqei = RT_BF_MAKE(VTD_BF_IQERCD_REG_IQEI, enmIqei);
1694	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG, UINT64_MAX, fIqei);
1695
1696	dmarFaultEventRaiseInterrupt(pDevIns);
1697
1698	DMAR_UNLOCK(pDevIns, pThisCC);
1699	}
1700
1701
1702	/**
1703	* Handles writes to GCMD_REG.
1704	*
1705	* @returns Strict VBox status code.
1706	* @param pDevIns The IOMMU device instance.
1707	* @param uGcmdReg The value written to GCMD_REG.
1708	*/
1709	static VBOXSTRICTRC dmarGcmdRegWrite(PPDMDEVINS pDevIns, uint32_t uGcmdReg)
1710	{
1711	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1712	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1713	uint32_t const fChanged = uGstsReg ^ uGcmdReg;
1714	uint64_t const fExtCapReg = pThis->fExtCapReg;
1715
1716	/* Queued-invalidation. */
1717	if ( (fExtCapReg & VTD_BF_ECAP_REG_QI_MASK)
1718	&& (fChanged & VTD_BF_GCMD_REG_QIE_MASK))
1719	{
1720	if (uGcmdReg & VTD_BF_GCMD_REG_QIE_MASK)
1721	{
1722	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_QIES_MASK);
1723	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1724	}
1725	else
1726	{
1727	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_QIES_MASK, 0 /* fOrMask */);
1728	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IQH_REG, 0);
1729	}
1730	}
1731
1732	if (fExtCapReg & VTD_BF_ECAP_REG_IR_MASK)
1733	{
1734	/* Set Interrupt Remapping Table Pointer (SIRTP). */
1735	if (uGcmdReg & VTD_BF_GCMD_REG_SIRTP_MASK)
1736	{
1737	/** @todo Perform global invalidation of all interrupt-entry cache when ESIRTPS is
1738	* supported. */
1739	pThis->uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
1740	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRTPS_MASK);
1741	}
1742
1743	/* Interrupt remapping. */
1744	if (fChanged & VTD_BF_GCMD_REG_IRE_MASK)
1745	{
1746	if (uGcmdReg & VTD_BF_GCMD_REG_IRE_MASK)
1747	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_IRES_MASK);
1748	else
1749	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_IRES_MASK, 0 /* fOrMask */);
1750	}
1751
1752	/* Compatibility format interrupts. */
1753	if (fChanged & VTD_BF_GCMD_REG_CFI_MASK)
1754	{
1755	if (uGcmdReg & VTD_BF_GCMD_REG_CFI_MASK)
1756	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_CFIS_MASK);
1757	else
1758	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_CFIS_MASK, 0 /* fOrMask */);
1759	}
1760	}
1761
1762	/* Set Root Table Pointer (SRTP). */
1763	if (uGcmdReg & VTD_BF_GCMD_REG_SRTP_MASK)
1764	{
1765	/** @todo Perform global invalidation of all remapping translation caches when
1766	* ESRTPS is supported. */
1767	pThis->uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
1768	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_RTPS_MASK);
1769	}
1770
1771	/* Translation (DMA remapping). */
1772	if (fChanged & VTD_BF_GCMD_REG_TE_MASK)
1773	{
1774	if (uGcmdReg & VTD_BF_GCMD_REG_TE_MASK)
1775	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, UINT32_MAX, VTD_BF_GSTS_REG_TES_MASK);
1776	else
1777	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_GSTS_REG_TES_MASK, 0 /* fOrMask */);
1778	}
1779
1780	return VINF_SUCCESS;
1781	}
1782
1783
1784	/**
1785	* Handles writes to CCMD_REG.
1786	*
1787	* @returns Strict VBox status code.
1788	* @param pDevIns The IOMMU device instance.
1789	* @param offReg The MMIO register offset.
1790	* @param cbReg The size of the MMIO access (in bytes).
1791	* @param uCcmdReg The value written to CCMD_REG.
1792	*/
1793	static VBOXSTRICTRC dmarCcmdRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uCcmdReg)
1794	{
1795	/* At present, we only care about responding to high 32-bits writes, low 32-bits are data. */
1796	if (offReg + cbReg > VTD_MMIO_OFF_CCMD_REG + 4)
1797	{
1798	/* Check if we need to invalidate the context-context. */
1799	bool const fIcc = RT_BF_GET(uCcmdReg, VTD_BF_CCMD_REG_ICC);
1800	if (fIcc)
1801	{
1802	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1803	uint8_t const uMajorVersion = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
1804	if (uMajorVersion < 6)
1805	{
1806	/* Register-based invalidation can only be used when queued-invalidations are not enabled. */
1807	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
1808	if (!(uGstsReg & VTD_BF_GSTS_REG_QIES_MASK))
1809	{
1810	/* Verify table translation mode is legacy. */
1811	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
1812	if (fTtm == VTD_TTM_LEGACY_MODE)
1813	{
1814	/** @todo Invalidate. */
1815	return VINF_SUCCESS;
1816	}
1817	pThis->enmDiag = kDmarDiag_CcmdReg_Ttm_Invalid;
1818	}
1819	else
1820	pThis->enmDiag = kDmarDiag_CcmdReg_Qi_Enabled;
1821	}
1822	else
1823	pThis->enmDiag = kDmarDiag_CcmdReg_Not_Supported;
1824	dmarRegChangeRaw64(pThis, VTD_MMIO_OFF_GSTS_REG, ~VTD_BF_CCMD_REG_CAIG_MASK, 0 /* fOrMask */);
1825	}
1826	}
1827	return VINF_SUCCESS;
1828	}
1829
1830
1831	/**
1832	* Handles writes to FECTL_REG.
1833	*
1834	* @returns Strict VBox status code.
1835	* @param pDevIns The IOMMU device instance.
1836	* @param uFectlReg The value written to FECTL_REG.
1837	*/
1838	static VBOXSTRICTRC dmarFectlRegWrite(PPDMDEVINS pDevIns, uint32_t uFectlReg)
1839	{
1840	/*
1841	* If software unmasks the interrupt when the interrupt is pending, we must raise
1842	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1843	*/
1844	if ( (uFectlReg & VTD_BF_FECTL_REG_IP_MASK)
1845	&& ~(uFectlReg & VTD_BF_FECTL_REG_IM_MASK))
1846	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_FAULT);
1847	return VINF_SUCCESS;
1848	}
1849
1850
1851	/**
1852	* Handles writes to FSTS_REG.
1853	*
1854	* @returns Strict VBox status code.
1855	* @param pDevIns The IOMMU device instance.
1856	* @param uFstsReg The value written to FSTS_REG.
1857	* @param uPrev The value in FSTS_REG prior to writing it.
1858	*/
1859	static VBOXSTRICTRC dmarFstsRegWrite(PPDMDEVINS pDevIns, uint32_t uFstsReg, uint32_t uPrev)
1860	{
1861	/*
1862	* If software clears other status bits in FSTS_REG (pertaining to primary fault logging),
1863	* the interrupt pending (IP) bit must be cleared.
1864	*
1865	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
1866	*/
1867	uint32_t const fChanged = uPrev ^ uFstsReg;
1868	if (fChanged & ( VTD_BF_FSTS_REG_ICE_MASK \| VTD_BF_FSTS_REG_ITE_MASK
1869	\| VTD_BF_FSTS_REG_IQE_MASK \| VTD_BF_FSTS_REG_PFO_MASK))
1870	{
1871	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1872	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
1873	}
1874	return VINF_SUCCESS;
1875	}
1876
1877
1878	/**
1879	* Handles writes to IQT_REG.
1880	*
1881	* @returns Strict VBox status code.
1882	* @param pDevIns The IOMMU device instance.
1883	* @param offReg The MMIO register offset.
1884	* @param uIqtReg The value written to IQT_REG.
1885	*/
1886	static VBOXSTRICTRC dmarIqtRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqtReg)
1887	{
1888	/* We only care about the low 32-bits, high 32-bits are reserved. */
1889	Assert(offReg == VTD_MMIO_OFF_IQT_REG);
1890	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1891
1892	/* Paranoia. */
1893	Assert(!(uIqtReg & ~VTD_BF_IQT_REG_QT_MASK));
1894
1895	uint32_t const offQt = uIqtReg;
1896	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
1897	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1898
1899	/* If the descriptor width is 256-bits, the queue tail offset must be aligned accordingly. */
1900	if ( fDw != VTD_IQA_REG_DW_256_BIT
1901	\|\| !(offQt & RT_BIT(4)))
1902	dmarInvQueueThreadWakeUpIfNeeded(pDevIns);
1903	else
1904	{
1905	/* Hardware treats bit 4 as RsvdZ in this situation, so clear it. */
1906	dmarRegChangeRaw32(pThis, offReg, ~RT_BIT(4), 0 /* fOrMask */);
1907	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Not_Aligned, VTDIQEI_QUEUE_TAIL_MISALIGNED);
1908	}
1909	return VINF_SUCCESS;
1910	}
1911
1912
1913	/**
1914	* Handles writes to IQA_REG.
1915	*
1916	* @returns Strict VBox status code.
1917	* @param pDevIns The IOMMU device instance.
1918	* @param offReg The MMIO register offset.
1919	* @param uIqaReg The value written to IQA_REG.
1920	*/
1921	static VBOXSTRICTRC dmarIqaRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint64_t uIqaReg)
1922	{
1923	/* At present, we only care about the low 32-bits, high 32-bits are data. */
1924	Assert(offReg == VTD_MMIO_OFF_IQA_REG); NOREF(offReg);
1925
1926	/** @todo What happens if IQA_REG is written when dmarInvQueueCanProcessRequests
1927	* returns true? The Intel VT-d spec. doesn't state anywhere that it
1928	* cannot happen or that it's ignored when it does happen. */
1929
1930	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1931	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
1932	if (fDw == VTD_IQA_REG_DW_256_BIT)
1933	{
1934	bool const fSupports256BitDw = (pThis->fExtCapReg & (VTD_BF_ECAP_REG_SMTS_MASK \| VTD_BF_ECAP_REG_ADMS_MASK));
1935	if (fSupports256BitDw)
1936	{ /* likely */ }
1937	else
1938	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dw_256_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
1939	}
1940	/* else: 128-bit descriptor width is validated lazily, see explanation in dmarR3InvQueueProcessRequests. */
1941
1942	return VINF_SUCCESS;
1943	}
1944
1945
1946	/**
1947	* Handles writes to ICS_REG.
1948	*
1949	* @returns Strict VBox status code.
1950	* @param pDevIns The IOMMU device instance.
1951	* @param uIcsReg The value written to ICS_REG.
1952	*/
1953	static VBOXSTRICTRC dmarIcsRegWrite(PPDMDEVINS pDevIns, uint32_t uIcsReg)
1954	{
1955	/*
1956	* If the IP field is set when software services the interrupt condition,
1957	* (by clearing the IWC field), the IP field must be cleared.
1958	*/
1959	if (!(uIcsReg & VTD_BF_ICS_REG_IWC_MASK))
1960	{
1961	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
1962	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, ~VTD_BF_IECTL_REG_IP_MASK, 0 /* fOrMask */);
1963	}
1964	return VINF_SUCCESS;
1965	}
1966
1967
1968	/**
1969	* Handles writes to IECTL_REG.
1970	*
1971	* @returns Strict VBox status code.
1972	* @param pDevIns The IOMMU device instance.
1973	* @param uIectlReg The value written to IECTL_REG.
1974	*/
1975	static VBOXSTRICTRC dmarIectlRegWrite(PPDMDEVINS pDevIns, uint32_t uIectlReg)
1976	{
1977	/*
1978	* If software unmasks the interrupt when the interrupt is pending, we must raise
1979	* the interrupt now (which will consequently clear the interrupt pending (IP) bit).
1980	*/
1981	if ( (uIectlReg & VTD_BF_IECTL_REG_IP_MASK)
1982	&& ~(uIectlReg & VTD_BF_IECTL_REG_IM_MASK))
1983	dmarEventRaiseInterrupt(pDevIns, DMAREVENTTYPE_INV_COMPLETE);
1984	return VINF_SUCCESS;
1985	}
1986
1987
1988	/**
1989	* Handles writes to FRCD_REG (High 64-bits).
1990	*
1991	* @returns Strict VBox status code.
1992	* @param pDevIns The IOMMU device instance.
1993	* @param offReg The MMIO register offset.
1994	* @param cbReg The size of the MMIO access (in bytes).
1995	* @param uFrcdHiReg The value written to FRCD_REG.
1996	* @param uPrev The value in FRCD_REG prior to writing it.
1997	*/
1998	static VBOXSTRICTRC dmarFrcdHiRegWrite(PPDMDEVINS pDevIns, uint16_t offReg, uint8_t cbReg, uint64_t uFrcdHiReg, uint64_t uPrev)
1999	{
2000	/* We only care about responding to high 32-bits, low 32-bits are read-only. */
2001	if (offReg + cbReg > DMAR_MMIO_OFF_FRCD_HI_REG + 4)
2002	{
2003	/*
2004	* If software cleared the RW1C F (fault) bit in all FRCD_REGs, hardware clears the
2005	* Primary Pending Fault (PPF) and the interrupt pending (IP) bits. Our implementation
2006	* has only 1 FRCD register.
2007	*
2008	* See Intel VT-d spec. 10.4.10 "Fault Event Control Register".
2009	*/
2010	AssertCompile(DMAR_FRCD_REG_COUNT == 1);
2011	uint64_t const fChanged = uPrev ^ uFrcdHiReg;
2012	if (fChanged & VTD_BF_1_FRCD_REG_F_MASK)
2013	{
2014	Assert(!(uFrcdHiReg & VTD_BF_1_FRCD_REG_F_MASK)); /* Software should only ever be able to clear this bit. */
2015	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2016	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FSTS_REG, ~VTD_BF_FSTS_REG_PPF_MASK, 0 /* fOrMask */);
2017	dmarRegChangeRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, ~VTD_BF_FECTL_REG_IP_MASK, 0 /* fOrMask */);
2018	}
2019	}
2020	return VINF_SUCCESS;
2021	}
2022
2023
2024	/**
2025	* Performs a PCI target abort for a DMA remapping (DR) operation.
2026	*
2027	* @param pDevIns The IOMMU device instance.
2028	*/
2029	static void dmarDrTargetAbort(PPDMDEVINS pDevIns)
2030	{
2031	/** @todo r=ramshankar: I don't know for sure if a PCI target abort is caused or not
2032	* as the Intel VT-d spec. is vague. Wording seems to suggest it does, but
2033	* who knows. */
2034	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
2035	uint16_t const u16Status = PDMPciDevGetStatus(pPciDev) \| VBOX_PCI_STATUS_SIG_TARGET_ABORT;
2036	PDMPciDevSetStatus(pPciDev, u16Status);
2037	}
2038
2039
2040	/**
2041	* Checks whether the address width (AW) is supported by our hardware
2042	* implementation for legacy mode address translation.
2043	*
2044	* @returns @c true if it's supported, @c false otherwise.
2045	* @param pThis The shared DMAR device state.
2046	* @param pCtxEntry The context entry.
2047	* @param pcPagingLevel Where to store the paging level. Optional, can be NULL.
2048	*/
2049	static bool dmarDrLegacyModeIsAwValid(PCDMAR pThis, PCVTD_CONTEXT_ENTRY_T pCtxEntry, uint8_t *pcPagingLevel)
2050	{
2051	uint8_t const fTt = RT_BF_GET(pCtxEntry->au64[0], VTD_BF_0_CONTEXT_ENTRY_TT);
2052	uint8_t const fAw = RT_BF_GET(pCtxEntry->au64[1], VTD_BF_1_CONTEXT_ENTRY_AW);
2053	uint8_t const fAwMask = RT_BIT(fAw);
2054	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
2055	Assert(!(fSagaw & ~(RT_BIT(1) \| RT_BIT(2) \| RT_BIT(3))));
2056
2057	uint8_t const cPagingLevel = fAw + 2;
2058	if (pcPagingLevel)
2059	*pcPagingLevel = cPagingLevel;
2060
2061	/* With pass-through, the address width must be the largest AGAW supported by hardware. */
2062	if (fTt == VTD_TT_UNTRANSLATED_PT)
2063	{
2064	Assert(pThis->cMaxPagingLevel >= 3 && pThis->cMaxPagingLevel <= 5); /* Paranoia. */
2065	return cPagingLevel == pThis->cMaxPagingLevel;
2066	}
2067
2068	/* The address width must be any of the ones supported by hardware. */
2069	if (fAw < 4)
2070	return (fSagaw & fAwMask) != 0;
2071
2072	return false;
2073	}
2074
2075
2076	/**
2077	* Reads a root entry from guest memory.
2078	*
2079	* @returns VBox status code.
2080	* @param pDevIns The IOMMU device instance.
2081	* @param uRtaddrReg The current RTADDR_REG value.
2082	* @param idxRootEntry The index of the root entry to read.
2083	* @param pRootEntry Where to store the read root entry.
2084	*/
2085	static int dmarDrReadRootEntry(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, uint8_t idxRootEntry, PVTD_ROOT_ENTRY_T pRootEntry)
2086	{
2087	size_t const cbRootEntry = sizeof(*pRootEntry);
2088	RTGCPHYS const GCPhysRootEntry = (uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK) + (idxRootEntry * cbRootEntry);
2089	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysRootEntry, pRootEntry, cbRootEntry);
2090	}
2091
2092
2093	/**
2094	* Reads a context entry from guest memory.
2095	*
2096	* @returns VBox status code.
2097	* @param pDevIns The IOMMU device instance.
2098	* @param GCPhysCtxTable The physical address of the context table.
2099	* @param idxCtxEntry The index of the context entry to read.
2100	* @param pCtxEntry Where to store the read context entry.
2101	*/
2102	static int dmarDrReadCtxEntry(PPDMDEVINS pDevIns, RTGCPHYS GCPhysCtxTable, uint8_t idxCtxEntry, PVTD_CONTEXT_ENTRY_T pCtxEntry)
2103	{
2104	/* We don't verify bits 63:HAW of GCPhysCtxTable is 0 since reading from such an address should fail anyway. */
2105	size_t const cbCtxEntry = sizeof(*pCtxEntry);
2106	RTGCPHYS const GCPhysCtxEntry = GCPhysCtxTable + (idxCtxEntry * cbCtxEntry);
2107	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysCtxEntry, pCtxEntry, cbCtxEntry);
2108	}
2109
2110
2111	/**
2112	* Validates and updates the output I/O page of a translation.
2113	*
2114	* @returns VBox status code.
2115	* @param pDevIns The IOMMU device instance.
2116	* @param GCPhysBase The output address of the translation.
2117	* @param cShift The page shift of the translated address.
2118	* @param fPerm The permissions granted for the translated region.
2119	* @param pMemReqIn The DMA memory request input.
2120	* @param pMemReqAux The DMA memory request auxiliary info.
2121	* @param pIoPageOut Where to store the output of the translation.
2122	*/
2123	static int dmarDrUpdateIoPageOut(PPDMDEVINS pDevIns, RTGCPHYS GCPhysBase, uint8_t cShift, uint8_t fPerm,
2124	PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux, PDMARIOPAGE pIoPageOut)
2125	{
2126	Assert(!(GCPhysBase & X86_PAGE_4K_OFFSET_MASK));
2127
2128	/* Ensure the output address is not in the interrupt address range. */
2129	if (GCPhysBase - VBOX_MSI_ADDR_BASE >= VBOX_MSI_ADDR_SIZE)
2130	{
2131	pIoPageOut->GCPhysBase = GCPhysBase;
2132	pIoPageOut->cShift = cShift;
2133	pIoPageOut->fPerm = fPerm;
2134	return VINF_SUCCESS;
2135	}
2136
2137	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrOut_Invalid, pMemReqIn, pMemReqAux);
2138	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2139	}
2140
2141
2142	/**
2143	* Performs second level translation by walking the I/O page tables.
2144	*
2145	* This is a DMA address-lookup callback function which performs the translation
2146	* (and access control) as part of the lookup.
2147	*
2148	* @returns VBox status code.
2149	* @param pDevIns The IOMMU device instance.
2150	* @param pMemReqIn The DMA memory request input.
2151	* @param pMemReqAux The DMA memory request auxiliary info.
2152	* @param pIoPageOut Where to store the output of the translation.
2153	*/
2154	static DECLCALLBACK(int) dmarDrSecondLevelTranslate(PPDMDEVINS pDevIns, PCDMARMEMREQIN pMemReqIn, PCDMARMEMREQAUX pMemReqAux,
2155	PDMARIOPAGE pIoPageOut)
2156	{
2157	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2158
2159	/* Sanity. */
2160	Assert(pIoPageOut);
2161	Assert(pMemReqIn->AddrRange.fPerm & (DMAR_PERM_READ \| DMAR_PERM_WRITE));
2162	Assert( pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE
2163	\|\| pMemReqAux->fTtm == VTD_TTM_SCALABLE_MODE);
2164	Assert(!(pMemReqAux->GCPhysSlPt & X86_PAGE_4K_OFFSET_MASK));
2165
2166	/* Mask of valid paging entry bits. */
2167	static uint64_t const s_auPtEntityRsvd[] = { VTD_SL_PTE_VALID_MASK,
2168	VTD_SL_PDE_VALID_MASK,
2169	VTD_SL_PDPE_VALID_MASK,
2170	VTD_SL_PML4E_VALID_MASK,
2171	VTD_SL_PML5E_VALID_MASK };
2172
2173	/* Paranoia. */
2174	Assert(pMemReqAux->cPagingLevel >= 3 && pMemReqAux->cPagingLevel <= 5);
2175	AssertCompile(RT_ELEMENTS(s_auPtEntityRsvd) == 5);
2176
2177	/* Second-level translations restricts input address to an implementation-specific MGAW. */
2178	uint64_t const uAddrIn = pMemReqIn->AddrRange.uAddr;
2179	if (!(uAddrIn & pThis->fMgawInvMask))
2180	{ /* likely */ }
2181	else
2182	{
2183	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_AddrIn_Invalid, pMemReqIn, pMemReqAux);
2184	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2185	}
2186
2187	/*
2188	* Traverse the I/O page table starting with the SLPTPTR (second-level page table pointer).
2189	* Unlike AMD IOMMU paging, here there is no feature for "skipping" levels.
2190	*/
2191	uint64_t uPtEntity = pMemReqAux->GCPhysSlPt;
2192	for (int8_t idxLevel = pMemReqAux->cPagingLevel - 1; idxLevel >= 0; idxLevel--)
2193	{
2194	/*
2195	* Read the paging entry for the current level.
2196	*/
2197	uint8_t const cLevelShift = X86_PAGE_4K_SHIFT + (idxLevel * 9);
2198	{
2199	uint16_t const idxPte = (uAddrIn >> cLevelShift) & UINT64_C(0x1ff);
2200	uint16_t const offPte = idxPte << 3;
2201	RTGCPHYS const GCPhysPtEntity = (uPtEntity & X86_PAGE_4K_BASE_MASK) \| offPte;
2202	int const rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysPtEntity, &uPtEntity, sizeof(uPtEntity));
2203	if (RT_SUCCESS(rc))
2204	{ /* likely */ }
2205	else
2206	{
2207	if ((GCPhysPtEntity & X86_PAGE_BASE_MASK) == pMemReqAux->GCPhysSlPt)
2208	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Slpptr_Read_Failed, pMemReqIn, pMemReqAux);
2209	else
2210	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Read_Pte_Failed, pMemReqIn, pMemReqAux);
2211	break;
2212	}
2213	}
2214
2215	/*
2216	* Check I/O permissions.
2217	* This must be done prior to check reserved bits for properly reporting errors SSL.2 and SSL.3.
2218	* See Intel spec. 7.1.3 "Fault conditions and Remapping hardware behavior for various request".
2219	*/
2220	uint8_t const fReqPerm = pMemReqIn->AddrRange.fPerm & pThis->fPermValidMask;
2221	uint8_t const fPtPerm = uPtEntity & pThis->fPermValidMask;
2222	Assert(!(fReqPerm & DMAR_PERM_EXE)); /* No Execute-requests support yet. */
2223	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_SLADS_MASK)); /* No Second-level access/dirty support. */
2224	if ((fPtPerm & fReqPerm) == fReqPerm)
2225	{ /* likely */ }
2226	else
2227	{
2228	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Perm_Denied, pMemReqIn, pMemReqAux);
2229	break;
2230	}
2231
2232	/*
2233	* Validate reserved bits of the current paging entry.
2234	*/
2235	if (!(uPtEntity & ~s_auPtEntityRsvd[idxLevel]))
2236	{ /* likely */ }
2237	else
2238	{
2239	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Rsvd, pMemReqIn, pMemReqAux);
2240	break;
2241	}
2242
2243	/*
2244	* Check if this is a 1GB page or a 2MB page.
2245	*/
2246	AssertCompile(VTD_BF_SL_PDE_PS_MASK == VTD_BF_SL_PDPE_PS_MASK);
2247	uint8_t const fLargePage = RT_BF_GET(uPtEntity, VTD_BF_SL_PDE_PS);
2248	if (fLargePage && idxLevel > 0)
2249	{
2250	Assert(idxLevel == 1 \|\| idxLevel == 2); /* Is guaranteed by the reserved bits check above. */
2251	uint8_t const fSllpsMask = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SLLPS);
2252	if (fSllpsMask & RT_BIT(idxLevel - 1))
2253	{
2254	/*
2255	* We don't support MTS (asserted below), hence IPAT and EMT fields of the paging entity are ignored.
2256	* All other reserved bits are identical to the regular page-size paging entity which we've already
2257	* checked above.
2258	*/
2259	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_MTS_MASK));
2260
2261	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2262	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2263	}
2264
2265	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Xm_Pte_Sllps_Invalid, pMemReqIn, pMemReqAux);
2266	break;
2267	}
2268
2269	/*
2270	* If this is the final PTE, compute the translation address and we're done.
2271	*/
2272	if (idxLevel == 0)
2273	{
2274	RTGCPHYS const GCPhysBase = uPtEntity & X86_GET_PAGE_BASE_MASK(cLevelShift);
2275	return dmarDrUpdateIoPageOut(pDevIns, GCPhysBase, cLevelShift, fPtPerm, pMemReqIn, pMemReqAux, pIoPageOut);
2276	}
2277	}
2278
2279	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2280	}
2281
2282
2283	/**
2284	* Checks whether two consecutive I/O page results of a DMA memory request
2285	* translates to a physically contiguous region.
2286	*
2287	* @returns @c true if the I/O pages are contiguous, @c false otherwise.
2288	* @param pIoPagePrev The previous I/O page.
2289	* @param pIoPage The current I/O page.
2290	*/
2291	static bool dmarIsIoPageAccessContig(PCDMARIOPAGE pIoPagePrev, PCDMARIOPAGE pIoPage)
2292	{
2293	/* Paranoia: Permissions for pages of a DMA memory request must be identical. */
2294	Assert(pIoPagePrev->fPerm == pIoPage->fPerm);
2295
2296	size_t const cbPrev = RT_BIT_64(pIoPagePrev->cShift);
2297	RTGCPHYS const GCPhysPrev = pIoPagePrev->GCPhysBase;
2298	RTGCPHYS const GCPhys = pIoPage->GCPhysBase;
2299	#ifdef RT_STRICT
2300	/* Paranoia: Ensure offset bits are 0. */
2301	{
2302	uint64_t const fOffMaskPrev = X86_GET_PAGE_OFFSET_MASK(pIoPagePrev->cShift);
2303	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(pIoPage->cShift);
2304	Assert(!(GCPhysPrev & fOffMaskPrev));
2305	Assert(!(GCPhys & fOffMask));
2306	}
2307	#endif
2308	return GCPhysPrev + cbPrev == GCPhys;
2309	}
2310
2311
2312	/**
2313	* Looks up the range of addresses for a DMA memory request remapping.
2314	*
2315	* @returns VBox status code.
2316	* @param pDevIns The IOMMU device instance.
2317	* @param pfnLookup The DMA address lookup function.
2318	* @param pMemReqRemap The DMA memory request remapping info.
2319	*/
2320	static int dmarDrMemRangeLookup(PPDMDEVINS pDevIns, PFNDMADDRLOOKUP pfnLookup, PDMARMEMREQREMAP pMemReqRemap)
2321	{
2322	AssertPtr(pfnLookup);
2323
2324	RTGCPHYS GCPhysAddr = NIL_RTGCPHYS;
2325	DMARMEMREQIN MemReqIn = pMemReqRemap->In;
2326	uint64_t const uAddrIn = MemReqIn.AddrRange.uAddr;
2327	size_t const cbAddrIn = MemReqIn.AddrRange.cb;
2328	uint64_t uAddrInBase = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2329	uint64_t offAddrIn = MemReqIn.AddrRange.uAddr & X86_PAGE_4K_OFFSET_MASK;
2330	size_t cbRemaining = cbAddrIn;
2331
2332	int rc;
2333	DMARIOPAGE IoPagePrev;
2334	RT_ZERO(IoPagePrev);
2335	for (;;)
2336	{
2337	/* Update the input memory request with the next address in our range that needs translation. */
2338	MemReqIn.AddrRange.uAddr = uAddrInBase;
2339	MemReqIn.AddrRange.cb = cbRemaining; /* Not currently accessed by pfnLookup, but keep things consistent. */
2340
2341	DMARIOPAGE IoPage;
2342	rc = pfnLookup(pDevIns, &MemReqIn, &pMemReqRemap->Aux, &IoPage);
2343	if (RT_SUCCESS(rc))
2344	{
2345	Assert(IoPage.cShift >= X86_PAGE_4K_SHIFT && IoPage.cShift <= X86_PAGE_1G_SHIFT);
2346
2347	/* Store the translated address before continuing to access more pages. */
2348	if (cbRemaining == cbAddrIn)
2349	{
2350	uint64_t const fOffMask = X86_GET_PAGE_OFFSET_MASK(IoPage.cShift);
2351	uint64_t const offAddrOut = uAddrIn & fOffMask;
2352	Assert(!(IoPage.GCPhysBase & fOffMask));
2353	GCPhysAddr = IoPage.GCPhysBase \| offAddrOut;
2354	}
2355	/* Check if addresses translated so far result in a physically contiguous region. */
2356	else if (!dmarIsIoPageAccessContig(&IoPagePrev, &IoPage))
2357	{
2358	rc = VERR_OUT_OF_RANGE;
2359	break;
2360	}
2361
2362	/* Store the I/O page lookup from the first/previous access. */
2363	IoPagePrev = IoPage;
2364
2365	/* Check if we need to access more pages. */
2366	size_t const cbPage = RT_BIT_64(IoPage.cShift);
2367	if (cbRemaining > cbPage - offAddrIn)
2368	{
2369	cbRemaining -= (cbPage - offAddrIn); /* Calculate how much more we need to access. */
2370	uAddrInBase += cbPage; /* Update address of the next access. */
2371	offAddrIn = 0; /* After first page, all pages are accessed from offset 0. */
2372	}
2373	else
2374	{
2375	/* Caller (PDM) doesn't expect more data accessed than what was requested. */
2376	cbRemaining = 0;
2377	break;
2378	}
2379	}
2380	else
2381	break;
2382	}
2383
2384	pMemReqRemap->Out.AddrRange.uAddr = GCPhysAddr;
2385	pMemReqRemap->Out.AddrRange.cb = cbAddrIn - cbRemaining;
2386	pMemReqRemap->Out.AddrRange.fPerm = IoPagePrev.fPerm;
2387	return rc;
2388	}
2389
2390
2391	/**
2392	* Handles legacy mode DMA address remapping.
2393	*
2394	* @returns VBox status code.
2395	* @param pDevIns The IOMMU device instance.
2396	* @param uRtaddrReg The current RTADDR_REG value.
2397	* @param pMemReqRemap The DMA memory request remapping info.
2398	*/
2399	static int dmarDrLegacyModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2400	{
2401	PCDMARMEMREQIN pMemReqIn = &pMemReqRemap->In;
2402	PDMARMEMREQAUX pMemReqAux = &pMemReqRemap->Aux;
2403	PDMARMEMREQOUT pMemReqOut = &pMemReqRemap->Out;
2404	Assert(pMemReqAux->fTtm == VTD_TTM_LEGACY_MODE); /* Paranoia. */
2405
2406	/* Read the root-entry from guest memory. */
2407	uint8_t const idxRootEntry = RT_HI_U8(pMemReqIn->idDevice);
2408	VTD_ROOT_ENTRY_T RootEntry;
2409	int rc = dmarDrReadRootEntry(pDevIns, uRtaddrReg, idxRootEntry, &RootEntry);
2410	if (RT_SUCCESS(rc))
2411	{
2412	/* Check if the root entry is present (must be done before validating reserved bits). */
2413	uint64_t const uRootEntryQword0 = RootEntry.au64[0];
2414	uint64_t const uRootEntryQword1 = RootEntry.au64[1];
2415	bool const fRootEntryPresent = RT_BF_GET(uRootEntryQword0, VTD_BF_0_ROOT_ENTRY_P);
2416	if (fRootEntryPresent)
2417	{
2418	/* Validate reserved bits in the root entry. */
2419	if ( !(uRootEntryQword0 & ~VTD_ROOT_ENTRY_0_VALID_MASK)
2420	&& !(uRootEntryQword1 & ~VTD_ROOT_ENTRY_1_VALID_MASK))
2421	{
2422	/* Read the context-entry from guest memory. */
2423	RTGCPHYS const GCPhysCtxTable = uRootEntryQword0 & VTD_BF_0_ROOT_ENTRY_CTP_MASK;
2424	uint8_t const idxCtxEntry = RT_LO_U8(pMemReqIn->idDevice);
2425	VTD_CONTEXT_ENTRY_T CtxEntry;
2426	rc = dmarDrReadCtxEntry(pDevIns, GCPhysCtxTable, idxCtxEntry, &CtxEntry);
2427	if (RT_SUCCESS(rc))
2428	{
2429	uint64_t const uCtxEntryQword0 = CtxEntry.au64[0];
2430	uint64_t const uCtxEntryQword1 = CtxEntry.au64[1];
2431
2432	/* Note the FPD bit which software can use to supress translation faults from here on in. */
2433	pMemReqAux->fFpd = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_FPD);
2434
2435	/* Check if the context-entry is present (must be done before validating reserved bits). */
2436	bool const fCtxEntryPresent = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_P);
2437	if (fCtxEntryPresent)
2438	{
2439	/* Validate reserved bits in the context-entry. */
2440	if ( !(uCtxEntryQword0 & ~VTD_CONTEXT_ENTRY_0_VALID_MASK)
2441	&& !(uCtxEntryQword1 & ~VTD_CONTEXT_ENTRY_1_VALID_MASK))
2442	{
2443	/* Get the domain ID for this mapping. */
2444	pMemReqOut->idDomain = RT_BF_GET(uCtxEntryQword1, VTD_BF_1_CONTEXT_ENTRY_DID);
2445
2446	/* Validate the translation type (TT). */
2447	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PCDMAR);
2448	uint8_t const fTt = RT_BF_GET(uCtxEntryQword0, VTD_BF_0_CONTEXT_ENTRY_TT);
2449	switch (fTt)
2450	{
2451	case VTD_TT_UNTRANSLATED_SLP:
2452	{
2453	/*
2454	* Untranslated requests are translated using second-level paging structures referenced
2455	* through SLPTPTR. Translated requests and Translation Requests are blocked.
2456	*/
2457	if (pMemReqIn->enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2458	{
2459	/* Validate the address width and get the paging level. */
2460	uint8_t cPagingLevel;
2461	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, &cPagingLevel))
2462	{
2463	/*
2464	* The second-level page table is located at the physical address specified
2465	* in the context entry with which we can finally perform second-level translation.
2466	*/
2467	pMemReqAux->cPagingLevel = cPagingLevel;
2468	pMemReqAux->GCPhysSlPt = uCtxEntryQword0 & VTD_BF_0_CONTEXT_ENTRY_SLPTPTR_MASK;
2469	return dmarDrMemRangeLookup(pDevIns, dmarDrSecondLevelTranslate, pMemReqRemap);
2470	}
2471	else
2472	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_Aw_Invalid, pMemReqIn, pMemReqAux);
2473	}
2474	else
2475	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Ut_At_Block, pMemReqIn, pMemReqAux);
2476	break;
2477	}
2478
2479	case VTD_TT_UNTRANSLATED_PT:
2480	{
2481	/*
2482	* Untranslated requests are processed as pass-through (PT) if PT is supported.
2483	* Translated and translation requests are blocked. If PT isn't supported this TT value
2484	* is reserved which I assume raises a fault (hence fallthru below).
2485	*/
2486	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_PT_MASK)
2487	{
2488	if (pMemReqRemap->In.enmAddrType == PCIADDRTYPE_UNTRANSLATED)
2489	{
2490	if (dmarDrLegacyModeIsAwValid(pThis, &CtxEntry, NULL /* pcPagingLevel */))
2491	{
2492	PDMARMEMREQOUT pOut = &pMemReqRemap->Out;
2493	PCDMARMEMREQIN pIn = &pMemReqRemap->In;
2494	pOut->AddrRange.uAddr = pIn->AddrRange.uAddr & X86_PAGE_4K_BASE_MASK;
2495	pOut->AddrRange.cb = pIn->AddrRange.cb;
2496	pOut->AddrRange.fPerm = DMAR_PERM_ALL;
2497	return VINF_SUCCESS;
2498	}
2499	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_Aw_Invalid, pMemReqIn, pMemReqAux);
2500	}
2501	else
2502	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Pt_At_Block, pMemReqIn, pMemReqAux);
2503	break;
2504	}
2505	RT_FALL_THRU();
2506	}
2507
2508	case VTD_TT_UNTRANSLATED_DEV_TLB:
2509	{
2510	/*
2511	* Untranslated, translated and translation requests are supported but requires
2512	* device-TLB support. We don't support device-TLBs, so it's treated as reserved.
2513	*/
2514	Assert(!(pThis->fExtCapReg & VTD_BF_ECAP_REG_DT_MASK));
2515	RT_FALL_THRU();
2516	}
2517
2518	default:
2519	{
2520	/* Any other TT value is reserved. */
2521	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_Tt_Invalid, pMemReqIn, pMemReqAux);
2522	break;
2523	}
2524	}
2525	}
2526	else
2527	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Rsvd, pMemReqIn, pMemReqAux);
2528	}
2529	else
2530	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Not_Present, pMemReqIn, pMemReqAux);
2531	}
2532	else
2533	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_CtxEntry_Read_Failed, pMemReqIn, pMemReqAux);
2534	}
2535	else
2536	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Rsvd, pMemReqIn, pMemReqAux);
2537	}
2538	else
2539	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Not_Present, pMemReqIn, pMemReqAux);
2540	}
2541	else
2542	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Lm_RootEntry_Read_Failed, pMemReqIn, pMemReqAux);
2543	return VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2544	}
2545
2546
2547	/**
2548	* Handles remapping of DMA address requests in scalable mode.
2549	*
2550	* @returns VBox status code.
2551	* @param pDevIns The IOMMU device instance.
2552	* @param uRtaddrReg The current RTADDR_REG value.
2553	* @param pMemReqRemap The DMA memory request remapping info.
2554	*/
2555	static int dmarDrScalableModeRemapAddr(PPDMDEVINS pDevIns, uint64_t uRtaddrReg, PDMARMEMREQREMAP pMemReqRemap)
2556	{
2557	RT_NOREF2(uRtaddrReg, pMemReqRemap);
2558	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2559	Assert(pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK);
2560	return VERR_NOT_IMPLEMENTED;
2561	}
2562
2563
2564	/**
2565	* Memory access bulk (one or more 4K pages) request from a device.
2566	*
2567	* @returns VBox status code.
2568	* @param pDevIns The IOMMU device instance.
2569	* @param idDevice The device ID (bus, device, function).
2570	* @param cIovas The number of addresses being accessed.
2571	* @param pauIovas The I/O virtual addresses for each page being accessed.
2572	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2573	* @param paGCPhysSpa Where to store the translated physical addresses.
2574	*
2575	* @thread Any.
2576	*/
2577	static DECLCALLBACK(int) iommuIntelMemBulkAccess(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
2578	uint32_t fFlags, PRTGCPHYS paGCPhysSpa)
2579	{
2580	RT_NOREF6(pDevIns, idDevice, cIovas, pauIovas, fFlags, paGCPhysSpa);
2581	return VERR_NOT_IMPLEMENTED;
2582	}
2583
2584
2585	/**
2586	* Memory access transaction from a device.
2587	*
2588	* @returns VBox status code.
2589	* @param pDevIns The IOMMU device instance.
2590	* @param idDevice The device ID (bus, device, function).
2591	* @param uIova The I/O virtual address being accessed.
2592	* @param cbIova The size of the access.
2593	* @param fFlags The access flags, see PDMIOMMU_MEM_F_XXX.
2594	* @param pGCPhysSpa Where to store the translated system physical address.
2595	* @param pcbContiguous Where to store the number of contiguous bytes translated
2596	* and permission-checked.
2597	*
2598	* @thread Any.
2599	*/
2600	static DECLCALLBACK(int) iommuIntelMemAccess(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
2601	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContiguous)
2602	{
2603	/* Validate. */
2604	AssertPtr(pDevIns);
2605	AssertPtr(pGCPhysSpa);
2606	AssertPtr(pcbContiguous);
2607	Assert(cbIova > 0); /** @todo Are we going to support ZLR (zero-length reads to write-only pages)? */
2608	Assert(!(fFlags & ~PDMIOMMU_MEM_F_VALID_MASK));
2609
2610	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2611	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2612
2613	DMAR_LOCK(pDevIns, pThisCC);
2614	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2615	uint64_t const uRtaddrReg = pThis->uRtaddrReg;
2616	DMAR_UNLOCK(pDevIns, pThisCC);
2617
2618	if (uGstsReg & VTD_BF_GSTS_REG_TES_MASK)
2619	{
2620	VTDREQTYPE enmReqType;
2621	uint8_t fReqPerm;
2622	if (fFlags & PDMIOMMU_MEM_F_READ)
2623	{
2624	enmReqType = VTDREQTYPE_READ;
2625	fReqPerm = DMAR_PERM_READ;
2626	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemRead));
2627	}
2628	else
2629	{
2630	enmReqType = VTDREQTYPE_WRITE;
2631	fReqPerm = DMAR_PERM_WRITE;
2632	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMemWrite));
2633	}
2634
2635	uint8_t const fTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
2636	DMARMEMREQREMAP MemReqRemap;
2637	RT_ZERO(MemReqRemap);
2638	MemReqRemap.In.AddrRange.uAddr = uIova;
2639	MemReqRemap.In.AddrRange.cb = cbIova;
2640	MemReqRemap.In.AddrRange.fPerm = fReqPerm;
2641	MemReqRemap.In.idDevice = idDevice;
2642	MemReqRemap.In.Pasid = NIL_PCIPASID;
2643	MemReqRemap.In.enmAddrType = PCIADDRTYPE_UNTRANSLATED;
2644	MemReqRemap.In.enmReqType = enmReqType;
2645	MemReqRemap.Aux.fTtm = fTtm;
2646	MemReqRemap.Out.AddrRange.uAddr = NIL_RTGCPHYS;
2647
2648	int rc;
2649	switch (fTtm)
2650	{
2651	case VTD_TTM_LEGACY_MODE:
2652	{
2653	rc = dmarDrLegacyModeRemapAddr(pDevIns, uRtaddrReg, &MemReqRemap);
2654	break;
2655	}
2656
2657	case VTD_TTM_SCALABLE_MODE:
2658	{
2659	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_SMTS_MASK)
2660	rc = dmarDrScalableModeRemapAddr(pDevIns, uRtaddrReg, &MemReqRemap);
2661	else
2662	{
2663	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2664	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Smts_Not_Supported, &MemReqRemap.In, &MemReqRemap.Aux);
2665	}
2666	break;
2667	}
2668
2669	case VTD_TTM_ABORT_DMA_MODE:
2670	{
2671	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2672	if (pThis->fExtCapReg & VTD_BF_ECAP_REG_ADMS_MASK)
2673	dmarDrTargetAbort(pDevIns);
2674	else
2675	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Adms_Not_Supported, &MemReqRemap.In, &MemReqRemap.Aux);
2676	break;
2677	}
2678
2679	default:
2680	{
2681	rc = VERR_IOMMU_ADDR_TRANSLATION_FAILED;
2682	dmarAtFaultRecord(pDevIns, kDmarDiag_At_Rta_Rsvd, &MemReqRemap.In, &MemReqRemap.Aux);
2683	break;
2684	}
2685	}
2686
2687	*pGCPhysSpa = MemReqRemap.Out.AddrRange.uAddr;
2688	*pcbContiguous = MemReqRemap.Out.AddrRange.cb;
2689	return rc;
2690	}
2691
2692	*pGCPhysSpa = uIova;
2693	*pcbContiguous = cbIova;
2694	return VINF_SUCCESS;
2695	}
2696
2697
2698	/**
2699	* Reads an IRTE from guest memory.
2700	*
2701	* @returns VBox status code.
2702	* @param pDevIns The IOMMU device instance.
2703	* @param uIrtaReg The IRTA_REG.
2704	* @param idxIntr The interrupt index.
2705	* @param pIrte Where to store the read IRTE.
2706	*/
2707	static int dmarIrReadIrte(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idxIntr, PVTD_IRTE_T pIrte)
2708	{
2709	Assert(idxIntr < VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg));
2710
2711	size_t const cbIrte = sizeof(*pIrte);
2712	RTGCPHYS const GCPhysIrte = (uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK) + (idxIntr * cbIrte);
2713	return PDMDevHlpPhysReadMeta(pDevIns, GCPhysIrte, pIrte, cbIrte);
2714	}
2715
2716
2717	/**
2718	* Remaps the source MSI to the destination MSI given the IRTE.
2719	*
2720	* @param fExtIntrMode Whether extended interrupt mode is enabled (i.e
2721	* IRTA_REG.EIME).
2722	* @param pIrte The IRTE used for the remapping.
2723	* @param pMsiIn The source MSI (currently unused).
2724	* @param pMsiOut Where to store the remapped MSI.
2725	*/
2726	static void dmarIrRemapFromIrte(bool fExtIntrMode, PCVTD_IRTE_T pIrte, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2727	{
2728	NOREF(pMsiIn);
2729	uint64_t const uIrteQword0 = pIrte->au64[0];
2730
2731	/*
2732	* Let's start with a clean slate and preserve unspecified bits if the need arises.
2733	* For instance, address bits 1:0 is supposed to be "ignored" by remapping hardware,
2734	* but it's not clear if hardware zeroes out these bits in the remapped MSI or if
2735	* it copies it from the source MSI.
2736	*/
2737	RT_ZERO(*pMsiOut);
2738	pMsiOut->Addr.n.u1DestMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DM);
2739	pMsiOut->Addr.n.u1RedirHint = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_RH);
2740	pMsiOut->Addr.n.u12Addr = VBOX_MSI_ADDR_BASE >> VBOX_MSI_ADDR_SHIFT;
2741	if (fExtIntrMode)
2742	{
2743	/*
2744	* Apparently the DMAR stuffs the high 24-bits of the destination ID into the
2745	* high 24-bits of the upper 32-bits of the message address, see @bugref{9967#c22}.
2746	*/
2747	uint32_t const idDest = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST);
2748	pMsiOut->Addr.n.u8DestId = idDest;
2749	pMsiOut->Addr.n.u32Rsvd0 = idDest & UINT32_C(0xffffff00);
2750	}
2751	else
2752	pMsiOut->Addr.n.u8DestId = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DST_XAPIC);
2753
2754	pMsiOut->Data.n.u8Vector = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_V);
2755	pMsiOut->Data.n.u3DeliveryMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_DLM);
2756	pMsiOut->Data.n.u1Level = 1;
2757	pMsiOut->Data.n.u1TriggerMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_TM);
2758	}
2759
2760
2761	/**
2762	* Handles remapping of interrupts in remappable interrupt format.
2763	*
2764	* @returns VBox status code.
2765	* @param pDevIns The IOMMU device instance.
2766	* @param uIrtaReg The IRTA_REG.
2767	* @param idDevice The device ID (bus, device, function).
2768	* @param pMsiIn The source MSI.
2769	* @param pMsiOut Where to store the remapped MSI.
2770	*/
2771	static int dmarIrRemapIntr(PPDMDEVINS pDevIns, uint64_t uIrtaReg, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2772	{
2773	Assert(pMsiIn->Addr.dmar_remap.fIntrFormat == VTD_INTR_FORMAT_REMAPPABLE);
2774
2775	/* Validate reserved bits in the interrupt request. */
2776	AssertCompile(VTD_REMAPPABLE_MSI_ADDR_VALID_MASK == UINT32_MAX);
2777	if (!(pMsiIn->Data.u32 & ~VTD_REMAPPABLE_MSI_DATA_VALID_MASK))
2778	{
2779	/* Compute the index into the interrupt remap table. */
2780	uint16_t const uHandleHi = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_HI);
2781	uint16_t const uHandleLo = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_HANDLE_LO);
2782	uint16_t const uHandle = uHandleLo \| (uHandleHi << 15);
2783	bool const fSubHandleValid = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_SHV);
2784	uint16_t const idxIntr = fSubHandleValid
2785	? uHandle + RT_BF_GET(pMsiIn->Data.u32, VTD_BF_REMAPPABLE_MSI_DATA_SUBHANDLE)
2786	: uHandle;
2787
2788	/* Validate the index. */
2789	uint32_t const cEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
2790	if (idxIntr < cEntries)
2791	{
2792	/** @todo Implement and read IRTE from interrupt-entry cache here. */
2793
2794	/* Read the interrupt remap table entry (IRTE) at the index. */
2795	VTD_IRTE_T Irte;
2796	int rc = dmarIrReadIrte(pDevIns, uIrtaReg, idxIntr, &Irte);
2797	if (RT_SUCCESS(rc))
2798	{
2799	/* Check if the IRTE is present (this must be done -before- checking reserved bits). */
2800	uint64_t const uIrteQword0 = Irte.au64[0];
2801	uint64_t const uIrteQword1 = Irte.au64[1];
2802	bool const fPresent = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_P);
2803	if (fPresent)
2804	{
2805	/* Validate reserved bits in the IRTE. */
2806	bool const fExtIntrMode = RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME);
2807	uint64_t const fQw0ValidMask = fExtIntrMode ? VTD_IRTE_0_X2APIC_VALID_MASK : VTD_IRTE_0_XAPIC_VALID_MASK;
2808	if ( !(uIrteQword0 & ~fQw0ValidMask)
2809	&& !(uIrteQword1 & ~VTD_IRTE_1_VALID_MASK))
2810	{
2811	/* Validate requester id (the device ID) as configured in the IRTE. */
2812	bool fSrcValid;
2813	DMARDIAG enmIrDiag;
2814	uint8_t const fSvt = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SVT);
2815	switch (fSvt)
2816	{
2817	case VTD_IRTE_SVT_NONE:
2818	{
2819	fSrcValid = true;
2820	enmIrDiag = kDmarDiag_None;
2821	break;
2822	}
2823
2824	case VTD_IRTE_SVT_VALIDATE_MASK:
2825	{
2826	static uint16_t const s_afValidMasks[] = { 0xffff, 0xfffb, 0xfff9, 0xfff8 };
2827	uint8_t const idxMask = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SQ) & 3;
2828	uint16_t const fValidMask = s_afValidMasks[idxMask];
2829	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2830	fSrcValid = (idDevice & fValidMask) == (idSource & fValidMask);
2831	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Masked;
2832	break;
2833	}
2834
2835	case VTD_IRTE_SVT_VALIDATE_BUS_RANGE:
2836	{
2837	uint16_t const idSource = RT_BF_GET(uIrteQword1, VTD_BF_1_IRTE_SID);
2838	uint8_t const uBusFirst = RT_HI_U8(idSource);
2839	uint8_t const uBusLast = RT_LO_U8(idSource);
2840	uint8_t const idDeviceBus = idDevice >> VBOX_PCI_BUS_SHIFT;
2841	fSrcValid = (idDeviceBus >= uBusFirst && idDeviceBus <= uBusLast);
2842	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Bus;
2843	break;
2844	}
2845
2846	default:
2847	{
2848	fSrcValid = false;
2849	enmIrDiag = kDmarDiag_Ir_Rfi_Irte_Svt_Rsvd;
2850	break;
2851	}
2852	}
2853
2854	if (fSrcValid)
2855	{
2856	uint8_t const fPostedMode = RT_BF_GET(uIrteQword0, VTD_BF_0_IRTE_IM);
2857	if (!fPostedMode)
2858	{
2859	dmarIrRemapFromIrte(fExtIntrMode, &Irte, pMsiIn, pMsiOut);
2860	return VINF_SUCCESS;
2861	}
2862	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Mode_Invalid, idDevice, idxIntr, &Irte);
2863	}
2864	else
2865	dmarIrFaultRecord(pDevIns, enmIrDiag, idDevice, idxIntr, &Irte);
2866	}
2867	else
2868	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Rsvd, idDevice, idxIntr, &Irte);
2869	}
2870	else
2871	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Not_Present, idDevice, idxIntr, &Irte);
2872	}
2873	else
2874	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Irte_Read_Failed, idDevice, idxIntr, NULL /* pIrte */);
2875	}
2876	else
2877	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Intr_Index_Invalid, idDevice, idxIntr, NULL /* pIrte */);
2878	}
2879	else
2880	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Rfi_Rsvd, idDevice, 0 /* idxIntr /, NULL / pIrte */);
2881	return VERR_IOMMU_INTR_REMAP_DENIED;
2882	}
2883
2884
2885	/**
2886	* Interrupt remap request from a device.
2887	*
2888	* @returns VBox status code.
2889	* @param pDevIns The IOMMU device instance.
2890	* @param idDevice The device ID (bus, device, function).
2891	* @param pMsiIn The source MSI.
2892	* @param pMsiOut Where to store the remapped MSI.
2893	*/
2894	static DECLCALLBACK(int) iommuIntelMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
2895	{
2896	/* Validate. */
2897	Assert(pDevIns);
2898	Assert(pMsiIn);
2899	Assert(pMsiOut);
2900	RT_NOREF1(idDevice);
2901
2902	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2903	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2904
2905	/* Lock and read all registers required for interrupt remapping up-front. */
2906	DMAR_LOCK(pDevIns, pThisCC);
2907	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
2908	uint64_t const uIrtaReg = pThis->uIrtaReg;
2909	DMAR_UNLOCK(pDevIns, pThisCC);
2910
2911	/* Check if interrupt remapping is enabled. */
2912	if (uGstsReg & VTD_BF_GSTS_REG_IRES_MASK)
2913	{
2914	bool const fIsRemappable = RT_BF_GET(pMsiIn->Addr.au32[0], VTD_BF_REMAPPABLE_MSI_ADDR_INTR_FMT);
2915	if (!fIsRemappable)
2916	{
2917	/* Handle compatibility format interrupts. */
2918	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapCfi));
2919
2920	/* If EIME is enabled or CFIs are disabled, block the interrupt. */
2921	if ( (uIrtaReg & VTD_BF_IRTA_REG_EIME_MASK)
2922	\|\| !(uGstsReg & VTD_BF_GSTS_REG_CFIS_MASK))
2923	{
2924	dmarIrFaultRecord(pDevIns, kDmarDiag_Ir_Cfi_Blocked, VTDIRFAULT_CFI_BLOCKED, idDevice, 0 /* idxIntr */);
2925	return VERR_IOMMU_INTR_REMAP_DENIED;
2926	}
2927
2928	/* Interrupt isn't subject to remapping, pass-through the interrupt. */
2929	pMsiOut = pMsiIn;
2930	return VINF_SUCCESS;
2931	}
2932
2933	/* Handle remappable format interrupts. */
2934	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMsiRemapRfi));
2935	return dmarIrRemapIntr(pDevIns, uIrtaReg, idDevice, pMsiIn, pMsiOut);
2936	}
2937
2938	/* Interrupt-remapping isn't enabled, all interrupts are pass-through. */
2939	pMsiOut = pMsiIn;
2940	return VINF_SUCCESS;
2941	}
2942
2943
2944	/**
2945	* @callback_method_impl{FNIOMMMIONEWWRITE}
2946	*/
2947	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
2948	{
2949	RT_NOREF1(pvUser);
2950	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
2951
2952	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
2953	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioWrite));
2954
2955	uint16_t const offReg = off;
2956	uint16_t const offLast = offReg + cb - 1;
2957	if (DMAR_IS_MMIO_OFF_VALID(offLast))
2958	{
2959	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
2960	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_WRITE);
2961
2962	uint64_t uPrev = 0;
2963	uint64_t const uRegWritten = cb == 8 ? dmarRegWrite64(pThis, offReg, (uint64_t )pv, &uPrev)
2964	: dmarRegWrite32(pThis, offReg, (uint32_t )pv, (uint32_t *)&uPrev);
2965	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2966	switch (off)
2967	{
2968	case VTD_MMIO_OFF_GCMD_REG: /* 32-bit */
2969	{
2970	rcStrict = dmarGcmdRegWrite(pDevIns, uRegWritten);
2971	break;
2972	}
2973
2974	case VTD_MMIO_OFF_CCMD_REG: /* 64-bit */
2975	case VTD_MMIO_OFF_CCMD_REG + 4:
2976	{
2977	rcStrict = dmarCcmdRegWrite(pDevIns, offReg, cb, uRegWritten);
2978	break;
2979	}
2980
2981	case VTD_MMIO_OFF_FSTS_REG: /* 32-bit */
2982	{
2983	rcStrict = dmarFstsRegWrite(pDevIns, uRegWritten, uPrev);
2984	break;
2985	}
2986
2987	case VTD_MMIO_OFF_FECTL_REG: /* 32-bit */
2988	{
2989	rcStrict = dmarFectlRegWrite(pDevIns, uRegWritten);
2990	break;
2991	}
2992
2993	case VTD_MMIO_OFF_IQT_REG: /* 64-bit */
2994	/* VTD_MMIO_OFF_IQT_REG + 4: / / High 32-bits reserved. */
2995	{
2996	rcStrict = dmarIqtRegWrite(pDevIns, offReg, uRegWritten);
2997	break;
2998	}
2999
3000	case VTD_MMIO_OFF_IQA_REG: /* 64-bit */
3001	/* VTD_MMIO_OFF_IQA_REG + 4: / / High 32-bits data. */
3002	{
3003	rcStrict = dmarIqaRegWrite(pDevIns, offReg, uRegWritten);
3004	break;
3005	}
3006
3007	case VTD_MMIO_OFF_ICS_REG: /* 32-bit */
3008	{
3009	rcStrict = dmarIcsRegWrite(pDevIns, uRegWritten);
3010	break;
3011	}
3012
3013	case VTD_MMIO_OFF_IECTL_REG: /* 32-bit */
3014	{
3015	rcStrict = dmarIectlRegWrite(pDevIns, uRegWritten);
3016	break;
3017	}
3018
3019	case DMAR_MMIO_OFF_FRCD_HI_REG: /* 64-bit */
3020	case DMAR_MMIO_OFF_FRCD_HI_REG + 4:
3021	{
3022	rcStrict = dmarFrcdHiRegWrite(pDevIns, offReg, cb, uRegWritten, uPrev);
3023	break;
3024	}
3025	}
3026
3027	DMAR_UNLOCK(pDevIns, pThisCC);
3028	LogFlowFunc(("offReg=%#x uRegWritten=%#RX64 rc=%Rrc\n", offReg, uRegWritten, VBOXSTRICTRC_VAL(rcStrict)));
3029	return rcStrict;
3030	}
3031
3032	return VINF_IOM_MMIO_UNUSED_FF;
3033	}
3034
3035
3036	/**
3037	* @callback_method_impl{FNIOMMMIONEWREAD}
3038	*/
3039	static DECLCALLBACK(VBOXSTRICTRC) dmarMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3040	{
3041	RT_NOREF1(pvUser);
3042	DMAR_ASSERT_MMIO_ACCESS_RET(off, cb);
3043
3044	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3045	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatMmioRead));
3046
3047	uint16_t const offReg = off;
3048	uint16_t const offLast = offReg + cb - 1;
3049	if (DMAR_IS_MMIO_OFF_VALID(offLast))
3050	{
3051	PCDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARCC);
3052	DMAR_LOCK_RET(pDevIns, pThisCC, VINF_IOM_R3_MMIO_READ);
3053
3054	if (cb == 8)
3055	{
3056	(uint64_t )pv = dmarRegRead64(pThis, offReg);
3057	LogFlowFunc(("offReg=%#x pv=%#RX64\n", offReg, (uint64_t )pv));
3058	}
3059	else
3060	{
3061	(uint32_t )pv = dmarRegRead32(pThis, offReg);
3062	LogFlowFunc(("offReg=%#x pv=%#RX32\n", offReg, (uint32_t )pv));
3063	}
3064
3065	DMAR_UNLOCK(pDevIns, pThisCC);
3066	return VINF_SUCCESS;
3067	}
3068
3069	return VINF_IOM_MMIO_UNUSED_FF;
3070	}
3071
3072
3073	#ifdef IN_RING3
3074	/**
3075	* Process requests in the invalidation queue.
3076	*
3077	* @param pDevIns The IOMMU device instance.
3078	* @param pvRequests The requests to process.
3079	* @param cbRequests The size of all requests (in bytes).
3080	* @param fDw The descriptor width (VTD_IQA_REG_DW_128_BIT or
3081	* VTD_IQA_REG_DW_256_BIT).
3082	* @param fTtm The table translation mode. Must not be VTD_TTM_RSVD.
3083	*/
3084	static void dmarR3InvQueueProcessRequests(PPDMDEVINS pDevIns, void const *pvRequests, uint32_t cbRequests, uint8_t fDw,
3085	uint8_t fTtm)
3086	{
3087	#define DMAR_IQE_FAULT_RECORD_RET(a_enmDiag, a_enmIqei) \
3088	do \
3089	{ \
3090	dmarIqeFaultRecord(pDevIns, (a_enmDiag), (a_enmIqei)); \
3091	return; \
3092	} while (0)
3093
3094	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3095	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3096
3097	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3098	Assert(fTtm != VTD_TTM_RSVD); /* Should've beeen handled by caller. */
3099
3100	/*
3101	* The below check is redundant since we check both TTM and DW for each
3102	* descriptor type we process. However, the order of errors reported by hardware
3103	* may differ hence this is kept commented out but not removed if we need to
3104	* change this in the future.
3105	*
3106	* In our implementation, we would report the descriptor type as invalid,
3107	* while on real hardware it may report descriptor width as invalid.
3108	* The Intel VT-d spec. is not clear which error takes preceedence.
3109	*/
3110	#if 0
3111	/*
3112	* Verify that 128-bit descriptors are not used when operating in scalable mode.
3113	* We don't check this while software writes IQA_REG but defer it until now because
3114	* RTADDR_REG can be updated lazily (via GCMD_REG.SRTP). The 256-bit descriptor check
3115	* -IS- performed when software writes IQA_REG since it only requires checking against
3116	* immutable hardware features.
3117	*/
3118	if ( fTtm != VTD_TTM_SCALABLE_MODE
3119	\|\| fDw != VTD_IQA_REG_DW_128_BIT)
3120	{ /* likely */ }
3121	else
3122	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_IqaReg_Dw_128_Invalid, VTDIQEI_INVALID_DESCRIPTOR_WIDTH);
3123	#endif
3124
3125	/*
3126	* Process requests in FIFO order.
3127	*/
3128	uint8_t const cbDsc = fDw == VTD_IQA_REG_DW_256_BIT ? 32 : 16;
3129	for (uint32_t offDsc = 0; offDsc < cbRequests; offDsc += cbDsc)
3130	{
3131	uint64_t const puDscQwords = (uint64_t const )((uintptr_t)pvRequests + offDsc);
3132	uint64_t const uQword0 = puDscQwords[0];
3133	uint64_t const uQword1 = puDscQwords[1];
3134	uint8_t const fDscType = VTD_GENERIC_INV_DSC_GET_TYPE(uQword0);
3135	switch (fDscType)
3136	{
3137	case VTD_INV_WAIT_DSC_TYPE:
3138	{
3139	/* Validate descriptor type. */
3140	if ( fTtm == VTD_TTM_LEGACY_MODE
3141	\|\| fDw == VTD_IQA_REG_DW_256_BIT)
3142	{ /* likely */ }
3143	else
3144	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3145
3146	/* Validate reserved bits. */
3147	uint64_t const fValidMask0 = !(pThis->fExtCapReg & VTD_BF_ECAP_REG_PDS_MASK)
3148	? VTD_INV_WAIT_DSC_0_VALID_MASK & ~VTD_BF_0_INV_WAIT_DSC_PD_MASK
3149	: VTD_INV_WAIT_DSC_0_VALID_MASK;
3150	if ( !(uQword0 & ~fValidMask0)
3151	&& !(uQword1 & ~VTD_INV_WAIT_DSC_1_VALID_MASK))
3152	{ /* likely */ }
3153	else
3154	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_0_1_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3155
3156	if (fDw == VTD_IQA_REG_DW_256_BIT)
3157	{
3158	if ( !puDscQwords[2]
3159	&& !puDscQwords[3])
3160	{ /* likely */ }
3161	else
3162	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Inv_Wait_Dsc_2_3_Rsvd, VTDIQEI_RSVD_FIELD_VIOLATION);
3163	}
3164
3165	/* Perform status write (this must be done prior to generating the completion interrupt). */
3166	bool const fSw = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_SW);
3167	if (fSw)
3168	{
3169	uint32_t const uStatus = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_STDATA);
3170	RTGCPHYS const GCPhysStatus = uQword1 & VTD_BF_1_INV_WAIT_DSC_STADDR_MASK;
3171	int const rc = PDMDevHlpPhysWrite(pDevIns, GCPhysStatus, (void const*)&uStatus, sizeof(uStatus));
3172	AssertRC(rc);
3173	}
3174
3175	/* Generate invalidation event interrupt. */
3176	bool const fIf = RT_BF_GET(uQword0, VTD_BF_0_INV_WAIT_DSC_IF);
3177	if (fIf)
3178	{
3179	DMAR_LOCK(pDevIns, pThisR3);
3180	dmarR3InvEventRaiseInterrupt(pDevIns);
3181	DMAR_UNLOCK(pDevIns, pThisR3);
3182	}
3183
3184	STAM_COUNTER_INC(&pThis->StatInvWaitDsc);
3185	break;
3186	}
3187
3188	case VTD_CC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatCcInvDsc); break;
3189	case VTD_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIotlbInvDsc); break;
3190	case VTD_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatDevtlbInvDsc); break;
3191	case VTD_IEC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatIecInvDsc); break;
3192	case VTD_P_IOTLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidIotlbInvDsc); break;
3193	case VTD_PC_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidCacheInvDsc); break;
3194	case VTD_P_DEV_TLB_INV_DSC_TYPE: STAM_COUNTER_INC(&pThis->StatPasidDevtlbInvDsc); break;
3195	default:
3196	{
3197	/* Stop processing further requests. */
3198	LogFunc(("Invalid descriptor type: %#x\n", fDscType));
3199	DMAR_IQE_FAULT_RECORD_RET(kDmarDiag_Iqei_Dsc_Type_Invalid, VTDIQEI_INVALID_DESCRIPTOR_TYPE);
3200	}
3201	}
3202	}
3203	#undef DMAR_IQE_FAULT_RECORD_RET
3204	}
3205
3206
3207	/**
3208	* The invalidation-queue thread.
3209	*
3210	* @returns VBox status code.
3211	* @param pDevIns The IOMMU device instance.
3212	* @param pThread The command thread.
3213	*/
3214	static DECLCALLBACK(int) dmarR3InvQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3215	{
3216	NOREF(pThread);
3217	LogFlowFunc(("\n"));
3218
3219	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
3220	return VINF_SUCCESS;
3221
3222	/*
3223	* Pre-allocate the maximum size of the invalidation queue allowed by the spec.
3224	* This prevents trashing the heap as well as deal with out-of-memory situations
3225	* up-front while starting the VM. It also simplifies the code from having to
3226	* dynamically grow/shrink the allocation based on how software sizes the queue.
3227	* Guests normally don't alter the queue size all the time, but that's not an
3228	* assumption we can make.
3229	*/
3230	uint8_t const cMaxPages = 1 << VTD_BF_IQA_REG_QS_MASK;
3231	size_t const cbMaxQs = cMaxPages << X86_PAGE_SHIFT;
3232	void *pvRequests = RTMemAllocZ(cbMaxQs);
3233	AssertPtrReturn(pvRequests, VERR_NO_MEMORY);
3234
3235	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3236	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3237
3238	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
3239	{
3240	/*
3241	* Sleep until we are woken up.
3242	*/
3243	{
3244	int const rc = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pThis->hEvtInvQueue, RT_INDEFINITE_WAIT);
3245	AssertLogRelMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_INTERRUPTED, ("%Rrc\n", rc), rc);
3246	if (RT_UNLIKELY(pThread->enmState != PDMTHREADSTATE_RUNNING))
3247	break;
3248	}
3249
3250	DMAR_LOCK(pDevIns, pThisR3);
3251	if (dmarInvQueueCanProcessRequests(pThis))
3252	{
3253	uint32_t offQueueHead;
3254	uint32_t offQueueTail;
3255	bool const fIsEmpty = dmarInvQueueIsEmptyEx(pThis, &offQueueHead, &offQueueTail);
3256	if (!fIsEmpty)
3257	{
3258	/*
3259	* Get the current queue size, descriptor width, queue base address and the
3260	* table translation mode while the lock is still held.
3261	*/
3262	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3263	uint8_t const cQueuePages = 1 << (uIqaReg & VTD_BF_IQA_REG_QS_MASK);
3264	uint32_t const cbQueue = cQueuePages << X86_PAGE_SHIFT;
3265	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3266	uint8_t const fTtm = RT_BF_GET(pThis->uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3267	RTGCPHYS const GCPhysRequests = (uIqaReg & VTD_BF_IQA_REG_IQA_MASK) + offQueueHead;
3268
3269	/* Paranoia. */
3270	Assert(cbQueue <= cbMaxQs);
3271	Assert(!(offQueueTail & ~VTD_BF_IQT_REG_QT_MASK));
3272	Assert(!(offQueueHead & ~VTD_BF_IQH_REG_QH_MASK));
3273	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueTail & RT_BIT(4)));
3274	Assert(fDw != VTD_IQA_REG_DW_256_BIT \|\| !(offQueueHead & RT_BIT(4)));
3275	Assert(offQueueHead < cbQueue);
3276
3277	/*
3278	* A table translation mode of "reserved" isn't valid for any descriptor type.
3279	* However, RTADDR_REG can be modified in parallel to invalidation-queue processing,
3280	* but if ESRTPS is support, we will perform a global invalidation when software
3281	* changes RTADDR_REG, or it's the responsibility of software to do it explicitly.
3282	* So caching TTM while reading all descriptors should not be a problem.
3283	*
3284	* Also, validate the queue tail offset as it's mutable by software.
3285	*/
3286	if ( fTtm != VTD_TTM_RSVD
3287	&& offQueueTail < cbQueue)
3288	{
3289	/* Don't hold the lock while reading (a potentially large amount of) requests */
3290	DMAR_UNLOCK(pDevIns, pThisR3);
3291
3292	int rc;
3293	uint32_t cbRequests;
3294	if (offQueueTail > offQueueHead)
3295	{
3296	/* The requests have not wrapped around, read them in one go. */
3297	cbRequests = offQueueTail - offQueueHead;
3298	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbRequests);
3299	}
3300	else
3301	{
3302	/* The requests have wrapped around, read forward and wrapped-around. */
3303	uint32_t const cbForward = cbQueue - offQueueHead;
3304	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests, pvRequests, cbForward);
3305
3306	uint32_t const cbWrapped = offQueueTail;
3307	if ( RT_SUCCESS(rc)
3308	&& cbWrapped > 0)
3309	{
3310	rc = PDMDevHlpPhysReadMeta(pDevIns, GCPhysRequests + cbForward,
3311	(void *)((uintptr_t)pvRequests + cbForward), cbWrapped);
3312	}
3313	cbRequests = cbForward + cbWrapped;
3314	}
3315
3316	/* Re-acquire the lock since we need to update device state. */
3317	DMAR_LOCK(pDevIns, pThisR3);
3318
3319	if (RT_SUCCESS(rc))
3320	{
3321	/* Indicate to software we've fetched all requests. */
3322	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_IQH_REG, offQueueTail);
3323
3324	/* Don't hold the lock while processing requests. */
3325	DMAR_UNLOCK(pDevIns, pThisR3);
3326
3327	/* Process all requests. */
3328	Assert(cbRequests <= cbQueue);
3329	dmarR3InvQueueProcessRequests(pDevIns, pvRequests, cbRequests, fDw, fTtm);
3330
3331	/*
3332	* We've processed all requests and the lock shouldn't be held at this point.
3333	* Using 'continue' here allows us to skip re-acquiring the lock just to release
3334	* it again before going back to the thread loop. It's a bit ugly but it certainly
3335	* helps with performance.
3336	*/
3337	DMAR_ASSERT_LOCK_IS_NOT_OWNER(pDevIns, pThisR3);
3338	continue;
3339	}
3340	else
3341	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqaReg_Dsc_Fetch_Error, VTDIQEI_FETCH_DESCRIPTOR_ERR);
3342	}
3343	else
3344	{
3345	if (fTtm == VTD_TTM_RSVD)
3346	dmarIqeFaultRecord(pDevIns, kDmarDiag_Iqei_Ttm_Rsvd, VTDIQEI_INVALID_TTM);
3347	else
3348	{
3349	Assert(offQueueTail >= cbQueue);
3350	dmarIqeFaultRecord(pDevIns, kDmarDiag_IqtReg_Qt_Invalid, VTDIQEI_INVALID_TAIL_PTR);
3351	}
3352	}
3353	}
3354	}
3355	DMAR_UNLOCK(pDevIns, pThisR3);
3356	}
3357
3358	RTMemFree(pvRequests);
3359	pvRequests = NULL;
3360
3361	LogFlowFunc(("Invalidation-queue thread terminating\n"));
3362	return VINF_SUCCESS;
3363	}
3364
3365
3366	/**
3367	* Wakes up the invalidation-queue thread so it can respond to a state
3368	* change.
3369	*
3370	* @returns VBox status code.
3371	* @param pDevIns The IOMMU device instance.
3372	* @param pThread The invalidation-queue thread.
3373	*
3374	* @thread EMT.
3375	*/
3376	static DECLCALLBACK(int) dmarR3InvQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
3377	{
3378	RT_NOREF(pThread);
3379	LogFlowFunc(("\n"));
3380	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3381	return PDMDevHlpSUPSemEventSignal(pDevIns, pThis->hEvtInvQueue);
3382	}
3383
3384
3385	/**
3386	* @callback_method_impl{FNDBGFHANDLERDEV}
3387	*/
3388	static DECLCALLBACK(void) dmarR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3389	{
3390	PCDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3391	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3392	bool const fVerbose = RTStrCmp(pszArgs, "verbose") == 0;
3393
3394	/*
3395	* We lock the device to get a consistent register state as it is
3396	* ASSUMED pHlp->pfnPrintf is expensive, so we copy the registers (the
3397	* ones we care about here) into temporaries and release the lock ASAP.
3398	*
3399	* Order of register being read and outputted is in accordance with the
3400	* spec. for no particular reason.
3401	* See Intel VT-d spec. 10.4 "Register Descriptions".
3402	*/
3403	DMAR_LOCK(pDevIns, pThisR3);
3404
3405	DMARDIAG const enmDiag = pThis->enmDiag;
3406	uint32_t const uVerReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_VER_REG);
3407	uint64_t const uCapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CAP_REG);
3408	uint64_t const uEcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_ECAP_REG);
3409	uint32_t const uGcmdReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GCMD_REG);
3410	uint32_t const uGstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_GSTS_REG);
3411	uint64_t const uRtaddrReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_RTADDR_REG);
3412	uint64_t const uCcmdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_CCMD_REG);
3413	uint32_t const uFstsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FSTS_REG);
3414	uint32_t const uFectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FECTL_REG);
3415	uint32_t const uFedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEDATA_REG);
3416	uint32_t const uFeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEADDR_REG);
3417	uint32_t const uFeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_FEUADDR_REG);
3418	uint64_t const uAflogReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_AFLOG_REG);
3419	uint32_t const uPmenReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PMEN_REG);
3420	uint32_t const uPlmbaseReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMBASE_REG);
3421	uint32_t const uPlmlimitReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PLMLIMIT_REG);
3422	uint64_t const uPhmbaseReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMBASE_REG);
3423	uint64_t const uPhmlimitReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PHMLIMIT_REG);
3424	uint64_t const uIqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQH_REG);
3425	uint64_t const uIqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQT_REG);
3426	uint64_t const uIqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQA_REG);
3427	uint32_t const uIcsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_ICS_REG);
3428	uint32_t const uIectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IECTL_REG);
3429	uint32_t const uIedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEDATA_REG);
3430	uint32_t const uIeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEADDR_REG);
3431	uint32_t const uIeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_IEUADDR_REG);
3432	uint64_t const uIqercdReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IQERCD_REG);
3433	uint64_t const uIrtaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_IRTA_REG);
3434	uint64_t const uPqhReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQH_REG);
3435	uint64_t const uPqtReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQT_REG);
3436	uint64_t const uPqaReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_PQA_REG);
3437	uint32_t const uPrsReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PRS_REG);
3438	uint32_t const uPectlReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PECTL_REG);
3439	uint32_t const uPedataReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEDATA_REG);
3440	uint32_t const uPeaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEADDR_REG);
3441	uint32_t const uPeuaddrReg = dmarRegReadRaw32(pThis, VTD_MMIO_OFF_PEUADDR_REG);
3442	uint64_t const uMtrrcapReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRCAP_REG);
3443	uint64_t const uMtrrdefReg = dmarRegReadRaw64(pThis, VTD_MMIO_OFF_MTRRDEF_REG);
3444
3445	DMAR_UNLOCK(pDevIns, pThisR3);
3446
3447	const char *const pszDiag = enmDiag < RT_ELEMENTS(g_apszDmarDiagDesc) ? g_apszDmarDiagDesc[enmDiag] : "(Unknown)";
3448	pHlp->pfnPrintf(pHlp, "Intel-IOMMU:\n");
3449	pHlp->pfnPrintf(pHlp, " Diag = %s\n", pszDiag);
3450
3451	/*
3452	* Non-verbose output.
3453	*/
3454	if (!fVerbose)
3455	{
3456	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3457	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3458	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3459	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3460	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3461	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3462	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3463	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3464	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3465	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3466	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3467	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3468	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3469	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3470	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3471	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3472	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3473	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3474	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3475	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3476	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3477	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3478	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3479	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3480	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3481	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3482	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3483	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3484	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3485	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3486	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3487	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3488	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3489	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3490	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3491	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3492	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3493	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3494	pHlp->pfnPrintf(pHlp, "\n");
3495	return;
3496	}
3497
3498	/*
3499	* Verbose output.
3500	*/
3501	pHlp->pfnPrintf(pHlp, " VER_REG = %#RX32\n", uVerReg);
3502	{
3503	pHlp->pfnPrintf(pHlp, " MAJ = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MAX));
3504	pHlp->pfnPrintf(pHlp, " MIN = %#x\n", RT_BF_GET(uVerReg, VTD_BF_VER_REG_MIN));
3505	}
3506	pHlp->pfnPrintf(pHlp, " CAP_REG = %#RX64\n", uCapReg);
3507	{
3508	uint8_t const uMgaw = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MGAW);
3509	uint8_t const uNfr = RT_BF_GET(uCapReg, VTD_BF_CAP_REG_NFR);
3510	pHlp->pfnPrintf(pHlp, " ND = %u\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ND));
3511	pHlp->pfnPrintf(pHlp, " AFL = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_AFL));
3512	pHlp->pfnPrintf(pHlp, " RWBF = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_RWBF));
3513	pHlp->pfnPrintf(pHlp, " PLMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PLMR));
3514	pHlp->pfnPrintf(pHlp, " PHMR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PHMR));
3515	pHlp->pfnPrintf(pHlp, " CM = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_CM));
3516	pHlp->pfnPrintf(pHlp, " SAGAW = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SAGAW));
3517	pHlp->pfnPrintf(pHlp, " MGAW = %#x (%u bits)\n", uMgaw, uMgaw + 1);
3518	pHlp->pfnPrintf(pHlp, " ZLR = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ZLR));
3519	pHlp->pfnPrintf(pHlp, " FRO = %#x bytes\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FRO));
3520	pHlp->pfnPrintf(pHlp, " SLLPS = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_SLLPS));
3521	pHlp->pfnPrintf(pHlp, " PSI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PSI));
3522	pHlp->pfnPrintf(pHlp, " NFR = %u (%u FRCD register%s)\n", uNfr, uNfr + 1, uNfr > 0 ? "s" : "");
3523	pHlp->pfnPrintf(pHlp, " MAMV = %#x\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_MAMV));
3524	pHlp->pfnPrintf(pHlp, " DWD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DWD));
3525	pHlp->pfnPrintf(pHlp, " DRD = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_DRD));
3526	pHlp->pfnPrintf(pHlp, " FL1GP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL1GP));
3527	pHlp->pfnPrintf(pHlp, " PI = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_PI));
3528	pHlp->pfnPrintf(pHlp, " FL5LP = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_FL5LP));
3529	pHlp->pfnPrintf(pHlp, " ESIRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESIRTPS));
3530	pHlp->pfnPrintf(pHlp, " ESRTPS = %RTbool\n", RT_BF_GET(uCapReg, VTD_BF_CAP_REG_ESRTPS));
3531	}
3532	pHlp->pfnPrintf(pHlp, " ECAP_REG = %#RX64\n", uEcapReg);
3533	{
3534	uint8_t const uPss = RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PSS);
3535	pHlp->pfnPrintf(pHlp, " C = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_C));
3536	pHlp->pfnPrintf(pHlp, " QI = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_QI));
3537	pHlp->pfnPrintf(pHlp, " DT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DT));
3538	pHlp->pfnPrintf(pHlp, " IR = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IR));
3539	pHlp->pfnPrintf(pHlp, " EIM = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EIM));
3540	pHlp->pfnPrintf(pHlp, " PT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PT));
3541	pHlp->pfnPrintf(pHlp, " SC = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SC));
3542	pHlp->pfnPrintf(pHlp, " IRO = %#x bytes\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_IRO));
3543	pHlp->pfnPrintf(pHlp, " MHMV = %#x\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MHMV));
3544	pHlp->pfnPrintf(pHlp, " MTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_MTS));
3545	pHlp->pfnPrintf(pHlp, " NEST = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NEST));
3546	pHlp->pfnPrintf(pHlp, " PRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PRS));
3547	pHlp->pfnPrintf(pHlp, " ERS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ERS));
3548	pHlp->pfnPrintf(pHlp, " SRS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SRS));
3549	pHlp->pfnPrintf(pHlp, " NWFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_NWFS));
3550	pHlp->pfnPrintf(pHlp, " EAFS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_EAFS));
3551	pHlp->pfnPrintf(pHlp, " PSS = %u (%u bits)\n", uPss, uPss > 0 ? uPss + 1 : 0);
3552	pHlp->pfnPrintf(pHlp, " PASID = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PASID));
3553	pHlp->pfnPrintf(pHlp, " DIT = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_DIT));
3554	pHlp->pfnPrintf(pHlp, " PDS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_PDS));
3555	pHlp->pfnPrintf(pHlp, " SMTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMTS));
3556	pHlp->pfnPrintf(pHlp, " VCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_VCS));
3557	pHlp->pfnPrintf(pHlp, " SLADS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLADS));
3558	pHlp->pfnPrintf(pHlp, " SLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SLTS));
3559	pHlp->pfnPrintf(pHlp, " FLTS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_FLTS));
3560	pHlp->pfnPrintf(pHlp, " SMPWCS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_SMPWCS));
3561	pHlp->pfnPrintf(pHlp, " RPS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPS));
3562	pHlp->pfnPrintf(pHlp, " ADMS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_ADMS));
3563	pHlp->pfnPrintf(pHlp, " RPRIVS = %RTbool\n", RT_BF_GET(uEcapReg, VTD_BF_ECAP_REG_RPRIVS));
3564	}
3565	pHlp->pfnPrintf(pHlp, " GCMD_REG = %#RX32\n", uGcmdReg);
3566	{
3567	uint8_t const fCfi = RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_CFI);
3568	pHlp->pfnPrintf(pHlp, " CFI = %u (%s)\n", fCfi, fCfi ? "Passthrough" : "Blocked");
3569	pHlp->pfnPrintf(pHlp, " SIRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SIRTP));
3570	pHlp->pfnPrintf(pHlp, " IRE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_IRE));
3571	pHlp->pfnPrintf(pHlp, " QIE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_QIE));
3572	pHlp->pfnPrintf(pHlp, " WBF = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_WBF));
3573	pHlp->pfnPrintf(pHlp, " EAFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3574	pHlp->pfnPrintf(pHlp, " SFL = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SFL));
3575	pHlp->pfnPrintf(pHlp, " SRTP = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_SRTP));
3576	pHlp->pfnPrintf(pHlp, " TE = %u\n", RT_BF_GET(uGcmdReg, VTD_BF_GCMD_REG_TE));
3577	}
3578	pHlp->pfnPrintf(pHlp, " GSTS_REG = %#RX32\n", uGstsReg);
3579	{
3580	uint8_t const fCfis = RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_CFIS);
3581	pHlp->pfnPrintf(pHlp, " CFIS = %u (%s)\n", fCfis, fCfis ? "Passthrough" : "Blocked");
3582	pHlp->pfnPrintf(pHlp, " IRTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRTPS));
3583	pHlp->pfnPrintf(pHlp, " IRES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_IRES));
3584	pHlp->pfnPrintf(pHlp, " QIES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_QIES));
3585	pHlp->pfnPrintf(pHlp, " WBFS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_WBFS));
3586	pHlp->pfnPrintf(pHlp, " AFLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_AFLS));
3587	pHlp->pfnPrintf(pHlp, " FLS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_FLS));
3588	pHlp->pfnPrintf(pHlp, " RTPS = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_RTPS));
3589	pHlp->pfnPrintf(pHlp, " TES = %u\n", RT_BF_GET(uGstsReg, VTD_BF_GSTS_REG_TES));
3590	}
3591	pHlp->pfnPrintf(pHlp, " RTADDR_REG = %#RX64\n", uRtaddrReg);
3592	{
3593	uint8_t const uTtm = RT_BF_GET(uRtaddrReg, VTD_BF_RTADDR_REG_TTM);
3594	pHlp->pfnPrintf(pHlp, " RTA = %#RX64\n", uRtaddrReg & VTD_BF_RTADDR_REG_RTA_MASK);
3595	pHlp->pfnPrintf(pHlp, " TTM = %u (%s)\n", uTtm, vtdRtaddrRegGetTtmDesc(uTtm));
3596	}
3597	pHlp->pfnPrintf(pHlp, " CCMD_REG = %#RX64\n", uCcmdReg);
3598	pHlp->pfnPrintf(pHlp, " FSTS_REG = %#RX32\n", uFstsReg);
3599	{
3600	pHlp->pfnPrintf(pHlp, " PFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PFO));
3601	pHlp->pfnPrintf(pHlp, " PPF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_PPF));
3602	pHlp->pfnPrintf(pHlp, " AFO = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_AFO));
3603	pHlp->pfnPrintf(pHlp, " APF = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_APF));
3604	pHlp->pfnPrintf(pHlp, " IQE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_IQE));
3605	pHlp->pfnPrintf(pHlp, " ICS = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ICE));
3606	pHlp->pfnPrintf(pHlp, " ITE = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_ITE));
3607	pHlp->pfnPrintf(pHlp, " FRI = %u\n", RT_BF_GET(uFstsReg, VTD_BF_FSTS_REG_FRI));
3608	}
3609	pHlp->pfnPrintf(pHlp, " FECTL_REG = %#RX32\n", uFectlReg);
3610	{
3611	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IM));
3612	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uFectlReg, VTD_BF_FECTL_REG_IP));
3613	}
3614	pHlp->pfnPrintf(pHlp, " FEDATA_REG = %#RX32\n", uFedataReg);
3615	pHlp->pfnPrintf(pHlp, " FEADDR_REG = %#RX32\n", uFeaddrReg);
3616	pHlp->pfnPrintf(pHlp, " FEUADDR_REG = %#RX32\n", uFeuaddrReg);
3617	pHlp->pfnPrintf(pHlp, " AFLOG_REG = %#RX64\n", uAflogReg);
3618	pHlp->pfnPrintf(pHlp, " PMEN_REG = %#RX32\n", uPmenReg);
3619	pHlp->pfnPrintf(pHlp, " PLMBASE_REG = %#RX32\n", uPlmbaseReg);
3620	pHlp->pfnPrintf(pHlp, " PLMLIMIT_REG = %#RX32\n", uPlmlimitReg);
3621	pHlp->pfnPrintf(pHlp, " PHMBASE_REG = %#RX64\n", uPhmbaseReg);
3622	pHlp->pfnPrintf(pHlp, " PHMLIMIT_REG = %#RX64\n", uPhmlimitReg);
3623	pHlp->pfnPrintf(pHlp, " IQH_REG = %#RX64\n", uIqhReg);
3624	pHlp->pfnPrintf(pHlp, " IQT_REG = %#RX64\n", uIqtReg);
3625	pHlp->pfnPrintf(pHlp, " IQA_REG = %#RX64\n", uIqaReg);
3626	{
3627	uint8_t const fDw = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_DW);
3628	uint8_t const fQs = RT_BF_GET(uIqaReg, VTD_BF_IQA_REG_QS);
3629	uint8_t const cQueuePages = 1 << fQs;
3630	pHlp->pfnPrintf(pHlp, " DW = %u (%s)\n", fDw, fDw == VTD_IQA_REG_DW_128_BIT ? "128-bit" : "256-bit");
3631	pHlp->pfnPrintf(pHlp, " QS = %u (%u page%s)\n", fQs, cQueuePages, cQueuePages > 1 ? "s" : "");
3632	}
3633	pHlp->pfnPrintf(pHlp, " ICS_REG = %#RX32\n", uIcsReg);
3634	{
3635	pHlp->pfnPrintf(pHlp, " IWC = %u\n", RT_BF_GET(uIcsReg, VTD_BF_ICS_REG_IWC));
3636	}
3637	pHlp->pfnPrintf(pHlp, " IECTL_REG = %#RX32\n", uIectlReg);
3638	{
3639	pHlp->pfnPrintf(pHlp, " IM = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IM));
3640	pHlp->pfnPrintf(pHlp, " IP = %RTbool\n", RT_BF_GET(uIectlReg, VTD_BF_IECTL_REG_IP));
3641	}
3642	pHlp->pfnPrintf(pHlp, " IEDATA_REG = %#RX32\n", uIedataReg);
3643	pHlp->pfnPrintf(pHlp, " IEADDR_REG = %#RX32\n", uIeaddrReg);
3644	pHlp->pfnPrintf(pHlp, " IEUADDR_REG = %#RX32\n", uIeuaddrReg);
3645	pHlp->pfnPrintf(pHlp, " IQERCD_REG = %#RX64\n", uIqercdReg);
3646	{
3647	pHlp->pfnPrintf(pHlp, " ICESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ICESID));
3648	pHlp->pfnPrintf(pHlp, " ITESID = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_ITESID));
3649	pHlp->pfnPrintf(pHlp, " IQEI = %#RX32\n", RT_BF_GET(uIqercdReg, VTD_BF_IQERCD_REG_IQEI));
3650	}
3651	pHlp->pfnPrintf(pHlp, " IRTA_REG = %#RX64\n", uIrtaReg);
3652	{
3653	uint32_t const cIrtEntries = VTD_IRTA_REG_GET_ENTRY_COUNT(uIrtaReg);
3654	uint32_t const cbIrt = sizeof(VTD_IRTE_T) * cIrtEntries;
3655	pHlp->pfnPrintf(pHlp, " IRTA = %#RX64\n", uIrtaReg & VTD_BF_IRTA_REG_IRTA_MASK);
3656	pHlp->pfnPrintf(pHlp, " EIME = %RTbool\n", RT_BF_GET(uIrtaReg, VTD_BF_IRTA_REG_EIME));
3657	pHlp->pfnPrintf(pHlp, " S = %u entries (%u bytes)\n", cIrtEntries, cbIrt);
3658	}
3659	pHlp->pfnPrintf(pHlp, " PQH_REG = %#RX64\n", uPqhReg);
3660	pHlp->pfnPrintf(pHlp, " PQT_REG = %#RX64\n", uPqtReg);
3661	pHlp->pfnPrintf(pHlp, " PQA_REG = %#RX64\n", uPqaReg);
3662	pHlp->pfnPrintf(pHlp, " PRS_REG = %#RX32\n", uPrsReg);
3663	pHlp->pfnPrintf(pHlp, " PECTL_REG = %#RX32\n", uPectlReg);
3664	pHlp->pfnPrintf(pHlp, " PEDATA_REG = %#RX32\n", uPedataReg);
3665	pHlp->pfnPrintf(pHlp, " PEADDR_REG = %#RX32\n", uPeaddrReg);
3666	pHlp->pfnPrintf(pHlp, " PEUADDR_REG = %#RX32\n", uPeuaddrReg);
3667	pHlp->pfnPrintf(pHlp, " MTRRCAP_REG = %#RX64\n", uMtrrcapReg);
3668	pHlp->pfnPrintf(pHlp, " MTRRDEF_REG = %#RX64\n", uMtrrdefReg);
3669	pHlp->pfnPrintf(pHlp, "\n");
3670	}
3671
3672
3673	/**
3674	* Initializes all registers in the DMAR unit.
3675	*
3676	* @param pDevIns The IOMMU device instance.
3677	*/
3678	static void dmarR3RegsInit(PPDMDEVINS pDevIns)
3679	{
3680	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3681
3682	/*
3683	* Wipe all registers (required on reset).
3684	*/
3685	RT_ZERO(pThis->abRegs0);
3686	RT_ZERO(pThis->abRegs1);
3687
3688	/*
3689	* Initialize registers not mutable by software prior to initializing other registers.
3690	*/
3691	/* VER_REG */
3692	{
3693	pThis->uVerReg = RT_BF_MAKE(VTD_BF_VER_REG_MIN, DMAR_VER_MINOR)
3694	\| RT_BF_MAKE(VTD_BF_VER_REG_MAX, DMAR_VER_MAJOR);
3695	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_VER_REG, pThis->uVerReg);
3696	}
3697
3698	uint8_t const fFlts = 1; /* First-level translation support. */
3699	uint8_t const fSlts = 1; /* Second-level translation support. */
3700	uint8_t const fPt = 1; /* Pass-Through support. */
3701	uint8_t const fSmts = fFlts & fSlts & fPt; /* Scalable mode translation support.*/
3702	uint8_t const fNest = 0; /* Nested translation support. */
3703
3704	/* CAP_REG */
3705	{
3706	uint8_t cGstPhysAddrBits;
3707	uint8_t cGstLinearAddrBits;
3708	PDMDevHlpCpuGetGuestAddrWidths(pDevIns, &cGstPhysAddrBits, &cGstLinearAddrBits);
3709
3710	uint8_t const fFl1gp = 1; /* First-level 1GB pages support. */
3711	uint8_t const fFl5lp = 1; /* First-level 5-level paging support (PML5E). */
3712	uint8_t const fSl2mp = 1; /* Second-level 2MB pages support. */
3713	uint8_t const fSl2gp = fSl2mp & 1; /* Second-level 1GB pages support. */
3714	uint8_t const fSllps = fSl2mp \| (fSl2gp << 1); /* Second-level large page support. */
3715	uint8_t const fMamv = (fSl2gp ? X86_PAGE_1G_SHIFT /* Maximum address mask value (for 2nd-level invalidations). */
3716	: X86_PAGE_2M_SHIFT)
3717	- X86_PAGE_4K_SHIFT;
3718	uint8_t const fNd = DMAR_ND; /* Number of domains supported. */
3719	uint8_t const fPsi = 1; /* Page selective invalidation. */
3720	uint8_t const uMgaw = cGstPhysAddrBits - 1; /* Maximum guest address width. */
3721	uint8_t const fSagaw = vtdCapRegGetSagaw(uMgaw); /* Supported adjust guest address width. */
3722	uint16_t const offFro = DMAR_MMIO_OFF_FRCD_LO_REG >> 4; /* MMIO offset of FRCD registers. */
3723	uint8_t const fEsrtps = 1; /* Enhanced SRTPS (auto invalidate cache on SRTP). */
3724	uint8_t const fEsirtps = 1; /* Enhanced SIRTPS (auto invalidate cache on SIRTP). */
3725	AssertCompile(DMAR_ND <= 6);
3726
3727	pThis->fCapReg = RT_BF_MAKE(VTD_BF_CAP_REG_ND, fNd)
3728	\| RT_BF_MAKE(VTD_BF_CAP_REG_AFL, 0) /* Advanced fault logging not supported. */
3729	\| RT_BF_MAKE(VTD_BF_CAP_REG_RWBF, 0) /* Software need not flush write-buffers. */
3730	\| RT_BF_MAKE(VTD_BF_CAP_REG_PLMR, 0) /* Protected Low-Memory Region not supported. */
3731	\| RT_BF_MAKE(VTD_BF_CAP_REG_PHMR, 0) /* Protected High-Memory Region not supported. */
3732	\| RT_BF_MAKE(VTD_BF_CAP_REG_CM, 1) /* Software should invalidate on mapping structure changes. */
3733	\| RT_BF_MAKE(VTD_BF_CAP_REG_SAGAW, fSlts ? fSagaw : 0)
3734	\| RT_BF_MAKE(VTD_BF_CAP_REG_MGAW, uMgaw)
3735	\| RT_BF_MAKE(VTD_BF_CAP_REG_ZLR, 1) /** @todo Figure out if/how to support zero-length reads. */
3736	\| RT_BF_MAKE(VTD_BF_CAP_REG_FRO, offFro)
3737	\| RT_BF_MAKE(VTD_BF_CAP_REG_SLLPS, fSlts & fSllps)
3738	\| RT_BF_MAKE(VTD_BF_CAP_REG_PSI, fPsi)
3739	\| RT_BF_MAKE(VTD_BF_CAP_REG_NFR, DMAR_FRCD_REG_COUNT - 1)
3740	\| RT_BF_MAKE(VTD_BF_CAP_REG_MAMV, fPsi & fMamv)
3741	\| RT_BF_MAKE(VTD_BF_CAP_REG_DWD, 1)
3742	\| RT_BF_MAKE(VTD_BF_CAP_REG_DRD, 1)
3743	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL1GP, fFlts & fFl1gp)
3744	\| RT_BF_MAKE(VTD_BF_CAP_REG_PI, 0) /* Posted Interrupts not supported. */
3745	\| RT_BF_MAKE(VTD_BF_CAP_REG_FL5LP, fFlts & fFl5lp)
3746	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESIRTPS, fEsirtps)
3747	\| RT_BF_MAKE(VTD_BF_CAP_REG_ESRTPS, fEsrtps);
3748	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_CAP_REG, pThis->fCapReg);
3749
3750	pThis->fHawBaseMask = ~(UINT64_MAX << cGstPhysAddrBits) & X86_PAGE_4K_BASE_MASK;
3751	pThis->fMgawInvMask = UINT64_MAX << cGstPhysAddrBits;
3752	pThis->cMaxPagingLevel = vtdCapRegGetMaxPagingLevel(fSagaw);
3753	}
3754
3755	/* ECAP_REG */
3756	{
3757	uint8_t const fQi = 1; /* Queued-invalidations. */
3758	uint8_t const fIr = !!(DMAR_ACPI_DMAR_FLAGS & ACPI_DMAR_F_INTR_REMAP); /* Interrupt remapping support. */
3759	uint8_t const fMhmv = 0xf; /* Maximum handle mask value. */
3760	uint16_t const offIro = DMAR_MMIO_OFF_IVA_REG >> 4; /* MMIO offset of IOTLB registers. */
3761	uint8_t const fEim = 1; /* Extended interrupt mode.*/
3762	uint8_t const fAdms = 1; /* Abort DMA mode support. */
3763	uint8_t const fErs = 0; /* Execute Request (not supported). */
3764
3765	pThis->fExtCapReg = RT_BF_MAKE(VTD_BF_ECAP_REG_C, 0) /* Accesses don't snoop CPU cache. */
3766	\| RT_BF_MAKE(VTD_BF_ECAP_REG_QI, fQi)
3767	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DT, 0) /* Device-TLBs not supported. */
3768	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IR, fQi & fIr)
3769	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EIM, fIr & fEim)
3770	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PT, fPt)
3771	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SC, 0) /* Snoop control not supported. */
3772	\| RT_BF_MAKE(VTD_BF_ECAP_REG_IRO, offIro)
3773	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MHMV, fIr & fMhmv)
3774	\| RT_BF_MAKE(VTD_BF_ECAP_REG_MTS, 0) /* Memory type not supported. */
3775	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NEST, fNest)
3776	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PRS, 0) /* 0 as DT not supported. */
3777	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ERS, fErs)
3778	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SRS, 0) /* Supervisor request not supported. */
3779	\| RT_BF_MAKE(VTD_BF_ECAP_REG_NWFS, 0) /* 0 as DT not supported. */
3780	\| RT_BF_MAKE(VTD_BF_ECAP_REG_EAFS, 0) /* 0 as SMPWCS not supported. */
3781	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PSS, 0) /* 0 as PASID not supported. */
3782	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PASID, 0) /* PASID not supported. */
3783	\| RT_BF_MAKE(VTD_BF_ECAP_REG_DIT, 0) /* 0 as DT not supported. */
3784	\| RT_BF_MAKE(VTD_BF_ECAP_REG_PDS, 0) /* 0 as DT not supported. */
3785	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMTS, fSmts)
3786	\| RT_BF_MAKE(VTD_BF_ECAP_REG_VCS, 0) /* 0 as PASID not supported (commands seem PASID specific). */
3787	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLADS, 0) /* Second-level accessed/dirty not supported. */
3788	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SLTS, fSlts)
3789	\| RT_BF_MAKE(VTD_BF_ECAP_REG_FLTS, fFlts)
3790	\| RT_BF_MAKE(VTD_BF_ECAP_REG_SMPWCS, 0) /* 0 as PASID not supported. */
3791	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPS, 0) /* We don't support RID_PASID field in SM context entry. */
3792	\| RT_BF_MAKE(VTD_BF_ECAP_REG_ADMS, fAdms)
3793	\| RT_BF_MAKE(VTD_BF_ECAP_REG_RPRIVS, 0); /* 0 as SRS not supported. */
3794	dmarRegWriteRaw64(pThis, VTD_MMIO_OFF_ECAP_REG, pThis->fExtCapReg);
3795
3796	pThis->fPermValidMask = DMAR_PERM_READ \| DMAR_PERM_WRITE;
3797	if (fErs)
3798	pThis->fPermValidMask = DMAR_PERM_EXE;
3799	}
3800
3801	/*
3802	* Initialize registers mutable by software.
3803	*/
3804	/* FECTL_REG */
3805	{
3806	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_FECTL_REG_IM, 1);
3807	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_FECTL_REG, uCtl);
3808	}
3809
3810	/* ICETL_REG */
3811	{
3812	uint32_t const uCtl = RT_BF_MAKE(VTD_BF_IECTL_REG_IM, 1);
3813	dmarRegWriteRaw32(pThis, VTD_MMIO_OFF_IECTL_REG, uCtl);
3814	}
3815
3816	#ifdef VBOX_STRICT
3817	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_PRS)); /* PECTL_REG - Reserved if don't support PRS. */
3818	Assert(!RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_MTS)); /* MTRRCAP_REG - Reserved if we don't support MTS. */
3819	#endif
3820	}
3821
3822
3823	/**
3824	* @interface_method_impl{PDMDEVREG,pfnReset}
3825	*/
3826	static DECLCALLBACK(void) iommuIntelR3Reset(PPDMDEVINS pDevIns)
3827	{
3828	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3829	LogFlowFunc(("\n"));
3830
3831	DMAR_LOCK(pDevIns, pThisR3);
3832	dmarR3RegsInit(pDevIns);
3833	DMAR_UNLOCK(pDevIns, pThisR3);
3834	}
3835
3836
3837	/**
3838	* @interface_method_impl{PDMDEVREG,pfnDestruct}
3839	*/
3840	static DECLCALLBACK(int) iommuIntelR3Destruct(PPDMDEVINS pDevIns)
3841	{
3842	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3843	PCDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PCDMARR3);
3844	LogFlowFunc(("\n"));
3845
3846	DMAR_LOCK(pDevIns, pThisR3);
3847
3848	if (pThis->hEvtInvQueue != NIL_SUPSEMEVENT)
3849	{
3850	PDMDevHlpSUPSemEventClose(pDevIns, pThis->hEvtInvQueue);
3851	pThis->hEvtInvQueue = NIL_SUPSEMEVENT;
3852	}
3853
3854	DMAR_UNLOCK(pDevIns, pThisR3);
3855	return VINF_SUCCESS;
3856	}
3857
3858
3859	/**
3860	* @interface_method_impl{PDMDEVREG,pfnConstruct}
3861	*/
3862	static DECLCALLBACK(int) iommuIntelR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
3863	{
3864	RT_NOREF(pCfg);
3865
3866	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
3867	PDMARR3 pThisR3 = PDMDEVINS_2_DATA_CC(pDevIns, PDMARR3);
3868	pThisR3->pDevInsR3 = pDevIns;
3869
3870	LogFlowFunc(("iInstance=%d\n", iInstance));
3871	NOREF(iInstance);
3872
3873	/*
3874	* Register the IOMMU with PDM.
3875	*/
3876	PDMIOMMUREGR3 IommuReg;
3877	RT_ZERO(IommuReg);
3878	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
3879	IommuReg.pfnMemAccess = iommuIntelMemAccess;
3880	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
3881	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
3882	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
3883	int rc = PDMDevHlpIommuRegister(pDevIns, &IommuReg, &pThisR3->CTX_SUFF(pIommuHlp), &pThis->idxIommu);
3884	if (RT_FAILURE(rc))
3885	return PDMDEV_SET_ERROR(pDevIns, rc, N_("Failed to register ourselves as an IOMMU device"));
3886	if (pThisR3->CTX_SUFF(pIommuHlp)->u32Version != PDM_IOMMUHLPR3_VERSION)
3887	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3888	N_("IOMMU helper version mismatch; got %#x expected %#x"),
3889	pThisR3->CTX_SUFF(pIommuHlp)->u32Version, PDM_IOMMUHLPR3_VERSION);
3890	if (pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd != PDM_IOMMUHLPR3_VERSION)
3891	return PDMDevHlpVMSetError(pDevIns, VERR_VERSION_MISMATCH, RT_SRC_POS,
3892	N_("IOMMU helper end-version mismatch; got %#x expected %#x"),
3893	pThisR3->CTX_SUFF(pIommuHlp)->u32TheEnd, PDM_IOMMUHLPR3_VERSION);
3894	AssertPtr(pThisR3->pIommuHlpR3->pfnLock);
3895	AssertPtr(pThisR3->pIommuHlpR3->pfnUnlock);
3896	AssertPtr(pThisR3->pIommuHlpR3->pfnLockIsOwner);
3897	AssertPtr(pThisR3->pIommuHlpR3->pfnSendMsi);
3898
3899	/*
3900	* Use PDM's critical section (via helpers) for the IOMMU device.
3901	*/
3902	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
3903	AssertRCReturn(rc, rc);
3904
3905	/*
3906	* Initialize PCI configuration registers.
3907	*/
3908	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
3909	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
3910
3911	/* Header. */
3912	PDMPciDevSetVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3913	PDMPciDevSetDeviceId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3914	PDMPciDevSetRevisionId(pPciDev, DMAR_PCI_REVISION_ID); /* VirtualBox specific device implementation revision */
3915	PDMPciDevSetClassBase(pPciDev, VBOX_PCI_CLASS_SYSTEM); /* System Base Peripheral */
3916	PDMPciDevSetClassSub(pPciDev, VBOX_PCI_SUB_SYSTEM_OTHER); /* Other */
3917	PDMPciDevSetHeaderType(pPciDev, 0); /* Single function, type 0 */
3918	PDMPciDevSetSubSystemId(pPciDev, DMAR_PCI_DEVICE_ID); /* VirtualBox DMAR device */
3919	PDMPciDevSetSubSystemVendorId(pPciDev, DMAR_PCI_VENDOR_ID); /* Intel */
3920
3921	/** @todo Chipset spec says PCI Express Capability Id. Relevant for us? */
3922	PDMPciDevSetStatus(pPciDev, 0);
3923	PDMPciDevSetCapabilityList(pPciDev, 0);
3924
3925	/** @todo VTBAR at 0x180? */
3926
3927	/*
3928	* Register the PCI function with PDM.
3929	*/
3930	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
3931	AssertLogRelRCReturn(rc, rc);
3932
3933	/** @todo Register MSI but what's the MSI capability offset? */
3934	#if 0
3935	/*
3936	* Register MSI support for the PCI device.
3937	* This must be done -after- registering it as a PCI device!
3938	*/
3939	#endif
3940
3941	/*
3942	* Register MMIO region.
3943	*/
3944	AssertCompile(!(DMAR_MMIO_BASE_PHYSADDR & X86_PAGE_4K_OFFSET_MASK));
3945	rc = PDMDevHlpMmioCreateAndMap(pDevIns, DMAR_MMIO_BASE_PHYSADDR, DMAR_MMIO_SIZE, dmarMmioWrite, dmarMmioRead,
3946	IOMMMIO_FLAGS_READ_DWORD_QWORD \| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED, "Intel-IOMMU",
3947	&pThis->hMmio);
3948	AssertLogRelRCReturn(rc, rc);
3949
3950	/*
3951	* Register debugger info items.
3952	*/
3953	rc = PDMDevHlpDBGFInfoRegister(pDevIns, "iommu", "Display IOMMU state.", dmarR3DbgInfo);
3954	AssertLogRelRCReturn(rc, rc);
3955
3956	#ifdef VBOX_WITH_STATISTICS
3957	/*
3958	* Statistics.
3959	*/
3960	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadR3, STAMTYPE_COUNTER, "R3/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in R3");
3961	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioReadRZ, STAMTYPE_COUNTER, "RZ/MmioRead", STAMUNIT_OCCURENCES, "Number of MMIO reads in RZ.");
3962
3963	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteR3, STAMTYPE_COUNTER, "R3/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in R3.");
3964	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMmioWriteRZ, STAMTYPE_COUNTER, "RZ/MmioWrite", STAMUNIT_OCCURENCES, "Number of MMIO writes in RZ.");
3965
3966	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiR3, STAMTYPE_COUNTER, "R3/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in R3.");
3967	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapCfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapCfi", STAMUNIT_OCCURENCES, "Number of compatibility-format interrupt remap requests in RZ.");
3968	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiR3, STAMTYPE_COUNTER, "R3/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in R3.");
3969	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMsiRemapRfiRZ, STAMTYPE_COUNTER, "RZ/MsiRemapRfi", STAMUNIT_OCCURENCES, "Number of remappable-format interrupt remap requests in RZ.");
3970
3971	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadR3, STAMTYPE_COUNTER, "R3/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in R3.");
3972	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemReadRZ, STAMTYPE_COUNTER, "RZ/MemRead", STAMUNIT_OCCURENCES, "Number of memory read translation requests in RZ.");
3973
3974	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteR3, STAMTYPE_COUNTER, "R3/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in R3.");
3975	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemWriteRZ, STAMTYPE_COUNTER, "RZ/MemWrite", STAMUNIT_OCCURENCES, "Number of memory write translation requests in RZ.");
3976
3977	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadR3, STAMTYPE_COUNTER, "R3/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in R3.");
3978	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkReadRZ, STAMTYPE_COUNTER, "RZ/MemBulkRead", STAMUNIT_OCCURENCES, "Number of memory bulk read translation requests in RZ.");
3979
3980	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteR3, STAMTYPE_COUNTER, "R3/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in R3.");
3981	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMemBulkWriteRZ, STAMTYPE_COUNTER, "RZ/MemBulkWrite", STAMUNIT_OCCURENCES, "Number of memory bulk write translation requests in RZ.");
3982
3983	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatCcInvDsc, STAMTYPE_COUNTER, "R3/QI/CcInv", STAMUNIT_OCCURENCES, "Number of cc_inv_dsc processed.");
3984	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/IotlbInv", STAMUNIT_OCCURENCES, "Number of iotlb_inv_dsc processed.");
3985	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/DevtlbInv", STAMUNIT_OCCURENCES, "Number of dev_tlb_inv_dsc processed.");
3986	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIecInvDsc, STAMTYPE_COUNTER, "R3/QI/IecInv", STAMUNIT_OCCURENCES, "Number of iec_inv processed.");
3987	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatInvWaitDsc, STAMTYPE_COUNTER, "R3/QI/InvWait", STAMUNIT_OCCURENCES, "Number of inv_wait_dsc processed.");
3988	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidIotlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidIotlbInv", STAMUNIT_OCCURENCES, "Number of p_iotlb_inv_dsc processed.");
3989	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidCacheInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidCacheInv", STAMUNIT_OCCURENCES, "Number of pc_inv_dsc pprocessed.");
3990	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatPasidDevtlbInvDsc, STAMTYPE_COUNTER, "R3/QI/PasidDevtlbInv", STAMUNIT_OCCURENCES, "Number of p_dev_tlb_inv_dsc processed.");
3991	#endif
3992
3993	/*
3994	* Initialize registers.
3995	*/
3996	dmarR3RegsInit(pDevIns);
3997
3998	/*
3999	* Create invalidation-queue thread and semaphore.
4000	*/
4001	char szInvQueueThread[32];
4002	RT_ZERO(szInvQueueThread);
4003	RTStrPrintf(szInvQueueThread, sizeof(szInvQueueThread), "IOMMU-QI-%u", iInstance);
4004	rc = PDMDevHlpThreadCreate(pDevIns, &pThisR3->pInvQueueThread, pThis, dmarR3InvQueueThread, dmarR3InvQueueThreadWakeUp,
4005	0 /* cbStack */, RTTHREADTYPE_IO, szInvQueueThread);
4006	AssertLogRelRCReturn(rc, rc);
4007
4008	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pThis->hEvtInvQueue);
4009	AssertLogRelRCReturn(rc, rc);
4010
4011	/*
4012	* Log some of the features exposed to software.
4013	*/
4014	uint8_t const uVerMax = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MAX);
4015	uint8_t const uVerMin = RT_BF_GET(pThis->uVerReg, VTD_BF_VER_REG_MIN);
4016	uint8_t const cMgawBits = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_MGAW) + 1;
4017	uint8_t const fSagaw = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_SAGAW);
4018	uint16_t const offFrcd = RT_BF_GET(pThis->fCapReg, VTD_BF_CAP_REG_FRO);
4019	uint16_t const offIva = RT_BF_GET(pThis->fExtCapReg, VTD_BF_ECAP_REG_IRO);
4020	LogRel(("%s: Mapped at %#RGp (%u-level page-table supported)\n",
4021	DMAR_LOG_PFX, DMAR_MMIO_BASE_PHYSADDR, pThis->cMaxPagingLevel));
4022	LogRel(("%s: Version=%u.%u Cap=%#RX64 ExtCap=%#RX64 Mgaw=%u bits Sagaw=%#x HawBaseMask=%#RX64 MgawInvMask=%#RX64 FRO=%#x IRO=%#x\n",
4023	DMAR_LOG_PFX, uVerMax, uVerMin, pThis->fCapReg, pThis->fExtCapReg, cMgawBits, fSagaw, pThis->fHawBaseMask,
4024	pThis->fMgawInvMask, offFrcd, offIva));
4025	return VINF_SUCCESS;
4026	}
4027
4028	#else
4029
4030	/**
4031	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
4032	*/
4033	static DECLCALLBACK(int) iommuIntelRZConstruct(PPDMDEVINS pDevIns)
4034	{
4035	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4036	PDMAR pThis = PDMDEVINS_2_DATA(pDevIns, PDMAR);
4037	PDMARCC pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PDMARCC);
4038	pThisCC->CTX_SUFF(pDevIns) = pDevIns;
4039
4040	/* We will use PDM's critical section (via helpers) for the IOMMU device. */
4041	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4042	AssertRCReturn(rc, rc);
4043
4044	/* Set up the MMIO RZ handlers. */
4045	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, dmarMmioWrite, dmarMmioRead, NULL /* pvUser */);
4046	AssertRCReturn(rc, rc);
4047
4048	/* Set up the IOMMU RZ callbacks. */
4049	PDMIOMMUREGCC IommuReg;
4050	RT_ZERO(IommuReg);
4051	IommuReg.u32Version = PDM_IOMMUREGCC_VERSION;
4052	IommuReg.idxIommu = pThis->idxIommu;
4053	IommuReg.pfnMemAccess = iommuIntelMemAccess;
4054	IommuReg.pfnMemBulkAccess = iommuIntelMemBulkAccess;
4055	IommuReg.pfnMsiRemap = iommuIntelMsiRemap;
4056	IommuReg.u32TheEnd = PDM_IOMMUREGCC_VERSION;
4057
4058	rc = PDMDevHlpIommuSetUpContext(pDevIns, &IommuReg, &pThisCC->CTX_SUFF(pIommuHlp));
4059	AssertRCReturn(rc, rc);
4060	AssertPtrReturn(pThisCC->CTX_SUFF(pIommuHlp), VERR_IOMMU_IPE_1);
4061	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32Version == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4062	AssertReturn(pThisCC->CTX_SUFF(pIommuHlp)->u32TheEnd == CTX_MID(PDM_IOMMUHLP,_VERSION), VERR_VERSION_MISMATCH);
4063	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLock);
4064	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnUnlock);
4065	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnLockIsOwner);
4066	AssertPtr(pThisCC->CTX_SUFF(pIommuHlp)->pfnSendMsi);
4067
4068	return VINF_SUCCESS;
4069	}
4070
4071	#endif
4072
4073
4074	/**
4075	* The device registration structure.
4076	*/
4077	PDMDEVREG const g_DeviceIommuIntel =
4078	{
4079	/* .u32Version = */ PDM_DEVREG_VERSION,
4080	/* .uReserved0 = */ 0,
4081	/* .szName = */ "iommu-intel",
4082	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE,
4083	/* .fClass = */ PDM_DEVREG_CLASS_PCI_BUILTIN,
4084	/* .cMaxInstances = */ 1,
4085	/* .uSharedVersion = */ 42,
4086	/* .cbInstanceShared = */ sizeof(DMAR),
4087	/* .cbInstanceCC = */ sizeof(DMARCC),
4088	/* .cbInstanceRC = */ sizeof(DMARRC),
4089	/* .cMaxPciDevices = */ 1,
4090	/* .cMaxMsixVectors = */ 0,
4091	/* .pszDescription = */ "IOMMU (Intel)",
4092	#if defined(IN_RING3)
4093	/* .pszRCMod = */ "VBoxDDRC.rc",
4094	/* .pszR0Mod = */ "VBoxDDR0.r0",
4095	/* .pfnConstruct = */ iommuIntelR3Construct,
4096	/* .pfnDestruct = */ iommuIntelR3Destruct,
4097	/* .pfnRelocate = */ NULL,
4098	/* .pfnMemSetup = */ NULL,
4099	/* .pfnPowerOn = */ NULL,
4100	/* .pfnReset = */ iommuIntelR3Reset,
4101	/* .pfnSuspend = */ NULL,
4102	/* .pfnResume = */ NULL,
4103	/* .pfnAttach = */ NULL,
4104	/* .pfnDetach = */ NULL,
4105	/* .pfnQueryInterface = */ NULL,
4106	/* .pfnInitComplete = */ NULL,
4107	/* .pfnPowerOff = */ NULL,
4108	/* .pfnSoftReset = */ NULL,
4109	/* .pfnReserved0 = */ NULL,
4110	/* .pfnReserved1 = */ NULL,
4111	/* .pfnReserved2 = */ NULL,
4112	/* .pfnReserved3 = */ NULL,
4113	/* .pfnReserved4 = */ NULL,
4114	/* .pfnReserved5 = */ NULL,
4115	/* .pfnReserved6 = */ NULL,
4116	/* .pfnReserved7 = */ NULL,
4117	#elif defined(IN_RING0)
4118	/* .pfnEarlyConstruct = */ NULL,
4119	/* .pfnConstruct = */ iommuIntelRZConstruct,
4120	/* .pfnDestruct = */ NULL,
4121	/* .pfnFinalDestruct = */ NULL,
4122	/* .pfnRequest = */ NULL,
4123	/* .pfnReserved0 = */ NULL,
4124	/* .pfnReserved1 = */ NULL,
4125	/* .pfnReserved2 = */ NULL,
4126	/* .pfnReserved3 = */ NULL,
4127	/* .pfnReserved4 = */ NULL,
4128	/* .pfnReserved5 = */ NULL,
4129	/* .pfnReserved6 = */ NULL,
4130	/* .pfnReserved7 = */ NULL,
4131	#elif defined(IN_RC)
4132	/* .pfnConstruct = */ iommuIntelRZConstruct,
4133	/* .pfnReserved0 = */ NULL,
4134	/* .pfnReserved1 = */ NULL,
4135	/* .pfnReserved2 = */ NULL,
4136	/* .pfnReserved3 = */ NULL,
4137	/* .pfnReserved4 = */ NULL,
4138	/* .pfnReserved5 = */ NULL,
4139	/* .pfnReserved6 = */ NULL,
4140	/* .pfnReserved7 = */ NULL,
4141	#else
4142	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
4143	#endif
4144	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
4145	};
4146
4147	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
4148

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source: vbox/trunk/src/VBox/Devices/Bus/DevIommuIntel.cpp@ 89553

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